From 09c49e24ee0336ab7f7845362e593f3b7a3dcd63 Mon Sep 17 00:00:00 2001 From: Raphael Coeffic Date: Sun, 9 Jan 2022 15:23:27 +0100 Subject: [PATCH] Remove SKY9X target --- radio/src/CMakeLists.txt | 4 +- radio/src/audio.cpp | 8 - radio/src/audio.h | 4 - radio/src/cli.cpp | 2 - radio/src/debounce.h | 2 - radio/src/gui/128x64/lcd.h | 4 - radio/src/gui/128x64/model_setup.cpp | 39 - radio/src/gui/128x64/model_telemetry.cpp | 12 - radio/src/gui/128x64/radio_diaganas.cpp | 2 - radio/src/gui/128x64/radio_diagkeys.cpp | 8 +- radio/src/gui/128x64/radio_setup.cpp | 6 +- radio/src/gui/128x64/view_main.cpp | 13 - radio/src/gui/128x64/view_statistics.cpp | 18 - .../src/gui/common/stdlcd/radio_hardware.cpp | 18 +- .../src/gui/common/stdlcd/radio_sdmanager.cpp | 3 - radio/src/gui/gui_common.cpp | 9 +- radio/src/keys.cpp | 3 - radio/src/main.cpp | 14 +- radio/src/myeeprom.h | 4 - radio/src/opentx.cpp | 50 - radio/src/opentx.h | 45 +- radio/src/pulses/dsm2.cpp | 19 - radio/src/pulses/modules_helpers.h | 11 - radio/src/pulses/ppm.cpp | 14 - radio/src/pulses/pulses.cpp | 12 - radio/src/pulses/pulses.h | 4 - radio/src/sdcard.h | 2 - radio/src/simu.cpp | 10 - .../conversions/conversions_216_218.cpp | 23 - .../conversions/conversions_218_219.cpp | 12 - .../src/storage/conversions/datastructs_218.h | 29 - .../storage/conversions/yaml/myeeprom_220.h | 4 - radio/src/storage/eeprom_raw.cpp | 16 - radio/src/storage/storage.h | 2 - radio/src/strhelpers.cpp | 11 - radio/src/targets/simu/CMakeLists.txt | 4 +- radio/src/targets/simu/opentxsimulator.cpp | 2 +- radio/src/targets/simu/simpgmspace.cpp | 29 - radio/src/targets/simu/simpgmspace.h | 45 - radio/src/targets/simu/simufatfs.cpp | 4 - radio/src/targets/sky9x/AT91SAM3S2.h | 7036 ---------------- radio/src/targets/sky9x/AT91SAM3S4.h | 7153 ----------------- radio/src/targets/sky9x/CMakeLists.txt | 151 - radio/src/targets/sky9x/MEDSdcard.c | 246 - radio/src/targets/sky9x/Media.h | 280 - radio/src/targets/sky9x/adc_driver.cpp | 137 - radio/src/targets/sky9x/audio_driver.cpp | 184 - radio/src/targets/sky9x/audio_driver.h | 42 - radio/src/targets/sky9x/aux_serial_driver.cpp | 124 - radio/src/targets/sky9x/bluetooth.cpp | 277 - radio/src/targets/sky9x/board.cpp | 494 -- radio/src/targets/sky9x/board.h | 425 - radio/src/targets/sky9x/board_lowlevel.c | 253 - radio/src/targets/sky9x/board_lowlevel.h | 634 -- radio/src/targets/sky9x/buzzer_driver.cpp | 48 - radio/src/targets/sky9x/chip.h | 122 - radio/src/targets/sky9x/coproc_driver.cpp | 203 - radio/src/targets/sky9x/core_cm3.c | 868 -- radio/src/targets/sky9x/core_cm3.h | 1816 ----- radio/src/targets/sky9x/crt.c | 131 - radio/src/targets/sky9x/diskio.cpp | 1381 ---- radio/src/targets/sky9x/eeprom_driver.cpp | 201 - radio/src/targets/sky9x/flash_driver.cpp | 94 - radio/src/targets/sky9x/haptic_driver.cpp | 45 - radio/src/targets/sky9x/i2c_driver.cpp | 82 - radio/src/targets/sky9x/i2c_driver.h | 34 - radio/src/targets/sky9x/joystick.cpp | 89 - radio/src/targets/sky9x/keys_driver.cpp | 168 - radio/src/targets/sky9x/lcd_driver.cpp | 222 - radio/src/targets/sky9x/massstorage.cpp | 209 - radio/src/targets/sky9x/pulses_driver.cpp | 313 - radio/src/targets/sky9x/pwr_driver.cpp | 48 - .../targets/sky9x/rotary_encoder_driver.cpp | 58 - radio/src/targets/sky9x/rtc_driver.cpp | 288 - radio/src/targets/sky9x/rtc_ds3231_driver.cpp | 71 - radio/src/targets/sky9x/sam3s4c_flash.ld | 162 - radio/src/targets/sky9x/sam3s8c_flash.ld | 162 - radio/src/targets/sky9x/sdcard_driver.cpp | 53 - radio/src/targets/sky9x/telemetry_driver.cpp | 187 - radio/src/targets/sky9x/trainer_driver.cpp | 96 - .../common/core/USBConfigurationDescriptor.c | 162 - .../common/core/USBConfigurationDescriptor.h | 150 - .../usb/common/core/USBDeviceDescriptor.h | 125 - .../core/USBDeviceQualifierDescriptor.h | 89 - .../usb/common/core/USBEndpointDescriptor.c | 109 - .../usb/common/core/USBEndpointDescriptor.h | 224 - .../sky9x/usb/common/core/USBFeatureRequest.c | 70 - .../sky9x/usb/common/core/USBFeatureRequest.h | 146 - .../usb/common/core/USBGenericDescriptor.c | 80 - .../usb/common/core/USBGenericDescriptor.h | 133 - .../sky9x/usb/common/core/USBGenericRequest.c | 138 - .../sky9x/usb/common/core/USBGenericRequest.h | 244 - .../usb/common/core/USBGetDescriptorRequest.c | 72 - .../usb/common/core/USBGetDescriptorRequest.h | 67 - .../core/USBInterfaceAssociationDescriptor.h | 86 - .../usb/common/core/USBInterfaceDescriptor.h | 87 - .../usb/common/core/USBInterfaceRequest.c | 69 - .../usb/common/core/USBInterfaceRequest.h | 68 - .../sky9x/usb/common/core/USBIrqHandler.c | 62 - .../sky9x/usb/common/core/USBIrqHandler.h | 52 - .../usb/common/core/USBSetAddressRequest.c | 56 - .../usb/common/core/USBSetAddressRequest.h | 60 - .../common/core/USBSetConfigurationRequest.c | 58 - .../common/core/USBSetConfigurationRequest.h | 61 - .../usb/common/core/USBStringDescriptor.h | 74 - .../targets/sky9x/usb/common/hid/HIDButton.h | 55 - .../sky9x/usb/common/hid/HIDDescriptor.h | 93 - .../usb/common/hid/HIDDeviceDescriptor.h | 68 - .../usb/common/hid/HIDGenericDescriptor.h | 63 - .../sky9x/usb/common/hid/HIDGenericDesktop.h | 109 - .../sky9x/usb/common/hid/HIDGenericRequest.h | 75 - .../sky9x/usb/common/hid/HIDIdleRequest.c | 56 - .../sky9x/usb/common/hid/HIDIdleRequest.h | 68 - .../usb/common/hid/HIDInterfaceDescriptor.h | 77 - .../targets/sky9x/usb/common/hid/HIDReport.h | 231 - .../sky9x/usb/common/hid/HIDReportRequest.c | 68 - .../sky9x/usb/common/hid/HIDReportRequest.h | 86 - .../common/massstorage/MSDeviceDescriptor.h | 73 - .../massstorage/MSInterfaceDescriptor.h | 75 - .../src/targets/sky9x/usb/device/core/USBD.h | 290 - .../sky9x/usb/device/core/USBDDriver.c | 754 -- .../sky9x/usb/device/core/USBDDriver.h | 101 - .../usb/device/core/USBDDriverDescriptors.h | 86 - .../targets/sky9x/usb/device/core/USBD_UDP.c | 1730 ---- .../device/hid-joystick/HIDDJoystickDriver.c | 356 - .../device/hid-joystick/HIDDJoystickDriver.h | 83 - .../HIDDJoystickDriverDescriptors.c | 297 - .../HIDDJoystickDriverDescriptors.h | 79 - .../hid-joystick/HIDDJoystickInputReport.c | 64 - .../hid-joystick/HIDDJoystickInputReport.h | 86 - .../sky9x/usb/device/massstorage/MSD.h | 233 - .../usb/device/massstorage/MSDDStateMachine.c | 610 -- .../usb/device/massstorage/MSDDStateMachine.h | 264 - .../sky9x/usb/device/massstorage/MSDDriver.c | 342 - .../sky9x/usb/device/massstorage/MSDDriver.h | 75 - .../device/massstorage/MSDDriverDescriptors.c | 469 -- .../device/massstorage/MSDDriverDescriptors.h | 83 - .../sky9x/usb/device/massstorage/MSDIOFifo.h | 135 - .../sky9x/usb/device/massstorage/MSDLun.c | 367 - .../sky9x/usb/device/massstorage/MSDLun.h | 161 - .../sky9x/usb/device/massstorage/SBC.h | 671 -- .../sky9x/usb/device/massstorage/SBCMethods.c | 1635 ---- .../sky9x/usb/device/massstorage/SBCMethods.h | 110 - radio/src/targets/sky9x/usb_driver.cpp | 45 - radio/src/targets/sky9x/vectors_sam3s.c | 173 - radio/src/telemetry/frsky.cpp | 4 - radio/src/telemetry/telemetry.cpp | 10 +- radio/src/telemetry/telemetry_sensors.cpp | 9 - radio/src/tests/mixer.cpp | 5 - radio/src/trainer.cpp | 20 - radio/src/translations.cpp | 6 - radio/src/translations.h | 6 - radio/src/translations/cn.h.txt | 4 +- radio/src/translations/cz.h.txt | 20 +- radio/src/translations/de.h.txt | 20 +- radio/src/translations/en.h.txt | 20 +- radio/src/translations/es.h.txt | 20 +- radio/src/translations/fi.h.txt | 20 +- radio/src/translations/fr.h.txt | 20 +- radio/src/translations/it.h.txt | 20 +- radio/src/translations/nl.h.txt | 20 +- radio/src/translations/pl.h.txt | 20 +- radio/src/translations/pt.h.txt | 20 +- radio/src/translations/se.h.txt | 20 +- radio/src/translations/tw.h.txt | 4 +- radio/src/translations/untranslated.h | 5 - 166 files changed, 24 insertions(+), 38415 deletions(-) delete mode 100644 radio/src/targets/sky9x/AT91SAM3S2.h delete mode 100644 radio/src/targets/sky9x/AT91SAM3S4.h delete mode 100644 radio/src/targets/sky9x/CMakeLists.txt delete mode 100644 radio/src/targets/sky9x/MEDSdcard.c delete mode 100644 radio/src/targets/sky9x/Media.h delete mode 100644 radio/src/targets/sky9x/adc_driver.cpp delete mode 100644 radio/src/targets/sky9x/audio_driver.cpp delete mode 100644 radio/src/targets/sky9x/audio_driver.h delete mode 100644 radio/src/targets/sky9x/aux_serial_driver.cpp delete mode 100644 radio/src/targets/sky9x/bluetooth.cpp delete mode 100644 radio/src/targets/sky9x/board.cpp delete mode 100644 radio/src/targets/sky9x/board.h delete mode 100644 radio/src/targets/sky9x/board_lowlevel.c delete mode 100644 radio/src/targets/sky9x/board_lowlevel.h delete mode 100644 radio/src/targets/sky9x/buzzer_driver.cpp delete mode 100644 radio/src/targets/sky9x/chip.h delete mode 100644 radio/src/targets/sky9x/coproc_driver.cpp delete mode 100644 radio/src/targets/sky9x/core_cm3.c delete mode 100644 radio/src/targets/sky9x/core_cm3.h delete mode 100644 radio/src/targets/sky9x/crt.c delete mode 100644 radio/src/targets/sky9x/diskio.cpp delete mode 100644 radio/src/targets/sky9x/eeprom_driver.cpp delete mode 100644 radio/src/targets/sky9x/flash_driver.cpp delete mode 100644 radio/src/targets/sky9x/haptic_driver.cpp delete mode 100644 radio/src/targets/sky9x/i2c_driver.cpp delete mode 100644 radio/src/targets/sky9x/i2c_driver.h delete mode 100644 radio/src/targets/sky9x/joystick.cpp delete mode 100644 radio/src/targets/sky9x/keys_driver.cpp delete mode 100644 radio/src/targets/sky9x/lcd_driver.cpp delete mode 100644 radio/src/targets/sky9x/massstorage.cpp delete mode 100644 radio/src/targets/sky9x/pulses_driver.cpp delete mode 100644 radio/src/targets/sky9x/pwr_driver.cpp delete mode 100644 radio/src/targets/sky9x/rotary_encoder_driver.cpp delete mode 100644 radio/src/targets/sky9x/rtc_driver.cpp delete mode 100644 radio/src/targets/sky9x/rtc_ds3231_driver.cpp delete mode 100644 radio/src/targets/sky9x/sam3s4c_flash.ld delete mode 100644 radio/src/targets/sky9x/sam3s8c_flash.ld delete mode 100644 radio/src/targets/sky9x/sdcard_driver.cpp delete mode 100644 radio/src/targets/sky9x/telemetry_driver.cpp delete mode 100644 radio/src/targets/sky9x/trainer_driver.cpp delete mode 100644 radio/src/targets/sky9x/usb/common/core/USBConfigurationDescriptor.c delete mode 100644 radio/src/targets/sky9x/usb/common/core/USBConfigurationDescriptor.h delete mode 100644 radio/src/targets/sky9x/usb/common/core/USBDeviceDescriptor.h delete mode 100644 radio/src/targets/sky9x/usb/common/core/USBDeviceQualifierDescriptor.h delete mode 100644 radio/src/targets/sky9x/usb/common/core/USBEndpointDescriptor.c delete mode 100644 radio/src/targets/sky9x/usb/common/core/USBEndpointDescriptor.h delete mode 100644 radio/src/targets/sky9x/usb/common/core/USBFeatureRequest.c delete mode 100644 radio/src/targets/sky9x/usb/common/core/USBFeatureRequest.h delete mode 100644 radio/src/targets/sky9x/usb/common/core/USBGenericDescriptor.c delete mode 100644 radio/src/targets/sky9x/usb/common/core/USBGenericDescriptor.h delete mode 100644 radio/src/targets/sky9x/usb/common/core/USBGenericRequest.c delete mode 100644 radio/src/targets/sky9x/usb/common/core/USBGenericRequest.h delete mode 100644 radio/src/targets/sky9x/usb/common/core/USBGetDescriptorRequest.c delete mode 100644 radio/src/targets/sky9x/usb/common/core/USBGetDescriptorRequest.h delete mode 100644 radio/src/targets/sky9x/usb/common/core/USBInterfaceAssociationDescriptor.h delete mode 100644 radio/src/targets/sky9x/usb/common/core/USBInterfaceDescriptor.h delete mode 100644 radio/src/targets/sky9x/usb/common/core/USBInterfaceRequest.c delete mode 100644 radio/src/targets/sky9x/usb/common/core/USBInterfaceRequest.h delete mode 100644 radio/src/targets/sky9x/usb/common/core/USBIrqHandler.c delete mode 100644 radio/src/targets/sky9x/usb/common/core/USBIrqHandler.h delete mode 100644 radio/src/targets/sky9x/usb/common/core/USBSetAddressRequest.c delete mode 100644 radio/src/targets/sky9x/usb/common/core/USBSetAddressRequest.h delete mode 100644 radio/src/targets/sky9x/usb/common/core/USBSetConfigurationRequest.c delete mode 100644 radio/src/targets/sky9x/usb/common/core/USBSetConfigurationRequest.h delete mode 100644 radio/src/targets/sky9x/usb/common/core/USBStringDescriptor.h delete mode 100644 radio/src/targets/sky9x/usb/common/hid/HIDButton.h delete mode 100644 radio/src/targets/sky9x/usb/common/hid/HIDDescriptor.h delete mode 100644 radio/src/targets/sky9x/usb/common/hid/HIDDeviceDescriptor.h delete mode 100644 radio/src/targets/sky9x/usb/common/hid/HIDGenericDescriptor.h delete mode 100644 radio/src/targets/sky9x/usb/common/hid/HIDGenericDesktop.h delete mode 100644 radio/src/targets/sky9x/usb/common/hid/HIDGenericRequest.h delete mode 100644 radio/src/targets/sky9x/usb/common/hid/HIDIdleRequest.c delete mode 100644 radio/src/targets/sky9x/usb/common/hid/HIDIdleRequest.h delete mode 100644 radio/src/targets/sky9x/usb/common/hid/HIDInterfaceDescriptor.h delete mode 100644 radio/src/targets/sky9x/usb/common/hid/HIDReport.h delete mode 100644 radio/src/targets/sky9x/usb/common/hid/HIDReportRequest.c delete mode 100644 radio/src/targets/sky9x/usb/common/hid/HIDReportRequest.h delete mode 100644 radio/src/targets/sky9x/usb/common/massstorage/MSDeviceDescriptor.h delete mode 100644 radio/src/targets/sky9x/usb/common/massstorage/MSInterfaceDescriptor.h delete mode 100644 radio/src/targets/sky9x/usb/device/core/USBD.h delete mode 100644 radio/src/targets/sky9x/usb/device/core/USBDDriver.c delete mode 100644 radio/src/targets/sky9x/usb/device/core/USBDDriver.h delete mode 100644 radio/src/targets/sky9x/usb/device/core/USBDDriverDescriptors.h delete mode 100644 radio/src/targets/sky9x/usb/device/core/USBD_UDP.c delete mode 100644 radio/src/targets/sky9x/usb/device/hid-joystick/HIDDJoystickDriver.c delete mode 100644 radio/src/targets/sky9x/usb/device/hid-joystick/HIDDJoystickDriver.h delete mode 100644 radio/src/targets/sky9x/usb/device/hid-joystick/HIDDJoystickDriverDescriptors.c delete mode 100644 radio/src/targets/sky9x/usb/device/hid-joystick/HIDDJoystickDriverDescriptors.h delete mode 100644 radio/src/targets/sky9x/usb/device/hid-joystick/HIDDJoystickInputReport.c delete mode 100644 radio/src/targets/sky9x/usb/device/hid-joystick/HIDDJoystickInputReport.h delete mode 100644 radio/src/targets/sky9x/usb/device/massstorage/MSD.h delete mode 100644 radio/src/targets/sky9x/usb/device/massstorage/MSDDStateMachine.c delete mode 100644 radio/src/targets/sky9x/usb/device/massstorage/MSDDStateMachine.h delete mode 100644 radio/src/targets/sky9x/usb/device/massstorage/MSDDriver.c delete mode 100644 radio/src/targets/sky9x/usb/device/massstorage/MSDDriver.h delete mode 100644 radio/src/targets/sky9x/usb/device/massstorage/MSDDriverDescriptors.c delete mode 100644 radio/src/targets/sky9x/usb/device/massstorage/MSDDriverDescriptors.h delete mode 100644 radio/src/targets/sky9x/usb/device/massstorage/MSDIOFifo.h delete mode 100644 radio/src/targets/sky9x/usb/device/massstorage/MSDLun.c delete mode 100644 radio/src/targets/sky9x/usb/device/massstorage/MSDLun.h delete mode 100644 radio/src/targets/sky9x/usb/device/massstorage/SBC.h delete mode 100644 radio/src/targets/sky9x/usb/device/massstorage/SBCMethods.c delete mode 100644 radio/src/targets/sky9x/usb/device/massstorage/SBCMethods.h delete mode 100644 radio/src/targets/sky9x/usb_driver.cpp delete mode 100644 radio/src/targets/sky9x/vectors_sam3s.c diff --git a/radio/src/CMakeLists.txt b/radio/src/CMakeLists.txt index 53166a85c..a60d997ae 100644 --- a/radio/src/CMakeLists.txt +++ b/radio/src/CMakeLists.txt @@ -1,7 +1,7 @@ include(CMakeForceCompiler) include(Bitmaps) -set(PCB_TYPES X9LITE X9LITES X7 XLITE XLITES X9D X9D+ X9E X10 X12S SKY9X 9XRPRO AR9X NV14) +set(PCB_TYPES X9LITE X9LITES X7 XLITE XLITES X9D X9D+ X9E X10 X12S NV14) set(RADIO_LANGUAGES CZ DE EN ES FR IT PT SK SE PL HU NL CN TW) set(TTS_LANGUAGES CZ DE EN ES FR IT PT SK SE PL HU NL RU CN) @@ -101,8 +101,6 @@ elseif(PCB STREQUAL NV14) include(targets/nv14/CMakeLists.txt) elseif(PCB STREQUAL X9E OR PCB STREQUAL X9D+ OR PCB STREQUAL X9D OR PCB STREQUAL X7 OR PCB STREQUAL X9LITE OR PCB STREQUAL X9LITES OR PCB STREQUAL XLITE OR PCB STREQUAL XLITES) include(targets/taranis/CMakeLists.txt) -elseif(PCB STREQUAL SKY9X OR PCB STREQUAL 9XRPRO OR PCB STREQUAL AR9X) - include(targets/sky9x/CMakeLists.txt) else() message(FATAL_ERROR "Unknown PCB '${PCB}'") endif() diff --git a/radio/src/audio.cpp b/radio/src/audio.cpp index a4f21b70b..b8ef99456 100644 --- a/radio/src/audio.cpp +++ b/radio/src/audio.cpp @@ -197,10 +197,6 @@ const char * const audioFilenames[] = { "servoko", "rxko", "modelpwr", -#if defined(PCBSKY9X) - "highmah", - "hightemp", -#endif "error", "warning1", "warning2", @@ -1101,10 +1097,6 @@ void audioEvent(unsigned int index) audioQueue.playTone(2250, 80, 20, PLAY_REPEAT(2)); break; case AU_TX_BATTERY_LOW: -#if defined(PCBSKY9X) - case AU_TX_MAH_HIGH: - case AU_TX_TEMP_HIGH: -#endif audioQueue.playTone(1950, 160, 20, PLAY_REPEAT(2), 1); audioQueue.playTone(2550, 160, 20, PLAY_REPEAT(2), -1); break; diff --git a/radio/src/audio.h b/radio/src/audio.h index 57bbcf86c..749e038be 100644 --- a/radio/src/audio.h +++ b/radio/src/audio.h @@ -572,10 +572,6 @@ void audioTimerCountdown(uint8_t timer, int value); #define AUDIO_WARNING1() AUDIO_BUZZER(audioEvent(AU_WARNING1), beep(3)) #define AUDIO_WARNING2() AUDIO_BUZZER(audioEvent(AU_WARNING2), beep(2)) #define AUDIO_TX_BATTERY_LOW() AUDIO_BUZZER(audioEvent(AU_TX_BATTERY_LOW), beep(4)) -#if defined(PCBSKY9X) -#define AUDIO_TX_MAH_HIGH() audioEvent(AU_TX_MAH_HIGH) -#define AUDIO_TX_TEMP_HIGH() audioEvent(AU_TX_TEMP_HIGH) -#endif #define AUDIO_ERROR() AUDIO_BUZZER(audioEvent(AU_ERROR), beep(4)) #define AUDIO_TIMER_COUNTDOWN(idx, val) audioTimerCountdown(idx, val) #define AUDIO_TIMER_ELAPSED(idx) AUDIO_BUZZER(audioEvent(AU_TIMER1_ELAPSED+idx), beep(3)) diff --git a/radio/src/cli.cpp b/radio/src/cli.cpp index fe984588b..84dc7a4f7 100644 --- a/radio/src/cli.cpp +++ b/radio/src/cli.cpp @@ -1171,13 +1171,11 @@ int cliDisplay(const char ** argv) serialPrint("volume = %d", getVolume()); } #endif -#if defined(STM32) else if (!strcmp(argv[1], "uid")) { char str[LEN_CPU_UID+1]; getCPUUniqueID(str); serialPrint("uid = %s", str); } -#endif else if (!strcmp(argv[1], "tim")) { int timerNumber; if (toInt(argv, 2, &timerNumber) > 0) { diff --git a/radio/src/debounce.h b/radio/src/debounce.h index 2853d972c..d25365669 100644 --- a/radio/src/debounce.h +++ b/radio/src/debounce.h @@ -42,7 +42,6 @@ class Debounce T debouncedState; }; -#if defined(STM32) class PinDebounce: public Debounce { public: @@ -51,6 +50,5 @@ class PinDebounce: public Debounce return Debounce::debounce(GPIO_ReadInputDataBit(GPIOx, GPIO_Pin)); } }; -#endif #endif // _DEBOUNCE_H_ diff --git a/radio/src/gui/128x64/lcd.h b/radio/src/gui/128x64/lcd.h index 53e6f47c6..e4e4088bc 100644 --- a/radio/src/gui/128x64/lcd.h +++ b/radio/src/gui/128x64/lcd.h @@ -97,10 +97,6 @@ extern coord_t lcdNextPos; #define DISPLAY_END (displayBuf + DISPLAY_BUFFER_SIZE) #define ASSERT_IN_DISPLAY(p) assert((p) >= displayBuf && (p) < DISPLAY_END) -#if defined(PCBSKY9X) - extern volatile uint8_t lcdLock ; - extern volatile uint32_t lcdInputs ; -#endif void lcdDrawChar(coord_t x, coord_t y, uint8_t c); void lcdDrawChar(coord_t x, coord_t y, uint8_t c, LcdFlags flags); diff --git a/radio/src/gui/128x64/model_setup.cpp b/radio/src/gui/128x64/model_setup.cpp index 35cb56284..899b91edc 100644 --- a/radio/src/gui/128x64/model_setup.cpp +++ b/radio/src/gui/128x64/model_setup.cpp @@ -168,14 +168,6 @@ enum MenuModelSetupItems { ITEM_MODEL_SETUP_EXTERNAL_MODULE_PXX2_RECEIVER_2, ITEM_MODEL_SETUP_EXTERNAL_MODULE_PXX2_RECEIVER_3, -#if defined(PCBSKY9X) && defined(REVX) - ITEM_MODEL_SETUP_EXTERNAL_MODULE_OUTPUT_TYPE, -#endif -#if defined(PCBSKY9X) - ITEM_MODEL_SETUP_EXTRA_MODULE_LABEL, - ITEM_MODEL_SETUP_EXTRA_MODULE_CHANNELS, - ITEM_MODEL_SETUP_EXTRA_MODULE_BIND, -#endif #endif #if defined(PCBTARANIS) @@ -207,8 +199,6 @@ enum MenuModelSetupItems { #if defined(HARDWARE_INTERNAL_MODULE) && defined(HARDWARE_EXTERNAL_MODULE) #define CURRENT_MODULE_EDITED(k) (k >= ITEM_MODEL_SETUP_EXTERNAL_MODULE_LABEL ? EXTERNAL_MODULE : INTERNAL_MODULE) #define CURRENT_RECEIVER_EDITED(k) (k - (k >= ITEM_MODEL_SETUP_EXTERNAL_MODULE_LABEL ? ITEM_MODEL_SETUP_EXTERNAL_MODULE_PXX2_RECEIVER_1 : ITEM_MODEL_SETUP_INTERNAL_MODULE_PXX2_RECEIVER_1)) -#elif defined(PCBSKY9X) - #define CURRENT_MODULE_EDITED(k) (k >= ITEM_MODEL_SETUP_EXTRA_MODULE_LABEL ? EXTRA_MODULE : EXTERNAL_MODULE) #elif defined(HARDWARE_INTERNAL_MODULE) #define CURRENT_MODULE_EDITED(k) (INTERNAL_MODULE) #define CURRENT_RECEIVER_EDITED(k) (k - ITEM_MODEL_SETUP_INTERNAL_MODULE_PXX2_RECEIVER_1) @@ -249,11 +239,7 @@ inline uint8_t MODULE_SUBTYPE_ROWS(int moduleIdx) g_model.timers[x].countdownBeep != COUNTDOWN_SILENT ? (uint8_t)1 \ : (uint8_t)0 -#if defined(PCBSKY9X) - #define EXTRA_MODULE_ROWS LABEL(ExtraModule), 1, 2, -#else #define EXTRA_MODULE_ROWS -#endif #if defined(FUNCTION_SWITCHES) #define FUNCTION_SWITCHES_ROWS READONLY_ROW, NAVIGATION_LINE_BY_LINE|3, NAVIGATION_LINE_BY_LINE|3, NAVIGATION_LINE_BY_LINE|3, NAVIGATION_LINE_BY_LINE|3, NAVIGATION_LINE_BY_LINE|3, NAVIGATION_LINE_BY_LINE|3, NAVIGATION_LINE_BY_LINE|(NUM_FUNCTIONS_SWITCHES-1), @@ -925,11 +911,6 @@ void menuModelSetup(event_t event) break; #endif -#if defined(PCBSKY9X) - case ITEM_MODEL_SETUP_EXTRA_MODULE_LABEL: - lcdDrawTextAlignedLeft(y, "RF Port 2 (PPM)"); - break; -#endif #if defined(HARDWARE_EXTERNAL_MODULE) case ITEM_MODEL_SETUP_EXTERNAL_MODULE_LABEL: @@ -1226,9 +1207,6 @@ void menuModelSetup(event_t event) #if defined(HARDWARE_INTERNAL_MODULE) case ITEM_MODEL_SETUP_INTERNAL_MODULE_CHANNELS: #endif -#if defined(PCBSKY9X) - case ITEM_MODEL_SETUP_EXTRA_MODULE_CHANNELS: -#endif #if defined(HARDWARE_EXTERNAL_MODULE) case ITEM_MODEL_SETUP_EXTERNAL_MODULE_CHANNELS: #endif @@ -1369,9 +1347,6 @@ void menuModelSetup(event_t event) break; #endif -#if defined(PCBSKY9X) - case ITEM_MODEL_SETUP_EXTRA_MODULE_BIND: -#endif #if defined(HARDWARE_INTERNAL_MODULE) case ITEM_MODEL_SETUP_INTERNAL_MODULE_NOT_ACCESS_RXNUM_BIND_RANGE: #endif @@ -1525,14 +1500,6 @@ void menuModelSetup(event_t event) break; } -#if defined(PCBSKY9X) && defined(REVX) - case ITEM_MODEL_SETUP_EXTERNAL_MODULE_OUTPUT_TYPE: - { - ModuleData & moduleData = g_model.moduleData[moduleIdx]; - moduleData.ppm.outputType = editChoice(MODEL_SETUP_2ND_COLUMN, y, STR_OUTPUT_TYPE, STR_VOUTPUT_TYPE, moduleData.ppm.outputType, 0, 1, attr, event); - break; - } -#endif #if defined(HARDWARE_INTERNAL_MODULE) case ITEM_MODEL_SETUP_INTERNAL_MODULE_FAILSAFE: @@ -1933,12 +1900,6 @@ void menuModelSetup(event_t event) checkModelIdUnique(g_eeGeneral.currModel, INTERNAL_MODULE); break; #endif -#if defined(PCBSKY9X) - case ITEM_MODEL_SETUP_EXTRA_MODULE_BIND: - if (menuHorizontalPosition == 0) - checkModelIdUnique(g_eeGeneral.currModel, EXTRA_MODULE); - break; -#endif #if defined(HARDWARE_EXTERNAL_MODULE) case ITEM_MODEL_SETUP_EXTERNAL_MODULE_NOT_ACCESS_RXNUM_BIND_RANGE: case ITEM_MODEL_SETUP_EXTERNAL_MODULE_PXX2_MODEL_NUM: diff --git a/radio/src/gui/128x64/model_telemetry.cpp b/radio/src/gui/128x64/model_telemetry.cpp index 1c0c78042..e9a12da4e 100644 --- a/radio/src/gui/128x64/model_telemetry.cpp +++ b/radio/src/gui/128x64/model_telemetry.cpp @@ -23,9 +23,6 @@ enum MenuModelTelemetryFrskyItems { ITEM_TELEMETRY_PROTOCOL_TYPE, -#if defined(REVX) - ITEM_TELEMETRY_INVERTED_SERIAL, -#endif ITEM_TELEMETRY_RSSI_LABEL, ITEM_TELEMETRY_RSSI_SOURCE, ITEM_TELEMETRY_RSSI_ALARM1, @@ -70,11 +67,7 @@ enum MenuModelTelemetryFrskyItems { #define TELEMETRY_TYPE_ROW (g_model.moduleData[EXTERNAL_MODULE].type == MODULE_TYPE_PPM) ? (uint8_t)0 : HIDDEN_ROW #endif -#if defined(REVX) - #define TELEMETRY_TYPE_ROWS TELEMETRY_TYPE_ROW, TELEMETRY_TYPE_ROW, -#else #define TELEMETRY_TYPE_ROWS TELEMETRY_TYPE_ROW, -#endif void onSensorMenu(const char * result) { @@ -187,11 +180,6 @@ void menuModelTelemetry(event_t event) } break; -#if defined(REVX) - case ITEM_TELEMETRY_INVERTED_SERIAL: - g_model.moduleData[EXTERNAL_MODULE].invertedSerial = editCheckBox(g_model.moduleData[EXTERNAL_MODULE].invertedSerial, TELEM_COL2, y, STR_INVERTED_SERIAL, attr, event); - break; -#endif case ITEM_TELEMETRY_SENSORS_LABEL: lcdDrawTextAlignedLeft(y, STR_TELEMETRY_SENSORS); diff --git a/radio/src/gui/128x64/radio_diaganas.cpp b/radio/src/gui/128x64/radio_diaganas.cpp index b6d86fc29..004e6d33b 100644 --- a/radio/src/gui/128x64/radio_diaganas.cpp +++ b/radio/src/gui/128x64/radio_diaganas.cpp @@ -41,8 +41,6 @@ void menuRadioDiagAnalogs(event_t event) // TODO enum #if defined(TX_CAPACITY_MEASUREMENT) #define ANAS_ITEMS_COUNT 3 -#elif defined(PCBSKY9X) - #define ANAS_ITEMS_COUNT 2 #else #define ANAS_ITEMS_COUNT 1 #endif diff --git a/radio/src/gui/128x64/radio_diagkeys.cpp b/radio/src/gui/128x64/radio_diagkeys.cpp index f76f64962..ff1b9a46e 100644 --- a/radio/src/gui/128x64/radio_diagkeys.cpp +++ b/radio/src/gui/128x64/radio_diagkeys.cpp @@ -63,13 +63,7 @@ void menuRadioDiagKeys(event_t event) } } -#if defined(PCBSKY9X) - if (i != SW_ID0) { - y = MENU_HEADER_HEIGHT +i*FH - 2*FH; - drawSwitch(8*FW, y, i+1, 0); - displaySwitchState(11*FW+2, y, i); - } -#elif (NUM_SWITCHES > 6) +#if (NUM_SWITCHES > 6) if (i < NUM_SWITCHES) { if (SWITCH_EXISTS(i)) { y = (i > 4) ? FH*(i-4)+1 : MENU_HEADER_HEIGHT + FH*i + 1; diff --git a/radio/src/gui/128x64/radio_setup.cpp b/radio/src/gui/128x64/radio_setup.cpp index 6b96e63ac..dd860a7c6 100644 --- a/radio/src/gui/128x64/radio_setup.cpp +++ b/radio/src/gui/128x64/radio_setup.cpp @@ -99,7 +99,7 @@ enum { ITEM_RADIO_SETUP_IMPERIAL, IF_FAI_CHOICE(ITEM_RADIO_SETUP_FAI) ITEM_RADIO_SETUP_SWITCHES_DELAY, - CASE_STM32(ITEM_RADIO_SETUP_USB_MODE) + ITEM_RADIO_SETUP_USB_MODE, CASE_JACK_DETECT(ITEM_RADIO_SETUP_JACK_MODE) ITEM_RADIO_SETUP_RX_CHANNEL_ORD, ITEM_RADIO_SETUP_STICK_MODE_LABELS, @@ -173,7 +173,7 @@ void menuRadioSetup(event_t event) CASE_PXX1(0) 0, 0, IF_FAI_CHOICE(0) 0, - CASE_STM32(0) // USB mode + 0, // USB mode CASE_JACK_DETECT(0) // Jack mode 0, COL_TX_MODE, 0, 1/*to force edit mode*/}); @@ -621,11 +621,9 @@ void menuRadioSetup(event_t event) if (attr) CHECK_INCDEC_GENVAR(event, g_eeGeneral.switchesDelay, -15, 100-15); break; -#if defined(STM32) case ITEM_RADIO_SETUP_USB_MODE: g_eeGeneral.USBMode = editChoice(RADIO_SETUP_2ND_COLUMN, y, STR_USBMODE, STR_USBMODES, g_eeGeneral.USBMode, USB_UNSELECTED_MODE, USB_MAX_MODE, attr, event); break; -#endif #if defined(JACK_DETECT_GPIO) case ITEM_RADIO_SETUP_JACK_MODE: diff --git a/radio/src/gui/128x64/view_main.cpp b/radio/src/gui/128x64/view_main.cpp index 35039c4a7..37ccb0576 100644 --- a/radio/src/gui/128x64/view_main.cpp +++ b/radio/src/gui/128x64/view_main.cpp @@ -277,20 +277,7 @@ void displayBattVoltage() #endif } -#if defined(PCBSKY9X) -void displayVoltageOrAlarm() -{ - if (g_eeGeneral.mAhWarn && (g_eeGeneral.mAhUsed + Current_used * (488 + g_eeGeneral.txCurrentCalibration)/8192/36) / 500 >= g_eeGeneral.mAhWarn) { - drawValueWithUnit(7*FW-1, 2*FH, (g_eeGeneral.mAhUsed + Current_used*(488 + g_eeGeneral.txCurrentCalibration)/8192/36)/10, UNIT_MAH, - BLINK|INVERS|DBLSIZE|RIGHT); - } - else { - displayBattVoltage(); - } -} -#else #define displayVoltageOrAlarm() displayBattVoltage() -#endif #if defined(RADIO_T8) #define EVT_KEY_CONTEXT_MENU EVT_KEY_LONG(KEY_ENTER) diff --git a/radio/src/gui/128x64/view_statistics.cpp b/radio/src/gui/128x64/view_statistics.cpp index 4384166b8..c2f8770fb 100644 --- a/radio/src/gui/128x64/view_statistics.cpp +++ b/radio/src/gui/128x64/view_statistics.cpp @@ -58,9 +58,7 @@ void menuStatisticsView(event_t event) #if !defined(PCBTARANIS) case EVT_KEY_LONG(KEY_MENU): // historical #endif -#if !defined(PCBSKY9X) case EVT_KEY_LONG(KEY_ENTER): -#endif g_eeGeneral.globalTimer = 0; storageDirty(EE_GENERAL); sessionTimer = 0; @@ -122,10 +120,6 @@ void menuStatisticsDebug(event_t event) break; case EVT_KEY_LONG(KEY_ENTER): -#if defined(PCBSKY9X) - g_eeGeneral.mAhUsed = 0; - Current_used = 0; -#endif g_eeGeneral.globalTimer = 0; sessionTimer = 0; storageDirty(EE_GENERAL); @@ -170,14 +164,6 @@ void menuStatisticsDebug(event_t event) break; } -#if defined(PCBSKY9X) - if (IS_RESET_REASON_WATCHDOG()) { - lcdDrawText(LCD_W-8*FW, 0, "WATCHDOG"); - } - else if (globalData.unexpectedShutdown) { - lcdDrawText(LCD_W-13*FW, 0, "UNEXP.SHTDOWN"); - } -#endif uint8_t y = FH + 1; @@ -214,12 +200,10 @@ void menuStatisticsDebug(event_t event) y += FH; #endif -#if defined(STM32) lcdDrawTextAlignedLeft(y, "Free Mem"); lcdDrawNumber(MENU_DEBUG_COL1_OFS, y, availableMemory(), LEFT); lcdDrawText(lcdLastRightPos, y, "b"); y += FH; -#endif #if defined(LUA) lcdDrawTextAlignedLeft(y, "Lua scripts"); @@ -256,7 +240,6 @@ void menuStatisticsDebug(event_t event) lcdInvertLastLine(); } -#if defined(STM32) void menuStatisticsDebug2(event_t event) { title(STR_MENUDEBUG); @@ -305,4 +288,3 @@ void menuStatisticsDebug2(event_t event) lcdDrawText(LCD_W/2, 7*FH+1, STR_MENUTORESET, CENTERED); lcdInvertLastLine(); } -#endif diff --git a/radio/src/gui/common/stdlcd/radio_hardware.cpp b/radio/src/gui/common/stdlcd/radio_hardware.cpp index 513415c68..08ae0e16c 100644 --- a/radio/src/gui/common/stdlcd/radio_hardware.cpp +++ b/radio/src/gui/common/stdlcd/radio_hardware.cpp @@ -88,10 +88,8 @@ enum { ITEM_RADIO_HARDWARE_BATTERY_CALIB, -#if defined(STM32) ITEM_RADIO_HARDWARE_RTC_BATTERY, ITEM_RADIO_HARDWARE_RTC_CHECK, -#endif #if defined(TX_CAPACITY_MEASUREMENT) ITEM_RADIO_HARDWARE_CAPACITY_CALIB, @@ -217,11 +215,7 @@ enum { #define SWITCH_TYPE_MAX(sw) ((MIXSRC_SF - MIXSRC_FIRST_SWITCH == sw || MIXSRC_SH - MIXSRC_FIRST_SWITCH <= sw) ? SWITCH_2POS : SWITCH_3POS) #endif -#if defined(STM32) #define RTC_ROW READONLY_ROW, 0, -#else - #define RTC_ROW -#endif #if defined(TX_CAPACITY_MEASUREMENT) #define TX_CAPACITY_MEASUREMENT_ROWS 0, @@ -488,14 +482,6 @@ void menuRadioHardware(event_t event) #if defined(PCBTARANIS) lcdDrawTextAlignedLeft(y, STR_BATT_CALIB); putsVolts(HW_SETTINGS_COLUMN2, y, getBatteryVoltage(), attr|PREC2|LEFT); -#elif defined(PCBSKY9X) - lcdDrawTextAlignedLeft(MENU_HEADER_HEIGHT+1+4*FH, STR_BATT_CALIB); - static int32_t adcBatt; - // TODO board.cpp - adcBatt = ((adcBatt * 7) + anaIn(TX_VOLTAGE)) / 8; - uint32_t batCalV = (adcBatt + adcBatt*(g_eeGeneral.txVoltageCalibration)/128) * 4191; - batCalV /= 55296; - putsVolts(HW_SETTINGS_COLUMN2, y, batCalV, (menuVerticalPosition==HEADER_LINE ? INVERS : 0)); #else lcdDrawTextAlignedLeft(MENU_HEADER_HEIGHT + 1 + (NUM_STICKS+NUM_POTS+NUM_SLIDERS+1)/2 * FH, STR_BATT_CALIB); putsVolts(HW_SETTINGS_COLUMN2, y, g_vbat100mV, attr|LEFT); @@ -505,7 +491,6 @@ void menuRadioHardware(event_t event) } break; -#if defined(STM32) case ITEM_RADIO_HARDWARE_RTC_BATTERY: lcdDrawTextAlignedLeft(y, STR_RTC_BATT); putsVolts(HW_SETTINGS_COLUMN2, y, getRTCBatteryVoltage(), PREC2|LEFT); @@ -514,7 +499,6 @@ void menuRadioHardware(event_t event) case ITEM_RADIO_HARDWARE_RTC_CHECK: g_eeGeneral.disableRtcWarning = 1 - editCheckBox(1 - g_eeGeneral.disableRtcWarning, HW_SETTINGS_COLUMN2, y, STR_RTC_CHECK, attr, event); break; -#endif #if defined(TX_CAPACITY_MEASUREMENT) case ITEM_RADIO_HARDWARE_CAPACITY_CALIB: @@ -686,4 +670,4 @@ void menuRadioHardware(event_t event) } } } -#endif // PCBSKY9X +#endif diff --git a/radio/src/gui/common/stdlcd/radio_sdmanager.cpp b/radio/src/gui/common/stdlcd/radio_sdmanager.cpp index 6dde5381c..6b1a4e168 100644 --- a/radio/src/gui/common/stdlcd/radio_sdmanager.cpp +++ b/radio/src/gui/common/stdlcd/radio_sdmanager.cpp @@ -83,9 +83,6 @@ void onSdFormatConfirm(const char * result) if (result == STR_OK) { showMessageBox(STR_FORMATTING); logsClose(); -#if defined(PCBSKY9X) - Card_state = SD_ST_DATA; -#endif audioQueue.stopSD(); if (sdCardFormat()) { f_chdir(ROOT_PATH); diff --git a/radio/src/gui/gui_common.cpp b/radio/src/gui/gui_common.cpp index 672dc5625..aa311214a 100644 --- a/radio/src/gui/gui_common.cpp +++ b/radio/src/gui/gui_common.cpp @@ -309,12 +309,6 @@ bool isSwitchAvailable(int swtch, SwitchContext context) swtch = -swtch; } -#if defined(PCBSKY9X) - if (swtch >= SWSRC_FIRST_SWITCH && swtch <= SWSRC_LAST_SWITCH) { - UNUSED(negative); - return true; - } -#else if (swtch >= SWSRC_FIRST_SWITCH && swtch <= SWSRC_LAST_SWITCH) { div_t swinfo = switchInfo(swtch); if (!SWITCH_EXISTS(swinfo.quot)) { @@ -328,7 +322,6 @@ bool isSwitchAvailable(int swtch, SwitchContext context) } return true; } -#endif #if NUM_XPOTS > 0 if (swtch >= SWSRC_FIRST_MULTIPOS_SWITCH && swtch <= SWSRC_LAST_MULTIPOS_SWITCH) { @@ -824,7 +817,7 @@ bool isTrainerModeAvailable(int mode) #if defined(BLUETOOTH) && !defined(PCBX9E) if (g_eeGeneral.bluetoothMode != BLUETOOTH_TRAINER && (mode == TRAINER_MODE_MASTER_BLUETOOTH || mode == TRAINER_MODE_SLAVE_BLUETOOTH)) return false; -#elif !defined(PCBSKY9X) +#else if (mode == TRAINER_MODE_MASTER_BLUETOOTH || mode == TRAINER_MODE_SLAVE_BLUETOOTH) return false; #endif diff --git a/radio/src/keys.cpp b/radio/src/keys.cpp index 4eae17951..b5b3bf9ca 100644 --- a/radio/src/keys.cpp +++ b/radio/src/keys.cpp @@ -177,9 +177,6 @@ void killAllEvents() bool waitKeysReleased() { -#if defined(PCBSKY9X) - RTOS_WAIT_MS(200); // 200ms -#endif // loop until all keys are up #if !defined(BOOT) diff --git a/radio/src/main.cpp b/radio/src/main.cpp index ba1ee62a9..fda115218 100644 --- a/radio/src/main.cpp +++ b/radio/src/main.cpp @@ -80,7 +80,7 @@ void openUsbMenu() #endif } -#elif defined(STM32) +#else void onUSBConnectMenu(const char *result) { @@ -286,11 +286,6 @@ void checkBatteryAlarms() AUDIO_TX_BATTERY_LOW(); // TRACE("checkBatteryAlarms(): battery low"); } -#if defined(PCBSKY9X) - else if (g_eeGeneral.mAhWarn && (g_eeGeneral.mAhUsed + Current_used * (488 + g_eeGeneral.txCurrentCalibration)/8192/36) / 500 >= g_eeGeneral.mAhWarn) { // TODO move calculation into board file - AUDIO_TX_MAH_HIGH(); - } -#endif } void checkBattery() @@ -480,9 +475,6 @@ void perMain() { DEBUG_TIMER_START(debugTimerPerMain1); -#if defined(PCBSKY9X) - calcConsumption(); -#endif checkSpeakerVolume(); @@ -520,12 +512,10 @@ void perMain() } #endif -#if defined(STM32) if ((!usbPlugged() || (getSelectedUsbMode() == USB_UNSELECTED_MODE)) && SD_CARD_PRESENT() && !sdMounted()) { sdMount(); } -#endif #if !defined(EEPROM) // In case the SD card is removed during the session @@ -540,7 +530,6 @@ void perMain() } #endif -#if defined(STM32) if (usbPlugged() && getSelectedUsbMode() == USB_MASS_STORAGE_MODE) { #if defined(LIBOPENUI) // draw some image showing USB @@ -555,7 +544,6 @@ void perMain() #endif return; } -#endif #if defined(MULTIMODULE) checkFailsafeMulti(); diff --git a/radio/src/myeeprom.h b/radio/src/myeeprom.h index 402021ca8..6e89bbd1b 100644 --- a/radio/src/myeeprom.h +++ b/radio/src/myeeprom.h @@ -260,11 +260,7 @@ enum SwashType { #define IS_MANUAL_RESET_TIMER(idx) (g_model.timers[idx].persistent == 2) -#if !defined(PCBSKY9X) #define TIMER_COUNTDOWN_START(x) (g_model.timers[x].countdownStart == 0 ? 20 : (g_model.timers[x].countdownStart == 1 ? 30 : (g_model.timers[x].countdownStart == -1 ? 10 : 5))) -#else -#define TIMER_COUNTDOWN_START(x) 10 -#endif #include "pulses/modules_constants.h" diff --git a/radio/src/opentx.cpp b/radio/src/opentx.cpp index 72c1bbb2c..52a1c0f9f 100644 --- a/radio/src/opentx.cpp +++ b/radio/src/opentx.cpp @@ -31,9 +31,6 @@ #include "view_text.h" #endif -#if defined(PCBSKY9X) -#include "audio_driver.h" -#endif extern uint16_t get_flysky_hall_adc_value(uint8_t ch); @@ -56,9 +53,7 @@ safetych_t safetyCh[MAX_OUTPUT_CHANNELS]; // __DMA for the MSC_BOT_Data member union ReusableBuffer reusableBuffer __DMA; -#if defined(STM32) uint8_t* MSC_BOT_Data = reusableBuffer.MSC_BOT_Data; -#endif #if defined(DEBUG_LATENCY) uint8_t latencyToggleSwitch = 0; @@ -602,11 +597,6 @@ void doSplash() resetBacklightTimeout(); drawSplash(); -#if defined(PCBSKY9X) - tmr10ms_t curTime = get_tmr10ms() + 10; - uint8_t contrast = 10; - lcdSetRefVolt(contrast); -#endif getADC(); // init ADC array @@ -640,15 +630,6 @@ void doSplash() } #endif -#if defined(PCBSKY9X) - if (curTime < get_tmr10ms()) { - curTime += 10; - if (contrast < g_eeGeneral.contrast) { - contrast += 1; - lcdSetRefVolt(contrast); - } - } -#endif checkBacklight(); } @@ -675,7 +656,6 @@ void checkMultiLowPower() } #endif -#if defined(STM32) static void checkRTCBattery() { GET_ADC_IF_MIXER_NOT_RUNNING(); @@ -683,7 +663,6 @@ static void checkRTCBattery() ALERT(STR_BATTERY, STR_WARN_RTC_BATTERY_LOW, AU_ERROR); } } -#endif #if defined(PCBFRSKY) || defined(PCBFLYSKY) static void checkFailsafe() @@ -718,13 +697,11 @@ void checkAll() checkFailsafe(); -#if defined(STM32) if (isVBatBridgeEnabled() && !g_eeGeneral.disableRtcWarning) { // only done once at board start checkRTCBattery(); } disableVBatBridge(); -#endif if (g_model.displayChecklist && modelHasNotes()) { readModelNotes(); @@ -1290,11 +1267,6 @@ void doMixerCalculations() getSwitchesPosition(!s_mixer_first_run_done); DEBUG_TIMER_STOP(debugTimerGetSwitches); -#if defined(PCBSKY9X) && !defined(SIMU) - Current_analogue = (Current_analogue*31 + s_anaFilt[8] ) >> 5 ; - if (Current_analogue > Current_max) - Current_max = Current_analogue ; -#endif DEBUG_TIMER_START(debugTimerEvalMixes); @@ -1452,11 +1424,6 @@ void opentxStart(const uint8_t startOptions = OPENTX_START_DEFAULT_ARGS) trace_event(trace_start, 0x12345678); #endif -#if defined(PCBSKY9X) && defined(SDCARD) && !defined(SIMU) - for (int i=0; i<500 && !Card_initialized; i++) { - RTOS_WAIT_MS(2); // 2ms - } -#endif #if defined(TEST_BUILD_WARNING) ALERT(STR_TEST_WARNING, TR_TEST_NOTSAFE, AU_ERROR); @@ -1513,12 +1480,6 @@ void opentxClose(uint8_t shutdown) sessionTimer = 0; } -#if defined(PCBSKY9X) - uint32_t mAhUsed = g_eeGeneral.mAhUsed + Current_used * (488 + g_eeGeneral.txCurrentCalibration) / 8192 / 36; - if (g_eeGeneral.mAhUsed != mAhUsed) { - g_eeGeneral.mAhUsed = mAhUsed; - } -#endif g_eeGeneral.unexpectedShutdown = 0; storageDirty(EE_GENERAL); @@ -1550,7 +1511,6 @@ void opentxClose(uint8_t shutdown) #endif } -#if defined(STM32) void opentxResume() { TRACE("opentxResume"); @@ -1583,7 +1543,6 @@ void opentxResume() storageDirty(EE_GENERAL); } } -#endif #define INSTANT_TRIM_MARGIN 10 /* around 1% */ @@ -1918,14 +1877,7 @@ void opentxInit() audioQueue.start(); BACKLIGHT_ENABLE(); -#if defined(PCBSKY9X) - // Set ADC gains here - setSticksGain(g_eeGeneral.sticksGain); -#endif -#if defined(PCBSKY9X) && defined(BLUETOOTH) - btInit(); -#endif #if defined(SPORT_UPDATE_PWR_GPIO) SPORT_UPDATE_POWER_INIT(); @@ -1984,7 +1936,6 @@ int main() initialise_monitor_handles(); #endif -#if defined(STM32) #if !defined(SIMU) /* Ensure all priority bits are assigned as preemption priority bits. */ @@ -1999,7 +1950,6 @@ int main() sizeof(reusableBuffer.hardwareAndSettings), sizeof(reusableBuffer.spectrumAnalyser), sizeof(reusableBuffer.MSC_BOT_Data)); -#endif // G: The WDT remains active after a WDT reset -- at maximum clock speed. So it's // important to disable it before commencing with system initialisation (or diff --git a/radio/src/opentx.h b/radio/src/opentx.h index 47d0de997..5a4a93b5a 100644 --- a/radio/src/opentx.h +++ b/radio/src/opentx.h @@ -34,9 +34,7 @@ #include "board.h" -#if defined(STM32) #include "usbd_conf.h" -#endif #if defined(LIBOPENUI) #include "libopenui.h" @@ -50,20 +48,6 @@ #define SWITCH_SIMU(a, b) (b) #endif -#if defined(PCBSKY9X) - #define IS_PCBSKY9X true - #define CASE_PCBSKY9X(x) x, -#else - #define IS_PCBSKY9X false - #define CASE_PCBSKY9X(x) -#endif - -#if defined(STM32) - #define CASE_STM32(x) x, -#else - #define CASE_STM32(x) -#endif - #if defined(VARIO) #define CASE_VARIO(x) x, #else @@ -196,12 +180,7 @@ #define CASE_PCBX9E(x) #endif -#if defined(PCBSKY9X) && !defined(PCBAR9X) - #define TX_CAPACITY_MEASUREMENT - #define CASE_CAPACITY(x) x, -#else #define CASE_CAPACITY(x) -#endif #if defined(FAI) #define IS_FAI_ENABLED() true @@ -579,11 +558,7 @@ int getTrimValue(uint8_t phase, uint8_t idx); bool setTrimValue(uint8_t phase, uint8_t idx, int trim); -#if defined(PCBSKY9X) - #define ROTARY_ENCODER_GRANULARITY (2 << g_eeGeneral.rotarySteps) -#else #define ROTARY_ENCODER_GRANULARITY (2) -#endif #include "gvars.h" @@ -610,12 +585,8 @@ void flightReset(uint8_t check=true); #if defined(SIMU) uint16_t getTmr2MHz(); uint16_t getTmr16KHz(); -#elif defined(STM32) - static inline uint16_t getTmr2MHz() { return TIMER_2MHz_TIMER->CNT; } -#elif defined(PCBSKY9X) - static inline uint16_t getTmr2MHz() { return TC1->TC_CHANNEL[0].TC_CV; } #else - uint16_t getTmr16KHz(); + static inline uint16_t getTmr2MHz() { return TIMER_2MHz_TIMER->CNT; } #endif @@ -875,10 +846,6 @@ enum AUDIO_SOUNDS { AU_SERVO_KO, AU_RX_OVERLOAD, AU_MODEL_STILL_POWERED, -#if defined(PCBSKY9X) - AU_TX_MAH_HIGH, - AU_TX_TEMP_HIGH, -#endif AU_ERROR, AU_WARNING1, AU_WARNING2, @@ -962,10 +929,6 @@ enum AUDIO_SOUNDS { #include "rtc.h" #endif -#if defined(REVX) -void setMFP(); -void clearMFP(); -#endif void checkBattery(); void opentxClose(uint8_t shutdown=true); @@ -1060,12 +1023,10 @@ union ReusableBuffer } sdManager; #endif -#if defined(STM32) struct { char id[27]; } version; -#endif // moduleOptions, receiverOptions, radioVersion PXX2HardwareAndSettings hardwareAndSettings; @@ -1141,10 +1102,8 @@ union ReusableBuffer ModuleInformation internalModule; } viewMain; -#if defined(STM32) // Data for the USB mass storage driver. If USB mass storage runs no menu is not allowed to be displayed uint8_t MSC_BOT_Data[MSC_MEDIA_PACKET]; -#endif }; extern ReusableBuffer reusableBuffer; @@ -1224,9 +1183,7 @@ void varioWakeup(); extern const unsigned char logo_taranis[]; #endif -#if defined(STM32) void usbPluggedIn(); -#endif #include "lua/lua_api.h" diff --git a/radio/src/pulses/dsm2.cpp b/radio/src/pulses/dsm2.cpp index 998a40272..6227a36c7 100644 --- a/radio/src/pulses/dsm2.cpp +++ b/radio/src/pulses/dsm2.cpp @@ -24,9 +24,6 @@ #define DSM2_SEND_BIND (1 << 7) #define DSM2_SEND_RANGECHECK (1 << 5) -#if defined(PCBSKY9X) -uint8_t dsm2BindTimer = DSM2_BIND_TIMEOUT; -#endif // DSM2 control bits #define DSM2_CHANS 6 @@ -135,28 +132,12 @@ void setupPulsesDSM2() break; } -#if defined(PCBSKY9X) - if (dsm2BindTimer > 0) { - dsm2BindTimer--; - if (switchState(SW_DSM2_BIND)) { - moduleState[EXTERNAL_MODULE].mode = MODULE_MODE_BIND; - dsmDat[0] |= DSM2_SEND_BIND; - } - } - else if (moduleState[EXTERNAL_MODULE].mode == MODULE_MODE_RANGECHECK) { - dsmDat[0] |= DSM2_SEND_RANGECHECK; - } - else { - moduleState[EXTERNAL_MODULE].mode = 0; - } -#else if (moduleState[EXTERNAL_MODULE].mode == MODULE_MODE_BIND) { dsmDat[0] |= DSM2_SEND_BIND; } else if (moduleState[EXTERNAL_MODULE].mode == MODULE_MODE_RANGECHECK) { dsmDat[0] |= DSM2_SEND_RANGECHECK; } -#endif dsmDat[1] = g_model.header.modelId[EXTERNAL_MODULE]; // DSM2 Header second byte for model match diff --git a/radio/src/pulses/modules_helpers.h b/radio/src/pulses/modules_helpers.h index 6037536ef..a5be66bbc 100644 --- a/radio/src/pulses/modules_helpers.h +++ b/radio/src/pulses/modules_helpers.h @@ -244,17 +244,10 @@ inline bool isModuleGhost(uint8_t idx) } #endif -#if defined(PCBSKY9X) -inline bool isExtraModule(uint8_t idx) -{ - return idx == EXTRA_MODULE; -} -#else inline bool isExtraModule(uint8_t) { return false; } -#endif inline bool isModuleTypePPM(uint8_t type) { @@ -263,10 +256,6 @@ inline bool isModuleTypePPM(uint8_t type) inline bool isModulePPM(uint8_t moduleIdx) { -#if defined(PCBSKY9X) - if (moduleIdx == EXTRA_MODULE) - return true; -#endif return isModuleTypePPM(g_model.moduleData[moduleIdx].type); } diff --git a/radio/src/pulses/ppm.cpp b/radio/src/pulses/ppm.cpp index 317ed104b..d40df31bd 100644 --- a/radio/src/pulses/ppm.cpp +++ b/radio/src/pulses/ppm.cpp @@ -33,32 +33,18 @@ void setupPulsesPPM(PpmPulsesData * ppmPulsesData, uint8_t channelsStart, int uint8_t firstCh = channelsStart; uint8_t lastCh = min(MAX_OUTPUT_CHANNELS, firstCh + 8 + channelsCount); -#if defined(STM32) ppmPulsesData->ptr = ppmPulsesData->pulses; -#else - uint16_t * ptr = ppmPulsesData->pulses; - ppmPulsesData->ptr = ptr; -#endif int32_t rest = 22500u * 2; rest += int32_t(frameLength) * 1000; for (uint32_t i=firstCh; iptr++ = v; /* as Pat MacKenzie suggests */ -#else - *ptr++ = v; /* as Pat MacKenzie suggests */ -#endif } rest = limit(9000, rest, 65535); /* avoids that CCR2 is bigger than ARR which would cause reboot */ -#if defined(STM32) *ppmPulsesData->ptr++ = rest; *ppmPulsesData->ptr = 0; // it's needed in case PPM is sent without DMA (we stop when we reach this 0) -#else - *ptr = rest; - *(ptr + 1) = 0; -#endif } void setupPulsesPPMTrainer() diff --git a/radio/src/pulses/pulses.cpp b/radio/src/pulses/pulses.cpp index fdd2601e4..052c71dbb 100755 --- a/radio/src/pulses/pulses.cpp +++ b/radio/src/pulses/pulses.cpp @@ -296,12 +296,8 @@ void enablePulsesExternalModule(uint8_t protocol) case PROTOCOL_CHANNELS_DSM2_LP45: case PROTOCOL_CHANNELS_DSM2_DSM2: case PROTOCOL_CHANNELS_DSM2_DSMX: -#if defined(PCBSKY9X) - extmoduleSerialStart(DSM2_BAUDRATE, DSM2_PERIOD * 2000, false); -#else extmoduleSerialStart(); mixerSchedulerSetPeriod(EXTERNAL_MODULE, DSM2_PERIOD); -#endif break; #endif @@ -333,12 +329,8 @@ void enablePulsesExternalModule(uint8_t protocol) #if defined(MULTIMODULE) case PROTOCOL_CHANNELS_MULTIMODULE: -#if defined(PCBSKY9X) - extmoduleSerialStart(MULTIMODULE_BAUDRATE, MULTIMODULE_PERIOD * 2000, true); -#else extmoduleSerialStart(); mixerSchedulerSetPeriod(EXTERNAL_MODULE, MULTIMODULE_PERIOD); -#endif getMultiModuleStatus(EXTERNAL_MODULE).failsafeChecked = false; getMultiModuleStatus(EXTERNAL_MODULE).flags = 0; #if defined(MULTI_PROTOLIST) @@ -349,12 +341,8 @@ void enablePulsesExternalModule(uint8_t protocol) #if defined(SBUS) case PROTOCOL_CHANNELS_SBUS: -#if defined(PCBSKY9X) - extmoduleSerialStart(SBUS_BAUDRATE, SBUS_PERIOD_HALF_US, false); -#else extmoduleSerialStart(); mixerSchedulerSetPeriod(EXTERNAL_MODULE, SBUS_PERIOD); -#endif break; #endif diff --git a/radio/src/pulses/pulses.h b/radio/src/pulses/pulses.h index c4a8a053f..fec47ed4c 100644 --- a/radio/src/pulses/pulses.h +++ b/radio/src/pulses/pulses.h @@ -33,10 +33,6 @@ #include "modules_helpers.h" #include "ff.h" -#if defined(PCBSKY9X) && defined(DSM2) - #define DSM2_BIND_TIMEOUT 255 // 255*11ms - extern uint8_t dsm2BindTimer; -#endif #if defined(DSM2) #define IS_DSM2_PROTOCOL(protocol) (protocol>=PROTOCOL_CHANNELS_DSM2_LP45 && protocol<=PROTOCOL_CHANNELS_DSM2_DSMX) diff --git a/radio/src/sdcard.h b/radio/src/sdcard.h index 51873d4b8..c6e628bcb 100644 --- a/radio/src/sdcard.h +++ b/radio/src/sdcard.h @@ -170,8 +170,6 @@ const char * getBasename(const char * path); #define ETX_FOURCC 0x3378746F // etx for Taranis X9D #elif defined(PCBNV14) #define ETX_FOURCC 0x3A78746F // etx for NV14 -#elif defined(PCBSKY9X) - #define ETX_FOURCC 0x3278746F // etx for sky9x #endif bool isFileAvailable(const char * filename, bool exclDir = false); diff --git a/radio/src/simu.cpp b/radio/src/simu.cpp index e88309434..31a03c705 100644 --- a/radio/src/simu.cpp +++ b/radio/src/simu.cpp @@ -431,15 +431,6 @@ void OpenTxSim::updateKeysAndSwitches(bool start) } \ simuSetSwitch(swtch, state_##swtch) \ -#if defined(PCBSKY9X) - SWITCH_KEY(1, 0, 3); - SWITCH_KEY(2, 1, 2); - SWITCH_KEY(3, 2, 2); - SWITCH_KEY(4, 3, 2); - SWITCH_KEY(5, 4, 2); - SWITCH_KEY(6, 5, 2); - SWITCH_KEY(7, 6, 2); -#else SWITCH_KEY(A, 0, 3); SWITCH_KEY(B, 1, 3); SWITCH_KEY(C, 2, 3); @@ -474,7 +465,6 @@ void OpenTxSim::updateKeysAndSwitches(bool start) SWITCH_KEY(Q, 16, 3); SWITCH_KEY(R, 17, 3); #endif -#endif } long OpenTxSim::onTimeout(FXObject*, FXSelector, void*) diff --git a/radio/src/storage/conversions/conversions_216_218.cpp b/radio/src/storage/conversions/conversions_216_218.cpp index 91cb468f1..67590c85d 100644 --- a/radio/src/storage/conversions/conversions_216_218.cpp +++ b/radio/src/storage/conversions/conversions_216_218.cpp @@ -53,10 +53,6 @@ enum Mix216Sources { MIXSRC216_LAST_POT = MIXSRC216_P3, #endif -#if defined(PCBSKY9X) - MIXSRC216_REa, - MIXSRC216_LAST_ROTARY_ENCODER = MIXSRC216_REa, -#endif MIXSRC216_MAX, @@ -527,13 +523,6 @@ PACK(typedef struct { uint8_t nPotsToWarn; \ int8_t potsWarnPosition[NUM_POTS+NUM_SLIDERS]; \ uint8_t spare[2]; -#elif defined(PCBSKY9X) -#define MODELDATA_EXTRA_216 \ - uint8_t externalModule; \ - ModuleData_v216 moduleData[NUM_MODULES+1]; \ - uint8_t nPotsToWarn; \ - int8_t potsWarnPosition[NUM_POTS+NUM_SLIDERS]; \ - uint8_t rxBattAlarms[2]; #endif #if defined(PCBTARANIS) @@ -882,15 +871,6 @@ void convertRadioData_217_to_218(RadioData &settings) memcpy(settings.bluetoothName, settings_v217.bluetoothName, sizeof(settings.bluetoothName)); #endif -#if defined(PCBSKY9X) - settings.txCurrentCalibration = settings_v217.txCurrentCalibration; - settings.mAhWarn = settings_v217.mAhWarn; - settings.mAhUsed = settings_v217.mAhUsed; - settings.temperatureCalib = settings_v217.temperatureCalib; - settings.optrexDisplay = settings_v217.optrexDisplay; - settings.sticksGain = settings_v217.sticksGain; - settings.rotarySteps = settings_v217.rotarySteps; -#endif } void convertModelData_216_to_217(ModelData &model) @@ -1206,9 +1186,6 @@ void convertModelData_217_to_218(ModelData &model) newModel.flightModeData[i].swtch = convertSwitch_217_to_218(oldModel.flightModeData[i].swtch); newModel.flightModeData[i].fadeIn = oldModel.flightModeData[i].fadeIn; newModel.flightModeData[i].fadeOut = oldModel.flightModeData[i].fadeOut; -#if defined(PCBSKY9X) - memcpy(newModel.flightModeData[i].rotaryEncoders, oldModel.flightModeData[i].rotaryEncoders, sizeof(newModel.flightModeData[i].rotaryEncoders)); -#endif memcpy(newModel.flightModeData[i].gvars, oldModel.flightModeData[i].gvars, sizeof(newModel.flightModeData[i].gvars)); } newModel.thrTraceSrc = oldModel.thrTraceSrc; diff --git a/radio/src/storage/conversions/conversions_218_219.cpp b/radio/src/storage/conversions/conversions_218_219.cpp index 0972a0ed5..798d29309 100644 --- a/radio/src/storage/conversions/conversions_218_219.cpp +++ b/radio/src/storage/conversions/conversions_218_219.cpp @@ -110,12 +110,8 @@ void convertModelData_218_to_219(ModelData &model) { static_assert(sizeof(ModelData_v218) <= sizeof(ModelData), "ModelData size has been reduced"); -#if defined(STM32) ModelData_v218 * oldModelAllocated = (ModelData_v218 *)malloc(sizeof(ModelData_v218)); ModelData_v218 &oldModel = *oldModelAllocated; -#else - ModelData_v218 oldModel; -#endif memcpy(&oldModel, &model, sizeof(ModelData_v218)); ModelData_v219 & newModel = (ModelData_v219 &) model; @@ -269,9 +265,7 @@ void convertModelData_218_to_219(ModelData &model) } } -#if !defined(PCBSKY9X) newModel.trainerData.mode = oldModel.trainerMode; -#endif newModel.trainerData.channelsStart = oldModel.moduleData[NUM_MODULES].channelsStart; newModel.trainerData.channelsCount = oldModel.moduleData[NUM_MODULES].channelsCount; newModel.trainerData.frameLength = oldModel.moduleData[NUM_MODULES].ppm.frameLength; @@ -365,9 +359,7 @@ void convertModelData_218_to_219(ModelData &model) } #endif -#if defined(STM32) free(oldModelAllocated); -#endif } void convertRadioData_218_to_219(RadioData & settings) @@ -377,11 +369,9 @@ void convertRadioData_218_to_219(RadioData & settings) settings.version = 219; settings.variant = EEPROM_VARIANT; -#if defined(STM32) RadioData_v218 * oldSettingsAllocated = (RadioData_v218 *)malloc(sizeof(RadioData_v218)); RadioData_v218 & oldSettings = *oldSettingsAllocated; memcpy(&oldSettings, &settings, sizeof(RadioData_v218)); -#endif #if defined(PCBX9D) || defined(PCBX9DP) // no bluetooth before PCBREV 2019 @@ -451,7 +441,5 @@ void convertRadioData_218_to_219(RadioData & settings) settings.pwrOnSpeed = 0; settings.pwrOffSpeed = 0; -#if defined(STM32) free(oldSettingsAllocated); -#endif } diff --git a/radio/src/storage/conversions/datastructs_218.h b/radio/src/storage/conversions/datastructs_218.h index 131de94e2..7e84c7708 100644 --- a/radio/src/storage/conversions/datastructs_218.h +++ b/radio/src/storage/conversions/datastructs_218.h @@ -112,17 +112,6 @@ #define MAX_INPUTS_218 32 #define MAX_TRAINER_CHANNELS_218 16 #define MAX_TELEMETRY_SENSORS_218 32 -#elif defined(PCBSKY9X) - #define MAX_MODELS_218 60 - #define MAX_OUTPUT_CHANNELS_218 32 // number of real output channels CH1-CH32 - #define MAX_FLIGHT_MODES_218 9 - #define MAX_MIXERS_218 64 - #define MAX_EXPOS_218 32 - #define MAX_LOGICAL_SWITCHES_218 64 - #define MAX_SPECIAL_FUNCTIONS_218 64 // number of functions assigned to switches - #define MAX_INPUTS_218 32 - #define MAX_TRAINER_CHANNELS_218 16 - #define MAX_TELEMETRY_SENSORS_218 32 #endif #if defined(COLORLCD) @@ -194,11 +183,7 @@ PACK(typedef struct { char name[LEN_TIMER_NAME_218]; }) TimerData_v218; -#if defined(PCBSKY9X) - #define ROTENC_DATA int16_t rotaryEncoders[1]; -#else #define ROTENC_DATA -#endif PACK(typedef struct { trim_t trim[NUM_TRIMS]; @@ -343,8 +328,6 @@ PACK(struct FrSkyTelemetryData_v217 { #define MODELDATA_EXTRA_218 uint8_t spare:3; uint8_t trainerMode:3; uint8_t potsWarnMode:2; ModuleData_v218 moduleData[NUM_MODULES+1]; ScriptData scriptsData[MAX_SCRIPTS_218]; char inputNames[MAX_INPUTS_218][LEN_INPUT_NAME_218]; uint8_t potsWarnEnabled; int8_t potsWarnPosition[3 + 4]; #elif defined(PCBTARANIS) #define MODELDATA_EXTRA_218 uint8_t spare:3; uint8_t trainerMode:3; uint8_t potsWarnMode:2; ModuleData_v218 moduleData[NUM_MODULES+1]; ScriptData scriptsData[MAX_SCRIPTS_218]; char inputNames[MAX_INPUTS_218][LEN_INPUT_NAME_218]; uint8_t potsWarnEnabled; int8_t potsWarnPosition[STORAGE_NUM_POTS + STORAGE_NUM_SLIDERS]; -#elif defined(PCBSKY9X) - #define MODELDATA_EXTRA_218 uint8_t spare:6; uint8_t potsWarnMode:2; ModuleData_v218 moduleData[NUM_MODULES+1]; char inputNames[MAX_INPUTS_218][LEN_INPUT_NAME_218]; uint8_t potsWarnEnabled; int8_t potsWarnPosition[STORAGE_NUM_POTS + STORAGE_NUM_SLIDERS]; uint8_t rxBattAlarms[2]; #endif PACK(struct TelemetrySensor_218 { @@ -507,18 +490,6 @@ PACK(struct ModelData_v218 { char switchNames[NUM_SWITCHES_218][LEN_SWITCH_NAME_218]; \ char anaNames[NUM_STICKS+STORAGE_NUM_POTS+STORAGE_NUM_SLIDERS][LEN_ANA_NAME_218]; \ BLUETOOTH_FIELDS_218 -#elif defined(PCBSKY9X) - #define EXTRA_GENERAL_FIELDS_218 \ - int8_t txCurrentCalibration; \ - int8_t temperatureWarn; \ - uint8_t mAhWarn; \ - uint16_t mAhUsed; \ - int8_t temperatureCalib; \ - uint8_t optrexDisplay; \ - uint8_t sticksGain; \ - uint8_t rotarySteps; \ - char switchNames[NUM_SWITCHES_218][LEN_SWITCH_NAME_218]; \ - char anaNames[NUM_STICKS+STORAGE_NUM_POTS+STORAGE_NUM_SLIDERS][LEN_ANA_NAME_218]; #else #define EXTRA_GENERAL_FIELDS_218 EXTRA_GENERAL_FIELDS_GENERAL_218 #endif diff --git a/radio/src/storage/conversions/yaml/myeeprom_220.h b/radio/src/storage/conversions/yaml/myeeprom_220.h index f8b780537..077811b58 100644 --- a/radio/src/storage/conversions/yaml/myeeprom_220.h +++ b/radio/src/storage/conversions/yaml/myeeprom_220.h @@ -249,11 +249,7 @@ enum SwashType { #define IS_MANUAL_RESET_TIMER(idx) (g_model.timers[idx].persistent == 2) -#if !defined(PCBSKY9X) #define TIMER_COUNTDOWN_START(x) (g_model.timers[x].countdownStart == 0 ? 20 : (g_model.timers[x].countdownStart == 1 ? 30 : (g_model.timers[x].countdownStart == -1 ? 10 : 5))) -#else -#define TIMER_COUNTDOWN_START(x) 10 -#endif // #include "pulses/modules_constants.h" diff --git a/radio/src/storage/eeprom_raw.cpp b/radio/src/storage/eeprom_raw.cpp index f3acf4ecb..d669ef933 100644 --- a/radio/src/storage/eeprom_raw.cpp +++ b/radio/src/storage/eeprom_raw.cpp @@ -263,14 +263,7 @@ bool eeLoadGeneral(bool allowFixes) if (g_eeGeneral.version != EEPROM_VER) { TRACE("EEPROM version %d instead of %d", g_eeGeneral.version, EEPROM_VER); -#if defined(PCBSKY9X) - if (!allowFixes) - return false; // prevent eeprom from being wiped - if (!eeConvert()) - return false; -#else return false; -#endif } return true; } @@ -302,10 +295,8 @@ void storageFormat() void eepromWriteWait(EepromWriteState state/* = EEPROM_IDLE*/) { while (eepromWriteState != state) { -#if defined(STM32) // Waits a little bit for CS transitions RTOS_WAIT_MS(2); -#endif eepromWriteProcess(); #ifdef SIMU sleep(5/*ms*/); @@ -466,10 +457,6 @@ const char * eeBackupModel(uint8_t i_fileSrc) return SDCARD_ERROR(result); } -#if defined(PCBSKY9X) - strcpy(statusLineMsg, "File "); - strcpy(statusLineMsg+5, &buf[sizeof(MODELS_PATH)]); -#endif uint16_t size = eeModelSize(i_fileSrc); @@ -499,9 +486,6 @@ const char * eeBackupModel(uint8_t i_fileSrc) f_close(&archiveFile); -#if defined(PCBSKY9X) - showStatusLine(); -#endif return NULL; } diff --git a/radio/src/storage/storage.h b/radio/src/storage/storage.h index 9c3be9dc3..5e4a2f121 100644 --- a/radio/src/storage/storage.h +++ b/radio/src/storage/storage.h @@ -28,8 +28,6 @@ #define WRITE_DELAY_10MS 1500 /* 15s */ #elif defined(PCBTARANIS) #define WRITE_DELAY_10MS 500 -#elif defined(PCBSKY9X) && !defined(REV0) - #define WRITE_DELAY_10MS 500 #else #define WRITE_DELAY_10MS 200 #endif diff --git a/radio/src/strhelpers.cpp b/radio/src/strhelpers.cpp index d2c8c868e..6f4858618 100644 --- a/radio/src/strhelpers.cpp +++ b/radio/src/strhelpers.cpp @@ -420,7 +420,6 @@ char *getFlightModeString(char *dest, int8_t idx) // return dest; // } -#if !defined(PCBSKY9X) int getRawSwitchIdx(char sw) { if (sw < 'A' || sw > 'Z') @@ -484,7 +483,6 @@ char *getSwitchName(char *dest, swsrc_t idx) } return dest; } -#endif char *getSwitchPositionName(char *dest, swsrc_t idx) { @@ -500,14 +498,6 @@ char *getSwitchPositionName(char *dest, swsrc_t idx) idx = -idx; } -#if defined(PCBSKY9X) -#define IDX_TRIMS_IN_STR_VSWITCHES (1 + SWSRC_LAST_SWITCH) -#define IDX_ON_IN_STR_VSWITCHES \ - (IDX_TRIMS_IN_STR_VSWITCHES + SWSRC_LAST_TRIM - SWSRC_FIRST_TRIM + 2) - if (idx <= SWSRC_LAST_SWITCH) { - getStringAtIndex(s, STR_VSWITCHES, idx); - } -#else #define IDX_TRIMS_IN_STR_VSWITCHES (1) #define IDX_ON_IN_STR_VSWITCHES \ (IDX_TRIMS_IN_STR_VSWITCHES + SWSRC_LAST_TRIM - SWSRC_FIRST_TRIM + 1) @@ -517,7 +507,6 @@ char *getSwitchPositionName(char *dest, swsrc_t idx) *s++ = (STR_CHAR_UP "-" STR_CHAR_DOWN)[swinfo.rem]; *s = '\0'; } -#endif // PCBSKY9X #if NUM_XPOTS > 0 else if (idx <= SWSRC_LAST_MULTIPOS_SWITCH) { diff --git a/radio/src/targets/simu/CMakeLists.txt b/radio/src/targets/simu/CMakeLists.txt index 8f45df562..b97f69bf5 100644 --- a/radio/src/targets/simu/CMakeLists.txt +++ b/radio/src/targets/simu/CMakeLists.txt @@ -78,9 +78,7 @@ if(Qt5Widgets_FOUND) set(all_libs_cmd ${CMAKE_COMMAND} -E echo "Building all simulator libraries") foreach(pcb ${PCB_TYPES}) set(pcbrev "") - if(pcb STREQUAL SKY9X) - set(pcbrev "-DPCBREV=REVC") - elseif(pcb STREQUAL X12S) + if(pcb STREQUAL X12S) set(pcbrev "-DPCBREV=13") endif() set(all_libs_cmd ${all_libs_cmd} && ${CMAKE_COMMAND} -DPCB=${pcb} ${pcbrev} -Wno-dev ${CMAKE_SOURCE_DIR} ${CMAKE_BINARY_DIR} && ${CMAKE_COMMAND} --build . --target libsimulator -- ${mkflags}) diff --git a/radio/src/targets/simu/opentxsimulator.cpp b/radio/src/targets/simu/opentxsimulator.cpp index 51408d2eb..727d423e5 100644 --- a/radio/src/targets/simu/opentxsimulator.cpp +++ b/radio/src/targets/simu/opentxsimulator.cpp @@ -633,7 +633,7 @@ const int OpenTxSimulator::voltageToAdc(const int volts) int ret = 0; #if defined(PCBHORUS) || defined(PCBX7) ret = (float)volts * 16.2f; -#elif defined(PCBTARANIS) || defined(PCBSKY9X) +#elif defined(PCBTARANIS) ret = (float)volts * 13.3f; #else ret = (float)volts * 14.15f; diff --git a/radio/src/targets/simu/simpgmspace.cpp b/radio/src/targets/simu/simpgmspace.cpp index caac33826..c816c19b0 100644 --- a/radio/src/targets/simu/simpgmspace.cpp +++ b/radio/src/targets/simu/simpgmspace.cpp @@ -47,7 +47,6 @@ bool simu_running = false; uint32_t telemetryErrors = 0; -#if defined(STM32) GPIO_TypeDef gpioa, gpiob, gpioc, gpiod, gpioe, gpiof, gpiog, gpioh, gpioi, gpioj; TIM_TypeDef tim1, tim2, tim3, tim4, tim5, tim6, tim7, tim8, tim9, tim10; RCC_TypeDef rcc; @@ -76,17 +75,6 @@ void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT) { void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) { } void UART3_Configure(uint32_t baudrate, uint32_t masterClock) { } void NVIC_Init(NVIC_InitTypeDef * NVIC_InitStruct) { } -#else -Pio Pioa, Piob, Pioc; -Pmc pmc; -Ssc ssc; -Pwm pwm; -Tc tc1; -Twi Twio; -Usart Usart0; -Dacc dacc; -Adc Adc0; -#endif FATFS g_FATFS_Obj; @@ -141,9 +129,7 @@ uint64_t CoGetOSTime(void) void simuInit() { -#if defined(STM32) RCC->CSR = 0; -#endif // set power button to "not pressed" #if defined(PWR_SWITCH_GPIO) // STM32 @@ -610,18 +596,6 @@ uint32_t readTrims() uint32_t switchState(uint8_t index) { -#if defined(PCBSKY9X) - switch(index) { - case 0: - return switchesStates[0] < 0; - case 1: - return switchesStates[0] == 0; - case 2: - return switchesStates[0] > 0; - default: - return switchesStates[index - 2] > 0; - } -#else div_t qr = div(index, 3); int state = switchesStates[qr.quot]; switch (qr.rem) { @@ -632,10 +606,8 @@ uint32_t switchState(uint8_t index) default: return state == 0; } -#endif } -#if defined(STM32) int usbPlugged() { return false; } int getSelectedUsbMode() { return USB_JOYSTICK_MODE; } void setSelectedUsbMode(int mode) {} @@ -747,7 +719,6 @@ uint32_t isBootloaderStart(const uint8_t * block) { return 1; } -#endif // defined(STM32) #if defined(PCBXLITES) bool isJackPlugged() diff --git a/radio/src/targets/simu/simpgmspace.h b/radio/src/targets/simu/simpgmspace.h index eb44b8ea7..d4ccd6b22 100644 --- a/radio/src/targets/simu/simpgmspace.h +++ b/radio/src/targets/simu/simpgmspace.h @@ -83,7 +83,6 @@ void sig(int sgn) #define __REV -#if defined(STM32) extern GPIO_TypeDef gpioa, gpiob, gpioc, gpiod, gpioe, gpiof, gpiog, gpioh, gpioi, gpioj; extern TIM_TypeDef tim1, tim2, tim3, tim4, tim5, tim6, tim7, tim8, tim9, tim10; extern USART_TypeDef Usart0, Usart1, Usart2, Usart3, Usart4; @@ -175,48 +174,6 @@ extern RTC_TypeDef rtc; #define ADC (&adc) #undef RTC #define RTC (&rtc) -#elif defined(PCBSKY9X) -extern Pmc pmc; -#undef PMC -#define PMC (&pmc) -extern Ssc ssc; -#undef SSC -#define SSC (&ssc) -extern Pmc pmc; -#undef PMC -#define PMC (&pmc) -extern Tc tc1; -#undef TC1 -#define TC1 (&tc1) -extern Pio Pioa, Piob, Pioc; -extern Twi Twio; -extern Dacc dacc; -extern Usart Usart0; -extern Adc Adc0; -#undef ADC -#define ADC (&Adc0) -#undef USART0 -#define USART0 (&Usart0) -#undef USART1 -#define USART1 (&Usart0) -#undef USART2 -#define USART2 (&Usart0) -#undef USART3 -#define USART3 (&Usart0) -#undef PIOA -#define PIOA (&Pioa) -#undef PIOB -#define PIOB (&Piob) -#undef PIOC -#define PIOC (&Pioc) -#undef TWI0 -#define TWI0 (&Twio) -#undef DACC -#define DACC (&dacc) -extern Pwm pwm; -#undef PWM -#define PWM (&pwm) -#endif extern uint8_t * eeprom; extern void startPdcUsartReceive() ; @@ -276,7 +233,6 @@ void simuMain(); #define USART_GetITStatus(...) 0 #define USART_ClearFlag(...) -#if defined(STM32) #define TIM_DeInit(...) #define TIM_SetCompare2(...) #define TIM_ClearFlag(...) @@ -287,7 +243,6 @@ void simuMain(); #define GPIO_ReadInputDataBit(GPIOx, pin) (GPIOx->BSRRL & pin) #define RCC_AHB1PeriphClockCmd(...) #define RCC_APB2PeriphClockCmd(...) -#endif // inline void delay_01us(uint32_t dummy) { } diff --git a/radio/src/targets/simu/simufatfs.cpp b/radio/src/targets/simu/simufatfs.cpp index 5598217b0..e8737e328 100644 --- a/radio/src/targets/simu/simufatfs.cpp +++ b/radio/src/targets/simu/simufatfs.cpp @@ -609,9 +609,5 @@ FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs) return FR_OK; } -#if defined(PCBSKY9X) -int32_t Card_state = SD_ST_MOUNTED; -uint32_t Card_CSD[4]; // TODO elsewhere -#endif #endif // #if defined(SIMU_USE_SDCARD) diff --git a/radio/src/targets/sky9x/AT91SAM3S2.h b/radio/src/targets/sky9x/AT91SAM3S2.h deleted file mode 100644 index 302f55631..000000000 --- a/radio/src/targets/sky9x/AT91SAM3S2.h +++ /dev/null @@ -1,7036 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Atmel Microcontroller Software Support */ -/* ---------------------------------------------------------------------------- */ -/* Copyright (c) 2009, Atmel Corporation */ -/* */ -/* All rights reserved. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following condition is met: */ -/* */ -/* - Redistributions of source code must retain the above copyright notice, */ -/* this list of conditions and the disclaimer below. */ -/* */ -/* Atmel's name may not be used to endorse or promote products derived from */ -/* this software without specific prior written permission. */ -/* */ -/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ -/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ -/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ -/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ -/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ -/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ -/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ -/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ -/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* ---------------------------------------------------------------------------- */ -/* */ -/* File Name : AT91SAM3S.h */ -/* Object : AT91SAM3S definitions */ -/* Generated by : AT91 SW Application Group */ -/* Generated on : 2009-10-26 */ - -#ifndef _AT91SAM3S2_H_ -#define _AT91SAM3S2_H_ - -/** \addtogroup AT91SAM3S_definitions AT91SAM3S definitions - This file defines all structures and symbols for AT91SAM3S: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __ASSEMBLY__ -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *) value) -#define REG_ACCESS(type, address) (*(type*)address) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ***************************************************************************** */ -/* CMSIS DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_cmsis CMSIS Definitions */ - -/*@{*/ - -/** - * \brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __MPU_PRESENT 0 /**< AT91SAM3S does not provide a MPU present or not */ -#define __NVIC_PRIO_BITS 4 /**< AT91SAM3S uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ - -/**< Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************/ - NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ -/****** AT91SAM3S specific Interrupt Numbers *****************************************/ - - SUPC_IRQn = 0, /**< 0 AT91SAM3S Supply Controller (SUPC) */ - RSTC_IRQn = 1, /**< 1 AT91SAM3S Reset Controller (RSTC) */ - RTC_IRQn = 2, /**< 2 AT91SAM3S Real Time Clock (RTC) */ - RTT_IRQn = 3, /**< 3 AT91SAM3S Real Time Timer (RTT) */ - WDT_IRQn = 4, /**< 4 AT91SAM3S Watchdog Timer (WDT) */ - PMC_IRQn = 5, /**< 5 AT91SAM3S Power Management Controller (PMC) */ - EFC_IRQn = 6, /**< 6 AT91SAM3S Enhanced Flash Controller (EFC) */ - UART0_IRQn = 8, /**< 8 AT91SAM3S UART 0 (UART0) */ - UART1_IRQn = 9, /**< 9 AT91SAM3S UART 1 (UART1) */ - SMC_IRQn = 10, /**< 10 AT91SAM3S Static Memory Controller (SMC) */ - PIOA_IRQn = 11, /**< 11 AT91SAM3S Parallel I/O Controller A (PIOA) */ - PIOB_IRQn = 12, /**< 12 AT91SAM3S Parallel I/O Controller B (PIOB) */ - PIOC_IRQn = 13, /**< 13 AT91SAM3S Parallel I/O Controller C (PIOC) */ - USART0_IRQn = 14, /**< 14 AT91SAM3S USART 0 (USART0) */ - USART1_IRQn = 15, /**< 15 AT91SAM3S USART 1 (USART1) */ - HSMCI_IRQn = 18, /**< 18 AT91SAM3S Multimedia Card Interface (HSMCI) */ - TWI0_IRQn = 19, /**< 19 AT91SAM3S Two Wire Interface 0 (TWI0) */ - TWI1_IRQn = 20, /**< 20 AT91SAM3S Two Wire Interface 1 (TWI1) */ - SPI_IRQn = 21, /**< 21 AT91SAM3S Serial Peripheral Interface (SPI) */ - SSC_IRQn = 22, /**< 22 AT91SAM3S Synchronous Serial Controler (SSC) */ - TC0_IRQn = 23, /**< 23 AT91SAM3S Timer/Counter 0 (TC0) */ - TC1_IRQn = 24, /**< 24 AT91SAM3S Timer/Counter 1 (TC1) */ - TC2_IRQn = 25, /**< 25 AT91SAM3S Timer/Counter 2 (TC2) */ - TC3_IRQn = 26, /**< 26 AT91SAM3S Timer/Counter 3 (TC3) */ - TC4_IRQn = 27, /**< 27 AT91SAM3S Timer/Counter 4 (TC4) */ - TC5_IRQn = 28, /**< 28 AT91SAM3S Timer/Counter 5 (TC5) */ - ADC_IRQn = 29, /**< 29 AT91SAM3S Analog To Digital Converter (ADC) */ - DACC_IRQn = 30, /**< 30 AT91SAM3S Digital To Analog Converter (DACC) */ - PWM_IRQn = 31, /**< 31 AT91SAM3S Pulse Width Modulation (PWM) */ - CRCCU_IRQn = 32, /**< 32 AT91SAM3S CRC Calculation Unit (CRCCU) */ - ACC_IRQn = 33, /**< 33 AT91SAM3S Analog Comparator (ACC) */ - UDP_IRQn = 34 /**< 34 AT91SAM3S USB Device Port (UDP) */ -} IRQn_Type; -/*@}*/ - -/* ***************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_api Peripheral Software API */ -/*@{*/ -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_ACC Analog Comparator Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Acc hardware registers */ -typedef struct { - WoReg ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */ - RwReg ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */ - RwReg Reserved1[7]; - WoReg ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */ - WoReg ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */ - RoReg ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */ - RoReg ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */ - RwReg Reserved2[24]; - RwReg ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */ - RwReg Reserved3[19]; - RwReg ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protect Mode Register */ - RoReg ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protect Status Register */ -} Acc; -#endif /* __ASSEMBLY__ */ -/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */ -#define ACC_CR_SWRST (0x1 << 0) /**< \brief (ACC_CR) SoftWare ReSeT */ -/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */ -#define ACC_MR_SELPLUS (0x7 << 0) /**< \brief (ACC_MR) SELection for PLUS comparator input */ -#define ACC_MR_SELMINUS (0x7 << 4) /**< \brief (ACC_MR) SELection for MINUS comparator input */ -#define ACC_MR_ACEN (0x1 << 8) /**< \brief (ACC_MR) Analog Comparator ENable */ -#define ACC_MR_ACEN_EN (0x1 << 8) /**< \brief (ACC_MR) Analog Comparator ENable */ -#define ACC_MR_ACEN_DIS (0x0 << 8) /**< \brief (ACC_MR) Analog Comparator Disable */ -#define ACC_MR_EDGETYP (0x3 << 9) /**< \brief (ACC_MR) EDGE TYPe */ -#define ACC_MR_EDGETYP_RISING (0x0 << 9) /**< \brief (ACC_MR) EDGE TYPe ,RISING edge*/ -#define ACC_MR_EDGETYP_FALLING (0x1 << 9) /**< \brief (ACC_MR) EDGE TYPe,falling edge */ -#define ACC_MR_EDGETYP_ANY (0x2 << 9) /**< \brief (ACC_MR) EDGE TYPe,any edge */ -#define ACC_MR_INV (0x1 << 12) /**< \brief (ACC_MR) INVert comparator output */ -#define ACC_MR_INV_EN (0x1 << 12) /**< \brief (ACC_MR) INVert comparator output */ -#define ACC_MR_INV_DIS (0x0 << 12) /**< \brief (ACC_MR) DIRECTLY */ -#define ACC_MR_SELFS (0x1 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ -#define ACC_MR_SELFS_CF (0x0 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ -#define ACC_MR_SELFS_OUTPUT (0x1 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ -#define ACC_MR_FE (0x1 << 14) /**< \brief (ACC_MR) Fault Enable */ -#define ACC_MR_FE_EN (0x1 << 14) /**< \brief (ACC_MR) Fault Enable */ -#define ACC_MR_FE_DIS (0x0 << 14) /**< \brief (ACC_MR) Fault Enable */ -/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */ -#define ACC_IER_CE (0x1 << 0) /**< \brief (ACC_IER) Comparison Edge */ -/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */ -#define ACC_IDR_CE (0x1 << 0) /**< \brief (ACC_IDR) Comparison Edge */ -/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */ -#define ACC_IMR_CE (0x1 << 0) /**< \brief (ACC_IMR) Comparison Edge */ -/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */ -#define ACC_ISR_CE (0x1 << 0) /**< \brief (ACC_ISR) Comparison Edge */ -#define ACC_ISR_SCO (0x1 << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */ -#define ACC_ISR_MASK (0x1 << 31) /**< \brief (ACC_ISR) */ -/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */ -#define ACC_ACR_ISEL (0x1 << 0) /**< \brief (ACC_ACR) Current SELection */ -#define ACC_ACR_HYST (0x3 << 1) /**< \brief (ACC_ACR) HYSTeresis selection */ -/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protect Mode Register -------- */ -#define ACC_WPMR_WPEN (0x1 << 0) /**< \brief (ACC_WPMR) Write Protect Enable */ -#define ACC_WPMR_WPKEY (0xffffff << 8) /**< \brief (ACC_WPMR) Write Protect KEY */ -/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protect Status Register -------- */ -#define ACC_WPSR_WPROTERR (0x1 << 0) /**< \brief (ACC_WPSR) Write PROTection ERRor */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Analog-to-digital Converter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_ADC Analog-to-digital Converter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Adc hardware registers */ -typedef struct { - WoReg ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */ - RwReg ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */ - RwReg ADC_SEQR1; /**< \brief (Adc Offset: 0x08) Channel Sequence 1Register */ - RwReg ADC_SEQR2; /**< \brief (Adc Offset: 0x0C) Channel Sequence 2 Register */ - WoReg ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */ - WoReg ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */ - RoReg ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */ - RwReg Reserved1[1]; - RoReg ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */ - WoReg ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */ - WoReg ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */ - RoReg ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */ - RoReg ADC_ISR; /**< \brief (Adc Offset: 0x30) Interrupt Status Register */ - RwReg Reserved2[2]; - RoReg ADC_OVER; /**< \brief (Adc Offset: 0x3C) Overrun Status Register */ - RwReg ADC_EMR; /**< \brief (Adc Offset: 0x40) Extended Mode Register */ - RwReg ADC_CWR; /**< \brief (Adc Offset: 0x44) Compare Window Register */ - RwReg ADC_CGR; /**< \brief (Adc Offset: 0x48) Channel Gain Register */ - RwReg ADC_COR; /**< \brief (Adc Offset: 0x4C) Channel Offset Register */ - RoReg ADC_CDR0; /**< \brief (Adc Offset: 0x50) Channel Data Register 0 */ - RoReg ADC_CDR1; /**< \brief (Adc Offset: 0x54) Channel Data Register 1 */ - RoReg ADC_CDR2; /**< \brief (Adc Offset: 0x58) Channel Data Register 2 */ - RoReg ADC_CDR3; /**< \brief (Adc Offset: 0x5C) Channel Data Register 3 */ - RoReg ADC_CDR4; /**< \brief (Adc Offset: 0x60) Channel Data Register 4 */ - RoReg ADC_CDR5; /**< \brief (Adc Offset: 0x64) Channel Data Register 5 */ - RoReg ADC_CDR6; /**< \brief (Adc Offset: 0x68) Channel Data Register 6 */ - RoReg ADC_CDR7; /**< \brief (Adc Offset: 0x6C) Channel Data Register 7 */ - RoReg ADC_CDR8; /**< \brief (Adc Offset: 0x70) Channel Data Register 8 */ - RoReg ADC_CDR9; /**< \brief (Adc Offset: 0x74) Channel Data Register 9 */ - RoReg ADC_CDR10; /**< \brief (Adc Offset: 0x78) Channel Data Register 10 */ - RoReg ADC_CDR11; /**< \brief (Adc Offset: 0x7C) Channel Data Register 11 */ - RoReg ADC_CDR12; /**< \brief (Adc Offset: 0x80) Channel Data Register 12 */ - RoReg ADC_CDR13; /**< \brief (Adc Offset: 0x84) Channel Data Register 13 */ - RoReg ADC_CDR14; /**< \brief (Adc Offset: 0x88) Channel Data Register 14 */ - RoReg ADC_CDR15; /**< \brief (Adc Offset: 0x8C) Channel Data Register 15 */ - RwReg Reserved3[1]; - RwReg ADC_ACR; /**< \brief (Adc Offset: 0x94) Analog Control Register */ - RwReg Reserved4[19]; - RwReg ADC_WPMR; /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */ - RoReg ADC_WPSR; /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */ - RwReg Reserved5[5]; - RwReg ADC_RPR; /**< \brief (Adc Offset: 0x100) Receive Pointer Register */ - RwReg ADC_RCR; /**< \brief (Adc Offset: 0x104) Receive Counter Register */ - RwReg ADC_TPR; /**< \brief (Adc Offset: 0x108) Transmit Pointer Register */ - RwReg ADC_TCR; /**< \brief (Adc Offset: 0x10C) Transmit Counter Register */ - RwReg ADC_RNPR; /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */ - RwReg ADC_RNCR; /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */ - RwReg ADC_TNPR; /**< \brief (Adc Offset: 0x118) Transmit Next Pointer Register */ - RwReg ADC_TNCR; /**< \brief (Adc Offset: 0x11C) Transmit Next Counter Register */ - WoReg ADC_PTCR; /**< \brief (Adc Offset: 0x120) Transfer Control Register */ - RoReg ADC_PTSR; /**< \brief (Adc Offset: 0x124) Transfer Status Register */ -} Adc; -#endif /* __ASSEMBLY__ */ -/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */ -#define ADC_CR_SWRST (0x1 << 0) /**< \brief (ADC_CR) Software Reset */ -#define ADC_CR_START (0x1 << 1) /**< \brief (ADC_CR) Start Conversion */ -/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */ -#define ADC_MR_TRGEN (0x1 << 0) /**< \brief (ADC_MR) Trigger Enable */ -#define ADC_MR_TRGEN_DIS (0x0 << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software.*/ -#define ADC_MR_TRGEN_EN (0x1) /**< (ADC) Hardware trigger selected by TRGSEL field is enabled.*/ -#define ADC_MR_TRGSEL (0x7 << 1) /**< \brief (ADC_MR) Trigger Selection */ -#define ADC_MR_TRGSEL_EXT (0x0 << 1) /**< \brief (ADC_MR) Selected TRGSEL = External Trigger*/ -#define ADC_MR_TRGSEL_TIOA0 (0x1 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO0*/ -#define ADC_MR_TRGSEL_TIOA1 (0x2 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO1*/ -#define ADC_MR_TRGSEL_TIOA2 (0x3 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO2*/ -#define ADC_MR_TRGSEL_PWM0_TRIG (0x4 << 1) /**< \brief (ADC_MR) Selected TRGSEL = PWM trigger*/ -#define ADC_MR_TRGSEL_PWM1_TRIG (0x5 << 1) /**< \brief (ADC_MR) Selected TRGSEL = PWM Trigger*/ -#define ADC_MR_TRGSEL_RESERVED (0x6 << 1) /**< \brief (ADC_MR) Selected TRGSEL = Reserved*/ -#define ADC_MR_LOWRES (0x1 << 4) /**< \brief (ADC_MR) Resolution */ -#define ADC_MR_LOWRES_12_BIT (0x0 << 4) /**< \brief (ADC_MR) 12-bit resolution*/ -#define ADC_MR_LOWRES_10_BIT (0x1 << 4) /**< \brief (ADC_MR) 10-bit resolution*/ -#define ADC_MR_SLEEP (0x1 << 5) /**< \brief (ADC_MR) Sleep Mode */ -#define ADC_MR_SLEEP_NORMAL (0x0 << 5) /**< \brief (ADC12B) Normal Mode*/ -#define ADC_MR_FWUP (0x1 << 6) /**< \brief (ADC_MR) Fast Wake Up */ -#define ADC_MR_FREERUN (0x1 << 7) /**< \brief (ADC_MR) Free Run Mode */ -#define ADC_MR_PRESCAL (0xff << 8) /**< \brief (ADC_MR) Prescaler Rate Selection */ -#define ADC_MR_STARTUP (0xf << 16) /**< \brief (ADC_MR) Start Up Time */ -#define ADC_MR_SETTLING (0x3 << 20) /**< \brief (ADC_MR) Analog Settling Time */ -#define ADC_MR_ANACH (0x1 << 23) /**< \brief (ADC_MR) Analog Change */ -#define ADC_MR_TRACKTIM (0xf << 24) /**< \brief (ADC_MR) Tracking Time */ -#define ADC_MR_TRANSFER (0x3 << 28) /**< \brief (ADC_MR) */ -#define ADC_MR_USEQ (0x1 << 31) /**< \brief (ADC_MR) User Sequence Enable */ -/* -------- ADC_SEQ1R : (ADC Offset: 0x08) Channel Sequence 1Register -------- */ -#define ADC_SEQ1R_USCH1 (0x7 << 0) /**< \brief (ADC_SEQ1R) User Sequence Number 1 */ -#define ADC_SEQ1R_USCH2 (0x7 << 4) /**< \brief (ADC_SEQ1R) User Sequence Number 2 */ -#define ADC_SEQ1R_USCH3 (0x7 << 8) /**< \brief (ADC_SEQ1R) User Sequence Number 3 */ -#define ADC_SEQ1R_USCH4 (0x7 << 12) /**< \brief (ADC_SEQ1R) User Sequence Number 4 */ -#define ADC_SEQ1R_USCH5 (0x7 << 16) /**< \brief (ADC_SEQ1R) User Sequence Number 5 */ -#define ADC_SEQ1R_USCH6 (0x7 << 20) /**< \brief (ADC_SEQ1R) User Sequence Number 6 */ -#define ADC_SEQ1R_USCH7 (0x7 << 24) /**< \brief (ADC_SEQ1R) User Sequence Number 7 */ -#define ADC_SEQ1R_USCH8 (0x7 << 28) /**< \brief (ADC_SEQ1R) User Sequence Number 8 */ -/* -------- ADC_SEQ2R : (ADC Offset: 0x0C) Channel Sequence 2 Register -------- */ -#define ADC_SEQ2R_USCH9 (0x7 << 0) /**< \brief (ADC_SEQ2R) User Sequence Number 9 */ -#define ADC_SEQ2R_USCH10 (0x7 << 4) /**< \brief (ADC_SEQ2R) User Sequence Number 10 */ -#define ADC_SEQ2R_USCH11 (0x7 << 8) /**< \brief (ADC_SEQ2R) User Sequence Number 11 */ -#define ADC_SEQ2R_USCH12 (0x7 << 12) /**< \brief (ADC_SEQ2R) User Sequence Number 12 */ -#define ADC_SEQ2R_USCH13 (0x7 << 16) /**< \brief (ADC_SEQ2R) User Sequence Number 13 */ -#define ADC_SEQ2R_USCH14 (0x7 << 20) /**< \brief (ADC_SEQ2R) User Sequence Number 14 */ -#define ADC_SEQ2R_USCH15 (0x7 << 24) /**< \brief (ADC_SEQ2R) User Sequence Number 15 */ -#define ADC_SEQ2R_USCH16 (0x7 << 28) /**< \brief (ADC_SEQ2R) User Sequence Number 16 */ -/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */ -#define ADC_CHER_CH0 (0x1 << 0) /**< \brief (ADC_CHER) Channel 0 Enable */ -#define ADC_CHER_CH1 (0x1 << 1) /**< \brief (ADC_CHER) Channel 1 Enable */ -#define ADC_CHER_CH2 (0x1 << 2) /**< \brief (ADC_CHER) Channel 2 Enable */ -#define ADC_CHER_CH3 (0x1 << 3) /**< \brief (ADC_CHER) Channel 3 Enable */ -#define ADC_CHER_CH4 (0x1 << 4) /**< \brief (ADC_CHER) Channel 4 Enable */ -#define ADC_CHER_CH5 (0x1 << 5) /**< \brief (ADC_CHER) Channel 5 Enable */ -#define ADC_CHER_CH6 (0x1 << 6) /**< \brief (ADC_CHER) Channel 6 Enable */ -#define ADC_CHER_CH7 (0x1 << 7) /**< \brief (ADC_CHER) Channel 7 Enable */ -#define ADC_CHER_CH8 (0x1 << 8) /**< \brief (ADC_CHER) Channel 8 Enable */ -#define ADC_CHER_CH9 (0x1 << 9) /**< \brief (ADC_CHER) Channel 9 Enable */ -#define ADC_CHER_CH10 (0x1 << 10) /**< \brief (ADC_CHER) Channel 10 Enable */ -#define ADC_CHER_CH11 (0x1 << 11) /**< \brief (ADC_CHER) Channel 11 Enable */ -#define ADC_CHER_CH12 (0x1 << 12) /**< \brief (ADC_CHER) Channel 12 Enable */ -#define ADC_CHER_CH13 (0x1 << 13) /**< \brief (ADC_CHER) Channel 13 Enable */ -#define ADC_CHER_CH14 (0x1 << 14) /**< \brief (ADC_CHER) Channel 14 Enable */ -#define ADC_CHER_CH15 (0x1 << 15) /**< \brief (ADC_CHER) Channel 15 Enable */ -/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */ -#define ADC_CHDR_CH0 (0x1 << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */ -#define ADC_CHDR_CH1 (0x1 << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */ -#define ADC_CHDR_CH2 (0x1 << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */ -#define ADC_CHDR_CH3 (0x1 << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */ -#define ADC_CHDR_CH4 (0x1 << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */ -#define ADC_CHDR_CH5 (0x1 << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */ -#define ADC_CHDR_CH6 (0x1 << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */ -#define ADC_CHDR_CH7 (0x1 << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */ -#define ADC_CHDR_CH8 (0x1 << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */ -#define ADC_CHDR_CH9 (0x1 << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */ -#define ADC_CHDR_CH10 (0x1 << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */ -#define ADC_CHDR_CH11 (0x1 << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */ -#define ADC_CHDR_CH12 (0x1 << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */ -#define ADC_CHDR_CH13 (0x1 << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */ -#define ADC_CHDR_CH14 (0x1 << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */ -#define ADC_CHDR_CH15 (0x1 << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */ -/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */ -#define ADC_CHSR_CH0 (0x1 << 0) /**< \brief (ADC_CHSR) Channel 0 Status */ -#define ADC_CHSR_CH1 (0x1 << 1) /**< \brief (ADC_CHSR) Channel 1 Status */ -#define ADC_CHSR_CH2 (0x1 << 2) /**< \brief (ADC_CHSR) Channel 2 Status */ -#define ADC_CHSR_CH3 (0x1 << 3) /**< \brief (ADC_CHSR) Channel 3 Status */ -#define ADC_CHSR_CH4 (0x1 << 4) /**< \brief (ADC_CHSR) Channel 4 Status */ -#define ADC_CHSR_CH5 (0x1 << 5) /**< \brief (ADC_CHSR) Channel 5 Status */ -#define ADC_CHSR_CH6 (0x1 << 6) /**< \brief (ADC_CHSR) Channel 6 Status */ -#define ADC_CHSR_CH7 (0x1 << 7) /**< \brief (ADC_CHSR) Channel 7 Status */ -#define ADC_CHSR_CH8 (0x1 << 8) /**< \brief (ADC_CHSR) Channel 8 Status */ -#define ADC_CHSR_CH9 (0x1 << 9) /**< \brief (ADC_CHSR) Channel 9 Status */ -#define ADC_CHSR_CH10 (0x1 << 10) /**< \brief (ADC_CHSR) Channel 10 Status */ -#define ADC_CHSR_CH11 (0x1 << 11) /**< \brief (ADC_CHSR) Channel 11 Status */ -#define ADC_CHSR_CH12 (0x1 << 12) /**< \brief (ADC_CHSR) Channel 12 Status */ -#define ADC_CHSR_CH13 (0x1 << 13) /**< \brief (ADC_CHSR) Channel 13 Status */ -#define ADC_CHSR_CH14 (0x1 << 14) /**< \brief (ADC_CHSR) Channel 14 Status */ -#define ADC_CHSR_CH15 (0x1 << 15) /**< \brief (ADC_CHSR) Channel 15 Status */ -/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */ -#define ADC_LCDR_LDATA (0xfff << 0) /**< \brief (ADC_LCDR) Last Data Converted */ -#define ADC_LCDR_CHNB (0xf << 12) /**< \brief (ADC_LCDR) Channel Number */ -/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */ -#define ADC_IER_EOC0 (0x1 << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */ -#define ADC_IER_EOC1 (0x1 << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */ -#define ADC_IER_EOC2 (0x1 << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */ -#define ADC_IER_EOC3 (0x1 << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */ -#define ADC_IER_EOC4 (0x1 << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */ -#define ADC_IER_EOC5 (0x1 << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */ -#define ADC_IER_EOC6 (0x1 << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */ -#define ADC_IER_EOC7 (0x1 << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */ -#define ADC_IER_EOC8 (0x1 << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */ -#define ADC_IER_EOC9 (0x1 << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */ -#define ADC_IER_EOC10 (0x1 << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */ -#define ADC_IER_EOC11 (0x1 << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */ -#define ADC_IER_EOC12 (0x1 << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */ -#define ADC_IER_EOC13 (0x1 << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */ -#define ADC_IER_EOC14 (0x1 << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */ -#define ADC_IER_EOC15 (0x1 << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */ -#define ADC_IER_DRDY (0x1 << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */ -#define ADC_IER_GOVRE (0x1 << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */ -#define ADC_IER_COMPE (0x1 << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */ -#define ADC_IER_ENDRX (0x1 << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */ -#define ADC_IER_RXBUFF (0x1 << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */ -/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */ -#define ADC_IDR_EOC0 (0x1 << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */ -#define ADC_IDR_EOC1 (0x1 << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */ -#define ADC_IDR_EOC2 (0x1 << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */ -#define ADC_IDR_EOC3 (0x1 << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */ -#define ADC_IDR_EOC4 (0x1 << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */ -#define ADC_IDR_EOC5 (0x1 << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */ -#define ADC_IDR_EOC6 (0x1 << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */ -#define ADC_IDR_EOC7 (0x1 << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */ -#define ADC_IDR_EOC8 (0x1 << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */ -#define ADC_IDR_EOC9 (0x1 << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */ -#define ADC_IDR_EOC10 (0x1 << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */ -#define ADC_IDR_EOC11 (0x1 << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */ -#define ADC_IDR_EOC12 (0x1 << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */ -#define ADC_IDR_EOC13 (0x1 << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */ -#define ADC_IDR_EOC14 (0x1 << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */ -#define ADC_IDR_EOC15 (0x1 << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */ -#define ADC_IDR_DRDY (0x1 << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */ -#define ADC_IDR_GOVRE (0x1 << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */ -#define ADC_IDR_COMPE (0x1 << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */ -#define ADC_IDR_ENDRX (0x1 << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */ -#define ADC_IDR_RXBUFF (0x1 << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */ -/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */ -#define ADC_IMR_EOC0 (0x1 << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */ -#define ADC_IMR_EOC1 (0x1 << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */ -#define ADC_IMR_EOC2 (0x1 << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */ -#define ADC_IMR_EOC3 (0x1 << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */ -#define ADC_IMR_EOC4 (0x1 << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */ -#define ADC_IMR_EOC5 (0x1 << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */ -#define ADC_IMR_EOC6 (0x1 << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */ -#define ADC_IMR_EOC7 (0x1 << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */ -#define ADC_IMR_EOC8 (0x1 << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */ -#define ADC_IMR_EOC9 (0x1 << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */ -#define ADC_IMR_EOC10 (0x1 << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */ -#define ADC_IMR_EOC11 (0x1 << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */ -#define ADC_IMR_EOC12 (0x1 << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */ -#define ADC_IMR_EOC13 (0x1 << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */ -#define ADC_IMR_EOC14 (0x1 << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */ -#define ADC_IMR_EOC15 (0x1 << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */ -#define ADC_IMR_DRDY (0x1 << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */ -#define ADC_IMR_GOVRE (0x1 << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */ -#define ADC_IMR_COMPE (0x1 << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */ -#define ADC_IMR_ENDRX (0x1 << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */ -#define ADC_IMR_RXBUFF (0x1 << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */ -/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */ -#define ADC_ISR_EOC0 (0x1 << 0) /**< \brief (ADC_ISR) End of Conversion 0 */ -#define ADC_ISR_EOC1 (0x1 << 1) /**< \brief (ADC_ISR) End of Conversion 1 */ -#define ADC_ISR_EOC2 (0x1 << 2) /**< \brief (ADC_ISR) End of Conversion 2 */ -#define ADC_ISR_EOC3 (0x1 << 3) /**< \brief (ADC_ISR) End of Conversion 3 */ -#define ADC_ISR_EOC4 (0x1 << 4) /**< \brief (ADC_ISR) End of Conversion 4 */ -#define ADC_ISR_EOC5 (0x1 << 5) /**< \brief (ADC_ISR) End of Conversion 5 */ -#define ADC_ISR_EOC6 (0x1 << 6) /**< \brief (ADC_ISR) End of Conversion 6 */ -#define ADC_ISR_EOC7 (0x1 << 7) /**< \brief (ADC_ISR) End of Conversion 7 */ -#define ADC_ISR_EOC8 (0x1 << 8) /**< \brief (ADC_ISR) End of Conversion 8 */ -#define ADC_ISR_EOC9 (0x1 << 9) /**< \brief (ADC_ISR) End of Conversion 9 */ -#define ADC_ISR_EOC10 (0x1 << 10) /**< \brief (ADC_ISR) End of Conversion 10 */ -#define ADC_ISR_EOC11 (0x1 << 11) /**< \brief (ADC_ISR) End of Conversion 11 */ -#define ADC_ISR_EOC12 (0x1 << 12) /**< \brief (ADC_ISR) End of Conversion 12 */ -#define ADC_ISR_EOC13 (0x1 << 13) /**< \brief (ADC_ISR) End of Conversion 13 */ -#define ADC_ISR_EOC14 (0x1 << 14) /**< \brief (ADC_ISR) End of Conversion 14 */ -#define ADC_ISR_EOC15 (0x1 << 15) /**< \brief (ADC_ISR) End of Conversion 15 */ -#define ADC_ISR_DRDY (0x1 << 24) /**< \brief (ADC_ISR) Data Ready */ -#define ADC_ISR_GOVRE (0x1 << 25) /**< \brief (ADC_ISR) General Overrun Error */ -#define ADC_ISR_COMPE (0x1 << 26) /**< \brief (ADC_ISR) Comparison Error */ -#define ADC_ISR_ENDRX (0x1 << 27) /**< \brief (ADC_ISR) End of RX Buffer */ -#define ADC_ISR_RXBUFF (0x1 << 28) /**< \brief (ADC_ISR) RX Buffer Full */ -/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */ -#define ADC_OVER_OVRE0 (0x1 << 0) /**< \brief (ADC_OVER) Overrun Error 0 */ -#define ADC_OVER_OVRE1 (0x1 << 1) /**< \brief (ADC_OVER) Overrun Error 1 */ -#define ADC_OVER_OVRE2 (0x1 << 2) /**< \brief (ADC_OVER) Overrun Error 2 */ -#define ADC_OVER_OVRE3 (0x1 << 3) /**< \brief (ADC_OVER) Overrun Error 3 */ -#define ADC_OVER_OVRE4 (0x1 << 4) /**< \brief (ADC_OVER) Overrun Error 4 */ -#define ADC_OVER_OVRE5 (0x1 << 5) /**< \brief (ADC_OVER) Overrun Error 5 */ -#define ADC_OVER_OVRE6 (0x1 << 6) /**< \brief (ADC_OVER) Overrun Error 6 */ -#define ADC_OVER_OVRE7 (0x1 << 7) /**< \brief (ADC_OVER) Overrun Error 7 */ -#define ADC_OVER_OVRE8 (0x1 << 8) /**< \brief (ADC_OVER) Overrun Error 8 */ -#define ADC_OVER_OVRE9 (0x1 << 9) /**< \brief (ADC_OVER) Overrun Error 9 */ -#define ADC_OVER_OVRE10 (0x1 << 10) /**< \brief (ADC_OVER) Overrun Error 10 */ -#define ADC_OVER_OVRE11 (0x1 << 11) /**< \brief (ADC_OVER) Overrun Error 11 */ -#define ADC_OVER_OVRE12 (0x1 << 12) /**< \brief (ADC_OVER) Overrun Error 12 */ -#define ADC_OVER_OVRE13 (0x1 << 13) /**< \brief (ADC_OVER) Overrun Error 13 */ -#define ADC_OVER_OVRE14 (0x1 << 14) /**< \brief (ADC_OVER) Overrun Error 14 */ -#define ADC_OVER_OVRE15 (0x1 << 15) /**< \brief (ADC_OVER) Overrun Error 15 */ -/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */ -#define ADC_EMR_CMPMODE (0x3 << 0) /**< \brief (ADC_EMR) Comparison Mode */ -#define ADC_EMR_CMPMODE_LOW (0x0 << 0) /**< \brief (ADC_EMR) Comparison Mode,lower than low threshold */ -#define ADC_EMR_CMPMODE_HIGH (0x1 << 0) /**< \brief (ADC_EMR) Comparison Mode,higher than high threshold */ -#define ADC_EMR_CMPMODE_IN (0x2 << 0) /**< \brief (ADC_EMR) Comparison Mode, in the comparison window */ -#define ADC_EMR_CMPMODE_OUT (0x3 << 0) /**< \brief (ADC_EMR) Comparison Mode, out of the comparison window */ -#define ADC_EMR_CMPSEL (0xf << 4) /**< \brief (ADC_EMR) Comparison Selected Channel */ -#define ADC_EMR_CMPALL (0x1 << 9) /**< \brief (ADC_EMR) Compare All Channels */ -#define ADC_EMR_TAG (0x1 << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */ -/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */ -#define ADC_CWR_LOWTHRES (0xfff << 0) /**< \brief (ADC_CWR) Low Threshold */ -#define ADC_CWR_HIGHTHRES (0xfff << 16) /**< \brief (ADC_CWR) High Threshold */ -/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */ -#define ADC_CGR_GAIN0 (0x3 << 0) /**< \brief (ADC_CGR) Gain for channel 0 */ -#define ADC_CGR_GAIN1 (0x3 << 2) /**< \brief (ADC_CGR) Gain for channel 1 */ -#define ADC_CGR_GAIN2 (0x3 << 4) /**< \brief (ADC_CGR) Gain for channel 2 */ -#define ADC_CGR_GAIN3 (0x3 << 6) /**< \brief (ADC_CGR) Gain for channel 3 */ -#define ADC_CGR_GAIN4 (0x3 << 8) /**< \brief (ADC_CGR) Gain for channel 4 */ -#define ADC_CGR_GAIN5 (0x3 << 10) /**< \brief (ADC_CGR) Gain for channel 5 */ -#define ADC_CGR_GAIN6 (0x3 << 12) /**< \brief (ADC_CGR) Gain for channel 6 */ -#define ADC_CGR_GAIN7 (0x3 << 14) /**< \brief (ADC_CGR) Gain for channel 7 */ -#define ADC_CGR_GAIN8 (0x3 << 16) /**< \brief (ADC_CGR) Gain for channel 8 */ -#define ADC_CGR_GAIN9 (0x3 << 18) /**< \brief (ADC_CGR) Gain for channel 9 */ -#define ADC_CGR_GAIN10 (0x3 << 20) /**< \brief (ADC_CGR) Gain for channel 10 */ -#define ADC_CGR_GAIN11 (0x3 << 22) /**< \brief (ADC_CGR) Gain for channel 11 */ -#define ADC_CGR_GAIN12 (0x3 << 24) /**< \brief (ADC_CGR) Gain for channel 12 */ -#define ADC_CGR_GAIN13 (0x3 << 26) /**< \brief (ADC_CGR) Gain for channel 13 */ -#define ADC_CGR_GAIN14 (0x3 << 28) /**< \brief (ADC_CGR) Gain for channel 14 */ -#define ADC_CGR_GAIN15 (0x3 << 30) /**< \brief (ADC_CGR) Gain for channel 15 */ -/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */ -#define ADC_COR_OFF0 (0x1 << 0) /**< \brief (ADC_COR) Offset for channel 0 */ -#define ADC_COR_OFF1 (0x1 << 1) /**< \brief (ADC_COR) Offset for channel 1 */ -#define ADC_COR_OFF2 (0x1 << 2) /**< \brief (ADC_COR) Offset for channel 2 */ -#define ADC_COR_OFF3 (0x1 << 3) /**< \brief (ADC_COR) Offset for channel 3 */ -#define ADC_COR_OFF4 (0x1 << 4) /**< \brief (ADC_COR) Offset for channel 4 */ -#define ADC_COR_OFF5 (0x1 << 5) /**< \brief (ADC_COR) Offset for channel 5 */ -#define ADC_COR_OFF6 (0x1 << 6) /**< \brief (ADC_COR) Offset for channel 6 */ -#define ADC_COR_OFF7 (0x1 << 7) /**< \brief (ADC_COR) Offset for channel 7 */ -#define ADC_COR_OFF8 (0x1 << 8) /**< \brief (ADC_COR) Offset for channel 8 */ -#define ADC_COR_OFF9 (0x1 << 9) /**< \brief (ADC_COR) Offset for channel 9 */ -#define ADC_COR_OFF10 (0x1 << 10) /**< \brief (ADC_COR) Offset for channel 10 */ -#define ADC_COR_OFF11 (0x1 << 11) /**< \brief (ADC_COR) Offset for channel 11 */ -#define ADC_COR_OFF12 (0x1 << 12) /**< \brief (ADC_COR) Offset for channel 12 */ -#define ADC_COR_OFF13 (0x1 << 13) /**< \brief (ADC_COR) Offset for channel 13 */ -#define ADC_COR_OFF14 (0x1 << 14) /**< \brief (ADC_COR) Offset for channel 14 */ -#define ADC_COR_OFF15 (0x1 << 15) /**< \brief (ADC_COR) Offset for channel 15 */ -#define ADC_COR_DIFF0 (0x1 << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */ -#define ADC_COR_DIFF1 (0x1 << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */ -#define ADC_COR_DIFF2 (0x1 << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */ -#define ADC_COR_DIFF3 (0x1 << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */ -#define ADC_COR_DIFF4 (0x1 << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */ -#define ADC_COR_DIFF5 (0x1 << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */ -#define ADC_COR_DIFF6 (0x1 << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */ -#define ADC_COR_DIFF7 (0x1 << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */ -#define ADC_COR_DIFF8 (0x1 << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */ -#define ADC_COR_DIFF9 (0x1 << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */ -#define ADC_COR_DIFF10 (0x1 << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */ -#define ADC_COR_DIFF11 (0x1 << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */ -#define ADC_COR_DIFF12 (0x1 << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */ -#define ADC_COR_DIFF13 (0x1 << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */ -#define ADC_COR_DIFF14 (0x1 << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */ -#define ADC_COR_DIFF15 (0x1 << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */ -/* -------- ADC_CDR0 : (ADC Offset: 0x50) Channel Data Register 0 -------- */ -#define ADC_CDR0_DATA (0x3ff << 0) /**< \brief (ADC_CDR0) Converted Data */ -/* -------- ADC_CDR1 : (ADC Offset: 0x54) Channel Data Register 1 -------- */ -#define ADC_CDR1_DATA (0x3ff << 0) /**< \brief (ADC_CDR1) Converted Data */ -/* -------- ADC_CDR2 : (ADC Offset: 0x58) Channel Data Register 2 -------- */ -#define ADC_CDR2_DATA (0x3ff << 0) /**< \brief (ADC_CDR2) Converted Data */ -/* -------- ADC_CDR3 : (ADC Offset: 0x5C) Channel Data Register 3 -------- */ -#define ADC_CDR3_DATA (0x3ff << 0) /**< \brief (ADC_CDR3) Converted Data */ -/* -------- ADC_CDR4 : (ADC Offset: 0x60) Channel Data Register 4 -------- */ -#define ADC_CDR4_DATA (0x3ff << 0) /**< \brief (ADC_CDR4) Converted Data */ -/* -------- ADC_CDR5 : (ADC Offset: 0x64) Channel Data Register 5 -------- */ -#define ADC_CDR5_DATA (0x3ff << 0) /**< \brief (ADC_CDR5) Converted Data */ -/* -------- ADC_CDR6 : (ADC Offset: 0x68) Channel Data Register 6 -------- */ -#define ADC_CDR6_DATA (0x3ff << 0) /**< \brief (ADC_CDR6) Converted Data */ -/* -------- ADC_CDR15 : (ADC Offset: 0x6C) Channel Data Register 15 -------- */ -#define ADC_CDR15_DATA (0x3ff << 0) /**< \brief (ADC_CDR15) Converted Data */ -/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */ -#define ADC_ACR_TSON (0x1 << 4) /**< \brief (ADC_ACR) Temperature Sensor On */ -#define ADC_ACR_IBCTL (0x3 << 8) /**< \brief (ADC_ACR) ADC Bias Current Control */ -/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */ -#define ADC_WPMR_WPEN (0x1 << 0) /**< \brief (ADC_WPMR) Write Protect Enable */ -#define ADC_WPMR_WPKEY (0xffffff << 8) /**< \brief (ADC_WPMR) Write Protect KEY */ -/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */ -#define ADC_WPSR_WPVS (0x1 << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */ -#define ADC_WPSR_WPVSRC (0xffff << 8) /**< \brief (ADC_WPSR) Write Protect Violation Source */ -/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */ -#define ADC_RPR_RXPTR (0xffffffff << 0) /**< \brief (ADC_RPR) Receive Pointer Register */ -/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */ -#define ADC_RCR_RXCTR (0xffff << 0) /**< \brief (ADC_RCR) Receive Counter Register */ -/* -------- ADC_TPR : (ADC Offset: 0x108) Transmit Pointer Register -------- */ -#define ADC_TPR_TXPTR (0xffffffff << 0) /**< \brief (ADC_TPR) Transmit Counter Register */ -/* -------- ADC_TCR : (ADC Offset: 0x10C) Transmit Counter Register -------- */ -#define ADC_TCR_TXCTR (0xffff << 0) /**< \brief (ADC_TCR) Transmit Counter Register */ -/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */ -#define ADC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (ADC_RNPR) Receive Next Pointer */ -/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */ -#define ADC_RNCR_RXNCTR (0xffff << 0) /**< \brief (ADC_RNCR) Receive Next Counter */ -/* -------- ADC_TNPR : (ADC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define ADC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (ADC_TNPR) Transmit Next Pointer */ -/* -------- ADC_TNCR : (ADC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define ADC_TNCR_TXNCTR (0xffff << 0) /**< \brief (ADC_TNCR) Transmit Counter Next */ -/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */ -#define ADC_PTCR_RXTEN (0x1 << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */ -#define ADC_PTCR_RXTDIS (0x1 << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */ -#define ADC_PTCR_TXTEN (0x1 << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */ -#define ADC_PTCR_TXTDIS (0x1 << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */ -/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */ -#define ADC_PTSR_RXTEN (0x1 << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */ -#define ADC_PTSR_TXTEN (0x1 << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Chip Identifier */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_CHIPID Chip Identifier */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Chipid hardware registers */ -typedef struct { - RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ - RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ -} Chipid; -#endif /* __ASSEMBLY__ */ -/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ -#define CHIPID_CIDR_VERSION (0x1f << 0) /**< \brief (CHIPID_CIDR) Version of the Device */ -#define CHIPID_CIDR_EPROC (0x7 << 5) /**< \brief (CHIPID_CIDR) Embedded Processor */ -#define CHIPID_CIDR_NVPSIZ (0xf << 8) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ -#define CHIPID_CIDR_NVPSIZ2 (0xf << 12) /**< \brief (CHIPID_CIDR) */ -#define CHIPID_CIDR_SRAMSIZ (0xf << 16) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ -#define CHIPID_CIDR_ARCH (0xff << 20) /**< \brief (CHIPID_CIDR) Architecture Identifier */ -#define CHIPID_CIDR_NVPTYP (0x7 << 28) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ -#define CHIPID_CIDR_EXT (0x1 << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ -/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ -#define CHIPID_EXID_EXID (0xffffffff << 0) /**< \brief (CHIPID_EXID) Chip ID Extension */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_CRCCU Cyclic Redundancy Check Calculation Unit */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Crccu hardware registers */ -typedef struct { - RwReg CRCCU_DSCR; /**< \brief (Crccu Offset: 0x00000000) CRCCU Descriptor Base Register */ - RwReg Reserved1[1]; - WoReg CRCCU_DMA_EN; /**< \brief (Crccu Offset: 0x00000008) CRCCU DMA Enable Register */ - WoReg CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x0000000C) CRCCU DMA Disable Register */ - RoReg CRCCU_DMA_SR; /**< \brief (Crccu Offset: 0x00000010) CRCCU DMA Status Register */ - WoReg CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x00000014) CRCCU DMA Interrupt Enable Register */ - WoReg CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x00000018) CRCCU DMA Interrupt Disable Register */ - RoReg CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register */ - RoReg CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x00000020) CRCCU DMA Interrupt Status Register */ - RwReg Reserved2[4]; - WoReg CRCCU_CR; /**< \brief (Crccu Offset: 0x00000034) CRCCU Control Register */ - RwReg CRCCU_MR; /**< \brief (Crccu Offset: 0x00000038) CRCCU Mode Register */ - RoReg CRCCU_SR; /**< \brief (Crccu Offset: 0x0000003C) CRCCU Status Register */ - WoReg CRCCU_IER; /**< \brief (Crccu Offset: 0x00000040) CRCCU Interrupt Enable Register */ - WoReg CRCCU_IDR; /**< \brief (Crccu Offset: 0x00000044) CRCCU Interrupt Disable Register */ - RoReg CRCCU_IMR; /**< \brief (Crccu Offset: 0x00000048) CRCCU Interrupt Mask Register */ - RoReg CRCCU_ISR; /**< \brief (Crccu Offset: 0x0000004C) CRCCU Interrupt Status Register */ -} Crccu; -#endif /* __ASSEMBLY__ */ -/* -------- CRCCU_DSCR : (CRCCU Offset: 0x00000000) CRCCU Descriptor Base Register -------- */ -#define CRCCU_DSCR_DSCR (0x7fffff << 9) /**< \brief (CRCCU_DSCR) Descriptor Base Address */ -/* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x00000008) CRCCU DMA Enable Register -------- */ -#define CRCCU_DMA_EN_DMAEN (0x1 << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable Register */ -/* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x0000000C) CRCCU DMA Disable Register -------- */ -#define CRCCU_DMA_DIS_DMADIS (0x1 << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable Register */ -/* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x00000010) CRCCU DMA Status Register -------- */ -#define CRCCU_DMA_SR_DMASR (0x1 << 0) /**< \brief (CRCCU_DMA_SR) DMA Status Register */ -/* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x00000014) CRCCU DMA Interrupt Enable Register -------- */ -#define CRCCU_DMA_IER_DMAIER (0x1 << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable register */ -/* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x00000018) CRCCU DMA Interrupt Disable Register -------- */ -#define CRCCU_DMA_IDR_DMAIDR (0x1 << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable register */ -/* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register -------- */ -#define CRCCU_DMA_IMR_DMAIMR (0x1 << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask Register */ -/* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x00000020) CRCCU DMA Interrupt Status Register -------- */ -#define CRCCU_DMA_ISR_DMAISR (0x1 << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status register */ -/* -------- CRCCU_CR : (CRCCU Offset: 0x00000034) CRCCU Control Register -------- */ -#define CRCCU_CR_RESET (0x1 << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */ -/* -------- CRCCU_MR : (CRCCU Offset: 0x00000038) CRCCU Mode Register -------- */ -#define CRCCU_MR_ENABLE (0x1 << 0) /**< \brief (CRCCU_MR) CRC Enable */ -#define CRCCU_MR_COMPARE (0x1 << 1) /**< \brief (CRCCU_MR) CRC Compare */ -#define CRCCU_MR_PTYPE (0x3 << 2) /**< \brief (CRCCU_MR) Primitive Polynomial */ -#define CRCCU_MR_PTYPE_CCIT8023 (0x0 << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */ -#define CRCCU_MR_PTYPE_CASTAGNOLI (0x1 << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */ -#define CRCCU_MR_PTYPE_CCIT16 (0x2 << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */ -#define CRCCU_MR_DIVIDER (0xf << 4) /**< \brief (CRCCU_MR) Request Divider */ -/* -------- CRCCU_SR : (CRCCU Offset: 0x0000003C) CRCCU Status Register -------- */ -#define CRCCU_SR_CRC (0xffffffff << 0) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */ -/* -------- CRCCU_IER : (CRCCU Offset: 0x00000040) CRCCU Interrupt Enable Register -------- */ -#define CRCCU_IER_ERRIER (0x1 << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */ -/* -------- CRCCU_IDR : (CRCCU Offset: 0x00000044) CRCCU Interrupt Disable Register -------- */ -#define CRCCU_IDR_ERRIDR (0x1 << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */ -/* -------- CRCCU_IMR : (CRCCU Offset: 0x00000048) CRCCU Interrupt Mask Register -------- */ -#define CRCCU_IMR_ERRIMR (0x1 << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */ -/* -------- CRCCU_ISR : (CRCCU Offset: 0x0000004C) CRCCU Interrupt Status Register -------- */ -#define CRCCU_ISR_ERRISR (0x1 << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_DACC Digital-to-Analog Converter Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Dacc hardware registers */ -typedef struct { - WoReg DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ - RwReg DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ - RwReg Reserved1[2]; - WoReg DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ - WoReg DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ - RoReg DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ - RwReg Reserved2[1]; - WoReg DACC_CDR; /**< \brief (Dacc Offset: 0x20) Conversion Data Register */ - WoReg DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ - WoReg DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ - RoReg DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ - RoReg DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ - RwReg Reserved3[24]; - RwReg DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ - RwReg Reserved4[19]; - RwReg DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */ - RoReg DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */ - RwReg Reserved5[5]; - RwReg DACC_RPR; /**< \brief (Dacc Offset: 0x100) Receive Pointer Register */ - RwReg DACC_RCR; /**< \brief (Dacc Offset: 0x104) Receive Counter Register */ - RwReg DACC_TPR; /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */ - RwReg DACC_TCR; /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */ - RwReg DACC_RNPR; /**< \brief (Dacc Offset: 0x110) Receive Next Pointer Register */ - RwReg DACC_RNCR; /**< \brief (Dacc Offset: 0x114) Receive Next Counter Register */ - RwReg DACC_TNPR; /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */ - RwReg DACC_TNCR; /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */ - WoReg DACC_PTCR; /**< \brief (Dacc Offset: 0x120) Transfer Control Register */ - RoReg DACC_PTSR; /**< \brief (Dacc Offset: 0x124) Transfer Status Register */ -} Dacc; -#endif /* __ASSEMBLY__ */ -/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ -#define DACC_CR_SWRST (0x1 << 0) /**< \brief (DACC_CR) Software Reset */ -/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ -#define DACC_MR_TRGEN (0x1 << 0) /**< \brief (DACC_MR) Trigger Enable */ -#define DACC_MR_TRGEN_DIS (0x0 << 0) // (DACC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. -#define DACC_MR_TRGEN_EN (0x1 << 0) // (DACC_MR) Hardware trigger selected by TRGSEL field is enabled. - -#define DACC_MR_TRGSEL (0x7 << 1) /**< \brief (DACC_MR) Trigger Selection */ -#define DACC_MR_TRGSEL_EXT_TRIG (0x0 << 1) // (DACC_MR) External trigger -#define DACC_MR_TRGSEL_TIOA_0 (0x1 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 0 -#define DACC_MR_TRGSEL_TIOA_1 (0x2 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 1 -#define DACC_MR_TRGSEL_TIOA_2 (0x3 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 2 -#define DACC_MR_TRGSEL_PWM_0 (0x4 << 1) // (DACC_MR) PWM Event Line 0 -#define DACC_MR_TRGSEL_PWM_1 (0x5 << 1) // (DACC_MR) PWM Event Line 1 -#define DACC_MR_WORD (0x1 << 4) /**< \brief (DACC_MR) Word Transfer */ -#define DACC_MR_WORD_HALF (0x0 << 4) /**< \brief (DACC_MR) Half-Word Transfer */ -#define DACC_MR_WORD_WORLD (0x1 << 4) /**< \brief (DACC_MR) Word Transfer */ -#define DACC_MR_SLEEP (0x1 << 5) /**< \brief (DACC_MR) Sleep Mode */ -#define DACC_MR_SLEEP_NORMAL (0x0 << 5) // (DACC_MR) Normal Mode -#define DACC_MR_SLEEP_SLEEP (0x1 << 5) // (DACC_MR) Sleep Modes -#define DACC_MR_FASTWKUP (0x1 << 6) /**< \brief (DACC_MR) Fast Wake up Mode */ -#define DACC_MR_REFRESH (0xff << 8) /**< \brief (DACC_MR) Refresh Period */ -#define DACC_MR_USER_SEL (0x3 << 16) /**< \brief (DACC_MR) User Channel Selection */ -#define DACC_MR_USER_SEL_0 (0x0 << 16) /**< \brief (DACC_MR) User Channel Selection */ -#define DACC_MR_USER_SEL_1 (0x1 << 16) /**< \brief (DACC_MR) User Channel Selection */ -#define DACC_MR_TAG (0x1 << 20) /**< \brief (DACC_MR) Tag Selection Mode */ -#define DACC_MR_MAXS (0x1 << 21) /**< \brief (DACC_MR) Max Speed Mode */ -#define DACC_MR_STARTUP (0x3f << 24) /**< \brief (DACC_MR) Startup Time Selection */ -/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ -#define DACC_CHER_CH0 (0x1 << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ -#define DACC_CHER_CH1 (0x1 << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ -#define DACC_CHER_CH2 (0x1 << 2) /**< \brief (DACC_CHER) Channel 2 Enable */ -/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ -#define DACC_CHDR_CH0 (0x1 << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ -#define DACC_CHDR_CH1 (0x1 << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ -#define DACC_CHDR_CH2 (0x1 << 2) /**< \brief (DACC_CHDR) Channel 2 Disable */ -/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ -#define DACC_CHSR_CH0 (0x1 << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ -#define DACC_CHSR_CH1 (0x1 << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ -#define DACC_CHSR_CH2 (0x1 << 2) /**< \brief (DACC_CHSR) Channel 2 Status */ -/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */ -#define DACC_CDR_DATA (0xffffffff << 0) /**< \brief (DACC_CDR) Data to Convert */ -/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ -#define DACC_IER_TXRDY (0x1 << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */ -#define DACC_IER_EOC (0x1 << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */ -#define DACC_IER_ENDTX (0x1 << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */ -#define DACC_IER_TXBUFE (0x1 << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */ -/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ -#define DACC_IDR_TXRDY (0x1 << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */ -#define DACC_IDR_EOC (0x1 << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */ -#define DACC_IDR_ENDTX (0x1 << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */ -#define DACC_IDR_TXBUFE (0x1 << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */ -/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ -#define DACC_IMR_TXRDY (0x1 << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */ -#define DACC_IMR_EOC (0x1 << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */ -#define DACC_IMR_ENDTX (0x1 << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */ -#define DACC_IMR_TXBUFE (0x1 << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */ -/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ -#define DACC_ISR_TXRDY (0x1 << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */ -#define DACC_ISR_EOC (0x1 << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */ -#define DACC_ISR_ENDTX (0x1 << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */ -#define DACC_ISR_TXBUFE (0x1 << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */ -/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ -#define DACC_ACR_IBCTLCH0 (0x3 << 0) /**< \brief (DACC_ACR) Analog Output Current Control */ -#define DACC_ACR_IBCTLCH1 (0x3 << 2) /**< \brief (DACC_ACR) Analog Output Current Control */ -#define DACC_ACR_IBCTLDACCORE (0x3 << 8) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */ -/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */ -#define DACC_WPMR_WPEN (0x1 << 0) /**< \brief (DACC_WPMR) Write Protect Enable */ -#define DACC_WPMR_WPKEY (0xffffff << 8) /**< \brief (DACC_WPMR) Write Protect KEY */ -/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */ -#define DACC_WPSR_WPROTERR (0x1 << 0) /**< \brief (DACC_WPSR) Write protection error */ -#define DACC_WPSR_WPROTADDR (0xff << 8) /**< \brief (DACC_WPSR) Write protection error address */ -/* -------- DACC_RPR : (DACC Offset: 0x100) Receive Pointer Register -------- */ -#define DACC_RPR_RXPTR (0xffffffff << 0) /**< \brief (DACC_RPR) Receive Pointer Register */ -/* -------- DACC_RCR : (DACC Offset: 0x104) Receive Counter Register -------- */ -#define DACC_RCR_RXCTR (0xffff << 0) /**< \brief (DACC_RCR) Receive Counter Register */ -/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */ -#define DACC_TPR_TXPTR (0xffffffff << 0) /**< \brief (DACC_TPR) Transmit Counter Register */ -/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */ -#define DACC_TCR_TXCTR (0xffff << 0) /**< \brief (DACC_TCR) Transmit Counter Register */ -/* -------- DACC_RNPR : (DACC Offset: 0x110) Receive Next Pointer Register -------- */ -#define DACC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (DACC_RNPR) Receive Next Pointer */ -/* -------- DACC_RNCR : (DACC Offset: 0x114) Receive Next Counter Register -------- */ -#define DACC_RNCR_RXNCTR (0xffff << 0) /**< \brief (DACC_RNCR) Receive Next Counter */ -/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define DACC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (DACC_TNPR) Transmit Next Pointer */ -/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define DACC_TNCR_TXNCTR (0xffff << 0) /**< \brief (DACC_TNCR) Transmit Counter Next */ -/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */ -#define DACC_PTCR_RXTEN (0x1 << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */ -#define DACC_PTCR_RXTDIS (0x1 << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */ -#define DACC_PTCR_TXTEN (0x1 << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */ -#define DACC_PTCR_TXTDIS (0x1 << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */ -/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */ -#define DACC_PTSR_RXTEN (0x1 << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */ -#define DACC_PTSR_TXTEN (0x1 << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_EFC Embedded Flash Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Efc hardware registers */ -typedef struct { - RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ - WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ - RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ - RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ -} Efc; -#endif /* __ASSEMBLY__ */ -/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ -#define EEFC_FMR_FRDY (0x1 << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */ -#define EEFC_FMR_FWS (0xf << 8) /**< \brief (EEFC_FMR) Flash Wait State */ -#define EEFC_FMR_FAM (0x1 << 24) /**< \brief (EEFC_FMR) Flash Access Mode */ -/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ -#define EEFC_FCR_FCMD (0xff << 0) /**< \brief (EEFC_FCR) Flash Command */ -#define EEFC_FCR_FARG (0xffff << 8) /**< \brief (EEFC_FCR) Flash Command Argument */ -#define EEFC_FCR_FKEY (0xff << 24) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ -/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ -#define EEFC_FSR_FRDY (0x1 << 0) /**< \brief (EEFC_FSR) Flash Ready Status */ -#define EEFC_FSR_FCMDE (0x1 << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */ -#define EEFC_FSR_FLOCKE (0x1 << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */ -/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ -#define EEFC_FRR_FVALUE (0xffffffff << 0) /**< \brief (EEFC_FRR) Flash Result Value */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_GPBR General Purpose Backup Register */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Gpbr hardware registers */ -typedef struct { - RwReg SYS_GPBR0; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register 0 */ - RwReg SYS_GPBR1; /**< \brief (Gpbr Offset: 0x4) General Purpose Backup Register 1 */ - RwReg SYS_GPBR2; /**< \brief (Gpbr Offset: 0x8) General Purpose Backup Register 2 */ - RwReg SYS_GPBR3; /**< \brief (Gpbr Offset: 0xC) General Purpose Backup Register 3 */ -} Gpbr; -#endif /* __ASSEMBLY__ */ -/* -------- SYS_GPBR0 : (GPBR Offset: 0x0) General Purpose Backup Register 0 -------- */ -#define SYS_GPBR0_GPBR_VALUE0 (0xffffffff << 0) /**< \brief (SYS_GPBR0) Value of GPBR x */ -/* -------- SYS_GPBR1 : (GPBR Offset: 0x4) General Purpose Backup Register 1 -------- */ -#define SYS_GPBR1_GPBR_VALUE1 (0xffffffff << 0) /**< \brief (SYS_GPBR1) Value of GPBR x */ -/* -------- SYS_GPBR2 : (GPBR Offset: 0x8) General Purpose Backup Register 2 -------- */ -#define SYS_GPBR2_GPBR_VALUE2 (0xffffffff << 0) /**< \brief (SYS_GPBR2) Value of GPBR x */ -/* -------- SYS_GPBR3 : (GPBR Offset: 0xC) General Purpose Backup Register 3 -------- */ -#define SYS_GPBR3_GPBR_VALUE3 (0xffffffff << 0) /**< \brief (SYS_GPBR3) Value of GPBR x */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_HSMCI High Speed MultiMedia Card Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Hsmci hardware registers */ -typedef struct { - WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ - RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ - RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ - RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ - RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ - WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ - RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ - RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ - RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ - RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ - WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ - RwReg Reserved1[2]; - RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ - WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ - WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ - RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ - RwReg Reserved2[1]; - RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ - RwReg Reserved3[35]; - RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ - RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ - RwReg Reserved4[5]; - RwReg HSMCI_RPR; /**< \brief (Hsmci Offset: 0x100) Receive Pointer Register */ - RwReg HSMCI_RCR; /**< \brief (Hsmci Offset: 0x104) Receive Counter Register */ - RwReg HSMCI_TPR; /**< \brief (Hsmci Offset: 0x108) Transmit Pointer Register */ - RwReg HSMCI_TCR; /**< \brief (Hsmci Offset: 0x10C) Transmit Counter Register */ - RwReg HSMCI_RNPR; /**< \brief (Hsmci Offset: 0x110) Receive Next Pointer Register */ - RwReg HSMCI_RNCR; /**< \brief (Hsmci Offset: 0x114) Receive Next Counter Register */ - RwReg HSMCI_TNPR; /**< \brief (Hsmci Offset: 0x118) Transmit Next Pointer Register */ - RwReg HSMCI_TNCR; /**< \brief (Hsmci Offset: 0x11C) Transmit Next Counter Register */ - WoReg HSMCI_PTCR; /**< \brief (Hsmci Offset: 0x120) Transfer Control Register */ - RoReg HSMCI_PTSR; /**< \brief (Hsmci Offset: 0x124) Transfer Status Register */ -} Hsmci; -#endif /* __ASSEMBLY__ */ -/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ -#define HSMCI_CR_MCIEN (0x1 << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ -#define HSMCI_CR_MCIDIS (0x1 << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ -#define HSMCI_CR_PWSEN (0x1 << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ -#define HSMCI_CR_PWSDIS (0x1 << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ -#define HSMCI_CR_SWRST (0x1 << 7) /**< \brief (HSMCI_CR) Software Reset */ -/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ -#define HSMCI_MR_CLKDIV (0xff << 0) /**< \brief (HSMCI_MR) Clock Divider */ -#define HSMCI_MR_PWSDIV (0x7 << 8) /**< \brief (HSMCI_MR) Power Saving Divider */ -#define HSMCI_MR_RDPROOF (0x1 << 11) /**< \brief (HSMCI_MR) */ -#define HSMCI_MR_WRPROOF (0x1 << 12) /**< \brief (HSMCI_MR) */ -#define HSMCI_MR_FBYTE (0x1 << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ -#define HSMCI_MR_PADV (0x1 << 14) /**< \brief (HSMCI_MR) Padding Value */ -#define HSMCI_MR_PDCMODE (0x1 << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */ -#define HSMCI_MR_BLKLEN (0xffff << 16) /**< \brief (HSMCI_MR) Data Block Length */ -/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ -#define HSMCI_DTOR_DTOCYC (0xf << 0) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ -#define HSMCI_DTOR_DTOMUL (0x7 << 4) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ -/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ -#define HSMCI_SDCR_SDCSEL (0x3 << 0) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ -#define HSMCI_SDCR_SDCBUS (0x3 << 6) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ -/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ -#define HSMCI_ARGR_ARG (0xffffffff << 0) /**< \brief (HSMCI_ARGR) Command Argument */ -/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ -#define HSMCI_CMDR_CMDNB (0x3f << 0) /**< \brief (HSMCI_CMDR) Command Number */ -#define HSMCI_CMDR_RSPTYP (0x3 << 6) /**< \brief (HSMCI_CMDR) Response Type */ -#define HSMCI_CMDR_SPCMD (0x7 << 8) /**< \brief (HSMCI_CMDR) Special Command */ -#define HSMCI_CMDR_OPDCMD (0x1 << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ -#define HSMCI_CMDR_MAXLAT (0x1 << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ -#define HSMCI_CMDR_TRCMD (0x3 << 16) /**< \brief (HSMCI_CMDR) Transfer Command */ -#define HSMCI_CMDR_TRDIR (0x1 << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ -#define HSMCI_CMDR_TRTYP (0x7 << 19) /**< \brief (HSMCI_CMDR) Transfer Type */ -#define HSMCI_CMDR_IOSPCMD (0x3 << 24) /**< \brief (HSMCI_CMDR) SDIO Special Command */ -#define HSMCI_CMDR_ATACS (0x1 << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ -#define HSMCI_CMDR_BOOT_ACK (0x1 << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */ -/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ -#define HSMCI_BLKR_BCNT (0xffff << 0) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ -#define HSMCI_BLKR_BLKLEN (0xffff << 16) /**< \brief (HSMCI_BLKR) Data Block Length */ -/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ -#define HSMCI_CSTOR_CSTOCYC (0xf << 0) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ -#define HSMCI_CSTOR_CSTOMUL (0x7 << 4) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ -/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ -#define HSMCI_RSPR_RSP (0xffffffff << 0) /**< \brief (HSMCI_RSPR[4]) Response */ -/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ -#define HSMCI_RDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_RDR) Data to Read */ -/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ -#define HSMCI_TDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_TDR) Data to Write */ -/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ -#define HSMCI_SR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_SR) Command Ready */ -#define HSMCI_SR_RXRDY (0x1 << 1) /**< \brief (HSMCI_SR) Receiver Ready */ -#define HSMCI_SR_TXRDY (0x1 << 2) /**< \brief (HSMCI_SR) Transmit Ready */ -#define HSMCI_SR_BLKE (0x1 << 3) /**< \brief (HSMCI_SR) Data Block Ended */ -#define HSMCI_SR_DTIP (0x1 << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */ -#define HSMCI_SR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ -#define HSMCI_SR_ENDRX (0x1 << 6) /**< \brief (HSMCI_SR) End of RX Buffer */ -#define HSMCI_SR_ENDTX (0x1 << 7) /**< \brief (HSMCI_SR) End of TX Buffer */ -#define HSMCI_SR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */ -#define HSMCI_SR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ -#define HSMCI_SR_CSRCV (0x1 << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */ -#define HSMCI_SR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_SR) RX Buffer Full */ -#define HSMCI_SR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_SR) TX Buffer Empty */ -#define HSMCI_SR_RINDE (0x1 << 16) /**< \brief (HSMCI_SR) Response Index Error */ -#define HSMCI_SR_RDIRE (0x1 << 17) /**< \brief (HSMCI_SR) Response Direction Error */ -#define HSMCI_SR_RCRCE (0x1 << 18) /**< \brief (HSMCI_SR) Response CRC Error */ -#define HSMCI_SR_RENDE (0x1 << 19) /**< \brief (HSMCI_SR) Response End Bit Error */ -#define HSMCI_SR_RTOE (0x1 << 20) /**< \brief (HSMCI_SR) Response Time-out Error */ -#define HSMCI_SR_DCRCE (0x1 << 21) /**< \brief (HSMCI_SR) Data CRC Error */ -#define HSMCI_SR_DTOE (0x1 << 22) /**< \brief (HSMCI_SR) Data Time-out Error */ -#define HSMCI_SR_CSTOE (0x1 << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */ -#define HSMCI_SR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ -#define HSMCI_SR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ -#define HSMCI_SR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */ -#define HSMCI_SR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */ -#define HSMCI_SR_OVRE (0x1 << 30) /**< \brief (HSMCI_SR) Overrun */ -#define HSMCI_SR_UNRE (0x1 << 31) /**< \brief (HSMCI_SR) Underrun */ -/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ -#define HSMCI_IER_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ -#define HSMCI_IER_RXRDY (0x1 << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ -#define HSMCI_IER_TXRDY (0x1 << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ -#define HSMCI_IER_BLKE (0x1 << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ -#define HSMCI_IER_DTIP (0x1 << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ -#define HSMCI_IER_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ -#define HSMCI_IER_ENDRX (0x1 << 6) /**< \brief (HSMCI_IER) End of Receive Buffer Interrupt Enable */ -#define HSMCI_IER_ENDTX (0x1 << 7) /**< \brief (HSMCI_IER) End of Transmit Buffer Interrupt Enable */ -#define HSMCI_IER_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */ -#define HSMCI_IER_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ -#define HSMCI_IER_CSRCV (0x1 << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ -#define HSMCI_IER_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IER) Receive Buffer Full Interrupt Enable */ -#define HSMCI_IER_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IER) Transmit Buffer Empty Interrupt Enable */ -#define HSMCI_IER_RINDE (0x1 << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ -#define HSMCI_IER_RDIRE (0x1 << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ -#define HSMCI_IER_RCRCE (0x1 << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ -#define HSMCI_IER_RENDE (0x1 << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ -#define HSMCI_IER_RTOE (0x1 << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ -#define HSMCI_IER_DCRCE (0x1 << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ -#define HSMCI_IER_DTOE (0x1 << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ -#define HSMCI_IER_CSTOE (0x1 << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ -#define HSMCI_IER_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ -#define HSMCI_IER_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ -#define HSMCI_IER_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ -#define HSMCI_IER_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ -#define HSMCI_IER_OVRE (0x1 << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ -#define HSMCI_IER_UNRE (0x1 << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ -/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ -#define HSMCI_IDR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ -#define HSMCI_IDR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ -#define HSMCI_IDR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ -#define HSMCI_IDR_BLKE (0x1 << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ -#define HSMCI_IDR_DTIP (0x1 << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ -#define HSMCI_IDR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ -#define HSMCI_IDR_ENDRX (0x1 << 6) /**< \brief (HSMCI_IDR) End of Receive Buffer Interrupt Disable */ -#define HSMCI_IDR_ENDTX (0x1 << 7) /**< \brief (HSMCI_IDR) End of Transmit Buffer Interrupt Disable */ -#define HSMCI_IDR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */ -#define HSMCI_IDR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ -#define HSMCI_IDR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ -#define HSMCI_IDR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IDR) Receive Buffer Full Interrupt Disable */ -#define HSMCI_IDR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IDR) Transmit Buffer Empty Interrupt Disable */ -#define HSMCI_IDR_RINDE (0x1 << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ -#define HSMCI_IDR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ -#define HSMCI_IDR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ -#define HSMCI_IDR_RENDE (0x1 << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ -#define HSMCI_IDR_RTOE (0x1 << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ -#define HSMCI_IDR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ -#define HSMCI_IDR_DTOE (0x1 << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ -#define HSMCI_IDR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ -#define HSMCI_IDR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ -#define HSMCI_IDR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ -#define HSMCI_IDR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ -#define HSMCI_IDR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ -#define HSMCI_IDR_OVRE (0x1 << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ -#define HSMCI_IDR_UNRE (0x1 << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ -/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ -#define HSMCI_IMR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ -#define HSMCI_IMR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ -#define HSMCI_IMR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ -#define HSMCI_IMR_BLKE (0x1 << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ -#define HSMCI_IMR_DTIP (0x1 << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ -#define HSMCI_IMR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ -#define HSMCI_IMR_ENDRX (0x1 << 6) /**< \brief (HSMCI_IMR) End of Receive Buffer Interrupt Mask */ -#define HSMCI_IMR_ENDTX (0x1 << 7) /**< \brief (HSMCI_IMR) End of Transmit Buffer Interrupt Mask */ -#define HSMCI_IMR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */ -#define HSMCI_IMR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ -#define HSMCI_IMR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ -#define HSMCI_IMR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IMR) Receive Buffer Full Interrupt Mask */ -#define HSMCI_IMR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IMR) Transmit Buffer Empty Interrupt Mask */ -#define HSMCI_IMR_RINDE (0x1 << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ -#define HSMCI_IMR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ -#define HSMCI_IMR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ -#define HSMCI_IMR_RENDE (0x1 << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ -#define HSMCI_IMR_RTOE (0x1 << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ -#define HSMCI_IMR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ -#define HSMCI_IMR_DTOE (0x1 << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ -#define HSMCI_IMR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ -#define HSMCI_IMR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ -#define HSMCI_IMR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ -#define HSMCI_IMR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ -#define HSMCI_IMR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ -#define HSMCI_IMR_OVRE (0x1 << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ -#define HSMCI_IMR_UNRE (0x1 << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ -/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ -#define HSMCI_CFG_FIFOMODE (0x1 << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ -#define HSMCI_CFG_FERRCTRL (0x1 << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ -#define HSMCI_CFG_HSMODE (0x1 << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ -#define HSMCI_CFG_LSYNC (0x1 << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ -/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ -#define HSMCI_WPMR_WP_EN (0x1 << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */ -#define HSMCI_WPMR_WP_KEY (0xffffff << 8) /**< \brief (HSMCI_WPMR) Write Protection Key password */ -/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ -#define HSMCI_WPSR_WP_VS (0xf << 0) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ -#define HSMCI_WPSR_WP_VSRC (0xffff << 8) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */ -/* -------- HSMCI_RPR : (HSMCI Offset: 0x100) Receive Pointer Register -------- */ -#define HSMCI_RPR_RXPTR (0xffffffff << 0) /**< \brief (HSMCI_RPR) Receive Pointer Register */ -/* -------- HSMCI_RCR : (HSMCI Offset: 0x104) Receive Counter Register -------- */ -#define HSMCI_RCR_RXCTR (0xffff << 0) /**< \brief (HSMCI_RCR) Receive Counter Register */ -/* -------- HSMCI_TPR : (HSMCI Offset: 0x108) Transmit Pointer Register -------- */ -#define HSMCI_TPR_TXPTR (0xffffffff << 0) /**< \brief (HSMCI_TPR) Transmit Counter Register */ -/* -------- HSMCI_TCR : (HSMCI Offset: 0x10C) Transmit Counter Register -------- */ -#define HSMCI_TCR_TXCTR (0xffff << 0) /**< \brief (HSMCI_TCR) Transmit Counter Register */ -/* -------- HSMCI_RNPR : (HSMCI Offset: 0x110) Receive Next Pointer Register -------- */ -#define HSMCI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (HSMCI_RNPR) Receive Next Pointer */ -/* -------- HSMCI_RNCR : (HSMCI Offset: 0x114) Receive Next Counter Register -------- */ -#define HSMCI_RNCR_RXNCTR (0xffff << 0) /**< \brief (HSMCI_RNCR) Receive Next Counter */ -/* -------- HSMCI_TNPR : (HSMCI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define HSMCI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (HSMCI_TNPR) Transmit Next Pointer */ -/* -------- HSMCI_TNCR : (HSMCI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define HSMCI_TNCR_TXNCTR (0xffff << 0) /**< \brief (HSMCI_TNCR) Transmit Counter Next */ -/* -------- HSMCI_PTCR : (HSMCI Offset: 0x120) Transfer Control Register -------- */ -#define HSMCI_PTCR_RXTEN (0x1 << 0) /**< \brief (HSMCI_PTCR) Receiver Transfer Enable */ -#define HSMCI_PTCR_RXTDIS (0x1 << 1) /**< \brief (HSMCI_PTCR) Receiver Transfer Disable */ -#define HSMCI_PTCR_TXTEN (0x1 << 8) /**< \brief (HSMCI_PTCR) Transmitter Transfer Enable */ -#define HSMCI_PTCR_TXTDIS (0x1 << 9) /**< \brief (HSMCI_PTCR) Transmitter Transfer Disable */ -/* -------- HSMCI_PTSR : (HSMCI Offset: 0x124) Transfer Status Register -------- */ -#define HSMCI_PTSR_RXTEN (0x1 << 0) /**< \brief (HSMCI_PTSR) Receiver Transfer Enable */ -#define HSMCI_PTSR_TXTEN (0x1 << 8) /**< \brief (HSMCI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_MATRIX AHB Bus Matrix */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Matrix hardware registers */ -typedef struct { - RwReg MATRIX_MCFG[4]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */ - RwReg Reserved1[12]; - RwReg MATRIX_SCFG[5]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ - RwReg Reserved2[11]; - RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */ - RwReg Reserved3[1]; - RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */ - RwReg Reserved4[1]; - RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */ - RwReg Reserved5[1]; - RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */ - RwReg Reserved6[1]; - RwReg MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */ - RwReg Reserved7[28]; - RwReg CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System IO Configuration register */ - RwReg Reserved8[1]; - RwReg CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register */ - RwReg Reserved9[49]; - RwReg MATRIX_WPMR; /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */ - RoReg MATRIX_WPSR; /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */ -} Matrix; -#endif /* __ASSEMBLY__ */ -/* -------- MATRIX_MCFG[4] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */ -#define MATRIX_MCFG_ULBT (0x7 << 0) /**< \brief (MATRIX_MCFG[4]) Undefined Length Burst Type */ -/* -------- MATRIX_SCFG[5] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ -#define MATRIX_SCFG_SLOT_CYCLE (0xff << 0) /**< \brief (MATRIX_SCFG[5]) Maximum Number of Allowed Cycles for a Burst */ -#define MATRIX_SCFG_DEFMSTR_TYPE (0x3 << 16) /**< \brief (MATRIX_SCFG[5]) Default Master Type */ -#define MATRIX_SCFG_FIXED_DEFMSTR (0x7 << 18) /**< \brief (MATRIX_SCFG[5]) Fixed Default Master */ -#define MATRIX_SCFG_ARBT (0x3 << 24) /**< \brief (MATRIX_SCFG[5]) Arbitration Type */ -/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */ -#define MATRIX_PRAS0_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS0) Master 0 Priority */ -#define MATRIX_PRAS0_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS0) Master 1 Priority */ -#define MATRIX_PRAS0_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS0) Master 2 Priority */ -#define MATRIX_PRAS0_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS0) Master 3 Priority */ -#define MATRIX_PRAS0_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS0) Master 4 Priority */ -/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */ -#define MATRIX_PRAS1_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS1) Master 0 Priority */ -#define MATRIX_PRAS1_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS1) Master 1 Priority */ -#define MATRIX_PRAS1_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS1) Master 2 Priority */ -#define MATRIX_PRAS1_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS1) Master 3 Priority */ -#define MATRIX_PRAS1_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS1) Master 4 Priority */ -/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */ -#define MATRIX_PRAS2_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS2) Master 0 Priority */ -#define MATRIX_PRAS2_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS2) Master 1 Priority */ -#define MATRIX_PRAS2_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS2) Master 2 Priority */ -#define MATRIX_PRAS2_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS2) Master 3 Priority */ -#define MATRIX_PRAS2_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS2) Master 4 Priority */ -/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */ -#define MATRIX_PRAS3_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS3) Master 0 Priority */ -#define MATRIX_PRAS3_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS3) Master 1 Priority */ -#define MATRIX_PRAS3_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS3) Master 2 Priority */ -#define MATRIX_PRAS3_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS3) Master 3 Priority */ -#define MATRIX_PRAS3_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS3) Master 4 Priority */ -/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */ -#define MATRIX_PRAS4_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS4) Master 0 Priority */ -#define MATRIX_PRAS4_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS4) Master 1 Priority */ -#define MATRIX_PRAS4_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS4) Master 2 Priority */ -#define MATRIX_PRAS4_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS4) Master 3 Priority */ -#define MATRIX_PRAS4_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS4) Master 4 Priority */ -/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System IO Configuration register -------- */ -#define CCFG_SYSIO_SYSIO4 (0x1 << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */ -#define CCFG_SYSIO_SYSIO5 (0x1 << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ -#define CCFG_SYSIO_SYSIO6 (0x1 << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ -#define CCFG_SYSIO_SYSIO7 (0x1 << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ -#define CCFG_SYSIO_SYSIO10 (0x1 << 10) /**< \brief (CCFG_SYSIO) PB10 or DDM Assignment */ -#define CCFG_SYSIO_SYSIO11 (0x1 << 11) /**< \brief (CCFG_SYSIO) PB11 or DDP Assignment */ -#define CCFG_SYSIO_SYSIO12 (0x1 << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */ -/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register -------- */ -#define CCFG_SMCNFCS_SMC_NFCS0 (0x1 << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */ -#define CCFG_SMCNFCS_SMC_NFCS1 (0x1 << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */ -#define CCFG_SMCNFCS_SMC_NFCS2 (0x1 << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */ -#define CCFG_SMCNFCS_SMC_NFCS3 (0x1 << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */ -/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */ -#define MATRIX_WPMR_WPEN (0x1 << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */ -#define MATRIX_WPMR_WPKEY (0xffffff << 8) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */ -/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */ -#define MATRIX_WPSR_WPVS (0x1 << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */ -#define MATRIX_WPSR_WPVSRC (0xffff << 8) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PDC Peripheral DMA Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pdc hardware registers */ -typedef struct { - RwReg Reserved1[64]; - RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x100) Receive Pointer Register */ - RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x104) Receive Counter Register */ - RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x108) Transmit Pointer Register */ - RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0x10C) Transmit Counter Register */ - RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x110) Receive Next Pointer Register */ - RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x114) Receive Next Counter Register */ - RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x118) Transmit Next Pointer Register */ - RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x11C) Transmit Next Counter Register */ - WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x120) Transfer Control Register */ - RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x124) Transfer Status Register */ -} Pdc; -#endif /* __ASSEMBLY__ */ -/* -------- PERIPH_RPR : (PDC Offset: 0x100) Receive Pointer Register -------- */ -#define PERIPH_RPR_RXPTR (0xffffffff << 0) /**< \brief (PERIPH_RPR) Receive Pointer Register */ -/* -------- PERIPH_RCR : (PDC Offset: 0x104) Receive Counter Register -------- */ -#define PERIPH_RCR_RXCTR (0xffff << 0) /**< \brief (PERIPH_RCR) Receive Counter Register */ -/* -------- PERIPH_TPR : (PDC Offset: 0x108) Transmit Pointer Register -------- */ -#define PERIPH_TPR_TXPTR (0xffffffff << 0) /**< \brief (PERIPH_TPR) Transmit Counter Register */ -/* -------- PERIPH_TCR : (PDC Offset: 0x10C) Transmit Counter Register -------- */ -#define PERIPH_TCR_TXCTR (0xffff << 0) /**< \brief (PERIPH_TCR) Transmit Counter Register */ -/* -------- PERIPH_RNPR : (PDC Offset: 0x110) Receive Next Pointer Register -------- */ -#define PERIPH_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PERIPH_RNPR) Receive Next Pointer */ -/* -------- PERIPH_RNCR : (PDC Offset: 0x114) Receive Next Counter Register -------- */ -#define PERIPH_RNCR_RXNCTR (0xffff << 0) /**< \brief (PERIPH_RNCR) Receive Next Counter */ -/* -------- PERIPH_TNPR : (PDC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define PERIPH_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */ -/* -------- PERIPH_TNCR : (PDC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define PERIPH_TNCR_TXNCTR (0xffff << 0) /**< \brief (PERIPH_TNCR) Transmit Counter Next */ -/* -------- PERIPH_PTCR : (PDC Offset: 0x120) Transfer Control Register -------- */ -#define PERIPH_PTCR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */ -#define PERIPH_PTCR_RXTDIS (0x1 << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */ -#define PERIPH_PTCR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */ -#define PERIPH_PTCR_TXTDIS (0x1 << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */ -/* -------- PERIPH_PTSR : (PDC Offset: 0x124) Transfer Status Register -------- */ -#define PERIPH_PTSR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */ -#define PERIPH_PTSR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Parallel Input/Output */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PIO Parallel Input/Output */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pio hardware registers */ -typedef struct { - WoReg PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ - WoReg PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ - RoReg PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ - RwReg Reserved1[1]; - WoReg PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ - WoReg PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ - RoReg PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ - RwReg Reserved2[1]; - WoReg PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ - WoReg PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ - RoReg PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ - RwReg Reserved3[1]; - WoReg PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ - WoReg PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ - RwReg PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ - RoReg PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ - WoReg PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ - WoReg PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ - RoReg PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ - RoReg PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ - WoReg PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ - WoReg PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ - RoReg PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ - RwReg Reserved4[1]; - WoReg PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ - WoReg PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ - RoReg PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ - RwReg Reserved5[1]; - RwReg PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ - RwReg Reserved6[2]; - WoReg PIO_SCIFSR; /**< \brief (Pio Offset: 0x0080) System Clock Glitch Input Filter Select Register */ - WoReg PIO_DIFSR; /**< \brief (Pio Offset: 0x0084) Debouncing Input Filter Select Register */ - RoReg PIO_IFDGSR; /**< \brief (Pio Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register */ - RwReg PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ - WoReg PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ - WoReg PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ - RoReg PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ - RwReg Reserved7[1]; - WoReg PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ - WoReg PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ - RoReg PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ - RwReg Reserved8[1]; - WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ - WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */ - RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ - RwReg Reserved9[1]; - WoReg PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ - WoReg PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ - RoReg PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ - RwReg Reserved10[1]; - WoReg PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */ - WoReg PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */ - RoReg PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ - RwReg Reserved11[1]; - RoReg PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ - RwReg PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */ - RoReg PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */ - RwReg Reserved12[5]; - RwReg PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ - RwReg Reserved13[19]; - RwReg PIO_PCMR; /**< \brief (Pio Offset: 0x150) Parallel Capture Mode Register */ - WoReg PIO_PCIER; /**< \brief (Pio Offset: 0x154) Parallel Capture Interrupt Enable Register */ - WoReg PIO_PCIDR; /**< \brief (Pio Offset: 0x158) Parallel Capture Interrupt Disable Register */ - RoReg PIO_PCIMR; /**< \brief (Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register */ - RoReg PIO_PCISR; /**< \brief (Pio Offset: 0x160) Parallel Capture Interrupt Status Register */ - RoReg PIO_PCRHR; /**< \brief (Pio Offset: 0x164) Parallel Capture Reception Holding Register */ - RwReg Reserved14[38]; -} Pio; -#endif /* __ASSEMBLY__ */ -/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ -#define PIO_PER_P0 (0x1 << 0) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P1 (0x1 << 1) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P2 (0x1 << 2) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P3 (0x1 << 3) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P4 (0x1 << 4) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P5 (0x1 << 5) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P6 (0x1 << 6) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P7 (0x1 << 7) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P8 (0x1 << 8) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P9 (0x1 << 9) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P10 (0x1 << 10) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P11 (0x1 << 11) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P12 (0x1 << 12) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P13 (0x1 << 13) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P14 (0x1 << 14) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P15 (0x1 << 15) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P16 (0x1 << 16) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P17 (0x1 << 17) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P18 (0x1 << 18) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P19 (0x1 << 19) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P20 (0x1 << 20) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P21 (0x1 << 21) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P22 (0x1 << 22) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P23 (0x1 << 23) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P24 (0x1 << 24) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P25 (0x1 << 25) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P26 (0x1 << 26) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P27 (0x1 << 27) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P28 (0x1 << 28) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P29 (0x1 << 29) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P30 (0x1 << 30) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P31 (0x1 << 31) /**< \brief (PIO_PER) PIO Enable */ -/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ -#define PIO_PDR_P0 (0x1 << 0) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P1 (0x1 << 1) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P2 (0x1 << 2) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P3 (0x1 << 3) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P4 (0x1 << 4) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P5 (0x1 << 5) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P6 (0x1 << 6) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P7 (0x1 << 7) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P8 (0x1 << 8) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P9 (0x1 << 9) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P10 (0x1 << 10) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P11 (0x1 << 11) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P12 (0x1 << 12) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P13 (0x1 << 13) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P14 (0x1 << 14) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P15 (0x1 << 15) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P16 (0x1 << 16) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P17 (0x1 << 17) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P18 (0x1 << 18) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P19 (0x1 << 19) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P20 (0x1 << 20) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P21 (0x1 << 21) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P22 (0x1 << 22) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P23 (0x1 << 23) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P24 (0x1 << 24) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P25 (0x1 << 25) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P26 (0x1 << 26) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P27 (0x1 << 27) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P28 (0x1 << 28) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P29 (0x1 << 29) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P30 (0x1 << 30) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P31 (0x1 << 31) /**< \brief (PIO_PDR) PIO Disable */ -/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ -#define PIO_PSR_P0 (0x1 << 0) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P1 (0x1 << 1) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P2 (0x1 << 2) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P3 (0x1 << 3) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P4 (0x1 << 4) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P5 (0x1 << 5) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P6 (0x1 << 6) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P7 (0x1 << 7) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P8 (0x1 << 8) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P9 (0x1 << 9) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P10 (0x1 << 10) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P11 (0x1 << 11) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P12 (0x1 << 12) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P13 (0x1 << 13) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P14 (0x1 << 14) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P15 (0x1 << 15) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P16 (0x1 << 16) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P17 (0x1 << 17) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P18 (0x1 << 18) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P19 (0x1 << 19) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P20 (0x1 << 20) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P21 (0x1 << 21) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P22 (0x1 << 22) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P23 (0x1 << 23) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P24 (0x1 << 24) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P25 (0x1 << 25) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P26 (0x1 << 26) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P27 (0x1 << 27) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P28 (0x1 << 28) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P29 (0x1 << 29) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P30 (0x1 << 30) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P31 (0x1 << 31) /**< \brief (PIO_PSR) PIO Status */ -/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ -#define PIO_OER_P0 (0x1 << 0) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P1 (0x1 << 1) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P2 (0x1 << 2) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P3 (0x1 << 3) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P4 (0x1 << 4) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P5 (0x1 << 5) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P6 (0x1 << 6) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P7 (0x1 << 7) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P8 (0x1 << 8) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P9 (0x1 << 9) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P10 (0x1 << 10) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P11 (0x1 << 11) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P12 (0x1 << 12) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P13 (0x1 << 13) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P14 (0x1 << 14) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P15 (0x1 << 15) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P16 (0x1 << 16) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P17 (0x1 << 17) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P18 (0x1 << 18) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P19 (0x1 << 19) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P20 (0x1 << 20) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P21 (0x1 << 21) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P22 (0x1 << 22) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P23 (0x1 << 23) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P24 (0x1 << 24) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P25 (0x1 << 25) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P26 (0x1 << 26) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P27 (0x1 << 27) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P28 (0x1 << 28) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P29 (0x1 << 29) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P30 (0x1 << 30) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P31 (0x1 << 31) /**< \brief (PIO_OER) Output Enable */ -/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ -#define PIO_ODR_P0 (0x1 << 0) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P1 (0x1 << 1) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P2 (0x1 << 2) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P3 (0x1 << 3) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P4 (0x1 << 4) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P5 (0x1 << 5) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P6 (0x1 << 6) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P7 (0x1 << 7) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P8 (0x1 << 8) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P9 (0x1 << 9) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P10 (0x1 << 10) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P11 (0x1 << 11) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P12 (0x1 << 12) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P13 (0x1 << 13) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P14 (0x1 << 14) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P15 (0x1 << 15) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P16 (0x1 << 16) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P17 (0x1 << 17) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P18 (0x1 << 18) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P19 (0x1 << 19) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P20 (0x1 << 20) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P21 (0x1 << 21) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P22 (0x1 << 22) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P23 (0x1 << 23) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P24 (0x1 << 24) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P25 (0x1 << 25) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P26 (0x1 << 26) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P27 (0x1 << 27) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P28 (0x1 << 28) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P29 (0x1 << 29) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P30 (0x1 << 30) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P31 (0x1 << 31) /**< \brief (PIO_ODR) Output Disable */ -/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ -#define PIO_OSR_P0 (0x1 << 0) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P1 (0x1 << 1) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P2 (0x1 << 2) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P3 (0x1 << 3) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P4 (0x1 << 4) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P5 (0x1 << 5) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P6 (0x1 << 6) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P7 (0x1 << 7) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P8 (0x1 << 8) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P9 (0x1 << 9) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P10 (0x1 << 10) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P11 (0x1 << 11) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P12 (0x1 << 12) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P13 (0x1 << 13) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P14 (0x1 << 14) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P15 (0x1 << 15) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P16 (0x1 << 16) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P17 (0x1 << 17) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P18 (0x1 << 18) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P19 (0x1 << 19) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P20 (0x1 << 20) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P21 (0x1 << 21) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P22 (0x1 << 22) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P23 (0x1 << 23) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P24 (0x1 << 24) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P25 (0x1 << 25) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P26 (0x1 << 26) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P27 (0x1 << 27) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P28 (0x1 << 28) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P29 (0x1 << 29) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P30 (0x1 << 30) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P31 (0x1 << 31) /**< \brief (PIO_OSR) Output Status */ -/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ -#define PIO_IFER_P0 (0x1 << 0) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P1 (0x1 << 1) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P2 (0x1 << 2) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P3 (0x1 << 3) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P4 (0x1 << 4) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P5 (0x1 << 5) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P6 (0x1 << 6) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P7 (0x1 << 7) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P8 (0x1 << 8) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P9 (0x1 << 9) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P10 (0x1 << 10) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P11 (0x1 << 11) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P12 (0x1 << 12) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P13 (0x1 << 13) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P14 (0x1 << 14) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P15 (0x1 << 15) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P16 (0x1 << 16) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P17 (0x1 << 17) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P18 (0x1 << 18) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P19 (0x1 << 19) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P20 (0x1 << 20) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P21 (0x1 << 21) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P22 (0x1 << 22) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P23 (0x1 << 23) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P24 (0x1 << 24) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P25 (0x1 << 25) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P26 (0x1 << 26) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P27 (0x1 << 27) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P28 (0x1 << 28) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P29 (0x1 << 29) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P30 (0x1 << 30) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P31 (0x1 << 31) /**< \brief (PIO_IFER) Input Filter Enable */ -/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ -#define PIO_IFDR_P0 (0x1 << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P1 (0x1 << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P2 (0x1 << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P3 (0x1 << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P4 (0x1 << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P5 (0x1 << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P6 (0x1 << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P7 (0x1 << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P8 (0x1 << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P9 (0x1 << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P10 (0x1 << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P11 (0x1 << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P12 (0x1 << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P13 (0x1 << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P14 (0x1 << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P15 (0x1 << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P16 (0x1 << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P17 (0x1 << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P18 (0x1 << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P19 (0x1 << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P20 (0x1 << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P21 (0x1 << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P22 (0x1 << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P23 (0x1 << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P24 (0x1 << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P25 (0x1 << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P26 (0x1 << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P27 (0x1 << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P28 (0x1 << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P29 (0x1 << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P30 (0x1 << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P31 (0x1 << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ -/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ -#define PIO_IFSR_P0 (0x1 << 0) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P1 (0x1 << 1) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P2 (0x1 << 2) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P3 (0x1 << 3) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P4 (0x1 << 4) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P5 (0x1 << 5) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P6 (0x1 << 6) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P7 (0x1 << 7) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P8 (0x1 << 8) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P9 (0x1 << 9) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P10 (0x1 << 10) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P11 (0x1 << 11) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P12 (0x1 << 12) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P13 (0x1 << 13) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P14 (0x1 << 14) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P15 (0x1 << 15) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P16 (0x1 << 16) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P17 (0x1 << 17) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P18 (0x1 << 18) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P19 (0x1 << 19) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P20 (0x1 << 20) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P21 (0x1 << 21) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P22 (0x1 << 22) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P23 (0x1 << 23) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P24 (0x1 << 24) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P25 (0x1 << 25) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P26 (0x1 << 26) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P27 (0x1 << 27) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P28 (0x1 << 28) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P29 (0x1 << 29) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P30 (0x1 << 30) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P31 (0x1 << 31) /**< \brief (PIO_IFSR) Input Filer Status */ -/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ -#define PIO_SODR_P0 (0x1 << 0) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P1 (0x1 << 1) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P2 (0x1 << 2) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P3 (0x1 << 3) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P4 (0x1 << 4) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P5 (0x1 << 5) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P6 (0x1 << 6) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P7 (0x1 << 7) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P8 (0x1 << 8) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P9 (0x1 << 9) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P10 (0x1 << 10) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P11 (0x1 << 11) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P12 (0x1 << 12) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P13 (0x1 << 13) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P14 (0x1 << 14) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P15 (0x1 << 15) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P16 (0x1 << 16) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P17 (0x1 << 17) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P18 (0x1 << 18) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P19 (0x1 << 19) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P20 (0x1 << 20) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P21 (0x1 << 21) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P22 (0x1 << 22) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P23 (0x1 << 23) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P24 (0x1 << 24) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P25 (0x1 << 25) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P26 (0x1 << 26) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P27 (0x1 << 27) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P28 (0x1 << 28) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P29 (0x1 << 29) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P30 (0x1 << 30) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P31 (0x1 << 31) /**< \brief (PIO_SODR) Set Output Data */ -/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ -#define PIO_CODR_P0 (0x1 << 0) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P1 (0x1 << 1) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P2 (0x1 << 2) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P3 (0x1 << 3) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P4 (0x1 << 4) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P5 (0x1 << 5) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P6 (0x1 << 6) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P7 (0x1 << 7) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P8 (0x1 << 8) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P9 (0x1 << 9) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P10 (0x1 << 10) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P11 (0x1 << 11) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P12 (0x1 << 12) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P13 (0x1 << 13) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P14 (0x1 << 14) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P15 (0x1 << 15) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P16 (0x1 << 16) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P17 (0x1 << 17) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P18 (0x1 << 18) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P19 (0x1 << 19) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P20 (0x1 << 20) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P21 (0x1 << 21) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P22 (0x1 << 22) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P23 (0x1 << 23) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P24 (0x1 << 24) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P25 (0x1 << 25) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P26 (0x1 << 26) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P27 (0x1 << 27) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P28 (0x1 << 28) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P29 (0x1 << 29) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P30 (0x1 << 30) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P31 (0x1 << 31) /**< \brief (PIO_CODR) Clear Output Data */ -/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ -#define PIO_ODSR_P0 (0x1 << 0) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P1 (0x1 << 1) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P2 (0x1 << 2) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P3 (0x1 << 3) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P4 (0x1 << 4) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P5 (0x1 << 5) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P6 (0x1 << 6) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P7 (0x1 << 7) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P8 (0x1 << 8) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P9 (0x1 << 9) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P10 (0x1 << 10) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P11 (0x1 << 11) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P12 (0x1 << 12) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P13 (0x1 << 13) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P14 (0x1 << 14) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P15 (0x1 << 15) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P16 (0x1 << 16) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P17 (0x1 << 17) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P18 (0x1 << 18) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P19 (0x1 << 19) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P20 (0x1 << 20) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P21 (0x1 << 21) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P22 (0x1 << 22) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P23 (0x1 << 23) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P24 (0x1 << 24) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P25 (0x1 << 25) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P26 (0x1 << 26) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P27 (0x1 << 27) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P28 (0x1 << 28) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P29 (0x1 << 29) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P30 (0x1 << 30) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P31 (0x1 << 31) /**< \brief (PIO_ODSR) Output Data Status */ -/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ -#define PIO_PDSR_P0 (0x1 << 0) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P1 (0x1 << 1) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P2 (0x1 << 2) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P3 (0x1 << 3) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P4 (0x1 << 4) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P5 (0x1 << 5) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P6 (0x1 << 6) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P7 (0x1 << 7) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P8 (0x1 << 8) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P9 (0x1 << 9) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P10 (0x1 << 10) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P11 (0x1 << 11) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P12 (0x1 << 12) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P13 (0x1 << 13) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P14 (0x1 << 14) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P15 (0x1 << 15) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P16 (0x1 << 16) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P17 (0x1 << 17) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P18 (0x1 << 18) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P19 (0x1 << 19) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P20 (0x1 << 20) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P21 (0x1 << 21) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P22 (0x1 << 22) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P23 (0x1 << 23) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P24 (0x1 << 24) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P25 (0x1 << 25) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P26 (0x1 << 26) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P27 (0x1 << 27) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P28 (0x1 << 28) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P29 (0x1 << 29) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P30 (0x1 << 30) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P31 (0x1 << 31) /**< \brief (PIO_PDSR) Output Data Status */ -/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ -#define PIO_IER_P0 (0x1 << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P1 (0x1 << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P2 (0x1 << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P3 (0x1 << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P4 (0x1 << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P5 (0x1 << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P6 (0x1 << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P7 (0x1 << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P8 (0x1 << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P9 (0x1 << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P10 (0x1 << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P11 (0x1 << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P12 (0x1 << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P13 (0x1 << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P14 (0x1 << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P15 (0x1 << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P16 (0x1 << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P17 (0x1 << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P18 (0x1 << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P19 (0x1 << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P20 (0x1 << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P21 (0x1 << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P22 (0x1 << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P23 (0x1 << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P24 (0x1 << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P25 (0x1 << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P26 (0x1 << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P27 (0x1 << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P28 (0x1 << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P29 (0x1 << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P30 (0x1 << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P31 (0x1 << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ -#define PIO_IDR_P0 (0x1 << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P1 (0x1 << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P2 (0x1 << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P3 (0x1 << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P4 (0x1 << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P5 (0x1 << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P6 (0x1 << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P7 (0x1 << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P8 (0x1 << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P9 (0x1 << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P10 (0x1 << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P11 (0x1 << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P12 (0x1 << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P13 (0x1 << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P14 (0x1 << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P15 (0x1 << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P16 (0x1 << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P17 (0x1 << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P18 (0x1 << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P19 (0x1 << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P20 (0x1 << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P21 (0x1 << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P22 (0x1 << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P23 (0x1 << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P24 (0x1 << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P25 (0x1 << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P26 (0x1 << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P27 (0x1 << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P28 (0x1 << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P29 (0x1 << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P30 (0x1 << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P31 (0x1 << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ -#define PIO_IMR_P0 (0x1 << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P1 (0x1 << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P2 (0x1 << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P3 (0x1 << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P4 (0x1 << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P5 (0x1 << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P6 (0x1 << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P7 (0x1 << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P8 (0x1 << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P9 (0x1 << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P10 (0x1 << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P11 (0x1 << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P12 (0x1 << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P13 (0x1 << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P14 (0x1 << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P15 (0x1 << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P16 (0x1 << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P17 (0x1 << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P18 (0x1 << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P19 (0x1 << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P20 (0x1 << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P21 (0x1 << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P22 (0x1 << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P23 (0x1 << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P24 (0x1 << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P25 (0x1 << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P26 (0x1 << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P27 (0x1 << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P28 (0x1 << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P29 (0x1 << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P30 (0x1 << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P31 (0x1 << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ -#define PIO_ISR_P0 (0x1 << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P1 (0x1 << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P2 (0x1 << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P3 (0x1 << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P4 (0x1 << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P5 (0x1 << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P6 (0x1 << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P7 (0x1 << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P8 (0x1 << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P9 (0x1 << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P10 (0x1 << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P11 (0x1 << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P12 (0x1 << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P13 (0x1 << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P14 (0x1 << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P15 (0x1 << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P16 (0x1 << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P17 (0x1 << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P18 (0x1 << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P19 (0x1 << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P20 (0x1 << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P21 (0x1 << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P22 (0x1 << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P23 (0x1 << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P24 (0x1 << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P25 (0x1 << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P26 (0x1 << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P27 (0x1 << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P28 (0x1 << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P29 (0x1 << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P30 (0x1 << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P31 (0x1 << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ -#define PIO_MDER_P0 (0x1 << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P1 (0x1 << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P2 (0x1 << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P3 (0x1 << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P4 (0x1 << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P5 (0x1 << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P6 (0x1 << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P7 (0x1 << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P8 (0x1 << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P9 (0x1 << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P10 (0x1 << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P11 (0x1 << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P12 (0x1 << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P13 (0x1 << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P14 (0x1 << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P15 (0x1 << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P16 (0x1 << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P17 (0x1 << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P18 (0x1 << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P19 (0x1 << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P20 (0x1 << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P21 (0x1 << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P22 (0x1 << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P23 (0x1 << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P24 (0x1 << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P25 (0x1 << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P26 (0x1 << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P27 (0x1 << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P28 (0x1 << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P29 (0x1 << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P30 (0x1 << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P31 (0x1 << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */ -/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ -#define PIO_MDDR_P0 (0x1 << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P1 (0x1 << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P2 (0x1 << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P3 (0x1 << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P4 (0x1 << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P5 (0x1 << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P6 (0x1 << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P7 (0x1 << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P8 (0x1 << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P9 (0x1 << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P10 (0x1 << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P11 (0x1 << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P12 (0x1 << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P13 (0x1 << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P14 (0x1 << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P15 (0x1 << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P16 (0x1 << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P17 (0x1 << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P18 (0x1 << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P19 (0x1 << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P20 (0x1 << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P21 (0x1 << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P22 (0x1 << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P23 (0x1 << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P24 (0x1 << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P25 (0x1 << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P26 (0x1 << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P27 (0x1 << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P28 (0x1 << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P29 (0x1 << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P30 (0x1 << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P31 (0x1 << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ -#define PIO_MDSR_P0 (0x1 << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P1 (0x1 << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P2 (0x1 << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P3 (0x1 << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P4 (0x1 << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P5 (0x1 << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P6 (0x1 << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P7 (0x1 << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P8 (0x1 << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P9 (0x1 << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P10 (0x1 << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P11 (0x1 << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P12 (0x1 << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P13 (0x1 << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P14 (0x1 << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P15 (0x1 << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P16 (0x1 << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P17 (0x1 << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P18 (0x1 << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P19 (0x1 << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P20 (0x1 << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P21 (0x1 << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P22 (0x1 << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P23 (0x1 << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P24 (0x1 << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P25 (0x1 << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P26 (0x1 << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P27 (0x1 << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P28 (0x1 << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P29 (0x1 << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P30 (0x1 << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P31 (0x1 << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */ -/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ -#define PIO_PUDR_P0 (0x1 << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P1 (0x1 << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P2 (0x1 << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P3 (0x1 << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P4 (0x1 << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P5 (0x1 << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P6 (0x1 << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P7 (0x1 << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P8 (0x1 << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P9 (0x1 << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P10 (0x1 << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P11 (0x1 << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P12 (0x1 << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P13 (0x1 << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P14 (0x1 << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P15 (0x1 << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P16 (0x1 << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P17 (0x1 << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P18 (0x1 << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P19 (0x1 << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P20 (0x1 << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P21 (0x1 << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P22 (0x1 << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P23 (0x1 << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P24 (0x1 << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P25 (0x1 << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P26 (0x1 << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P27 (0x1 << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P28 (0x1 << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P29 (0x1 << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P30 (0x1 << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P31 (0x1 << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */ -/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ -#define PIO_PUER_P0 (0x1 << 0) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P1 (0x1 << 1) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P2 (0x1 << 2) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P3 (0x1 << 3) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P4 (0x1 << 4) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P5 (0x1 << 5) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P6 (0x1 << 6) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P7 (0x1 << 7) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P8 (0x1 << 8) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P9 (0x1 << 9) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P10 (0x1 << 10) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P11 (0x1 << 11) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P12 (0x1 << 12) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P13 (0x1 << 13) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P14 (0x1 << 14) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P15 (0x1 << 15) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P16 (0x1 << 16) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P17 (0x1 << 17) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P18 (0x1 << 18) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P19 (0x1 << 19) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P20 (0x1 << 20) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P21 (0x1 << 21) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P22 (0x1 << 22) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P23 (0x1 << 23) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P24 (0x1 << 24) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P25 (0x1 << 25) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P26 (0x1 << 26) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P27 (0x1 << 27) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P28 (0x1 << 28) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P29 (0x1 << 29) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P30 (0x1 << 30) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P31 (0x1 << 31) /**< \brief (PIO_PUER) Pull Up Enable. */ -/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ -#define PIO_PUSR_P0 (0x1 << 0) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P1 (0x1 << 1) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P2 (0x1 << 2) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P3 (0x1 << 3) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P4 (0x1 << 4) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P5 (0x1 << 5) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P6 (0x1 << 6) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P7 (0x1 << 7) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P8 (0x1 << 8) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P9 (0x1 << 9) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P10 (0x1 << 10) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P11 (0x1 << 11) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P12 (0x1 << 12) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P13 (0x1 << 13) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P14 (0x1 << 14) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P15 (0x1 << 15) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P16 (0x1 << 16) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P17 (0x1 << 17) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P18 (0x1 << 18) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P19 (0x1 << 19) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P20 (0x1 << 20) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P21 (0x1 << 21) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P22 (0x1 << 22) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P23 (0x1 << 23) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P24 (0x1 << 24) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P25 (0x1 << 25) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P26 (0x1 << 26) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P27 (0x1 << 27) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P28 (0x1 << 28) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P29 (0x1 << 29) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P30 (0x1 << 30) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P31 (0x1 << 31) /**< \brief (PIO_PUSR) Pull Up Status. */ -/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ -#define PIO_ABCDSR_P0 (0x1 << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P1 (0x1 << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P2 (0x1 << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P3 (0x1 << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P4 (0x1 << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P5 (0x1 << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P6 (0x1 << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P7 (0x1 << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P8 (0x1 << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P9 (0x1 << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P10 (0x1 << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P11 (0x1 << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P12 (0x1 << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P13 (0x1 << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P14 (0x1 << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P15 (0x1 << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P16 (0x1 << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P17 (0x1 << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P18 (0x1 << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P19 (0x1 << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P20 (0x1 << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P21 (0x1 << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P22 (0x1 << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P23 (0x1 << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P24 (0x1 << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P25 (0x1 << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P26 (0x1 << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P27 (0x1 << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P28 (0x1 << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P29 (0x1 << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P30 (0x1 << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P31 (0x1 << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -/* -------- PIO_SCIFSR : (PIO Offset: 0x0080) System Clock Glitch Input Filter Select Register -------- */ -#define PIO_SCIFSR_P0 (0x1 << 0) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P1 (0x1 << 1) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P2 (0x1 << 2) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P3 (0x1 << 3) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P4 (0x1 << 4) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P5 (0x1 << 5) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P6 (0x1 << 6) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P7 (0x1 << 7) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P8 (0x1 << 8) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P9 (0x1 << 9) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P10 (0x1 << 10) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P11 (0x1 << 11) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P12 (0x1 << 12) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P13 (0x1 << 13) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P14 (0x1 << 14) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P15 (0x1 << 15) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P16 (0x1 << 16) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P17 (0x1 << 17) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P18 (0x1 << 18) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P19 (0x1 << 19) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P20 (0x1 << 20) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P21 (0x1 << 21) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P22 (0x1 << 22) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P23 (0x1 << 23) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P24 (0x1 << 24) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P25 (0x1 << 25) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P26 (0x1 << 26) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P27 (0x1 << 27) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P28 (0x1 << 28) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P29 (0x1 << 29) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P30 (0x1 << 30) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P31 (0x1 << 31) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -/* -------- PIO_DIFSR : (PIO Offset: 0x0084) Debouncing Input Filter Select Register -------- */ -#define PIO_DIFSR_P0 (0x1 << 0) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P1 (0x1 << 1) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P2 (0x1 << 2) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P3 (0x1 << 3) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P4 (0x1 << 4) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P5 (0x1 << 5) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P6 (0x1 << 6) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P7 (0x1 << 7) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P8 (0x1 << 8) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P9 (0x1 << 9) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P10 (0x1 << 10) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P11 (0x1 << 11) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P12 (0x1 << 12) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P13 (0x1 << 13) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P14 (0x1 << 14) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P15 (0x1 << 15) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P16 (0x1 << 16) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P17 (0x1 << 17) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P18 (0x1 << 18) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P19 (0x1 << 19) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P20 (0x1 << 20) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P21 (0x1 << 21) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P22 (0x1 << 22) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P23 (0x1 << 23) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P24 (0x1 << 24) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P25 (0x1 << 25) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P26 (0x1 << 26) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P27 (0x1 << 27) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P28 (0x1 << 28) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P29 (0x1 << 29) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P30 (0x1 << 30) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P31 (0x1 << 31) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -/* -------- PIO_IFDGSR : (PIO Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register -------- */ -#define PIO_IFDGSR_P0 (0x1 << 0) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P1 (0x1 << 1) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P2 (0x1 << 2) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P3 (0x1 << 3) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P4 (0x1 << 4) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P5 (0x1 << 5) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P6 (0x1 << 6) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P7 (0x1 << 7) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P8 (0x1 << 8) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P9 (0x1 << 9) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P10 (0x1 << 10) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P11 (0x1 << 11) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P12 (0x1 << 12) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P13 (0x1 << 13) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P14 (0x1 << 14) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P15 (0x1 << 15) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P16 (0x1 << 16) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P17 (0x1 << 17) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P18 (0x1 << 18) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P19 (0x1 << 19) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P20 (0x1 << 20) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P21 (0x1 << 21) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P22 (0x1 << 22) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P23 (0x1 << 23) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P24 (0x1 << 24) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P25 (0x1 << 25) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P26 (0x1 << 26) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P27 (0x1 << 27) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P28 (0x1 << 28) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P29 (0x1 << 29) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P30 (0x1 << 30) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P31 (0x1 << 31) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ -#define PIO_SCDR_DIV0 (0x1 << 0) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV1 (0x1 << 1) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV2 (0x1 << 2) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV3 (0x1 << 3) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV4 (0x1 << 4) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV5 (0x1 << 5) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV6 (0x1 << 6) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV7 (0x1 << 7) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV8 (0x1 << 8) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV9 (0x1 << 9) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV10 (0x1 << 10) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV11 (0x1 << 11) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV12 (0x1 << 12) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV13 (0x1 << 13) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ -#define PIO_PPDDR_P0 (0x1 << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P1 (0x1 << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P2 (0x1 << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P3 (0x1 << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P4 (0x1 << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P5 (0x1 << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P6 (0x1 << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P7 (0x1 << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P8 (0x1 << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P9 (0x1 << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P10 (0x1 << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P11 (0x1 << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P12 (0x1 << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P13 (0x1 << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P14 (0x1 << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P15 (0x1 << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P16 (0x1 << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P17 (0x1 << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P18 (0x1 << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P19 (0x1 << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P20 (0x1 << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P21 (0x1 << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P22 (0x1 << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P23 (0x1 << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P24 (0x1 << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P25 (0x1 << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P26 (0x1 << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P27 (0x1 << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P28 (0x1 << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P29 (0x1 << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P30 (0x1 << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P31 (0x1 << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ -#define PIO_PPDER_P0 (0x1 << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P1 (0x1 << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P2 (0x1 << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P3 (0x1 << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P4 (0x1 << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P5 (0x1 << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P6 (0x1 << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P7 (0x1 << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P8 (0x1 << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P9 (0x1 << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P10 (0x1 << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P11 (0x1 << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P12 (0x1 << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P13 (0x1 << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P14 (0x1 << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P15 (0x1 << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P16 (0x1 << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P17 (0x1 << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P18 (0x1 << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P19 (0x1 << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P20 (0x1 << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P21 (0x1 << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P22 (0x1 << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P23 (0x1 << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P24 (0x1 << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P25 (0x1 << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P26 (0x1 << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P27 (0x1 << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P28 (0x1 << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P29 (0x1 << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P30 (0x1 << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P31 (0x1 << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */ -/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ -#define PIO_PPDSR_P0 (0x1 << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P1 (0x1 << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P2 (0x1 << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P3 (0x1 << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P4 (0x1 << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P5 (0x1 << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P6 (0x1 << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P7 (0x1 << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P8 (0x1 << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P9 (0x1 << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P10 (0x1 << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P11 (0x1 << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P12 (0x1 << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P13 (0x1 << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P14 (0x1 << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P15 (0x1 << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P16 (0x1 << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P17 (0x1 << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P18 (0x1 << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P19 (0x1 << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P20 (0x1 << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P21 (0x1 << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P22 (0x1 << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P23 (0x1 << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P24 (0x1 << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P25 (0x1 << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P26 (0x1 << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P27 (0x1 << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P28 (0x1 << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P29 (0x1 << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P30 (0x1 << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P31 (0x1 << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */ -/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ -#define PIO_OWER_P0 (0x1 << 0) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P1 (0x1 << 1) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P2 (0x1 << 2) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P3 (0x1 << 3) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P4 (0x1 << 4) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P5 (0x1 << 5) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P6 (0x1 << 6) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P7 (0x1 << 7) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P8 (0x1 << 8) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P9 (0x1 << 9) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P10 (0x1 << 10) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P11 (0x1 << 11) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P12 (0x1 << 12) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P13 (0x1 << 13) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P14 (0x1 << 14) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P15 (0x1 << 15) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P16 (0x1 << 16) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P17 (0x1 << 17) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P18 (0x1 << 18) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P19 (0x1 << 19) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P20 (0x1 << 20) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P21 (0x1 << 21) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P22 (0x1 << 22) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P23 (0x1 << 23) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P24 (0x1 << 24) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P25 (0x1 << 25) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P26 (0x1 << 26) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P27 (0x1 << 27) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P28 (0x1 << 28) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P29 (0x1 << 29) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P30 (0x1 << 30) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P31 (0x1 << 31) /**< \brief (PIO_OWER) Output Write Enable. */ -/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ -#define PIO_OWDR_P0 (0x1 << 0) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P1 (0x1 << 1) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P2 (0x1 << 2) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P3 (0x1 << 3) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P4 (0x1 << 4) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P5 (0x1 << 5) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P6 (0x1 << 6) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P7 (0x1 << 7) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P8 (0x1 << 8) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P9 (0x1 << 9) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P10 (0x1 << 10) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P11 (0x1 << 11) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P12 (0x1 << 12) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P13 (0x1 << 13) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P14 (0x1 << 14) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P15 (0x1 << 15) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P16 (0x1 << 16) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P17 (0x1 << 17) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P18 (0x1 << 18) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P19 (0x1 << 19) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P20 (0x1 << 20) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P21 (0x1 << 21) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P22 (0x1 << 22) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P23 (0x1 << 23) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P24 (0x1 << 24) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P25 (0x1 << 25) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P26 (0x1 << 26) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P27 (0x1 << 27) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P28 (0x1 << 28) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P29 (0x1 << 29) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P30 (0x1 << 30) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P31 (0x1 << 31) /**< \brief (PIO_OWDR) Output Write Disable. */ -/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ -#define PIO_OWSR_P0 (0x1 << 0) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P1 (0x1 << 1) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P2 (0x1 << 2) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P3 (0x1 << 3) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P4 (0x1 << 4) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P5 (0x1 << 5) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P6 (0x1 << 6) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P7 (0x1 << 7) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P8 (0x1 << 8) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P9 (0x1 << 9) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P10 (0x1 << 10) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P11 (0x1 << 11) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P12 (0x1 << 12) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P13 (0x1 << 13) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P14 (0x1 << 14) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P15 (0x1 << 15) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P16 (0x1 << 16) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P17 (0x1 << 17) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P18 (0x1 << 18) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P19 (0x1 << 19) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P20 (0x1 << 20) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P21 (0x1 << 21) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P22 (0x1 << 22) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P23 (0x1 << 23) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P24 (0x1 << 24) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P25 (0x1 << 25) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P26 (0x1 << 26) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P27 (0x1 << 27) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P28 (0x1 << 28) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P29 (0x1 << 29) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P30 (0x1 << 30) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P31 (0x1 << 31) /**< \brief (PIO_OWSR) Output Write Status. */ -/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ -#define PIO_AIMER_P0 (0x1 << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P1 (0x1 << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P2 (0x1 << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P3 (0x1 << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P4 (0x1 << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P5 (0x1 << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P6 (0x1 << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P7 (0x1 << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P8 (0x1 << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P9 (0x1 << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P10 (0x1 << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P11 (0x1 << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P12 (0x1 << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P13 (0x1 << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P14 (0x1 << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P15 (0x1 << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P16 (0x1 << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P17 (0x1 << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P18 (0x1 << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P19 (0x1 << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P20 (0x1 << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P21 (0x1 << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P22 (0x1 << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P23 (0x1 << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P24 (0x1 << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P25 (0x1 << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P26 (0x1 << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P27 (0x1 << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P28 (0x1 << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P29 (0x1 << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P30 (0x1 << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P31 (0x1 << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */ -#define PIO_AIMDR_P0 (0x1 << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P1 (0x1 << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P2 (0x1 << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P3 (0x1 << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P4 (0x1 << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P5 (0x1 << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P6 (0x1 << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P7 (0x1 << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P8 (0x1 << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P9 (0x1 << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P10 (0x1 << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P11 (0x1 << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P12 (0x1 << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P13 (0x1 << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P14 (0x1 << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P15 (0x1 << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P16 (0x1 << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P17 (0x1 << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P18 (0x1 << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P19 (0x1 << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P20 (0x1 << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P21 (0x1 << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P22 (0x1 << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P23 (0x1 << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P24 (0x1 << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P25 (0x1 << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P26 (0x1 << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P27 (0x1 << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P28 (0x1 << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P29 (0x1 << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P30 (0x1 << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P31 (0x1 << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ -#define PIO_AIMMR_P0 (0x1 << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P1 (0x1 << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P2 (0x1 << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P3 (0x1 << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P4 (0x1 << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P5 (0x1 << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P6 (0x1 << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P7 (0x1 << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P8 (0x1 << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P9 (0x1 << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P10 (0x1 << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P11 (0x1 << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P12 (0x1 << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P13 (0x1 << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P14 (0x1 << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P15 (0x1 << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P16 (0x1 << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P17 (0x1 << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P18 (0x1 << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P19 (0x1 << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P20 (0x1 << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P21 (0x1 << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P22 (0x1 << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P23 (0x1 << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P24 (0x1 << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P25 (0x1 << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P26 (0x1 << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P27 (0x1 << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P28 (0x1 << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P29 (0x1 << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P30 (0x1 << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P31 (0x1 << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ -#define PIO_ESR_P0 (0x1 << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P1 (0x1 << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P2 (0x1 << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P3 (0x1 << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P4 (0x1 << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P5 (0x1 << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P6 (0x1 << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P7 (0x1 << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P8 (0x1 << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P9 (0x1 << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P10 (0x1 << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P11 (0x1 << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P12 (0x1 << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P13 (0x1 << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P14 (0x1 << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P15 (0x1 << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P16 (0x1 << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P17 (0x1 << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P18 (0x1 << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P19 (0x1 << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P20 (0x1 << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P21 (0x1 << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P22 (0x1 << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P23 (0x1 << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P24 (0x1 << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P25 (0x1 << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P26 (0x1 << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P27 (0x1 << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P28 (0x1 << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P29 (0x1 << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P30 (0x1 << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P31 (0x1 << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ -#define PIO_LSR_P0 (0x1 << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P1 (0x1 << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P2 (0x1 << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P3 (0x1 << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P4 (0x1 << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P5 (0x1 << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P6 (0x1 << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P7 (0x1 << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P8 (0x1 << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P9 (0x1 << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P10 (0x1 << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P11 (0x1 << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P12 (0x1 << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P13 (0x1 << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P14 (0x1 << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P15 (0x1 << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P16 (0x1 << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P17 (0x1 << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P18 (0x1 << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P19 (0x1 << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P20 (0x1 << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P21 (0x1 << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P22 (0x1 << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P23 (0x1 << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P24 (0x1 << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P25 (0x1 << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P26 (0x1 << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P27 (0x1 << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P28 (0x1 << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P29 (0x1 << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P30 (0x1 << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P31 (0x1 << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ -#define PIO_ELSR_P0 (0x1 << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P1 (0x1 << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P2 (0x1 << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P3 (0x1 << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P4 (0x1 << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P5 (0x1 << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P6 (0x1 << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P7 (0x1 << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P8 (0x1 << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P9 (0x1 << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P10 (0x1 << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P11 (0x1 << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P12 (0x1 << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P13 (0x1 << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P14 (0x1 << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P15 (0x1 << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P16 (0x1 << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P17 (0x1 << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P18 (0x1 << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P19 (0x1 << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P20 (0x1 << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P21 (0x1 << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P22 (0x1 << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P23 (0x1 << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P24 (0x1 << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P25 (0x1 << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P26 (0x1 << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P27 (0x1 << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P28 (0x1 << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P29 (0x1 << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P30 (0x1 << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P31 (0x1 << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */ -#define PIO_FELLSR_P0 (0x1 << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P1 (0x1 << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P2 (0x1 << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P3 (0x1 << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P4 (0x1 << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P5 (0x1 << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P6 (0x1 << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P7 (0x1 << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P8 (0x1 << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P9 (0x1 << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P10 (0x1 << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P11 (0x1 << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P12 (0x1 << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P13 (0x1 << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P14 (0x1 << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P15 (0x1 << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P16 (0x1 << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P17 (0x1 << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P18 (0x1 << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P19 (0x1 << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P20 (0x1 << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P21 (0x1 << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P22 (0x1 << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P23 (0x1 << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P24 (0x1 << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P25 (0x1 << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P26 (0x1 << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P27 (0x1 << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P28 (0x1 << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P29 (0x1 << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P30 (0x1 << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P31 (0x1 << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */ -#define PIO_REHLSR_P0 (0x1 << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P1 (0x1 << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P2 (0x1 << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P3 (0x1 << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P4 (0x1 << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P5 (0x1 << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P6 (0x1 << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P7 (0x1 << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P8 (0x1 << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P9 (0x1 << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P10 (0x1 << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P11 (0x1 << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P12 (0x1 << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P13 (0x1 << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P14 (0x1 << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P15 (0x1 << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P16 (0x1 << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P17 (0x1 << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P18 (0x1 << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P19 (0x1 << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P20 (0x1 << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P21 (0x1 << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P22 (0x1 << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P23 (0x1 << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P24 (0x1 << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P25 (0x1 << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P26 (0x1 << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P27 (0x1 << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P28 (0x1 << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P29 (0x1 << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P30 (0x1 << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P31 (0x1 << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ -#define PIO_FRLHSR_P0 (0x1 << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P1 (0x1 << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P2 (0x1 << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P3 (0x1 << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P4 (0x1 << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P5 (0x1 << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P6 (0x1 << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P7 (0x1 << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P8 (0x1 << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P9 (0x1 << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P10 (0x1 << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P11 (0x1 << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P12 (0x1 << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P13 (0x1 << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P14 (0x1 << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P15 (0x1 << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P16 (0x1 << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P17 (0x1 << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P18 (0x1 << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P19 (0x1 << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P20 (0x1 << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P21 (0x1 << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P22 (0x1 << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P23 (0x1 << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P24 (0x1 << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P25 (0x1 << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P26 (0x1 << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P27 (0x1 << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P28 (0x1 << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P29 (0x1 << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P30 (0x1 << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P31 (0x1 << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ -#define PIO_LOCKSR_P0 (0x1 << 0) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P1 (0x1 << 1) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P2 (0x1 << 2) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P3 (0x1 << 3) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P4 (0x1 << 4) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P5 (0x1 << 5) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P6 (0x1 << 6) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P7 (0x1 << 7) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P8 (0x1 << 8) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P9 (0x1 << 9) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P10 (0x1 << 10) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P11 (0x1 << 11) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P12 (0x1 << 12) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P13 (0x1 << 13) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P14 (0x1 << 14) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P15 (0x1 << 15) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P16 (0x1 << 16) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P17 (0x1 << 17) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P18 (0x1 << 18) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P19 (0x1 << 19) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P20 (0x1 << 20) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P21 (0x1 << 21) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P22 (0x1 << 22) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P23 (0x1 << 23) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P24 (0x1 << 24) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P25 (0x1 << 25) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P26 (0x1 << 26) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P27 (0x1 << 27) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P28 (0x1 << 28) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P29 (0x1 << 29) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P30 (0x1 << 30) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P31 (0x1 << 31) /**< \brief (PIO_LOCKSR) Lock Status. */ -/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */ -#define PIO_WPMR_WPEN (0x1 << 0) /**< \brief (PIO_WPMR) Write Protect Enable */ -#define PIO_WPMR_WPKEY (0xffffff << 8) /**< \brief (PIO_WPMR) Write Protect KEY */ -/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */ -#define PIO_WPSR_WPVS (0x1 << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */ -#define PIO_WPSR_WPVSRC (0xffff << 8) /**< \brief (PIO_WPSR) Write Protect Violation Source */ -/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ -#define PIO_SCHMITT_SCHMITT0 (0x1 << 0) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT1 (0x1 << 1) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT2 (0x1 << 2) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT3 (0x1 << 3) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT4 (0x1 << 4) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT5 (0x1 << 5) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT6 (0x1 << 6) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT7 (0x1 << 7) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT8 (0x1 << 8) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT9 (0x1 << 9) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT10 (0x1 << 10) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT11 (0x1 << 11) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT12 (0x1 << 12) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT13 (0x1 << 13) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT14 (0x1 << 14) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT15 (0x1 << 15) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT16 (0x1 << 16) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT17 (0x1 << 17) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT18 (0x1 << 18) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT19 (0x1 << 19) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT20 (0x1 << 20) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT21 (0x1 << 21) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT22 (0x1 << 22) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT23 (0x1 << 23) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT24 (0x1 << 24) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT25 (0x1 << 25) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT26 (0x1 << 26) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT27 (0x1 << 27) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT28 (0x1 << 28) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT29 (0x1 << 29) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT30 (0x1 << 30) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT31 (0x1 << 31) /**< \brief (PIO_SCHMITT) */ -/* -------- PIO_PCMR : (PIO Offset: 0x150) Parallel Capture Mode Register -------- */ -#define PIO_PCMR_PCEN (0x1 << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */ -#define PIO_PCMR_DSIZE (0x3 << 4) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */ -#define PIO_PCMR_ALWYS (0x1 << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */ -#define PIO_PCMR_HALFS (0x1 << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */ -#define PIO_PCMR_FRSTS (0x1 << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */ -/* -------- PIO_PCIER : (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register -------- */ -#define PIO_PCIER_DRDY (0x1 << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */ -#define PIO_PCIER_OVRE (0x1 << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */ -#define PIO_PCIER_ENDRX (0x1 << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */ -#define PIO_PCIER_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */ -/* -------- PIO_PCIDR : (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register -------- */ -#define PIO_PCIDR_DRDY (0x1 << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */ -#define PIO_PCIDR_OVRE (0x1 << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */ -#define PIO_PCIDR_ENDRX (0x1 << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */ -#define PIO_PCIDR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */ -/* -------- PIO_PCIMR : (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register -------- */ -#define PIO_PCIMR_DRDY (0x1 << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */ -#define PIO_PCIMR_OVRE (0x1 << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */ -#define PIO_PCIMR_ENDRX (0x1 << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */ -#define PIO_PCIMR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */ -/* -------- PIO_PCISR : (PIO Offset: 0x160) Parallel Capture Interrupt Status Register -------- */ -#define PIO_PCISR_DRDY (0x1 << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */ -#define PIO_PCISR_OVRE (0x1 << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error. */ -#define PIO_PCISR_ENDRX (0x1 << 2) /**< \brief (PIO_PCISR) End of Reception Transfer. */ -#define PIO_PCISR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCISR) Reception Buffer Full */ -/* -------- PIO_PCRHR : (PIO Offset: 0x164) Parallel Capture Reception Holding Register -------- */ -#define PIO_PCRHR_RDATA (0xffffffff << 0) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data. */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Power Management Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PMC Power Management Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pmc hardware registers */ -typedef struct { - WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ - WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ - RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ - RwReg Reserved1[1]; - WoReg PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ - WoReg PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ - RoReg PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ - RwReg Reserved2[1]; - RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ - RoReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ - RwReg CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ - RwReg CKGR_PLLBR; /**< \brief (Pmc Offset: 0x002C) PLLB Register */ - RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ - RwReg Reserved3[1]; - RwReg PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ - RwReg Reserved4[1]; - RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ - RwReg Reserved5[5]; - WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ - WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ - RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ - RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ - RwReg PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ - RwReg PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ - WoReg PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ - RwReg Reserved6[26]; - RwReg PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */ - RoReg PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */ - RwReg Reserved7[5]; - WoReg PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ - WoReg PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ - RoReg PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ - RwReg Reserved8[1]; - RwReg PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ -} Pmc; -#endif /* __ASSEMBLY__ */ -/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ -#define PMC_SCER_UDP (0x1 << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */ -#define PMC_SCER_PCK0 (0x1 << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ -#define PMC_SCER_PCK1 (0x1 << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ -#define PMC_SCER_PCK2 (0x1 << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ -/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ -#define PMC_SCDR_UDP (0x1 << 7) /**< \brief (PMC_SCDR) USB Device Port Clock Disable */ -#define PMC_SCDR_PCK0 (0x1 << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ -#define PMC_SCDR_PCK1 (0x1 << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ -#define PMC_SCDR_PCK2 (0x1 << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ -/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ -#define PMC_SCSR_UDP (0x1 << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */ -#define PMC_SCSR_PCK0 (0x1 << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ -#define PMC_SCSR_PCK1 (0x1 << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ -#define PMC_SCSR_PCK2 (0x1 << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ -/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ -#define PMC_PCER0_PID2 (0x1 << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */ -#define PMC_PCER0_PID3 (0x1 << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */ -#define PMC_PCER0_PID4 (0x1 << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */ -#define PMC_PCER0_PID5 (0x1 << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */ -#define PMC_PCER0_PID6 (0x1 << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */ -#define PMC_PCER0_PID7 (0x1 << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */ -#define PMC_PCER0_PID8 (0x1 << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ -#define PMC_PCER0_PID9 (0x1 << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ -#define PMC_PCER0_PID10 (0x1 << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ -#define PMC_PCER0_PID11 (0x1 << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ -#define PMC_PCER0_PID12 (0x1 << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ -#define PMC_PCER0_PID13 (0x1 << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ -#define PMC_PCER0_PID14 (0x1 << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ -#define PMC_PCER0_PID15 (0x1 << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ -#define PMC_PCER0_PID16 (0x1 << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ -#define PMC_PCER0_PID17 (0x1 << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ -#define PMC_PCER0_PID18 (0x1 << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ -#define PMC_PCER0_PID19 (0x1 << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ -#define PMC_PCER0_PID20 (0x1 << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ -#define PMC_PCER0_PID21 (0x1 << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ -#define PMC_PCER0_PID22 (0x1 << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ -#define PMC_PCER0_PID23 (0x1 << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ -#define PMC_PCER0_PID24 (0x1 << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ -#define PMC_PCER0_PID25 (0x1 << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ -#define PMC_PCER0_PID26 (0x1 << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ -#define PMC_PCER0_PID27 (0x1 << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ -#define PMC_PCER0_PID28 (0x1 << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ -#define PMC_PCER0_PID29 (0x1 << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ -#define PMC_PCER0_PID30 (0x1 << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ -#define PMC_PCER0_PID31 (0x1 << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ -/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ -#define PMC_PCDR0_PID2 (0x1 << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */ -#define PMC_PCDR0_PID3 (0x1 << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */ -#define PMC_PCDR0_PID4 (0x1 << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */ -#define PMC_PCDR0_PID5 (0x1 << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */ -#define PMC_PCDR0_PID6 (0x1 << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */ -#define PMC_PCDR0_PID7 (0x1 << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */ -#define PMC_PCDR0_PID8 (0x1 << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ -#define PMC_PCDR0_PID9 (0x1 << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ -#define PMC_PCDR0_PID10 (0x1 << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ -#define PMC_PCDR0_PID11 (0x1 << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ -#define PMC_PCDR0_PID12 (0x1 << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ -#define PMC_PCDR0_PID13 (0x1 << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ -#define PMC_PCDR0_PID14 (0x1 << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ -#define PMC_PCDR0_PID15 (0x1 << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ -#define PMC_PCDR0_PID16 (0x1 << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ -#define PMC_PCDR0_PID17 (0x1 << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ -#define PMC_PCDR0_PID18 (0x1 << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ -#define PMC_PCDR0_PID19 (0x1 << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ -#define PMC_PCDR0_PID20 (0x1 << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ -#define PMC_PCDR0_PID21 (0x1 << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ -#define PMC_PCDR0_PID22 (0x1 << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ -#define PMC_PCDR0_PID23 (0x1 << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ -#define PMC_PCDR0_PID24 (0x1 << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ -#define PMC_PCDR0_PID25 (0x1 << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ -#define PMC_PCDR0_PID26 (0x1 << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ -#define PMC_PCDR0_PID27 (0x1 << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ -#define PMC_PCDR0_PID28 (0x1 << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ -#define PMC_PCDR0_PID29 (0x1 << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ -#define PMC_PCDR0_PID30 (0x1 << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ -#define PMC_PCDR0_PID31 (0x1 << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ -/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ -#define PMC_PCSR0_PID2 (0x1 << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */ -#define PMC_PCSR0_PID3 (0x1 << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */ -#define PMC_PCSR0_PID4 (0x1 << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */ -#define PMC_PCSR0_PID5 (0x1 << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */ -#define PMC_PCSR0_PID6 (0x1 << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */ -#define PMC_PCSR0_PID7 (0x1 << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */ -#define PMC_PCSR0_PID8 (0x1 << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ -#define PMC_PCSR0_PID9 (0x1 << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ -#define PMC_PCSR0_PID10 (0x1 << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ -#define PMC_PCSR0_PID11 (0x1 << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ -#define PMC_PCSR0_PID12 (0x1 << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ -#define PMC_PCSR0_PID13 (0x1 << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ -#define PMC_PCSR0_PID14 (0x1 << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ -#define PMC_PCSR0_PID15 (0x1 << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ -#define PMC_PCSR0_PID16 (0x1 << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ -#define PMC_PCSR0_PID17 (0x1 << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ -#define PMC_PCSR0_PID18 (0x1 << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ -#define PMC_PCSR0_PID19 (0x1 << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ -#define PMC_PCSR0_PID20 (0x1 << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ -#define PMC_PCSR0_PID21 (0x1 << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ -#define PMC_PCSR0_PID22 (0x1 << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ -#define PMC_PCSR0_PID23 (0x1 << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ -#define PMC_PCSR0_PID24 (0x1 << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ -#define PMC_PCSR0_PID25 (0x1 << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ -#define PMC_PCSR0_PID26 (0x1 << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ -#define PMC_PCSR0_PID27 (0x1 << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ -#define PMC_PCSR0_PID28 (0x1 << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ -#define PMC_PCSR0_PID29 (0x1 << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ -#define PMC_PCSR0_PID30 (0x1 << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ -#define PMC_PCSR0_PID31 (0x1 << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ -/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ -#define CKGR_MOR_MOSCXTEN (0x1 << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */ -#define CKGR_MOR_MOSCXTBY (0x1 << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */ -#define CKGR_MOR_WAITMODE (0x1 << 2) /**< \brief (CKGR_MOR) Wait Mode Command */ -#define CKGR_MOR_MOSCRCEN (0x1 << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */ -#define CKGR_MOR_MOSCRCF (0x7 << 4) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */ -#define CKGR_MOR_MOSCXTST (0xff << 8) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */ -#define CKGR_MOR_KEY (0xff << 16) /**< \brief (CKGR_MOR) Password */ -#define CKGR_MOR_MOSCSEL (0x1 << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */ -#define CKGR_MOR_CFDEN (0x1 << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ -/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ -#define CKGR_MCFR_MAINF (0xffff << 0) /**< \brief (CKGR_MCFR) Main Clock Frequency */ -#define CKGR_MCFR_MAINFRDY (0x1 << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */ -/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ -#define CKGR_PLLAR_DIVA (0xff << 0) /**< \brief (CKGR_PLLAR) Divider */ -#define CKGR_PLLAR_PLLACOUNT (0x3f << 8) /**< \brief (CKGR_PLLAR) PLLA Counter */ -#define CKGR_PLLAR_MULA (0x7ff << 16) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ -#define CKGR_PLLAR_STUCKTO1 (0x1 << 29) /**< \brief (CKGR_PLLAR) */ -/* -------- CKGR_PLLBR : (PMC Offset: 0x002C) PLLB Register -------- */ -#define CKGR_PLLBR_DIVB (0xff << 0) /**< \brief (CKGR_PLLBR) Divider */ -#define CKGR_PLLBR_PLLBCOUNT (0x3f << 8) /**< \brief (CKGR_PLLBR) PLLB Counter */ -#define CKGR_PLLBR_MULB (0x7ff << 16) /**< \brief (CKGR_PLLBR) PLLB Multiplier */ -/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ -#define PMC_MCKR_CSS (0x3 << 0) /**< \brief (PMC_MCKR) Master Clock Source Selection */ -#define PMC_MCKR_CSS_SLOW_CLK (0x0 << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ -#define PMC_MCKR_CSS_MAIN_CLK (0x1 << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ -#define PMC_MCKR_CSS_PLLA_CLK (0x2 << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ -#define PMC_MCKR_CSS_PLLB_CLK (0x3 << 0) /**< \brief (PMC_MCKR) PLLB Clock is selected */ -#define PMC_MCKR_PRES (0x7 << 4) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ -#define PMC_MCKR_PRES_CLK (0x0 << 4) /**< \brief (PMC_MCKR) Selected clock */ -#define PMC_MCKR_PRES_CLK_2 (0x1 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ -#define PMC_MCKR_PRES_CLK_4 (0x2 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ -#define PMC_MCKR_PRES_CLK_8 (0x3 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ -#define PMC_MCKR_PRES_CLK_16 (0x4 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ -#define PMC_MCKR_PRES_CLK_32 (0x5 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ -#define PMC_MCKR_PRES_CLK_64 (0x6 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ -#define PMC_MCKR_PLLADIV2 (0x1 << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */ -#define PMC_MCKR_PLLBDIV2 (0x1 << 13) /**< \brief (PMC_MCKR) PLLB Divisor by 2 */ -/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ -#define PMC_USB_USBS (0x1 << 0) /**< \brief (PMC_USB) USB Input Clock Selection */ -#define PMC_USB_USBDIV (0xf << 8) /**< \brief (PMC_USB) Divider for USB Clock. */ -/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ -#define PMC_PCK_CSS (0x7 << 0) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */ -#define PMC_PCK_PRES (0x7 << 4) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */ -/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ -#define PMC_IER_MOSCXTS (0x1 << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ -#define PMC_IER_LOCKA (0x1 << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ -#define PMC_IER_LOCKB (0x1 << 2) /**< \brief (PMC_IER) PLLB Lock Interrupt Enable */ -#define PMC_IER_MCKRDY (0x1 << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ -#define PMC_IER_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ -#define PMC_IER_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ -#define PMC_IER_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ -#define PMC_IER_MOSCSELS (0x1 << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */ -#define PMC_IER_MOSCRCS (0x1 << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */ -#define PMC_IER_CFDEV (0x1 << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ -/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ -#define PMC_IDR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */ -#define PMC_IDR_LOCKA (0x1 << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ -#define PMC_IDR_LOCKB (0x1 << 2) /**< \brief (PMC_IDR) PLLB Lock Interrupt Disable */ -#define PMC_IDR_MCKRDY (0x1 << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ -#define PMC_IDR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ -#define PMC_IDR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ -#define PMC_IDR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ -#define PMC_IDR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */ -#define PMC_IDR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */ -#define PMC_IDR_CFDEV (0x1 << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ -/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ -#define PMC_SR_MOSCXTS (0x1 << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */ -#define PMC_SR_LOCKA (0x1 << 1) /**< \brief (PMC_SR) PLLA Lock Status */ -#define PMC_SR_LOCKB (0x1 << 2) /**< \brief (PMC_SR) PLLB Lock Status */ -#define PMC_SR_MCKRDY (0x1 << 3) /**< \brief (PMC_SR) Master Clock Status */ -#define PMC_SR_OSCSELS (0x1 << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */ -#define PMC_SR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_MOSCSELS (0x1 << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */ -#define PMC_SR_MOSCRCS (0x1 << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */ -#define PMC_SR_CFDEV (0x1 << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ -#define PMC_SR_CFDS (0x1 << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ -#define PMC_SR_FOS (0x1 << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ -/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ -#define PMC_IMR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */ -#define PMC_IMR_LOCKA (0x1 << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ -#define PMC_IMR_LOCKB (0x1 << 2) /**< \brief (PMC_IMR) PLLB Lock Interrupt Mask */ -#define PMC_IMR_MCKRDY (0x1 << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ -#define PMC_IMR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ -#define PMC_IMR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ -#define PMC_IMR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ -#define PMC_IMR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */ -#define PMC_IMR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */ -#define PMC_IMR_CFDEV (0x1 << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ -/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ -#define PMC_FSMR_FSTT0 (0x1 << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ -#define PMC_FSMR_FSTT1 (0x1 << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ -#define PMC_FSMR_FSTT2 (0x1 << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ -#define PMC_FSMR_FSTT3 (0x1 << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ -#define PMC_FSMR_FSTT4 (0x1 << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ -#define PMC_FSMR_FSTT5 (0x1 << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ -#define PMC_FSMR_FSTT6 (0x1 << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ -#define PMC_FSMR_FSTT7 (0x1 << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ -#define PMC_FSMR_FSTT8 (0x1 << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ -#define PMC_FSMR_FSTT9 (0x1 << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ -#define PMC_FSMR_FSTT10 (0x1 << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ -#define PMC_FSMR_FSTT11 (0x1 << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ -#define PMC_FSMR_FSTT12 (0x1 << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ -#define PMC_FSMR_FSTT13 (0x1 << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ -#define PMC_FSMR_FSTT14 (0x1 << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ -#define PMC_FSMR_FSTT15 (0x1 << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ -#define PMC_FSMR_RTTAL (0x1 << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ -#define PMC_FSMR_RTCAL (0x1 << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ -#define PMC_FSMR_USBAL (0x1 << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ -#define PMC_FSMR_LPM (0x1 << 20) /**< \brief (PMC_FSMR) Low Power Mode */ -/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ -#define PMC_FSPR_FSTP0 (0x1 << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP1 (0x1 << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP2 (0x1 << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP3 (0x1 << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP4 (0x1 << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP5 (0x1 << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP6 (0x1 << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP7 (0x1 << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP8 (0x1 << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP9 (0x1 << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP10 (0x1 << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP11 (0x1 << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP12 (0x1 << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP13 (0x1 << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP14 (0x1 << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP15 (0x1 << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ -#define PMC_FOCR_FOCLR (0x1 << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ -/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */ -#define PMC_WPMR_WPEN (0x1 << 0) /**< \brief (PMC_WPMR) Write Protect Enable */ -#define PMC_WPMR_WPKEY (0xffffff << 8) /**< \brief (PMC_WPMR) Write Protect KEY */ -/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */ -#define PMC_WPSR_WPVS (0x1 << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */ -#define PMC_WPSR_WPVSRC (0xffff << 8) /**< \brief (PMC_WPSR) Write Protect Violation Source */ -/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ -#define PMC_PCER1_PID32 (0x1 << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ -#define PMC_PCER1_PID33 (0x1 << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ -#define PMC_PCER1_PID34 (0x1 << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ -#define PMC_PCER1_PID35 (0x1 << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ -#define PMC_PCER1_PID36 (0x1 << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */ -#define PMC_PCER1_PID37 (0x1 << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ -#define PMC_PCER1_PID38 (0x1 << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */ -#define PMC_PCER1_PID39 (0x1 << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ -#define PMC_PCER1_PID40 (0x1 << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ -#define PMC_PCER1_PID41 (0x1 << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ -#define PMC_PCER1_PID42 (0x1 << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ -#define PMC_PCER1_PID43 (0x1 << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ -#define PMC_PCER1_PID44 (0x1 << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ -#define PMC_PCER1_PID45 (0x1 << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ -#define PMC_PCER1_PID46 (0x1 << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ -#define PMC_PCER1_PID47 (0x1 << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ -#define PMC_PCER1_PID48 (0x1 << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */ -#define PMC_PCER1_PID49 (0x1 << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */ -#define PMC_PCER1_PID50 (0x1 << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */ -#define PMC_PCER1_PID51 (0x1 << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */ -#define PMC_PCER1_PID52 (0x1 << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */ -#define PMC_PCER1_PID53 (0x1 << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */ -#define PMC_PCER1_PID54 (0x1 << 22) /**< \brief (PMC_PCER1) Peripheral Clock 54 Enable */ -#define PMC_PCER1_PID55 (0x1 << 23) /**< \brief (PMC_PCER1) Peripheral Clock 55 Enable */ -#define PMC_PCER1_PID56 (0x1 << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */ -#define PMC_PCER1_PID57 (0x1 << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */ -#define PMC_PCER1_PID58 (0x1 << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */ -#define PMC_PCER1_PID59 (0x1 << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */ -#define PMC_PCER1_PID60 (0x1 << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */ -#define PMC_PCER1_PID61 (0x1 << 29) /**< \brief (PMC_PCER1) Peripheral Clock 61 Enable */ -#define PMC_PCER1_PID62 (0x1 << 30) /**< \brief (PMC_PCER1) Peripheral Clock 62 Enable */ -#define PMC_PCER1_PID63 (0x1 << 31) /**< \brief (PMC_PCER1) Peripheral Clock 63 Enable */ -/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ -#define PMC_PCDR1_PID32 (0x1 << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ -#define PMC_PCDR1_PID33 (0x1 << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ -#define PMC_PCDR1_PID34 (0x1 << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ -#define PMC_PCDR1_PID35 (0x1 << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ -#define PMC_PCDR1_PID36 (0x1 << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */ -#define PMC_PCDR1_PID37 (0x1 << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ -#define PMC_PCDR1_PID38 (0x1 << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */ -#define PMC_PCDR1_PID39 (0x1 << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ -#define PMC_PCDR1_PID40 (0x1 << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ -#define PMC_PCDR1_PID41 (0x1 << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ -#define PMC_PCDR1_PID42 (0x1 << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ -#define PMC_PCDR1_PID43 (0x1 << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ -#define PMC_PCDR1_PID44 (0x1 << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ -#define PMC_PCDR1_PID45 (0x1 << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ -#define PMC_PCDR1_PID46 (0x1 << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ -#define PMC_PCDR1_PID47 (0x1 << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ -#define PMC_PCDR1_PID48 (0x1 << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */ -#define PMC_PCDR1_PID49 (0x1 << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */ -#define PMC_PCDR1_PID50 (0x1 << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */ -#define PMC_PCDR1_PID51 (0x1 << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */ -#define PMC_PCDR1_PID52 (0x1 << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */ -#define PMC_PCDR1_PID53 (0x1 << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */ -#define PMC_PCDR1_PID54 (0x1 << 22) /**< \brief (PMC_PCDR1) Peripheral Clock 54 Disable */ -#define PMC_PCDR1_PID55 (0x1 << 23) /**< \brief (PMC_PCDR1) Peripheral Clock 55 Disable */ -#define PMC_PCDR1_PID56 (0x1 << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */ -#define PMC_PCDR1_PID57 (0x1 << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */ -#define PMC_PCDR1_PID58 (0x1 << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */ -#define PMC_PCDR1_PID59 (0x1 << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */ -#define PMC_PCDR1_PID60 (0x1 << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */ -#define PMC_PCDR1_PID61 (0x1 << 29) /**< \brief (PMC_PCDR1) Peripheral Clock 61 Disable */ -#define PMC_PCDR1_PID62 (0x1 << 30) /**< \brief (PMC_PCDR1) Peripheral Clock 62 Disable */ -#define PMC_PCDR1_PID63 (0x1 << 31) /**< \brief (PMC_PCDR1) Peripheral Clock 63 Disable */ -/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ -#define PMC_PCSR1_PID32 (0x1 << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ -#define PMC_PCSR1_PID33 (0x1 << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ -#define PMC_PCSR1_PID34 (0x1 << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ -#define PMC_PCSR1_PID35 (0x1 << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ -#define PMC_PCSR1_PID36 (0x1 << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */ -#define PMC_PCSR1_PID37 (0x1 << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ -#define PMC_PCSR1_PID38 (0x1 << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */ -#define PMC_PCSR1_PID39 (0x1 << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ -#define PMC_PCSR1_PID40 (0x1 << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ -#define PMC_PCSR1_PID41 (0x1 << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ -#define PMC_PCSR1_PID42 (0x1 << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ -#define PMC_PCSR1_PID43 (0x1 << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ -#define PMC_PCSR1_PID44 (0x1 << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ -#define PMC_PCSR1_PID45 (0x1 << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ -#define PMC_PCSR1_PID46 (0x1 << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ -#define PMC_PCSR1_PID47 (0x1 << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ -#define PMC_PCSR1_PID48 (0x1 << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */ -#define PMC_PCSR1_PID49 (0x1 << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */ -#define PMC_PCSR1_PID50 (0x1 << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */ -#define PMC_PCSR1_PID51 (0x1 << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */ -#define PMC_PCSR1_PID52 (0x1 << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */ -#define PMC_PCSR1_PID53 (0x1 << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */ -#define PMC_PCSR1_PID54 (0x1 << 22) /**< \brief (PMC_PCSR1) Peripheral Clock 54 Status */ -#define PMC_PCSR1_PID55 (0x1 << 23) /**< \brief (PMC_PCSR1) Peripheral Clock 55 Status */ -#define PMC_PCSR1_PID56 (0x1 << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */ -#define PMC_PCSR1_PID57 (0x1 << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */ -#define PMC_PCSR1_PID58 (0x1 << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */ -#define PMC_PCSR1_PID59 (0x1 << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */ -#define PMC_PCSR1_PID60 (0x1 << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */ -#define PMC_PCSR1_PID61 (0x1 << 29) /**< \brief (PMC_PCSR1) Peripheral Clock 61 Status */ -#define PMC_PCSR1_PID62 (0x1 << 30) /**< \brief (PMC_PCSR1) Peripheral Clock 62 Status */ -#define PMC_PCSR1_PID63 (0x1 << 31) /**< \brief (PMC_PCSR1) Peripheral Clock 63 Status */ -/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ -#define PMC_OCR_CAL4 (0x7f << 0) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 Mhz */ -#define PMC_OCR_SEL4 (0x1 << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 Mhz */ -#define PMC_OCR_CAL8 (0x7f << 8) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 Mhz */ -#define PMC_OCR_SEL8 (0x1 << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 Mhz */ -#define PMC_OCR_CAL12 (0x7f << 16) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 Mhz */ -#define PMC_OCR_SEL12 (0x1 << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 Mhz */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PWM Pulse Width Modulation Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief PwmCh_num hardware registers */ -typedef struct { - RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ - RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ - RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ - RwReg PWM_CPDR; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ - RwReg PWM_CPDRUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ - RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ - RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ - RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ -} PwmCh_num; -/** \brief Pwm hardware registers */ -typedef struct { - RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ - WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ - WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ - RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ - WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ - WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ - RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ - RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ - RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ - RwReg Reserved1[1]; - RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ - RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ - WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ - WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ - WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ - RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ - RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ - RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ - RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ - WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ - WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ - WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ - WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ - RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ - RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ - WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ - RwReg PWM_FPV; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */ - RwReg PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ - RwReg Reserved2[3]; - RwReg PWM_ELxMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ - RwReg Reserved3[11]; - RwReg PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */ - RwReg Reserved4[12]; - WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */ - RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */ - RwReg Reserved5[5]; - RwReg PWM_RPR; /**< \brief (Pwm Offset: 0x100) Receive Pointer Register */ - RwReg PWM_RCR; /**< \brief (Pwm Offset: 0x104) Receive Counter Register */ - RwReg PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */ - RwReg PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */ - RwReg PWM_RNPR; /**< \brief (Pwm Offset: 0x110) Receive Next Pointer Register */ - RwReg PWM_RNCR; /**< \brief (Pwm Offset: 0x114) Receive Next Counter Register */ - RwReg PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */ - RwReg PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */ - WoReg PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */ - RoReg PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */ - RwReg Reserved6[2]; - RwReg PWM_CMP0V; /**< \brief (Pwm Offset: 0x130) PWM Comparison 0 Value Register */ - WoReg PWM_CMP0VUPD; /**< \brief (Pwm Offset: 0x134) PWM Comparison 0 Value Update Register */ - RwReg PWM_CMP0M; /**< \brief (Pwm Offset: 0x138) PWM Comparison 0 Mode Register */ - WoReg PWM_CMP0MUPD; /**< \brief (Pwm Offset: 0x13C) PWM Comparison 0 Mode Update Register */ - RwReg PWM_CMP1V; /**< \brief (Pwm Offset: 0x140) PWM Comparison 1 Value Register */ - WoReg PWM_CMP1VUPD; /**< \brief (Pwm Offset: 0x144) PWM Comparison 1 Value Update Register */ - RwReg PWM_CMP1M; /**< \brief (Pwm Offset: 0x148) PWM Comparison 1 Mode Register */ - WoReg PWM_CMP1MUPD; /**< \brief (Pwm Offset: 0x14C) PWM Comparison 1 Mode Update Register */ - RwReg PWM_CMP2V; /**< \brief (Pwm Offset: 0x150) PWM Comparison 2 Value Register */ - WoReg PWM_CMP2VUPD; /**< \brief (Pwm Offset: 0x154) PWM Comparison 2 Value Update Register */ - RwReg PWM_CMP2M; /**< \brief (Pwm Offset: 0x158) PWM Comparison 2 Mode Register */ - WoReg PWM_CMP2MUPD; /**< \brief (Pwm Offset: 0x15C) PWM Comparison 2 Mode Update Register */ - RwReg PWM_CMP3V; /**< \brief (Pwm Offset: 0x160) PWM Comparison 3 Value Register */ - WoReg PWM_CMP3VUPD; /**< \brief (Pwm Offset: 0x164) PWM Comparison 3 Value Update Register */ - RwReg PWM_CMP3M; /**< \brief (Pwm Offset: 0x168) PWM Comparison 3 Mode Register */ - WoReg PWM_CMP3MUPD; /**< \brief (Pwm Offset: 0x16C) PWM Comparison 3 Mode Update Register */ - RwReg PWM_CMP4V; /**< \brief (Pwm Offset: 0x170) PWM Comparison 4 Value Register */ - WoReg PWM_CMP4VUPD; /**< \brief (Pwm Offset: 0x174) PWM Comparison 4 Value Update Register */ - RwReg PWM_CMP4M; /**< \brief (Pwm Offset: 0x178) PWM Comparison 4 Mode Register */ - WoReg PWM_CMP4MUPD; /**< \brief (Pwm Offset: 0x17C) PWM Comparison 4 Mode Update Register */ - RwReg PWM_CMP5V; /**< \brief (Pwm Offset: 0x180) PWM Comparison 5 Value Register */ - WoReg PWM_CMP5VUPD; /**< \brief (Pwm Offset: 0x184) PWM Comparison 5 Value Update Register */ - RwReg PWM_CMP5M; /**< \brief (Pwm Offset: 0x188) PWM Comparison 5 Mode Register */ - WoReg PWM_CMP5MUPD; /**< \brief (Pwm Offset: 0x18C) PWM Comparison 5 Mode Update Register */ - RwReg PWM_CMP6V; /**< \brief (Pwm Offset: 0x190) PWM Comparison 6 Value Register */ - WoReg PWM_CMP6VUPD; /**< \brief (Pwm Offset: 0x194) PWM Comparison 6 Value Update Register */ - RwReg PWM_CMP6M; /**< \brief (Pwm Offset: 0x198) PWM Comparison 6 Mode Register */ - WoReg PWM_CMP6MUPD; /**< \brief (Pwm Offset: 0x19C) PWM Comparison 6 Mode Update Register */ - RwReg PWM_CMP7V; /**< \brief (Pwm Offset: 0x1A0) PWM Comparison 7 Value Register */ - WoReg PWM_CMP7VUPD; /**< \brief (Pwm Offset: 0x1A4) PWM Comparison 7 Value Update Register */ - RwReg PWM_CMP7M; /**< \brief (Pwm Offset: 0x1A8) PWM Comparison 7 Mode Register */ - WoReg PWM_CMP7MUPD; /**< \brief (Pwm Offset: 0x1AC) PWM Comparison 7 Mode Update Register */ - RwReg Reserved7[20]; - PwmCh_num PWM_CH_NUM[4]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ -} Pwm; -#endif /* __ASSEMBLY__ */ -/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ -#define PWM_CLK_DIVA (0xff << 0) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ -#define PWM_CLK_PREA (0xf << 8) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ -#define PWM_CLK_DIVB (0xff << 16) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ -#define PWM_CLK_PREB (0xf << 24) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ -/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ -#define PWM_ENA_CHID0 (0x1 << 0) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID1 (0x1 << 1) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID2 (0x1 << 2) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID3 (0x1 << 3) /**< \brief (PWM_ENA) Channel ID */ -/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ -#define PWM_DIS_CHID0 (0x1 << 0) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID1 (0x1 << 1) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID2 (0x1 << 2) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID3 (0x1 << 3) /**< \brief (PWM_DIS) Channel ID */ -/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ -#define PWM_SR_CHID0 (0x1 << 0) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID1 (0x1 << 1) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID2 (0x1 << 2) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID3 (0x1 << 3) /**< \brief (PWM_SR) Channel ID */ -/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ -#define PWM_IER1_CHID0 (0x1 << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ -#define PWM_IER1_CHID1 (0x1 << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ -#define PWM_IER1_CHID2 (0x1 << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ -#define PWM_IER1_CHID3 (0x1 << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ -#define PWM_IER1_FCHID0 (0x1 << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ -#define PWM_IER1_FCHID1 (0x1 << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ -#define PWM_IER1_FCHID2 (0x1 << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ -#define PWM_IER1_FCHID3 (0x1 << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ -/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ -#define PWM_IDR1_CHID0 (0x1 << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ -#define PWM_IDR1_CHID1 (0x1 << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ -#define PWM_IDR1_CHID2 (0x1 << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ -#define PWM_IDR1_CHID3 (0x1 << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ -#define PWM_IDR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ -#define PWM_IDR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ -#define PWM_IDR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ -#define PWM_IDR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ -/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ -#define PWM_IMR1_CHID0 (0x1 << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ -#define PWM_IMR1_CHID1 (0x1 << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ -#define PWM_IMR1_CHID2 (0x1 << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ -#define PWM_IMR1_CHID3 (0x1 << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ -#define PWM_IMR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ -#define PWM_IMR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ -#define PWM_IMR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ -#define PWM_IMR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ -/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ -#define PWM_ISR1_CHID0 (0x1 << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ -#define PWM_ISR1_CHID1 (0x1 << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ -#define PWM_ISR1_CHID2 (0x1 << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ -#define PWM_ISR1_CHID3 (0x1 << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ -#define PWM_ISR1_FCHID0 (0x1 << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ -#define PWM_ISR1_FCHID1 (0x1 << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ -#define PWM_ISR1_FCHID2 (0x1 << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ -#define PWM_ISR1_FCHID3 (0x1 << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ -/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ -#define PWM_SCM_SYNC0 (0x1 << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ -#define PWM_SCM_SYNC1 (0x1 << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ -#define PWM_SCM_SYNC2 (0x1 << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ -#define PWM_SCM_SYNC3 (0x1 << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ -#define PWM_SCM_UPDM (0x3 << 16) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ -#define PWM_SCM_PTRM (0x1 << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */ -#define PWM_SCM_PTRCS (0x7 << 21) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */ -/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ -#define PWM_SCUC_UPDULOCK (0x1 << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ -/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ -#define PWM_SCUP_UPR (0xf << 0) /**< \brief (PWM_SCUP) Update Period */ -#define PWM_SCUP_UPRCNT (0xf << 4) /**< \brief (PWM_SCUP) Update Period Counter */ -/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ -#define PWM_SCUPUPD_UPRUPD (0xf << 0) /**< \brief (PWM_SCUPUPD) Update Period Update */ -/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ -#define PWM_IER2_WRDY (0x1 << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ -#define PWM_IER2_ENDTX (0x1 << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */ -#define PWM_IER2_TXBUFE (0x1 << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */ -#define PWM_IER2_UNRE (0x1 << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ -#define PWM_IER2_CMPM0 (0x1 << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ -#define PWM_IER2_CMPM1 (0x1 << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ -#define PWM_IER2_CMPM2 (0x1 << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ -#define PWM_IER2_CMPM3 (0x1 << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ -#define PWM_IER2_CMPM4 (0x1 << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ -#define PWM_IER2_CMPM5 (0x1 << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ -#define PWM_IER2_CMPM6 (0x1 << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ -#define PWM_IER2_CMPM7 (0x1 << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ -#define PWM_IER2_CMPU0 (0x1 << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ -#define PWM_IER2_CMPU1 (0x1 << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ -#define PWM_IER2_CMPU2 (0x1 << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ -#define PWM_IER2_CMPU3 (0x1 << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ -#define PWM_IER2_CMPU4 (0x1 << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ -#define PWM_IER2_CMPU5 (0x1 << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ -#define PWM_IER2_CMPU6 (0x1 << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ -#define PWM_IER2_CMPU7 (0x1 << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ -/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ -#define PWM_IDR2_WRDY (0x1 << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ -#define PWM_IDR2_ENDTX (0x1 << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */ -#define PWM_IDR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */ -#define PWM_IDR2_UNRE (0x1 << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ -#define PWM_IDR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ -#define PWM_IDR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ -#define PWM_IDR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ -#define PWM_IDR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ -#define PWM_IDR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ -#define PWM_IDR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ -#define PWM_IDR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ -#define PWM_IDR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ -#define PWM_IDR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ -#define PWM_IDR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ -#define PWM_IDR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ -#define PWM_IDR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ -#define PWM_IDR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ -#define PWM_IDR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ -#define PWM_IDR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ -#define PWM_IDR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ -/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ -#define PWM_IMR2_WRDY (0x1 << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ -#define PWM_IMR2_ENDTX (0x1 << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */ -#define PWM_IMR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */ -#define PWM_IMR2_UNRE (0x1 << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ -#define PWM_IMR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ -#define PWM_IMR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ -#define PWM_IMR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ -#define PWM_IMR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ -#define PWM_IMR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ -#define PWM_IMR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ -#define PWM_IMR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ -#define PWM_IMR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ -#define PWM_IMR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ -#define PWM_IMR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ -#define PWM_IMR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ -#define PWM_IMR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ -#define PWM_IMR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ -#define PWM_IMR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ -#define PWM_IMR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ -#define PWM_IMR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ -/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ -#define PWM_ISR2_WRDY (0x1 << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ -#define PWM_ISR2_ENDTX (0x1 << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */ -#define PWM_ISR2_TXBUFE (0x1 << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */ -#define PWM_ISR2_UNRE (0x1 << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ -#define PWM_ISR2_CMPM0 (0x1 << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ -#define PWM_ISR2_CMPM1 (0x1 << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ -#define PWM_ISR2_CMPM2 (0x1 << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ -#define PWM_ISR2_CMPM3 (0x1 << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ -#define PWM_ISR2_CMPM4 (0x1 << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ -#define PWM_ISR2_CMPM5 (0x1 << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ -#define PWM_ISR2_CMPM6 (0x1 << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ -#define PWM_ISR2_CMPM7 (0x1 << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ -#define PWM_ISR2_CMPU0 (0x1 << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ -#define PWM_ISR2_CMPU1 (0x1 << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ -#define PWM_ISR2_CMPU2 (0x1 << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ -#define PWM_ISR2_CMPU3 (0x1 << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ -#define PWM_ISR2_CMPU4 (0x1 << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ -#define PWM_ISR2_CMPU5 (0x1 << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ -#define PWM_ISR2_CMPU6 (0x1 << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ -#define PWM_ISR2_CMPU7 (0x1 << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ -/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ -#define PWM_OOV_OOVH0 (0x1 << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ -#define PWM_OOV_OOVH1 (0x1 << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ -#define PWM_OOV_OOVH2 (0x1 << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ -#define PWM_OOV_OOVH3 (0x1 << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ -#define PWM_OOV_OOVL0 (0x1 << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ -#define PWM_OOV_OOVL1 (0x1 << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ -#define PWM_OOV_OOVL2 (0x1 << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ -#define PWM_OOV_OOVL3 (0x1 << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ -/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ -#define PWM_OS_OSH0 (0x1 << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ -#define PWM_OS_OSH1 (0x1 << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ -#define PWM_OS_OSH2 (0x1 << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ -#define PWM_OS_OSH3 (0x1 << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ -#define PWM_OS_OSL0 (0x1 << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ -#define PWM_OS_OSL1 (0x1 << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ -#define PWM_OS_OSL2 (0x1 << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ -#define PWM_OS_OSL3 (0x1 << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ -/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ -#define PWM_OSS_OSSH0 (0x1 << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ -#define PWM_OSS_OSSH1 (0x1 << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ -#define PWM_OSS_OSSH2 (0x1 << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ -#define PWM_OSS_OSSH3 (0x1 << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ -#define PWM_OSS_OSSL0 (0x1 << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ -#define PWM_OSS_OSSL1 (0x1 << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ -#define PWM_OSS_OSSL2 (0x1 << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ -#define PWM_OSS_OSSL3 (0x1 << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ -/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ -#define PWM_OSC_OSCH0 (0x1 << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ -#define PWM_OSC_OSCH1 (0x1 << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ -#define PWM_OSC_OSCH2 (0x1 << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ -#define PWM_OSC_OSCH3 (0x1 << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ -#define PWM_OSC_OSCL0 (0x1 << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ -#define PWM_OSC_OSCL1 (0x1 << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ -#define PWM_OSC_OSCL2 (0x1 << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ -#define PWM_OSC_OSCL3 (0x1 << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ -/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ -#define PWM_OSSUPD_OSSUPH0 (0x1 << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ -#define PWM_OSSUPD_OSSUPH1 (0x1 << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ -#define PWM_OSSUPD_OSSUPH2 (0x1 << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ -#define PWM_OSSUPD_OSSUPH3 (0x1 << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ -#define PWM_OSSUPD_OSSUPL0 (0x1 << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ -#define PWM_OSSUPD_OSSUPL1 (0x1 << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ -#define PWM_OSSUPD_OSSUPL2 (0x1 << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ -#define PWM_OSSUPD_OSSUPL3 (0x1 << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ -/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ -#define PWM_OSCUPD_OSCUPH0 (0x1 << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ -#define PWM_OSCUPD_OSCUPH1 (0x1 << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ -#define PWM_OSCUPD_OSCUPH2 (0x1 << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ -#define PWM_OSCUPD_OSCUPH3 (0x1 << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ -#define PWM_OSCUPD_OSCUPL0 (0x1 << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ -#define PWM_OSCUPD_OSCUPL1 (0x1 << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ -#define PWM_OSCUPD_OSCUPL2 (0x1 << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ -#define PWM_OSCUPD_OSCUPL3 (0x1 << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ -/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ -#define PWM_FMR_FPOL0 (0x1 << 0) /**< \brief (PWM_FMR) Fault 0 Polarity */ -#define PWM_FMR_FPOL1 (0x1 << 1) /**< \brief (PWM_FMR) Fault 1 Polarity */ -#define PWM_FMR_FPOL2 (0x1 << 2) /**< \brief (PWM_FMR) Fault 2 Polarity */ -#define PWM_FMR_FPOL3 (0x1 << 3) /**< \brief (PWM_FMR) Fault 3 Polarity */ -#define PWM_FMR_FMOD0 (0x1 << 8) /**< \brief (PWM_FMR) Fault 0 Activation Mode */ -#define PWM_FMR_FMOD1 (0x1 << 9) /**< \brief (PWM_FMR) Fault 1 Activation Mode */ -#define PWM_FMR_FMOD2 (0x1 << 10) /**< \brief (PWM_FMR) Fault 2 Activation Mode */ -#define PWM_FMR_FMOD3 (0x1 << 11) /**< \brief (PWM_FMR) Fault 3 Activation Mode */ -#define PWM_FMR_FFIL0 (0x1 << 16) /**< \brief (PWM_FMR) Fault 0 Filtering */ -#define PWM_FMR_FFIL1 (0x1 << 17) /**< \brief (PWM_FMR) Fault 1 Filtering */ -#define PWM_FMR_FFIL2 (0x1 << 18) /**< \brief (PWM_FMR) Fault 2 Filtering */ -#define PWM_FMR_FFIL3 (0x1 << 19) /**< \brief (PWM_FMR) Fault 3 Filtering */ -/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ -#define PWM_FSR_FIV0 (0x1 << 0) /**< \brief (PWM_FSR) Fault Input 0 Value */ -#define PWM_FSR_FIV1 (0x1 << 1) /**< \brief (PWM_FSR) Fault Input 1 Value */ -#define PWM_FSR_FIV2 (0x1 << 2) /**< \brief (PWM_FSR) Fault Input 2 Value */ -#define PWM_FSR_FIV3 (0x1 << 3) /**< \brief (PWM_FSR) Fault Input 3 Value */ -#define PWM_FSR_FS0 (0x1 << 8) /**< \brief (PWM_FSR) Fault 0 Status */ -#define PWM_FSR_FS1 (0x1 << 9) /**< \brief (PWM_FSR) Fault 1 Status */ -#define PWM_FSR_FS2 (0x1 << 10) /**< \brief (PWM_FSR) Fault 2 Status */ -#define PWM_FSR_FS3 (0x1 << 11) /**< \brief (PWM_FSR) Fault 3 Status */ -/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ -#define PWM_FCR_FCLR0 (0x1 << 0) /**< \brief (PWM_FCR) Fault 0 Clear */ -#define PWM_FCR_FCLR1 (0x1 << 1) /**< \brief (PWM_FCR) Fault 1 Clear */ -#define PWM_FCR_FCLR2 (0x1 << 2) /**< \brief (PWM_FCR) Fault 2 Clear */ -#define PWM_FCR_FCLR3 (0x1 << 3) /**< \brief (PWM_FCR) Fault 3 Clear */ -/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */ -#define PWM_FPV_FPVH0 (0x1 << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */ -#define PWM_FPV_FPVH1 (0x1 << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */ -#define PWM_FPV_FPVH2 (0x1 << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */ -#define PWM_FPV_FPVH3 (0x1 << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */ -#define PWM_FPV_FPVL0 (0x1 << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */ -#define PWM_FPV_FPVL1 (0x1 << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */ -#define PWM_FPV_FPVL2 (0x1 << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */ -#define PWM_FPV_FPVL3 (0x1 << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */ -/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ -#define PWM_FPE_FPE0 (0xff << 0) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 0 for channel x */ -#define PWM_FPE_FPE1 (0xff << 8) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 1 for channel x */ -#define PWM_FPE_FPE2 (0xff << 16) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 2 for channel x */ -#define PWM_FPE_FPE3 (0xff << 24) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 3 for channel x */ -/* -------- PWM_ELxMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ -#define PWM_ELxMR_CSEL0 (0x1 << 0) /**< \brief (PWM_ELxMR[2]) Comparison 0 Selection */ -#define PWM_ELxMR_CSEL1 (0x1 << 1) /**< \brief (PWM_ELxMR[2]) Comparison 1 Selection */ -#define PWM_ELxMR_CSEL2 (0x1 << 2) /**< \brief (PWM_ELxMR[2]) Comparison 2 Selection */ -#define PWM_ELxMR_CSEL3 (0x1 << 3) /**< \brief (PWM_ELxMR[2]) Comparison 3 Selection */ -#define PWM_ELxMR_CSEL4 (0x1 << 4) /**< \brief (PWM_ELxMR[2]) Comparison 4 Selection */ -#define PWM_ELxMR_CSEL5 (0x1 << 5) /**< \brief (PWM_ELxMR[2]) Comparison 5 Selection */ -#define PWM_ELxMR_CSEL6 (0x1 << 6) /**< \brief (PWM_ELxMR[2]) Comparison 6 Selection */ -#define PWM_ELxMR_CSEL7 (0x1 << 7) /**< \brief (PWM_ELxMR[2]) Comparison 7 Selection */ -/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */ -#define PWM_SMMR_GCEN0 (0x1 << 0) /**< \brief (PWM_SMMR) Gray Count ENable */ -#define PWM_SMMR_GCEN1 (0x1 << 1) /**< \brief (PWM_SMMR) Gray Count ENable */ -#define PWM_SMMR_DOWN0 (0x1 << 16) /**< \brief (PWM_SMMR) DOWN Count */ -#define PWM_SMMR_DOWN1 (0x1 << 17) /**< \brief (PWM_SMMR) DOWN Count */ -/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */ -#define PWM_WPCR_WPCMD (0x3 << 0) /**< \brief (PWM_WPCR) Write Protect Command */ -#define PWM_WPCR_WPRG0 (0x1 << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */ -#define PWM_WPCR_WPRG1 (0x1 << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */ -#define PWM_WPCR_WPRG2 (0x1 << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */ -#define PWM_WPCR_WPRG3 (0x1 << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */ -#define PWM_WPCR_WPRG4 (0x1 << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */ -#define PWM_WPCR_WPRG5 (0x1 << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */ -#define PWM_WPCR_WPKEY (0xffffff << 8) /**< \brief (PWM_WPCR) Write Protect Key */ -/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */ -#define PWM_WPSR_WPSWS0 (0x1 << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS1 (0x1 << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS2 (0x1 << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS3 (0x1 << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS4 (0x1 << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS5 (0x1 << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPVS (0x1 << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ -#define PWM_WPSR_WPHWS0 (0x1 << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS1 (0x1 << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS2 (0x1 << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS3 (0x1 << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS4 (0x1 << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS5 (0x1 << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPVSRC (0xffff << 16) /**< \brief (PWM_WPSR) Write Protect Violation Source */ -/* -------- PWM_RPR : (PWM Offset: 0x100) Receive Pointer Register -------- */ -#define PWM_RPR_RXPTR (0xffffffff << 0) /**< \brief (PWM_RPR) Receive Pointer Register */ -/* -------- PWM_RCR : (PWM Offset: 0x104) Receive Counter Register -------- */ -#define PWM_RCR_RXCTR (0xffff << 0) /**< \brief (PWM_RCR) Receive Counter Register */ -/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */ -#define PWM_TPR_TXPTR (0xffffffff << 0) /**< \brief (PWM_TPR) Transmit Counter Register */ -/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */ -#define PWM_TCR_TXCTR (0xffff << 0) /**< \brief (PWM_TCR) Transmit Counter Register */ -/* -------- PWM_RNPR : (PWM Offset: 0x110) Receive Next Pointer Register -------- */ -#define PWM_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PWM_RNPR) Receive Next Pointer */ -/* -------- PWM_RNCR : (PWM Offset: 0x114) Receive Next Counter Register -------- */ -#define PWM_RNCR_RXNCTR (0xffff << 0) /**< \brief (PWM_RNCR) Receive Next Counter */ -/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */ -#define PWM_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PWM_TNPR) Transmit Next Pointer */ -/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */ -#define PWM_TNCR_TXNCTR (0xffff << 0) /**< \brief (PWM_TNCR) Transmit Counter Next */ -/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */ -#define PWM_PTCR_RXTEN (0x1 << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */ -#define PWM_PTCR_RXTDIS (0x1 << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */ -#define PWM_PTCR_TXTEN (0x1 << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */ -#define PWM_PTCR_TXTDIS (0x1 << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */ -/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */ -#define PWM_PTSR_RXTEN (0x1 << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */ -#define PWM_PTSR_TXTEN (0x1 << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */ -/* -------- PWM_CMP0V : (PWM Offset: 0x130) PWM Comparison 0 Value Register -------- */ -#define PWM_CMP0V_CV (0xffffff << 0) /**< \brief (PWM_CMP0V) Comparison x Value */ -#define PWM_CMP0V_CVM (0x1 << 24) /**< \brief (PWM_CMP0V) Comparison x Value Mode */ -/* -------- PWM_CMP0VUPD : (PWM Offset: 0x134) PWM Comparison 0 Value Update Register -------- */ -#define PWM_CMP0VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP0VUPD) Comparison x Value Update */ -#define PWM_CMP0VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP0VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP0M : (PWM Offset: 0x138) PWM Comparison 0 Mode Register -------- */ -#define PWM_CMP0M_CEN (0x1 << 0) /**< \brief (PWM_CMP0M) Comparison x Enable */ -#define PWM_CMP0M_CTR (0xf << 4) /**< \brief (PWM_CMP0M) Comparison x Trigger */ -#define PWM_CMP0M_CPR (0xf << 8) /**< \brief (PWM_CMP0M) Comparison x Period */ -#define PWM_CMP0M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP0M) Comparison x Period Counter */ -#define PWM_CMP0M_CUPR (0xf << 16) /**< \brief (PWM_CMP0M) Comparison x Update Period */ -#define PWM_CMP0M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP0M) Comparison x Update Period Counter */ -/* -------- PWM_CMP0MUPD : (PWM Offset: 0x13C) PWM Comparison 0 Mode Update Register -------- */ -#define PWM_CMP0MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP0MUPD) Comparison x Enable Update */ -#define PWM_CMP0MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP0MUPD) Comparison x Trigger Update */ -#define PWM_CMP0MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP0MUPD) Comparison x Period Update */ -#define PWM_CMP0MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP0MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP1V : (PWM Offset: 0x140) PWM Comparison 1 Value Register -------- */ -#define PWM_CMP1V_CV (0xffffff << 0) /**< \brief (PWM_CMP1V) Comparison x Value */ -#define PWM_CMP1V_CVM (0x1 << 24) /**< \brief (PWM_CMP1V) Comparison x Value Mode */ -/* -------- PWM_CMP1VUPD : (PWM Offset: 0x144) PWM Comparison 1 Value Update Register -------- */ -#define PWM_CMP1VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP1VUPD) Comparison x Value Update */ -#define PWM_CMP1VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP1VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP1M : (PWM Offset: 0x148) PWM Comparison 1 Mode Register -------- */ -#define PWM_CMP1M_CEN (0x1 << 0) /**< \brief (PWM_CMP1M) Comparison x Enable */ -#define PWM_CMP1M_CTR (0xf << 4) /**< \brief (PWM_CMP1M) Comparison x Trigger */ -#define PWM_CMP1M_CPR (0xf << 8) /**< \brief (PWM_CMP1M) Comparison x Period */ -#define PWM_CMP1M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP1M) Comparison x Period Counter */ -#define PWM_CMP1M_CUPR (0xf << 16) /**< \brief (PWM_CMP1M) Comparison x Update Period */ -#define PWM_CMP1M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP1M) Comparison x Update Period Counter */ -/* -------- PWM_CMP1MUPD : (PWM Offset: 0x14C) PWM Comparison 1 Mode Update Register -------- */ -#define PWM_CMP1MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP1MUPD) Comparison x Enable Update */ -#define PWM_CMP1MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP1MUPD) Comparison x Trigger Update */ -#define PWM_CMP1MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP1MUPD) Comparison x Period Update */ -#define PWM_CMP1MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP1MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP2V : (PWM Offset: 0x150) PWM Comparison 2 Value Register -------- */ -#define PWM_CMP2V_CV (0xffffff << 0) /**< \brief (PWM_CMP2V) Comparison x Value */ -#define PWM_CMP2V_CVM (0x1 << 24) /**< \brief (PWM_CMP2V) Comparison x Value Mode */ -/* -------- PWM_CMP2VUPD : (PWM Offset: 0x154) PWM Comparison 2 Value Update Register -------- */ -#define PWM_CMP2VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP2VUPD) Comparison x Value Update */ -#define PWM_CMP2VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP2VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP2M : (PWM Offset: 0x158) PWM Comparison 2 Mode Register -------- */ -#define PWM_CMP2M_CEN (0x1 << 0) /**< \brief (PWM_CMP2M) Comparison x Enable */ -#define PWM_CMP2M_CTR (0xf << 4) /**< \brief (PWM_CMP2M) Comparison x Trigger */ -#define PWM_CMP2M_CPR (0xf << 8) /**< \brief (PWM_CMP2M) Comparison x Period */ -#define PWM_CMP2M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP2M) Comparison x Period Counter */ -#define PWM_CMP2M_CUPR (0xf << 16) /**< \brief (PWM_CMP2M) Comparison x Update Period */ -#define PWM_CMP2M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP2M) Comparison x Update Period Counter */ -/* -------- PWM_CMP2MUPD : (PWM Offset: 0x15C) PWM Comparison 2 Mode Update Register -------- */ -#define PWM_CMP2MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP2MUPD) Comparison x Enable Update */ -#define PWM_CMP2MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP2MUPD) Comparison x Trigger Update */ -#define PWM_CMP2MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP2MUPD) Comparison x Period Update */ -#define PWM_CMP2MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP2MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP3V : (PWM Offset: 0x160) PWM Comparison 3 Value Register -------- */ -#define PWM_CMP3V_CV (0xffffff << 0) /**< \brief (PWM_CMP3V) Comparison x Value */ -#define PWM_CMP3V_CVM (0x1 << 24) /**< \brief (PWM_CMP3V) Comparison x Value Mode */ -/* -------- PWM_CMP3VUPD : (PWM Offset: 0x164) PWM Comparison 3 Value Update Register -------- */ -#define PWM_CMP3VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP3VUPD) Comparison x Value Update */ -#define PWM_CMP3VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP3VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP3M : (PWM Offset: 0x168) PWM Comparison 3 Mode Register -------- */ -#define PWM_CMP3M_CEN (0x1 << 0) /**< \brief (PWM_CMP3M) Comparison x Enable */ -#define PWM_CMP3M_CTR (0xf << 4) /**< \brief (PWM_CMP3M) Comparison x Trigger */ -#define PWM_CMP3M_CPR (0xf << 8) /**< \brief (PWM_CMP3M) Comparison x Period */ -#define PWM_CMP3M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP3M) Comparison x Period Counter */ -#define PWM_CMP3M_CUPR (0xf << 16) /**< \brief (PWM_CMP3M) Comparison x Update Period */ -#define PWM_CMP3M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP3M) Comparison x Update Period Counter */ -/* -------- PWM_CMP3MUPD : (PWM Offset: 0x16C) PWM Comparison 3 Mode Update Register -------- */ -#define PWM_CMP3MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP3MUPD) Comparison x Enable Update */ -#define PWM_CMP3MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP3MUPD) Comparison x Trigger Update */ -#define PWM_CMP3MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP3MUPD) Comparison x Period Update */ -#define PWM_CMP3MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP3MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP4V : (PWM Offset: 0x170) PWM Comparison 4 Value Register -------- */ -#define PWM_CMP4V_CV (0xffffff << 0) /**< \brief (PWM_CMP4V) Comparison x Value */ -#define PWM_CMP4V_CVM (0x1 << 24) /**< \brief (PWM_CMP4V) Comparison x Value Mode */ -/* -------- PWM_CMP4VUPD : (PWM Offset: 0x174) PWM Comparison 4 Value Update Register -------- */ -#define PWM_CMP4VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP4VUPD) Comparison x Value Update */ -#define PWM_CMP4VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP4VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP4M : (PWM Offset: 0x178) PWM Comparison 4 Mode Register -------- */ -#define PWM_CMP4M_CEN (0x1 << 0) /**< \brief (PWM_CMP4M) Comparison x Enable */ -#define PWM_CMP4M_CTR (0xf << 4) /**< \brief (PWM_CMP4M) Comparison x Trigger */ -#define PWM_CMP4M_CPR (0xf << 8) /**< \brief (PWM_CMP4M) Comparison x Period */ -#define PWM_CMP4M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP4M) Comparison x Period Counter */ -#define PWM_CMP4M_CUPR (0xf << 16) /**< \brief (PWM_CMP4M) Comparison x Update Period */ -#define PWM_CMP4M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP4M) Comparison x Update Period Counter */ -/* -------- PWM_CMP4MUPD : (PWM Offset: 0x17C) PWM Comparison 4 Mode Update Register -------- */ -#define PWM_CMP4MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP4MUPD) Comparison x Enable Update */ -#define PWM_CMP4MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP4MUPD) Comparison x Trigger Update */ -#define PWM_CMP4MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP4MUPD) Comparison x Period Update */ -#define PWM_CMP4MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP4MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP5V : (PWM Offset: 0x180) PWM Comparison 5 Value Register -------- */ -#define PWM_CMP5V_CV (0xffffff << 0) /**< \brief (PWM_CMP5V) Comparison x Value */ -#define PWM_CMP5V_CVM (0x1 << 24) /**< \brief (PWM_CMP5V) Comparison x Value Mode */ -/* -------- PWM_CMP5VUPD : (PWM Offset: 0x184) PWM Comparison 5 Value Update Register -------- */ -#define PWM_CMP5VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP5VUPD) Comparison x Value Update */ -#define PWM_CMP5VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP5VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP5M : (PWM Offset: 0x188) PWM Comparison 5 Mode Register -------- */ -#define PWM_CMP5M_CEN (0x1 << 0) /**< \brief (PWM_CMP5M) Comparison x Enable */ -#define PWM_CMP5M_CTR (0xf << 4) /**< \brief (PWM_CMP5M) Comparison x Trigger */ -#define PWM_CMP5M_CPR (0xf << 8) /**< \brief (PWM_CMP5M) Comparison x Period */ -#define PWM_CMP5M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP5M) Comparison x Period Counter */ -#define PWM_CMP5M_CUPR (0xf << 16) /**< \brief (PWM_CMP5M) Comparison x Update Period */ -#define PWM_CMP5M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP5M) Comparison x Update Period Counter */ -/* -------- PWM_CMP5MUPD : (PWM Offset: 0x18C) PWM Comparison 5 Mode Update Register -------- */ -#define PWM_CMP5MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP5MUPD) Comparison x Enable Update */ -#define PWM_CMP5MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP5MUPD) Comparison x Trigger Update */ -#define PWM_CMP5MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP5MUPD) Comparison x Period Update */ -#define PWM_CMP5MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP5MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP6V : (PWM Offset: 0x190) PWM Comparison 6 Value Register -------- */ -#define PWM_CMP6V_CV (0xffffff << 0) /**< \brief (PWM_CMP6V) Comparison x Value */ -#define PWM_CMP6V_CVM (0x1 << 24) /**< \brief (PWM_CMP6V) Comparison x Value Mode */ -/* -------- PWM_CMP6VUPD : (PWM Offset: 0x194) PWM Comparison 6 Value Update Register -------- */ -#define PWM_CMP6VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP6VUPD) Comparison x Value Update */ -#define PWM_CMP6VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP6VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP6M : (PWM Offset: 0x198) PWM Comparison 6 Mode Register -------- */ -#define PWM_CMP6M_CEN (0x1 << 0) /**< \brief (PWM_CMP6M) Comparison x Enable */ -#define PWM_CMP6M_CTR (0xf << 4) /**< \brief (PWM_CMP6M) Comparison x Trigger */ -#define PWM_CMP6M_CPR (0xf << 8) /**< \brief (PWM_CMP6M) Comparison x Period */ -#define PWM_CMP6M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP6M) Comparison x Period Counter */ -#define PWM_CMP6M_CUPR (0xf << 16) /**< \brief (PWM_CMP6M) Comparison x Update Period */ -#define PWM_CMP6M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP6M) Comparison x Update Period Counter */ -/* -------- PWM_CMP6MUPD : (PWM Offset: 0x19C) PWM Comparison 6 Mode Update Register -------- */ -#define PWM_CMP6MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP6MUPD) Comparison x Enable Update */ -#define PWM_CMP6MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP6MUPD) Comparison x Trigger Update */ -#define PWM_CMP6MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP6MUPD) Comparison x Period Update */ -#define PWM_CMP6MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP6MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP7V : (PWM Offset: 0x1A0) PWM Comparison 7 Value Register -------- */ -#define PWM_CMP7V_CV (0xffffff << 0) /**< \brief (PWM_CMP7V) Comparison x Value */ -#define PWM_CMP7V_CVM (0x1 << 24) /**< \brief (PWM_CMP7V) Comparison x Value Mode */ -/* -------- PWM_CMP7VUPD : (PWM Offset: 0x1A4) PWM Comparison 7 Value Update Register -------- */ -#define PWM_CMP7VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP7VUPD) Comparison x Value Update */ -#define PWM_CMP7VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP7VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP7M : (PWM Offset: 0x1A8) PWM Comparison 7 Mode Register -------- */ -#define PWM_CMP7M_CEN (0x1 << 0) /**< \brief (PWM_CMP7M) Comparison x Enable */ -#define PWM_CMP7M_CTR (0xf << 4) /**< \brief (PWM_CMP7M) Comparison x Trigger */ -#define PWM_CMP7M_CPR (0xf << 8) /**< \brief (PWM_CMP7M) Comparison x Period */ -#define PWM_CMP7M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP7M) Comparison x Period Counter */ -#define PWM_CMP7M_CUPR (0xf << 16) /**< \brief (PWM_CMP7M) Comparison x Update Period */ -#define PWM_CMP7M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP7M) Comparison x Update Period Counter */ -/* -------- PWM_CMP7MUPD : (PWM Offset: 0x1AC) PWM Comparison 7 Mode Update Register -------- */ -#define PWM_CMP7MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP7MUPD) Comparison x Enable Update */ -#define PWM_CMP7MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP7MUPD) Comparison x Trigger Update */ -#define PWM_CMP7MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP7MUPD) Comparison x Period Update */ -#define PWM_CMP7MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP7MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMR0 : (PWM Offset: 0x200) PWM Channel Mode Register (ch_num = 0) -------- */ -#define PWM_CMR0_CPRE (0xf << 0) /**< \brief (PWM_CMR0) Channel Pre-scaler */ -#define PWM_CMR0_CALG (0x1 << 8) /**< \brief (PWM_CMR0) Channel Alignment */ -#define PWM_CMR0_CPOL (0x1 << 9) /**< \brief (PWM_CMR0) Channel Polarity */ -#define PWM_CMR0_CES (0x1 << 10) /**< \brief (PWM_CMR0) Counter Event Selection */ -#define PWM_CMR0_DTE (0x1 << 16) /**< \brief (PWM_CMR0) Dead-Time Generator Enable */ -#define PWM_CMR0_DTHI (0x1 << 17) /**< \brief (PWM_CMR0) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR0_DTLI (0x1 << 18) /**< \brief (PWM_CMR0) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY0 : (PWM Offset: 0x204) PWM Channel Duty Cycle Register (ch_num = 0) -------- */ -#define PWM_CDTY0_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY0) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD0 : (PWM Offset: 0x208) PWM Channel Duty Cycle Update Register (ch_num = 0) -------- */ -#define PWM_CDTYUPD0_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD0) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD0 : (PWM Offset: 0x20C) PWM Channel Period Register (ch_num = 0) -------- */ -#define PWM_CPRD0_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD0) Channel Period */ -/* -------- PWM_CPRDUPD0 : (PWM Offset: 0x210) PWM Channel Period Update Register (ch_num = 0) -------- */ -#define PWM_CPRDUPD0_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD0) Channel Period Update */ -/* -------- PWM_CCNT0 : (PWM Offset: 0x214) PWM Channel Counter Register (ch_num = 0) -------- */ -#define PWM_CCNT0_CNT (0xffffff << 0) /**< \brief (PWM_CCNT0) Channel Counter Register */ -/* -------- PWM_DT0 : (PWM Offset: 0x218) PWM Channel Dead Time Register (ch_num = 0) -------- */ -#define PWM_DT0_DTH (0xffff << 0) /**< \brief (PWM_DT0) Dead-Time Value for PWMHx Output */ -#define PWM_DT0_DTL (0xffff << 16) /**< \brief (PWM_DT0) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD0 : (PWM Offset: 0x21C) PWM Channel Dead Time Update Register (ch_num = 0) -------- */ -#define PWM_DTUPD0_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD0_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR1 : (PWM Offset: 0x220) PWM Channel Mode Register (ch_num = 1) -------- */ -#define PWM_CMR1_CPRE (0xf << 0) /**< \brief (PWM_CMR1) Channel Pre-scaler */ -#define PWM_CMR1_CALG (0x1 << 8) /**< \brief (PWM_CMR1) Channel Alignment */ -#define PWM_CMR1_CPOL (0x1 << 9) /**< \brief (PWM_CMR1) Channel Polarity */ -#define PWM_CMR1_CES (0x1 << 10) /**< \brief (PWM_CMR1) Counter Event Selection */ -#define PWM_CMR1_DTE (0x1 << 16) /**< \brief (PWM_CMR1) Dead-Time Generator Enable */ -#define PWM_CMR1_DTHI (0x1 << 17) /**< \brief (PWM_CMR1) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR1_DTLI (0x1 << 18) /**< \brief (PWM_CMR1) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY1 : (PWM Offset: 0x224) PWM Channel Duty Cycle Register (ch_num = 1) -------- */ -#define PWM_CDTY1_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY1) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD1 : (PWM Offset: 0x228) PWM Channel Duty Cycle Update Register (ch_num = 1) -------- */ -#define PWM_CDTYUPD1_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD1) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD1 : (PWM Offset: 0x22C) PWM Channel Period Register (ch_num = 1) -------- */ -#define PWM_CPRD1_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD1) Channel Period */ -/* -------- PWM_CPRDUPD1 : (PWM Offset: 0x230) PWM Channel Period Update Register (ch_num = 1) -------- */ -#define PWM_CPRDUPD1_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD1) Channel Period Update */ -/* -------- PWM_CCNT1 : (PWM Offset: 0x234) PWM Channel Counter Register (ch_num = 1) -------- */ -#define PWM_CCNT1_CNT (0xffffff << 0) /**< \brief (PWM_CCNT1) Channel Counter Register */ -/* -------- PWM_DT1 : (PWM Offset: 0x238) PWM Channel Dead Time Register (ch_num = 1) -------- */ -#define PWM_DT1_DTH (0xffff << 0) /**< \brief (PWM_DT1) Dead-Time Value for PWMHx Output */ -#define PWM_DT1_DTL (0xffff << 16) /**< \brief (PWM_DT1) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD1 : (PWM Offset: 0x23C) PWM Channel Dead Time Update Register (ch_num = 1) -------- */ -#define PWM_DTUPD1_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD1_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR2 : (PWM Offset: 0x240) PWM Channel Mode Register (ch_num = 2) -------- */ -#define PWM_CMR2_CPRE (0xf << 0) /**< \brief (PWM_CMR2) Channel Pre-scaler */ -#define PWM_CMR2_CALG (0x1 << 8) /**< \brief (PWM_CMR2) Channel Alignment */ -#define PWM_CMR2_CPOL (0x1 << 9) /**< \brief (PWM_CMR2) Channel Polarity */ -#define PWM_CMR2_CES (0x1 << 10) /**< \brief (PWM_CMR2) Counter Event Selection */ -#define PWM_CMR2_DTE (0x1 << 16) /**< \brief (PWM_CMR2) Dead-Time Generator Enable */ -#define PWM_CMR2_DTHI (0x1 << 17) /**< \brief (PWM_CMR2) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR2_DTLI (0x1 << 18) /**< \brief (PWM_CMR2) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY2 : (PWM Offset: 0x244) PWM Channel Duty Cycle Register (ch_num = 2) -------- */ -#define PWM_CDTY2_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY2) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD2 : (PWM Offset: 0x248) PWM Channel Duty Cycle Update Register (ch_num = 2) -------- */ -#define PWM_CDTYUPD2_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD2) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD2 : (PWM Offset: 0x24C) PWM Channel Period Register (ch_num = 2) -------- */ -#define PWM_CPRD2_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD2) Channel Period */ -/* -------- PWM_CPRDUPD2 : (PWM Offset: 0x250) PWM Channel Period Update Register (ch_num = 2) -------- */ -#define PWM_CPRDUPD2_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD2) Channel Period Update */ -/* -------- PWM_CCNT2 : (PWM Offset: 0x254) PWM Channel Counter Register (ch_num = 2) -------- */ -#define PWM_CCNT2_CNT (0xffffff << 0) /**< \brief (PWM_CCNT2) Channel Counter Register */ -/* -------- PWM_DT2 : (PWM Offset: 0x258) PWM Channel Dead Time Register (ch_num = 2) -------- */ -#define PWM_DT2_DTH (0xffff << 0) /**< \brief (PWM_DT2) Dead-Time Value for PWMHx Output */ -#define PWM_DT2_DTL (0xffff << 16) /**< \brief (PWM_DT2) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD2 : (PWM Offset: 0x25C) PWM Channel Dead Time Update Register (ch_num = 2) -------- */ -#define PWM_DTUPD2_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD2_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR3 : (PWM Offset: 0x260) PWM Channel Mode Register (ch_num = 3) -------- */ -#define PWM_CMR3_CPRE (0xf << 0) /**< \brief (PWM_CMR3) Channel Pre-scaler */ -#define PWM_CMR3_CALG (0x1 << 8) /**< \brief (PWM_CMR3) Channel Alignment */ -#define PWM_CMR3_CPOL (0x1 << 9) /**< \brief (PWM_CMR3) Channel Polarity */ -#define PWM_CMR3_CES (0x1 << 10) /**< \brief (PWM_CMR3) Counter Event Selection */ -#define PWM_CMR3_DTE (0x1 << 16) /**< \brief (PWM_CMR3) Dead-Time Generator Enable */ -#define PWM_CMR3_DTHI (0x1 << 17) /**< \brief (PWM_CMR3) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR3_DTLI (0x1 << 18) /**< \brief (PWM_CMR3) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY3 : (PWM Offset: 0x264) PWM Channel Duty Cycle Register (ch_num = 3) -------- */ -#define PWM_CDTY3_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY3) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD3 : (PWM Offset: 0x268) PWM Channel Duty Cycle Update Register (ch_num = 3) -------- */ -#define PWM_CDTYUPD3_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD3) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD3 : (PWM Offset: 0x26C) PWM Channel Period Register (ch_num = 3) -------- */ -#define PWM_CPRD3_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD3) Channel Period */ -/* -------- PWM_CPRDUPD3 : (PWM Offset: 0x270) PWM Channel Period Update Register (ch_num = 3) -------- */ -#define PWM_CPRDUPD3_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD3) Channel Period Update */ -/* -------- PWM_CCNT3 : (PWM Offset: 0x274) PWM Channel Counter Register (ch_num = 3) -------- */ -#define PWM_CCNT3_CNT (0xffffff << 0) /**< \brief (PWM_CCNT3) Channel Counter Register */ -/* -------- PWM_DT3 : (PWM Offset: 0x278) PWM Channel Dead Time Register (ch_num = 3) -------- */ -#define PWM_DT3_DTH (0xffff << 0) /**< \brief (PWM_DT3) Dead-Time Value for PWMHx Output */ -#define PWM_DT3_DTL (0xffff << 16) /**< \brief (PWM_DT3) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD3 : (PWM Offset: 0x27C) PWM Channel Dead Time Update Register (ch_num = 3) -------- */ -#define PWM_DTUPD3_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD3_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMLx Output */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Reset Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_RSTC Reset Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rstc hardware registers */ -typedef struct { - WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ - RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ - RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ -} Rstc; -#endif /* __ASSEMBLY__ */ -/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ -#define RSTC_CR_PROCRST (0x1 << 0) /**< \brief (RSTC_CR) Processor Reset */ -#define RSTC_CR_PERRST (0x1 << 2) /**< \brief (RSTC_CR) Peripheral Reset */ -#define RSTC_CR_EXTRST (0x1 << 3) /**< \brief (RSTC_CR) External Reset */ -#define RSTC_CR_KEY (0xff << 24) /**< \brief (RSTC_CR) Password */ -/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ -#define RSTC_SR_URSTS (0x1 << 0) /**< \brief (RSTC_SR) User Reset Status */ -#define RSTC_SR_RSTTYP (0x7 << 8) /**< \brief (RSTC_SR) Reset Type */ -#define RSTC_SR_NRSTL (0x1 << 16) /**< \brief (RSTC_SR) NRST Pin Level */ -#define RSTC_SR_SRCMP (0x1 << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ -/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ -#define RSTC_MR_URSTEN (0x1 << 0) /**< \brief (RSTC_MR) User Reset Enable */ -#define RSTC_MR_URSTIEN (0x1 << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ -#define RSTC_MR_ERSTL (0xf << 8) /**< \brief (RSTC_MR) External Reset Length */ -#define RSTC_MR_KEY (0xff << 24) /**< \brief (RSTC_MR) Password */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Real-time Clock */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_RTC Real-time Clock */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rtc hardware registers */ -typedef struct { - RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ - RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ - RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ - RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ - RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ - RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ - RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ - WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ - WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ - WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ - RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ - RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ -} Rtc; -#endif /* __ASSEMBLY__ */ -/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ -#define RTC_CR_UPDTIM (0x1 << 0) /**< \brief (RTC_CR) Update Request Time Register */ -#define RTC_CR_UPDCAL (0x1 << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ -#define RTC_CR_TIMEVSEL (0x3 << 8) /**< \brief (RTC_CR) Time Event Selection */ -#define RTC_CR_TIMEVSEL_MINUTE (0x0 << 8) /**< \brief (RTC_CR) Minute change. */ -#define RTC_CR_TIMEVSEL_HOUR (0x1 << 8) /**< \brief (RTC_CR) Hour change. */ -#define RTC_CR_TIMEVSEL_DAY24 (0x2 << 8) /**< \brief (RTC_CR) Every day at midnight. */ -#define RTC_CR_TIMEVSEL_DAY12 (0x3 << 8) /**< \brief (RTC_CR) Every day at noon. */ -#define RTC_CR_CALEVSEL (0x3 << 16) /**< \brief (RTC_CR) Calendar Event Selection */ -#define RTC_CR_CALEVSEL_WEEK (0x0 << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00). */ -#define RTC_CR_CALEVSEL_MONTH (0x1 << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00). */ -/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ -#define RTC_MR_HRMOD (0x1 << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ -/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ -#define RTC_TIMR_SEC (0x7f << 0) /**< \brief (RTC_TIMR) Current Second */ -#define RTC_TIMR_MIN (0x7f << 8) /**< \brief (RTC_TIMR) Current Minute */ -#define RTC_TIMR_HOUR (0x3f << 16) /**< \brief (RTC_TIMR) Current Hour */ -#define RTC_TIMR_AMPM (0x1 << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ -/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ -#define RTC_CALR_CENT (0x7f << 0) /**< \brief (RTC_CALR) Current Century */ -#define RTC_CALR_YEAR (0xff << 8) /**< \brief (RTC_CALR) Current Year */ -#define RTC_CALR_MONTH (0x1f << 16) /**< \brief (RTC_CALR) Current Month */ -#define RTC_CALR_DAY (0x7 << 21) /**< \brief (RTC_CALR) Current Day in Current Week */ -#define RTC_CALR_DATE (0x3f << 24) /**< \brief (RTC_CALR) Current Day in Current Month */ -/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ -#define RTC_TIMALR_SEC (0x7f << 0) /**< \brief (RTC_TIMALR) Second Alarm */ -#define RTC_TIMALR_SECEN (0x1 << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ -#define RTC_TIMALR_MIN (0x7f << 8) /**< \brief (RTC_TIMALR) Minute Alarm */ -#define RTC_TIMALR_MINEN (0x1 << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ -#define RTC_TIMALR_HOUR (0x3f << 16) /**< \brief (RTC_TIMALR) Hour Alarm */ -#define RTC_TIMALR_AMPM (0x1 << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ -#define RTC_TIMALR_HOUREN (0x1 << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ -/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ -#define RTC_CALALR_MONTH (0x1f << 16) /**< \brief (RTC_CALALR) Month Alarm */ -#define RTC_CALALR_MTHEN (0x1 << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ -#define RTC_CALALR_DATE (0x3f << 24) /**< \brief (RTC_CALALR) Date Alarm */ -#define RTC_CALALR_DATEEN (0x1 << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ -/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ -#define RTC_SR_ACKUPD (0x1 << 0) /**< \brief (RTC_SR) Acknowledge for Update */ -#define RTC_SR_ALARM (0x1 << 1) /**< \brief (RTC_SR) Alarm Flag */ -#define RTC_SR_SEC (0x1 << 2) /**< \brief (RTC_SR) Second Event */ -#define RTC_SR_TIMEV (0x1 << 3) /**< \brief (RTC_SR) Time Event */ -#define RTC_SR_CALEV (0x1 << 4) /**< \brief (RTC_SR) Calendar Event */ -/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ -#define RTC_SCCR_ACKCLR (0x1 << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ -#define RTC_SCCR_ALRCLR (0x1 << 1) /**< \brief (RTC_SCCR) Alarm Clear */ -#define RTC_SCCR_SECCLR (0x1 << 2) /**< \brief (RTC_SCCR) Second Clear */ -#define RTC_SCCR_TIMCLR (0x1 << 3) /**< \brief (RTC_SCCR) Time Clear */ -#define RTC_SCCR_CALCLR (0x1 << 4) /**< \brief (RTC_SCCR) Calendar Clear */ -/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ -#define RTC_IER_ACKEN (0x1 << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ -#define RTC_IER_ALREN (0x1 << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ -#define RTC_IER_SECEN (0x1 << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ -#define RTC_IER_TIMEN (0x1 << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ -#define RTC_IER_CALEN (0x1 << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ -/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ -#define RTC_IDR_ACKDIS (0x1 << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ -#define RTC_IDR_ALRDIS (0x1 << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ -#define RTC_IDR_SECDIS (0x1 << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ -#define RTC_IDR_TIMDIS (0x1 << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ -#define RTC_IDR_CALDIS (0x1 << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ -/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ -#define RTC_IMR_ACK (0x1 << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ -#define RTC_IMR_ALR (0x1 << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ -#define RTC_IMR_SEC (0x1 << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ -#define RTC_IMR_TIM (0x1 << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ -#define RTC_IMR_CAL (0x1 << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ -/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ -#define RTC_VER_NVTIM (0x1 << 0) /**< \brief (RTC_VER) Non-valid Time */ -#define RTC_VER_NVCAL (0x1 << 1) /**< \brief (RTC_VER) Non-valid Calendar */ -#define RTC_VER_NVTIMALR (0x1 << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ -#define RTC_VER_NVCALALR (0x1 << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Real-time Timer */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_RTT Real-time Timer */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rtt hardware registers */ -typedef struct { - RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ - RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ - RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ - RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ -} Rtt; -#endif /* __ASSEMBLY__ */ -/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ -#define RTT_MR_RTPRES (0xffff << 0) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ -#define RTT_MR_ALMIEN (0x1 << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ -#define RTT_MR_RTTINCIEN (0x1 << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ -#define RTT_MR_RTTRST (0x1 << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ -/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ -#define RTT_AR_ALMV (0xffffffff << 0) /**< \brief (RTT_AR) Alarm Value */ -/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ -#define RTT_VR_CRTV (0xffffffff << 0) /**< \brief (RTT_VR) Current Real-time Value */ -/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ -#define RTT_SR_ALMS (0x1 << 0) /**< \brief (RTT_SR) Real-time Alarm Status */ -#define RTT_SR_RTTINC (0x1 << 1) /**< \brief (RTT_SR) Real-time Timer Increment */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Static Memory Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SMC Static Memory Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief SmcCs_number hardware registers */ -typedef struct { - RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ - RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ - RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ - RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */ -} SmcCs_number; -/** \brief Smc hardware registers */ -typedef struct { - SmcCs_number SMC_CS_NUMBER[5]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 4 */ - RwReg Reserved1[12]; - RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */ - WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */ - WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */ - RwReg Reserved2[22]; - RwReg SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */ - RoReg SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */ -} Smc; -#endif /* __ASSEMBLY__ */ -/* -------- SMC_SETUP0 : (SMC Offset: 0x0) SMC Setup Register (CS_number = 0) -------- */ -#define SMC_SETUP0_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP0) NWE Setup Length */ -#define SMC_SETUP0_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP0) NCS Setup Length in WRITE Access */ -#define SMC_SETUP0_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP0) NRD Setup Length */ -#define SMC_SETUP0_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP0) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE0 : (SMC Offset: 0x4) SMC Pulse Register (CS_number = 0) -------- */ -#define SMC_PULSE0_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE0) NWE Pulse Length */ -#define SMC_PULSE0_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE0) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE0_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE0) NRD Pulse Length */ -#define SMC_PULSE0_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE0) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE0 : (SMC Offset: 0x8) SMC Cycle Register (CS_number = 0) -------- */ -#define SMC_CYCLE0_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE0) Total Write Cycle Length */ -#define SMC_CYCLE0_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE0) Total Read Cycle Length */ -/* -------- SMC_MODE0 : (SMC Offset: 0xC) SMC Mode Register (CS_number = 0) -------- */ -#define SMC_MODE0_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE0) */ -#define SMC_MODE0_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE0) */ -#define SMC_MODE0_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE0) NWAIT Mode */ -#define SMC_MODE0_DBW (0x3 << 12) /**< \brief (SMC_MODE0) Data Bus Width */ -#define SMC_MODE0_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE0) Data Float Time */ -#define SMC_MODE0_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE0) TDF Optimization */ -#define SMC_MODE0_PMEN (0x1 << 24) /**< \brief (SMC_MODE0) Page Mode Enabled */ -#define SMC_MODE0_PS (0x3 << 28) /**< \brief (SMC_MODE0) Page Size */ -/* -------- SMC_SETUP1 : (SMC Offset: 0x10) SMC Setup Register (CS_number = 1) -------- */ -#define SMC_SETUP1_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP1) NWE Setup Length */ -#define SMC_SETUP1_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP1) NCS Setup Length in WRITE Access */ -#define SMC_SETUP1_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP1) NRD Setup Length */ -#define SMC_SETUP1_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP1) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE1 : (SMC Offset: 0x14) SMC Pulse Register (CS_number = 1) -------- */ -#define SMC_PULSE1_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE1) NWE Pulse Length */ -#define SMC_PULSE1_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE1) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE1_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE1) NRD Pulse Length */ -#define SMC_PULSE1_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE1) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE1 : (SMC Offset: 0x18) SMC Cycle Register (CS_number = 1) -------- */ -#define SMC_CYCLE1_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE1) Total Write Cycle Length */ -#define SMC_CYCLE1_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE1) Total Read Cycle Length */ -/* -------- SMC_MODE1 : (SMC Offset: 0x1C) SMC Mode Register (CS_number = 1) -------- */ -#define SMC_MODE1_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE1) */ -#define SMC_MODE1_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE1) */ -#define SMC_MODE1_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE1) NWAIT Mode */ -#define SMC_MODE1_DBW (0x3 << 12) /**< \brief (SMC_MODE1) Data Bus Width */ -#define SMC_MODE1_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE1) Data Float Time */ -#define SMC_MODE1_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE1) TDF Optimization */ -#define SMC_MODE1_PMEN (0x1 << 24) /**< \brief (SMC_MODE1) Page Mode Enabled */ -#define SMC_MODE1_PS (0x3 << 28) /**< \brief (SMC_MODE1) Page Size */ -/* -------- SMC_SETUP2 : (SMC Offset: 0x20) SMC Setup Register (CS_number = 2) -------- */ -#define SMC_SETUP2_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP2) NWE Setup Length */ -#define SMC_SETUP2_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP2) NCS Setup Length in WRITE Access */ -#define SMC_SETUP2_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP2) NRD Setup Length */ -#define SMC_SETUP2_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP2) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE2 : (SMC Offset: 0x24) SMC Pulse Register (CS_number = 2) -------- */ -#define SMC_PULSE2_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE2) NWE Pulse Length */ -#define SMC_PULSE2_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE2) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE2_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE2) NRD Pulse Length */ -#define SMC_PULSE2_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE2) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE2 : (SMC Offset: 0x28) SMC Cycle Register (CS_number = 2) -------- */ -#define SMC_CYCLE2_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE2) Total Write Cycle Length */ -#define SMC_CYCLE2_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE2) Total Read Cycle Length */ -/* -------- SMC_MODE2 : (SMC Offset: 0x2C) SMC Mode Register (CS_number = 2) -------- */ -#define SMC_MODE2_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE2) */ -#define SMC_MODE2_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE2) */ -#define SMC_MODE2_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE2) NWAIT Mode */ -#define SMC_MODE2_DBW (0x3 << 12) /**< \brief (SMC_MODE2) Data Bus Width */ -#define SMC_MODE2_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE2) Data Float Time */ -#define SMC_MODE2_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE2) TDF Optimization */ -#define SMC_MODE2_PMEN (0x1 << 24) /**< \brief (SMC_MODE2) Page Mode Enabled */ -#define SMC_MODE2_PS (0x3 << 28) /**< \brief (SMC_MODE2) Page Size */ -/* -------- SMC_SETUP3 : (SMC Offset: 0x30) SMC Setup Register (CS_number = 3) -------- */ -#define SMC_SETUP3_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP3) NWE Setup Length */ -#define SMC_SETUP3_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP3) NCS Setup Length in WRITE Access */ -#define SMC_SETUP3_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP3) NRD Setup Length */ -#define SMC_SETUP3_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP3) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE3 : (SMC Offset: 0x34) SMC Pulse Register (CS_number = 3) -------- */ -#define SMC_PULSE3_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE3) NWE Pulse Length */ -#define SMC_PULSE3_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE3) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE3_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE3) NRD Pulse Length */ -#define SMC_PULSE3_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE3) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE3 : (SMC Offset: 0x38) SMC Cycle Register (CS_number = 3) -------- */ -#define SMC_CYCLE3_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE3) Total Write Cycle Length */ -#define SMC_CYCLE3_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE3) Total Read Cycle Length */ -/* -------- SMC_MODE3 : (SMC Offset: 0x3C) SMC Mode Register (CS_number = 3) -------- */ -#define SMC_MODE3_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE3) */ -#define SMC_MODE3_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE3) */ -#define SMC_MODE3_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE3) NWAIT Mode */ -#define SMC_MODE3_DBW (0x3 << 12) /**< \brief (SMC_MODE3) Data Bus Width */ -#define SMC_MODE3_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE3) Data Float Time */ -#define SMC_MODE3_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE3) TDF Optimization */ -#define SMC_MODE3_PMEN (0x1 << 24) /**< \brief (SMC_MODE3) Page Mode Enabled */ -#define SMC_MODE3_PS (0x3 << 28) /**< \brief (SMC_MODE3) Page Size */ -/* -------- SMC_SETUP4 : (SMC Offset: 0x40) SMC Setup Register (CS_number = 4) -------- */ -#define SMC_SETUP4_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP4) NWE Setup Length */ -#define SMC_SETUP4_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP4) NCS Setup Length in WRITE Access */ -#define SMC_SETUP4_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP4) NRD Setup Length */ -#define SMC_SETUP4_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP4) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE4 : (SMC Offset: 0x44) SMC Pulse Register (CS_number = 4) -------- */ -#define SMC_PULSE4_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE4) NWE Pulse Length */ -#define SMC_PULSE4_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE4) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE4_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE4) NRD Pulse Length */ -#define SMC_PULSE4_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE4) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE4 : (SMC Offset: 0x48) SMC Cycle Register (CS_number = 4) -------- */ -#define SMC_CYCLE4_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE4) Total Write Cycle Length */ -#define SMC_CYCLE4_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE4) Total Read Cycle Length */ -/* -------- SMC_MODE4 : (SMC Offset: 0x4C) SMC Mode Register (CS_number = 4) -------- */ -#define SMC_MODE4_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE4) */ -#define SMC_MODE4_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE4) */ -#define SMC_MODE4_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE4) NWAIT Mode */ -#define SMC_MODE4_DBW (0x3 << 12) /**< \brief (SMC_MODE4) Data Bus Width */ -#define SMC_MODE4_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE4) Data Float Time */ -#define SMC_MODE4_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE4) TDF Optimization */ -#define SMC_MODE4_PMEN (0x1 << 24) /**< \brief (SMC_MODE4) Page Mode Enabled */ -#define SMC_MODE4_PS (0x3 << 28) /**< \brief (SMC_MODE4) Page Size */ -/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */ -#define SMC_OCMS_SMSE (0x1 << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ -#define SMC_OCMS_CS0SE (0x1 << 16) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -#define SMC_OCMS_CS1SE (0x1 << 17) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -#define SMC_OCMS_CS2SE (0x1 << 18) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -#define SMC_OCMS_CS3SE (0x1 << 19) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */ -#define SMC_KEY1_KEY1 (0xffffffff << 0) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ -/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */ -#define SMC_KEY2_KEY2 (0xffffffff << 0) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ -/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */ -#define SMC_WPMR_WPEN (0x1 << 0) /**< \brief (SMC_WPMR) Write Protect Enable */ -#define SMC_WPMR_WPKEY (0xffffff << 8) /**< \brief (SMC_WPMR) Write Protect KEY */ -/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */ -#define SMC_WPSR_WPVS (0x1 << 0) /**< \brief (SMC_WPSR) Write Protect Enable */ -#define SMC_WPSR_WPVSRC (0xffff << 8) /**< \brief (SMC_WPSR) Write Protect Violation Source */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SPI Serial Peripheral Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Spi hardware registers */ -typedef struct { - WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ - RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ - RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ - WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ - RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ - WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ - WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ - RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ - RwReg Reserved1[4]; - RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ - RwReg Reserved2[41]; - RwReg SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */ - RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ - RwReg Reserved3[5]; - RwReg SPI_RPR; /**< \brief (Spi Offset: 0x100) Receive Pointer Register */ - RwReg SPI_RCR; /**< \brief (Spi Offset: 0x104) Receive Counter Register */ - RwReg SPI_TPR; /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */ - RwReg SPI_TCR; /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */ - RwReg SPI_RNPR; /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */ - RwReg SPI_RNCR; /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */ - RwReg SPI_TNPR; /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */ - RwReg SPI_TNCR; /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */ - WoReg SPI_PTCR; /**< \brief (Spi Offset: 0x120) Transfer Control Register */ - RoReg SPI_PTSR; /**< \brief (Spi Offset: 0x124) Transfer Status Register */ -} Spi; -#endif /* __ASSEMBLY__ */ -/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ -#define SPI_CR_SPIEN (0x1 << 0) /**< \brief (SPI_CR) SPI Enable */ -#define SPI_CR_SPIDIS (0x1 << 1) /**< \brief (SPI_CR) SPI Disable */ -#define SPI_CR_SWRST (0x1 << 7) /**< \brief (SPI_CR) SPI Software Reset */ -#define SPI_CR_LASTXFER (0x1 << 24) /**< \brief (SPI_CR) Last Transfer */ -/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ -#define SPI_MR_MSTR (0x1 << 0) /**< \brief (SPI_MR) Master/Slave Mode */ -#define SPI_MR_PS (0x1 << 1) /**< \brief (SPI_MR) Peripheral Select */ -#define SPI_MR_PS_FIXED (0x0 << 1) /**< \brief (SPI_MR) Fixed Peripheral Select. */ -#define SPI_MR_PS_VARIABLE (0x1 << 1) /**< \brief (SPI_MR) Variable Peripheral Select. */ -#define SPI_MR_PCSDEC (0x1 << 2) /**< \brief (SPI_MR) Chip Select Decode */ -#define SPI_MR_MODFDIS (0x1 << 4) /**< \brief (SPI_MR) Mode Fault Detection */ -#define SPI_MR_WDRBT (0x1 << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ -#define SPI_MR_LLB (0x1 << 7) /**< \brief (SPI_MR) Local Loopback Enable */ -#define SPI_MR_PCS (0xf << 16) /**< \brief (SPI_MR) Peripheral Chip Select */ -#define SPI_MR_DLYBCS (0xff << 24) /**< \brief (SPI_MR) Delay Between Chip Selects */ -/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ -#define SPI_RDR_RD (0xffff << 0) /**< \brief (SPI_RDR) Receive Data */ -#define SPI_RDR_PCS (0xf << 16) /**< \brief (SPI_RDR) Peripheral Chip Select */ -/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ -#define SPI_TDR_TD (0xffff << 0) /**< \brief (SPI_TDR) Transmit Data */ -#define SPI_TDR_PCS (0xf << 16) /**< \brief (SPI_TDR) Peripheral Chip Select */ -#define SPI_TDR_LASTXFER (0x1 << 24) /**< \brief (SPI_TDR) Last Transfer */ -/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ -#define SPI_SR_RDRF (0x1 << 0) /**< \brief (SPI_SR) Receive Data Register Full */ -#define SPI_SR_TDRE (0x1 << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */ -#define SPI_SR_MODF (0x1 << 2) /**< \brief (SPI_SR) Mode Fault Error */ -#define SPI_SR_OVRES (0x1 << 3) /**< \brief (SPI_SR) Overrun Error Status */ -#define SPI_SR_ENDRX (0x1 << 4) /**< \brief (SPI_SR) End of RX buffer */ -#define SPI_SR_ENDTX (0x1 << 5) /**< \brief (SPI_SR) End of TX buffer */ -#define SPI_SR_RXBUFF (0x1 << 6) /**< \brief (SPI_SR) RX Buffer Full */ -#define SPI_SR_TXBUFE (0x1 << 7) /**< \brief (SPI_SR) TX Buffer Empty */ -#define SPI_SR_NSSR (0x1 << 8) /**< \brief (SPI_SR) NSS Rising */ -#define SPI_SR_TXEMPTY (0x1 << 9) /**< \brief (SPI_SR) Transmission Registers Empty */ -#define SPI_SR_UNDES (0x1 << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */ -#define SPI_SR_SPIENS (0x1 << 16) /**< \brief (SPI_SR) SPI Enable Status */ -/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ -#define SPI_IER_RDRF (0x1 << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ -#define SPI_IER_TDRE (0x1 << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ -#define SPI_IER_MODF (0x1 << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ -#define SPI_IER_OVRES (0x1 << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ -#define SPI_IER_ENDRX (0x1 << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */ -#define SPI_IER_ENDTX (0x1 << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */ -#define SPI_IER_RXBUFF (0x1 << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */ -#define SPI_IER_TXBUFE (0x1 << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */ -#define SPI_IER_NSSR (0x1 << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ -#define SPI_IER_TXEMPTY (0x1 << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ -#define SPI_IER_UNDES (0x1 << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ -/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ -#define SPI_IDR_RDRF (0x1 << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ -#define SPI_IDR_TDRE (0x1 << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ -#define SPI_IDR_MODF (0x1 << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ -#define SPI_IDR_OVRES (0x1 << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ -#define SPI_IDR_ENDRX (0x1 << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */ -#define SPI_IDR_ENDTX (0x1 << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */ -#define SPI_IDR_RXBUFF (0x1 << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */ -#define SPI_IDR_TXBUFE (0x1 << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */ -#define SPI_IDR_NSSR (0x1 << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ -#define SPI_IDR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ -#define SPI_IDR_UNDES (0x1 << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ -/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ -#define SPI_IMR_RDRF (0x1 << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ -#define SPI_IMR_TDRE (0x1 << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ -#define SPI_IMR_MODF (0x1 << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ -#define SPI_IMR_OVRES (0x1 << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ -#define SPI_IMR_ENDRX (0x1 << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */ -#define SPI_IMR_ENDTX (0x1 << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */ -#define SPI_IMR_RXBUFF (0x1 << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */ -#define SPI_IMR_TXBUFE (0x1 << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */ -#define SPI_IMR_NSSR (0x1 << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ -#define SPI_IMR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ -#define SPI_IMR_UNDES (0x1 << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ -/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ -#define SPI_CSR_CPOL (0x1 << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ -#define SPI_CSR_NCPHA (0x1 << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ -#define SPI_CSR_CSNAAT (0x1 << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ -#define SPI_CSR_CSAAT (0x1 << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ -#define SPI_CSR_BITS (0xf << 4) /**< \brief (SPI_CSR[4]) Bits Per Transfer (See the (Note:) below the register table; Section 9.9 "SPI Chip Select Register" on page 35.) */ -#define SPI_CSR_BITS_8 (0x0 << 4) /**< \brief (SPI_CSR[4]) 8 */ -#define SPI_CSR_BITS_9 (0x1 << 4) /**< \brief (SPI_CSR[4]) 9 */ -#define SPI_CSR_BITS_10 (0x2 << 4) /**< \brief (SPI_CSR[4]) 10 */ -#define SPI_CSR_BITS_11 (0x3 << 4) /**< \brief (SPI_CSR[4]) 11 */ -#define SPI_CSR_BITS_12 (0x4 << 4) /**< \brief (SPI_CSR[4]) 12 */ -#define SPI_CSR_BITS_13 (0x5 << 4) /**< \brief (SPI_CSR[4]) 13 */ -#define SPI_CSR_BITS_14 (0x6 << 4) /**< \brief (SPI_CSR[4]) 14 */ -#define SPI_CSR_BITS_15 (0x7 << 4) /**< \brief (SPI_CSR[4]) 15 */ -#define SPI_CSR_BITS_16 (0x8 << 4) /**< \brief (SPI_CSR[4]) 16 */ -#define SPI_CSR_SCBR (0xff << 8) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */ -#define SPI_CSR_DLYBS (0xff << 16) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ -#define SPI_CSR_DLYBCT (0xff << 24) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ -/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */ -#define SPI_WPMR_SPIWPEN (0x1 << 0) /**< \brief (SPI_WPMR) SPI Write Protection Enable */ -#define SPI_WPMR_SPIWPKEY (0xffffff << 8) /**< \brief (SPI_WPMR) SPI Write Protection Key Password */ -/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ -#define SPI_WPSR_SPIWPVS (0x7 << 0) /**< \brief (SPI_WPSR) SPI Write Protection Violation Status */ -#define SPI_WPSR_SPIWPVSRC (0xff << 8) /**< \brief (SPI_WPSR) SPI Write Protection Violation Source */ -/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */ -#define SPI_RPR_RXPTR (0xffffffff << 0) /**< \brief (SPI_RPR) Receive Pointer Register */ -/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */ -#define SPI_RCR_RXCTR (0xffff << 0) /**< \brief (SPI_RCR) Receive Counter Register */ -/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */ -#define SPI_TPR_TXPTR (0xffffffff << 0) /**< \brief (SPI_TPR) Transmit Counter Register */ -/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */ -#define SPI_TCR_TXCTR (0xffff << 0) /**< \brief (SPI_TCR) Transmit Counter Register */ -/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */ -#define SPI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (SPI_RNPR) Receive Next Pointer */ -/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */ -#define SPI_RNCR_RXNCTR (0xffff << 0) /**< \brief (SPI_RNCR) Receive Next Counter */ -/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define SPI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (SPI_TNPR) Transmit Next Pointer */ -/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define SPI_TNCR_TXNCTR (0xffff << 0) /**< \brief (SPI_TNCR) Transmit Counter Next */ -/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */ -#define SPI_PTCR_RXTEN (0x1 << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */ -#define SPI_PTCR_RXTDIS (0x1 << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */ -#define SPI_PTCR_TXTEN (0x1 << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */ -#define SPI_PTCR_TXTDIS (0x1 << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */ -/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */ -#define SPI_PTSR_RXTEN (0x1 << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */ -#define SPI_PTSR_TXTEN (0x1 << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SSC Synchronous Serial Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Ssc hardware registers */ -typedef struct { - WoReg SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ - RwReg SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ - RwReg Reserved1[2]; - RwReg SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ - RwReg SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ - RwReg SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ - RwReg SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ - RoReg SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ - WoReg SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ - RwReg Reserved2[2]; - RoReg SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ - RwReg SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ - RwReg SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ - RwReg SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ - RoReg SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ - WoReg SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ - WoReg SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ - RoReg SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ - RwReg Reserved3[37]; - RwReg SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */ - RoReg SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */ - RwReg Reserved4[5]; - RwReg SSC_RPR; /**< \brief (Ssc Offset: 0x100) Receive Pointer Register */ - RwReg SSC_RCR; /**< \brief (Ssc Offset: 0x104) Receive Counter Register */ - RwReg SSC_TPR; /**< \brief (Ssc Offset: 0x108) Transmit Pointer Register */ - RwReg SSC_TCR; /**< \brief (Ssc Offset: 0x10C) Transmit Counter Register */ - RwReg SSC_RNPR; /**< \brief (Ssc Offset: 0x110) Receive Next Pointer Register */ - RwReg SSC_RNCR; /**< \brief (Ssc Offset: 0x114) Receive Next Counter Register */ - RwReg SSC_TNPR; /**< \brief (Ssc Offset: 0x118) Transmit Next Pointer Register */ - RwReg SSC_TNCR; /**< \brief (Ssc Offset: 0x11C) Transmit Next Counter Register */ - WoReg SSC_PTCR; /**< \brief (Ssc Offset: 0x120) Transfer Control Register */ - RoReg SSC_PTSR; /**< \brief (Ssc Offset: 0x124) Transfer Status Register */ -} Ssc; -#endif /* __ASSEMBLY__ */ -/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ -#define SSC_CR_RXEN (0x1 << 0) /**< \brief (SSC_CR) Receive Enable */ -#define SSC_CR_RXDIS (0x1 << 1) /**< \brief (SSC_CR) Receive Disable */ -#define SSC_CR_TXEN (0x1 << 8) /**< \brief (SSC_CR) Transmit Enable */ -#define SSC_CR_TXDIS (0x1 << 9) /**< \brief (SSC_CR) Transmit Disable */ -#define SSC_CR_SWRST (0x1 << 15) /**< \brief (SSC_CR) Software Reset */ -/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ -#define SSC_CMR_DIV (0xfff << 0) /**< \brief (SSC_CMR) Clock Divider */ -/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ -#define SSC_RCMR_CKS (0x3 << 0) /**< \brief (SSC_RCMR) Receive Clock Selection */ -#define SSC_RCMR_CKS_DIV (0x0 << 0) /**< \brief (SSC_RCMR) Divided Clock */ -#define SSC_RCMR_CKS_TK (0x1 << 0) /**< \brief (SSC_RCMR) TK Clock signal */ -#define SSC_RCMR_CKS_RK (0x2 << 0) /**< \brief (SSC_RCMR) RK pin */ -#define SSC_RCMR_CKO (0x7 << 2) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ -#define SSC_RCMR_CKI (0x1 << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ -#define SSC_RCMR_CKG (0x3 << 6) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ -#define SSC_RCMR_CKG_NONE (0x0 << 6) /**< \brief (SSC_RCMR) None, continuous clock */ -#define SSC_RCMR_CKG_LOW (0x1 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */ -#define SSC_RCMR_CKG_HIGH (0x2 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */ -#define SSC_RCMR_START (0xf << 8) /**< \brief (SSC_RCMR) Receive Start Selection */ -#define SSC_RCMR_STOP (0x1 << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ -#define SSC_RCMR_STTDLY (0xff << 16) /**< \brief (SSC_RCMR) Receive Start Delay */ -#define SSC_RCMR_PERIOD (0xff << 24) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ -/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ -#define SSC_RFMR_DATLEN (0x1f << 0) /**< \brief (SSC_RFMR) Data Length */ -#define SSC_RFMR_LOOP (0x1 << 5) /**< \brief (SSC_RFMR) Loop Mode */ -#define SSC_RFMR_MSBF (0x1 << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ -#define SSC_RFMR_DATNB (0xf << 8) /**< \brief (SSC_RFMR) Data Number per Frame */ -#define SSC_RFMR_FSLEN (0xf << 16) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ -#define SSC_RFMR_FSOS (0x7 << 20) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ -#define SSC_RFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ -#define SSC_RFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_RFMR) FSLEN Field Extension */ -/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ -#define SSC_TCMR_CKS (0x3 << 0) /**< \brief (SSC_TCMR) Transmit Clock Selection */ -#define SSC_TCMR_CKO (0x7 << 2) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ -#define SSC_TCMR_CKI (0x1 << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ -#define SSC_TCMR_CKG (0x3 << 6) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ -#define SSC_TCMR_START (0xf << 8) /**< \brief (SSC_TCMR) Transmit Start Selection */ -#define SSC_TCMR_STTDLY (0xff << 16) /**< \brief (SSC_TCMR) Transmit Start Delay */ -#define SSC_TCMR_PERIOD (0xff << 24) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ -/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ -#define SSC_TFMR_DATLEN (0x1f << 0) /**< \brief (SSC_TFMR) Data Length */ -#define SSC_TFMR_DATDEF (0x1 << 5) /**< \brief (SSC_TFMR) Data Default Value */ -#define SSC_TFMR_MSBF (0x1 << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ -#define SSC_TFMR_DATNB (0xf << 8) /**< \brief (SSC_TFMR) Data Number per frame */ -#define SSC_TFMR_FSLEN (0xf << 16) /**< \brief (SSC_TFMR) Transmit Frame Syn Length */ -#define SSC_TFMR_FSOS (0x7 << 20) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ -#define SSC_TFMR_FSDEN (0x1 << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ -#define SSC_TFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ -#define SSC_TFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_TFMR) FSLEN Field Extension */ -/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ -#define SSC_RHR_RDAT (0xffffffff << 0) /**< \brief (SSC_RHR) Receive Data */ -/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ -#define SSC_THR_TDAT (0xffffffff << 0) /**< \brief (SSC_THR) Transmit Data */ -/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ -#define SSC_RSHR_RSDAT (0xffff << 0) /**< \brief (SSC_RSHR) Receive Synchronization Data */ -/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ -#define SSC_TSHR_TSDAT (0xffff << 0) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ -/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ -#define SSC_RC0R_CP0 (0xffff << 0) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ -/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ -#define SSC_RC1R_CP1 (0xffff << 0) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ -/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ -#define SSC_SR_TXRDY (0x1 << 0) /**< \brief (SSC_SR) Transmit Ready */ -#define SSC_SR_TXEMPTY (0x1 << 1) /**< \brief (SSC_SR) Transmit Empty */ -#define SSC_SR_ENDTX (0x1 << 2) /**< \brief (SSC_SR) End of Transmission */ -#define SSC_SR_TXBUFE (0x1 << 3) /**< \brief (SSC_SR) Transmit Buffer Empty */ -#define SSC_SR_RXRDY (0x1 << 4) /**< \brief (SSC_SR) Receive Ready */ -#define SSC_SR_OVRUN (0x1 << 5) /**< \brief (SSC_SR) Receive Overrun */ -#define SSC_SR_ENDRX (0x1 << 6) /**< \brief (SSC_SR) End of Reception */ -#define SSC_SR_RXBUFF (0x1 << 7) /**< \brief (SSC_SR) Receive Buffer Full */ -#define SSC_SR_CP0 (0x1 << 8) /**< \brief (SSC_SR) Compare 0 */ -#define SSC_SR_CP1 (0x1 << 9) /**< \brief (SSC_SR) Compare 1 */ -#define SSC_SR_TXSYN (0x1 << 10) /**< \brief (SSC_SR) Transmit Sync */ -#define SSC_SR_RXSYN (0x1 << 11) /**< \brief (SSC_SR) Receive Sync */ -#define SSC_SR_TXEN (0x1 << 16) /**< \brief (SSC_SR) Transmit Enable */ -#define SSC_SR_RXEN (0x1 << 17) /**< \brief (SSC_SR) Receive Enable */ -/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ -#define SSC_IER_TXRDY (0x1 << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ -#define SSC_IER_TXEMPTY (0x1 << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ -#define SSC_IER_ENDTX (0x1 << 2) /**< \brief (SSC_IER) End of Transmission Interrupt Enable */ -#define SSC_IER_TXBUFE (0x1 << 3) /**< \brief (SSC_IER) Transmit Buffer Empty Interrupt Enable */ -#define SSC_IER_RXRDY (0x1 << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ -#define SSC_IER_OVRUN (0x1 << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ -#define SSC_IER_ENDRX (0x1 << 6) /**< \brief (SSC_IER) End of Reception Interrupt Enable */ -#define SSC_IER_RXBUFF (0x1 << 7) /**< \brief (SSC_IER) Receive Buffer Full Interrupt Enable */ -#define SSC_IER_CP0 (0x1 << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ -#define SSC_IER_CP1 (0x1 << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ -#define SSC_IER_TXSYN (0x1 << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ -#define SSC_IER_RXSYN (0x1 << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ -/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ -#define SSC_IDR_TXRDY (0x1 << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ -#define SSC_IDR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ -#define SSC_IDR_ENDTX (0x1 << 2) /**< \brief (SSC_IDR) End of Transmission Interrupt Disable */ -#define SSC_IDR_TXBUFE (0x1 << 3) /**< \brief (SSC_IDR) Transmit Buffer Empty Interrupt Disable */ -#define SSC_IDR_RXRDY (0x1 << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ -#define SSC_IDR_OVRUN (0x1 << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ -#define SSC_IDR_ENDRX (0x1 << 6) /**< \brief (SSC_IDR) End of Reception Interrupt Disable */ -#define SSC_IDR_RXBUFF (0x1 << 7) /**< \brief (SSC_IDR) Receive Buffer Full Interrupt Disable */ -#define SSC_IDR_CP0 (0x1 << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ -#define SSC_IDR_CP1 (0x1 << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ -#define SSC_IDR_TXSYN (0x1 << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ -#define SSC_IDR_RXSYN (0x1 << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ -/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ -#define SSC_IMR_TXRDY (0x1 << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ -#define SSC_IMR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ -#define SSC_IMR_ENDTX (0x1 << 2) /**< \brief (SSC_IMR) End of Transmission Interrupt Mask */ -#define SSC_IMR_TXBUFE (0x1 << 3) /**< \brief (SSC_IMR) Transmit Buffer Empty Interrupt Mask */ -#define SSC_IMR_RXRDY (0x1 << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ -#define SSC_IMR_OVRUN (0x1 << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ -#define SSC_IMR_ENDRX (0x1 << 6) /**< \brief (SSC_IMR) End of Reception Interrupt Mask */ -#define SSC_IMR_RXBUFF (0x1 << 7) /**< \brief (SSC_IMR) Receive Buffer Full Interrupt Mask */ -#define SSC_IMR_CP0 (0x1 << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ -#define SSC_IMR_CP1 (0x1 << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ -#define SSC_IMR_TXSYN (0x1 << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ -#define SSC_IMR_RXSYN (0x1 << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ -/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */ -#define SSC_WPMR_WPEN (0x1 << 0) /**< \brief (SSC_WPMR) Write Protect Enable */ -#define SSC_WPMR_WPKEY (0xffffff << 8) /**< \brief (SSC_WPMR) Write Protect KEY */ -/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */ -#define SSC_WPSR_WPVS (0x1 << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */ -#define SSC_WPSR_WPVSRC (0xffff << 8) /**< \brief (SSC_WPSR) Write Protect Violation Source */ -/* -------- SSC_RPR : (SSC Offset: 0x100) Receive Pointer Register -------- */ -#define SSC_RPR_RXPTR (0xffffffff << 0) /**< \brief (SSC_RPR) Receive Pointer Register */ -/* -------- SSC_RCR : (SSC Offset: 0x104) Receive Counter Register -------- */ -#define SSC_RCR_RXCTR (0xffff << 0) /**< \brief (SSC_RCR) Receive Counter Register */ -/* -------- SSC_TPR : (SSC Offset: 0x108) Transmit Pointer Register -------- */ -#define SSC_TPR_TXPTR (0xffffffff << 0) /**< \brief (SSC_TPR) Transmit Counter Register */ -/* -------- SSC_TCR : (SSC Offset: 0x10C) Transmit Counter Register -------- */ -#define SSC_TCR_TXCTR (0xffff << 0) /**< \brief (SSC_TCR) Transmit Counter Register */ -/* -------- SSC_RNPR : (SSC Offset: 0x110) Receive Next Pointer Register -------- */ -#define SSC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (SSC_RNPR) Receive Next Pointer */ -/* -------- SSC_RNCR : (SSC Offset: 0x114) Receive Next Counter Register -------- */ -#define SSC_RNCR_RXNCTR (0xffff << 0) /**< \brief (SSC_RNCR) Receive Next Counter */ -/* -------- SSC_TNPR : (SSC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define SSC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (SSC_TNPR) Transmit Next Pointer */ -/* -------- SSC_TNCR : (SSC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define SSC_TNCR_TXNCTR (0xffff << 0) /**< \brief (SSC_TNCR) Transmit Counter Next */ -/* -------- SSC_PTCR : (SSC Offset: 0x120) Transfer Control Register -------- */ -#define SSC_PTCR_RXTEN (0x1 << 0) /**< \brief (SSC_PTCR) Receiver Transfer Enable */ -#define SSC_PTCR_RXTDIS (0x1 << 1) /**< \brief (SSC_PTCR) Receiver Transfer Disable */ -#define SSC_PTCR_TXTEN (0x1 << 8) /**< \brief (SSC_PTCR) Transmitter Transfer Enable */ -#define SSC_PTCR_TXTDIS (0x1 << 9) /**< \brief (SSC_PTCR) Transmitter Transfer Disable */ -/* -------- SSC_PTSR : (SSC Offset: 0x124) Transfer Status Register -------- */ -#define SSC_PTSR_RXTEN (0x1 << 0) /**< \brief (SSC_PTSR) Receiver Transfer Enable */ -#define SSC_PTSR_TXTEN (0x1 << 8) /**< \brief (SSC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Supply Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SUPC Supply Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Supc hardware registers */ -typedef struct { - WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ - RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ - RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ - RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */ - RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */ - RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ -} Supc; -#endif /* __ASSEMBLY__ */ -/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ -#define SUPC_CR_VROFF (0x1 << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ -#define SUPC_CR_VROFF_NO_EFFECT (0x0 << 2) /**< \brief (SUPC_CR) no effect. */ -#define SUPC_CR_VROFF_STOP_VREG (0x1 << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */ -#define SUPC_CR_XTALSEL (0x1 << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ -#define SUPC_CR_XTALSEL_NO_EFFECT (0x0 << 3) /**< \brief (SUPC_CR) no effect. */ -#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1 << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */ -#define SUPC_CR_KEY (0xff << 24) /**< \brief (SUPC_CR) Password */ -/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ -#define SUPC_SMMR_SMTH (0xf << 0) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ -#define SUPC_SMMR_SMTH_1_9V (0x0 << 0) /**< \brief (SUPC_SMMR) 1.9 V */ -#define SUPC_SMMR_SMTH_2_0V (0x1 << 0) /**< \brief (SUPC_SMMR) 2.0 V */ -#define SUPC_SMMR_SMTH_2_1V (0x2 << 0) /**< \brief (SUPC_SMMR) 2.1 V */ -#define SUPC_SMMR_SMTH_2_2V (0x3 << 0) /**< \brief (SUPC_SMMR) 2.2 V */ -#define SUPC_SMMR_SMTH_2_3V (0x4 << 0) /**< \brief (SUPC_SMMR) 2.3 V */ -#define SUPC_SMMR_SMTH_2_4V (0x5 << 0) /**< \brief (SUPC_SMMR) 2.4 V */ -#define SUPC_SMMR_SMTH_2_5V (0x6 << 0) /**< \brief (SUPC_SMMR) 2.5 V */ -#define SUPC_SMMR_SMTH_2_6V (0x7 << 0) /**< \brief (SUPC_SMMR) 2.6 V */ -#define SUPC_SMMR_SMTH_2_7V (0x8 << 0) /**< \brief (SUPC_SMMR) 2.7 V */ -#define SUPC_SMMR_SMTH_2_8V (0x9 << 0) /**< \brief (SUPC_SMMR) 2.8 V */ -#define SUPC_SMMR_SMTH_2_9V (0xA << 0) /**< \brief (SUPC_SMMR) 2.9 V */ -#define SUPC_SMMR_SMTH_3_0V (0xB << 0) /**< \brief (SUPC_SMMR) 3.0 V */ -#define SUPC_SMMR_SMTH_3_1V (0xC << 0) /**< \brief (SUPC_SMMR) 3.1 V */ -#define SUPC_SMMR_SMTH_3_2V (0xD << 0) /**< \brief (SUPC_SMMR) 3.2 V */ -#define SUPC_SMMR_SMTH_3_3V (0xE << 0) /**< \brief (SUPC_SMMR) 3.3 V */ -#define SUPC_SMMR_SMTH_3_4V (0xF << 0) /**< \brief (SUPC_SMMR) 3.4 V */ -#define SUPC_SMMR_SMSMPL (0x7 << 8) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ -#define SUPC_SMMR_SMSMPL_SMD (0x0 << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ -#define SUPC_SMMR_SMSMPL_CSM (0x1 << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ -#define SUPC_SMMR_SMSMPL_32SLCK (0x2 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ -#define SUPC_SMMR_SMSMPL_256SLCK (0x3 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ -#define SUPC_SMMR_SMSMPL_2048SLCK (0x4 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ -#define SUPC_SMMR_SMRSTEN (0x1 << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ -#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMIEN (0x1 << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ -#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMIEN_ENABLE (0x1 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */ -/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ -#define SUPC_MR_BODRSTEN (0x1 << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ -#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */ -#define SUPC_MR_BODRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ -#define SUPC_MR_BODDIS (0x1 << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ -#define SUPC_MR_BODDIS_ENABLE (0x0 << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */ -#define SUPC_MR_BODDIS_DISABLE (0x1 << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */ -#define SUPC_MR_ONREG (0x1 << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */ -#define SUPC_MR_ONREG_ONREG_UNUSED (0x0 << 14) /**< \brief (SUPC_MR) Voltage Regulator is not used */ -#define SUPC_MR_ONREG_ONREG_USED (0x1 << 14) /**< \brief (SUPC_MR) Voltage Regulator is used */ -#define SUPC_MR_OSCBYPASS (0x1 << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ -#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0 << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */ -#define SUPC_MR_OSCBYPASS_BYPASS (0x1 << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */ -#define SUPC_MR_KEY (0xff << 24) /**< \brief (SUPC_MR) Password Key */ -/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */ -#define SUPC_WUMR_SMEN (0x1 << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */ -#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */ -#define SUPC_WUMR_SMEN_ENABLE (0x1 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */ -#define SUPC_WUMR_RTTEN (0x1 << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */ -#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */ -#define SUPC_WUMR_RTTEN_ENABLE (0x1 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */ -#define SUPC_WUMR_RTCEN (0x1 << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */ -#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */ -#define SUPC_WUMR_RTCEN_ENABLE (0x1 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */ -#define SUPC_WUMR_WKUPDBC (0x7 << 12) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer */ -#define SUPC_WUMR_WKUPDBC_1SCLK (0x0 << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ -#define SUPC_WUMR_WKUPDBC_3SCLK (0x1 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 3 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_32SCLK (0x2 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_512SCLK (0x3 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 512 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_4096SCLK (0x4 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 4,096 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_32768SCLK (0x5 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32,768 SLCK periods */ -/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */ -#define SUPC_WUIR_WKUPEN0 (0x1 << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */ -#define SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN0_ENABLE (0x1 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN1 (0x1 << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */ -#define SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN1_ENABLE (0x1 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN2 (0x1 << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */ -#define SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN2_ENABLE (0x1 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN3 (0x1 << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */ -#define SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN3_ENABLE (0x1 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN4 (0x1 << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */ -#define SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN4_ENABLE (0x1 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN5 (0x1 << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */ -#define SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN5_ENABLE (0x1 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN6 (0x1 << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */ -#define SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN6_ENABLE (0x1 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN7 (0x1 << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */ -#define SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN7_ENABLE (0x1 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN8 (0x1 << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */ -#define SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN8_ENABLE (0x1 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN9 (0x1 << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */ -#define SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN9_ENABLE (0x1 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN10 (0x1 << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */ -#define SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN10_ENABLE (0x1 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN11 (0x1 << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */ -#define SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN11_ENABLE (0x1 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN12 (0x1 << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */ -#define SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN12_ENABLE (0x1 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN13 (0x1 << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */ -#define SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN13_ENABLE (0x1 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN14 (0x1 << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */ -#define SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN14_ENABLE (0x1 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN15 (0x1 << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */ -#define SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN15_ENABLE (0x1 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT0 (0x1 << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */ -#define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0 << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1 << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT1 (0x1 << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */ -#define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0 << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1 << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT2 (0x1 << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */ -#define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0 << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1 << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT3 (0x1 << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */ -#define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0 << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1 << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT4 (0x1 << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */ -#define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0 << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1 << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT5 (0x1 << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */ -#define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0 << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1 << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT6 (0x1 << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */ -#define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0 << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1 << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT7 (0x1 << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */ -#define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0 << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1 << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT8 (0x1 << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */ -#define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0 << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1 << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT9 (0x1 << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */ -#define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0 << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1 << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT10 (0x1 << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */ -#define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0 << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1 << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT11 (0x1 << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */ -#define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0 << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1 << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT12 (0x1 << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */ -#define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0 << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1 << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT13 (0x1 << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */ -#define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0 << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1 << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT14 (0x1 << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */ -#define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0 << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1 << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT15 (0x1 << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */ -#define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0 << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1 << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ -#define SUPC_SR_WKUPS (0x1 << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */ -#define SUPC_SR_WKUPS_NO (0x0 << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_WKUPS_PRESENT (0x1 << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_SMWS (0x1 << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */ -#define SUPC_SR_SMWS_NO (0x0 << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_SMWS_PRESENT (0x1 << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_BODRSTS (0x1 << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */ -#define SUPC_SR_BODRSTS_NO (0x0 << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */ -#define SUPC_SR_BODRSTS_PRESENT (0x1 << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ -#define SUPC_SR_SMRSTS (0x1 << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */ -#define SUPC_SR_SMRSTS_NO (0x0 << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ -#define SUPC_SR_SMRSTS_PRESENT (0x1 << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ -#define SUPC_SR_SMS (0x1 << 5) /**< \brief (SUPC_SR) Supply Monitor Status */ -#define SUPC_SR_SMS_NO (0x0 << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */ -#define SUPC_SR_SMS_PRESENT (0x1 << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */ -#define SUPC_SR_SMOS (0x1 << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ -#define SUPC_SR_SMOS_HIGH (0x0 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */ -#define SUPC_SR_SMOS_LOW (0x1 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */ -#define SUPC_SR_OSCSEL (0x1 << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ -#define SUPC_SR_OSCSEL_RC (0x0 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */ -#define SUPC_SR_OSCSEL_CRYST (0x1 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */ -#define SUPC_SR_WKUPIS0 (0x1 << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */ -#define SUPC_SR_WKUPIS0_DIS (0x0 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS0_EN (0x1 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS1 (0x1 << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */ -#define SUPC_SR_WKUPIS1_DIS (0x0 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS1_EN (0x1 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS2 (0x1 << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */ -#define SUPC_SR_WKUPIS2_DIS (0x0 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS2_EN (0x1 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS3 (0x1 << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */ -#define SUPC_SR_WKUPIS3_DIS (0x0 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS3_EN (0x1 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS4 (0x1 << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */ -#define SUPC_SR_WKUPIS4_DIS (0x0 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS4_EN (0x1 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS5 (0x1 << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */ -#define SUPC_SR_WKUPIS5_DIS (0x0 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS5_EN (0x1 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS6 (0x1 << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */ -#define SUPC_SR_WKUPIS6_DIS (0x0 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS6_EN (0x1 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS7 (0x1 << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */ -#define SUPC_SR_WKUPIS7_DIS (0x0 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS7_EN (0x1 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS8 (0x1 << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */ -#define SUPC_SR_WKUPIS8_DIS (0x0 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS8_EN (0x1 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS9 (0x1 << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */ -#define SUPC_SR_WKUPIS9_DIS (0x0 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS9_EN (0x1 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS10 (0x1 << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */ -#define SUPC_SR_WKUPIS10_DIS (0x0 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS10_EN (0x1 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS11 (0x1 << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */ -#define SUPC_SR_WKUPIS11_DIS (0x0 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS11_EN (0x1 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS12 (0x1 << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */ -#define SUPC_SR_WKUPIS12_DIS (0x0 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS12_EN (0x1 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS13 (0x1 << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */ -#define SUPC_SR_WKUPIS13_DIS (0x0 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS13_EN (0x1 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS14 (0x1 << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */ -#define SUPC_SR_WKUPIS14_DIS (0x0 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS14_EN (0x1 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS15 (0x1 << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */ -#define SUPC_SR_WKUPIS15_DIS (0x0 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS15_EN (0x1 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Timer Counter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_TC Timer Counter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief TcChannel hardware registers */ -typedef struct { - RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ - RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ - RwReg Reserved1[2]; - RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ - RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ - RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ - RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ - RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ - RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ - RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ - RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ - RwReg Reserved2[4]; -} TcChannel; -/** \brief Tc hardware registers */ -typedef struct { - TcChannel TC_CHANNEL[3]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ - WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ - RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ - WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ - WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ - RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ - RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ - RwReg TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ - RwReg Reserved1[2]; - RwReg TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */ - RwReg Reserved2[5]; - RoReg TC_VER; /**< \brief (Tc Offset: 0xFC) Version Register */ -} Tc; -#endif /* __ASSEMBLY__ */ -/* -------- TC_CCR0 : (TC Offset: 0x0) Channel Control Register (channel = 0) -------- */ -#define TC_CCR0_CLKEN (0x1 << 0) /**< \brief (TC_CCR0) Counter Clock Enable Command */ -#define TC_CCR0_CLKDIS (0x1 << 1) /**< \brief (TC_CCR0) Counter Clock Disable Command */ -#define TC_CCR0_SWTRG (0x1 << 2) /**< \brief (TC_CCR0) Software Trigger Command */ -/* -------- TC_CMR0 : (TC Offset: 0x4) Channel Mode Register (channel = 0) -------- */ -#define TC_CMR0_TCCLKS (0x7 << 0) /**< \brief (TC_CMR0) Clock Selection */ -#define TC_CM0_TCCLKS_TIMER_DIV1_CLOCK (0x0 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV1_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV2_CLOCK (0x1 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV2_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV3_CLOCK (0x2 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV3_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV4_CLOCK (0x3 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV4_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV5_CLOCK (0x4 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV5_CLOCK*/ -#define TC_CM0_TCCLKS_XC0 (0x5 << 0) /**< (TC_CMR0) Clock selected: XC0*/ -#define TC_CM0_TCCLKS_XC1 (0x6 << 0) /**< (TC_CMR0) Clock selected: XC1*/ -#define TC_CM0_TCCLKS_XC2 (0x7 << 0) /**< (TC_CMR0) Clock selected: XC2*/ -#define TC_CMR0_CLKI (0x1 << 3) /**< \brief (TC_CMR0) Clock Invert */ -#define TC_CMR0_BURST (0x3 << 4) /**< \brief (TC_CMR0) Burst Signal Selection */ -#define TC_CMR0_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR0) The clock is not gated by an external signal. */ -#define TC_CMR0_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR0) XC0 is ANDed with the selected clock. */ -#define TC_CMR0_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR0) XC1 is ANDed with the selected clock. */ -#define TC_CMR0_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR0) XC2 is ANDed with the selected clock. */ -#define TC_CMR0_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR0) Counter Clock Stopped with RB Loading */ -#define TC_CMR0_LDBDIS (0x1 << 7) /**< \brief (TC_CMR0) Counter Clock Disable with RB Loading */ -#define TC_CMR0_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR0) External Trigger Edge Selection */ -#define TC_CMR0_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR0) rising edge */ -#define TC_CMR0_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR0) falling edge */ -#define TC_CMR0_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR0) each edge */ -#define TC_CMR0_ABETRG (0x1 << 10) /**< \brief (TC_CMR0) TIOA or TIOB External Trigger Selection */ -#define TC_CMR0_CPCTRG (0x1 << 14) /**< \brief (TC_CMR0) RC Compare Trigger Enable */ -#define TC_CMR0_WAVE (0x1 << 15) /**< \brief (TC_CMR0) */ -#define TC_CMR0_LDRA (0x3 << 16) /**< \brief (TC_CMR0) RA Loading Selection */ -#define TC_CMR0_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR0) rising edge of TIOA */ -#define TC_CMR0_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR0) falling edge of TIOA */ -#define TC_CMR0_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR0) each edge of TIOA */ -#define TC_CMR0_LDRB (0x3 << 18) /**< \brief (TC_CMR0) RB Loading Selection */ -#define TC_CMR0_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR0) rising edge of TIOA */ -#define TC_CMR0_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR0) falling edge of TIOA */ -#define TC_CMR0_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR0) each edge of TIOA */ - -#define TC_CMR0_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define TC_CMR0_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define TC_CMR0_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define TC_CMR0_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle - -#define TC_CMR0_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define TC_CMR0_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define TC_CMR0_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define TC_CMR0_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -/* -------- TC_CV0 : (TC Offset: 0x10) Counter Value (channel = 0) -------- */ -#define TC_CV0_CV (0xffff << 0) /**< \brief (TC_CV0) Counter Value */ -/* -------- TC_RA0 : (TC Offset: 0x14) Register A (channel = 0) -------- */ -#define TC_RA0_RA (0xffff << 0) /**< \brief (TC_RA0) Register A */ -/* -------- TC_RB0 : (TC Offset: 0x18) Register B (channel = 0) -------- */ -#define TC_RB0_RB (0xffff << 0) /**< \brief (TC_RB0) Register B */ -/* -------- TC_RC0 : (TC Offset: 0x1C) Register C (channel = 0) -------- */ -#define TC_RC0_RC (0xffff << 0) /**< \brief (TC_RC0) Register C */ -/* -------- TC_SR0 : (TC Offset: 0x20) Status Register (channel = 0) -------- */ -#define TC_SR0_COVFS (0x1 << 0) /**< \brief (TC_SR0) Counter Overflow Status */ -#define TC_SR0_LOVRS (0x1 << 1) /**< \brief (TC_SR0) Load Overrun Status */ -#define TC_SR0_CPAS (0x1 << 2) /**< \brief (TC_SR0) RA Compare Status */ -#define TC_SR0_CPBS (0x1 << 3) /**< \brief (TC_SR0) RB Compare Status */ -#define TC_SR0_CPCS (0x1 << 4) /**< \brief (TC_SR0) RC Compare Status */ -#define TC_SR0_LDRAS (0x1 << 5) /**< \brief (TC_SR0) RA Loading Status */ -#define TC_SR0_LDRBS (0x1 << 6) /**< \brief (TC_SR0) RB Loading Status */ -#define TC_SR0_ETRGS (0x1 << 7) /**< \brief (TC_SR0) External Trigger Status */ -#define TC_SR0_CLKSTA (0x1 << 16) /**< \brief (TC_SR0) Clock Enabling Status */ -#define TC_SR0_MTIOA (0x1 << 17) /**< \brief (TC_SR0) TIOA Mirror */ -#define TC_SR0_MTIOB (0x1 << 18) /**< \brief (TC_SR0) TIOB Mirror */ -/* -------- TC_IER0 : (TC Offset: 0x24) Interrupt Enable Register (channel = 0) -------- */ -#define TC_IER0_COVFS (0x1 << 0) /**< \brief (TC_IER0) Counter Overflow */ -#define TC_IER0_LOVRS (0x1 << 1) /**< \brief (TC_IER0) Load Overrun */ -#define TC_IER0_CPAS (0x1 << 2) /**< \brief (TC_IER0) RA Compare */ -#define TC_IER0_CPBS (0x1 << 3) /**< \brief (TC_IER0) RB Compare */ -#define TC_IER0_CPCS (0x1 << 4) /**< \brief (TC_IER0) RC Compare */ -#define TC_IER0_LDRAS (0x1 << 5) /**< \brief (TC_IER0) RA Loading */ -#define TC_IER0_LDRBS (0x1 << 6) /**< \brief (TC_IER0) RB Loading */ -#define TC_IER0_ETRGS (0x1 << 7) /**< \brief (TC_IER0) External Trigger */ -/* -------- TC_IDR0 : (TC Offset: 0x28) Interrupt Disable Register (channel = 0) -------- */ -#define TC_IDR0_COVFS (0x1 << 0) /**< \brief (TC_IDR0) Counter Overflow */ -#define TC_IDR0_LOVRS (0x1 << 1) /**< \brief (TC_IDR0) Load Overrun */ -#define TC_IDR0_CPAS (0x1 << 2) /**< \brief (TC_IDR0) RA Compare */ -#define TC_IDR0_CPBS (0x1 << 3) /**< \brief (TC_IDR0) RB Compare */ -#define TC_IDR0_CPCS (0x1 << 4) /**< \brief (TC_IDR0) RC Compare */ -#define TC_IDR0_LDRAS (0x1 << 5) /**< \brief (TC_IDR0) RA Loading */ -#define TC_IDR0_LDRBS (0x1 << 6) /**< \brief (TC_IDR0) RB Loading */ -#define TC_IDR0_ETRGS (0x1 << 7) /**< \brief (TC_IDR0) External Trigger */ -/* -------- TC_IMR0 : (TC Offset: 0x2C) Interrupt Mask Register (channel = 0) -------- */ -#define TC_IMR0_COVFS (0x1 << 0) /**< \brief (TC_IMR0) Counter Overflow */ -#define TC_IMR0_LOVRS (0x1 << 1) /**< \brief (TC_IMR0) Load Overrun */ -#define TC_IMR0_CPAS (0x1 << 2) /**< \brief (TC_IMR0) RA Compare */ -#define TC_IMR0_CPBS (0x1 << 3) /**< \brief (TC_IMR0) RB Compare */ -#define TC_IMR0_CPCS (0x1 << 4) /**< \brief (TC_IMR0) RC Compare */ -#define TC_IMR0_LDRAS (0x1 << 5) /**< \brief (TC_IMR0) RA Loading */ -#define TC_IMR0_LDRBS (0x1 << 6) /**< \brief (TC_IMR0) RB Loading */ -#define TC_IMR0_ETRGS (0x1 << 7) /**< \brief (TC_IMR0) External Trigger */ -/* -------- TC_CCR1 : (TC Offset: 0x40) Channel Control Register (channel = 1) -------- */ -#define TC_CCR1_CLKEN (0x1 << 0) /**< \brief (TC_CCR1) Counter Clock Enable Command */ -#define TC_CCR1_CLKDIS (0x1 << 1) /**< \brief (TC_CCR1) Counter Clock Disable Command */ -#define TC_CCR1_SWTRG (0x1 << 2) /**< \brief (TC_CCR1) Software Trigger Command */ -/* -------- TC_CMR1 : (TC Offset: 0x44) Channel Mode Register (channel = 1) -------- */ -#define TC_CMR1_TCCLKS (0x7 << 0) /**< \brief (TC_CMR1) Clock Selection */ -#define TC_CMR1_CLKI (0x1 << 3) /**< \brief (TC_CMR1) Clock Invert */ -#define TC_CMR1_BURST (0x3 << 4) /**< \brief (TC_CMR1) Burst Signal Selection */ -#define TC_CMR1_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR1) The clock is not gated by an external signal. */ -#define TC_CMR1_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR1) XC0 is ANDed with the selected clock. */ -#define TC_CMR1_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR1) XC1 is ANDed with the selected clock. */ -#define TC_CMR1_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR1) XC2 is ANDed with the selected clock. */ -#define TC_CMR1_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR1) Counter Clock Stopped with RB Loading */ -#define TC_CMR1_LDBDIS (0x1 << 7) /**< \brief (TC_CMR1) Counter Clock Disable with RB Loading */ -#define TC_CMR1_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR1) External Trigger Edge Selection */ -#define TC_CMR1_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR1) rising edge */ -#define TC_CMR1_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR1) falling edge */ -#define TC_CMR1_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR1) each edge */ -#define TC_CMR1_ABETRG (0x1 << 10) /**< \brief (TC_CMR1) TIOA or TIOB External Trigger Selection */ -#define TC_CMR1_CPCTRG (0x1 << 14) /**< \brief (TC_CMR1) RC Compare Trigger Enable */ -#define TC_CMR1_WAVE (0x1 << 15) /**< \brief (TC_CMR1) */ -#define TC_CMR1_LDRA (0x3 << 16) /**< \brief (TC_CMR1) RA Loading Selection */ -#define TC_CMR1_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR1) rising edge of TIOA */ -#define TC_CMR1_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR1) falling edge of TIOA */ -#define TC_CMR1_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR1) each edge of TIOA */ -#define TC_CMR1_LDRB (0x3 << 18) /**< \brief (TC_CMR1) RB Loading Selection */ -#define TC_CMR1_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR1) rising edge of TIOA */ -#define TC_CMR1_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR1) falling edge of TIOA */ -#define TC_CMR1_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR1) each edge of TIOA */ -/* -------- TC_CV1 : (TC Offset: 0x50) Counter Value (channel = 1) -------- */ -#define TC_CV1_CV (0xffff << 0) /**< \brief (TC_CV1) Counter Value */ -/* -------- TC_RA1 : (TC Offset: 0x54) Register A (channel = 1) -------- */ -#define TC_RA1_RA (0xffff << 0) /**< \brief (TC_RA1) Register A */ -/* -------- TC_RB1 : (TC Offset: 0x58) Register B (channel = 1) -------- */ -#define TC_RB1_RB (0xffff << 0) /**< \brief (TC_RB1) Register B */ -/* -------- TC_RC1 : (TC Offset: 0x5C) Register C (channel = 1) -------- */ -#define TC_RC1_RC (0xffff << 0) /**< \brief (TC_RC1) Register C */ -/* -------- TC_SR1 : (TC Offset: 0x60) Status Register (channel = 1) -------- */ -#define TC_SR1_COVFS (0x1 << 0) /**< \brief (TC_SR1) Counter Overflow Status */ -#define TC_SR1_LOVRS (0x1 << 1) /**< \brief (TC_SR1) Load Overrun Status */ -#define TC_SR1_CPAS (0x1 << 2) /**< \brief (TC_SR1) RA Compare Status */ -#define TC_SR1_CPBS (0x1 << 3) /**< \brief (TC_SR1) RB Compare Status */ -#define TC_SR1_CPCS (0x1 << 4) /**< \brief (TC_SR1) RC Compare Status */ -#define TC_SR1_LDRAS (0x1 << 5) /**< \brief (TC_SR1) RA Loading Status */ -#define TC_SR1_LDRBS (0x1 << 6) /**< \brief (TC_SR1) RB Loading Status */ -#define TC_SR1_ETRGS (0x1 << 7) /**< \brief (TC_SR1) External Trigger Status */ -#define TC_SR1_CLKSTA (0x1 << 16) /**< \brief (TC_SR1) Clock Enabling Status */ -#define TC_SR1_MTIOA (0x1 << 17) /**< \brief (TC_SR1) TIOA Mirror */ -#define TC_SR1_MTIOB (0x1 << 18) /**< \brief (TC_SR1) TIOB Mirror */ -/* -------- TC_IER1 : (TC Offset: 0x64) Interrupt Enable Register (channel = 1) -------- */ -#define TC_IER1_COVFS (0x1 << 0) /**< \brief (TC_IER1) Counter Overflow */ -#define TC_IER1_LOVRS (0x1 << 1) /**< \brief (TC_IER1) Load Overrun */ -#define TC_IER1_CPAS (0x1 << 2) /**< \brief (TC_IER1) RA Compare */ -#define TC_IER1_CPBS (0x1 << 3) /**< \brief (TC_IER1) RB Compare */ -#define TC_IER1_CPCS (0x1 << 4) /**< \brief (TC_IER1) RC Compare */ -#define TC_IER1_LDRAS (0x1 << 5) /**< \brief (TC_IER1) RA Loading */ -#define TC_IER1_LDRBS (0x1 << 6) /**< \brief (TC_IER1) RB Loading */ -#define TC_IER1_ETRGS (0x1 << 7) /**< \brief (TC_IER1) External Trigger */ -/* -------- TC_IDR1 : (TC Offset: 0x68) Interrupt Disable Register (channel = 1) -------- */ -#define TC_IDR1_COVFS (0x1 << 0) /**< \brief (TC_IDR1) Counter Overflow */ -#define TC_IDR1_LOVRS (0x1 << 1) /**< \brief (TC_IDR1) Load Overrun */ -#define TC_IDR1_CPAS (0x1 << 2) /**< \brief (TC_IDR1) RA Compare */ -#define TC_IDR1_CPBS (0x1 << 3) /**< \brief (TC_IDR1) RB Compare */ -#define TC_IDR1_CPCS (0x1 << 4) /**< \brief (TC_IDR1) RC Compare */ -#define TC_IDR1_LDRAS (0x1 << 5) /**< \brief (TC_IDR1) RA Loading */ -#define TC_IDR1_LDRBS (0x1 << 6) /**< \brief (TC_IDR1) RB Loading */ -#define TC_IDR1_ETRGS (0x1 << 7) /**< \brief (TC_IDR1) External Trigger */ -/* -------- TC_IMR1 : (TC Offset: 0x6C) Interrupt Mask Register (channel = 1) -------- */ -#define TC_IMR1_COVFS (0x1 << 0) /**< \brief (TC_IMR1) Counter Overflow */ -#define TC_IMR1_LOVRS (0x1 << 1) /**< \brief (TC_IMR1) Load Overrun */ -#define TC_IMR1_CPAS (0x1 << 2) /**< \brief (TC_IMR1) RA Compare */ -#define TC_IMR1_CPBS (0x1 << 3) /**< \brief (TC_IMR1) RB Compare */ -#define TC_IMR1_CPCS (0x1 << 4) /**< \brief (TC_IMR1) RC Compare */ -#define TC_IMR1_LDRAS (0x1 << 5) /**< \brief (TC_IMR1) RA Loading */ -#define TC_IMR1_LDRBS (0x1 << 6) /**< \brief (TC_IMR1) RB Loading */ -#define TC_IMR1_ETRGS (0x1 << 7) /**< \brief (TC_IMR1) External Trigger */ -/* -------- TC_CCR2 : (TC Offset: 0x80) Channel Control Register (channel = 2) -------- */ -#define TC_CCR2_CLKEN (0x1 << 0) /**< \brief (TC_CCR2) Counter Clock Enable Command */ -#define TC_CCR2_CLKDIS (0x1 << 1) /**< \brief (TC_CCR2) Counter Clock Disable Command */ -#define TC_CCR2_SWTRG (0x1 << 2) /**< \brief (TC_CCR2) Software Trigger Command */ -/* -------- TC_CMR2 : (TC Offset: 0x84) Channel Mode Register (channel = 2) -------- */ -#define TC_CMR2_TCCLKS (0x7 << 0) /**< \brief (TC_CMR2) Clock Selection */ -#define TC_CMR2_CLKI (0x1 << 3) /**< \brief (TC_CMR2) Clock Invert */ -#define TC_CMR2_BURST (0x3 << 4) /**< \brief (TC_CMR2) Burst Signal Selection */ -#define TC_CMR2_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR2) The clock is not gated by an external signal. */ -#define TC_CMR2_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR2) XC0 is ANDed with the selected clock. */ -#define TC_CMR2_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR2) XC1 is ANDed with the selected clock. */ -#define TC_CMR2_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR2) XC2 is ANDed with the selected clock. */ -#define TC_CMR2_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR2) Counter Clock Stopped with RB Loading */ -#define TC_CMR2_LDBDIS (0x1 << 7) /**< \brief (TC_CMR2) Counter Clock Disable with RB Loading */ -#define TC_CMR2_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR2) External Trigger Edge Selection */ -#define TC_CMR2_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR2) rising edge */ -#define TC_CMR2_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR2) falling edge */ -#define TC_CMR2_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR2) each edge */ -#define TC_CMR2_ABETRG (0x1 << 10) /**< \brief (TC_CMR2) TIOA or TIOB External Trigger Selection */ -#define TC_CMR2_CPCTRG (0x1 << 14) /**< \brief (TC_CMR2) RC Compare Trigger Enable */ -#define TC_CMR2_WAVE (0x1 << 15) /**< \brief (TC_CMR2) */ -#define TC_CMR2_LDRA (0x3 << 16) /**< \brief (TC_CMR2) RA Loading Selection */ -#define TC_CMR2_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR2) rising edge of TIOA */ -#define TC_CMR2_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR2) falling edge of TIOA */ -#define TC_CMR2_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR2) each edge of TIOA */ -#define TC_CMR2_LDRB (0x3 << 18) /**< \brief (TC_CMR2) RB Loading Selection */ -#define TC_CMR2_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR2) rising edge of TIOA */ -#define TC_CMR2_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR2) falling edge of TIOA */ -#define TC_CMR2_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR2) each edge of TIOA */ -/* -------- TC_CV2 : (TC Offset: 0x90) Counter Value (channel = 2) -------- */ -#define TC_CV2_CV (0xffff << 0) /**< \brief (TC_CV2) Counter Value */ -/* -------- TC_RA2 : (TC Offset: 0x94) Register A (channel = 2) -------- */ -#define TC_RA2_RA (0xffff << 0) /**< \brief (TC_RA2) Register A */ -/* -------- TC_RB2 : (TC Offset: 0x98) Register B (channel = 2) -------- */ -#define TC_RB2_RB (0xffff << 0) /**< \brief (TC_RB2) Register B */ -/* -------- TC_RC2 : (TC Offset: 0x9C) Register C (channel = 2) -------- */ -#define TC_RC2_RC (0xffff << 0) /**< \brief (TC_RC2) Register C */ -/* -------- TC_SR2 : (TC Offset: 0xA0) Status Register (channel = 2) -------- */ -#define TC_SR2_COVFS (0x1 << 0) /**< \brief (TC_SR2) Counter Overflow Status */ -#define TC_SR2_LOVRS (0x1 << 1) /**< \brief (TC_SR2) Load Overrun Status */ -#define TC_SR2_CPAS (0x1 << 2) /**< \brief (TC_SR2) RA Compare Status */ -#define TC_SR2_CPBS (0x1 << 3) /**< \brief (TC_SR2) RB Compare Status */ -#define TC_SR2_CPCS (0x1 << 4) /**< \brief (TC_SR2) RC Compare Status */ -#define TC_SR2_LDRAS (0x1 << 5) /**< \brief (TC_SR2) RA Loading Status */ -#define TC_SR2_LDRBS (0x1 << 6) /**< \brief (TC_SR2) RB Loading Status */ -#define TC_SR2_ETRGS (0x1 << 7) /**< \brief (TC_SR2) External Trigger Status */ -#define TC_SR2_CLKSTA (0x1 << 16) /**< \brief (TC_SR2) Clock Enabling Status */ -#define TC_SR2_MTIOA (0x1 << 17) /**< \brief (TC_SR2) TIOA Mirror */ -#define TC_SR2_MTIOB (0x1 << 18) /**< \brief (TC_SR2) TIOB Mirror */ -/* -------- TC_IER2 : (TC Offset: 0xA4) Interrupt Enable Register (channel = 2) -------- */ -#define TC_IER2_COVFS (0x1 << 0) /**< \brief (TC_IER2) Counter Overflow */ -#define TC_IER2_LOVRS (0x1 << 1) /**< \brief (TC_IER2) Load Overrun */ -#define TC_IER2_CPAS (0x1 << 2) /**< \brief (TC_IER2) RA Compare */ -#define TC_IER2_CPBS (0x1 << 3) /**< \brief (TC_IER2) RB Compare */ -#define TC_IER2_CPCS (0x1 << 4) /**< \brief (TC_IER2) RC Compare */ -#define TC_IER2_LDRAS (0x1 << 5) /**< \brief (TC_IER2) RA Loading */ -#define TC_IER2_LDRBS (0x1 << 6) /**< \brief (TC_IER2) RB Loading */ -#define TC_IER2_ETRGS (0x1 << 7) /**< \brief (TC_IER2) External Trigger */ -/* -------- TC_IDR2 : (TC Offset: 0xA8) Interrupt Disable Register (channel = 2) -------- */ -#define TC_IDR2_COVFS (0x1 << 0) /**< \brief (TC_IDR2) Counter Overflow */ -#define TC_IDR2_LOVRS (0x1 << 1) /**< \brief (TC_IDR2) Load Overrun */ -#define TC_IDR2_CPAS (0x1 << 2) /**< \brief (TC_IDR2) RA Compare */ -#define TC_IDR2_CPBS (0x1 << 3) /**< \brief (TC_IDR2) RB Compare */ -#define TC_IDR2_CPCS (0x1 << 4) /**< \brief (TC_IDR2) RC Compare */ -#define TC_IDR2_LDRAS (0x1 << 5) /**< \brief (TC_IDR2) RA Loading */ -#define TC_IDR2_LDRBS (0x1 << 6) /**< \brief (TC_IDR2) RB Loading */ -#define TC_IDR2_ETRGS (0x1 << 7) /**< \brief (TC_IDR2) External Trigger */ -/* -------- TC_IMR2 : (TC Offset: 0xAC) Interrupt Mask Register (channel = 2) -------- */ -#define TC_IMR2_COVFS (0x1 << 0) /**< \brief (TC_IMR2) Counter Overflow */ -#define TC_IMR2_LOVRS (0x1 << 1) /**< \brief (TC_IMR2) Load Overrun */ -#define TC_IMR2_CPAS (0x1 << 2) /**< \brief (TC_IMR2) RA Compare */ -#define TC_IMR2_CPBS (0x1 << 3) /**< \brief (TC_IMR2) RB Compare */ -#define TC_IMR2_CPCS (0x1 << 4) /**< \brief (TC_IMR2) RC Compare */ -#define TC_IMR2_LDRAS (0x1 << 5) /**< \brief (TC_IMR2) RA Loading */ -#define TC_IMR2_LDRBS (0x1 << 6) /**< \brief (TC_IMR2) RB Loading */ -#define TC_IMR2_ETRGS (0x1 << 7) /**< \brief (TC_IMR2) External Trigger */ -/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ -#define TC_BCR_SYNC (0x1 << 0) /**< \brief (TC_BCR) Synchro Command */ -/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ -#define TC_BMR_TC0XC0S (0x3 << 0) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ -#define TC_BMR_TC0XC0S_TCLK0 (0x0 << 0) /**< \brief (TC_BMR) TCLK0 */ -#define TC_BMR_TC0XC0S_NONE (0x1 << 0) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC0XC0S_TIOA1 (0x2 << 0) /**< \brief (TC_BMR) TIOA1 */ -#define TC_BMR_TC0XC0S_TIOA2 (0x3 << 0) /**< \brief (TC_BMR) TIOA2 */ -#define TC_BMR_TC1XC1S (0x3 << 2) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ -#define TC_BMR_TC1XC1S_TCLK1 (0x0 << 2) /**< \brief (TC_BMR) TCLK1 */ -#define TC_BMR_TC1XC1S_NONE (0x1 << 2) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC1XC1S_TIOA0 (0x2 << 2) /**< \brief (TC_BMR) TIOA0 */ -#define TC_BMR_TC1XC1S_TIOA2 (0x3 << 2) /**< \brief (TC_BMR) TIOA2 */ -#define TC_BMR_TC2XC2S (0x3 << 4) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ -#define TC_BMR_TC2XC2S_TCLK2 (0x0 << 4) /**< \brief (TC_BMR) TCLK2 */ -#define TC_BMR_TC2XC2S_NONE (0x1 << 4) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC2XC2S_TIOA0 (0x2 << 4) /**< \brief (TC_BMR) TIOA0 */ -#define TC_BMR_TC2XC2S_TIOA1 (0x3 << 4) /**< \brief (TC_BMR) TIOA1 */ -#define TC_BMR_QDEN (0x1 << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */ -#define TC_BMR_POSEN (0x1 << 9) /**< \brief (TC_BMR) POSition ENabled */ -#define TC_BMR_SPEEDEN (0x1 << 10) /**< \brief (TC_BMR) SPEED ENabled */ -#define TC_BMR_QDTRANS (0x1 << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */ -#define TC_BMR_EDGPHA (0x1 << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */ -#define TC_BMR_INVA (0x1 << 13) /**< \brief (TC_BMR) INVerted phA */ -#define TC_BMR_INVB (0x1 << 14) /**< \brief (TC_BMR) INVerted phB */ -#define TC_BMR_INVIDX (0x1 << 15) /**< \brief (TC_BMR) INVerted InDeX */ -#define TC_BMR_SWAP (0x1 << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */ -#define TC_BMR_IDXPHB (0x1 << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */ -#define TC_BMR_FILTER (0x1 << 19) /**< \brief (TC_BMR) */ -#define TC_BMR_MAXFILT (0x3f << 20) /**< \brief (TC_BMR) MAXimum FILTer */ -/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ -#define TC_QIER_IDX (0x1 << 0) /**< \brief (TC_QIER) InDeX */ -#define TC_QIER_DIRCHG (0x1 << 1) /**< \brief (TC_QIER) DIRection CHanGe */ -#define TC_QIER_QERR (0x1 << 2) /**< \brief (TC_QIER) Quadrature ERRor */ -/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ -#define TC_QIDR_IDX (0x1 << 0) /**< \brief (TC_QIDR) InDeX */ -#define TC_QIDR_DIRCHG (0x1 << 1) /**< \brief (TC_QIDR) DIRection CHanGe */ -#define TC_QIDR_QERR (0x1 << 2) /**< \brief (TC_QIDR) Quadrature ERRor */ -/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ -#define TC_QIMR_IDX (0x1 << 0) /**< \brief (TC_QIMR) InDeX */ -#define TC_QIMR_DIRCHG (0x1 << 1) /**< \brief (TC_QIMR) DIRection CHanGe */ -#define TC_QIMR_QERR (0x1 << 2) /**< \brief (TC_QIMR) Quadrature ERRor */ -/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ -#define TC_QISR_IDX (0x1 << 0) /**< \brief (TC_QISR) InDeX */ -#define TC_QISR_DIRCHG (0x1 << 1) /**< \brief (TC_QISR) DIRection CHanGe */ -#define TC_QISR_QERR (0x1 << 2) /**< \brief (TC_QISR) Quadrature ERRor */ -#define TC_QISR_DIR (0x1 << 8) /**< \brief (TC_QISR) Direction */ -/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ -#define TC_FMR_ENCF0 (0x1 << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */ -#define TC_FMR_ENCF1 (0x1 << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */ -/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */ -#define TC_WPMR_WPEN (0x1 << 0) /**< \brief (TC_WPMR) Write Protect Enable */ -#define TC_WPMR_WPKEY (0xffffff << 8) /**< \brief (TC_WPMR) Write Protect KEY */ -/* -------- TC_VER : (TC Offset: 0xFC) Version Register -------- */ -#define TC_VER_VERSION (0xfff << 0) /**< \brief (TC_VER) */ -#define TC_VER_MFN (0x7 << 16) /**< \brief (TC_VER) */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Two-wire Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_TWI Two-wire Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Twi hardware registers */ -typedef struct { - WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */ - RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */ - RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */ - RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */ - RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */ - RwReg Reserved1[3]; - RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */ - WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */ - WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */ - RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */ - RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */ - WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */ - RwReg Reserved2[50]; - RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */ - RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */ - RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */ - RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */ - RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */ - RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */ - RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */ - RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */ - WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */ - RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */ -} Twi; -#endif /* __ASSEMBLY__ */ -/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */ -#define TWI_CR_START (0x1 << 0) /**< \brief (TWI_CR) Send a START Condition */ -#define TWI_CR_STOP (0x1 << 1) /**< \brief (TWI_CR) Send a STOP Condition */ -#define TWI_CR_MSEN (0x1 << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */ -#define TWI_CR_MSDIS (0x1 << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */ -#define TWI_CR_SVEN (0x1 << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */ -#define TWI_CR_SVDIS (0x1 << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */ -#define TWI_CR_QUICK (0x1 << 6) /**< \brief (TWI_CR) SMBUS Quick Command */ -#define TWI_CR_SWRST (0x1 << 7) /**< \brief (TWI_CR) Software Reset */ -/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */ -#define TWI_MMR_IADRSZ (0x3 << 8) /**< \brief (TWI_MMR) Internal Device Address Size */ -#define TWI_MMR_IADRSZ_NO (0x0 << 8) /**< \brief (TWI_MMR) No internal device address */ -#define TWI_MMR_IADRSZ_1_BYTE (0x1 << 8) /**< \brief (TWI_MMR) One-byte internal device address */ -#define TWI_MMR_IADRSZ_2_BYTE (0x2 << 8) /**< \brief (TWI_MMR) Two-byte internal device address */ -#define TWI_MMR_IADRSZ_3_BYTE (0x3 << 8) /**< \brief (TWI_MMR) Three-byte internal device address */ -#define TWI_MMR_MREAD (0x1 << 12) /**< \brief (TWI_MMR) Master Read Direction */ -#define TWI_MMR_DADR (0x7f << 16) /**< \brief (TWI_MMR) Device Address */ -/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */ -#define TWI_SMR_SADR (0x7f << 16) /**< \brief (TWI_SMR) Slave Address */ -/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */ -#define TWI_IADR_IADR (0xffffff << 0) /**< \brief (TWI_IADR) Internal Address */ -/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */ -#define TWI_CWGR_CLDIV (0xff << 0) /**< \brief (TWI_CWGR) Clock Low Divider */ -#define TWI_CWGR_CHDIV (0xff << 8) /**< \brief (TWI_CWGR) Clock High Divider */ -#define TWI_CWGR_CKDIV (0x7 << 16) /**< \brief (TWI_CWGR) Clock Divider */ -/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */ -#define TWI_SR_TXCOMP (0x1 << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */ -#define TWI_SR_RXRDY (0x1 << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */ -#define TWI_SR_TXRDY (0x1 << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */ -#define TWI_SR_SVREAD (0x1 << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */ -#define TWI_SR_SVACC (0x1 << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */ -#define TWI_SR_GACC (0x1 << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */ -#define TWI_SR_OVRE (0x1 << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */ -#define TWI_SR_NACK (0x1 << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */ -#define TWI_SR_ARBLST (0x1 << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */ -#define TWI_SR_SCLWS (0x1 << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */ -#define TWI_SR_EOSACC (0x1 << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */ -#define TWI_SR_ENDRX (0x1 << 12) /**< \brief (TWI_SR) End of RX buffer */ -#define TWI_SR_ENDTX (0x1 << 13) /**< \brief (TWI_SR) End of TX buffer */ -#define TWI_SR_RXBUFF (0x1 << 14) /**< \brief (TWI_SR) RX Buffer Full */ -#define TWI_SR_TXBUFE (0x1 << 15) /**< \brief (TWI_SR) TX Buffer Empty */ -/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */ -#define TWI_IER_TXCOMP (0x1 << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */ -#define TWI_IER_RXRDY (0x1 << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */ -#define TWI_IER_TXRDY (0x1 << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */ -#define TWI_IER_SVACC (0x1 << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */ -#define TWI_IER_GACC (0x1 << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */ -#define TWI_IER_OVRE (0x1 << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */ -#define TWI_IER_NACK (0x1 << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */ -#define TWI_IER_ARBLST (0x1 << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */ -#define TWI_IER_SCL_WS (0x1 << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */ -#define TWI_IER_EOSACC (0x1 << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */ -#define TWI_IER_ENDRX (0x1 << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */ -#define TWI_IER_ENDTX (0x1 << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */ -#define TWI_IER_RXBUFF (0x1 << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */ -#define TWI_IER_TXBUFE (0x1 << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */ -/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */ -#define TWI_IDR_TXCOMP (0x1 << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */ -#define TWI_IDR_RXRDY (0x1 << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */ -#define TWI_IDR_TXRDY (0x1 << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */ -#define TWI_IDR_SVACC (0x1 << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */ -#define TWI_IDR_GACC (0x1 << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */ -#define TWI_IDR_OVRE (0x1 << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */ -#define TWI_IDR_NACK (0x1 << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */ -#define TWI_IDR_ARBLST (0x1 << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */ -#define TWI_IDR_SCL_WS (0x1 << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */ -#define TWI_IDR_EOSACC (0x1 << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */ -#define TWI_IDR_ENDRX (0x1 << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */ -#define TWI_IDR_ENDTX (0x1 << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */ -#define TWI_IDR_RXBUFF (0x1 << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */ -#define TWI_IDR_TXBUFE (0x1 << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */ -/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */ -#define TWI_IMR_TXCOMP (0x1 << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */ -#define TWI_IMR_RXRDY (0x1 << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */ -#define TWI_IMR_TXRDY (0x1 << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */ -#define TWI_IMR_SVACC (0x1 << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */ -#define TWI_IMR_GACC (0x1 << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */ -#define TWI_IMR_OVRE (0x1 << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */ -#define TWI_IMR_NACK (0x1 << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */ -#define TWI_IMR_ARBLST (0x1 << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */ -#define TWI_IMR_SCL_WS (0x1 << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */ -#define TWI_IMR_EOSACC (0x1 << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */ -#define TWI_IMR_ENDRX (0x1 << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */ -#define TWI_IMR_ENDTX (0x1 << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */ -#define TWI_IMR_RXBUFF (0x1 << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */ -#define TWI_IMR_TXBUFE (0x1 << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */ -/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */ -#define TWI_RHR_RXDATA (0xff << 0) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */ -/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */ -#define TWI_THR_TXDATA (0xff << 0) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */ -/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */ -#define TWI_RPR_RXPTR (0xffffffff << 0) /**< \brief (TWI_RPR) Receive Pointer Register */ -/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */ -#define TWI_RCR_RXCTR (0xffff << 0) /**< \brief (TWI_RCR) Receive Counter Register */ -/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */ -#define TWI_TPR_TXPTR (0xffffffff << 0) /**< \brief (TWI_TPR) Transmit Counter Register */ -/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */ -#define TWI_TCR_TXCTR (0xffff << 0) /**< \brief (TWI_TCR) Transmit Counter Register */ -/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */ -#define TWI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (TWI_RNPR) Receive Next Pointer */ -/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */ -#define TWI_RNCR_RXNCTR (0xffff << 0) /**< \brief (TWI_RNCR) Receive Next Counter */ -/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define TWI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (TWI_TNPR) Transmit Next Pointer */ -/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define TWI_TNCR_TXNCTR (0xffff << 0) /**< \brief (TWI_TNCR) Transmit Counter Next */ -/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */ -#define TWI_PTCR_RXTEN (0x1 << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */ -#define TWI_PTCR_RXTDIS (0x1 << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */ -#define TWI_PTCR_TXTEN (0x1 << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */ -#define TWI_PTCR_TXTDIS (0x1 << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */ -/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */ -#define TWI_PTSR_RXTEN (0x1 << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */ -#define TWI_PTSR_TXTEN (0x1 << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_UART Universal Asynchronous Receiver Transmitter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Uart hardware registers */ -typedef struct { - WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ - RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ - WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ - WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ - RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ - RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ - RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ - WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ - RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ - RwReg Reserved1[55]; - RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */ - RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */ - RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */ - RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */ - RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */ - RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */ - RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */ - RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */ - WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */ - RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */ -} Uart; -#endif /* __ASSEMBLY__ */ -/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ -#define UART_CR_RSTRX (0x1 << 2) /**< \brief (UART_CR) Reset Receiver */ -#define UART_CR_RSTTX (0x1 << 3) /**< \brief (UART_CR) Reset Transmitter */ -#define UART_CR_RXEN (0x1 << 4) /**< \brief (UART_CR) Receiver Enable */ -#define UART_CR_RXDIS (0x1 << 5) /**< \brief (UART_CR) Receiver Disable */ -#define UART_CR_TXEN (0x1 << 6) /**< \brief (UART_CR) Transmitter Enable */ -#define UART_CR_TXDIS (0x1 << 7) /**< \brief (UART_CR) Transmitter Disable */ -#define UART_CR_RSTSTA (0x1 << 8) /**< \brief (UART_CR) Reset Status Bits */ -/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ -#define UART_MR_PAR (0x7 << 9) /**< \brief (UART_MR) Parity Type */ -#define UART_MR_CHMODE (0x3 << 14) /**< \brief (UART_MR) Channel Mode */ -/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ -#define UART_IER_RXRDY (0x1 << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ -#define UART_IER_TXRDY (0x1 << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ -#define UART_IER_ENDRX (0x1 << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */ -#define UART_IER_ENDTX (0x1 << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */ -#define UART_IER_OVRE (0x1 << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ -#define UART_IER_FRAME (0x1 << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ -#define UART_IER_PARE (0x1 << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ -#define UART_IER_TXEMPTY (0x1 << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ -#define UART_IER_TXBUFE (0x1 << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */ -#define UART_IER_RXBUFF (0x1 << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */ -/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ -#define UART_IDR_RXRDY (0x1 << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ -#define UART_IDR_TXRDY (0x1 << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ -#define UART_IDR_ENDRX (0x1 << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */ -#define UART_IDR_ENDTX (0x1 << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */ -#define UART_IDR_OVRE (0x1 << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ -#define UART_IDR_FRAME (0x1 << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ -#define UART_IDR_PARE (0x1 << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ -#define UART_IDR_TXEMPTY (0x1 << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ -#define UART_IDR_TXBUFE (0x1 << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */ -#define UART_IDR_RXBUFF (0x1 << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */ -/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ -#define UART_IMR_RXRDY (0x1 << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ -#define UART_IMR_TXRDY (0x1 << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ -#define UART_IMR_ENDRX (0x1 << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */ -#define UART_IMR_ENDTX (0x1 << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */ -#define UART_IMR_OVRE (0x1 << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ -#define UART_IMR_FRAME (0x1 << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ -#define UART_IMR_PARE (0x1 << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ -#define UART_IMR_TXEMPTY (0x1 << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ -#define UART_IMR_TXBUFE (0x1 << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */ -#define UART_IMR_RXBUFF (0x1 << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */ -/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ -#define UART_SR_RXRDY (0x1 << 0) /**< \brief (UART_SR) Receiver Ready */ -#define UART_SR_TXRDY (0x1 << 1) /**< \brief (UART_SR) Transmitter Ready */ -#define UART_SR_ENDRX (0x1 << 3) /**< \brief (UART_SR) End of Receiver Transfer */ -#define UART_SR_ENDTX (0x1 << 4) /**< \brief (UART_SR) End of Transmitter Transfer */ -#define UART_SR_OVRE (0x1 << 5) /**< \brief (UART_SR) Overrun Error */ -#define UART_SR_FRAME (0x1 << 6) /**< \brief (UART_SR) Framing Error */ -#define UART_SR_PARE (0x1 << 7) /**< \brief (UART_SR) Parity Error */ -#define UART_SR_TXEMPTY (0x1 << 9) /**< \brief (UART_SR) Transmitter Empty */ -#define UART_SR_TXBUFE (0x1 << 11) /**< \brief (UART_SR) Transmission Buffer Empty */ -#define UART_SR_RXBUFF (0x1 << 12) /**< \brief (UART_SR) Receive Buffer Full */ -/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ -#define UART_RHR_RXCHR (0xff << 0) /**< \brief (UART_RHR) Received Character */ -/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ -#define UART_THR_TXCHR (0xff << 0) /**< \brief (UART_THR) Character to be Transmitted */ -/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ -#define UART_BRGR_CD (0xffff << 0) /**< \brief (UART_BRGR) Clock Divisor */ -/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */ -#define UART_RPR_RXPTR (0xffffffff << 0) /**< \brief (UART_RPR) Receive Pointer Register */ -/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */ -#define UART_RCR_RXCTR (0xffff << 0) /**< \brief (UART_RCR) Receive Counter Register */ -/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */ -#define UART_TPR_TXPTR (0xffffffff << 0) /**< \brief (UART_TPR) Transmit Counter Register */ -/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */ -#define UART_TCR_TXCTR (0xffff << 0) /**< \brief (UART_TCR) Transmit Counter Register */ -/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */ -#define UART_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (UART_RNPR) Receive Next Pointer */ -/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */ -#define UART_RNCR_RXNCTR (0xffff << 0) /**< \brief (UART_RNCR) Receive Next Counter */ -/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */ -#define UART_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (UART_TNPR) Transmit Next Pointer */ -/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */ -#define UART_TNCR_TXNCTR (0xffff << 0) /**< \brief (UART_TNCR) Transmit Counter Next */ -/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */ -#define UART_PTCR_RXTEN (0x1 << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */ -#define UART_PTCR_RXTDIS (0x1 << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */ -#define UART_PTCR_TXTEN (0x1 << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */ -#define UART_PTCR_TXTDIS (0x1 << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */ -/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */ -#define UART_PTSR_RXTEN (0x1 << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */ -#define UART_PTSR_TXTEN (0x1 << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR USB Device Port */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_UDP USB Device Port */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Udp hardware registers */ -typedef struct { - RoReg UDP_FRM_NUM; /**< \brief (Udp Offset: 0x000) Frame Number Register */ - RwReg UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */ - RwReg UDP_FADDR; /**< \brief (Udp Offset: 0x008) Function Address Register */ - RwReg Reserved1[1]; - WoReg UDP_IER; /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */ - WoReg UDP_IDR; /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */ - RoReg UDP_IMR; /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */ - RoReg UDP_ISR; /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */ - WoReg UDP_ICR; /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */ - RwReg Reserved2[1]; - RwReg UDP_RST_EP; /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */ - RwReg Reserved3[1]; - RwReg UDP_CSR[8]; /**< \brief (Udp Offset: 0x30) Endpoint Control and Status Register (ept_num = 0) */ - RwReg UDP_FDR[8]; /**< \brief (Udp Offset: 0x50) Endpoint FIFO Data Register (ept_num = 0) */ - RwReg Reserved4[1]; - RwReg UDP_TXVC; /**< \brief (Udp Offset: 0x074) Transceiver Control Register */ -} Udp; -#endif /* __ASSEMBLY__ */ -/* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */ -#define UDP_FRM_NUM_FRM_NUM (0x7ff << 0) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */ -#define UDP_FRM_NUM_FRM_ERR (0x1 << 16) /**< \brief (UDP_FRM_NUM) Frame Error */ -#define UDP_FRM_NUM_FRM_OK (0x1 << 17) /**< \brief (UDP_FRM_NUM) Frame OK */ -/* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */ -#define UDP_GLB_STAT_FADDEN (0x1 << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */ -#define UDP_GLB_STAT_CONFG (0x1 << 1) /**< \brief (UDP_GLB_STAT) Configured */ -#define UDP_GLB_STAT_ESR (0x1 << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */ -#define UDP_GLB_STAT_RSMINPR (0x1 << 3) /**< \brief (UDP_GLB_STAT) */ -#define UDP_GLB_STAT_RMWUPE (0x1 << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */ -/* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */ -#define UDP_FADDR_FADD (0x7f << 0) /**< \brief (UDP_FADDR) Function Address Value */ -#define UDP_FADDR_FEN (0x1 << 8) /**< \brief (UDP_FADDR) Function Enable */ -/* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */ -#define UDP_IER_EP0INT (0x1 << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */ -#define UDP_IER_EP1INT (0x1 << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */ -#define UDP_IER_EP2INT (0x1 << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */ -#define UDP_IER_EP3INT (0x1 << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */ -#define UDP_IER_EP4INT (0x1 << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */ -#define UDP_IER_EP5INT (0x1 << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */ -#define UDP_IER_EP6INT (0x1 << 6) /**< \brief (UDP_IER) Enable Endpoint 6 Interrupt */ -#define UDP_IER_EP7INT (0x1 << 7) /**< \brief (UDP_IER) Enable Endpoint 7 Interrupt */ -#define UDP_IER_RXSUSP (0x1 << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */ -#define UDP_IER_RXRSM (0x1 << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */ -#define UDP_IER_EXTRSM (0x1 << 10) /**< \brief (UDP_IER) */ -#define UDP_IER_SOFINT (0x1 << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */ -#define UDP_IER_WAKEUP (0x1 << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */ -/* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */ -#define UDP_IDR_EP0INT (0x1 << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */ -#define UDP_IDR_EP1INT (0x1 << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */ -#define UDP_IDR_EP2INT (0x1 << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */ -#define UDP_IDR_EP3INT (0x1 << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */ -#define UDP_IDR_EP4INT (0x1 << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */ -#define UDP_IDR_EP5INT (0x1 << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */ -#define UDP_IDR_EP6INT (0x1 << 6) /**< \brief (UDP_IDR) Disable Endpoint 6 Interrupt */ -#define UDP_IDR_EP7INT (0x1 << 7) /**< \brief (UDP_IDR) Disable Endpoint 7 Interrupt */ -#define UDP_IDR_RXSUSP (0x1 << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */ -#define UDP_IDR_RXRSM (0x1 << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */ -#define UDP_IDR_EXTRSM (0x1 << 10) /**< \brief (UDP_IDR) */ -#define UDP_IDR_SOFINT (0x1 << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */ -#define UDP_IDR_WAKEUP (0x1 << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */ -/* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */ -#define UDP_IMR_EP0INT (0x1 << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */ -#define UDP_IMR_EP1INT (0x1 << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */ -#define UDP_IMR_EP2INT (0x1 << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */ -#define UDP_IMR_EP3INT (0x1 << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */ -#define UDP_IMR_EP4INT (0x1 << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */ -#define UDP_IMR_EP5INT (0x1 << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */ -#define UDP_IMR_EP6INT (0x1 << 6) /**< \brief (UDP_IMR) Mask Endpoint 6 Interrupt */ -#define UDP_IMR_EP7INT (0x1 << 7) /**< \brief (UDP_IMR) Mask Endpoint 7 Interrupt */ -#define UDP_IMR_RXSUSP (0x1 << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */ -#define UDP_IMR_RXRSM (0x1 << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */ -#define UDP_IMR_EXTRSM (0x1 << 10) /**< \brief (UDP_IMR) */ -#define UDP_IMR_SOFINT (0x1 << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */ -#define UDP_IMR_BIT12 (0x1 << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */ -#define UDP_IMR_WAKEUP (0x1 << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */ -/* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */ -#define UDP_ISR_EP0INT (0x1 << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */ -#define UDP_ISR_EP1INT (0x1 << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */ -#define UDP_ISR_EP2INT (0x1 << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */ -#define UDP_ISR_EP3INT (0x1 << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */ -#define UDP_ISR_EP4INT (0x1 << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */ -#define UDP_ISR_EP5INT (0x1 << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */ -#define UDP_ISR_EP6INT (0x1 << 6) /**< \brief (UDP_ISR) Endpoint 6 Interrupt Status */ -#define UDP_ISR_EP7INT (0x1 << 7) /**< \brief (UDP_ISR) Endpoint 7Interrupt Status */ -#define UDP_ISR_RXSUSP (0x1 << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */ -#define UDP_ISR_RXRSM (0x1 << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ -#define UDP_ISR_EXTRSM (0x1 << 10) /**< \brief (UDP_ISR) */ -#define UDP_ISR_SOFINT (0x1 << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */ -#define UDP_ISR_ENDBUSRES (0x1 << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */ -#define UDP_ISR_WAKEUP (0x1 << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ -/* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */ -#define UDP_ICR_RXSUSP (0x1 << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */ -#define UDP_ICR_RXRSM (0x1 << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */ -#define UDP_ICR_EXTRSM (0x1 << 10) /**< \brief (UDP_ICR) */ -#define UDP_ICR_SOFINT (0x1 << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */ -#define UDP_ICR_ENDBUSRES (0x1 << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */ -#define UDP_ICR_WAKEUP (0x1 << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */ -/* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */ -#define UDP_RST_EP_EP0 (0x1 << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */ -#define UDP_RST_EP_EP1 (0x1 << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */ -#define UDP_RST_EP_EP2 (0x1 << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */ -#define UDP_RST_EP_EP3 (0x1 << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */ -#define UDP_RST_EP_EP4 (0x1 << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */ -#define UDP_RST_EP_EP5 (0x1 << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */ -#define UDP_RST_EP_EP6 (0x1 << 6) /**< \brief (UDP_RST_EP) Reset Endpoint 6 */ -#define UDP_RST_EP_EP7 (0x1 << 7) /**< \brief (UDP_RST_EP) Reset Endpoint 7 */ -/* -------- UDP_CSR[8] : (UDP Offset: 0x2C) Endpoint Control and Status Register (ept_num = 0) -------- */ -#define UDP_CSR_TXCOMP (0x1 << 0) /**< \brief (UDP_CSR[8]) Generates an IN Packet with Data Previously Written in the DPR */ -#define UDP_CSR_RX_DATA_BK0 (0x1 << 1) /**< \brief (UDP_CSR[8]) Receive Data Bank 0 */ -#define UDP_CSR_RXSETUP (0x1 << 2) /**< \brief (UDP_CSR[8]) Received Setup */ -#define UDP_CSR_STALLSENTISOERROR (0x1 << 3) /**< \brief (UDP_CSR[8]) */ -#define UDP_CSR_TXPKTRDY (0x1 << 4) /**< \brief (UDP_CSR[8]) Transmit Packet Ready */ -#define UDP_CSR_FORCESTALL (0x1 << 5) /**< \brief (UDP_CSR[8]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */ -#define UDP_CSR_RX_DATA_BK1 (0x1 << 6) /**< \brief (UDP_CSR[8]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */ -#define UDP_CSR_DIR (0x1 << 7) /**< \brief (UDP_CSR[8]) Transfer Direction (only available for control endpoints) */ -#define UDP_CSR_EPTYPE (0x7 << 8) /**< \brief (UDP_CSR[8]) Endpoint Type */ -#define UDP_CSR_EPTYPE_CTRL (0x0 << 8) /**< \brief (UDP_CSR[8]) Control */ -#define UDP_CSR_EPTYPE_ISO_OUT (0x1 << 8) /**< \brief (UDP_CSR[8]) Isochronous OUT */ -#define UDP_CSR_EPTYPE_BULK_OUT (0x2 << 8) /**< \brief (UDP_CSR[8]) Bulk OUT */ -#define UDP_CSR_EPTYPE_INT_OUT (0x3 << 8) /**< \brief (UDP_CSR[8]) Interrupt OUT */ -#define UDP_CSR_EPTYPE_ISO_IN (0x5 << 8) /**< \brief (UDP_CSR[8]) Isochronous IN */ -#define UDP_CSR_EPTYPE_BULK_IN (0x6 << 8) /**< \brief (UDP_CSR[8]) Bulk IN */ -#define UDP_CSR_EPTYPE_INT_IN (0x7 << 8) /**< \brief (UDP_CSR[8]) Interrupt IN */ -#define UDP_CSR_DTGLE (0x1 << 11) /**< \brief (UDP_CSR[8]) Data Toggle */ -#define UDP_CSR_EPEDS (0x1 << 15) /**< \brief (UDP_CSR[8]) Endpoint Enable Disable */ -#define UDP_CSR_RXBYTECNT (0x7ff << 16) /**< \brief (UDP_CSR[8]) Number of Bytes Available in the FIFO */ -/* -------- UDP_FDR[8] : (UDP Offset: 0x4C) Endpoint FIFO Data Register (ept_num = 0) -------- */ -#define UDP_FDR_FIFO_DATA (0xff << 0) /**< \brief (UDP_FDR[8]) FIFO Data Value */ -/* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */ -#define UDP_TXVC_TXVDIS (0x1 << 8) /**< \brief (UDP_TXVC) Transceiver Disable */ -#define UDP_TXVC_PUON (0x1 << 9) /**< \brief (UDP_TXVC) Pullup On */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_USART Universal Synchronous Asynchronous Receiver Transmitter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Usart hardware registers */ -typedef struct { - WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ - RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ - WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ - WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ - RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ - RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ - RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */ - WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */ - RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ - RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ - RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ - RwReg Reserved1[5]; - RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ - RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ - RwReg Reserved2[1]; - RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ - RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */ - RwReg Reserved3[36]; - RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */ - RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */ - RwReg Reserved4[4]; - RoReg US_VERSION; /**< \brief (Usart Offset: 0xFC) Version Register */ - RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */ - RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */ - RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */ - RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */ - RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */ - RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */ - RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */ - RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */ - WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */ - RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */ -} Usart; -#endif /* __ASSEMBLY__ */ -/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ -#define US_CR_RSTRX (0x1 << 2) /**< \brief (US_CR) Reset Receiver */ -#define US_CR_RSTTX (0x1 << 3) /**< \brief (US_CR) Reset Transmitter */ -#define US_CR_RXEN (0x1 << 4) /**< \brief (US_CR) Receiver Enable */ -#define US_CR_RXDIS (0x1 << 5) /**< \brief (US_CR) Receiver Disable */ -#define US_CR_TXEN (0x1 << 6) /**< \brief (US_CR) Transmitter Enable */ -#define US_CR_TXDIS (0x1 << 7) /**< \brief (US_CR) Transmitter Disable */ -#define US_CR_RSTSTA (0x1 << 8) /**< \brief (US_CR) Reset Status Bits */ -#define US_CR_STTBRK (0x1 << 9) /**< \brief (US_CR) Start Break */ -#define US_CR_STPBRK (0x1 << 10) /**< \brief (US_CR) Stop Break */ -#define US_CR_STTTO (0x1 << 11) /**< \brief (US_CR) Start Time-out */ -#define US_CR_SENDA (0x1 << 12) /**< \brief (US_CR) Send Address */ -#define US_CR_RSTIT (0x1 << 13) /**< \brief (US_CR) Reset Iterations */ -#define US_CR_RSTNACK (0x1 << 14) /**< \brief (US_CR) Reset Non Acknowledge */ -#define US_CR_RETTO (0x1 << 15) /**< \brief (US_CR) Rearm Time-out */ -#define US_CR_DTREN (0x1 << 16) /**< \brief (US_CR) Data Terminal Ready Enable */ -#define US_CR_DTRDIS (0x1 << 17) /**< \brief (US_CR) Data Terminal Ready Disable */ -#define US_CR_RTSEN__FCS (0x1 << 18) /**< \brief (US_CR) Request to Send Enable/Force SPI Chip Select */ -#define US_CR_RTSDIS__RCS (0x1 << 19) /**< \brief (US_CR) Request to Send Disable/Release SPI Chip Select */ -/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ -#define US_MR_USART_MODE (0xf << 0) /**< \brief (US_MR) */ -#define US_MR_USART_MODE_NORMAL (0x0) /**< (USART) Normal*/ -#define US_MR_USART_MODE_RS485 (0x1) /**< (USART) RS485*/ -#define US_MR_USART_MODE_HWHSH (0x2) /**< (USART) Hardware Handshaking*/ -#define US_MR_USART_MODE_ISO7816_0 (0x4) /**< (USART) ISO7816 protocol: T = 0*/ -#define US_MR_USART_MODE_ISO7816_1 (0x6) /**< (USART) ISO7816 protocol: T = 1*/ -#define US_MR_USART_MODE_IRDA (0x8) /**< (USART) IrDA*/ -#define US_MR_USART_MODE_SPIM (0xE) /**< (USART) SPI Master*/ -#define US_MR_USART_MODE_SPIS (0xF) /**< (USART) SPI Slave*/ -#define US_MR_USCLKS (0x3 << 4) /**< \brief (US_MR) Clock Selection */ -#define US_MR_USCLKS_CLOCK (0x0 << 4) /**< (USART) MCK*/ -#define US_MR_USCLKS_FDIV1 (0x1 << 4) /**< (USART) MCK/DIV(DIV=8)*/ -#define US_MR_USCLKS_SLOW (0x2 << 4) /**< (USART) Reserved*/ -#define US_MR_USCLKS_EXT (0x3 << 4) /**< (USART) SCK*/ -#define US_MR_CHRL (0x3 << 6) /**< \brief (US_MR) Character Length. */ -#define US_MR_CHRL_5_BITS (0x0 << 6) /**< (USART) Character Length: 5 bits*/ -#define US_MR_CHRL_6_BITS (0x1 << 6) /**< (USART) Character Length: 6 bits*/ -#define US_MR_CHRL_7_BITS (0x2 << 6) /**< (USART) Character Length: 7 bits*/ -#define US_MR_CHRL_8_BITS (0x3 << 6) /**< (USART) Character Length: 8 bits*/ -#define US_MR_SYNC__CPHA (0x1 << 8) /**< \brief (US_MR) Synchronous Mode Select or SPI Clock Phase */ -#define US_MR_PAR (0x7 << 9) /**< \brief (US_MR) Parity Type */ -#define US_MR_PAR_EVEN (0x0 << 9) /**< (USART) Even Parity*/ -#define US_MR_PAR_ODD (0x1 << 9) /**< (USART) Odd Parity*/ -#define US_MR_PAR_SPACE (0x2 << 9) /**< (USART) Parity forced to 0 (Space)*/ -#define US_MR_PAR_MARK (0x3 << 9) /**< (USART) Parity forced to 1 (Mark)*/ -#define US_MR_PAR_NONE (0x4 << 9) /**< (USART) No Parity*/ -#define US_MR_PAR_MULTI_DROP (0x6 << 9) /**< (USART) Multi-drop mode*/ -#define US_MR_NBSTOP (0x3 << 12) /**< \brief (US_MR) Number of Stop Bits */ -#define US_MR_NBSTOP_1_BIT (0x0 << 12) /**< (USART) 1 stop bit*/ -#define US_MR_NBSTOP_15_BIT (0x1 << 12) /**< (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits*/ -#define US_MR_NBSTOP_2_BIT (0x2 << 12) /**< (USART) 2 stop bits*/ -#define US_MR_CHMODE (0x3 << 14) /**< \brief (US_MR) Channel Mode */ -#define US_MR_CHMODE_NORMAL (0x0 << 14) /**< (USART) Normal Mode: The USART channel operates as an RX/TX USART.*/ -#define US_MR_CHMODE_AUTO (0x1 << 14) /**< (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin.*/ -#define US_MR_CHMODE_LOCAL (0x2 << 14) /**< (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.*/ -#define US_MR_CHMODE_REMOTE (0x3 << 14) /**< (USART) Remote Loopback: RXD pin is internally connected to TXD pin.*/ -#define US_MR_MSBF__CPOL (0x1 << 16) /**< \brief (US_MR) Bit Order or SPI Clock Polarity */ -#define US_MR_MODE9 (0x1 << 17) /**< \brief (US_MR) 9-bit Character Length */ -#define US_MR_CLKO (0x1 << 18) /**< \brief (US_MR) Clock Output Select */ -#define US_MR_OVER (0x1 << 19) /**< \brief (US_MR) Oversampling Mode */ -#define US_MR_INACK (0x1 << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ -#define US_MR_DSNACK (0x1 << 21) /**< \brief (US_MR) Disable Successive NACK */ -#define US_MR_VAR_SYNC (0x1 << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ -#define US_MR_INVDATA (0x1 << 23) /**< \brief (US_MR) INverted Data */ -#define US_MR_MAX_ITERATION (0x7 << 24) /**< \brief (US_MR) */ -#define US_MR_FILTER (0x1 << 28) /**< \brief (US_MR) Infrared Receive Line Filter */ -#define US_MR_MAN (0x1 << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ -#define US_MR_MODSYNC_ (0x1 << 30) /**< \brief (US_MR) */ -#define US_MR_ONEBIT (0x1 << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ -/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ -#define US_IER_RXRDY (0x1 << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ -#define US_IER_TXRDY (0x1 << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ -#define US_IER_RXBRK (0x1 << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ -#define US_IER_ENDRX (0x1 << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */ -#define US_IER_ENDTX (0x1 << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */ -#define US_IER_OVRE (0x1 << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ -#define US_IER_FRAME (0x1 << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ -#define US_IER_PARE (0x1 << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ -#define US_IER_TIMEOUT (0x1 << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ -#define US_IER_TXEMPTY (0x1 << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ -#define US_IER_ITER__UNRE (0x1 << 10) /**< \brief (US_IER) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IER_TXBUFE (0x1 << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */ -#define US_IER_RXBUFF (0x1 << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */ -#define US_IER_NACK (0x1 << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */ -#define US_IER_RIIC (0x1 << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */ -#define US_IER_DSRIC (0x1 << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */ -#define US_IER_DCDIC (0x1 << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */ -#define US_IER_CTSIC (0x1 << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ -#define US_IER_MANE (0x1 << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ -/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ -#define US_IDR_RXRDY (0x1 << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ -#define US_IDR_TXRDY (0x1 << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ -#define US_IDR_RXBRK (0x1 << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ -#define US_IDR_ENDRX (0x1 << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */ -#define US_IDR_ENDTX (0x1 << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */ -#define US_IDR_OVRE (0x1 << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */ -#define US_IDR_FRAME (0x1 << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ -#define US_IDR_PARE (0x1 << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ -#define US_IDR_TIMEOUT (0x1 << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ -#define US_IDR_TXEMPTY (0x1 << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ -#define US_IDR_ITER__UNRE (0x1 << 10) /**< \brief (US_IDR) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IDR_TXBUFE (0x1 << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */ -#define US_IDR_RXBUFF (0x1 << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */ -#define US_IDR_NACK (0x1 << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */ -#define US_IDR_RIIC (0x1 << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */ -#define US_IDR_DSRIC (0x1 << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */ -#define US_IDR_DCDIC (0x1 << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */ -#define US_IDR_CTSIC (0x1 << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ -#define US_IDR_MANE (0x1 << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ -/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ -#define US_IMR_RXRDY (0x1 << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ -#define US_IMR_TXRDY (0x1 << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ -#define US_IMR_RXBRK (0x1 << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ -#define US_IMR_ENDRX (0x1 << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */ -#define US_IMR_ENDTX (0x1 << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */ -#define US_IMR_OVRE (0x1 << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ -#define US_IMR_FRAME (0x1 << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ -#define US_IMR_PARE (0x1 << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ -#define US_IMR_TIMEOUT (0x1 << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ -#define US_IMR_TXEMPTY (0x1 << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ -#define US_IMR_ITER__UNRE (0x1 << 10) /**< \brief (US_IMR) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IMR_TXBUFE (0x1 << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */ -#define US_IMR_RXBUFF (0x1 << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */ -#define US_IMR_NACK (0x1 << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */ -#define US_IMR_RIIC (0x1 << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */ -#define US_IMR_DSRIC (0x1 << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */ -#define US_IMR_DCDIC (0x1 << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */ -#define US_IMR_CTSIC (0x1 << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ -#define US_IMR_MANE (0x1 << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ -/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ -#define US_CSR_RXRDY (0x1 << 0) /**< \brief (US_CSR) Receiver Ready */ -#define US_CSR_TXRDY (0x1 << 1) /**< \brief (US_CSR) Transmitter Ready */ -#define US_CSR_RXBRK (0x1 << 2) /**< \brief (US_CSR) Break Received/End of Break */ -#define US_CSR_ENDRX (0x1 << 3) /**< \brief (US_CSR) End of Receiver Transfer */ -#define US_CSR_ENDTX (0x1 << 4) /**< \brief (US_CSR) End of Transmitter Transfer */ -#define US_CSR_OVRE (0x1 << 5) /**< \brief (US_CSR) Overrun Error */ -#define US_CSR_FRAME (0x1 << 6) /**< \brief (US_CSR) Framing Error */ -#define US_CSR_PARE (0x1 << 7) /**< \brief (US_CSR) Parity Error */ -#define US_CSR_TIMEOUT (0x1 << 8) /**< \brief (US_CSR) Receiver Time-out */ -#define US_CSR_TXEMPTY (0x1 << 9) /**< \brief (US_CSR) Transmitter Empty */ -#define US_CSR_ITER__UNRE (0x1 << 10) /**< \brief (US_CSR) Max number of Repetitions Reached or SPI Underrun Error */ -#define US_CSR_TXBUFE (0x1 << 11) /**< \brief (US_CSR) Transmission Buffer Empty */ -#define US_CSR_RXBUFF (0x1 << 12) /**< \brief (US_CSR) Reception Buffer Full */ -#define US_CSR_NACK (0x1 << 13) /**< \brief (US_CSR) */ -#define US_CSR_RIIC (0x1 << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */ -#define US_CSR_DSRIC (0x1 << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */ -#define US_CSR_DCDIC (0x1 << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */ -#define US_CSR_CTSIC (0x1 << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */ -#define US_CSR_RI (0x1 << 20) /**< \brief (US_CSR) Image of RI Input */ -#define US_CSR_DSR (0x1 << 21) /**< \brief (US_CSR) Image of DSR Input */ -#define US_CSR_DCD (0x1 << 22) /**< \brief (US_CSR) Image of DCD Input */ -#define US_CSR_CTS (0x1 << 23) /**< \brief (US_CSR) Image of CTS Input */ -#define US_CSR_MANERR (0x1 << 24) /**< \brief (US_CSR) Manchester Error */ -/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */ -#define US_RHR_RXCHR (0x1ff << 0) /**< \brief (US_RHR) Received Character */ -#define US_RHR_RXSYNH (0x1 << 15) /**< \brief (US_RHR) Received Sync */ -/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */ -#define US_THR_TXCHR (0x1ff << 0) /**< \brief (US_THR) Character to be Transmitted */ -#define US_THR_TXSYNH (0x1 << 15) /**< \brief (US_THR) Sync Field to be transmitted */ -/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ -#define US_BRGR_CD (0xffff << 0) /**< \brief (US_BRGR) Clock Divider */ -#define US_BRGR_FP (0x7 << 16) /**< \brief (US_BRGR) Fractional Part */ -/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ -#define US_RTOR_TO (0xffff << 0) /**< \brief (US_RTOR) Time-out Value */ -/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ -#define US_TTGR_TG (0xff << 0) /**< \brief (US_TTGR) Timeguard Value */ -/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ -#define US_FIDI_FI_DI_RATIO (0x7ff << 0) /**< \brief (US_FIDI) FI Over DI Ratio Value */ -/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ -#define US_NER_NB_ERRORS (0xff << 0) /**< \brief (US_NER) Number of Errors */ -/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ -#define US_IF_IRDA_FILTER (0xff << 0) /**< \brief (US_IF) IrDA Filter */ -/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */ -#define US_MAN_TX_PL (0xf << 0) /**< \brief (US_MAN) Transmitter Preamble Length */ -#define US_MAN_TX_PP (0x3 << 8) /**< \brief (US_MAN) Transmitter Preamble Pattern */ -#define US_MAN_TX_MPOL (0x1 << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ -#define US_MAN_RX_PL (0xf << 16) /**< \brief (US_MAN) Receiver Preamble Length */ -#define US_MAN_RX_PP (0x3 << 24) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ -#define US_MAN_RX_MPOL (0x1 << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ -#define US_MAN_STUCKTO1 (0x1 << 29) /**< \brief (US_MAN) */ -#define US_MAN_DRIFT (0x1 << 30) /**< \brief (US_MAN) Drift compensation */ -/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */ -#define US_WPMR_WPEN (0x1 << 0) /**< \brief (US_WPMR) Write Protect Enable */ -#define US_WPMR_WPKEY (0xffffff << 8) /**< \brief (US_WPMR) Write Protect KEY */ -/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */ -#define US_WPSR_WPVS (0x1 << 0) /**< \brief (US_WPSR) Write Protect Violation Status */ -#define US_WPSR_WPVSRC (0xffff << 8) /**< \brief (US_WPSR) Write Protect Violation Source */ -/* -------- US_VERSION : (USART Offset: 0xFC) Version Register -------- */ -#define US_VERSION_VERSION (0xfff << 0) /**< \brief (US_VERSION) */ -#define US_VERSION_MFN (0x7 << 16) /**< \brief (US_VERSION) */ -/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */ -#define US_RPR_RXPTR (0xffffffff << 0) /**< \brief (US_RPR) Receive Pointer Register */ -/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */ -#define US_RCR_RXCTR (0xffff << 0) /**< \brief (US_RCR) Receive Counter Register */ -/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */ -#define US_TPR_TXPTR (0xffffffff << 0) /**< \brief (US_TPR) Transmit Counter Register */ -/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */ -#define US_TCR_TXCTR (0xffff << 0) /**< \brief (US_TCR) Transmit Counter Register */ -/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */ -#define US_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (US_RNPR) Receive Next Pointer */ -/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */ -#define US_RNCR_RXNCTR (0xffff << 0) /**< \brief (US_RNCR) Receive Next Counter */ -/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */ -#define US_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (US_TNPR) Transmit Next Pointer */ -/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */ -#define US_TNCR_TXNCTR (0xffff << 0) /**< \brief (US_TNCR) Transmit Counter Next */ -/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */ -#define US_PTCR_RXTEN (0x1 << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */ -#define US_PTCR_RXTDIS (0x1 << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */ -#define US_PTCR_TXTEN (0x1 << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */ -#define US_PTCR_TXTDIS (0x1 << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */ -/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */ -#define US_PTSR_RXTEN (0x1 << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */ -#define US_PTSR_TXTEN (0x1 << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Watchdog Timer */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_WDT Watchdog Timer */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Wdt hardware registers */ -typedef struct { - WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ - RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ - RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ -} Wdt; -#endif /* __ASSEMBLY__ */ -/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ -#define WDT_CR_WDRSTT (0x1 << 0) /**< \brief (WDT_CR) Watchdog Restart */ -#define WDT_CR_KEY (0xff << 24) /**< \brief (WDT_CR) Password */ -/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ -#define WDT_MR_WDV (0xfff << 0) /**< \brief (WDT_MR) Watchdog Counter Value */ -#define WDT_MR_WDFIEN (0x1 << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ -#define WDT_MR_WDRSTEN (0x1 << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ -#define WDT_MR_WDRPROC (0x1 << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */ -#define WDT_MR_WDDIS (0x1 << 15) /**< \brief (WDT_MR) Watchdog Disable */ -#define WDT_MR_WDD (0xfff << 16) /**< \brief (WDT_MR) Watchdog Delta Value */ -#define WDT_MR_WDDBGHLT (0x1 << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ -#define WDT_MR_WDIDLEHLT (0x1 << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ -/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ -#define WDT_SR_WDUNF (0x1 << 0) /**< \brief (WDT_SR) Watchdog Underflow */ -#define WDT_SR_WDERR (0x1 << 1) /**< \brief (WDT_SR) Watchdog Error */ - -/*@}*/ - -/*@}*/ - -/* ***************************************************************************** */ -/* REGISTER ACCESS DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_reg Registers Access Definitions */ -/*@{*/ - -/* ========== Register definition for HSMCI peripheral ========== */ -#define REG_HSMCI_CR REG_ACCESS(WoReg, 0x40000000U) /**< \brief (HSMCI) Control Register */ -#define REG_HSMCI_MR REG_ACCESS(RwReg, 0x40000004U) /**< \brief (HSMCI) Mode Register */ -#define REG_HSMCI_DTOR REG_ACCESS(RwReg, 0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ -#define REG_HSMCI_SDCR REG_ACCESS(RwReg, 0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ -#define REG_HSMCI_ARGR REG_ACCESS(RwReg, 0x40000010U) /**< \brief (HSMCI) Argument Register */ -#define REG_HSMCI_CMDR REG_ACCESS(WoReg, 0x40000014U) /**< \brief (HSMCI) Command Register */ -#define REG_HSMCI_BLKR REG_ACCESS(RwReg, 0x40000018U) /**< \brief (HSMCI) Block Register */ -#define REG_HSMCI_CSTOR REG_ACCESS(RwReg, 0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ -#define REG_HSMCI_RSPR REG_ACCESS(RoReg, 0x40000020U) /**< \brief (HSMCI) Response Register */ -#define REG_HSMCI_RDR REG_ACCESS(RoReg, 0x40000030U) /**< \brief (HSMCI) Receive Data Register */ -#define REG_HSMCI_TDR REG_ACCESS(WoReg, 0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ -#define REG_HSMCI_SR REG_ACCESS(RoReg, 0x40000040U) /**< \brief (HSMCI) Status Register */ -#define REG_HSMCI_IER REG_ACCESS(WoReg, 0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ -#define REG_HSMCI_IDR REG_ACCESS(WoReg, 0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ -#define REG_HSMCI_IMR REG_ACCESS(RoReg, 0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ -#define REG_HSMCI_CFG REG_ACCESS(RwReg, 0x40000054U) /**< \brief (HSMCI) Configuration Register */ -#define REG_HSMCI_WPMR REG_ACCESS(RwReg, 0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ -#define REG_HSMCI_WPSR REG_ACCESS(RoReg, 0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ -#define REG_HSMCI_RPR REG_ACCESS(RwReg, 0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */ -#define REG_HSMCI_RCR REG_ACCESS(RwReg, 0x40000104U) /**< \brief (HSMCI) Receive Counter Register */ -#define REG_HSMCI_TPR REG_ACCESS(RwReg, 0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */ -#define REG_HSMCI_TCR REG_ACCESS(RwReg, 0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */ -#define REG_HSMCI_RNPR REG_ACCESS(RwReg, 0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */ -#define REG_HSMCI_RNCR REG_ACCESS(RwReg, 0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */ -#define REG_HSMCI_TNPR REG_ACCESS(RwReg, 0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */ -#define REG_HSMCI_TNCR REG_ACCESS(RwReg, 0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */ -#define REG_HSMCI_PTCR REG_ACCESS(WoReg, 0x40000120U) /**< \brief (HSMCI) Transfer Control Register */ -#define REG_HSMCI_PTSR REG_ACCESS(RoReg, 0x40000124U) /**< \brief (HSMCI) Transfer Status Register */ -/* ========== Register definition for SSC peripheral ========== */ -#define REG_SSC_CR REG_ACCESS(WoReg, 0x40004000U) /**< \brief (SSC) Control Register */ -#define REG_SSC_CMR REG_ACCESS(RwReg, 0x40004004U) /**< \brief (SSC) Clock Mode Register */ -#define REG_SSC_RCMR REG_ACCESS(RwReg, 0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ -#define REG_SSC_RFMR REG_ACCESS(RwReg, 0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ -#define REG_SSC_TCMR REG_ACCESS(RwReg, 0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ -#define REG_SSC_TFMR REG_ACCESS(RwReg, 0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ -#define REG_SSC_RHR REG_ACCESS(RoReg, 0x40004020U) /**< \brief (SSC) Receive Holding Register */ -#define REG_SSC_THR REG_ACCESS(WoReg, 0x40004024U) /**< \brief (SSC) Transmit Holding Register */ -#define REG_SSC_RSHR REG_ACCESS(RoReg, 0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ -#define REG_SSC_TSHR REG_ACCESS(RwReg, 0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ -#define REG_SSC_RC0R REG_ACCESS(RwReg, 0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ -#define REG_SSC_RC1R REG_ACCESS(RwReg, 0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ -#define REG_SSC_SR REG_ACCESS(RoReg, 0x40004040U) /**< \brief (SSC) Status Register */ -#define REG_SSC_IER REG_ACCESS(WoReg, 0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ -#define REG_SSC_IDR REG_ACCESS(WoReg, 0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ -#define REG_SSC_IMR REG_ACCESS(RoReg, 0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ -#define REG_SSC_WPMR REG_ACCESS(RwReg, 0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */ -#define REG_SSC_WPSR REG_ACCESS(RoReg, 0x400040E8U) /**< \brief (SSC) Write Protect Status Register */ -#define REG_SSC_RPR REG_ACCESS(RwReg, 0x40004100U) /**< \brief (SSC) Receive Pointer Register */ -#define REG_SSC_RCR REG_ACCESS(RwReg, 0x40004104U) /**< \brief (SSC) Receive Counter Register */ -#define REG_SSC_TPR REG_ACCESS(RwReg, 0x40004108U) /**< \brief (SSC) Transmit Pointer Register */ -#define REG_SSC_TCR REG_ACCESS(RwReg, 0x4000410CU) /**< \brief (SSC) Transmit Counter Register */ -#define REG_SSC_RNPR REG_ACCESS(RwReg, 0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */ -#define REG_SSC_RNCR REG_ACCESS(RwReg, 0x40004114U) /**< \brief (SSC) Receive Next Counter Register */ -#define REG_SSC_TNPR REG_ACCESS(RwReg, 0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */ -#define REG_SSC_TNCR REG_ACCESS(RwReg, 0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */ -#define REG_SSC_PTCR REG_ACCESS(WoReg, 0x40004120U) /**< \brief (SSC) Transfer Control Register */ -#define REG_SSC_PTSR REG_ACCESS(RoReg, 0x40004124U) /**< \brief (SSC) Transfer Status Register */ -/* ========== Register definition for SPI peripheral ========== */ -#define REG_SPI_CR REG_ACCESS(WoReg, 0x40008000U) /**< \brief (SPI) Control Register */ -#define REG_SPI_MR REG_ACCESS(RwReg, 0x40008004U) /**< \brief (SPI) Mode Register */ -#define REG_SPI_RDR REG_ACCESS(RoReg, 0x40008008U) /**< \brief (SPI) Receive Data Register */ -#define REG_SPI_TDR REG_ACCESS(WoReg, 0x4000800CU) /**< \brief (SPI) Transmit Data Register */ -#define REG_SPI_SR REG_ACCESS(RoReg, 0x40008010U) /**< \brief (SPI) Status Register */ -#define REG_SPI_IER REG_ACCESS(WoReg, 0x40008014U) /**< \brief (SPI) Interrupt Enable Register */ -#define REG_SPI_IDR REG_ACCESS(WoReg, 0x40008018U) /**< \brief (SPI) Interrupt Disable Register */ -#define REG_SPI_IMR REG_ACCESS(RoReg, 0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */ -#define REG_SPI_CSR REG_ACCESS(RwReg, 0x40008030U) /**< \brief (SPI) Chip Select Register */ -#define REG_SPI_WPMR REG_ACCESS(RwReg, 0x400080E4U) /**< \brief (SPI) Write Protection Control Register */ -#define REG_SPI_WPSR REG_ACCESS(RoReg, 0x400080E8U) /**< \brief (SPI) Write Protection Status Register */ -#define REG_SPI_RPR REG_ACCESS(RwReg, 0x40008100U) /**< \brief (SPI) Receive Pointer Register */ -#define REG_SPI_RCR REG_ACCESS(RwReg, 0x40008104U) /**< \brief (SPI) Receive Counter Register */ -#define REG_SPI_TPR REG_ACCESS(RwReg, 0x40008108U) /**< \brief (SPI) Transmit Pointer Register */ -#define REG_SPI_TCR REG_ACCESS(RwReg, 0x4000810CU) /**< \brief (SPI) Transmit Counter Register */ -#define REG_SPI_RNPR REG_ACCESS(RwReg, 0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */ -#define REG_SPI_RNCR REG_ACCESS(RwReg, 0x40008114U) /**< \brief (SPI) Receive Next Counter Register */ -#define REG_SPI_TNPR REG_ACCESS(RwReg, 0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */ -#define REG_SPI_TNCR REG_ACCESS(RwReg, 0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */ -#define REG_SPI_PTCR REG_ACCESS(WoReg, 0x40008120U) /**< \brief (SPI) Transfer Control Register */ -#define REG_SPI_PTSR REG_ACCESS(RoReg, 0x40008124U) /**< \brief (SPI) Transfer Status Register */ -/* ========== Register definition for TC0 peripheral ========== */ -#define REG_TC0_CCR0 REG_ACCESS(WoReg, 0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ -#define REG_TC0_CMR0 REG_ACCESS(RwReg, 0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ -#define REG_TC0_CV0 REG_ACCESS(RoReg, 0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */ -#define REG_TC0_RA0 REG_ACCESS(RwReg, 0x40010014U) /**< \brief (TC0) Register A (channel = 0) */ -#define REG_TC0_RB0 REG_ACCESS(RwReg, 0x40010018U) /**< \brief (TC0) Register B (channel = 0) */ -#define REG_TC0_RC0 REG_ACCESS(RwReg, 0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */ -#define REG_TC0_SR0 REG_ACCESS(RoReg, 0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */ -#define REG_TC0_IER0 REG_ACCESS(WoReg, 0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ -#define REG_TC0_IDR0 REG_ACCESS(WoReg, 0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ -#define REG_TC0_IMR0 REG_ACCESS(RoReg, 0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ -#define REG_TC0_CCR1 REG_ACCESS(WoReg, 0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ -#define REG_TC0_CMR1 REG_ACCESS(RwReg, 0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ -#define REG_TC0_CV1 REG_ACCESS(RoReg, 0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */ -#define REG_TC0_RA1 REG_ACCESS(RwReg, 0x40010054U) /**< \brief (TC0) Register A (channel = 1) */ -#define REG_TC0_RB1 REG_ACCESS(RwReg, 0x40010058U) /**< \brief (TC0) Register B (channel = 1) */ -#define REG_TC0_RC1 REG_ACCESS(RwReg, 0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */ -#define REG_TC0_SR1 REG_ACCESS(RoReg, 0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */ -#define REG_TC0_IER1 REG_ACCESS(WoReg, 0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ -#define REG_TC0_IDR1 REG_ACCESS(WoReg, 0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ -#define REG_TC0_IMR1 REG_ACCESS(RoReg, 0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ -#define REG_TC0_CCR2 REG_ACCESS(WoReg, 0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ -#define REG_TC0_CMR2 REG_ACCESS(RwReg, 0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ -#define REG_TC0_CV2 REG_ACCESS(RoReg, 0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */ -#define REG_TC0_RA2 REG_ACCESS(RwReg, 0x40010094U) /**< \brief (TC0) Register A (channel = 2) */ -#define REG_TC0_RB2 REG_ACCESS(RwReg, 0x40010098U) /**< \brief (TC0) Register B (channel = 2) */ -#define REG_TC0_RC2 REG_ACCESS(RwReg, 0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */ -#define REG_TC0_SR2 REG_ACCESS(RoReg, 0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */ -#define REG_TC0_IER2 REG_ACCESS(WoReg, 0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ -#define REG_TC0_IDR2 REG_ACCESS(WoReg, 0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ -#define REG_TC0_IMR2 REG_ACCESS(RoReg, 0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ -#define REG_TC0_BCR REG_ACCESS(WoReg, 0x400100C0U) /**< \brief (TC0) Block Control Register */ -#define REG_TC0_BMR REG_ACCESS(RwReg, 0x400100C4U) /**< \brief (TC0) Block Mode Register */ -#define REG_TC0_QIER REG_ACCESS(WoReg, 0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ -#define REG_TC0_QIDR REG_ACCESS(WoReg, 0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ -#define REG_TC0_QIMR REG_ACCESS(RoReg, 0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ -#define REG_TC0_QISR REG_ACCESS(RoReg, 0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ -#define REG_TC0_FMR REG_ACCESS(RwReg, 0x400100D8U) /**< \brief (TC0) Fault Mode Register */ -#define REG_TC0_WPMR REG_ACCESS(RwReg, 0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */ -#define REG_TC0_VER REG_ACCESS(RoReg, 0x400100FCU) /**< \brief (TC0) Version Register */ -/* ========== Register definition for TC1 peripheral ========== */ -#define REG_TC1_CCR0 REG_ACCESS(WoReg, 0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ -#define REG_TC1_CMR0 REG_ACCESS(RwReg, 0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ -#define REG_TC1_CV0 REG_ACCESS(RoReg, 0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */ -#define REG_TC1_RA0 REG_ACCESS(RwReg, 0x40014014U) /**< \brief (TC1) Register A (channel = 0) */ -#define REG_TC1_RB0 REG_ACCESS(RwReg, 0x40014018U) /**< \brief (TC1) Register B (channel = 0) */ -#define REG_TC1_RC0 REG_ACCESS(RwReg, 0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */ -#define REG_TC1_SR0 REG_ACCESS(RoReg, 0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */ -#define REG_TC1_IER0 REG_ACCESS(WoReg, 0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ -#define REG_TC1_IDR0 REG_ACCESS(WoReg, 0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ -#define REG_TC1_IMR0 REG_ACCESS(RoReg, 0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ -#define REG_TC1_CCR1 REG_ACCESS(WoReg, 0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ -#define REG_TC1_CMR1 REG_ACCESS(RwReg, 0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ -#define REG_TC1_CV1 REG_ACCESS(RoReg, 0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */ -#define REG_TC1_RA1 REG_ACCESS(RwReg, 0x40014054U) /**< \brief (TC1) Register A (channel = 1) */ -#define REG_TC1_RB1 REG_ACCESS(RwReg, 0x40014058U) /**< \brief (TC1) Register B (channel = 1) */ -#define REG_TC1_RC1 REG_ACCESS(RwReg, 0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */ -#define REG_TC1_SR1 REG_ACCESS(RoReg, 0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */ -#define REG_TC1_IER1 REG_ACCESS(WoReg, 0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ -#define REG_TC1_IDR1 REG_ACCESS(WoReg, 0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ -#define REG_TC1_IMR1 REG_ACCESS(RoReg, 0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ -#define REG_TC1_CCR2 REG_ACCESS(WoReg, 0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ -#define REG_TC1_CMR2 REG_ACCESS(RwReg, 0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ -#define REG_TC1_CV2 REG_ACCESS(RoReg, 0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */ -#define REG_TC1_RA2 REG_ACCESS(RwReg, 0x40014094U) /**< \brief (TC1) Register A (channel = 2) */ -#define REG_TC1_RB2 REG_ACCESS(RwReg, 0x40014098U) /**< \brief (TC1) Register B (channel = 2) */ -#define REG_TC1_RC2 REG_ACCESS(RwReg, 0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */ -#define REG_TC1_SR2 REG_ACCESS(RoReg, 0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */ -#define REG_TC1_IER2 REG_ACCESS(WoReg, 0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ -#define REG_TC1_IDR2 REG_ACCESS(WoReg, 0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ -#define REG_TC1_IMR2 REG_ACCESS(RoReg, 0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ -#define REG_TC1_BCR REG_ACCESS(WoReg, 0x400140C0U) /**< \brief (TC1) Block Control Register */ -#define REG_TC1_BMR REG_ACCESS(RwReg, 0x400140C4U) /**< \brief (TC1) Block Mode Register */ -#define REG_TC1_QIER REG_ACCESS(WoReg, 0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ -#define REG_TC1_QIDR REG_ACCESS(WoReg, 0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ -#define REG_TC1_QIMR REG_ACCESS(RoReg, 0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ -#define REG_TC1_QISR REG_ACCESS(RoReg, 0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ -#define REG_TC1_FMR REG_ACCESS(RwReg, 0x400140D8U) /**< \brief (TC1) Fault Mode Register */ -#define REG_TC1_WPMR REG_ACCESS(RwReg, 0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */ -#define REG_TC1_VER REG_ACCESS(RoReg, 0x400140FCU) /**< \brief (TC1) Version Register */ -/* ========== Register definition for TWI0 peripheral ========== */ -#define REG_TWI0_CR REG_ACCESS(WoReg, 0x40018000U) /**< \brief (TWI0) Control Register */ -#define REG_TWI0_MMR REG_ACCESS(RwReg, 0x40018004U) /**< \brief (TWI0) Master Mode Register */ -#define REG_TWI0_SMR REG_ACCESS(RwReg, 0x40018008U) /**< \brief (TWI0) Slave Mode Register */ -#define REG_TWI0_IADR REG_ACCESS(RwReg, 0x4001800CU) /**< \brief (TWI0) Internal Address Register */ -#define REG_TWI0_CWGR REG_ACCESS(RwReg, 0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */ -#define REG_TWI0_SR REG_ACCESS(RoReg, 0x40018020U) /**< \brief (TWI0) Status Register */ -#define REG_TWI0_IER REG_ACCESS(WoReg, 0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */ -#define REG_TWI0_IDR REG_ACCESS(WoReg, 0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */ -#define REG_TWI0_IMR REG_ACCESS(RoReg, 0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */ -#define REG_TWI0_RHR REG_ACCESS(RoReg, 0x40018030U) /**< \brief (TWI0) Receive Holding Register */ -#define REG_TWI0_THR REG_ACCESS(WoReg, 0x40018034U) /**< \brief (TWI0) Transmit Holding Register */ -#define REG_TWI0_RPR REG_ACCESS(RwReg, 0x40018100U) /**< \brief (TWI0) Receive Pointer Register */ -#define REG_TWI0_RCR REG_ACCESS(RwReg, 0x40018104U) /**< \brief (TWI0) Receive Counter Register */ -#define REG_TWI0_TPR REG_ACCESS(RwReg, 0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */ -#define REG_TWI0_TCR REG_ACCESS(RwReg, 0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */ -#define REG_TWI0_RNPR REG_ACCESS(RwReg, 0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */ -#define REG_TWI0_RNCR REG_ACCESS(RwReg, 0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */ -#define REG_TWI0_TNPR REG_ACCESS(RwReg, 0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */ -#define REG_TWI0_TNCR REG_ACCESS(RwReg, 0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */ -#define REG_TWI0_PTCR REG_ACCESS(WoReg, 0x40018120U) /**< \brief (TWI0) Transfer Control Register */ -#define REG_TWI0_PTSR REG_ACCESS(RoReg, 0x40018124U) /**< \brief (TWI0) Transfer Status Register */ -/* ========== Register definition for TWI1 peripheral ========== */ -#define REG_TWI1_CR REG_ACCESS(WoReg, 0x4001C000U) /**< \brief (TWI1) Control Register */ -#define REG_TWI1_MMR REG_ACCESS(RwReg, 0x4001C004U) /**< \brief (TWI1) Master Mode Register */ -#define REG_TWI1_SMR REG_ACCESS(RwReg, 0x4001C008U) /**< \brief (TWI1) Slave Mode Register */ -#define REG_TWI1_IADR REG_ACCESS(RwReg, 0x4001C00CU) /**< \brief (TWI1) Internal Address Register */ -#define REG_TWI1_CWGR REG_ACCESS(RwReg, 0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */ -#define REG_TWI1_SR REG_ACCESS(RoReg, 0x4001C020U) /**< \brief (TWI1) Status Register */ -#define REG_TWI1_IER REG_ACCESS(WoReg, 0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */ -#define REG_TWI1_IDR REG_ACCESS(WoReg, 0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */ -#define REG_TWI1_IMR REG_ACCESS(RoReg, 0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */ -#define REG_TWI1_RHR REG_ACCESS(RoReg, 0x4001C030U) /**< \brief (TWI1) Receive Holding Register */ -#define REG_TWI1_THR REG_ACCESS(WoReg, 0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */ -#define REG_TWI1_RPR REG_ACCESS(RwReg, 0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */ -#define REG_TWI1_RCR REG_ACCESS(RwReg, 0x4001C104U) /**< \brief (TWI1) Receive Counter Register */ -#define REG_TWI1_TPR REG_ACCESS(RwReg, 0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */ -#define REG_TWI1_TCR REG_ACCESS(RwReg, 0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */ -#define REG_TWI1_RNPR REG_ACCESS(RwReg, 0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */ -#define REG_TWI1_RNCR REG_ACCESS(RwReg, 0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */ -#define REG_TWI1_TNPR REG_ACCESS(RwReg, 0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */ -#define REG_TWI1_TNCR REG_ACCESS(RwReg, 0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */ -#define REG_TWI1_PTCR REG_ACCESS(WoReg, 0x4001C120U) /**< \brief (TWI1) Transfer Control Register */ -#define REG_TWI1_PTSR REG_ACCESS(RoReg, 0x4001C124U) /**< \brief (TWI1) Transfer Status Register */ -/* ========== Register definition for PWM peripheral ========== */ -#define REG_PWM_CLK REG_ACCESS(RwReg, 0x40020000U) /**< \brief (PWM) PWM Clock Register */ -#define REG_PWM_ENA REG_ACCESS(WoReg, 0x40020004U) /**< \brief (PWM) PWM Enable Register */ -#define REG_PWM_DIS REG_ACCESS(WoReg, 0x40020008U) /**< \brief (PWM) PWM Disable Register */ -#define REG_PWM_SR REG_ACCESS(RoReg, 0x4002000CU) /**< \brief (PWM) PWM Status Register */ -#define REG_PWM_IER1 REG_ACCESS(WoReg, 0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ -#define REG_PWM_IDR1 REG_ACCESS(WoReg, 0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ -#define REG_PWM_IMR1 REG_ACCESS(RoReg, 0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ -#define REG_PWM_ISR1 REG_ACCESS(RoReg, 0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ -#define REG_PWM_SCM REG_ACCESS(RwReg, 0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ -#define REG_PWM_SCUC REG_ACCESS(RwReg, 0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ -#define REG_PWM_SCUP REG_ACCESS(RwReg, 0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ -#define REG_PWM_SCUPUPD REG_ACCESS(WoReg, 0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ -#define REG_PWM_IER2 REG_ACCESS(WoReg, 0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ -#define REG_PWM_IDR2 REG_ACCESS(WoReg, 0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ -#define REG_PWM_IMR2 REG_ACCESS(RoReg, 0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ -#define REG_PWM_ISR2 REG_ACCESS(RoReg, 0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ -#define REG_PWM_OOV REG_ACCESS(RwReg, 0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */ -#define REG_PWM_OS REG_ACCESS(RwReg, 0x40020048U) /**< \brief (PWM) PWM Output Selection Register */ -#define REG_PWM_OSS REG_ACCESS(WoReg, 0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */ -#define REG_PWM_OSC REG_ACCESS(WoReg, 0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */ -#define REG_PWM_OSSUPD REG_ACCESS(WoReg, 0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ -#define REG_PWM_OSCUPD REG_ACCESS(WoReg, 0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ -#define REG_PWM_FMR REG_ACCESS(RwReg, 0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */ -#define REG_PWM_FSR REG_ACCESS(RoReg, 0x40020060U) /**< \brief (PWM) PWM Fault Status Register */ -#define REG_PWM_FCR REG_ACCESS(WoReg, 0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */ -#define REG_PWM_FPV REG_ACCESS(RwReg, 0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */ -#define REG_PWM_FPE REG_ACCESS(RwReg, 0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ -#define REG_PWM_ELxMR REG_ACCESS(RwReg, 0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ -#define REG_PWM_SMMR REG_ACCESS(RwReg, 0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */ -#define REG_PWM_WPCR REG_ACCESS(WoReg, 0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */ -#define REG_PWM_WPSR REG_ACCESS(RoReg, 0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */ -#define REG_PWM_RPR REG_ACCESS(RwReg, 0x40020100U) /**< \brief (PWM) Receive Pointer Register */ -#define REG_PWM_RCR REG_ACCESS(RwReg, 0x40020104U) /**< \brief (PWM) Receive Counter Register */ -#define REG_PWM_TPR REG_ACCESS(RwReg, 0x40020108U) /**< \brief (PWM) Transmit Pointer Register */ -#define REG_PWM_TCR REG_ACCESS(RwReg, 0x4002010CU) /**< \brief (PWM) Transmit Counter Register */ -#define REG_PWM_RNPR REG_ACCESS(RwReg, 0x40020110U) /**< \brief (PWM) Receive Next Pointer Register */ -#define REG_PWM_RNCR REG_ACCESS(RwReg, 0x40020114U) /**< \brief (PWM) Receive Next Counter Register */ -#define REG_PWM_TNPR REG_ACCESS(RwReg, 0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */ -#define REG_PWM_TNCR REG_ACCESS(RwReg, 0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */ -#define REG_PWM_PTCR REG_ACCESS(WoReg, 0x40020120U) /**< \brief (PWM) Transfer Control Register */ -#define REG_PWM_PTSR REG_ACCESS(RoReg, 0x40020124U) /**< \brief (PWM) Transfer Status Register */ -#define REG_PWM_CMP0V REG_ACCESS(RwReg, 0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ -#define REG_PWM_CMP0VUPD REG_ACCESS(WoReg, 0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ -#define REG_PWM_CMP0M REG_ACCESS(RwReg, 0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ -#define REG_PWM_CMP0MUPD REG_ACCESS(WoReg, 0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ -#define REG_PWM_CMP1V REG_ACCESS(RwReg, 0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ -#define REG_PWM_CMP1VUPD REG_ACCESS(WoReg, 0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ -#define REG_PWM_CMP1M REG_ACCESS(RwReg, 0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ -#define REG_PWM_CMP1MUPD REG_ACCESS(WoReg, 0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ -#define REG_PWM_CMP2V REG_ACCESS(RwReg, 0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ -#define REG_PWM_CMP2VUPD REG_ACCESS(WoReg, 0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ -#define REG_PWM_CMP2M REG_ACCESS(RwReg, 0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ -#define REG_PWM_CMP2MUPD REG_ACCESS(WoReg, 0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ -#define REG_PWM_CMP3V REG_ACCESS(RwReg, 0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ -#define REG_PWM_CMP3VUPD REG_ACCESS(WoReg, 0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ -#define REG_PWM_CMP3M REG_ACCESS(RwReg, 0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ -#define REG_PWM_CMP3MUPD REG_ACCESS(WoReg, 0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ -#define REG_PWM_CMP4V REG_ACCESS(RwReg, 0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ -#define REG_PWM_CMP4VUPD REG_ACCESS(WoReg, 0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ -#define REG_PWM_CMP4M REG_ACCESS(RwReg, 0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ -#define REG_PWM_CMP4MUPD REG_ACCESS(WoReg, 0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ -#define REG_PWM_CMP5V REG_ACCESS(RwReg, 0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ -#define REG_PWM_CMP5VUPD REG_ACCESS(WoReg, 0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ -#define REG_PWM_CMP5M REG_ACCESS(RwReg, 0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ -#define REG_PWM_CMP5MUPD REG_ACCESS(WoReg, 0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ -#define REG_PWM_CMP6V REG_ACCESS(RwReg, 0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ -#define REG_PWM_CMP6VUPD REG_ACCESS(WoReg, 0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ -#define REG_PWM_CMP6M REG_ACCESS(RwReg, 0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ -#define REG_PWM_CMP6MUPD REG_ACCESS(WoReg, 0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ -#define REG_PWM_CMP7V REG_ACCESS(RwReg, 0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ -#define REG_PWM_CMP7VUPD REG_ACCESS(WoReg, 0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ -#define REG_PWM_CMP7M REG_ACCESS(RwReg, 0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ -#define REG_PWM_CMP7MUPD REG_ACCESS(WoReg, 0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ -#define REG_PWM_CMR0 REG_ACCESS(RwReg, 0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ -#define REG_PWM_CDTY0 REG_ACCESS(RwReg, 0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ -#define REG_PWM_CDTYUPD0 REG_ACCESS(WoReg, 0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ -#define REG_PWM_CPRD0 REG_ACCESS(RwReg, 0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ -#define REG_PWM_CPRDUPD0 REG_ACCESS(WoReg, 0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ -#define REG_PWM_CCNT0 REG_ACCESS(RoReg, 0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ -#define REG_PWM_DT0 REG_ACCESS(RwReg, 0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ -#define REG_PWM_DTUPD0 REG_ACCESS(WoReg, 0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ -#define REG_PWM_CMR1 REG_ACCESS(RwReg, 0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ -#define REG_PWM_CDTY1 REG_ACCESS(RwReg, 0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ -#define REG_PWM_CDTYUPD1 REG_ACCESS(WoReg, 0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ -#define REG_PWM_CPRD1 REG_ACCESS(RwReg, 0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ -#define REG_PWM_CPRDUPD1 REG_ACCESS(WoReg, 0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ -#define REG_PWM_CCNT1 REG_ACCESS(RoReg, 0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ -#define REG_PWM_DT1 REG_ACCESS(RwReg, 0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ -#define REG_PWM_DTUPD1 REG_ACCESS(WoReg, 0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ -#define REG_PWM_CMR2 REG_ACCESS(RwReg, 0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ -#define REG_PWM_CDTY2 REG_ACCESS(RwReg, 0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ -#define REG_PWM_CDTYUPD2 REG_ACCESS(WoReg, 0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ -#define REG_PWM_CPRD2 REG_ACCESS(RwReg, 0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ -#define REG_PWM_CPRDUPD2 REG_ACCESS(WoReg, 0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ -#define REG_PWM_CCNT2 REG_ACCESS(RoReg, 0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ -#define REG_PWM_DT2 REG_ACCESS(RwReg, 0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ -#define REG_PWM_DTUPD2 REG_ACCESS(WoReg, 0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ -#define REG_PWM_CMR3 REG_ACCESS(RwReg, 0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ -#define REG_PWM_CDTY3 REG_ACCESS(RwReg, 0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ -#define REG_PWM_CDTYUPD3 REG_ACCESS(WoReg, 0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ -#define REG_PWM_CPRD3 REG_ACCESS(RwReg, 0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ -#define REG_PWM_CPRDUPD3 REG_ACCESS(WoReg, 0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ -#define REG_PWM_CCNT3 REG_ACCESS(RoReg, 0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ -#define REG_PWM_DT3 REG_ACCESS(RwReg, 0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ -#define REG_PWM_DTUPD3 REG_ACCESS(WoReg, 0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ -/* ========== Register definition for USART0 peripheral ========== */ -#define REG_USART0_CR REG_ACCESS(WoReg, 0x40024000U) /**< \brief (USART0) Control Register */ -#define REG_USART0_MR REG_ACCESS(RwReg, 0x40024004U) /**< \brief (USART0) Mode Register */ -#define REG_USART0_IER REG_ACCESS(WoReg, 0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ -#define REG_USART0_IDR REG_ACCESS(WoReg, 0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ -#define REG_USART0_IMR REG_ACCESS(RoReg, 0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ -#define REG_USART0_CSR REG_ACCESS(RoReg, 0x40024014U) /**< \brief (USART0) Channel Status Register */ -#define REG_USART0_RHR REG_ACCESS(RoReg, 0x40024018U) /**< \brief (USART0) Receiver Holding Register */ -#define REG_USART0_THR REG_ACCESS(WoReg, 0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */ -#define REG_USART0_BRGR REG_ACCESS(RwReg, 0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ -#define REG_USART0_RTOR REG_ACCESS(RwReg, 0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ -#define REG_USART0_TTGR REG_ACCESS(RwReg, 0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ -#define REG_USART0_FIDI REG_ACCESS(RwReg, 0x40024040U) /**< \brief (USART0) FI DI Ratio Register */ -#define REG_USART0_NER REG_ACCESS(RoReg, 0x40024044U) /**< \brief (USART0) Number of Errors Register */ -#define REG_USART0_IF REG_ACCESS(RwReg, 0x4002404CU) /**< \brief (USART0) IrDA Filter Register */ -#define REG_USART0_MAN REG_ACCESS(RwReg, 0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ -#define REG_USART0_WPMR REG_ACCESS(RwReg, 0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */ -#define REG_USART0_WPSR REG_ACCESS(RoReg, 0x400240E8U) /**< \brief (USART0) Write Protect Status Register */ -#define REG_USART0_VERSION REG_ACCESS(RoReg, 0x400240FCU) /**< \brief (USART0) Version Register */ -#define REG_USART0_RPR REG_ACCESS(RwReg, 0x40024100U) /**< \brief (USART0) Receive Pointer Register */ -#define REG_USART0_RCR REG_ACCESS(RwReg, 0x40024104U) /**< \brief (USART0) Receive Counter Register */ -#define REG_USART0_TPR REG_ACCESS(RwReg, 0x40024108U) /**< \brief (USART0) Transmit Pointer Register */ -#define REG_USART0_TCR REG_ACCESS(RwReg, 0x4002410CU) /**< \brief (USART0) Transmit Counter Register */ -#define REG_USART0_RNPR REG_ACCESS(RwReg, 0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */ -#define REG_USART0_RNCR REG_ACCESS(RwReg, 0x40024114U) /**< \brief (USART0) Receive Next Counter Register */ -#define REG_USART0_TNPR REG_ACCESS(RwReg, 0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */ -#define REG_USART0_TNCR REG_ACCESS(RwReg, 0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */ -#define REG_USART0_PTCR REG_ACCESS(WoReg, 0x40024120U) /**< \brief (USART0) Transfer Control Register */ -#define REG_USART0_PTSR REG_ACCESS(RoReg, 0x40024124U) /**< \brief (USART0) Transfer Status Register */ -/* ========== Register definition for USART1 peripheral ========== */ -#define REG_USART1_CR REG_ACCESS(WoReg, 0x40028000U) /**< \brief (USART1) Control Register */ -#define REG_USART1_MR REG_ACCESS(RwReg, 0x40028004U) /**< \brief (USART1) Mode Register */ -#define REG_USART1_IER REG_ACCESS(WoReg, 0x40028008U) /**< \brief (USART1) Interrupt Enable Register */ -#define REG_USART1_IDR REG_ACCESS(WoReg, 0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */ -#define REG_USART1_IMR REG_ACCESS(RoReg, 0x40028010U) /**< \brief (USART1) Interrupt Mask Register */ -#define REG_USART1_CSR REG_ACCESS(RoReg, 0x40028014U) /**< \brief (USART1) Channel Status Register */ -#define REG_USART1_RHR REG_ACCESS(RoReg, 0x40028018U) /**< \brief (USART1) Receiver Holding Register */ -#define REG_USART1_THR REG_ACCESS(WoReg, 0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */ -#define REG_USART1_BRGR REG_ACCESS(RwReg, 0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */ -#define REG_USART1_RTOR REG_ACCESS(RwReg, 0x40028024U) /**< \brief (USART1) Receiver Time-out Register */ -#define REG_USART1_TTGR REG_ACCESS(RwReg, 0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */ -#define REG_USART1_FIDI REG_ACCESS(RwReg, 0x40028040U) /**< \brief (USART1) FI DI Ratio Register */ -#define REG_USART1_NER REG_ACCESS(RoReg, 0x40028044U) /**< \brief (USART1) Number of Errors Register */ -#define REG_USART1_IF REG_ACCESS(RwReg, 0x4002804CU) /**< \brief (USART1) IrDA Filter Register */ -#define REG_USART1_MAN REG_ACCESS(RwReg, 0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ -#define REG_USART1_WPMR REG_ACCESS(RwReg, 0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */ -#define REG_USART1_WPSR REG_ACCESS(RoReg, 0x400280E8U) /**< \brief (USART1) Write Protect Status Register */ -#define REG_USART1_VERSION REG_ACCESS(RoReg, 0x400280FCU) /**< \brief (USART1) Version Register */ -#define REG_USART1_RPR REG_ACCESS(RwReg, 0x40028100U) /**< \brief (USART1) Receive Pointer Register */ -#define REG_USART1_RCR REG_ACCESS(RwReg, 0x40028104U) /**< \brief (USART1) Receive Counter Register */ -#define REG_USART1_TPR REG_ACCESS(RwReg, 0x40028108U) /**< \brief (USART1) Transmit Pointer Register */ -#define REG_USART1_TCR REG_ACCESS(RwReg, 0x4002810CU) /**< \brief (USART1) Transmit Counter Register */ -#define REG_USART1_RNPR REG_ACCESS(RwReg, 0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */ -#define REG_USART1_RNCR REG_ACCESS(RwReg, 0x40028114U) /**< \brief (USART1) Receive Next Counter Register */ -#define REG_USART1_TNPR REG_ACCESS(RwReg, 0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */ -#define REG_USART1_TNCR REG_ACCESS(RwReg, 0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */ -#define REG_USART1_PTCR REG_ACCESS(WoReg, 0x40028120U) /**< \brief (USART1) Transfer Control Register */ -#define REG_USART1_PTSR REG_ACCESS(RoReg, 0x40028124U) /**< \brief (USART1) Transfer Status Register */ -/* ========== Register definition for UDP peripheral ========== */ -#define REG_UDP_FRM_NUM REG_ACCESS(RoReg, 0x40034000U) /**< \brief (UDP) Frame Number Register */ -#define REG_UDP_GLB_STAT REG_ACCESS(RwReg, 0x40034004U) /**< \brief (UDP) Global State Register */ -#define REG_UDP_FADDR REG_ACCESS(RwReg, 0x40034008U) /**< \brief (UDP) Function Address Register */ -#define REG_UDP_IER REG_ACCESS(WoReg, 0x40034010U) /**< \brief (UDP) Interrupt Enable Register */ -#define REG_UDP_IDR REG_ACCESS(WoReg, 0x40034014U) /**< \brief (UDP) Interrupt Disable Register */ -#define REG_UDP_IMR REG_ACCESS(RoReg, 0x40034018U) /**< \brief (UDP) Interrupt Mask Register */ -#define REG_UDP_ISR REG_ACCESS(RoReg, 0x4003401CU) /**< \brief (UDP) Interrupt Status Register */ -#define REG_UDP_ICR REG_ACCESS(WoReg, 0x40034020U) /**< \brief (UDP) Interrupt Clear Register */ -#define REG_UDP_RST_EP REG_ACCESS(RwReg, 0x40034028U) /**< \brief (UDP) Reset Endpoint Register */ -#define REG_UDP_CSR REG_ACCESS(RwReg, 0x4003402CU) /**< \brief (UDP) Endpoint Control and Status Register (ept_num = 0) */ -#define REG_UDP_FDR REG_ACCESS(RwReg, 0x4003404CU) /**< \brief (UDP) Endpoint FIFO Data Register (ept_num = 0) */ -#define REG_UDP_TXVC REG_ACCESS(RwReg, 0x40034074U) /**< \brief (UDP) Transceiver Control Register */ -/* ========== Register definition for ADC peripheral ========== */ -#define REG_ADC_CR REG_ACCESS(WoReg, 0x40038000U) /**< \brief (ADC) Control Register */ -#define REG_ADC_MR REG_ACCESS(RwReg, 0x40038004U) /**< \brief (ADC) Mode Register */ -#define REG_ADC_SEQ1R REG_ACCESS(RwReg, 0x40038008U) /**< \brief (ADC) Channel Sequence 1Register */ -#define REG_ADC_SEQ2R REG_ACCESS(RwReg, 0x4003800CU) /**< \brief (ADC) Channel Sequence 2 Register */ -#define REG_ADC_CHER REG_ACCESS(WoReg, 0x40038010U) /**< \brief (ADC) Channel Enable Register */ -#define REG_ADC_CHDR REG_ACCESS(WoReg, 0x40038014U) /**< \brief (ADC) Channel Disable Register */ -#define REG_ADC_CHSR REG_ACCESS(RoReg, 0x40038018U) /**< \brief (ADC) Channel Status Register */ -#define REG_ADC_LCDR REG_ACCESS(RoReg, 0x40038020U) /**< \brief (ADC) Last Converted Data Register */ -#define REG_ADC_IER REG_ACCESS(WoReg, 0x40038024U) /**< \brief (ADC) Interrupt Enable Register */ -#define REG_ADC_IDR REG_ACCESS(WoReg, 0x40038028U) /**< \brief (ADC) Interrupt Disable Register */ -#define REG_ADC_IMR REG_ACCESS(RoReg, 0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */ -#define REG_ADC_ISR REG_ACCESS(RoReg, 0x40038030U) /**< \brief (ADC) Interrupt Status Register */ -#define REG_ADC_OVER REG_ACCESS(RoReg, 0x4003803CU) /**< \brief (ADC) Overrun Status Register */ -#define REG_ADC_EMR REG_ACCESS(RwReg, 0x40038040U) /**< \brief (ADC) Extended Mode Register */ -#define REG_ADC_CWR REG_ACCESS(RwReg, 0x40038044U) /**< \brief (ADC) Compare Window Register */ -#define REG_ADC_CGR REG_ACCESS(RwReg, 0x40038048U) /**< \brief (ADC) Channel Gain Register */ -#define REG_ADC_COR REG_ACCESS(RwReg, 0x4003804CU) /**< \brief (ADC) Channel Offset Register */ -#define REG_ADC_CDR0 REG_ACCESS(RoReg, 0x40038050U) /**< \brief (ADC) Channel Data Register 0 */ -#define REG_ADC_CDR1 REG_ACCESS(RoReg, 0x40038054U) /**< \brief (ADC) Channel Data Register 1 */ -#define REG_ADC_CDR2 REG_ACCESS(RoReg, 0x40038058U) /**< \brief (ADC) Channel Data Register 2 */ -#define REG_ADC_CDR3 REG_ACCESS(RoReg, 0x4003805CU) /**< \brief (ADC) Channel Data Register 3 */ -#define REG_ADC_CDR4 REG_ACCESS(RoReg, 0x40038060U) /**< \brief (ADC) Channel Data Register 4 */ -#define REG_ADC_CDR5 REG_ACCESS(RoReg, 0x40038064U) /**< \brief (ADC) Channel Data Register 5 */ -#define REG_ADC_CDR6 REG_ACCESS(RoReg, 0x40038068U) /**< \brief (ADC) Channel Data Register 6 */ -#define REG_ADC_CDR15 REG_ACCESS(RoReg, 0x4003806CU) /**< \brief (ADC) Channel Data Register 15 */ -#define REG_ADC_ACR REG_ACCESS(RwReg, 0x40038094U) /**< \brief (ADC) Analog Control Register */ -#define REG_ADC_WPMR REG_ACCESS(RwReg, 0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */ -#define REG_ADC_WPSR REG_ACCESS(RoReg, 0x400380E8U) /**< \brief (ADC) Write Protect Status Register */ -#define REG_ADC_RPR REG_ACCESS(RwReg, 0x40038100U) /**< \brief (ADC) Receive Pointer Register */ -#define REG_ADC_RCR REG_ACCESS(RwReg, 0x40038104U) /**< \brief (ADC) Receive Counter Register */ -#define REG_ADC_TPR REG_ACCESS(RwReg, 0x40038108U) /**< \brief (ADC) Transmit Pointer Register */ -#define REG_ADC_TCR REG_ACCESS(RwReg, 0x4003810CU) /**< \brief (ADC) Transmit Counter Register */ -#define REG_ADC_RNPR REG_ACCESS(RwReg, 0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */ -#define REG_ADC_RNCR REG_ACCESS(RwReg, 0x40038114U) /**< \brief (ADC) Receive Next Counter Register */ -#define REG_ADC_TNPR REG_ACCESS(RwReg, 0x40038118U) /**< \brief (ADC) Transmit Next Pointer Register */ -#define REG_ADC_TNCR REG_ACCESS(RwReg, 0x4003811CU) /**< \brief (ADC) Transmit Next Counter Register */ -#define REG_ADC_PTCR REG_ACCESS(WoReg, 0x40038120U) /**< \brief (ADC) Transfer Control Register */ -#define REG_ADC_PTSR REG_ACCESS(RoReg, 0x40038124U) /**< \brief (ADC) Transfer Status Register */ -/* ========== Register definition for DACC peripheral ========== */ -#define REG_DACC_CR REG_ACCESS(WoReg, 0x4003C000U) /**< \brief (DACC) Control Register */ -#define REG_DACC_MR REG_ACCESS(RwReg, 0x4003C004U) /**< \brief (DACC) Mode Register */ -#define REG_DACC_CHER REG_ACCESS(WoReg, 0x4003C010U) /**< \brief (DACC) Channel Enable Register */ -#define REG_DACC_CHDR REG_ACCESS(WoReg, 0x4003C014U) /**< \brief (DACC) Channel Disable Register */ -#define REG_DACC_CHSR REG_ACCESS(RoReg, 0x4003C018U) /**< \brief (DACC) Channel Status Register */ -#define REG_DACC_CDR REG_ACCESS(WoReg, 0x4003C020U) /**< \brief (DACC) Conversion Data Register */ -#define REG_DACC_IER REG_ACCESS(WoReg, 0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */ -#define REG_DACC_IDR REG_ACCESS(WoReg, 0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */ -#define REG_DACC_IMR REG_ACCESS(RoReg, 0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */ -#define REG_DACC_ISR REG_ACCESS(RoReg, 0x4003C030U) /**< \brief (DACC) Interrupt Status Register */ -#define REG_DACC_ACR REG_ACCESS(RwReg, 0x4003C094U) /**< \brief (DACC) Analog Current Register */ -#define REG_DACC_WPMR REG_ACCESS(RwReg, 0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */ -#define REG_DACC_WPSR REG_ACCESS(RoReg, 0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */ -#define REG_DACC_RPR REG_ACCESS(RwReg, 0x4003C100U) /**< \brief (DACC) Receive Pointer Register */ -#define REG_DACC_RCR REG_ACCESS(RwReg, 0x4003C104U) /**< \brief (DACC) Receive Counter Register */ -#define REG_DACC_TPR REG_ACCESS(RwReg, 0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */ -#define REG_DACC_TCR REG_ACCESS(RwReg, 0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */ -#define REG_DACC_RNPR REG_ACCESS(RwReg, 0x4003C110U) /**< \brief (DACC) Receive Next Pointer Register */ -#define REG_DACC_RNCR REG_ACCESS(RwReg, 0x4003C114U) /**< \brief (DACC) Receive Next Counter Register */ -#define REG_DACC_TNPR REG_ACCESS(RwReg, 0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */ -#define REG_DACC_TNCR REG_ACCESS(RwReg, 0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */ -#define REG_DACC_PTCR REG_ACCESS(WoReg, 0x4003C120U) /**< \brief (DACC) Transfer Control Register */ -#define REG_DACC_PTSR REG_ACCESS(RoReg, 0x4003C124U) /**< \brief (DACC) Transfer Status Register */ -/* ========== Register definition for ACC peripheral ========== */ -#define REG_ACC_CR REG_ACCESS(WoReg, 0x40040000U) /**< \brief (ACC) Control Register */ -#define REG_ACC_MR REG_ACCESS(RwReg, 0x40040004U) /**< \brief (ACC) Mode Register */ -#define REG_ACC_IER REG_ACCESS(WoReg, 0x40040024U) /**< \brief (ACC) Interrupt Enable Register */ -#define REG_ACC_IDR REG_ACCESS(WoReg, 0x40040028U) /**< \brief (ACC) Interrupt Disable Register */ -#define REG_ACC_IMR REG_ACCESS(RoReg, 0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */ -#define REG_ACC_ISR REG_ACCESS(RoReg, 0x40040030U) /**< \brief (ACC) Interrupt Status Register */ -#define REG_ACC_ACR REG_ACCESS(RwReg, 0x40040094U) /**< \brief (ACC) Analog Control Register */ -#define REG_ACC_WPMR REG_ACCESS(RwReg, 0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */ -#define REG_ACC_WPSR REG_ACCESS(RoReg, 0x400400E8U) /**< \brief (ACC) Write Protect Status Register */ -/* ========== Register definition for CRCCU peripheral ========== */ -#define REG_CRCCU_DSCR REG_ACCESS(RwReg, 0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */ -#define REG_CRCCU_DMA_EN REG_ACCESS(WoReg, 0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */ -#define REG_CRCCU_DMA_DIS REG_ACCESS(WoReg, 0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */ -#define REG_CRCCU_DMA_SR REG_ACCESS(RoReg, 0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */ -#define REG_CRCCU_DMA_IER REG_ACCESS(WoReg, 0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */ -#define REG_CRCCU_DMA_IDR REG_ACCESS(WoReg, 0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */ -#define REG_CRCCU_DMA_IMR REG_ACCESS(RoReg, 0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */ -#define REG_CRCCU_DMA_ISR REG_ACCESS(RoReg, 0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */ -#define REG_CRCCU_CR REG_ACCESS(WoReg, 0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */ -#define REG_CRCCU_MR REG_ACCESS(RwReg, 0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */ -#define REG_CRCCU_SR REG_ACCESS(RoReg, 0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */ -#define REG_CRCCU_IER REG_ACCESS(WoReg, 0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */ -#define REG_CRCCU_IDR REG_ACCESS(WoReg, 0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */ -#define REG_CRCCU_IMR REG_ACCESS(RoReg, 0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */ -#define REG_CRCCU_ISR REG_ACCESS(RoReg, 0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */ -/* ========== Register definition for SMC peripheral ========== */ -#define REG_SMC_SETUP0 REG_ACCESS(RwReg, 0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ -#define REG_SMC_PULSE0 REG_ACCESS(RwReg, 0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ -#define REG_SMC_CYCLE0 REG_ACCESS(RwReg, 0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ -#define REG_SMC_MODE0 REG_ACCESS(RwReg, 0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ -#define REG_SMC_SETUP1 REG_ACCESS(RwReg, 0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ -#define REG_SMC_PULSE1 REG_ACCESS(RwReg, 0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ -#define REG_SMC_CYCLE1 REG_ACCESS(RwReg, 0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ -#define REG_SMC_MODE1 REG_ACCESS(RwReg, 0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ -#define REG_SMC_SETUP2 REG_ACCESS(RwReg, 0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ -#define REG_SMC_PULSE2 REG_ACCESS(RwReg, 0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ -#define REG_SMC_CYCLE2 REG_ACCESS(RwReg, 0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ -#define REG_SMC_MODE2 REG_ACCESS(RwReg, 0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ -#define REG_SMC_SETUP3 REG_ACCESS(RwReg, 0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ -#define REG_SMC_PULSE3 REG_ACCESS(RwReg, 0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ -#define REG_SMC_CYCLE3 REG_ACCESS(RwReg, 0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ -#define REG_SMC_MODE3 REG_ACCESS(RwReg, 0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ -#define REG_SMC_SETUP4 REG_ACCESS(RwReg, 0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */ -#define REG_SMC_PULSE4 REG_ACCESS(RwReg, 0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */ -#define REG_SMC_CYCLE4 REG_ACCESS(RwReg, 0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */ -#define REG_SMC_MODE4 REG_ACCESS(RwReg, 0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */ -#define REG_SMC_OCMS REG_ACCESS(RwReg, 0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */ -#define REG_SMC_KEY1 REG_ACCESS(WoReg, 0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */ -#define REG_SMC_KEY2 REG_ACCESS(WoReg, 0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */ -#define REG_SMC_WPMR REG_ACCESS(RwReg, 0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */ -#define REG_SMC_WPSR REG_ACCESS(RoReg, 0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */ -/* ========== Register definition for MATRIX peripheral ========== */ -#define REG_MATRIX_MCFG REG_ACCESS(RwReg, 0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ -#define REG_MATRIX_SCFG REG_ACCESS(RwReg, 0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ -#define REG_MATRIX_PRAS0 REG_ACCESS(RwReg, 0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ -#define REG_MATRIX_PRAS1 REG_ACCESS(RwReg, 0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ -#define REG_MATRIX_PRAS2 REG_ACCESS(RwReg, 0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ -#define REG_MATRIX_PRAS3 REG_ACCESS(RwReg, 0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ -#define REG_MATRIX_PRAS4 REG_ACCESS(RwReg, 0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ -#define REG_MATRIX_SYSIO REG_ACCESS(RwReg, 0x400E0314U) /**< \brief (MATRIX) System IO Configuration register */ -#define REG_MATRIX_SMCNFCS REG_ACCESS(RwReg, 0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */ -#define REG_MATRIX_WPMR REG_ACCESS(RwReg, 0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */ -#define REG_MATRIX_WPSR REG_ACCESS(RoReg, 0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */ -/* ========== Register definition for PMC peripheral ========== */ -#define REG_PMC_SCER REG_ACCESS(WoReg, 0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ -#define REG_PMC_SCDR REG_ACCESS(WoReg, 0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ -#define REG_PMC_SCSR REG_ACCESS(RoReg, 0x400E0408U) /**< \brief (PMC) System Clock Status Register */ -#define REG_PMC_PCER0 REG_ACCESS(WoReg, 0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ -#define REG_PMC_PCDR0 REG_ACCESS(WoReg, 0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ -#define REG_PMC_PCSR0 REG_ACCESS(RoReg, 0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ -#define REG_PMC_MOR REG_ACCESS(RwReg, 0x400E0420U) /**< \brief (PMC) Main Oscillator Register */ -#define REG_PMC_MCFR REG_ACCESS(RoReg, 0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */ -#define REG_PMC_PLLAR REG_ACCESS(RwReg, 0x400E0428U) /**< \brief (PMC) PLLA Register */ -#define REG_PMC_PLLBR REG_ACCESS(RwReg, 0x400E042CU) /**< \brief (PMC) PLLB Register */ -#define REG_PMC_MCKR REG_ACCESS(RwReg, 0x400E0430U) /**< \brief (PMC) Master Clock Register */ -#define REG_PMC_USB REG_ACCESS(RwReg, 0x400E0438U) /**< \brief (PMC) USB Clock Register */ -#define REG_PMC_PCK REG_ACCESS(RwReg, 0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */ -#define REG_PMC_IER REG_ACCESS(WoReg, 0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */ -#define REG_PMC_IDR REG_ACCESS(WoReg, 0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */ -#define REG_PMC_SR REG_ACCESS(RoReg, 0x400E0468U) /**< \brief (PMC) Status Register */ -#define REG_PMC_IMR REG_ACCESS(RoReg, 0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */ -#define REG_PMC_FSMR REG_ACCESS(RwReg, 0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */ -#define REG_PMC_FSPR REG_ACCESS(RwReg, 0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */ -#define REG_PMC_FOCR REG_ACCESS(WoReg, 0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ -#define REG_PMC_WPMR REG_ACCESS(RwReg, 0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */ -#define REG_PMC_WPSR REG_ACCESS(RoReg, 0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */ -#define REG_PMC_PCER1 REG_ACCESS(WoReg, 0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ -#define REG_PMC_PCDR1 REG_ACCESS(WoReg, 0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ -#define REG_PMC_PCSR1 REG_ACCESS(RoReg, 0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ -#define REG_PMC_OCR REG_ACCESS(RwReg, 0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */ -/* ========== Register definition for UART0 peripheral ========== */ -#define REG_UART0_CR REG_ACCESS(WoReg, 0x400E0600U) /**< \brief (UART0) Control Register */ -#define REG_UART0_MR REG_ACCESS(RwReg, 0x400E0604U) /**< \brief (UART0) Mode Register */ -#define REG_UART0_IER REG_ACCESS(WoReg, 0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */ -#define REG_UART0_IDR REG_ACCESS(WoReg, 0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */ -#define REG_UART0_IMR REG_ACCESS(RoReg, 0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */ -#define REG_UART0_SR REG_ACCESS(RoReg, 0x400E0614U) /**< \brief (UART0) Status Register */ -#define REG_UART0_RHR REG_ACCESS(RoReg, 0x400E0618U) /**< \brief (UART0) Receive Holding Register */ -#define REG_UART0_THR REG_ACCESS(WoReg, 0x400E061CU) /**< \brief (UART0) Transmit Holding Register */ -#define REG_UART0_BRGR REG_ACCESS(RwReg, 0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */ -#define REG_UART0_RPR REG_ACCESS(RwReg, 0x400E0700U) /**< \brief (UART0) Receive Pointer Register */ -#define REG_UART0_RCR REG_ACCESS(RwReg, 0x400E0704U) /**< \brief (UART0) Receive Counter Register */ -#define REG_UART0_TPR REG_ACCESS(RwReg, 0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */ -#define REG_UART0_TCR REG_ACCESS(RwReg, 0x400E070CU) /**< \brief (UART0) Transmit Counter Register */ -#define REG_UART0_RNPR REG_ACCESS(RwReg, 0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */ -#define REG_UART0_RNCR REG_ACCESS(RwReg, 0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */ -#define REG_UART0_TNPR REG_ACCESS(RwReg, 0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */ -#define REG_UART0_TNCR REG_ACCESS(RwReg, 0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */ -#define REG_UART0_PTCR REG_ACCESS(WoReg, 0x400E0720U) /**< \brief (UART0) Transfer Control Register */ -#define REG_UART0_PTSR REG_ACCESS(RoReg, 0x400E0724U) /**< \brief (UART0) Transfer Status Register */ -/* ========== Register definition for CHIPID peripheral ========== */ -#define REG_CHIPID_CIDR REG_ACCESS(RoReg, 0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ -#define REG_CHIPID_EXID REG_ACCESS(RoReg, 0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ -/* ========== Register definition for UART1 peripheral ========== */ -#define REG_UART1_CR REG_ACCESS(WoReg, 0x400E0800U) /**< \brief (UART1) Control Register */ -#define REG_UART1_MR REG_ACCESS(RwReg, 0x400E0804U) /**< \brief (UART1) Mode Register */ -#define REG_UART1_IER REG_ACCESS(WoReg, 0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */ -#define REG_UART1_IDR REG_ACCESS(WoReg, 0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */ -#define REG_UART1_IMR REG_ACCESS(RoReg, 0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */ -#define REG_UART1_SR REG_ACCESS(RoReg, 0x400E0814U) /**< \brief (UART1) Status Register */ -#define REG_UART1_RHR REG_ACCESS(RoReg, 0x400E0818U) /**< \brief (UART1) Receive Holding Register */ -#define REG_UART1_THR REG_ACCESS(WoReg, 0x400E081CU) /**< \brief (UART1) Transmit Holding Register */ -#define REG_UART1_BRGR REG_ACCESS(RwReg, 0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */ -#define REG_UART1_RPR REG_ACCESS(RwReg, 0x400E0900U) /**< \brief (UART1) Receive Pointer Register */ -#define REG_UART1_RCR REG_ACCESS(RwReg, 0x400E0904U) /**< \brief (UART1) Receive Counter Register */ -#define REG_UART1_TPR REG_ACCESS(RwReg, 0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */ -#define REG_UART1_TCR REG_ACCESS(RwReg, 0x400E090CU) /**< \brief (UART1) Transmit Counter Register */ -#define REG_UART1_RNPR REG_ACCESS(RwReg, 0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */ -#define REG_UART1_RNCR REG_ACCESS(RwReg, 0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */ -#define REG_UART1_TNPR REG_ACCESS(RwReg, 0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */ -#define REG_UART1_TNCR REG_ACCESS(RwReg, 0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */ -#define REG_UART1_PTCR REG_ACCESS(WoReg, 0x400E0920U) /**< \brief (UART1) Transfer Control Register */ -#define REG_UART1_PTSR REG_ACCESS(RoReg, 0x400E0924U) /**< \brief (UART1) Transfer Status Register */ -/* ========== Register definition for EFC peripheral ========== */ -#define REG_EFC_FMR REG_ACCESS(RwReg, 0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */ -#define REG_EFC_FCR REG_ACCESS(WoReg, 0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */ -#define REG_EFC_FSR REG_ACCESS(RoReg, 0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */ -#define REG_EFC_FRR REG_ACCESS(RoReg, 0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */ -/* ========== Register definition for PIOA peripheral ========== */ -#define REG_PIOA_PER REG_ACCESS(WoReg, 0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ -#define REG_PIOA_PDR REG_ACCESS(WoReg, 0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ -#define REG_PIOA_PSR REG_ACCESS(RoReg, 0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ -#define REG_PIOA_OER REG_ACCESS(WoReg, 0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ -#define REG_PIOA_ODR REG_ACCESS(WoReg, 0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ -#define REG_PIOA_OSR REG_ACCESS(RoReg, 0x400E0E18U) /**< \brief (PIOA) Output Status Register */ -#define REG_PIOA_IFER REG_ACCESS(WoReg, 0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ -#define REG_PIOA_IFDR REG_ACCESS(WoReg, 0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ -#define REG_PIOA_IFSR REG_ACCESS(RoReg, 0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ -#define REG_PIOA_SODR REG_ACCESS(WoReg, 0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ -#define REG_PIOA_CODR REG_ACCESS(WoReg, 0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ -#define REG_PIOA_ODSR REG_ACCESS(RwReg, 0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ -#define REG_PIOA_PDSR REG_ACCESS(RoReg, 0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ -#define REG_PIOA_IER REG_ACCESS(WoReg, 0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ -#define REG_PIOA_IDR REG_ACCESS(WoReg, 0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ -#define REG_PIOA_IMR REG_ACCESS(RoReg, 0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ -#define REG_PIOA_ISR REG_ACCESS(RoReg, 0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ -#define REG_PIOA_MDER REG_ACCESS(WoReg, 0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ -#define REG_PIOA_MDDR REG_ACCESS(WoReg, 0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ -#define REG_PIOA_MDSR REG_ACCESS(RoReg, 0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ -#define REG_PIOA_PUDR REG_ACCESS(WoReg, 0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ -#define REG_PIOA_PUER REG_ACCESS(WoReg, 0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ -#define REG_PIOA_PUSR REG_ACCESS(RoReg, 0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ -#define REG_PIOA_ABCDSR REG_ACCESS(RwReg, 0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ -#define REG_PIOA_SCIFSR REG_ACCESS(WoReg, 0x400E0E80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */ -#define REG_PIOA_DIFSR REG_ACCESS(WoReg, 0x400E0E84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */ -#define REG_PIOA_IFDGSR REG_ACCESS(RoReg, 0x400E0E88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOA_SCDR REG_ACCESS(RwReg, 0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ -#define REG_PIOA_PPDDR REG_ACCESS(WoReg, 0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ -#define REG_PIOA_PPDER REG_ACCESS(WoReg, 0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ -#define REG_PIOA_PPDSR REG_ACCESS(RoReg, 0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ -#define REG_PIOA_OWER REG_ACCESS(WoReg, 0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ -#define REG_PIOA_OWDR REG_ACCESS(WoReg, 0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ -#define REG_PIOA_OWSR REG_ACCESS(RoReg, 0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ -#define REG_PIOA_AIMER REG_ACCESS(WoReg, 0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ -#define REG_PIOA_AIMDR REG_ACCESS(WoReg, 0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ -#define REG_PIOA_AIMMR REG_ACCESS(RoReg, 0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ -#define REG_PIOA_ESR REG_ACCESS(WoReg, 0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ -#define REG_PIOA_LSR REG_ACCESS(WoReg, 0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ -#define REG_PIOA_ELSR REG_ACCESS(RoReg, 0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ -#define REG_PIOA_FELLSR REG_ACCESS(WoReg, 0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ -#define REG_PIOA_REHLSR REG_ACCESS(WoReg, 0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ -#define REG_PIOA_FRLHSR REG_ACCESS(RoReg, 0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ -#define REG_PIOA_LOCKSR REG_ACCESS(RoReg, 0x400E0EE0U) /**< \brief (PIOA) Lock Status */ -#define REG_PIOA_WPMR REG_ACCESS(RwReg, 0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */ -#define REG_PIOA_WPSR REG_ACCESS(RoReg, 0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */ -#define REG_PIOA_SCHMITT REG_ACCESS(RwReg, 0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ -#define REG_PIOA_PCMR REG_ACCESS(RwReg, 0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */ -#define REG_PIOA_PCIER REG_ACCESS(WoReg, 0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */ -#define REG_PIOA_PCIDR REG_ACCESS(WoReg, 0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */ -#define REG_PIOA_PCIMR REG_ACCESS(RoReg, 0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */ -#define REG_PIOA_PCISR REG_ACCESS(RoReg, 0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */ -#define REG_PIOA_PCRHR REG_ACCESS(RoReg, 0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */ -/* ========== Register definition for PIOB peripheral ========== */ -#define REG_PIOB_PER REG_ACCESS(WoReg, 0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ -#define REG_PIOB_PDR REG_ACCESS(WoReg, 0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ -#define REG_PIOB_PSR REG_ACCESS(RoReg, 0x400E1008U) /**< \brief (PIOB) PIO Status Register */ -#define REG_PIOB_OER REG_ACCESS(WoReg, 0x400E1010U) /**< \brief (PIOB) Output Enable Register */ -#define REG_PIOB_ODR REG_ACCESS(WoReg, 0x400E1014U) /**< \brief (PIOB) Output Disable Register */ -#define REG_PIOB_OSR REG_ACCESS(RoReg, 0x400E1018U) /**< \brief (PIOB) Output Status Register */ -#define REG_PIOB_IFER REG_ACCESS(WoReg, 0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ -#define REG_PIOB_IFDR REG_ACCESS(WoReg, 0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ -#define REG_PIOB_IFSR REG_ACCESS(RoReg, 0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ -#define REG_PIOB_SODR REG_ACCESS(WoReg, 0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ -#define REG_PIOB_CODR REG_ACCESS(WoReg, 0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ -#define REG_PIOB_ODSR REG_ACCESS(RwReg, 0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ -#define REG_PIOB_PDSR REG_ACCESS(RoReg, 0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ -#define REG_PIOB_IER REG_ACCESS(WoReg, 0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ -#define REG_PIOB_IDR REG_ACCESS(WoReg, 0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ -#define REG_PIOB_IMR REG_ACCESS(RoReg, 0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ -#define REG_PIOB_ISR REG_ACCESS(RoReg, 0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ -#define REG_PIOB_MDER REG_ACCESS(WoReg, 0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ -#define REG_PIOB_MDDR REG_ACCESS(WoReg, 0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ -#define REG_PIOB_MDSR REG_ACCESS(RoReg, 0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ -#define REG_PIOB_PUDR REG_ACCESS(WoReg, 0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ -#define REG_PIOB_PUER REG_ACCESS(WoReg, 0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ -#define REG_PIOB_PUSR REG_ACCESS(RoReg, 0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ -#define REG_PIOB_ABCDSR REG_ACCESS(RwReg, 0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ -#define REG_PIOB_SCIFSR REG_ACCESS(WoReg, 0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */ -#define REG_PIOB_DIFSR REG_ACCESS(WoReg, 0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */ -#define REG_PIOB_IFDGSR REG_ACCESS(RoReg, 0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOB_SCDR REG_ACCESS(RwReg, 0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ -#define REG_PIOB_PPDDR REG_ACCESS(WoReg, 0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ -#define REG_PIOB_PPDER REG_ACCESS(WoReg, 0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ -#define REG_PIOB_PPDSR REG_ACCESS(RoReg, 0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ -#define REG_PIOB_OWER REG_ACCESS(WoReg, 0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ -#define REG_PIOB_OWDR REG_ACCESS(WoReg, 0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ -#define REG_PIOB_OWSR REG_ACCESS(RoReg, 0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ -#define REG_PIOB_AIMER REG_ACCESS(WoReg, 0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ -#define REG_PIOB_AIMDR REG_ACCESS(WoReg, 0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ -#define REG_PIOB_AIMMR REG_ACCESS(RoReg, 0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ -#define REG_PIOB_ESR REG_ACCESS(WoReg, 0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ -#define REG_PIOB_LSR REG_ACCESS(WoReg, 0x400E10C4U) /**< \brief (PIOB) Level Select Register */ -#define REG_PIOB_ELSR REG_ACCESS(RoReg, 0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ -#define REG_PIOB_FELLSR REG_ACCESS(WoReg, 0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ -#define REG_PIOB_REHLSR REG_ACCESS(WoReg, 0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ -#define REG_PIOB_FRLHSR REG_ACCESS(RoReg, 0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ -#define REG_PIOB_LOCKSR REG_ACCESS(RoReg, 0x400E10E0U) /**< \brief (PIOB) Lock Status */ -#define REG_PIOB_WPMR REG_ACCESS(RwReg, 0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */ -#define REG_PIOB_WPSR REG_ACCESS(RoReg, 0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */ -#define REG_PIOB_SCHMITT REG_ACCESS(RwReg, 0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ -#define REG_PIOB_PCMR REG_ACCESS(RwReg, 0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */ -#define REG_PIOB_PCIER REG_ACCESS(WoReg, 0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */ -#define REG_PIOB_PCIDR REG_ACCESS(WoReg, 0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */ -#define REG_PIOB_PCIMR REG_ACCESS(RoReg, 0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */ -#define REG_PIOB_PCISR REG_ACCESS(RoReg, 0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */ -#define REG_PIOB_PCRHR REG_ACCESS(RoReg, 0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */ -/* ========== Register definition for PIOC peripheral ========== */ -#define REG_PIOC_PER REG_ACCESS(WoReg, 0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ -#define REG_PIOC_PDR REG_ACCESS(WoReg, 0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ -#define REG_PIOC_PSR REG_ACCESS(RoReg, 0x400E1208U) /**< \brief (PIOC) PIO Status Register */ -#define REG_PIOC_OER REG_ACCESS(WoReg, 0x400E1210U) /**< \brief (PIOC) Output Enable Register */ -#define REG_PIOC_ODR REG_ACCESS(WoReg, 0x400E1214U) /**< \brief (PIOC) Output Disable Register */ -#define REG_PIOC_OSR REG_ACCESS(RoReg, 0x400E1218U) /**< \brief (PIOC) Output Status Register */ -#define REG_PIOC_IFER REG_ACCESS(WoReg, 0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ -#define REG_PIOC_IFDR REG_ACCESS(WoReg, 0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ -#define REG_PIOC_IFSR REG_ACCESS(RoReg, 0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ -#define REG_PIOC_SODR REG_ACCESS(WoReg, 0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ -#define REG_PIOC_CODR REG_ACCESS(WoReg, 0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ -#define REG_PIOC_ODSR REG_ACCESS(RwReg, 0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ -#define REG_PIOC_PDSR REG_ACCESS(RoReg, 0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ -#define REG_PIOC_IER REG_ACCESS(WoReg, 0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ -#define REG_PIOC_IDR REG_ACCESS(WoReg, 0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ -#define REG_PIOC_IMR REG_ACCESS(RoReg, 0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ -#define REG_PIOC_ISR REG_ACCESS(RoReg, 0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ -#define REG_PIOC_MDER REG_ACCESS(WoReg, 0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ -#define REG_PIOC_MDDR REG_ACCESS(WoReg, 0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ -#define REG_PIOC_MDSR REG_ACCESS(RoReg, 0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ -#define REG_PIOC_PUDR REG_ACCESS(WoReg, 0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ -#define REG_PIOC_PUER REG_ACCESS(WoReg, 0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ -#define REG_PIOC_PUSR REG_ACCESS(RoReg, 0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ -#define REG_PIOC_ABCDSR REG_ACCESS(RwReg, 0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */ -#define REG_PIOC_SCIFSR REG_ACCESS(WoReg, 0x400E1280U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */ -#define REG_PIOC_DIFSR REG_ACCESS(WoReg, 0x400E1284U) /**< \brief (PIOC) Debouncing Input Filter Select Register */ -#define REG_PIOC_IFDGSR REG_ACCESS(RoReg, 0x400E1288U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOC_SCDR REG_ACCESS(RwReg, 0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ -#define REG_PIOC_PPDDR REG_ACCESS(WoReg, 0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */ -#define REG_PIOC_PPDER REG_ACCESS(WoReg, 0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */ -#define REG_PIOC_PPDSR REG_ACCESS(RoReg, 0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */ -#define REG_PIOC_OWER REG_ACCESS(WoReg, 0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ -#define REG_PIOC_OWDR REG_ACCESS(WoReg, 0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ -#define REG_PIOC_OWSR REG_ACCESS(RoReg, 0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ -#define REG_PIOC_AIMER REG_ACCESS(WoReg, 0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ -#define REG_PIOC_AIMDR REG_ACCESS(WoReg, 0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ -#define REG_PIOC_AIMMR REG_ACCESS(RoReg, 0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ -#define REG_PIOC_ESR REG_ACCESS(WoReg, 0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ -#define REG_PIOC_LSR REG_ACCESS(WoReg, 0x400E12C4U) /**< \brief (PIOC) Level Select Register */ -#define REG_PIOC_ELSR REG_ACCESS(RoReg, 0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ -#define REG_PIOC_FELLSR REG_ACCESS(WoReg, 0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ -#define REG_PIOC_REHLSR REG_ACCESS(WoReg, 0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ -#define REG_PIOC_FRLHSR REG_ACCESS(RoReg, 0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ -#define REG_PIOC_LOCKSR REG_ACCESS(RoReg, 0x400E12E0U) /**< \brief (PIOC) Lock Status */ -#define REG_PIOC_WPMR REG_ACCESS(RwReg, 0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */ -#define REG_PIOC_WPSR REG_ACCESS(RoReg, 0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */ -#define REG_PIOC_SCHMITT REG_ACCESS(RwReg, 0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */ -#define REG_PIOC_PCMR REG_ACCESS(RwReg, 0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */ -#define REG_PIOC_PCIER REG_ACCESS(WoReg, 0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */ -#define REG_PIOC_PCIDR REG_ACCESS(WoReg, 0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */ -#define REG_PIOC_PCIMR REG_ACCESS(RoReg, 0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */ -#define REG_PIOC_PCISR REG_ACCESS(RoReg, 0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */ -#define REG_PIOC_PCRHR REG_ACCESS(RoReg, 0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */ -/* ========== Register definition for RSTC peripheral ========== */ -#define REG_RSTC_CR REG_ACCESS(WoReg, 0x400E1400U) /**< \brief (RSTC) Control Register */ -#define REG_RSTC_SR REG_ACCESS(RoReg, 0x400E1404U) /**< \brief (RSTC) Status Register */ -#define REG_RSTC_MR REG_ACCESS(RwReg, 0x400E1408U) /**< \brief (RSTC) Mode Register */ -/* ========== Register definition for SUPC peripheral ========== */ -#define REG_SUPC_CR REG_ACCESS(WoReg, 0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */ -#define REG_SUPC_SMMR REG_ACCESS(RwReg, 0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ -#define REG_SUPC_MR REG_ACCESS(RwReg, 0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */ -#define REG_SUPC_WUMR REG_ACCESS(RwReg, 0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */ -#define REG_SUPC_WUIR REG_ACCESS(RwReg, 0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */ -#define REG_SUPC_SR REG_ACCESS(RoReg, 0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */ -/* ========== Register definition for RTT peripheral ========== */ -#define REG_RTT_MR REG_ACCESS(RwReg, 0x400E1430U) /**< \brief (RTT) Mode Register */ -#define REG_RTT_AR REG_ACCESS(RwReg, 0x400E1434U) /**< \brief (RTT) Alarm Register */ -#define REG_RTT_VR REG_ACCESS(RoReg, 0x400E1438U) /**< \brief (RTT) Value Register */ -#define REG_RTT_SR REG_ACCESS(RoReg, 0x400E143CU) /**< \brief (RTT) Status Register */ -/* ========== Register definition for WDT peripheral ========== */ -#define REG_WDT_CR REG_ACCESS(WoReg, 0x400E1450U) /**< \brief (WDT) Control Register */ -#define REG_WDT_MR REG_ACCESS(RwReg, 0x400E1454U) /**< \brief (WDT) Mode Register */ -#define REG_WDT_SR REG_ACCESS(RoReg, 0x400E1458U) /**< \brief (WDT) Status Register */ -/* ========== Register definition for RTC peripheral ========== */ -#define REG_RTC_CR REG_ACCESS(RwReg, 0x400E1460U) /**< \brief (RTC) Control Register */ -#define REG_RTC_MR REG_ACCESS(RwReg, 0x400E1464U) /**< \brief (RTC) Mode Register */ -#define REG_RTC_TIMR REG_ACCESS(RwReg, 0x400E1468U) /**< \brief (RTC) Time Register */ -#define REG_RTC_CALR REG_ACCESS(RwReg, 0x400E146CU) /**< \brief (RTC) Calendar Register */ -#define REG_RTC_TIMALR REG_ACCESS(RwReg, 0x400E1470U) /**< \brief (RTC) Time Alarm Register */ -#define REG_RTC_CALALR REG_ACCESS(RwReg, 0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */ -#define REG_RTC_SR REG_ACCESS(RoReg, 0x400E1478U) /**< \brief (RTC) Status Register */ -#define REG_RTC_SCCR REG_ACCESS(WoReg, 0x400E147CU) /**< \brief (RTC) Status Clear Command Register */ -#define REG_RTC_IER REG_ACCESS(WoReg, 0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */ -#define REG_RTC_IDR REG_ACCESS(WoReg, 0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */ -#define REG_RTC_IMR REG_ACCESS(RoReg, 0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */ -#define REG_RTC_VER REG_ACCESS(RoReg, 0x400E148CU) /**< \brief (RTC) Valid Entry Register */ -/* ========== Register definition for GPBR peripheral ========== */ -#define REG_GPBR_GPBR0 REG_ACCESS(RwReg, 0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register 0 */ -#define REG_GPBR_GPBR1 REG_ACCESS(RwReg, 0x400E1494U) /**< \brief (GPBR) General Purpose Backup Register 1 */ -#define REG_GPBR_GPBR2 REG_ACCESS(RwReg, 0x400E1498U) /**< \brief (GPBR) General Purpose Backup Register 2 */ -#define REG_GPBR_GPBR3 REG_ACCESS(RwReg, 0x400E149CU) /**< \brief (GPBR) General Purpose Backup Register 3 */ -/*@}*/ - -/* ***************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_id Peripheral Ids Definitions */ -/*@{*/ - -#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ -#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ -#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ -#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ -#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ -#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ -#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */ -#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ -#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ -#define ID_SMC (10) /**< \brief Static Memory Controller (SMC) */ -#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ -#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ -#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ -#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ -#define ID_USART1 (15) /**< \brief USART 1 (USART1) */ -#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ -#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ -#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ -#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ -#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */ -#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ -#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ -#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ -#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ -#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ -#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ -#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ -#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ -#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ -#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ -#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ -#define ID_UDP (34) /**< \brief USB Device Port (UDP) */ -/*@}*/ - -/* ***************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_base Peripheral Base Address Definitions */ -/*@{*/ - -#define HSMCI CAST(Hsmci , 0x40000000U) /**< \brief (HSMCI ) Base Address */ -#define PDC_HSMCI CAST(Pdc , 0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ -#define SSC CAST(Ssc , 0x40004000U) /**< \brief (SSC ) Base Address */ -#define PDC_SSC CAST(Pdc , 0x40004100U) /**< \brief (PDC_SSC ) Base Address */ -#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */ -#define PDC_SPI CAST(Pdc , 0x40008100U) /**< \brief (PDC_SPI ) Base Address */ -#define TC0 CAST(Tc , 0x40010000U) /**< \brief (TC0 ) Base Address */ -#define TC1 CAST(Tc , 0x40014000U) /**< \brief (TC1 ) Base Address */ -#define TWI0 CAST(Twi , 0x40018000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 CAST(Pdc , 0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 CAST(Twi , 0x4001C000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 CAST(Pdc , 0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define PWM CAST(Pwm , 0x40020000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM CAST(Pdc , 0x40020100U) /**< \brief (PDC_PWM ) Base Address */ -#define USART0 CAST(Usart , 0x40024000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 CAST(Pdc , 0x40024100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 CAST(Usart , 0x40028000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 CAST(Pdc , 0x40028100U) /**< \brief (PDC_USART1) Base Address */ -#define UDP CAST(Udp , 0x40034000U) /**< \brief (UDP ) Base Address */ -#define ADC CAST(Adc , 0x40038000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC CAST(Pdc , 0x40038100U) /**< \brief (PDC_ADC ) Base Address */ -#define DACC CAST(Dacc , 0x4003C000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC CAST(Pdc , 0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ -#define ACC CAST(Acc , 0x40040000U) /**< \brief (ACC ) Base Address */ -#define CRCCU CAST(Crccu , 0x40044000U) /**< \brief (CRCCU ) Base Address */ -#define SMC CAST(Smc , 0x400E0000U) /**< \brief (SMC ) Base Address */ -#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */ -#define UART0 CAST(Uart , 0x400E0600U) /**< \brief (UART0 ) Base Address */ -#define PDC_UART0 CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ -#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define UART1 CAST(Uart , 0x400E0800U) /**< \brief (UART1 ) Base Address */ -#define PDC_UART1 CAST(Pdc , 0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ -#define EFC CAST(Efc , 0x400E0A00U) /**< \brief (EFC ) Base Address */ -#define PIOA CAST(Pio , 0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB CAST(Pio , 0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC CAST(Pio , 0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define RSTC CAST(Rstc , 0x400E1400U) /**< \brief (RSTC ) Base Address */ -#define SUPC CAST(Supc , 0x400E1410U) /**< \brief (SUPC ) Base Address */ -#define RTT CAST(Rtt , 0x400E1430U) /**< \brief (RTT ) Base Address */ -#define WDT CAST(Wdt , 0x400E1450U) /**< \brief (WDT ) Base Address */ -#define RTC CAST(Rtc , 0x400E1460U) /**< \brief (RTC ) Base Address */ -#define GPBR CAST(Gpbr , 0x400E1490U) /**< \brief (GPBR ) Base Address */ - -// indices for three pio structures -#define iPIOA 0 -#define iPIOB 1 -#define iPIOC 2 -/*@}*/ - -/* ***************************************************************************** */ -/* PIO DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_pio Peripheral Pio Definitions */ -/*@{*/ - -#define PIO_PA0 (1 << 0) /**< \brief Pin Controlled by PA0 */ -#define PIO_PA1 (1 << 1) /**< \brief Pin Controlled by PA1 */ -#define PIO_PA2 (1 << 2) /**< \brief Pin Controlled by PA2 */ -#define PIO_PA3 (1 << 3) /**< \brief Pin Controlled by PA3 */ -#define PIO_PA4 (1 << 4) /**< \brief Pin Controlled by PA4 */ -#define PIO_PA5 (1 << 5) /**< \brief Pin Controlled by PA5 */ -#define PIO_PA6 (1 << 6) /**< \brief Pin Controlled by PA6 */ -#define PIO_PA7 (1 << 7) /**< \brief Pin Controlled by PA7 */ -#define PIO_PA8 (1 << 8) /**< \brief Pin Controlled by PA8 */ -#define PIO_PA9 (1 << 9) /**< \brief Pin Controlled by PA9 */ -#define PIO_PA10 (1 << 10) /**< \brief Pin Controlled by PA10 */ -#define PIO_PA11 (1 << 11) /**< \brief Pin Controlled by PA11 */ -#define PIO_PA12 (1 << 12) /**< \brief Pin Controlled by PA12 */ -#define PIO_PA13 (1 << 13) /**< \brief Pin Controlled by PA13 */ -#define PIO_PA14 (1 << 14) /**< \brief Pin Controlled by PA14 */ -#define PIO_PA15 (1 << 15) /**< \brief Pin Controlled by PA15 */ -#define PIO_PA16 (1 << 16) /**< \brief Pin Controlled by PA16 */ -#define PIO_PA17 (1 << 17) /**< \brief Pin Controlled by PA17 */ -#define PIO_PA18 (1 << 18) /**< \brief Pin Controlled by PA18 */ -#define PIO_PA19 (1 << 19) /**< \brief Pin Controlled by PA19 */ -#define PIO_PA20 (1 << 20) /**< \brief Pin Controlled by PA20 */ -#define PIO_PA21 (1 << 21) /**< \brief Pin Controlled by PA21 */ -#define PIO_PA22 (1 << 22) /**< \brief Pin Controlled by PA22 */ -#define PIO_PA23 (1 << 23) /**< \brief Pin Controlled by PA23 */ -#define PIO_PA24 (1 << 24) /**< \brief Pin Controlled by PA24 */ -#define PIO_PA25 (1 << 25) /**< \brief Pin Controlled by PA25 */ -#define PIO_PA26 (1 << 26) /**< \brief Pin Controlled by PA26 */ -#define PIO_PA27 (1 << 27) /**< \brief Pin Controlled by PA27 */ -#define PIO_PA28 (1 << 28) /**< \brief Pin Controlled by PA28 */ -#define PIO_PA29 (1 << 29) /**< \brief Pin Controlled by PA29 */ -#define PIO_PA30 (1 << 30) /**< \brief Pin Controlled by PA30 */ -#define PIO_PA31 (1 << 31) /**< \brief Pin Controlled by PA31 */ -#define PIO_PB0 (1 << 0) /**< \brief Pin Controlled by PB0 */ -#define PIO_PB1 (1 << 1) /**< \brief Pin Controlled by PB1 */ -#define PIO_PB2 (1 << 2) /**< \brief Pin Controlled by PB2 */ -#define PIO_PB3 (1 << 3) /**< \brief Pin Controlled by PB3 */ -#define PIO_PB4 (1 << 4) /**< \brief Pin Controlled by PB4 */ -#define PIO_PB5 (1 << 5) /**< \brief Pin Controlled by PB5 */ -#define PIO_PB6 (1 << 6) /**< \brief Pin Controlled by PB6 */ -#define PIO_PB7 (1 << 7) /**< \brief Pin Controlled by PB7 */ -#define PIO_PB8 (1 << 8) /**< \brief Pin Controlled by PB8 */ -#define PIO_PB9 (1 << 9) /**< \brief Pin Controlled by PB9 */ -#define PIO_PB10 (1 << 10) /**< \brief Pin Controlled by PB10 */ -#define PIO_PB11 (1 << 11) /**< \brief Pin Controlled by PB11 */ -#define PIO_PB12 (1 << 12) /**< \brief Pin Controlled by PB12 */ -#define PIO_PB13 (1 << 13) /**< \brief Pin Controlled by PB13 */ -#define PIO_PB14 (1 << 14) /**< \brief Pin Controlled by PB14 */ -#define PIO_PC0 (1 << 0) /**< \brief Pin Controlled by PC0 */ -#define PIO_PC1 (1 << 1) /**< \brief Pin Controlled by PC1 */ -#define PIO_PC2 (1 << 2) /**< \brief Pin Controlled by PC2 */ -#define PIO_PC3 (1 << 3) /**< \brief Pin Controlled by PC3 */ -#define PIO_PC4 (1 << 4) /**< \brief Pin Controlled by PC4 */ -#define PIO_PC5 (1 << 5) /**< \brief Pin Controlled by PC5 */ -#define PIO_PC6 (1 << 6) /**< \brief Pin Controlled by PC6 */ -#define PIO_PC7 (1 << 7) /**< \brief Pin Controlled by PC7 */ -#define PIO_PC8 (1 << 8) /**< \brief Pin Controlled by PC8 */ -#define PIO_PC9 (1 << 9) /**< \brief Pin Controlled by PC9 */ -#define PIO_PC10 (1 << 10) /**< \brief Pin Controlled by PC10 */ -#define PIO_PC11 (1 << 11) /**< \brief Pin Controlled by PC11 */ -#define PIO_PC12 (1 << 12) /**< \brief Pin Controlled by PC12 */ -#define PIO_PC13 (1 << 13) /**< \brief Pin Controlled by PC13 */ -#define PIO_PC14 (1 << 14) /**< \brief Pin Controlled by PC14 */ -#define PIO_PC15 (1 << 15) /**< \brief Pin Controlled by PC15 */ -#define PIO_PC16 (1 << 16) /**< \brief Pin Controlled by PC16 */ -#define PIO_PC17 (1 << 17) /**< \brief Pin Controlled by PC17 */ -#define PIO_PC18 (1 << 18) /**< \brief Pin Controlled by PC18 */ -#define PIO_PC19 (1 << 19) /**< \brief Pin Controlled by PC19 */ -#define PIO_PC20 (1 << 20) /**< \brief Pin Controlled by PC20 */ -#define PIO_PC21 (1 << 21) /**< \brief Pin Controlled by PC21 */ -#define PIO_PC22 (1 << 22) /**< \brief Pin Controlled by PC22 */ -#define PIO_PC23 (1 << 23) /**< \brief Pin Controlled by PC23 */ -#define PIO_PC24 (1 << 24) /**< \brief Pin Controlled by PC24 */ -#define PIO_PC25 (1 << 25) /**< \brief Pin Controlled by PC25 */ -#define PIO_PC26 (1 << 26) /**< \brief Pin Controlled by PC26 */ -#define PIO_PC27 (1 << 27) /**< \brief Pin Controlled by PC27 */ -#define PIO_PC28 (1 << 28) /**< \brief Pin Controlled by PC28 */ -#define PIO_PC29 (1 << 29) /**< \brief Pin Controlled by PC29 */ -#define PIO_PC30 (1 << 30) /**< \brief Pin Controlled by PC30 */ -#define PIO_PC31 (1 << 31) /**< \brief Pin Controlled by PC31 */ -/* ========== Pio definition for HSMCI peripheral ========== */ -#define PIO_PA28C_MCCDA (1 << 28) /**< \brief Hsmci signal: MCCDA */ -#define PIO_PA29C_MCCK (1 << 29) /**< \brief Hsmci signal: MCCK */ -#define PIO_PA30C_MCDA0 (1 << 30) /**< \brief Hsmci signal: MCDA0 */ -#define PIO_PA31C_MCDA1 (1 << 31) /**< \brief Hsmci signal: MCDA1 */ -#define PIO_PA26C_MCDA2 (1 << 26) /**< \brief Hsmci signal: MCDA2 */ -#define PIO_PA27C_MCDA3 (1 << 27) /**< \brief Hsmci signal: MCDA3 */ -/* ========== Pio definition for SSC peripheral ========== */ -#define PIO_PA18A_RD (1 << 18) /**< \brief Ssc signal: RD */ -#define PIO_PA20A_RF (1 << 20) /**< \brief Ssc signal: RF */ -#define PIO_PA19A_RK (1 << 19) /**< \brief Ssc signal: RK */ -#define PIO_PA17A_TD (1 << 17) /**< \brief Ssc signal: TD */ -#define PIO_PA15A_TF (1 << 15) /**< \brief Ssc signal: TF */ -#define PIO_PA16A_TK (1 << 16) /**< \brief Ssc signal: TK */ -/* ========== Pio definition for SPI peripheral ========== */ -#define PIO_PA12A_MISO (1 << 12) /**< \brief Spi signal: MISO */ -#define PIO_PA13A_MOSI (1 << 13) /**< \brief Spi signal: MOSI */ -#define PIO_PA11A_NPCS0 (1 << 11) /**< \brief Spi signal: NPCS0 */ -#define PIO_PA31A_NPCS1 (1 << 31) /**< \brief Spi signal: NPCS1 */ -#define PIO_PA9B_NPCS1 (1 << 9) /**< \brief Spi signal: NPCS1 */ -#define PIO_PB14A_NPCS1 (1 << 14) /**< \brief Spi signal: NPCS1 */ -#define PIO_PC4B_NPCS1 (1 << 4) /**< \brief Spi signal: NPCS1 */ -#define PIO_PA10B_NPCS2 (1 << 10) /**< \brief Spi signal: NPCS2 */ -#define PIO_PA30B_NPCS2 (1 << 30) /**< \brief Spi signal: NPCS2 */ -#define PIO_PB2B_NPCS2 (1 << 2) /**< \brief Spi signal: NPCS2 */ -#define PIO_PA22B_NPCS3 (1 << 22) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA3B_NPCS3 (1 << 3) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA5B_NPCS3 (1 << 5) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA14A_SPCK (1 << 14) /**< \brief Spi signal: SPCK */ -/* ========== Pio definition for TC0 peripheral ========== */ -#define PIO_PA4B_TCLK0 (1 << 4) /**< \brief Tc0 signal: TCLK0 */ -#define PIO_PA28B_TCLK1 (1 << 28) /**< \brief Tc0 signal: TCLK1 */ -#define PIO_PA29B_TCLK2 (1 << 29) /**< \brief Tc0 signal: TCLK2 */ -#define PIO_PA0B_TIOA0 (1 << 0) /**< \brief Tc0 signal: TIOA0 */ -#define PIO_PA15B_TIOA1 (1 << 15) /**< \brief Tc0 signal: TIOA1 */ -#define PIO_PA26B_TIOA2 (1 << 26) /**< \brief Tc0 signal: TIOA2 */ -#define PIO_PA1B_TIOB0 (1 << 1) /**< \brief Tc0 signal: TIOB0 */ -#define PIO_PA16B_TIOB1 (1 << 16) /**< \brief Tc0 signal: TIOB1 */ -#define PIO_PA27B_TIOB2 (1 << 27) /**< \brief Tc0 signal: TIOB2 */ -/* ========== Pio definition for TC1 peripheral ========== */ -#define PIO_PC25B_TCLK3 (1 << 25) /**< \brief Tc1 signal: TCLK3 */ -#define PIO_PC28B_TCLK4 (1 << 28) /**< \brief Tc1 signal: TCLK4 */ -#define PIO_PC31B_TCLK5 (1 << 31) /**< \brief Tc1 signal: TCLK5 */ -#define PIO_PC23B_TIOA3 (1 << 23) /**< \brief Tc1 signal: TIOA3 */ -#define PIO_PC26B_TIOA4 (1 << 26) /**< \brief Tc1 signal: TIOA4 */ -#define PIO_PC29B_TIOA5 (1 << 29) /**< \brief Tc1 signal: TIOA5 */ -#define PIO_PC24B_TIOB3 (1 << 24) /**< \brief Tc1 signal: TIOB3 */ -#define PIO_PC27B_TIOB4 (1 << 27) /**< \brief Tc1 signal: TIOB4 */ -#define PIO_PC30B_TIOB5 (1 << 30) /**< \brief Tc1 signal: TIOB5 */ -/* ========== Pio definition for TWI0 peripheral ========== */ -#define PIO_PA4A_TWCK0 (1 << 4) /**< \brief Twi0 signal: TWCK0 */ -#define PIO_PA3A_TWD0 (1 << 3) /**< \brief Twi0 signal: TWD0 */ -/* ========== Pio definition for TWI1 peripheral ========== */ -#define PIO_PB5A_TWCK1 (1 << 5) /**< \brief Twi1 signal: TWCK1 */ -#define PIO_PB4A_TWD1 (1 << 4) /**< \brief Twi1 signal: TWD1 */ -/* ========== Pio definition for PWM peripheral ========== */ -#define PIO_PA9C_PWMFI0 (1 << 9) /**< \brief Pwm signal: PWMFI0 */ -#define PIO_PA0A_PWMH0 (1 << 0) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA11B_PWMH0 (1 << 11) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA23B_PWMH0 (1 << 23) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PB0A_PWMH0 (1 << 0) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PC18B_PWMH0 (1 << 18) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA1A_PWMH1 (1 << 1) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA12B_PWMH1 (1 << 12) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA24B_PWMH1 (1 << 24) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PB1A_PWMH1 (1 << 1) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PC19B_PWMH1 (1 << 19) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA13B_PWMH2 (1 << 13) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA2A_PWMH2 (1 << 2) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA25B_PWMH2 (1 << 25) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PB4B_PWMH2 (1 << 4) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PC20B_PWMH2 (1 << 20) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA14B_PWMH3 (1 << 14) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA17C_PWMH3 (1 << 17) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA7B_PWMH3 (1 << 7) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PB14B_PWMH3 (1 << 14) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC21B_PWMH3 (1 << 21) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA19B_PWML0 (1 << 19) /**< \brief Pwm signal: PWML0 */ -#define PIO_PB5B_PWML0 (1 << 5) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC0B_PWML0 (1 << 0) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC13B_PWML0 (1 << 13) /**< \brief Pwm signal: PWML0 */ -#define PIO_PA20B_PWML1 (1 << 20) /**< \brief Pwm signal: PWML1 */ -#define PIO_PB12A_PWML1 (1 << 12) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC1B_PWML1 (1 << 1) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC15B_PWML1 (1 << 15) /**< \brief Pwm signal: PWML1 */ -#define PIO_PA16C_PWML2 (1 << 16) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA30A_PWML2 (1 << 30) /**< \brief Pwm signal: PWML2 */ -#define PIO_PB13A_PWML2 (1 << 13) /**< \brief Pwm signal: PWML2 */ -#define PIO_PC2B_PWML2 (1 << 2) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA15C_PWML3 (1 << 15) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC22B_PWML3 (1 << 22) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC3B_PWML3 (1 << 3) /**< \brief Pwm signal: PWML3 */ -/* ========== Pio definition for USART0 peripheral ========== */ -#define PIO_PA8A_CTS0 (1 << 8) /**< \brief Usart0 signal: CTS0 */ -#define PIO_PA7A_RTS0 (1 << 7) /**< \brief Usart0 signal: RTS0 */ -#define PIO_PA5A_RXD0 (1 << 5) /**< \brief Usart0 signal: RXD0 */ -#define PIO_PA2B_SCK0 (1 << 2) /**< \brief Usart0 signal: SCK0 */ -#define PIO_PA6A_TXD0 (1 << 6) /**< \brief Usart0 signal: TXD0 */ -/* ========== Pio definition for USART1 peripheral ========== */ -#define PIO_PA25A_CTS1 (1 << 25) /**< \brief Usart1 signal: CTS1 */ -#define PIO_PA26A_DCD1 (1 << 26) /**< \brief Usart1 signal: DCD1 */ -#define PIO_PA28A_DSR1 (1 << 28) /**< \brief Usart1 signal: DSR1 */ -#define PIO_PA27A_DTR1 (1 << 27) /**< \brief Usart1 signal: DTR1 */ -#define PIO_PA29A_RI1 (1 << 29) /**< \brief Usart1 signal: RI1 */ -#define PIO_PA24A_RTS1 (1 << 24) /**< \brief Usart1 signal: RTS1 */ -#define PIO_PA21A_RXD1 (1 << 21) /**< \brief Usart1 signal: RXD1 */ -#define PIO_PA23A_SCK1 (1 << 23) /**< \brief Usart1 signal: SCK1 */ -#define PIO_PA22A_TXD1 (1 << 22) /**< \brief Usart1 signal: TXD1 */ -/* ========== Pio definition for ADC peripheral ========== */ -#define PIO_PA17X1_AD0 (1 << 17) /**< \brief Adc signal: AD0 */ -#define PIO_PA18X1_AD1 (1 << 18) /**< \brief Adc signal: AD1 */ -#define PIO_PC13X1_AD10 (1 << 13) /**< \brief Adc signal: AD10 */ -#define PIO_PC15X1_AD11 (1 << 15) /**< \brief Adc signal: AD11 */ -#define PIO_PC12X1_AD12 (1 << 12) /**< \brief Adc signal: AD12 */ -#define PIO_PC29X1_AD13 (1 << 29) /**< \brief Adc signal: AD13 */ -#define PIO_PC30X1_AD14 (1 << 30) /**< \brief Adc signal: AD14 */ -#define PIO_PA19X1_AD2 (1 << 19) /**< \brief Adc signal: AD2 */ -#define PIO_PA20X1_AD3 (1 << 20) /**< \brief Adc signal: AD3 */ -#define PIO_PB0X1_AD4 (1 << 0) /**< \brief Adc signal: AD4 */ -#define PIO_PB1X1_AD5 (1 << 1) /**< \brief Adc signal: AD5 */ -#define PIO_PB2X1_AD6 (1 << 2) /**< \brief Adc signal: AD6 */ -#define PIO_PB3X1_AD7 (1 << 3) /**< \brief Adc signal: AD7 */ -#define PIO_PA21X1_AD8 (1 << 21) /**< \brief Adc signal: AD8 */ -#define PIO_PA22X1_AD9 (1 << 22) /**< \brief Adc signal: AD9 */ -#define PIO_PA8B_ADTRG (1 << 8) /**< \brief Adc signal: ADTRG */ -/* ========== Pio definition for DACC peripheral ========== */ -#define PIO_PB13X1_DAC0 (1 << 13) /**< \brief Dacc signal: DAC0 */ -#define PIO_PB14X1_DAC1 (1 << 14) /**< \brief Dacc signal: DAC1 */ -#define PIO_PA2C_DATRG (1 << 2) /**< \brief Dacc signal: DATRG */ -/* ========== Pio definition for PMC peripheral ========== */ -#define PIO_PA6B_PCK0 (1 << 6) /**< \brief Pmc signal: PCK0 */ -#define PIO_PB13B_PCK0 (1 << 13) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA17B_PCK1 (1 << 17) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA21B_PCK1 (1 << 21) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA18B_PCK2 (1 << 18) /**< \brief Pmc signal: PCK2 */ -#define PIO_PA31B_PCK2 (1 << 31) /**< \brief Pmc signal: PCK2 */ -#define PIO_PB3B_PCK2 (1 << 3) /**< \brief Pmc signal: PCK2 */ -/* ========== Pio definition for UART0 peripheral ========== */ -#define PIO_PA9A_URXD0 (1 << 9) /**< \brief Uart0 signal: URXD0 */ -#define PIO_PA10A_UTXD0 (1 << 10) /**< \brief Uart0 signal: UTXD0 */ -/* ========== Pio definition for UART1 peripheral ========== */ -#define PIO_PB2A_URXD1 (1 << 2) /**< \brief Uart1 signal: URXD1 */ -#define PIO_PB3A_UTXD1 (1 << 3) /**< \brief Uart1 signal: UTXD1 */ -/* ========== Pio definition for PIOA peripheral ========== */ -#define PIO_PA24X1_PIODC0 (1 << 24) /**< \brief Pioa signal: PIODC0 */ -#define PIO_PA25X1_PIODC1 (1 << 25) /**< \brief Pioa signal: PIODC1 */ -#define PIO_PA26X1_PIODC2 (1 << 26) /**< \brief Pioa signal: PIODC2 */ -#define PIO_PA27X1_PIODC3 (1 << 27) /**< \brief Pioa signal: PIODC3 */ -#define PIO_PA28X1_PIODC4 (1 << 28) /**< \brief Pioa signal: PIODC4 */ -#define PIO_PA29X1_PIODC5 (1 << 29) /**< \brief Pioa signal: PIODC5 */ -#define PIO_PA30X1_PIODC6 (1 << 30) /**< \brief Pioa signal: PIODC6 */ -#define PIO_PA31X1_PIODC7 (1 << 31) /**< \brief Pioa signal: PIODC7 */ -#define PIO_PA23X1_PIODCCLK (1 << 23) /**< \brief Pioa signal: PIODCCLK */ -#define PIO_PA15X1_PIODCEN1 (1 << 15) /**< \brief Pioa signal: PIODCEN1 */ -#define PIO_PA16X1_PIODCEN2 (1 << 16) /**< \brief Pioa signal: PIODCEN2 */ -/*@}*/ - -/* ***************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ - -#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */ -#define AT91C_IFLASH (0x00400000) /**< Internal Flash base address */ -#define AT91C_IROM (0x00800000) /**< Internal ROM base address */ -#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */ -#define AT91C_EBI_CS0 (0x60000000) /**< EBI Chip Select 0 base address */ -#define AT91C_EBI_CS1 (0x61000000) /**< EBI Chip Select 1 base address */ -#define AT91C_EBI_CS2 (0x62000000) /**< EBI Chip Select 2 base address */ -#define AT91C_EBI_CS3 (0x63000000) /**< EBI Chip Select 3 base address */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif // _AT91SAM3S2_H_ diff --git a/radio/src/targets/sky9x/AT91SAM3S4.h b/radio/src/targets/sky9x/AT91SAM3S4.h deleted file mode 100644 index 881274a79..000000000 --- a/radio/src/targets/sky9x/AT91SAM3S4.h +++ /dev/null @@ -1,7153 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Atmel Microcontroller Software Support */ -/* ---------------------------------------------------------------------------- */ -/* Copyright (c) 2009, Atmel Corporation */ -/* */ -/* All rights reserved. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following condition is met: */ -/* */ -/* - Redistributions of source code must retain the above copyright notice, */ -/* this list of conditions and the disclaimer below. */ -/* */ -/* Atmel's name may not be used to endorse or promote products derived from */ -/* this software without specific prior written permission. */ -/* */ -/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ -/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ -/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ -/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ -/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ -/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ -/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ -/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ -/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* ---------------------------------------------------------------------------- */ -/* */ -/* File Name : AT91SAM3S.h */ -/* Object : AT91SAM3S definitions */ -/* Generated by : AT91 SW Application Group */ -/* Generated on : 2009-10-26 */ - -#ifndef _AT91SAM3S4_H_ -#define _AT91SAM3S4_H_ - -/** \addtogroup AT91SAM3S_definitions AT91SAM3S definitions - This file defines all structures and symbols for AT91SAM3S: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __ASSEMBLY__ -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *) value) -#define REG_ACCESS(type, address) (*(type*)address) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ***************************************************************************** */ -/* CMSIS DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_cmsis CMSIS Definitions */ - -/*@{*/ - -/** - * \brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __MPU_PRESENT 0 /**< AT91SAM3S does not provide a MPU present or not */ -#define __NVIC_PRIO_BITS 4 /**< AT91SAM3S uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ - -/**< Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************/ - NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ -/****** AT91SAM3S specific Interrupt Numbers *****************************************/ - - SUPC_IRQn = 0, /**< 0 AT91SAM3S Supply Controller (SUPC) */ - RSTC_IRQn = 1, /**< 1 AT91SAM3S Reset Controller (RSTC) */ - RTC_IRQn = 2, /**< 2 AT91SAM3S Real Time Clock (RTC) */ - RTT_IRQn = 3, /**< 3 AT91SAM3S Real Time Timer (RTT) */ - WDT_IRQn = 4, /**< 4 AT91SAM3S Watchdog Timer (WDT) */ - PMC_IRQn = 5, /**< 5 AT91SAM3S Power Management Controller (PMC) */ - EFC_IRQn = 6, /**< 6 AT91SAM3S Enhanced Flash Controller (EFC) */ - UART0_IRQn = 8, /**< 8 AT91SAM3S UART 0 (UART0) */ - UART1_IRQn = 9, /**< 9 AT91SAM3S UART 1 (UART1) */ - SMC_IRQn = 10, /**< 10 AT91SAM3S Static Memory Controller (SMC) */ - PIOA_IRQn = 11, /**< 11 AT91SAM3S Parallel I/O Controller A (PIOA) */ - PIOB_IRQn = 12, /**< 12 AT91SAM3S Parallel I/O Controller B (PIOB) */ - PIOC_IRQn = 13, /**< 13 AT91SAM3S Parallel I/O Controller C (PIOC) */ - USART0_IRQn = 14, /**< 14 AT91SAM3S USART 0 (USART0) */ - USART1_IRQn = 15, /**< 15 AT91SAM3S USART 1 (USART1) */ - HSMCI_IRQn = 18, /**< 18 AT91SAM3S Multimedia Card Interface (HSMCI) */ - TWI0_IRQn = 19, /**< 19 AT91SAM3S Two Wire Interface 0 (TWI0) */ - TWI1_IRQn = 20, /**< 20 AT91SAM3S Two Wire Interface 1 (TWI1) */ - SPI_IRQn = 21, /**< 21 AT91SAM3S Serial Peripheral Interface (SPI) */ - SSC_IRQn = 22, /**< 22 AT91SAM3S Synchronous Serial Controler (SSC) */ - TC0_IRQn = 23, /**< 23 AT91SAM3S Timer/Counter 0 (TC0) */ - TC1_IRQn = 24, /**< 24 AT91SAM3S Timer/Counter 1 (TC1) */ - TC2_IRQn = 25, /**< 25 AT91SAM3S Timer/Counter 2 (TC2) */ - TC3_IRQn = 26, /**< 26 AT91SAM3S Timer/Counter 3 (TC3) */ - TC4_IRQn = 27, /**< 27 AT91SAM3S Timer/Counter 4 (TC4) */ - TC5_IRQn = 28, /**< 28 AT91SAM3S Timer/Counter 5 (TC5) */ - ADC_IRQn = 29, /**< 29 AT91SAM3S Analog To Digital Converter (ADC) */ - DACC_IRQn = 30, /**< 30 AT91SAM3S Digital To Analog Converter (DACC) */ - PWM_IRQn = 31, /**< 31 AT91SAM3S Pulse Width Modulation (PWM) */ - CRCCU_IRQn = 32, /**< 32 AT91SAM3S CRC Calculation Unit (CRCCU) */ - ACC_IRQn = 33, /**< 33 AT91SAM3S Analog Comparator (ACC) */ - UDP_IRQn = 34 /**< 34 AT91SAM3S USB Device Port (UDP) */ -} IRQn_Type; -/*@}*/ - -/* ***************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_api Peripheral Software API */ -/*@{*/ -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_ACC Analog Comparator Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Acc hardware registers */ -typedef struct { - WoReg ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */ - RwReg ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */ - RwReg Reserved1[7]; - WoReg ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */ - WoReg ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */ - RoReg ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */ - RoReg ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */ - RwReg Reserved2[24]; - RwReg ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */ - RwReg Reserved3[19]; - RwReg ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protect Mode Register */ - RoReg ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protect Status Register */ -} Acc; -#endif /* __ASSEMBLY__ */ -/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */ -#define ACC_CR_SWRST (0x1 << 0) /**< \brief (ACC_CR) SoftWare ReSeT */ -/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */ -#define ACC_MR_SELPLUS (0x7 << 0) /**< \brief (ACC_MR) SELection for PLUS comparator input */ -#define ACC_MR_SELMINUS (0x7 << 4) /**< \brief (ACC_MR) SELection for MINUS comparator input */ -#define ACC_MR_ACEN (0x1 << 8) /**< \brief (ACC_MR) Analog Comparator ENable */ -#define ACC_MR_ACEN_EN (0x1 << 8) /**< \brief (ACC_MR) Analog Comparator ENable */ -#define ACC_MR_ACEN_DIS (0x0 << 8) /**< \brief (ACC_MR) Analog Comparator Disable */ -#define ACC_MR_EDGETYP (0x3 << 9) /**< \brief (ACC_MR) EDGE TYPe */ -#define ACC_MR_EDGETYP_RISING (0x0 << 9) /**< \brief (ACC_MR) EDGE TYPe ,RISING edge*/ -#define ACC_MR_EDGETYP_FALLING (0x1 << 9) /**< \brief (ACC_MR) EDGE TYPe,falling edge */ -#define ACC_MR_EDGETYP_ANY (0x2 << 9) /**< \brief (ACC_MR) EDGE TYPe,any edge */ -#define ACC_MR_INV (0x1 << 12) /**< \brief (ACC_MR) INVert comparator output */ -#define ACC_MR_INV_EN (0x1 << 12) /**< \brief (ACC_MR) INVert comparator output */ -#define ACC_MR_INV_DIS (0x0 << 12) /**< \brief (ACC_MR) DIRECTLY */ -#define ACC_MR_SELFS (0x1 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ -#define ACC_MR_SELFS_CF (0x0 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ -#define ACC_MR_SELFS_OUTPUT (0x1 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ -#define ACC_MR_FE (0x1 << 14) /**< \brief (ACC_MR) Fault Enable */ -#define ACC_MR_FE_EN (0x1 << 14) /**< \brief (ACC_MR) Fault Enable */ -#define ACC_MR_FE_DIS (0x0 << 14) /**< \brief (ACC_MR) Fault Enable */ -/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */ -#define ACC_IER_CE (0x1 << 0) /**< \brief (ACC_IER) Comparison Edge */ -/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */ -#define ACC_IDR_CE (0x1 << 0) /**< \brief (ACC_IDR) Comparison Edge */ -/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */ -#define ACC_IMR_CE (0x1 << 0) /**< \brief (ACC_IMR) Comparison Edge */ -/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */ -#define ACC_ISR_CE (0x1 << 0) /**< \brief (ACC_ISR) Comparison Edge */ -#define ACC_ISR_SCO (0x1 << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */ -#define ACC_ISR_MASK (0x1 << 31) /**< \brief (ACC_ISR) */ -/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */ -#define ACC_ACR_ISEL (0x1 << 0) /**< \brief (ACC_ACR) Current SELection */ -#define ACC_ACR_HYST (0x3 << 1) /**< \brief (ACC_ACR) HYSTeresis selection */ -/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protect Mode Register -------- */ -#define ACC_WPMR_WPEN (0x1 << 0) /**< \brief (ACC_WPMR) Write Protect Enable */ -#define ACC_WPMR_WPKEY (0xffffff << 8) /**< \brief (ACC_WPMR) Write Protect KEY */ -/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protect Status Register -------- */ -#define ACC_WPSR_WPROTERR (0x1 << 0) /**< \brief (ACC_WPSR) Write PROTection ERRor */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Analog-to-digital Converter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_ADC Analog-to-digital Converter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Adc hardware registers */ -typedef struct { - WoReg ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */ - RwReg ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */ - RwReg ADC_SEQR1; /**< \brief (Adc Offset: 0x08) Channel Sequence 1Register */ - RwReg ADC_SEQR2; /**< \brief (Adc Offset: 0x0C) Channel Sequence 2 Register */ - WoReg ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */ - WoReg ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */ - RoReg ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */ - RwReg Reserved1[1]; - RoReg ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */ - WoReg ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */ - WoReg ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */ - RoReg ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */ - RoReg ADC_ISR; /**< \brief (Adc Offset: 0x30) Interrupt Status Register */ - RwReg Reserved2[2]; - RoReg ADC_OVER; /**< \brief (Adc Offset: 0x3C) Overrun Status Register */ - RwReg ADC_EMR; /**< \brief (Adc Offset: 0x40) Extended Mode Register */ - RwReg ADC_CWR; /**< \brief (Adc Offset: 0x44) Compare Window Register */ - RwReg ADC_CGR; /**< \brief (Adc Offset: 0x48) Channel Gain Register */ - RwReg ADC_COR; /**< \brief (Adc Offset: 0x4C) Channel Offset Register */ - RoReg ADC_CDR0; /**< \brief (Adc Offset: 0x50) Channel Data Register 0 */ - RoReg ADC_CDR1; /**< \brief (Adc Offset: 0x54) Channel Data Register 1 */ - RoReg ADC_CDR2; /**< \brief (Adc Offset: 0x58) Channel Data Register 2 */ - RoReg ADC_CDR3; /**< \brief (Adc Offset: 0x5C) Channel Data Register 3 */ - RoReg ADC_CDR4; /**< \brief (Adc Offset: 0x60) Channel Data Register 4 */ - RoReg ADC_CDR5; /**< \brief (Adc Offset: 0x64) Channel Data Register 5 */ - RoReg ADC_CDR6; /**< \brief (Adc Offset: 0x68) Channel Data Register 6 */ - RoReg ADC_CDR7; /**< \brief (Adc Offset: 0x6C) Channel Data Register 7 */ - RoReg ADC_CDR8; /**< \brief (Adc Offset: 0x70) Channel Data Register 8 */ - RoReg ADC_CDR9; /**< \brief (Adc Offset: 0x74) Channel Data Register 9 */ - RoReg ADC_CDR10; /**< \brief (Adc Offset: 0x78) Channel Data Register 10 */ - RoReg ADC_CDR11; /**< \brief (Adc Offset: 0x7C) Channel Data Register 11 */ - RoReg ADC_CDR12; /**< \brief (Adc Offset: 0x80) Channel Data Register 12 */ - RoReg ADC_CDR13; /**< \brief (Adc Offset: 0x84) Channel Data Register 13 */ - RoReg ADC_CDR14; /**< \brief (Adc Offset: 0x88) Channel Data Register 14 */ - RoReg ADC_CDR15; /**< \brief (Adc Offset: 0x8C) Channel Data Register 15 */ - RwReg Reserved3[1]; - RwReg ADC_ACR; /**< \brief (Adc Offset: 0x94) Analog Control Register */ - RwReg Reserved4[19]; - RwReg ADC_WPMR; /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */ - RoReg ADC_WPSR; /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */ - RwReg Reserved5[5]; - RwReg ADC_RPR; /**< \brief (Adc Offset: 0x100) Receive Pointer Register */ - RwReg ADC_RCR; /**< \brief (Adc Offset: 0x104) Receive Counter Register */ - RwReg ADC_TPR; /**< \brief (Adc Offset: 0x108) Transmit Pointer Register */ - RwReg ADC_TCR; /**< \brief (Adc Offset: 0x10C) Transmit Counter Register */ - RwReg ADC_RNPR; /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */ - RwReg ADC_RNCR; /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */ - RwReg ADC_TNPR; /**< \brief (Adc Offset: 0x118) Transmit Next Pointer Register */ - RwReg ADC_TNCR; /**< \brief (Adc Offset: 0x11C) Transmit Next Counter Register */ - WoReg ADC_PTCR; /**< \brief (Adc Offset: 0x120) Transfer Control Register */ - RoReg ADC_PTSR; /**< \brief (Adc Offset: 0x124) Transfer Status Register */ -} Adc; -#endif /* __ASSEMBLY__ */ -/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */ -#define ADC_CR_SWRST (0x1 << 0) /**< \brief (ADC_CR) Software Reset */ -#define ADC_CR_START (0x1 << 1) /**< \brief (ADC_CR) Start Conversion */ -/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */ -#define ADC_MR_TRGEN (0x1 << 0) /**< \brief (ADC_MR) Trigger Enable */ -#define ADC_MR_TRGEN_DIS (0x0 << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software.*/ -#define ADC_MR_TRGEN_EN (0x1) /**< (ADC) Hardware trigger selected by TRGSEL field is enabled.*/ -#define ADC_MR_TRGSEL (0x7 << 1) /**< \brief (ADC_MR) Trigger Selection */ -#define ADC_MR_TRGSEL_EXT (0x0 << 1) /**< \brief (ADC_MR) Selected TRGSEL = External Trigger*/ -#define ADC_MR_TRGSEL_TIOA0 (0x1 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO0*/ -#define ADC_MR_TRGSEL_TIOA1 (0x2 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO1*/ -#define ADC_MR_TRGSEL_TIOA2 (0x3 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO2*/ -#define ADC_MR_TRGSEL_PWM0_TRIG (0x4 << 1) /**< \brief (ADC_MR) Selected TRGSEL = PWM trigger*/ -#define ADC_MR_TRGSEL_PWM1_TRIG (0x5 << 1) /**< \brief (ADC_MR) Selected TRGSEL = PWM Trigger*/ -#define ADC_MR_TRGSEL_RESERVED (0x6 << 1) /**< \brief (ADC_MR) Selected TRGSEL = Reserved*/ -#define ADC_MR_LOWRES (0x1 << 4) /**< \brief (ADC_MR) Resolution */ -#define ADC_MR_LOWRES_12_BIT (0x0 << 4) /**< \brief (ADC_MR) 12-bit resolution*/ -#define ADC_MR_LOWRES_10_BIT (0x1 << 4) /**< \brief (ADC_MR) 10-bit resolution*/ -#define ADC_MR_SLEEP (0x1 << 5) /**< \brief (ADC_MR) Sleep Mode */ -#define ADC_MR_SLEEP_NORMAL (0x0 << 5) /**< \brief (ADC12B) Normal Mode*/ -#define ADC_MR_FWUP (0x1 << 6) /**< \brief (ADC_MR) Fast Wake Up */ -#define ADC_MR_FREERUN (0x1 << 7) /**< \brief (ADC_MR) Free Run Mode */ -#define ADC_MR_PRESCAL (0xff << 8) /**< \brief (ADC_MR) Prescaler Rate Selection */ -#define ADC_MR_STARTUP (0xf << 16) /**< \brief (ADC_MR) Start Up Time */ -#define ADC_MR_SETTLING (0x3 << 20) /**< \brief (ADC_MR) Analog Settling Time */ -#define ADC_MR_ANACH (0x1 << 23) /**< \brief (ADC_MR) Analog Change */ -#define ADC_MR_TRACKTIM (0xf << 24) /**< \brief (ADC_MR) Tracking Time */ -#define ADC_MR_TRANSFER (0x3 << 28) /**< \brief (ADC_MR) */ -#define ADC_MR_USEQ (0x1 << 31) /**< \brief (ADC_MR) User Sequence Enable */ -/* -------- ADC_SEQ1R : (ADC Offset: 0x08) Channel Sequence 1Register -------- */ -#define ADC_SEQ1R_USCH1 (0x7 << 0) /**< \brief (ADC_SEQ1R) User Sequence Number 1 */ -#define ADC_SEQ1R_USCH2 (0x7 << 4) /**< \brief (ADC_SEQ1R) User Sequence Number 2 */ -#define ADC_SEQ1R_USCH3 (0x7 << 8) /**< \brief (ADC_SEQ1R) User Sequence Number 3 */ -#define ADC_SEQ1R_USCH4 (0x7 << 12) /**< \brief (ADC_SEQ1R) User Sequence Number 4 */ -#define ADC_SEQ1R_USCH5 (0x7 << 16) /**< \brief (ADC_SEQ1R) User Sequence Number 5 */ -#define ADC_SEQ1R_USCH6 (0x7 << 20) /**< \brief (ADC_SEQ1R) User Sequence Number 6 */ -#define ADC_SEQ1R_USCH7 (0x7 << 24) /**< \brief (ADC_SEQ1R) User Sequence Number 7 */ -#define ADC_SEQ1R_USCH8 (0x7 << 28) /**< \brief (ADC_SEQ1R) User Sequence Number 8 */ -/* -------- ADC_SEQ2R : (ADC Offset: 0x0C) Channel Sequence 2 Register -------- */ -#define ADC_SEQ2R_USCH9 (0x7 << 0) /**< \brief (ADC_SEQ2R) User Sequence Number 9 */ -#define ADC_SEQ2R_USCH10 (0x7 << 4) /**< \brief (ADC_SEQ2R) User Sequence Number 10 */ -#define ADC_SEQ2R_USCH11 (0x7 << 8) /**< \brief (ADC_SEQ2R) User Sequence Number 11 */ -#define ADC_SEQ2R_USCH12 (0x7 << 12) /**< \brief (ADC_SEQ2R) User Sequence Number 12 */ -#define ADC_SEQ2R_USCH13 (0x7 << 16) /**< \brief (ADC_SEQ2R) User Sequence Number 13 */ -#define ADC_SEQ2R_USCH14 (0x7 << 20) /**< \brief (ADC_SEQ2R) User Sequence Number 14 */ -#define ADC_SEQ2R_USCH15 (0x7 << 24) /**< \brief (ADC_SEQ2R) User Sequence Number 15 */ -#define ADC_SEQ2R_USCH16 (0x7 << 28) /**< \brief (ADC_SEQ2R) User Sequence Number 16 */ -/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */ -#define ADC_CHER_CH0 (0x1 << 0) /**< \brief (ADC_CHER) Channel 0 Enable */ -#define ADC_CHER_CH1 (0x1 << 1) /**< \brief (ADC_CHER) Channel 1 Enable */ -#define ADC_CHER_CH2 (0x1 << 2) /**< \brief (ADC_CHER) Channel 2 Enable */ -#define ADC_CHER_CH3 (0x1 << 3) /**< \brief (ADC_CHER) Channel 3 Enable */ -#define ADC_CHER_CH4 (0x1 << 4) /**< \brief (ADC_CHER) Channel 4 Enable */ -#define ADC_CHER_CH5 (0x1 << 5) /**< \brief (ADC_CHER) Channel 5 Enable */ -#define ADC_CHER_CH6 (0x1 << 6) /**< \brief (ADC_CHER) Channel 6 Enable */ -#define ADC_CHER_CH7 (0x1 << 7) /**< \brief (ADC_CHER) Channel 7 Enable */ -#define ADC_CHER_CH8 (0x1 << 8) /**< \brief (ADC_CHER) Channel 8 Enable */ -#define ADC_CHER_CH9 (0x1 << 9) /**< \brief (ADC_CHER) Channel 9 Enable */ -#define ADC_CHER_CH10 (0x1 << 10) /**< \brief (ADC_CHER) Channel 10 Enable */ -#define ADC_CHER_CH11 (0x1 << 11) /**< \brief (ADC_CHER) Channel 11 Enable */ -#define ADC_CHER_CH12 (0x1 << 12) /**< \brief (ADC_CHER) Channel 12 Enable */ -#define ADC_CHER_CH13 (0x1 << 13) /**< \brief (ADC_CHER) Channel 13 Enable */ -#define ADC_CHER_CH14 (0x1 << 14) /**< \brief (ADC_CHER) Channel 14 Enable */ -#define ADC_CHER_CH15 (0x1 << 15) /**< \brief (ADC_CHER) Channel 15 Enable */ -/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */ -#define ADC_CHDR_CH0 (0x1 << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */ -#define ADC_CHDR_CH1 (0x1 << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */ -#define ADC_CHDR_CH2 (0x1 << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */ -#define ADC_CHDR_CH3 (0x1 << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */ -#define ADC_CHDR_CH4 (0x1 << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */ -#define ADC_CHDR_CH5 (0x1 << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */ -#define ADC_CHDR_CH6 (0x1 << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */ -#define ADC_CHDR_CH7 (0x1 << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */ -#define ADC_CHDR_CH8 (0x1 << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */ -#define ADC_CHDR_CH9 (0x1 << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */ -#define ADC_CHDR_CH10 (0x1 << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */ -#define ADC_CHDR_CH11 (0x1 << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */ -#define ADC_CHDR_CH12 (0x1 << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */ -#define ADC_CHDR_CH13 (0x1 << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */ -#define ADC_CHDR_CH14 (0x1 << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */ -#define ADC_CHDR_CH15 (0x1 << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */ -/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */ -#define ADC_CHSR_CH0 (0x1 << 0) /**< \brief (ADC_CHSR) Channel 0 Status */ -#define ADC_CHSR_CH1 (0x1 << 1) /**< \brief (ADC_CHSR) Channel 1 Status */ -#define ADC_CHSR_CH2 (0x1 << 2) /**< \brief (ADC_CHSR) Channel 2 Status */ -#define ADC_CHSR_CH3 (0x1 << 3) /**< \brief (ADC_CHSR) Channel 3 Status */ -#define ADC_CHSR_CH4 (0x1 << 4) /**< \brief (ADC_CHSR) Channel 4 Status */ -#define ADC_CHSR_CH5 (0x1 << 5) /**< \brief (ADC_CHSR) Channel 5 Status */ -#define ADC_CHSR_CH6 (0x1 << 6) /**< \brief (ADC_CHSR) Channel 6 Status */ -#define ADC_CHSR_CH7 (0x1 << 7) /**< \brief (ADC_CHSR) Channel 7 Status */ -#define ADC_CHSR_CH8 (0x1 << 8) /**< \brief (ADC_CHSR) Channel 8 Status */ -#define ADC_CHSR_CH9 (0x1 << 9) /**< \brief (ADC_CHSR) Channel 9 Status */ -#define ADC_CHSR_CH10 (0x1 << 10) /**< \brief (ADC_CHSR) Channel 10 Status */ -#define ADC_CHSR_CH11 (0x1 << 11) /**< \brief (ADC_CHSR) Channel 11 Status */ -#define ADC_CHSR_CH12 (0x1 << 12) /**< \brief (ADC_CHSR) Channel 12 Status */ -#define ADC_CHSR_CH13 (0x1 << 13) /**< \brief (ADC_CHSR) Channel 13 Status */ -#define ADC_CHSR_CH14 (0x1 << 14) /**< \brief (ADC_CHSR) Channel 14 Status */ -#define ADC_CHSR_CH15 (0x1 << 15) /**< \brief (ADC_CHSR) Channel 15 Status */ -/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */ -#define ADC_LCDR_LDATA (0xfff << 0) /**< \brief (ADC_LCDR) Last Data Converted */ -#define ADC_LCDR_CHNB (0xf << 12) /**< \brief (ADC_LCDR) Channel Number */ -/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */ -#define ADC_IER_EOC0 (0x1 << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */ -#define ADC_IER_EOC1 (0x1 << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */ -#define ADC_IER_EOC2 (0x1 << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */ -#define ADC_IER_EOC3 (0x1 << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */ -#define ADC_IER_EOC4 (0x1 << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */ -#define ADC_IER_EOC5 (0x1 << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */ -#define ADC_IER_EOC6 (0x1 << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */ -#define ADC_IER_EOC7 (0x1 << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */ -#define ADC_IER_EOC8 (0x1 << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */ -#define ADC_IER_EOC9 (0x1 << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */ -#define ADC_IER_EOC10 (0x1 << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */ -#define ADC_IER_EOC11 (0x1 << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */ -#define ADC_IER_EOC12 (0x1 << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */ -#define ADC_IER_EOC13 (0x1 << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */ -#define ADC_IER_EOC14 (0x1 << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */ -#define ADC_IER_EOC15 (0x1 << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */ -#define ADC_IER_DRDY (0x1 << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */ -#define ADC_IER_GOVRE (0x1 << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */ -#define ADC_IER_COMPE (0x1 << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */ -#define ADC_IER_ENDRX (0x1 << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */ -#define ADC_IER_RXBUFF (0x1 << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */ -/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */ -#define ADC_IDR_EOC0 (0x1 << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */ -#define ADC_IDR_EOC1 (0x1 << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */ -#define ADC_IDR_EOC2 (0x1 << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */ -#define ADC_IDR_EOC3 (0x1 << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */ -#define ADC_IDR_EOC4 (0x1 << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */ -#define ADC_IDR_EOC5 (0x1 << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */ -#define ADC_IDR_EOC6 (0x1 << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */ -#define ADC_IDR_EOC7 (0x1 << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */ -#define ADC_IDR_EOC8 (0x1 << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */ -#define ADC_IDR_EOC9 (0x1 << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */ -#define ADC_IDR_EOC10 (0x1 << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */ -#define ADC_IDR_EOC11 (0x1 << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */ -#define ADC_IDR_EOC12 (0x1 << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */ -#define ADC_IDR_EOC13 (0x1 << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */ -#define ADC_IDR_EOC14 (0x1 << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */ -#define ADC_IDR_EOC15 (0x1 << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */ -#define ADC_IDR_DRDY (0x1 << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */ -#define ADC_IDR_GOVRE (0x1 << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */ -#define ADC_IDR_COMPE (0x1 << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */ -#define ADC_IDR_ENDRX (0x1 << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */ -#define ADC_IDR_RXBUFF (0x1 << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */ -/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */ -#define ADC_IMR_EOC0 (0x1 << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */ -#define ADC_IMR_EOC1 (0x1 << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */ -#define ADC_IMR_EOC2 (0x1 << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */ -#define ADC_IMR_EOC3 (0x1 << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */ -#define ADC_IMR_EOC4 (0x1 << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */ -#define ADC_IMR_EOC5 (0x1 << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */ -#define ADC_IMR_EOC6 (0x1 << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */ -#define ADC_IMR_EOC7 (0x1 << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */ -#define ADC_IMR_EOC8 (0x1 << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */ -#define ADC_IMR_EOC9 (0x1 << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */ -#define ADC_IMR_EOC10 (0x1 << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */ -#define ADC_IMR_EOC11 (0x1 << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */ -#define ADC_IMR_EOC12 (0x1 << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */ -#define ADC_IMR_EOC13 (0x1 << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */ -#define ADC_IMR_EOC14 (0x1 << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */ -#define ADC_IMR_EOC15 (0x1 << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */ -#define ADC_IMR_DRDY (0x1 << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */ -#define ADC_IMR_GOVRE (0x1 << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */ -#define ADC_IMR_COMPE (0x1 << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */ -#define ADC_IMR_ENDRX (0x1 << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */ -#define ADC_IMR_RXBUFF (0x1 << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */ -/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */ -#define ADC_ISR_EOC0 (0x1 << 0) /**< \brief (ADC_ISR) End of Conversion 0 */ -#define ADC_ISR_EOC1 (0x1 << 1) /**< \brief (ADC_ISR) End of Conversion 1 */ -#define ADC_ISR_EOC2 (0x1 << 2) /**< \brief (ADC_ISR) End of Conversion 2 */ -#define ADC_ISR_EOC3 (0x1 << 3) /**< \brief (ADC_ISR) End of Conversion 3 */ -#define ADC_ISR_EOC4 (0x1 << 4) /**< \brief (ADC_ISR) End of Conversion 4 */ -#define ADC_ISR_EOC5 (0x1 << 5) /**< \brief (ADC_ISR) End of Conversion 5 */ -#define ADC_ISR_EOC6 (0x1 << 6) /**< \brief (ADC_ISR) End of Conversion 6 */ -#define ADC_ISR_EOC7 (0x1 << 7) /**< \brief (ADC_ISR) End of Conversion 7 */ -#define ADC_ISR_EOC8 (0x1 << 8) /**< \brief (ADC_ISR) End of Conversion 8 */ -#define ADC_ISR_EOC9 (0x1 << 9) /**< \brief (ADC_ISR) End of Conversion 9 */ -#define ADC_ISR_EOC10 (0x1 << 10) /**< \brief (ADC_ISR) End of Conversion 10 */ -#define ADC_ISR_EOC11 (0x1 << 11) /**< \brief (ADC_ISR) End of Conversion 11 */ -#define ADC_ISR_EOC12 (0x1 << 12) /**< \brief (ADC_ISR) End of Conversion 12 */ -#define ADC_ISR_EOC13 (0x1 << 13) /**< \brief (ADC_ISR) End of Conversion 13 */ -#define ADC_ISR_EOC14 (0x1 << 14) /**< \brief (ADC_ISR) End of Conversion 14 */ -#define ADC_ISR_EOC15 (0x1 << 15) /**< \brief (ADC_ISR) End of Conversion 15 */ -#define ADC_ISR_DRDY (0x1 << 24) /**< \brief (ADC_ISR) Data Ready */ -#define ADC_ISR_GOVRE (0x1 << 25) /**< \brief (ADC_ISR) General Overrun Error */ -#define ADC_ISR_COMPE (0x1 << 26) /**< \brief (ADC_ISR) Comparison Error */ -#define ADC_ISR_ENDRX (0x1 << 27) /**< \brief (ADC_ISR) End of RX Buffer */ -#define ADC_ISR_RXBUFF (0x1 << 28) /**< \brief (ADC_ISR) RX Buffer Full */ -/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */ -#define ADC_OVER_OVRE0 (0x1 << 0) /**< \brief (ADC_OVER) Overrun Error 0 */ -#define ADC_OVER_OVRE1 (0x1 << 1) /**< \brief (ADC_OVER) Overrun Error 1 */ -#define ADC_OVER_OVRE2 (0x1 << 2) /**< \brief (ADC_OVER) Overrun Error 2 */ -#define ADC_OVER_OVRE3 (0x1 << 3) /**< \brief (ADC_OVER) Overrun Error 3 */ -#define ADC_OVER_OVRE4 (0x1 << 4) /**< \brief (ADC_OVER) Overrun Error 4 */ -#define ADC_OVER_OVRE5 (0x1 << 5) /**< \brief (ADC_OVER) Overrun Error 5 */ -#define ADC_OVER_OVRE6 (0x1 << 6) /**< \brief (ADC_OVER) Overrun Error 6 */ -#define ADC_OVER_OVRE7 (0x1 << 7) /**< \brief (ADC_OVER) Overrun Error 7 */ -#define ADC_OVER_OVRE8 (0x1 << 8) /**< \brief (ADC_OVER) Overrun Error 8 */ -#define ADC_OVER_OVRE9 (0x1 << 9) /**< \brief (ADC_OVER) Overrun Error 9 */ -#define ADC_OVER_OVRE10 (0x1 << 10) /**< \brief (ADC_OVER) Overrun Error 10 */ -#define ADC_OVER_OVRE11 (0x1 << 11) /**< \brief (ADC_OVER) Overrun Error 11 */ -#define ADC_OVER_OVRE12 (0x1 << 12) /**< \brief (ADC_OVER) Overrun Error 12 */ -#define ADC_OVER_OVRE13 (0x1 << 13) /**< \brief (ADC_OVER) Overrun Error 13 */ -#define ADC_OVER_OVRE14 (0x1 << 14) /**< \brief (ADC_OVER) Overrun Error 14 */ -#define ADC_OVER_OVRE15 (0x1 << 15) /**< \brief (ADC_OVER) Overrun Error 15 */ -/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */ -#define ADC_EMR_CMPMODE (0x3 << 0) /**< \brief (ADC_EMR) Comparison Mode */ -#define ADC_EMR_CMPMODE_LOW (0x0 << 0) /**< \brief (ADC_EMR) Comparison Mode,lower than low threshold */ -#define ADC_EMR_CMPMODE_HIGH (0x1 << 0) /**< \brief (ADC_EMR) Comparison Mode,higher than high threshold */ -#define ADC_EMR_CMPMODE_IN (0x2 << 0) /**< \brief (ADC_EMR) Comparison Mode, in the comparison window */ -#define ADC_EMR_CMPMODE_OUT (0x3 << 0) /**< \brief (ADC_EMR) Comparison Mode, out of the comparison window */ -#define ADC_EMR_CMPSEL (0xf << 4) /**< \brief (ADC_EMR) Comparison Selected Channel */ -#define ADC_EMR_CMPALL (0x1 << 9) /**< \brief (ADC_EMR) Compare All Channels */ -#define ADC_EMR_TAG (0x1 << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */ -/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */ -#define ADC_CWR_LOWTHRES (0xfff << 0) /**< \brief (ADC_CWR) Low Threshold */ -#define ADC_CWR_HIGHTHRES (0xfff << 16) /**< \brief (ADC_CWR) High Threshold */ -/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */ -#define ADC_CGR_GAIN0 (0x3 << 0) /**< \brief (ADC_CGR) Gain for channel 0 */ -#define ADC_CGR_GAIN1 (0x3 << 2) /**< \brief (ADC_CGR) Gain for channel 1 */ -#define ADC_CGR_GAIN2 (0x3 << 4) /**< \brief (ADC_CGR) Gain for channel 2 */ -#define ADC_CGR_GAIN3 (0x3 << 6) /**< \brief (ADC_CGR) Gain for channel 3 */ -#define ADC_CGR_GAIN4 (0x3 << 8) /**< \brief (ADC_CGR) Gain for channel 4 */ -#define ADC_CGR_GAIN5 (0x3 << 10) /**< \brief (ADC_CGR) Gain for channel 5 */ -#define ADC_CGR_GAIN6 (0x3 << 12) /**< \brief (ADC_CGR) Gain for channel 6 */ -#define ADC_CGR_GAIN7 (0x3 << 14) /**< \brief (ADC_CGR) Gain for channel 7 */ -#define ADC_CGR_GAIN8 (0x3 << 16) /**< \brief (ADC_CGR) Gain for channel 8 */ -#define ADC_CGR_GAIN9 (0x3 << 18) /**< \brief (ADC_CGR) Gain for channel 9 */ -#define ADC_CGR_GAIN10 (0x3 << 20) /**< \brief (ADC_CGR) Gain for channel 10 */ -#define ADC_CGR_GAIN11 (0x3 << 22) /**< \brief (ADC_CGR) Gain for channel 11 */ -#define ADC_CGR_GAIN12 (0x3 << 24) /**< \brief (ADC_CGR) Gain for channel 12 */ -#define ADC_CGR_GAIN13 (0x3 << 26) /**< \brief (ADC_CGR) Gain for channel 13 */ -#define ADC_CGR_GAIN14 (0x3 << 28) /**< \brief (ADC_CGR) Gain for channel 14 */ -#define ADC_CGR_GAIN15 (0x3 << 30) /**< \brief (ADC_CGR) Gain for channel 15 */ -/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */ -#define ADC_COR_OFF0 (0x1 << 0) /**< \brief (ADC_COR) Offset for channel 0 */ -#define ADC_COR_OFF1 (0x1 << 1) /**< \brief (ADC_COR) Offset for channel 1 */ -#define ADC_COR_OFF2 (0x1 << 2) /**< \brief (ADC_COR) Offset for channel 2 */ -#define ADC_COR_OFF3 (0x1 << 3) /**< \brief (ADC_COR) Offset for channel 3 */ -#define ADC_COR_OFF4 (0x1 << 4) /**< \brief (ADC_COR) Offset for channel 4 */ -#define ADC_COR_OFF5 (0x1 << 5) /**< \brief (ADC_COR) Offset for channel 5 */ -#define ADC_COR_OFF6 (0x1 << 6) /**< \brief (ADC_COR) Offset for channel 6 */ -#define ADC_COR_OFF7 (0x1 << 7) /**< \brief (ADC_COR) Offset for channel 7 */ -#define ADC_COR_OFF8 (0x1 << 8) /**< \brief (ADC_COR) Offset for channel 8 */ -#define ADC_COR_OFF9 (0x1 << 9) /**< \brief (ADC_COR) Offset for channel 9 */ -#define ADC_COR_OFF10 (0x1 << 10) /**< \brief (ADC_COR) Offset for channel 10 */ -#define ADC_COR_OFF11 (0x1 << 11) /**< \brief (ADC_COR) Offset for channel 11 */ -#define ADC_COR_OFF12 (0x1 << 12) /**< \brief (ADC_COR) Offset for channel 12 */ -#define ADC_COR_OFF13 (0x1 << 13) /**< \brief (ADC_COR) Offset for channel 13 */ -#define ADC_COR_OFF14 (0x1 << 14) /**< \brief (ADC_COR) Offset for channel 14 */ -#define ADC_COR_OFF15 (0x1 << 15) /**< \brief (ADC_COR) Offset for channel 15 */ -#define ADC_COR_DIFF0 (0x1 << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */ -#define ADC_COR_DIFF1 (0x1 << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */ -#define ADC_COR_DIFF2 (0x1 << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */ -#define ADC_COR_DIFF3 (0x1 << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */ -#define ADC_COR_DIFF4 (0x1 << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */ -#define ADC_COR_DIFF5 (0x1 << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */ -#define ADC_COR_DIFF6 (0x1 << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */ -#define ADC_COR_DIFF7 (0x1 << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */ -#define ADC_COR_DIFF8 (0x1 << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */ -#define ADC_COR_DIFF9 (0x1 << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */ -#define ADC_COR_DIFF10 (0x1 << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */ -#define ADC_COR_DIFF11 (0x1 << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */ -#define ADC_COR_DIFF12 (0x1 << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */ -#define ADC_COR_DIFF13 (0x1 << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */ -#define ADC_COR_DIFF14 (0x1 << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */ -#define ADC_COR_DIFF15 (0x1 << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */ -/* -------- ADC_CDR0 : (ADC Offset: 0x50) Channel Data Register 0 -------- */ -#define ADC_CDR0_DATA (0x3ff << 0) /**< \brief (ADC_CDR0) Converted Data */ -/* -------- ADC_CDR1 : (ADC Offset: 0x54) Channel Data Register 1 -------- */ -#define ADC_CDR1_DATA (0x3ff << 0) /**< \brief (ADC_CDR1) Converted Data */ -/* -------- ADC_CDR2 : (ADC Offset: 0x58) Channel Data Register 2 -------- */ -#define ADC_CDR2_DATA (0x3ff << 0) /**< \brief (ADC_CDR2) Converted Data */ -/* -------- ADC_CDR3 : (ADC Offset: 0x5C) Channel Data Register 3 -------- */ -#define ADC_CDR3_DATA (0x3ff << 0) /**< \brief (ADC_CDR3) Converted Data */ -/* -------- ADC_CDR4 : (ADC Offset: 0x60) Channel Data Register 4 -------- */ -#define ADC_CDR4_DATA (0x3ff << 0) /**< \brief (ADC_CDR4) Converted Data */ -/* -------- ADC_CDR5 : (ADC Offset: 0x64) Channel Data Register 5 -------- */ -#define ADC_CDR5_DATA (0x3ff << 0) /**< \brief (ADC_CDR5) Converted Data */ -/* -------- ADC_CDR6 : (ADC Offset: 0x68) Channel Data Register 6 -------- */ -#define ADC_CDR6_DATA (0x3ff << 0) /**< \brief (ADC_CDR6) Converted Data */ -/* -------- ADC_CDR15 : (ADC Offset: 0x6C) Channel Data Register 15 -------- */ -#define ADC_CDR15_DATA (0x3ff << 0) /**< \brief (ADC_CDR15) Converted Data */ -/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */ -#define ADC_ACR_TSON (0x1 << 4) /**< \brief (ADC_ACR) Temperature Sensor On */ -#define ADC_ACR_IBCTL (0x3 << 8) /**< \brief (ADC_ACR) ADC Bias Current Control */ -/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */ -#define ADC_WPMR_WPEN (0x1 << 0) /**< \brief (ADC_WPMR) Write Protect Enable */ -#define ADC_WPMR_WPKEY (0xffffff << 8) /**< \brief (ADC_WPMR) Write Protect KEY */ -/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */ -#define ADC_WPSR_WPVS (0x1 << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */ -#define ADC_WPSR_WPVSRC (0xffff << 8) /**< \brief (ADC_WPSR) Write Protect Violation Source */ -/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */ -#define ADC_RPR_RXPTR (0xffffffff << 0) /**< \brief (ADC_RPR) Receive Pointer Register */ -/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */ -#define ADC_RCR_RXCTR (0xffff << 0) /**< \brief (ADC_RCR) Receive Counter Register */ -/* -------- ADC_TPR : (ADC Offset: 0x108) Transmit Pointer Register -------- */ -#define ADC_TPR_TXPTR (0xffffffff << 0) /**< \brief (ADC_TPR) Transmit Counter Register */ -/* -------- ADC_TCR : (ADC Offset: 0x10C) Transmit Counter Register -------- */ -#define ADC_TCR_TXCTR (0xffff << 0) /**< \brief (ADC_TCR) Transmit Counter Register */ -/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */ -#define ADC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (ADC_RNPR) Receive Next Pointer */ -/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */ -#define ADC_RNCR_RXNCTR (0xffff << 0) /**< \brief (ADC_RNCR) Receive Next Counter */ -/* -------- ADC_TNPR : (ADC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define ADC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (ADC_TNPR) Transmit Next Pointer */ -/* -------- ADC_TNCR : (ADC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define ADC_TNCR_TXNCTR (0xffff << 0) /**< \brief (ADC_TNCR) Transmit Counter Next */ -/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */ -#define ADC_PTCR_RXTEN (0x1 << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */ -#define ADC_PTCR_RXTDIS (0x1 << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */ -#define ADC_PTCR_TXTEN (0x1 << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */ -#define ADC_PTCR_TXTDIS (0x1 << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */ -/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */ -#define ADC_PTSR_RXTEN (0x1 << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */ -#define ADC_PTSR_TXTEN (0x1 << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Chip Identifier */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_CHIPID Chip Identifier */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Chipid hardware registers */ -typedef struct { - RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ - RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ -} Chipid; -#endif /* __ASSEMBLY__ */ -/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ -#define CHIPID_CIDR_VERSION (0x1f << 0) /**< \brief (CHIPID_CIDR) Version of the Device */ -#define CHIPID_CIDR_EPROC (0x7 << 5) /**< \brief (CHIPID_CIDR) Embedded Processor */ -#define CHIPID_CIDR_NVPSIZ (0xf << 8) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ -#define CHIPID_CIDR_NVPSIZ2 (0xf << 12) /**< \brief (CHIPID_CIDR) */ -#define CHIPID_CIDR_SRAMSIZ (0xf << 16) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ -#define CHIPID_CIDR_ARCH (0xff << 20) /**< \brief (CHIPID_CIDR) Architecture Identifier */ -#define CHIPID_CIDR_NVPTYP (0x7 << 28) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ -#define CHIPID_CIDR_EXT (0x1 << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ -/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ -#define CHIPID_EXID_EXID (0xffffffff << 0) /**< \brief (CHIPID_EXID) Chip ID Extension */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_CRCCU Cyclic Redundancy Check Calculation Unit */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Crccu hardware registers */ -typedef struct { - RwReg CRCCU_DSCR; /**< \brief (Crccu Offset: 0x00000000) CRCCU Descriptor Base Register */ - RwReg Reserved1[1]; - WoReg CRCCU_DMA_EN; /**< \brief (Crccu Offset: 0x00000008) CRCCU DMA Enable Register */ - WoReg CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x0000000C) CRCCU DMA Disable Register */ - RoReg CRCCU_DMA_SR; /**< \brief (Crccu Offset: 0x00000010) CRCCU DMA Status Register */ - WoReg CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x00000014) CRCCU DMA Interrupt Enable Register */ - WoReg CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x00000018) CRCCU DMA Interrupt Disable Register */ - RoReg CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register */ - RoReg CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x00000020) CRCCU DMA Interrupt Status Register */ - RwReg Reserved2[4]; - WoReg CRCCU_CR; /**< \brief (Crccu Offset: 0x00000034) CRCCU Control Register */ - RwReg CRCCU_MR; /**< \brief (Crccu Offset: 0x00000038) CRCCU Mode Register */ - RoReg CRCCU_SR; /**< \brief (Crccu Offset: 0x0000003C) CRCCU Status Register */ - WoReg CRCCU_IER; /**< \brief (Crccu Offset: 0x00000040) CRCCU Interrupt Enable Register */ - WoReg CRCCU_IDR; /**< \brief (Crccu Offset: 0x00000044) CRCCU Interrupt Disable Register */ - RoReg CRCCU_IMR; /**< \brief (Crccu Offset: 0x00000048) CRCCU Interrupt Mask Register */ - RoReg CRCCU_ISR; /**< \brief (Crccu Offset: 0x0000004C) CRCCU Interrupt Status Register */ -} Crccu; -#endif /* __ASSEMBLY__ */ -/* -------- CRCCU_DSCR : (CRCCU Offset: 0x00000000) CRCCU Descriptor Base Register -------- */ -#define CRCCU_DSCR_DSCR (0x7fffff << 9) /**< \brief (CRCCU_DSCR) Descriptor Base Address */ -/* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x00000008) CRCCU DMA Enable Register -------- */ -#define CRCCU_DMA_EN_DMAEN (0x1 << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable Register */ -/* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x0000000C) CRCCU DMA Disable Register -------- */ -#define CRCCU_DMA_DIS_DMADIS (0x1 << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable Register */ -/* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x00000010) CRCCU DMA Status Register -------- */ -#define CRCCU_DMA_SR_DMASR (0x1 << 0) /**< \brief (CRCCU_DMA_SR) DMA Status Register */ -/* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x00000014) CRCCU DMA Interrupt Enable Register -------- */ -#define CRCCU_DMA_IER_DMAIER (0x1 << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable register */ -/* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x00000018) CRCCU DMA Interrupt Disable Register -------- */ -#define CRCCU_DMA_IDR_DMAIDR (0x1 << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable register */ -/* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register -------- */ -#define CRCCU_DMA_IMR_DMAIMR (0x1 << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask Register */ -/* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x00000020) CRCCU DMA Interrupt Status Register -------- */ -#define CRCCU_DMA_ISR_DMAISR (0x1 << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status register */ -/* -------- CRCCU_CR : (CRCCU Offset: 0x00000034) CRCCU Control Register -------- */ -#define CRCCU_CR_RESET (0x1 << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */ -/* -------- CRCCU_MR : (CRCCU Offset: 0x00000038) CRCCU Mode Register -------- */ -#define CRCCU_MR_ENABLE (0x1 << 0) /**< \brief (CRCCU_MR) CRC Enable */ -#define CRCCU_MR_COMPARE (0x1 << 1) /**< \brief (CRCCU_MR) CRC Compare */ -#define CRCCU_MR_PTYPE (0x3 << 2) /**< \brief (CRCCU_MR) Primitive Polynomial */ -#define CRCCU_MR_PTYPE_CCIT8023 (0x0 << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */ -#define CRCCU_MR_PTYPE_CASTAGNOLI (0x1 << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */ -#define CRCCU_MR_PTYPE_CCIT16 (0x2 << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */ -#define CRCCU_MR_DIVIDER (0xf << 4) /**< \brief (CRCCU_MR) Request Divider */ -/* -------- CRCCU_SR : (CRCCU Offset: 0x0000003C) CRCCU Status Register -------- */ -#define CRCCU_SR_CRC (0xffffffff << 0) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */ -/* -------- CRCCU_IER : (CRCCU Offset: 0x00000040) CRCCU Interrupt Enable Register -------- */ -#define CRCCU_IER_ERRIER (0x1 << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */ -/* -------- CRCCU_IDR : (CRCCU Offset: 0x00000044) CRCCU Interrupt Disable Register -------- */ -#define CRCCU_IDR_ERRIDR (0x1 << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */ -/* -------- CRCCU_IMR : (CRCCU Offset: 0x00000048) CRCCU Interrupt Mask Register -------- */ -#define CRCCU_IMR_ERRIMR (0x1 << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */ -/* -------- CRCCU_ISR : (CRCCU Offset: 0x0000004C) CRCCU Interrupt Status Register -------- */ -#define CRCCU_ISR_ERRISR (0x1 << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_DACC Digital-to-Analog Converter Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Dacc hardware registers */ -typedef struct { - WoReg DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ - RwReg DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ - RwReg Reserved1[2]; - WoReg DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ - WoReg DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ - RoReg DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ - RwReg Reserved2[1]; - WoReg DACC_CDR; /**< \brief (Dacc Offset: 0x20) Conversion Data Register */ - WoReg DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ - WoReg DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ - RoReg DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ - RoReg DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ - RwReg Reserved3[24]; - RwReg DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ - RwReg Reserved4[19]; - RwReg DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */ - RoReg DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */ - RwReg Reserved5[5]; - RwReg DACC_RPR; /**< \brief (Dacc Offset: 0x100) Receive Pointer Register */ - RwReg DACC_RCR; /**< \brief (Dacc Offset: 0x104) Receive Counter Register */ - RwReg DACC_TPR; /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */ - RwReg DACC_TCR; /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */ - RwReg DACC_RNPR; /**< \brief (Dacc Offset: 0x110) Receive Next Pointer Register */ - RwReg DACC_RNCR; /**< \brief (Dacc Offset: 0x114) Receive Next Counter Register */ - RwReg DACC_TNPR; /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */ - RwReg DACC_TNCR; /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */ - WoReg DACC_PTCR; /**< \brief (Dacc Offset: 0x120) Transfer Control Register */ - RoReg DACC_PTSR; /**< \brief (Dacc Offset: 0x124) Transfer Status Register */ -} Dacc; -#endif /* __ASSEMBLY__ */ -/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ -#define DACC_CR_SWRST (0x1 << 0) /**< \brief (DACC_CR) Software Reset */ -/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ -#define DACC_MR_TRGEN (0x1 << 0) /**< \brief (DACC_MR) Trigger Enable */ -#define DACC_MR_TRGEN_DIS (0x0 << 0) // (DACC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. -#define DACC_MR_TRGEN_EN (0x1 << 0) // (DACC_MR) Hardware trigger selected by TRGSEL field is enabled. - -#define DACC_MR_TRGSEL (0x7 << 1) /**< \brief (DACC_MR) Trigger Selection */ -#define DACC_MR_TRGSEL_EXT_TRIG (0x0 << 1) // (DACC_MR) External trigger -#define DACC_MR_TRGSEL_TIOA_0 (0x1 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 0 -#define DACC_MR_TRGSEL_TIOA_1 (0x2 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 1 -#define DACC_MR_TRGSEL_TIOA_2 (0x3 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 2 -#define DACC_MR_TRGSEL_PWM_0 (0x4 << 1) // (DACC_MR) PWM Event Line 0 -#define DACC_MR_TRGSEL_PWM_1 (0x5 << 1) // (DACC_MR) PWM Event Line 1 -#define DACC_MR_WORD (0x1 << 4) /**< \brief (DACC_MR) Word Transfer */ -#define DACC_MR_WORD_HALF (0x0 << 4) /**< \brief (DACC_MR) Half-Word Transfer */ -#define DACC_MR_WORD_WORLD (0x1 << 4) /**< \brief (DACC_MR) Word Transfer */ -#define DACC_MR_SLEEP (0x1 << 5) /**< \brief (DACC_MR) Sleep Mode */ -#define DACC_MR_SLEEP_NORMAL (0x0 << 5) // (DACC_MR) Normal Mode -#define DACC_MR_SLEEP_SLEEP (0x1 << 5) // (DACC_MR) Sleep Modes -#define DACC_MR_FASTWKUP (0x1 << 6) /**< \brief (DACC_MR) Fast Wake up Mode */ -#define DACC_MR_REFRESH (0xff << 8) /**< \brief (DACC_MR) Refresh Period */ -#define DACC_MR_USER_SEL (0x3 << 16) /**< \brief (DACC_MR) User Channel Selection */ -#define DACC_MR_USER_SEL_0 (0x0 << 16) /**< \brief (DACC_MR) User Channel Selection */ -#define DACC_MR_USER_SEL_1 (0x1 << 16) /**< \brief (DACC_MR) User Channel Selection */ -#define DACC_MR_TAG (0x1 << 20) /**< \brief (DACC_MR) Tag Selection Mode */ -#define DACC_MR_MAXS (0x1 << 21) /**< \brief (DACC_MR) Max Speed Mode */ -#define DACC_MR_STARTUP (0x3f << 24) /**< \brief (DACC_MR) Startup Time Selection */ -/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ -#define DACC_CHER_CH0 (0x1 << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ -#define DACC_CHER_CH1 (0x1 << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ -#define DACC_CHER_CH2 (0x1 << 2) /**< \brief (DACC_CHER) Channel 2 Enable */ -/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ -#define DACC_CHDR_CH0 (0x1 << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ -#define DACC_CHDR_CH1 (0x1 << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ -#define DACC_CHDR_CH2 (0x1 << 2) /**< \brief (DACC_CHDR) Channel 2 Disable */ -/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ -#define DACC_CHSR_CH0 (0x1 << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ -#define DACC_CHSR_CH1 (0x1 << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ -#define DACC_CHSR_CH2 (0x1 << 2) /**< \brief (DACC_CHSR) Channel 2 Status */ -/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */ -#define DACC_CDR_DATA (0xffffffff << 0) /**< \brief (DACC_CDR) Data to Convert */ -/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ -#define DACC_IER_TXRDY (0x1 << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */ -#define DACC_IER_EOC (0x1 << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */ -#define DACC_IER_ENDTX (0x1 << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */ -#define DACC_IER_TXBUFE (0x1 << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */ -/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ -#define DACC_IDR_TXRDY (0x1 << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */ -#define DACC_IDR_EOC (0x1 << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */ -#define DACC_IDR_ENDTX (0x1 << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */ -#define DACC_IDR_TXBUFE (0x1 << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */ -/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ -#define DACC_IMR_TXRDY (0x1 << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */ -#define DACC_IMR_EOC (0x1 << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */ -#define DACC_IMR_ENDTX (0x1 << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */ -#define DACC_IMR_TXBUFE (0x1 << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */ -/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ -#define DACC_ISR_TXRDY (0x1 << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */ -#define DACC_ISR_EOC (0x1 << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */ -#define DACC_ISR_ENDTX (0x1 << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */ -#define DACC_ISR_TXBUFE (0x1 << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */ -/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ -#define DACC_ACR_IBCTLCH0 (0x3 << 0) /**< \brief (DACC_ACR) Analog Output Current Control */ -#define DACC_ACR_IBCTLCH1 (0x3 << 2) /**< \brief (DACC_ACR) Analog Output Current Control */ -#define DACC_ACR_IBCTLDACCORE (0x3 << 8) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */ -/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */ -#define DACC_WPMR_WPEN (0x1 << 0) /**< \brief (DACC_WPMR) Write Protect Enable */ -#define DACC_WPMR_WPKEY (0xffffff << 8) /**< \brief (DACC_WPMR) Write Protect KEY */ -/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */ -#define DACC_WPSR_WPROTERR (0x1 << 0) /**< \brief (DACC_WPSR) Write protection error */ -#define DACC_WPSR_WPROTADDR (0xff << 8) /**< \brief (DACC_WPSR) Write protection error address */ -/* -------- DACC_RPR : (DACC Offset: 0x100) Receive Pointer Register -------- */ -#define DACC_RPR_RXPTR (0xffffffff << 0) /**< \brief (DACC_RPR) Receive Pointer Register */ -/* -------- DACC_RCR : (DACC Offset: 0x104) Receive Counter Register -------- */ -#define DACC_RCR_RXCTR (0xffff << 0) /**< \brief (DACC_RCR) Receive Counter Register */ -/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */ -#define DACC_TPR_TXPTR (0xffffffff << 0) /**< \brief (DACC_TPR) Transmit Counter Register */ -/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */ -#define DACC_TCR_TXCTR (0xffff << 0) /**< \brief (DACC_TCR) Transmit Counter Register */ -/* -------- DACC_RNPR : (DACC Offset: 0x110) Receive Next Pointer Register -------- */ -#define DACC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (DACC_RNPR) Receive Next Pointer */ -/* -------- DACC_RNCR : (DACC Offset: 0x114) Receive Next Counter Register -------- */ -#define DACC_RNCR_RXNCTR (0xffff << 0) /**< \brief (DACC_RNCR) Receive Next Counter */ -/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define DACC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (DACC_TNPR) Transmit Next Pointer */ -/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define DACC_TNCR_TXNCTR (0xffff << 0) /**< \brief (DACC_TNCR) Transmit Counter Next */ -/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */ -#define DACC_PTCR_RXTEN (0x1 << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */ -#define DACC_PTCR_RXTDIS (0x1 << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */ -#define DACC_PTCR_TXTEN (0x1 << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */ -#define DACC_PTCR_TXTDIS (0x1 << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */ -/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */ -#define DACC_PTSR_RXTEN (0x1 << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */ -#define DACC_PTSR_TXTEN (0x1 << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_EFC Embedded Flash Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Efc hardware registers */ -typedef struct { - RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ - WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ - RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ - RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ -} Efc; -#endif /* __ASSEMBLY__ */ -/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ -#define EEFC_FMR_FRDY (0x1 << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */ -#define EEFC_FMR_FWS (0xf << 8) /**< \brief (EEFC_FMR) Flash Wait State */ -#define EEFC_FMR_FAM (0x1 << 24) /**< \brief (EEFC_FMR) Flash Access Mode */ -/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ -#define EEFC_FCR_FCMD (0xff << 0) /**< \brief (EEFC_FCR) Flash Command */ -#define EEFC_FCR_FARG (0xffff << 8) /**< \brief (EEFC_FCR) Flash Command Argument */ -#define EEFC_FCR_FKEY (0xff << 24) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ -/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ -#define EEFC_FSR_FRDY (0x1 << 0) /**< \brief (EEFC_FSR) Flash Ready Status */ -#define EEFC_FSR_FCMDE (0x1 << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */ -#define EEFC_FSR_FLOCKE (0x1 << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */ -/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ -#define EEFC_FRR_FVALUE (0xffffffff << 0) /**< \brief (EEFC_FRR) Flash Result Value */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_GPBR General Purpose Backup Register */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Gpbr hardware registers */ -typedef struct { - RwReg SYS_GPBR0; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register 0 */ - RwReg SYS_GPBR1; /**< \brief (Gpbr Offset: 0x4) General Purpose Backup Register 1 */ - RwReg SYS_GPBR2; /**< \brief (Gpbr Offset: 0x8) General Purpose Backup Register 2 */ - RwReg SYS_GPBR3; /**< \brief (Gpbr Offset: 0xC) General Purpose Backup Register 3 */ -} Gpbr; -#endif /* __ASSEMBLY__ */ -/* -------- SYS_GPBR0 : (GPBR Offset: 0x0) General Purpose Backup Register 0 -------- */ -#define SYS_GPBR0_GPBR_VALUE0 (0xffffffff << 0) /**< \brief (SYS_GPBR0) Value of GPBR x */ -/* -------- SYS_GPBR1 : (GPBR Offset: 0x4) General Purpose Backup Register 1 -------- */ -#define SYS_GPBR1_GPBR_VALUE1 (0xffffffff << 0) /**< \brief (SYS_GPBR1) Value of GPBR x */ -/* -------- SYS_GPBR2 : (GPBR Offset: 0x8) General Purpose Backup Register 2 -------- */ -#define SYS_GPBR2_GPBR_VALUE2 (0xffffffff << 0) /**< \brief (SYS_GPBR2) Value of GPBR x */ -/* -------- SYS_GPBR3 : (GPBR Offset: 0xC) General Purpose Backup Register 3 -------- */ -#define SYS_GPBR3_GPBR_VALUE3 (0xffffffff << 0) /**< \brief (SYS_GPBR3) Value of GPBR x */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_HSMCI High Speed MultiMedia Card Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Hsmci hardware registers */ -typedef struct { - WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ - RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ - RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ - RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ - RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ - WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ - RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ - RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ - RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ - RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ - WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ - RwReg Reserved1[2]; - RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ - WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ - WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ - RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ - RwReg Reserved2[1]; - RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ - RwReg Reserved3[35]; - RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ - RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ - RwReg Reserved4[5]; - RwReg HSMCI_RPR; /**< \brief (Hsmci Offset: 0x100) Receive Pointer Register */ - RwReg HSMCI_RCR; /**< \brief (Hsmci Offset: 0x104) Receive Counter Register */ - RwReg HSMCI_TPR; /**< \brief (Hsmci Offset: 0x108) Transmit Pointer Register */ - RwReg HSMCI_TCR; /**< \brief (Hsmci Offset: 0x10C) Transmit Counter Register */ - RwReg HSMCI_RNPR; /**< \brief (Hsmci Offset: 0x110) Receive Next Pointer Register */ - RwReg HSMCI_RNCR; /**< \brief (Hsmci Offset: 0x114) Receive Next Counter Register */ - RwReg HSMCI_TNPR; /**< \brief (Hsmci Offset: 0x118) Transmit Next Pointer Register */ - RwReg HSMCI_TNCR; /**< \brief (Hsmci Offset: 0x11C) Transmit Next Counter Register */ - WoReg HSMCI_PTCR; /**< \brief (Hsmci Offset: 0x120) Transfer Control Register */ - RoReg HSMCI_PTSR; /**< \brief (Hsmci Offset: 0x124) Transfer Status Register */ -} Hsmci; -#endif /* __ASSEMBLY__ */ -/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ -#define HSMCI_CR_MCIEN (0x1 << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ -#define HSMCI_CR_MCIDIS (0x1 << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ -#define HSMCI_CR_PWSEN (0x1 << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ -#define HSMCI_CR_PWSDIS (0x1 << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ -#define HSMCI_CR_SWRST (0x1 << 7) /**< \brief (HSMCI_CR) Software Reset */ -/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ -#define HSMCI_MR_CLKDIV_Pos 0 -#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */ -#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos))) -#define HSMCI_MR_PWSDIV_Pos 8 -#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */ -#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos))) -#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) */ -#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) */ -#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ -#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ -#define HSMCI_MR_PDCMODE (0x1u << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */ -#define HSMCI_MR_BLKLEN_Pos 16 -#define HSMCI_MR_BLKLEN_Msk (0xffffu << HSMCI_MR_BLKLEN_Pos) /**< \brief (HSMCI_MR) Data Block Length */ -#define HSMCI_MR_BLKLEN(value) ((HSMCI_MR_BLKLEN_Msk & ((value) << HSMCI_MR_BLKLEN_Pos))) -/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ -#define HSMCI_DTOR_DTOCYC_Pos 0 -#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ -#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos))) -#define HSMCI_DTOR_DTOMUL_Pos 4 -#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ -#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */ -#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */ -#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */ -#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */ -#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */ -#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */ -#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */ -#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */ -/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ -#define HSMCI_SDCR_SDCSEL_Pos 0 -#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ -#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */ -#define HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) - */ -#define HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */ -#define HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */ -#define HSMCI_SDCR_SDCBUS_Pos 6 -#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ -#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */ -#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */ -#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */ -/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ -#define HSMCI_ARGR_ARG (0xffffffff << 0) /**< \brief (HSMCI_ARGR) Command Argument */ -/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ -#define HSMCI_CMDR_CMDNB_Pos 0 -#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */ -#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos))) -#define HSMCI_CMDR_RSPTYP_Pos 6 -#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */ -#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */ -#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */ -#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */ -#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */ -#define HSMCI_CMDR_SPCMD_Pos 8 -#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */ -#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */ -#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD:74 clock cycles for initialization sequence. */ -#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD:Wait for the end of the current data block transfer before sending the pending command. */ -#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command.The host cancels the ability for the device to return a command completion signal on the command line. */ -#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command:Corresponds to the Interrupt Mode (CMD40). */ -#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response:Corresponds to the Interrupt Mode (CMD40). */ -#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request.Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ -#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation.This command allows the host processor to terminate the boot operation mode. */ -#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ -#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */ -#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */ -#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ -#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */ -#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */ -#define HSMCI_CMDR_TRCMD_Pos 16 -#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */ -#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */ -#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */ -#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */ -#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ -#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */ -#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */ -#define HSMCI_CMDR_TRTYP_Pos 19 -#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */ -#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */ -#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */ -#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */ -#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */ -#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */ -#define HSMCI_CMDR_IOSPCMD_Pos 24 -#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */ -#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */ -#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */ -#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */ -#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ -#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */ -#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ -#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */ -/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ -#define HSMCI_BLKR_BCNT_Pos 0 -#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ -#define HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */ -#define HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */ -#define HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */ -#define HSMCI_BLKR_BLKLEN_Pos 16 -#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */ -#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos))) -/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ -#define HSMCI_CSTOR_CSTOCYC_Pos 0 -#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ -#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos))) -#define HSMCI_CSTOR_CSTOMUL_Pos 4 -#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ -#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */ -#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */ -#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */ -#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */ -#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */ -#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */ -#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */ -#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */ -/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ -#define HSMCI_RSPR_RSP (0xffffffff << 0) /**< \brief (HSMCI_RSPR[4]) Response */ -/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ -#define HSMCI_RDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_RDR) Data to Read */ -/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ -#define HSMCI_TDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_TDR) Data to Write */ -/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ -#define HSMCI_SR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_SR) Command Ready */ -#define HSMCI_SR_RXRDY (0x1 << 1) /**< \brief (HSMCI_SR) Receiver Ready */ -#define HSMCI_SR_TXRDY (0x1 << 2) /**< \brief (HSMCI_SR) Transmit Ready */ -#define HSMCI_SR_BLKE (0x1 << 3) /**< \brief (HSMCI_SR) Data Block Ended */ -#define HSMCI_SR_DTIP (0x1 << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */ -#define HSMCI_SR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ -#define HSMCI_SR_ENDRX (0x1 << 6) /**< \brief (HSMCI_SR) End of RX Buffer */ -#define HSMCI_SR_ENDTX (0x1 << 7) /**< \brief (HSMCI_SR) End of TX Buffer */ -#define HSMCI_SR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */ -#define HSMCI_SR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ -#define HSMCI_SR_CSRCV (0x1 << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */ -#define HSMCI_SR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_SR) RX Buffer Full */ -#define HSMCI_SR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_SR) TX Buffer Empty */ -#define HSMCI_SR_RINDE (0x1 << 16) /**< \brief (HSMCI_SR) Response Index Error */ -#define HSMCI_SR_RDIRE (0x1 << 17) /**< \brief (HSMCI_SR) Response Direction Error */ -#define HSMCI_SR_RCRCE (0x1 << 18) /**< \brief (HSMCI_SR) Response CRC Error */ -#define HSMCI_SR_RENDE (0x1 << 19) /**< \brief (HSMCI_SR) Response End Bit Error */ -#define HSMCI_SR_RTOE (0x1 << 20) /**< \brief (HSMCI_SR) Response Time-out Error */ -#define HSMCI_SR_DCRCE (0x1 << 21) /**< \brief (HSMCI_SR) Data CRC Error */ -#define HSMCI_SR_DTOE (0x1 << 22) /**< \brief (HSMCI_SR) Data Time-out Error */ -#define HSMCI_SR_CSTOE (0x1 << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */ -#define HSMCI_SR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ -#define HSMCI_SR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ -#define HSMCI_SR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */ -#define HSMCI_SR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */ -#define HSMCI_SR_OVRE (0x1 << 30) /**< \brief (HSMCI_SR) Overrun */ -#define HSMCI_SR_UNRE (0x1 << 31) /**< \brief (HSMCI_SR) Underrun */ -/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ -#define HSMCI_IER_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ -#define HSMCI_IER_RXRDY (0x1 << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ -#define HSMCI_IER_TXRDY (0x1 << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ -#define HSMCI_IER_BLKE (0x1 << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ -#define HSMCI_IER_DTIP (0x1 << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ -#define HSMCI_IER_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ -#define HSMCI_IER_ENDRX (0x1 << 6) /**< \brief (HSMCI_IER) End of Receive Buffer Interrupt Enable */ -#define HSMCI_IER_ENDTX (0x1 << 7) /**< \brief (HSMCI_IER) End of Transmit Buffer Interrupt Enable */ -#define HSMCI_IER_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */ -#define HSMCI_IER_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ -#define HSMCI_IER_CSRCV (0x1 << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ -#define HSMCI_IER_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IER) Receive Buffer Full Interrupt Enable */ -#define HSMCI_IER_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IER) Transmit Buffer Empty Interrupt Enable */ -#define HSMCI_IER_RINDE (0x1 << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ -#define HSMCI_IER_RDIRE (0x1 << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ -#define HSMCI_IER_RCRCE (0x1 << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ -#define HSMCI_IER_RENDE (0x1 << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ -#define HSMCI_IER_RTOE (0x1 << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ -#define HSMCI_IER_DCRCE (0x1 << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ -#define HSMCI_IER_DTOE (0x1 << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ -#define HSMCI_IER_CSTOE (0x1 << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ -#define HSMCI_IER_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ -#define HSMCI_IER_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ -#define HSMCI_IER_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ -#define HSMCI_IER_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ -#define HSMCI_IER_OVRE (0x1 << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ -#define HSMCI_IER_UNRE (0x1 << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ -/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ -#define HSMCI_IDR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ -#define HSMCI_IDR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ -#define HSMCI_IDR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ -#define HSMCI_IDR_BLKE (0x1 << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ -#define HSMCI_IDR_DTIP (0x1 << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ -#define HSMCI_IDR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ -#define HSMCI_IDR_ENDRX (0x1 << 6) /**< \brief (HSMCI_IDR) End of Receive Buffer Interrupt Disable */ -#define HSMCI_IDR_ENDTX (0x1 << 7) /**< \brief (HSMCI_IDR) End of Transmit Buffer Interrupt Disable */ -#define HSMCI_IDR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */ -#define HSMCI_IDR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ -#define HSMCI_IDR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ -#define HSMCI_IDR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IDR) Receive Buffer Full Interrupt Disable */ -#define HSMCI_IDR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IDR) Transmit Buffer Empty Interrupt Disable */ -#define HSMCI_IDR_RINDE (0x1 << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ -#define HSMCI_IDR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ -#define HSMCI_IDR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ -#define HSMCI_IDR_RENDE (0x1 << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ -#define HSMCI_IDR_RTOE (0x1 << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ -#define HSMCI_IDR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ -#define HSMCI_IDR_DTOE (0x1 << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ -#define HSMCI_IDR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ -#define HSMCI_IDR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ -#define HSMCI_IDR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ -#define HSMCI_IDR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ -#define HSMCI_IDR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ -#define HSMCI_IDR_OVRE (0x1 << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ -#define HSMCI_IDR_UNRE (0x1 << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ -/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ -#define HSMCI_IMR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ -#define HSMCI_IMR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ -#define HSMCI_IMR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ -#define HSMCI_IMR_BLKE (0x1 << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ -#define HSMCI_IMR_DTIP (0x1 << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ -#define HSMCI_IMR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ -#define HSMCI_IMR_ENDRX (0x1 << 6) /**< \brief (HSMCI_IMR) End of Receive Buffer Interrupt Mask */ -#define HSMCI_IMR_ENDTX (0x1 << 7) /**< \brief (HSMCI_IMR) End of Transmit Buffer Interrupt Mask */ -#define HSMCI_IMR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */ -#define HSMCI_IMR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ -#define HSMCI_IMR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ -#define HSMCI_IMR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IMR) Receive Buffer Full Interrupt Mask */ -#define HSMCI_IMR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IMR) Transmit Buffer Empty Interrupt Mask */ -#define HSMCI_IMR_RINDE (0x1 << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ -#define HSMCI_IMR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ -#define HSMCI_IMR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ -#define HSMCI_IMR_RENDE (0x1 << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ -#define HSMCI_IMR_RTOE (0x1 << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ -#define HSMCI_IMR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ -#define HSMCI_IMR_DTOE (0x1 << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ -#define HSMCI_IMR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ -#define HSMCI_IMR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ -#define HSMCI_IMR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ -#define HSMCI_IMR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ -#define HSMCI_IMR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ -#define HSMCI_IMR_OVRE (0x1 << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ -#define HSMCI_IMR_UNRE (0x1 << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ -/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ -#define HSMCI_CFG_FIFOMODE (0x1 << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ -#define HSMCI_CFG_FERRCTRL (0x1 << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ -#define HSMCI_CFG_HSMODE (0x1 << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ -#define HSMCI_CFG_LSYNC (0x1 << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ -/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ -#define HSMCI_WPMR_WP_EN (0x1 << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */ -#define HSMCI_WPMR_WP_KEY (0xffffff << 8) /**< \brief (HSMCI_WPMR) Write Protection Key password */ -/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ -#define HSMCI_WPSR_WP_VS (0xf << 0) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ -#define HSMCI_WPSR_WP_VSRC (0xffff << 8) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */ -/* -------- HSMCI_RPR : (HSMCI Offset: 0x100) Receive Pointer Register -------- */ -#define HSMCI_RPR_RXPTR (0xffffffff << 0) /**< \brief (HSMCI_RPR) Receive Pointer Register */ -/* -------- HSMCI_RCR : (HSMCI Offset: 0x104) Receive Counter Register -------- */ -#define HSMCI_RCR_RXCTR (0xffff << 0) /**< \brief (HSMCI_RCR) Receive Counter Register */ -/* -------- HSMCI_TPR : (HSMCI Offset: 0x108) Transmit Pointer Register -------- */ -#define HSMCI_TPR_TXPTR (0xffffffff << 0) /**< \brief (HSMCI_TPR) Transmit Counter Register */ -/* -------- HSMCI_TCR : (HSMCI Offset: 0x10C) Transmit Counter Register -------- */ -#define HSMCI_TCR_TXCTR (0xffff << 0) /**< \brief (HSMCI_TCR) Transmit Counter Register */ -/* -------- HSMCI_RNPR : (HSMCI Offset: 0x110) Receive Next Pointer Register -------- */ -#define HSMCI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (HSMCI_RNPR) Receive Next Pointer */ -/* -------- HSMCI_RNCR : (HSMCI Offset: 0x114) Receive Next Counter Register -------- */ -#define HSMCI_RNCR_RXNCTR (0xffff << 0) /**< \brief (HSMCI_RNCR) Receive Next Counter */ -/* -------- HSMCI_TNPR : (HSMCI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define HSMCI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (HSMCI_TNPR) Transmit Next Pointer */ -/* -------- HSMCI_TNCR : (HSMCI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define HSMCI_TNCR_TXNCTR (0xffff << 0) /**< \brief (HSMCI_TNCR) Transmit Counter Next */ -/* -------- HSMCI_PTCR : (HSMCI Offset: 0x120) Transfer Control Register -------- */ -#define HSMCI_PTCR_RXTEN (0x1 << 0) /**< \brief (HSMCI_PTCR) Receiver Transfer Enable */ -#define HSMCI_PTCR_RXTDIS (0x1 << 1) /**< \brief (HSMCI_PTCR) Receiver Transfer Disable */ -#define HSMCI_PTCR_TXTEN (0x1 << 8) /**< \brief (HSMCI_PTCR) Transmitter Transfer Enable */ -#define HSMCI_PTCR_TXTDIS (0x1 << 9) /**< \brief (HSMCI_PTCR) Transmitter Transfer Disable */ -/* -------- HSMCI_PTSR : (HSMCI Offset: 0x124) Transfer Status Register -------- */ -#define HSMCI_PTSR_RXTEN (0x1 << 0) /**< \brief (HSMCI_PTSR) Receiver Transfer Enable */ -#define HSMCI_PTSR_TXTEN (0x1 << 8) /**< \brief (HSMCI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_MATRIX AHB Bus Matrix */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Matrix hardware registers */ -typedef struct { - RwReg MATRIX_MCFG[4]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */ - RwReg Reserved1[12]; - RwReg MATRIX_SCFG[5]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ - RwReg Reserved2[11]; - RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */ - RwReg Reserved3[1]; - RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */ - RwReg Reserved4[1]; - RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */ - RwReg Reserved5[1]; - RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */ - RwReg Reserved6[1]; - RwReg MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */ - RwReg Reserved7[28]; - RwReg CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System IO Configuration register */ - RwReg Reserved8[1]; - RwReg CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register */ - RwReg Reserved9[49]; - RwReg MATRIX_WPMR; /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */ - RoReg MATRIX_WPSR; /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */ -} Matrix; -#endif /* __ASSEMBLY__ */ -/* -------- MATRIX_MCFG[4] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */ -#define MATRIX_MCFG_ULBT (0x7 << 0) /**< \brief (MATRIX_MCFG[4]) Undefined Length Burst Type */ -/* -------- MATRIX_SCFG[5] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ -#define MATRIX_SCFG_SLOT_CYCLE (0xff << 0) /**< \brief (MATRIX_SCFG[5]) Maximum Number of Allowed Cycles for a Burst */ -#define MATRIX_SCFG_DEFMSTR_TYPE (0x3 << 16) /**< \brief (MATRIX_SCFG[5]) Default Master Type */ -#define MATRIX_SCFG_FIXED_DEFMSTR (0x7 << 18) /**< \brief (MATRIX_SCFG[5]) Fixed Default Master */ -#define MATRIX_SCFG_ARBT (0x3 << 24) /**< \brief (MATRIX_SCFG[5]) Arbitration Type */ -/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */ -#define MATRIX_PRAS0_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS0) Master 0 Priority */ -#define MATRIX_PRAS0_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS0) Master 1 Priority */ -#define MATRIX_PRAS0_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS0) Master 2 Priority */ -#define MATRIX_PRAS0_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS0) Master 3 Priority */ -#define MATRIX_PRAS0_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS0) Master 4 Priority */ -/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */ -#define MATRIX_PRAS1_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS1) Master 0 Priority */ -#define MATRIX_PRAS1_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS1) Master 1 Priority */ -#define MATRIX_PRAS1_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS1) Master 2 Priority */ -#define MATRIX_PRAS1_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS1) Master 3 Priority */ -#define MATRIX_PRAS1_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS1) Master 4 Priority */ -/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */ -#define MATRIX_PRAS2_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS2) Master 0 Priority */ -#define MATRIX_PRAS2_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS2) Master 1 Priority */ -#define MATRIX_PRAS2_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS2) Master 2 Priority */ -#define MATRIX_PRAS2_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS2) Master 3 Priority */ -#define MATRIX_PRAS2_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS2) Master 4 Priority */ -/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */ -#define MATRIX_PRAS3_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS3) Master 0 Priority */ -#define MATRIX_PRAS3_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS3) Master 1 Priority */ -#define MATRIX_PRAS3_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS3) Master 2 Priority */ -#define MATRIX_PRAS3_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS3) Master 3 Priority */ -#define MATRIX_PRAS3_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS3) Master 4 Priority */ -/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */ -#define MATRIX_PRAS4_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS4) Master 0 Priority */ -#define MATRIX_PRAS4_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS4) Master 1 Priority */ -#define MATRIX_PRAS4_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS4) Master 2 Priority */ -#define MATRIX_PRAS4_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS4) Master 3 Priority */ -#define MATRIX_PRAS4_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS4) Master 4 Priority */ -/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System IO Configuration register -------- */ -#define CCFG_SYSIO_SYSIO4 (0x1 << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */ -#define CCFG_SYSIO_SYSIO5 (0x1 << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ -#define CCFG_SYSIO_SYSIO6 (0x1 << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ -#define CCFG_SYSIO_SYSIO7 (0x1 << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ -#define CCFG_SYSIO_SYSIO10 (0x1 << 10) /**< \brief (CCFG_SYSIO) PB10 or DDM Assignment */ -#define CCFG_SYSIO_SYSIO11 (0x1 << 11) /**< \brief (CCFG_SYSIO) PB11 or DDP Assignment */ -#define CCFG_SYSIO_SYSIO12 (0x1 << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */ -/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register -------- */ -#define CCFG_SMCNFCS_SMC_NFCS0 (0x1 << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */ -#define CCFG_SMCNFCS_SMC_NFCS1 (0x1 << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */ -#define CCFG_SMCNFCS_SMC_NFCS2 (0x1 << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */ -#define CCFG_SMCNFCS_SMC_NFCS3 (0x1 << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */ -/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */ -#define MATRIX_WPMR_WPEN (0x1 << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */ -#define MATRIX_WPMR_WPKEY (0xffffff << 8) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */ -/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */ -#define MATRIX_WPSR_WPVS (0x1 << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */ -#define MATRIX_WPSR_WPVSRC (0xffff << 8) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PDC Peripheral DMA Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pdc hardware registers */ -typedef struct { - RwReg Reserved1[64]; - RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x100) Receive Pointer Register */ - RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x104) Receive Counter Register */ - RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x108) Transmit Pointer Register */ - RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0x10C) Transmit Counter Register */ - RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x110) Receive Next Pointer Register */ - RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x114) Receive Next Counter Register */ - RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x118) Transmit Next Pointer Register */ - RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x11C) Transmit Next Counter Register */ - WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x120) Transfer Control Register */ - RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x124) Transfer Status Register */ -} Pdc; -#endif /* __ASSEMBLY__ */ -/* -------- PERIPH_RPR : (PDC Offset: 0x100) Receive Pointer Register -------- */ -#define PERIPH_RPR_RXPTR (0xffffffff << 0) /**< \brief (PERIPH_RPR) Receive Pointer Register */ -/* -------- PERIPH_RCR : (PDC Offset: 0x104) Receive Counter Register -------- */ -#define PERIPH_RCR_RXCTR (0xffff << 0) /**< \brief (PERIPH_RCR) Receive Counter Register */ -/* -------- PERIPH_TPR : (PDC Offset: 0x108) Transmit Pointer Register -------- */ -#define PERIPH_TPR_TXPTR (0xffffffff << 0) /**< \brief (PERIPH_TPR) Transmit Counter Register */ -/* -------- PERIPH_TCR : (PDC Offset: 0x10C) Transmit Counter Register -------- */ -#define PERIPH_TCR_TXCTR (0xffff << 0) /**< \brief (PERIPH_TCR) Transmit Counter Register */ -/* -------- PERIPH_RNPR : (PDC Offset: 0x110) Receive Next Pointer Register -------- */ -#define PERIPH_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PERIPH_RNPR) Receive Next Pointer */ -/* -------- PERIPH_RNCR : (PDC Offset: 0x114) Receive Next Counter Register -------- */ -#define PERIPH_RNCR_RXNCTR (0xffff << 0) /**< \brief (PERIPH_RNCR) Receive Next Counter */ -/* -------- PERIPH_TNPR : (PDC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define PERIPH_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */ -/* -------- PERIPH_TNCR : (PDC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define PERIPH_TNCR_TXNCTR (0xffff << 0) /**< \brief (PERIPH_TNCR) Transmit Counter Next */ -/* -------- PERIPH_PTCR : (PDC Offset: 0x120) Transfer Control Register -------- */ -#define PERIPH_PTCR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */ -#define PERIPH_PTCR_RXTDIS (0x1 << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */ -#define PERIPH_PTCR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */ -#define PERIPH_PTCR_TXTDIS (0x1 << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */ -/* -------- PERIPH_PTSR : (PDC Offset: 0x124) Transfer Status Register -------- */ -#define PERIPH_PTSR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */ -#define PERIPH_PTSR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Parallel Input/Output */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PIO Parallel Input/Output */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pio hardware registers */ -typedef struct { - WoReg PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ - WoReg PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ - RoReg PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ - RwReg Reserved1[1]; - WoReg PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ - WoReg PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ - RoReg PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ - RwReg Reserved2[1]; - WoReg PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ - WoReg PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ - RoReg PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ - RwReg Reserved3[1]; - WoReg PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ - WoReg PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ - RwReg PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ - RoReg PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ - WoReg PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ - WoReg PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ - RoReg PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ - RoReg PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ - WoReg PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ - WoReg PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ - RoReg PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ - RwReg Reserved4[1]; - WoReg PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ - WoReg PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ - RoReg PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ - RwReg Reserved5[1]; - RwReg PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ - RwReg Reserved6[2]; - WoReg PIO_SCIFSR; /**< \brief (Pio Offset: 0x0080) System Clock Glitch Input Filter Select Register */ - WoReg PIO_DIFSR; /**< \brief (Pio Offset: 0x0084) Debouncing Input Filter Select Register */ - RoReg PIO_IFDGSR; /**< \brief (Pio Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register */ - RwReg PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ - WoReg PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ - WoReg PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ - RoReg PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ - RwReg Reserved7[1]; - WoReg PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ - WoReg PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ - RoReg PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ - RwReg Reserved8[1]; - WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ - WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */ - RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ - RwReg Reserved9[1]; - WoReg PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ - WoReg PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ - RoReg PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ - RwReg Reserved10[1]; - WoReg PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */ - WoReg PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */ - RoReg PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ - RwReg Reserved11[1]; - RoReg PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ - RwReg PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */ - RoReg PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */ - RwReg Reserved12[5]; - RwReg PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ - RwReg Reserved13[19]; - RwReg PIO_PCMR; /**< \brief (Pio Offset: 0x150) Parallel Capture Mode Register */ - WoReg PIO_PCIER; /**< \brief (Pio Offset: 0x154) Parallel Capture Interrupt Enable Register */ - WoReg PIO_PCIDR; /**< \brief (Pio Offset: 0x158) Parallel Capture Interrupt Disable Register */ - RoReg PIO_PCIMR; /**< \brief (Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register */ - RoReg PIO_PCISR; /**< \brief (Pio Offset: 0x160) Parallel Capture Interrupt Status Register */ - RoReg PIO_PCRHR; /**< \brief (Pio Offset: 0x164) Parallel Capture Reception Holding Register */ - RwReg Reserved14[38]; -} Pio; -#endif /* __ASSEMBLY__ */ -/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ -#define PIO_PER_P0 (0x1 << 0) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P1 (0x1 << 1) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P2 (0x1 << 2) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P3 (0x1 << 3) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P4 (0x1 << 4) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P5 (0x1 << 5) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P6 (0x1 << 6) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P7 (0x1 << 7) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P8 (0x1 << 8) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P9 (0x1 << 9) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P10 (0x1 << 10) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P11 (0x1 << 11) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P12 (0x1 << 12) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P13 (0x1 << 13) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P14 (0x1 << 14) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P15 (0x1 << 15) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P16 (0x1 << 16) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P17 (0x1 << 17) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P18 (0x1 << 18) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P19 (0x1 << 19) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P20 (0x1 << 20) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P21 (0x1 << 21) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P22 (0x1 << 22) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P23 (0x1 << 23) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P24 (0x1 << 24) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P25 (0x1 << 25) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P26 (0x1 << 26) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P27 (0x1 << 27) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P28 (0x1 << 28) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P29 (0x1 << 29) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P30 (0x1 << 30) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P31 (0x1 << 31) /**< \brief (PIO_PER) PIO Enable */ -/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ -#define PIO_PDR_P0 (0x1 << 0) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P1 (0x1 << 1) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P2 (0x1 << 2) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P3 (0x1 << 3) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P4 (0x1 << 4) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P5 (0x1 << 5) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P6 (0x1 << 6) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P7 (0x1 << 7) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P8 (0x1 << 8) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P9 (0x1 << 9) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P10 (0x1 << 10) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P11 (0x1 << 11) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P12 (0x1 << 12) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P13 (0x1 << 13) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P14 (0x1 << 14) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P15 (0x1 << 15) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P16 (0x1 << 16) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P17 (0x1 << 17) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P18 (0x1 << 18) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P19 (0x1 << 19) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P20 (0x1 << 20) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P21 (0x1 << 21) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P22 (0x1 << 22) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P23 (0x1 << 23) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P24 (0x1 << 24) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P25 (0x1 << 25) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P26 (0x1 << 26) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P27 (0x1 << 27) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P28 (0x1 << 28) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P29 (0x1 << 29) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P30 (0x1 << 30) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P31 (0x1 << 31) /**< \brief (PIO_PDR) PIO Disable */ -/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ -#define PIO_PSR_P0 (0x1 << 0) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P1 (0x1 << 1) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P2 (0x1 << 2) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P3 (0x1 << 3) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P4 (0x1 << 4) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P5 (0x1 << 5) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P6 (0x1 << 6) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P7 (0x1 << 7) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P8 (0x1 << 8) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P9 (0x1 << 9) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P10 (0x1 << 10) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P11 (0x1 << 11) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P12 (0x1 << 12) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P13 (0x1 << 13) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P14 (0x1 << 14) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P15 (0x1 << 15) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P16 (0x1 << 16) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P17 (0x1 << 17) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P18 (0x1 << 18) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P19 (0x1 << 19) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P20 (0x1 << 20) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P21 (0x1 << 21) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P22 (0x1 << 22) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P23 (0x1 << 23) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P24 (0x1 << 24) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P25 (0x1 << 25) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P26 (0x1 << 26) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P27 (0x1 << 27) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P28 (0x1 << 28) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P29 (0x1 << 29) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P30 (0x1 << 30) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P31 (0x1 << 31) /**< \brief (PIO_PSR) PIO Status */ -/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ -#define PIO_OER_P0 (0x1 << 0) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P1 (0x1 << 1) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P2 (0x1 << 2) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P3 (0x1 << 3) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P4 (0x1 << 4) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P5 (0x1 << 5) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P6 (0x1 << 6) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P7 (0x1 << 7) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P8 (0x1 << 8) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P9 (0x1 << 9) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P10 (0x1 << 10) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P11 (0x1 << 11) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P12 (0x1 << 12) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P13 (0x1 << 13) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P14 (0x1 << 14) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P15 (0x1 << 15) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P16 (0x1 << 16) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P17 (0x1 << 17) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P18 (0x1 << 18) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P19 (0x1 << 19) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P20 (0x1 << 20) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P21 (0x1 << 21) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P22 (0x1 << 22) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P23 (0x1 << 23) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P24 (0x1 << 24) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P25 (0x1 << 25) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P26 (0x1 << 26) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P27 (0x1 << 27) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P28 (0x1 << 28) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P29 (0x1 << 29) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P30 (0x1 << 30) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P31 (0x1 << 31) /**< \brief (PIO_OER) Output Enable */ -/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ -#define PIO_ODR_P0 (0x1 << 0) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P1 (0x1 << 1) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P2 (0x1 << 2) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P3 (0x1 << 3) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P4 (0x1 << 4) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P5 (0x1 << 5) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P6 (0x1 << 6) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P7 (0x1 << 7) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P8 (0x1 << 8) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P9 (0x1 << 9) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P10 (0x1 << 10) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P11 (0x1 << 11) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P12 (0x1 << 12) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P13 (0x1 << 13) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P14 (0x1 << 14) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P15 (0x1 << 15) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P16 (0x1 << 16) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P17 (0x1 << 17) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P18 (0x1 << 18) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P19 (0x1 << 19) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P20 (0x1 << 20) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P21 (0x1 << 21) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P22 (0x1 << 22) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P23 (0x1 << 23) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P24 (0x1 << 24) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P25 (0x1 << 25) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P26 (0x1 << 26) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P27 (0x1 << 27) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P28 (0x1 << 28) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P29 (0x1 << 29) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P30 (0x1 << 30) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P31 (0x1 << 31) /**< \brief (PIO_ODR) Output Disable */ -/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ -#define PIO_OSR_P0 (0x1 << 0) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P1 (0x1 << 1) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P2 (0x1 << 2) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P3 (0x1 << 3) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P4 (0x1 << 4) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P5 (0x1 << 5) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P6 (0x1 << 6) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P7 (0x1 << 7) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P8 (0x1 << 8) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P9 (0x1 << 9) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P10 (0x1 << 10) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P11 (0x1 << 11) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P12 (0x1 << 12) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P13 (0x1 << 13) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P14 (0x1 << 14) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P15 (0x1 << 15) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P16 (0x1 << 16) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P17 (0x1 << 17) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P18 (0x1 << 18) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P19 (0x1 << 19) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P20 (0x1 << 20) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P21 (0x1 << 21) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P22 (0x1 << 22) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P23 (0x1 << 23) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P24 (0x1 << 24) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P25 (0x1 << 25) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P26 (0x1 << 26) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P27 (0x1 << 27) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P28 (0x1 << 28) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P29 (0x1 << 29) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P30 (0x1 << 30) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P31 (0x1 << 31) /**< \brief (PIO_OSR) Output Status */ -/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ -#define PIO_IFER_P0 (0x1 << 0) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P1 (0x1 << 1) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P2 (0x1 << 2) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P3 (0x1 << 3) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P4 (0x1 << 4) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P5 (0x1 << 5) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P6 (0x1 << 6) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P7 (0x1 << 7) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P8 (0x1 << 8) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P9 (0x1 << 9) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P10 (0x1 << 10) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P11 (0x1 << 11) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P12 (0x1 << 12) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P13 (0x1 << 13) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P14 (0x1 << 14) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P15 (0x1 << 15) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P16 (0x1 << 16) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P17 (0x1 << 17) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P18 (0x1 << 18) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P19 (0x1 << 19) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P20 (0x1 << 20) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P21 (0x1 << 21) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P22 (0x1 << 22) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P23 (0x1 << 23) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P24 (0x1 << 24) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P25 (0x1 << 25) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P26 (0x1 << 26) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P27 (0x1 << 27) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P28 (0x1 << 28) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P29 (0x1 << 29) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P30 (0x1 << 30) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P31 (0x1 << 31) /**< \brief (PIO_IFER) Input Filter Enable */ -/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ -#define PIO_IFDR_P0 (0x1 << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P1 (0x1 << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P2 (0x1 << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P3 (0x1 << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P4 (0x1 << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P5 (0x1 << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P6 (0x1 << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P7 (0x1 << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P8 (0x1 << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P9 (0x1 << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P10 (0x1 << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P11 (0x1 << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P12 (0x1 << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P13 (0x1 << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P14 (0x1 << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P15 (0x1 << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P16 (0x1 << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P17 (0x1 << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P18 (0x1 << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P19 (0x1 << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P20 (0x1 << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P21 (0x1 << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P22 (0x1 << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P23 (0x1 << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P24 (0x1 << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P25 (0x1 << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P26 (0x1 << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P27 (0x1 << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P28 (0x1 << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P29 (0x1 << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P30 (0x1 << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P31 (0x1 << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ -/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ -#define PIO_IFSR_P0 (0x1 << 0) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P1 (0x1 << 1) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P2 (0x1 << 2) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P3 (0x1 << 3) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P4 (0x1 << 4) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P5 (0x1 << 5) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P6 (0x1 << 6) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P7 (0x1 << 7) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P8 (0x1 << 8) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P9 (0x1 << 9) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P10 (0x1 << 10) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P11 (0x1 << 11) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P12 (0x1 << 12) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P13 (0x1 << 13) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P14 (0x1 << 14) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P15 (0x1 << 15) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P16 (0x1 << 16) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P17 (0x1 << 17) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P18 (0x1 << 18) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P19 (0x1 << 19) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P20 (0x1 << 20) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P21 (0x1 << 21) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P22 (0x1 << 22) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P23 (0x1 << 23) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P24 (0x1 << 24) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P25 (0x1 << 25) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P26 (0x1 << 26) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P27 (0x1 << 27) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P28 (0x1 << 28) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P29 (0x1 << 29) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P30 (0x1 << 30) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P31 (0x1 << 31) /**< \brief (PIO_IFSR) Input Filer Status */ -/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ -#define PIO_SODR_P0 (0x1 << 0) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P1 (0x1 << 1) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P2 (0x1 << 2) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P3 (0x1 << 3) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P4 (0x1 << 4) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P5 (0x1 << 5) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P6 (0x1 << 6) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P7 (0x1 << 7) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P8 (0x1 << 8) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P9 (0x1 << 9) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P10 (0x1 << 10) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P11 (0x1 << 11) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P12 (0x1 << 12) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P13 (0x1 << 13) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P14 (0x1 << 14) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P15 (0x1 << 15) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P16 (0x1 << 16) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P17 (0x1 << 17) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P18 (0x1 << 18) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P19 (0x1 << 19) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P20 (0x1 << 20) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P21 (0x1 << 21) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P22 (0x1 << 22) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P23 (0x1 << 23) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P24 (0x1 << 24) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P25 (0x1 << 25) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P26 (0x1 << 26) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P27 (0x1 << 27) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P28 (0x1 << 28) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P29 (0x1 << 29) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P30 (0x1 << 30) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P31 (0x1 << 31) /**< \brief (PIO_SODR) Set Output Data */ -/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ -#define PIO_CODR_P0 (0x1 << 0) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P1 (0x1 << 1) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P2 (0x1 << 2) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P3 (0x1 << 3) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P4 (0x1 << 4) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P5 (0x1 << 5) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P6 (0x1 << 6) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P7 (0x1 << 7) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P8 (0x1 << 8) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P9 (0x1 << 9) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P10 (0x1 << 10) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P11 (0x1 << 11) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P12 (0x1 << 12) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P13 (0x1 << 13) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P14 (0x1 << 14) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P15 (0x1 << 15) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P16 (0x1 << 16) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P17 (0x1 << 17) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P18 (0x1 << 18) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P19 (0x1 << 19) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P20 (0x1 << 20) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P21 (0x1 << 21) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P22 (0x1 << 22) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P23 (0x1 << 23) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P24 (0x1 << 24) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P25 (0x1 << 25) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P26 (0x1 << 26) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P27 (0x1 << 27) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P28 (0x1 << 28) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P29 (0x1 << 29) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P30 (0x1 << 30) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P31 (0x1 << 31) /**< \brief (PIO_CODR) Clear Output Data */ -/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ -#define PIO_ODSR_P0 (0x1 << 0) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P1 (0x1 << 1) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P2 (0x1 << 2) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P3 (0x1 << 3) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P4 (0x1 << 4) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P5 (0x1 << 5) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P6 (0x1 << 6) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P7 (0x1 << 7) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P8 (0x1 << 8) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P9 (0x1 << 9) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P10 (0x1 << 10) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P11 (0x1 << 11) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P12 (0x1 << 12) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P13 (0x1 << 13) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P14 (0x1 << 14) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P15 (0x1 << 15) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P16 (0x1 << 16) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P17 (0x1 << 17) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P18 (0x1 << 18) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P19 (0x1 << 19) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P20 (0x1 << 20) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P21 (0x1 << 21) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P22 (0x1 << 22) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P23 (0x1 << 23) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P24 (0x1 << 24) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P25 (0x1 << 25) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P26 (0x1 << 26) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P27 (0x1 << 27) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P28 (0x1 << 28) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P29 (0x1 << 29) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P30 (0x1 << 30) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P31 (0x1 << 31) /**< \brief (PIO_ODSR) Output Data Status */ -/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ -#define PIO_PDSR_P0 (0x1 << 0) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P1 (0x1 << 1) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P2 (0x1 << 2) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P3 (0x1 << 3) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P4 (0x1 << 4) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P5 (0x1 << 5) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P6 (0x1 << 6) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P7 (0x1 << 7) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P8 (0x1 << 8) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P9 (0x1 << 9) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P10 (0x1 << 10) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P11 (0x1 << 11) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P12 (0x1 << 12) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P13 (0x1 << 13) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P14 (0x1 << 14) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P15 (0x1 << 15) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P16 (0x1 << 16) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P17 (0x1 << 17) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P18 (0x1 << 18) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P19 (0x1 << 19) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P20 (0x1 << 20) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P21 (0x1 << 21) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P22 (0x1 << 22) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P23 (0x1 << 23) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P24 (0x1 << 24) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P25 (0x1 << 25) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P26 (0x1 << 26) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P27 (0x1 << 27) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P28 (0x1 << 28) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P29 (0x1 << 29) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P30 (0x1 << 30) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P31 (0x1 << 31) /**< \brief (PIO_PDSR) Output Data Status */ -/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ -#define PIO_IER_P0 (0x1 << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P1 (0x1 << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P2 (0x1 << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P3 (0x1 << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P4 (0x1 << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P5 (0x1 << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P6 (0x1 << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P7 (0x1 << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P8 (0x1 << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P9 (0x1 << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P10 (0x1 << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P11 (0x1 << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P12 (0x1 << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P13 (0x1 << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P14 (0x1 << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P15 (0x1 << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P16 (0x1 << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P17 (0x1 << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P18 (0x1 << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P19 (0x1 << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P20 (0x1 << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P21 (0x1 << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P22 (0x1 << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P23 (0x1 << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P24 (0x1 << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P25 (0x1 << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P26 (0x1 << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P27 (0x1 << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P28 (0x1 << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P29 (0x1 << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P30 (0x1 << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P31 (0x1 << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ -#define PIO_IDR_P0 (0x1 << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P1 (0x1 << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P2 (0x1 << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P3 (0x1 << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P4 (0x1 << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P5 (0x1 << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P6 (0x1 << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P7 (0x1 << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P8 (0x1 << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P9 (0x1 << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P10 (0x1 << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P11 (0x1 << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P12 (0x1 << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P13 (0x1 << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P14 (0x1 << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P15 (0x1 << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P16 (0x1 << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P17 (0x1 << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P18 (0x1 << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P19 (0x1 << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P20 (0x1 << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P21 (0x1 << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P22 (0x1 << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P23 (0x1 << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P24 (0x1 << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P25 (0x1 << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P26 (0x1 << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P27 (0x1 << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P28 (0x1 << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P29 (0x1 << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P30 (0x1 << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P31 (0x1 << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ -#define PIO_IMR_P0 (0x1 << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P1 (0x1 << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P2 (0x1 << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P3 (0x1 << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P4 (0x1 << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P5 (0x1 << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P6 (0x1 << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P7 (0x1 << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P8 (0x1 << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P9 (0x1 << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P10 (0x1 << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P11 (0x1 << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P12 (0x1 << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P13 (0x1 << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P14 (0x1 << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P15 (0x1 << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P16 (0x1 << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P17 (0x1 << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P18 (0x1 << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P19 (0x1 << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P20 (0x1 << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P21 (0x1 << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P22 (0x1 << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P23 (0x1 << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P24 (0x1 << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P25 (0x1 << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P26 (0x1 << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P27 (0x1 << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P28 (0x1 << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P29 (0x1 << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P30 (0x1 << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P31 (0x1 << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ -#define PIO_ISR_P0 (0x1 << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P1 (0x1 << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P2 (0x1 << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P3 (0x1 << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P4 (0x1 << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P5 (0x1 << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P6 (0x1 << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P7 (0x1 << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P8 (0x1 << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P9 (0x1 << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P10 (0x1 << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P11 (0x1 << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P12 (0x1 << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P13 (0x1 << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P14 (0x1 << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P15 (0x1 << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P16 (0x1 << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P17 (0x1 << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P18 (0x1 << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P19 (0x1 << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P20 (0x1 << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P21 (0x1 << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P22 (0x1 << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P23 (0x1 << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P24 (0x1 << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P25 (0x1 << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P26 (0x1 << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P27 (0x1 << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P28 (0x1 << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P29 (0x1 << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P30 (0x1 << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P31 (0x1 << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ -#define PIO_MDER_P0 (0x1 << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P1 (0x1 << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P2 (0x1 << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P3 (0x1 << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P4 (0x1 << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P5 (0x1 << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P6 (0x1 << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P7 (0x1 << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P8 (0x1 << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P9 (0x1 << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P10 (0x1 << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P11 (0x1 << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P12 (0x1 << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P13 (0x1 << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P14 (0x1 << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P15 (0x1 << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P16 (0x1 << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P17 (0x1 << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P18 (0x1 << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P19 (0x1 << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P20 (0x1 << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P21 (0x1 << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P22 (0x1 << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P23 (0x1 << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P24 (0x1 << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P25 (0x1 << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P26 (0x1 << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P27 (0x1 << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P28 (0x1 << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P29 (0x1 << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P30 (0x1 << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P31 (0x1 << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */ -/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ -#define PIO_MDDR_P0 (0x1 << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P1 (0x1 << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P2 (0x1 << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P3 (0x1 << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P4 (0x1 << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P5 (0x1 << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P6 (0x1 << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P7 (0x1 << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P8 (0x1 << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P9 (0x1 << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P10 (0x1 << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P11 (0x1 << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P12 (0x1 << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P13 (0x1 << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P14 (0x1 << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P15 (0x1 << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P16 (0x1 << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P17 (0x1 << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P18 (0x1 << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P19 (0x1 << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P20 (0x1 << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P21 (0x1 << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P22 (0x1 << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P23 (0x1 << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P24 (0x1 << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P25 (0x1 << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P26 (0x1 << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P27 (0x1 << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P28 (0x1 << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P29 (0x1 << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P30 (0x1 << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P31 (0x1 << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ -#define PIO_MDSR_P0 (0x1 << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P1 (0x1 << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P2 (0x1 << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P3 (0x1 << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P4 (0x1 << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P5 (0x1 << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P6 (0x1 << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P7 (0x1 << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P8 (0x1 << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P9 (0x1 << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P10 (0x1 << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P11 (0x1 << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P12 (0x1 << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P13 (0x1 << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P14 (0x1 << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P15 (0x1 << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P16 (0x1 << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P17 (0x1 << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P18 (0x1 << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P19 (0x1 << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P20 (0x1 << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P21 (0x1 << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P22 (0x1 << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P23 (0x1 << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P24 (0x1 << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P25 (0x1 << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P26 (0x1 << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P27 (0x1 << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P28 (0x1 << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P29 (0x1 << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P30 (0x1 << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P31 (0x1 << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */ -/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ -#define PIO_PUDR_P0 (0x1 << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P1 (0x1 << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P2 (0x1 << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P3 (0x1 << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P4 (0x1 << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P5 (0x1 << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P6 (0x1 << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P7 (0x1 << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P8 (0x1 << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P9 (0x1 << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P10 (0x1 << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P11 (0x1 << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P12 (0x1 << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P13 (0x1 << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P14 (0x1 << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P15 (0x1 << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P16 (0x1 << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P17 (0x1 << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P18 (0x1 << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P19 (0x1 << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P20 (0x1 << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P21 (0x1 << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P22 (0x1 << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P23 (0x1 << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P24 (0x1 << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P25 (0x1 << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P26 (0x1 << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P27 (0x1 << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P28 (0x1 << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P29 (0x1 << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P30 (0x1 << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P31 (0x1 << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */ -/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ -#define PIO_PUER_P0 (0x1 << 0) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P1 (0x1 << 1) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P2 (0x1 << 2) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P3 (0x1 << 3) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P4 (0x1 << 4) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P5 (0x1 << 5) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P6 (0x1 << 6) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P7 (0x1 << 7) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P8 (0x1 << 8) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P9 (0x1 << 9) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P10 (0x1 << 10) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P11 (0x1 << 11) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P12 (0x1 << 12) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P13 (0x1 << 13) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P14 (0x1 << 14) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P15 (0x1 << 15) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P16 (0x1 << 16) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P17 (0x1 << 17) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P18 (0x1 << 18) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P19 (0x1 << 19) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P20 (0x1 << 20) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P21 (0x1 << 21) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P22 (0x1 << 22) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P23 (0x1 << 23) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P24 (0x1 << 24) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P25 (0x1 << 25) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P26 (0x1 << 26) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P27 (0x1 << 27) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P28 (0x1 << 28) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P29 (0x1 << 29) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P30 (0x1 << 30) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P31 (0x1 << 31) /**< \brief (PIO_PUER) Pull Up Enable. */ -/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ -#define PIO_PUSR_P0 (0x1 << 0) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P1 (0x1 << 1) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P2 (0x1 << 2) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P3 (0x1 << 3) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P4 (0x1 << 4) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P5 (0x1 << 5) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P6 (0x1 << 6) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P7 (0x1 << 7) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P8 (0x1 << 8) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P9 (0x1 << 9) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P10 (0x1 << 10) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P11 (0x1 << 11) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P12 (0x1 << 12) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P13 (0x1 << 13) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P14 (0x1 << 14) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P15 (0x1 << 15) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P16 (0x1 << 16) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P17 (0x1 << 17) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P18 (0x1 << 18) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P19 (0x1 << 19) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P20 (0x1 << 20) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P21 (0x1 << 21) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P22 (0x1 << 22) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P23 (0x1 << 23) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P24 (0x1 << 24) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P25 (0x1 << 25) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P26 (0x1 << 26) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P27 (0x1 << 27) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P28 (0x1 << 28) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P29 (0x1 << 29) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P30 (0x1 << 30) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P31 (0x1 << 31) /**< \brief (PIO_PUSR) Pull Up Status. */ -/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ -#define PIO_ABCDSR_P0 (0x1 << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P1 (0x1 << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P2 (0x1 << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P3 (0x1 << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P4 (0x1 << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P5 (0x1 << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P6 (0x1 << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P7 (0x1 << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P8 (0x1 << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P9 (0x1 << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P10 (0x1 << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P11 (0x1 << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P12 (0x1 << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P13 (0x1 << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P14 (0x1 << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P15 (0x1 << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P16 (0x1 << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P17 (0x1 << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P18 (0x1 << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P19 (0x1 << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P20 (0x1 << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P21 (0x1 << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P22 (0x1 << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P23 (0x1 << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P24 (0x1 << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P25 (0x1 << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P26 (0x1 << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P27 (0x1 << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P28 (0x1 << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P29 (0x1 << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P30 (0x1 << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P31 (0x1 << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -/* -------- PIO_SCIFSR : (PIO Offset: 0x0080) System Clock Glitch Input Filter Select Register -------- */ -#define PIO_SCIFSR_P0 (0x1 << 0) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P1 (0x1 << 1) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P2 (0x1 << 2) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P3 (0x1 << 3) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P4 (0x1 << 4) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P5 (0x1 << 5) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P6 (0x1 << 6) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P7 (0x1 << 7) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P8 (0x1 << 8) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P9 (0x1 << 9) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P10 (0x1 << 10) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P11 (0x1 << 11) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P12 (0x1 << 12) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P13 (0x1 << 13) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P14 (0x1 << 14) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P15 (0x1 << 15) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P16 (0x1 << 16) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P17 (0x1 << 17) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P18 (0x1 << 18) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P19 (0x1 << 19) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P20 (0x1 << 20) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P21 (0x1 << 21) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P22 (0x1 << 22) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P23 (0x1 << 23) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P24 (0x1 << 24) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P25 (0x1 << 25) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P26 (0x1 << 26) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P27 (0x1 << 27) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P28 (0x1 << 28) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P29 (0x1 << 29) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P30 (0x1 << 30) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P31 (0x1 << 31) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -/* -------- PIO_DIFSR : (PIO Offset: 0x0084) Debouncing Input Filter Select Register -------- */ -#define PIO_DIFSR_P0 (0x1 << 0) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P1 (0x1 << 1) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P2 (0x1 << 2) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P3 (0x1 << 3) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P4 (0x1 << 4) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P5 (0x1 << 5) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P6 (0x1 << 6) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P7 (0x1 << 7) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P8 (0x1 << 8) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P9 (0x1 << 9) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P10 (0x1 << 10) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P11 (0x1 << 11) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P12 (0x1 << 12) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P13 (0x1 << 13) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P14 (0x1 << 14) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P15 (0x1 << 15) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P16 (0x1 << 16) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P17 (0x1 << 17) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P18 (0x1 << 18) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P19 (0x1 << 19) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P20 (0x1 << 20) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P21 (0x1 << 21) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P22 (0x1 << 22) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P23 (0x1 << 23) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P24 (0x1 << 24) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P25 (0x1 << 25) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P26 (0x1 << 26) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P27 (0x1 << 27) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P28 (0x1 << 28) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P29 (0x1 << 29) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P30 (0x1 << 30) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P31 (0x1 << 31) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -/* -------- PIO_IFDGSR : (PIO Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register -------- */ -#define PIO_IFDGSR_P0 (0x1 << 0) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P1 (0x1 << 1) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P2 (0x1 << 2) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P3 (0x1 << 3) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P4 (0x1 << 4) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P5 (0x1 << 5) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P6 (0x1 << 6) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P7 (0x1 << 7) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P8 (0x1 << 8) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P9 (0x1 << 9) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P10 (0x1 << 10) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P11 (0x1 << 11) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P12 (0x1 << 12) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P13 (0x1 << 13) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P14 (0x1 << 14) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P15 (0x1 << 15) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P16 (0x1 << 16) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P17 (0x1 << 17) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P18 (0x1 << 18) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P19 (0x1 << 19) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P20 (0x1 << 20) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P21 (0x1 << 21) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P22 (0x1 << 22) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P23 (0x1 << 23) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P24 (0x1 << 24) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P25 (0x1 << 25) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P26 (0x1 << 26) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P27 (0x1 << 27) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P28 (0x1 << 28) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P29 (0x1 << 29) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P30 (0x1 << 30) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P31 (0x1 << 31) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ -#define PIO_SCDR_DIV0 (0x1 << 0) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV1 (0x1 << 1) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV2 (0x1 << 2) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV3 (0x1 << 3) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV4 (0x1 << 4) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV5 (0x1 << 5) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV6 (0x1 << 6) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV7 (0x1 << 7) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV8 (0x1 << 8) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV9 (0x1 << 9) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV10 (0x1 << 10) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV11 (0x1 << 11) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV12 (0x1 << 12) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV13 (0x1 << 13) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ -#define PIO_PPDDR_P0 (0x1 << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P1 (0x1 << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P2 (0x1 << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P3 (0x1 << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P4 (0x1 << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P5 (0x1 << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P6 (0x1 << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P7 (0x1 << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P8 (0x1 << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P9 (0x1 << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P10 (0x1 << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P11 (0x1 << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P12 (0x1 << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P13 (0x1 << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P14 (0x1 << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P15 (0x1 << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P16 (0x1 << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P17 (0x1 << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P18 (0x1 << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P19 (0x1 << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P20 (0x1 << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P21 (0x1 << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P22 (0x1 << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P23 (0x1 << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P24 (0x1 << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P25 (0x1 << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P26 (0x1 << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P27 (0x1 << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P28 (0x1 << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P29 (0x1 << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P30 (0x1 << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P31 (0x1 << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ -#define PIO_PPDER_P0 (0x1 << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P1 (0x1 << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P2 (0x1 << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P3 (0x1 << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P4 (0x1 << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P5 (0x1 << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P6 (0x1 << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P7 (0x1 << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P8 (0x1 << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P9 (0x1 << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P10 (0x1 << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P11 (0x1 << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P12 (0x1 << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P13 (0x1 << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P14 (0x1 << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P15 (0x1 << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P16 (0x1 << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P17 (0x1 << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P18 (0x1 << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P19 (0x1 << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P20 (0x1 << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P21 (0x1 << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P22 (0x1 << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P23 (0x1 << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P24 (0x1 << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P25 (0x1 << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P26 (0x1 << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P27 (0x1 << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P28 (0x1 << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P29 (0x1 << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P30 (0x1 << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P31 (0x1 << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */ -/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ -#define PIO_PPDSR_P0 (0x1 << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P1 (0x1 << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P2 (0x1 << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P3 (0x1 << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P4 (0x1 << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P5 (0x1 << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P6 (0x1 << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P7 (0x1 << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P8 (0x1 << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P9 (0x1 << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P10 (0x1 << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P11 (0x1 << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P12 (0x1 << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P13 (0x1 << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P14 (0x1 << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P15 (0x1 << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P16 (0x1 << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P17 (0x1 << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P18 (0x1 << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P19 (0x1 << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P20 (0x1 << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P21 (0x1 << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P22 (0x1 << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P23 (0x1 << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P24 (0x1 << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P25 (0x1 << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P26 (0x1 << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P27 (0x1 << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P28 (0x1 << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P29 (0x1 << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P30 (0x1 << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P31 (0x1 << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */ -/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ -#define PIO_OWER_P0 (0x1 << 0) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P1 (0x1 << 1) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P2 (0x1 << 2) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P3 (0x1 << 3) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P4 (0x1 << 4) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P5 (0x1 << 5) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P6 (0x1 << 6) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P7 (0x1 << 7) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P8 (0x1 << 8) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P9 (0x1 << 9) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P10 (0x1 << 10) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P11 (0x1 << 11) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P12 (0x1 << 12) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P13 (0x1 << 13) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P14 (0x1 << 14) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P15 (0x1 << 15) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P16 (0x1 << 16) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P17 (0x1 << 17) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P18 (0x1 << 18) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P19 (0x1 << 19) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P20 (0x1 << 20) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P21 (0x1 << 21) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P22 (0x1 << 22) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P23 (0x1 << 23) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P24 (0x1 << 24) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P25 (0x1 << 25) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P26 (0x1 << 26) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P27 (0x1 << 27) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P28 (0x1 << 28) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P29 (0x1 << 29) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P30 (0x1 << 30) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P31 (0x1 << 31) /**< \brief (PIO_OWER) Output Write Enable. */ -/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ -#define PIO_OWDR_P0 (0x1 << 0) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P1 (0x1 << 1) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P2 (0x1 << 2) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P3 (0x1 << 3) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P4 (0x1 << 4) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P5 (0x1 << 5) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P6 (0x1 << 6) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P7 (0x1 << 7) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P8 (0x1 << 8) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P9 (0x1 << 9) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P10 (0x1 << 10) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P11 (0x1 << 11) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P12 (0x1 << 12) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P13 (0x1 << 13) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P14 (0x1 << 14) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P15 (0x1 << 15) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P16 (0x1 << 16) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P17 (0x1 << 17) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P18 (0x1 << 18) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P19 (0x1 << 19) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P20 (0x1 << 20) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P21 (0x1 << 21) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P22 (0x1 << 22) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P23 (0x1 << 23) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P24 (0x1 << 24) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P25 (0x1 << 25) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P26 (0x1 << 26) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P27 (0x1 << 27) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P28 (0x1 << 28) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P29 (0x1 << 29) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P30 (0x1 << 30) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P31 (0x1 << 31) /**< \brief (PIO_OWDR) Output Write Disable. */ -/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ -#define PIO_OWSR_P0 (0x1 << 0) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P1 (0x1 << 1) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P2 (0x1 << 2) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P3 (0x1 << 3) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P4 (0x1 << 4) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P5 (0x1 << 5) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P6 (0x1 << 6) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P7 (0x1 << 7) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P8 (0x1 << 8) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P9 (0x1 << 9) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P10 (0x1 << 10) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P11 (0x1 << 11) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P12 (0x1 << 12) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P13 (0x1 << 13) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P14 (0x1 << 14) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P15 (0x1 << 15) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P16 (0x1 << 16) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P17 (0x1 << 17) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P18 (0x1 << 18) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P19 (0x1 << 19) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P20 (0x1 << 20) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P21 (0x1 << 21) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P22 (0x1 << 22) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P23 (0x1 << 23) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P24 (0x1 << 24) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P25 (0x1 << 25) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P26 (0x1 << 26) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P27 (0x1 << 27) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P28 (0x1 << 28) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P29 (0x1 << 29) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P30 (0x1 << 30) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P31 (0x1 << 31) /**< \brief (PIO_OWSR) Output Write Status. */ -/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ -#define PIO_AIMER_P0 (0x1 << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P1 (0x1 << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P2 (0x1 << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P3 (0x1 << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P4 (0x1 << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P5 (0x1 << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P6 (0x1 << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P7 (0x1 << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P8 (0x1 << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P9 (0x1 << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P10 (0x1 << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P11 (0x1 << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P12 (0x1 << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P13 (0x1 << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P14 (0x1 << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P15 (0x1 << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P16 (0x1 << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P17 (0x1 << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P18 (0x1 << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P19 (0x1 << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P20 (0x1 << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P21 (0x1 << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P22 (0x1 << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P23 (0x1 << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P24 (0x1 << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P25 (0x1 << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P26 (0x1 << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P27 (0x1 << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P28 (0x1 << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P29 (0x1 << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P30 (0x1 << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P31 (0x1 << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */ -#define PIO_AIMDR_P0 (0x1 << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P1 (0x1 << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P2 (0x1 << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P3 (0x1 << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P4 (0x1 << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P5 (0x1 << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P6 (0x1 << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P7 (0x1 << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P8 (0x1 << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P9 (0x1 << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P10 (0x1 << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P11 (0x1 << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P12 (0x1 << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P13 (0x1 << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P14 (0x1 << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P15 (0x1 << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P16 (0x1 << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P17 (0x1 << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P18 (0x1 << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P19 (0x1 << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P20 (0x1 << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P21 (0x1 << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P22 (0x1 << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P23 (0x1 << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P24 (0x1 << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P25 (0x1 << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P26 (0x1 << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P27 (0x1 << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P28 (0x1 << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P29 (0x1 << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P30 (0x1 << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P31 (0x1 << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ -#define PIO_AIMMR_P0 (0x1 << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P1 (0x1 << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P2 (0x1 << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P3 (0x1 << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P4 (0x1 << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P5 (0x1 << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P6 (0x1 << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P7 (0x1 << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P8 (0x1 << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P9 (0x1 << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P10 (0x1 << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P11 (0x1 << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P12 (0x1 << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P13 (0x1 << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P14 (0x1 << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P15 (0x1 << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P16 (0x1 << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P17 (0x1 << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P18 (0x1 << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P19 (0x1 << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P20 (0x1 << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P21 (0x1 << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P22 (0x1 << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P23 (0x1 << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P24 (0x1 << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P25 (0x1 << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P26 (0x1 << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P27 (0x1 << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P28 (0x1 << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P29 (0x1 << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P30 (0x1 << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P31 (0x1 << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ -#define PIO_ESR_P0 (0x1 << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P1 (0x1 << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P2 (0x1 << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P3 (0x1 << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P4 (0x1 << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P5 (0x1 << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P6 (0x1 << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P7 (0x1 << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P8 (0x1 << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P9 (0x1 << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P10 (0x1 << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P11 (0x1 << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P12 (0x1 << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P13 (0x1 << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P14 (0x1 << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P15 (0x1 << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P16 (0x1 << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P17 (0x1 << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P18 (0x1 << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P19 (0x1 << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P20 (0x1 << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P21 (0x1 << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P22 (0x1 << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P23 (0x1 << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P24 (0x1 << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P25 (0x1 << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P26 (0x1 << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P27 (0x1 << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P28 (0x1 << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P29 (0x1 << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P30 (0x1 << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P31 (0x1 << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ -#define PIO_LSR_P0 (0x1 << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P1 (0x1 << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P2 (0x1 << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P3 (0x1 << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P4 (0x1 << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P5 (0x1 << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P6 (0x1 << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P7 (0x1 << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P8 (0x1 << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P9 (0x1 << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P10 (0x1 << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P11 (0x1 << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P12 (0x1 << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P13 (0x1 << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P14 (0x1 << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P15 (0x1 << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P16 (0x1 << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P17 (0x1 << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P18 (0x1 << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P19 (0x1 << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P20 (0x1 << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P21 (0x1 << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P22 (0x1 << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P23 (0x1 << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P24 (0x1 << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P25 (0x1 << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P26 (0x1 << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P27 (0x1 << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P28 (0x1 << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P29 (0x1 << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P30 (0x1 << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P31 (0x1 << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ -#define PIO_ELSR_P0 (0x1 << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P1 (0x1 << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P2 (0x1 << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P3 (0x1 << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P4 (0x1 << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P5 (0x1 << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P6 (0x1 << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P7 (0x1 << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P8 (0x1 << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P9 (0x1 << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P10 (0x1 << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P11 (0x1 << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P12 (0x1 << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P13 (0x1 << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P14 (0x1 << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P15 (0x1 << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P16 (0x1 << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P17 (0x1 << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P18 (0x1 << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P19 (0x1 << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P20 (0x1 << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P21 (0x1 << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P22 (0x1 << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P23 (0x1 << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P24 (0x1 << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P25 (0x1 << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P26 (0x1 << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P27 (0x1 << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P28 (0x1 << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P29 (0x1 << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P30 (0x1 << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P31 (0x1 << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */ -#define PIO_FELLSR_P0 (0x1 << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P1 (0x1 << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P2 (0x1 << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P3 (0x1 << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P4 (0x1 << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P5 (0x1 << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P6 (0x1 << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P7 (0x1 << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P8 (0x1 << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P9 (0x1 << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P10 (0x1 << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P11 (0x1 << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P12 (0x1 << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P13 (0x1 << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P14 (0x1 << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P15 (0x1 << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P16 (0x1 << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P17 (0x1 << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P18 (0x1 << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P19 (0x1 << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P20 (0x1 << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P21 (0x1 << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P22 (0x1 << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P23 (0x1 << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P24 (0x1 << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P25 (0x1 << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P26 (0x1 << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P27 (0x1 << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P28 (0x1 << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P29 (0x1 << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P30 (0x1 << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P31 (0x1 << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */ -#define PIO_REHLSR_P0 (0x1 << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P1 (0x1 << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P2 (0x1 << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P3 (0x1 << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P4 (0x1 << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P5 (0x1 << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P6 (0x1 << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P7 (0x1 << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P8 (0x1 << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P9 (0x1 << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P10 (0x1 << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P11 (0x1 << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P12 (0x1 << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P13 (0x1 << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P14 (0x1 << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P15 (0x1 << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P16 (0x1 << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P17 (0x1 << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P18 (0x1 << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P19 (0x1 << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P20 (0x1 << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P21 (0x1 << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P22 (0x1 << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P23 (0x1 << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P24 (0x1 << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P25 (0x1 << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P26 (0x1 << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P27 (0x1 << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P28 (0x1 << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P29 (0x1 << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P30 (0x1 << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P31 (0x1 << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ -#define PIO_FRLHSR_P0 (0x1 << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P1 (0x1 << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P2 (0x1 << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P3 (0x1 << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P4 (0x1 << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P5 (0x1 << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P6 (0x1 << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P7 (0x1 << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P8 (0x1 << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P9 (0x1 << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P10 (0x1 << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P11 (0x1 << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P12 (0x1 << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P13 (0x1 << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P14 (0x1 << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P15 (0x1 << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P16 (0x1 << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P17 (0x1 << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P18 (0x1 << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P19 (0x1 << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P20 (0x1 << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P21 (0x1 << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P22 (0x1 << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P23 (0x1 << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P24 (0x1 << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P25 (0x1 << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P26 (0x1 << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P27 (0x1 << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P28 (0x1 << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P29 (0x1 << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P30 (0x1 << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P31 (0x1 << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ -#define PIO_LOCKSR_P0 (0x1 << 0) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P1 (0x1 << 1) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P2 (0x1 << 2) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P3 (0x1 << 3) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P4 (0x1 << 4) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P5 (0x1 << 5) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P6 (0x1 << 6) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P7 (0x1 << 7) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P8 (0x1 << 8) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P9 (0x1 << 9) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P10 (0x1 << 10) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P11 (0x1 << 11) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P12 (0x1 << 12) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P13 (0x1 << 13) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P14 (0x1 << 14) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P15 (0x1 << 15) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P16 (0x1 << 16) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P17 (0x1 << 17) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P18 (0x1 << 18) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P19 (0x1 << 19) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P20 (0x1 << 20) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P21 (0x1 << 21) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P22 (0x1 << 22) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P23 (0x1 << 23) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P24 (0x1 << 24) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P25 (0x1 << 25) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P26 (0x1 << 26) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P27 (0x1 << 27) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P28 (0x1 << 28) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P29 (0x1 << 29) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P30 (0x1 << 30) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P31 (0x1 << 31) /**< \brief (PIO_LOCKSR) Lock Status. */ -/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */ -#define PIO_WPMR_WPEN (0x1 << 0) /**< \brief (PIO_WPMR) Write Protect Enable */ -#define PIO_WPMR_WPKEY (0xffffff << 8) /**< \brief (PIO_WPMR) Write Protect KEY */ -/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */ -#define PIO_WPSR_WPVS (0x1 << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */ -#define PIO_WPSR_WPVSRC (0xffff << 8) /**< \brief (PIO_WPSR) Write Protect Violation Source */ -/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ -#define PIO_SCHMITT_SCHMITT0 (0x1 << 0) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT1 (0x1 << 1) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT2 (0x1 << 2) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT3 (0x1 << 3) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT4 (0x1 << 4) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT5 (0x1 << 5) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT6 (0x1 << 6) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT7 (0x1 << 7) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT8 (0x1 << 8) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT9 (0x1 << 9) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT10 (0x1 << 10) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT11 (0x1 << 11) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT12 (0x1 << 12) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT13 (0x1 << 13) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT14 (0x1 << 14) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT15 (0x1 << 15) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT16 (0x1 << 16) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT17 (0x1 << 17) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT18 (0x1 << 18) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT19 (0x1 << 19) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT20 (0x1 << 20) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT21 (0x1 << 21) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT22 (0x1 << 22) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT23 (0x1 << 23) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT24 (0x1 << 24) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT25 (0x1 << 25) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT26 (0x1 << 26) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT27 (0x1 << 27) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT28 (0x1 << 28) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT29 (0x1 << 29) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT30 (0x1 << 30) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT31 (0x1 << 31) /**< \brief (PIO_SCHMITT) */ -/* -------- PIO_PCMR : (PIO Offset: 0x150) Parallel Capture Mode Register -------- */ -#define PIO_PCMR_PCEN (0x1 << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */ -#define PIO_PCMR_DSIZE (0x3 << 4) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */ -#define PIO_PCMR_ALWYS (0x1 << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */ -#define PIO_PCMR_HALFS (0x1 << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */ -#define PIO_PCMR_FRSTS (0x1 << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */ -/* -------- PIO_PCIER : (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register -------- */ -#define PIO_PCIER_DRDY (0x1 << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */ -#define PIO_PCIER_OVRE (0x1 << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */ -#define PIO_PCIER_ENDRX (0x1 << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */ -#define PIO_PCIER_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */ -/* -------- PIO_PCIDR : (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register -------- */ -#define PIO_PCIDR_DRDY (0x1 << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */ -#define PIO_PCIDR_OVRE (0x1 << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */ -#define PIO_PCIDR_ENDRX (0x1 << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */ -#define PIO_PCIDR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */ -/* -------- PIO_PCIMR : (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register -------- */ -#define PIO_PCIMR_DRDY (0x1 << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */ -#define PIO_PCIMR_OVRE (0x1 << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */ -#define PIO_PCIMR_ENDRX (0x1 << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */ -#define PIO_PCIMR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */ -/* -------- PIO_PCISR : (PIO Offset: 0x160) Parallel Capture Interrupt Status Register -------- */ -#define PIO_PCISR_DRDY (0x1 << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */ -#define PIO_PCISR_OVRE (0x1 << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error. */ -#define PIO_PCISR_ENDRX (0x1 << 2) /**< \brief (PIO_PCISR) End of Reception Transfer. */ -#define PIO_PCISR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCISR) Reception Buffer Full */ -/* -------- PIO_PCRHR : (PIO Offset: 0x164) Parallel Capture Reception Holding Register -------- */ -#define PIO_PCRHR_RDATA (0xffffffff << 0) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data. */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Power Management Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PMC Power Management Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pmc hardware registers */ -typedef struct { - WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ - WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ - RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ - RwReg Reserved1[1]; - WoReg PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ - WoReg PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ - RoReg PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ - RwReg Reserved2[1]; - RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ - RoReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ - RwReg CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ - RwReg CKGR_PLLBR; /**< \brief (Pmc Offset: 0x002C) PLLB Register */ - RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ - RwReg Reserved3[1]; - RwReg PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ - RwReg Reserved4[1]; - RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ - RwReg Reserved5[5]; - WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ - WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ - RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ - RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ - RwReg PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ - RwReg PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ - WoReg PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ - RwReg Reserved6[26]; - RwReg PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */ - RoReg PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */ - RwReg Reserved7[5]; - WoReg PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ - WoReg PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ - RoReg PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ - RwReg Reserved8[1]; - RwReg PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ -} Pmc; -#endif /* __ASSEMBLY__ */ -/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ -#define PMC_SCER_UDP (0x1 << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */ -#define PMC_SCER_PCK0 (0x1 << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ -#define PMC_SCER_PCK1 (0x1 << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ -#define PMC_SCER_PCK2 (0x1 << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ -/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ -#define PMC_SCDR_UDP (0x1 << 7) /**< \brief (PMC_SCDR) USB Device Port Clock Disable */ -#define PMC_SCDR_PCK0 (0x1 << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ -#define PMC_SCDR_PCK1 (0x1 << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ -#define PMC_SCDR_PCK2 (0x1 << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ -/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ -#define PMC_SCSR_UDP (0x1 << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */ -#define PMC_SCSR_PCK0 (0x1 << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ -#define PMC_SCSR_PCK1 (0x1 << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ -#define PMC_SCSR_PCK2 (0x1 << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ -/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ -#define PMC_PCER0_PID2 (0x1 << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */ -#define PMC_PCER0_PID3 (0x1 << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */ -#define PMC_PCER0_PID4 (0x1 << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */ -#define PMC_PCER0_PID5 (0x1 << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */ -#define PMC_PCER0_PID6 (0x1 << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */ -#define PMC_PCER0_PID7 (0x1 << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */ -#define PMC_PCER0_PID8 (0x1 << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ -#define PMC_PCER0_PID9 (0x1 << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ -#define PMC_PCER0_PID10 (0x1 << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ -#define PMC_PCER0_PID11 (0x1 << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ -#define PMC_PCER0_PID12 (0x1 << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ -#define PMC_PCER0_PID13 (0x1 << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ -#define PMC_PCER0_PID14 (0x1 << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ -#define PMC_PCER0_PID15 (0x1 << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ -#define PMC_PCER0_PID16 (0x1 << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ -#define PMC_PCER0_PID17 (0x1 << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ -#define PMC_PCER0_PID18 (0x1 << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ -#define PMC_PCER0_PID19 (0x1 << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ -#define PMC_PCER0_PID20 (0x1 << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ -#define PMC_PCER0_PID21 (0x1 << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ -#define PMC_PCER0_PID22 (0x1 << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ -#define PMC_PCER0_PID23 (0x1 << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ -#define PMC_PCER0_PID24 (0x1 << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ -#define PMC_PCER0_PID25 (0x1 << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ -#define PMC_PCER0_PID26 (0x1 << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ -#define PMC_PCER0_PID27 (0x1 << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ -#define PMC_PCER0_PID28 (0x1 << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ -#define PMC_PCER0_PID29 (0x1 << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ -#define PMC_PCER0_PID30 (0x1 << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ -#define PMC_PCER0_PID31 (0x1 << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ -/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ -#define PMC_PCDR0_PID2 (0x1 << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */ -#define PMC_PCDR0_PID3 (0x1 << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */ -#define PMC_PCDR0_PID4 (0x1 << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */ -#define PMC_PCDR0_PID5 (0x1 << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */ -#define PMC_PCDR0_PID6 (0x1 << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */ -#define PMC_PCDR0_PID7 (0x1 << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */ -#define PMC_PCDR0_PID8 (0x1 << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ -#define PMC_PCDR0_PID9 (0x1 << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ -#define PMC_PCDR0_PID10 (0x1 << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ -#define PMC_PCDR0_PID11 (0x1 << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ -#define PMC_PCDR0_PID12 (0x1 << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ -#define PMC_PCDR0_PID13 (0x1 << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ -#define PMC_PCDR0_PID14 (0x1 << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ -#define PMC_PCDR0_PID15 (0x1 << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ -#define PMC_PCDR0_PID16 (0x1 << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ -#define PMC_PCDR0_PID17 (0x1 << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ -#define PMC_PCDR0_PID18 (0x1 << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ -#define PMC_PCDR0_PID19 (0x1 << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ -#define PMC_PCDR0_PID20 (0x1 << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ -#define PMC_PCDR0_PID21 (0x1 << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ -#define PMC_PCDR0_PID22 (0x1 << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ -#define PMC_PCDR0_PID23 (0x1 << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ -#define PMC_PCDR0_PID24 (0x1 << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ -#define PMC_PCDR0_PID25 (0x1 << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ -#define PMC_PCDR0_PID26 (0x1 << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ -#define PMC_PCDR0_PID27 (0x1 << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ -#define PMC_PCDR0_PID28 (0x1 << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ -#define PMC_PCDR0_PID29 (0x1 << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ -#define PMC_PCDR0_PID30 (0x1 << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ -#define PMC_PCDR0_PID31 (0x1 << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ -/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ -#define PMC_PCSR0_PID2 (0x1 << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */ -#define PMC_PCSR0_PID3 (0x1 << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */ -#define PMC_PCSR0_PID4 (0x1 << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */ -#define PMC_PCSR0_PID5 (0x1 << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */ -#define PMC_PCSR0_PID6 (0x1 << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */ -#define PMC_PCSR0_PID7 (0x1 << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */ -#define PMC_PCSR0_PID8 (0x1 << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ -#define PMC_PCSR0_PID9 (0x1 << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ -#define PMC_PCSR0_PID10 (0x1 << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ -#define PMC_PCSR0_PID11 (0x1 << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ -#define PMC_PCSR0_PID12 (0x1 << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ -#define PMC_PCSR0_PID13 (0x1 << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ -#define PMC_PCSR0_PID14 (0x1 << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ -#define PMC_PCSR0_PID15 (0x1 << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ -#define PMC_PCSR0_PID16 (0x1 << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ -#define PMC_PCSR0_PID17 (0x1 << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ -#define PMC_PCSR0_PID18 (0x1 << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ -#define PMC_PCSR0_PID19 (0x1 << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ -#define PMC_PCSR0_PID20 (0x1 << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ -#define PMC_PCSR0_PID21 (0x1 << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ -#define PMC_PCSR0_PID22 (0x1 << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ -#define PMC_PCSR0_PID23 (0x1 << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ -#define PMC_PCSR0_PID24 (0x1 << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ -#define PMC_PCSR0_PID25 (0x1 << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ -#define PMC_PCSR0_PID26 (0x1 << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ -#define PMC_PCSR0_PID27 (0x1 << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ -#define PMC_PCSR0_PID28 (0x1 << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ -#define PMC_PCSR0_PID29 (0x1 << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ -#define PMC_PCSR0_PID30 (0x1 << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ -#define PMC_PCSR0_PID31 (0x1 << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ -/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ -#define CKGR_MOR_MOSCXTEN (0x1 << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */ -#define CKGR_MOR_MOSCXTBY (0x1 << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */ -#define CKGR_MOR_WAITMODE (0x1 << 2) /**< \brief (CKGR_MOR) Wait Mode Command */ -#define CKGR_MOR_MOSCRCEN (0x1 << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */ -#define CKGR_MOR_MOSCRCF (0x7 << 4) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */ -#define CKGR_MOR_MOSCXTST (0xff << 8) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */ -#define CKGR_MOR_KEY (0xff << 16) /**< \brief (CKGR_MOR) Password */ -#define CKGR_MOR_MOSCSEL (0x1 << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */ -#define CKGR_MOR_CFDEN (0x1 << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ -/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ -#define CKGR_MCFR_MAINF (0xffff << 0) /**< \brief (CKGR_MCFR) Main Clock Frequency */ -#define CKGR_MCFR_MAINFRDY (0x1 << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */ -/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ -#define CKGR_PLLAR_DIVA (0xff << 0) /**< \brief (CKGR_PLLAR) Divider */ -#define CKGR_PLLAR_PLLACOUNT (0x3f << 8) /**< \brief (CKGR_PLLAR) PLLA Counter */ -#define CKGR_PLLAR_MULA (0x7ff << 16) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ -#define CKGR_PLLAR_STUCKTO1 (0x1 << 29) /**< \brief (CKGR_PLLAR) */ -/* -------- CKGR_PLLBR : (PMC Offset: 0x002C) PLLB Register -------- */ -#define CKGR_PLLBR_DIVB_Pos 0 -#define CKGR_PLLBR_DIVB_Msk (0xffu << CKGR_PLLBR_DIVB_Pos) /**< \brief (CKGR_PLLBR) Divider */ -#define CKGR_PLLBR_DIVB(value) ((CKGR_PLLBR_DIVB_Msk & ((value) << CKGR_PLLBR_DIVB_Pos))) -#define CKGR_PLLBR_PLLBCOUNT_Pos 8 -#define CKGR_PLLBR_PLLBCOUNT_Msk (0x3fu << CKGR_PLLBR_PLLBCOUNT_Pos) /**< \brief (CKGR_PLLBR) PLLB Counter */ -#define CKGR_PLLBR_PLLBCOUNT(value) ((CKGR_PLLBR_PLLBCOUNT_Msk & ((value) << CKGR_PLLBR_PLLBCOUNT_Pos))) -#define CKGR_PLLBR_MULB_Pos 16 -#define CKGR_PLLBR_MULB_Msk (0x7ffu << CKGR_PLLBR_MULB_Pos) /**< \brief (CKGR_PLLBR) PLLB Multiplier */ -#define CKGR_PLLBR_MULB(value) ((CKGR_PLLBR_MULB_Msk & ((value) << CKGR_PLLBR_MULB_Pos))) -/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ -#define PMC_MCKR_CSS (0x3 << 0) /**< \brief (PMC_MCKR) Master Clock Source Selection */ -#define PMC_MCKR_CSS_SLOW_CLK (0x0 << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ -#define PMC_MCKR_CSS_MAIN_CLK (0x1 << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ -#define PMC_MCKR_CSS_PLLA_CLK (0x2 << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ -#define PMC_MCKR_CSS_PLLB_CLK (0x3 << 0) /**< \brief (PMC_MCKR) PLLB Clock is selected */ -#define PMC_MCKR_PRES (0x7 << 4) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ -#define PMC_MCKR_PRES_CLK (0x0 << 4) /**< \brief (PMC_MCKR) Selected clock */ -#define PMC_MCKR_PRES_CLK_2 (0x1 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ -#define PMC_MCKR_PRES_CLK_4 (0x2 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ -#define PMC_MCKR_PRES_CLK_8 (0x3 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ -#define PMC_MCKR_PRES_CLK_16 (0x4 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ -#define PMC_MCKR_PRES_CLK_32 (0x5 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ -#define PMC_MCKR_PRES_CLK_64 (0x6 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ -#define PMC_MCKR_PLLADIV2 (0x1 << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */ -#define PMC_MCKR_PLLBDIV2 (0x1 << 13) /**< \brief (PMC_MCKR) PLLB Divisor by 2 */ -/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ -#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */ -#define PMC_USB_USBDIV_Pos 8 -#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock. */ -#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos))) -/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ -#define PMC_PCK_CSS (0x7 << 0) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */ -#define PMC_PCK_PRES (0x7 << 4) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */ -/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ -#define PMC_IER_MOSCXTS (0x1 << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ -#define PMC_IER_LOCKA (0x1 << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ -#define PMC_IER_LOCKB (0x1 << 2) /**< \brief (PMC_IER) PLLB Lock Interrupt Enable */ -#define PMC_IER_MCKRDY (0x1 << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ -#define PMC_IER_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ -#define PMC_IER_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ -#define PMC_IER_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ -#define PMC_IER_MOSCSELS (0x1 << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */ -#define PMC_IER_MOSCRCS (0x1 << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */ -#define PMC_IER_CFDEV (0x1 << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ -/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ -#define PMC_IDR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */ -#define PMC_IDR_LOCKA (0x1 << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ -#define PMC_IDR_LOCKB (0x1 << 2) /**< \brief (PMC_IDR) PLLB Lock Interrupt Disable */ -#define PMC_IDR_MCKRDY (0x1 << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ -#define PMC_IDR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ -#define PMC_IDR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ -#define PMC_IDR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ -#define PMC_IDR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */ -#define PMC_IDR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */ -#define PMC_IDR_CFDEV (0x1 << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ -/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ -#define PMC_SR_MOSCXTS (0x1 << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */ -#define PMC_SR_LOCKA (0x1 << 1) /**< \brief (PMC_SR) PLLA Lock Status */ -#define PMC_SR_LOCKB (0x1 << 2) /**< \brief (PMC_SR) PLLB Lock Status */ -#define PMC_SR_MCKRDY (0x1 << 3) /**< \brief (PMC_SR) Master Clock Status */ -#define PMC_SR_OSCSELS (0x1 << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */ -#define PMC_SR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_MOSCSELS (0x1 << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */ -#define PMC_SR_MOSCRCS (0x1 << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */ -#define PMC_SR_CFDEV (0x1 << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ -#define PMC_SR_CFDS (0x1 << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ -#define PMC_SR_FOS (0x1 << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ -/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ -#define PMC_IMR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */ -#define PMC_IMR_LOCKA (0x1 << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ -#define PMC_IMR_LOCKB (0x1 << 2) /**< \brief (PMC_IMR) PLLB Lock Interrupt Mask */ -#define PMC_IMR_MCKRDY (0x1 << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ -#define PMC_IMR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ -#define PMC_IMR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ -#define PMC_IMR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ -#define PMC_IMR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */ -#define PMC_IMR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */ -#define PMC_IMR_CFDEV (0x1 << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ -/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ -#define PMC_FSMR_FSTT0 (0x1 << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ -#define PMC_FSMR_FSTT1 (0x1 << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ -#define PMC_FSMR_FSTT2 (0x1 << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ -#define PMC_FSMR_FSTT3 (0x1 << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ -#define PMC_FSMR_FSTT4 (0x1 << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ -#define PMC_FSMR_FSTT5 (0x1 << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ -#define PMC_FSMR_FSTT6 (0x1 << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ -#define PMC_FSMR_FSTT7 (0x1 << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ -#define PMC_FSMR_FSTT8 (0x1 << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ -#define PMC_FSMR_FSTT9 (0x1 << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ -#define PMC_FSMR_FSTT10 (0x1 << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ -#define PMC_FSMR_FSTT11 (0x1 << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ -#define PMC_FSMR_FSTT12 (0x1 << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ -#define PMC_FSMR_FSTT13 (0x1 << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ -#define PMC_FSMR_FSTT14 (0x1 << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ -#define PMC_FSMR_FSTT15 (0x1 << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ -#define PMC_FSMR_RTTAL (0x1 << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ -#define PMC_FSMR_RTCAL (0x1 << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ -#define PMC_FSMR_USBAL (0x1 << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ -#define PMC_FSMR_LPM (0x1 << 20) /**< \brief (PMC_FSMR) Low Power Mode */ -/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ -#define PMC_FSPR_FSTP0 (0x1 << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP1 (0x1 << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP2 (0x1 << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP3 (0x1 << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP4 (0x1 << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP5 (0x1 << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP6 (0x1 << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP7 (0x1 << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP8 (0x1 << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP9 (0x1 << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP10 (0x1 << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP11 (0x1 << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP12 (0x1 << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP13 (0x1 << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP14 (0x1 << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP15 (0x1 << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ -#define PMC_FOCR_FOCLR (0x1 << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ -/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */ -#define PMC_WPMR_WPEN (0x1 << 0) /**< \brief (PMC_WPMR) Write Protect Enable */ -#define PMC_WPMR_WPKEY (0xffffff << 8) /**< \brief (PMC_WPMR) Write Protect KEY */ -/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */ -#define PMC_WPSR_WPVS (0x1 << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */ -#define PMC_WPSR_WPVSRC (0xffff << 8) /**< \brief (PMC_WPSR) Write Protect Violation Source */ -/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ -#define PMC_PCER1_PID32 (0x1 << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ -#define PMC_PCER1_PID33 (0x1 << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ -#define PMC_PCER1_PID34 (0x1 << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ -#define PMC_PCER1_PID35 (0x1 << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ -#define PMC_PCER1_PID36 (0x1 << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */ -#define PMC_PCER1_PID37 (0x1 << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ -#define PMC_PCER1_PID38 (0x1 << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */ -#define PMC_PCER1_PID39 (0x1 << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ -#define PMC_PCER1_PID40 (0x1 << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ -#define PMC_PCER1_PID41 (0x1 << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ -#define PMC_PCER1_PID42 (0x1 << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ -#define PMC_PCER1_PID43 (0x1 << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ -#define PMC_PCER1_PID44 (0x1 << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ -#define PMC_PCER1_PID45 (0x1 << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ -#define PMC_PCER1_PID46 (0x1 << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ -#define PMC_PCER1_PID47 (0x1 << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ -#define PMC_PCER1_PID48 (0x1 << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */ -#define PMC_PCER1_PID49 (0x1 << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */ -#define PMC_PCER1_PID50 (0x1 << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */ -#define PMC_PCER1_PID51 (0x1 << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */ -#define PMC_PCER1_PID52 (0x1 << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */ -#define PMC_PCER1_PID53 (0x1 << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */ -#define PMC_PCER1_PID54 (0x1 << 22) /**< \brief (PMC_PCER1) Peripheral Clock 54 Enable */ -#define PMC_PCER1_PID55 (0x1 << 23) /**< \brief (PMC_PCER1) Peripheral Clock 55 Enable */ -#define PMC_PCER1_PID56 (0x1 << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */ -#define PMC_PCER1_PID57 (0x1 << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */ -#define PMC_PCER1_PID58 (0x1 << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */ -#define PMC_PCER1_PID59 (0x1 << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */ -#define PMC_PCER1_PID60 (0x1 << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */ -#define PMC_PCER1_PID61 (0x1 << 29) /**< \brief (PMC_PCER1) Peripheral Clock 61 Enable */ -#define PMC_PCER1_PID62 (0x1 << 30) /**< \brief (PMC_PCER1) Peripheral Clock 62 Enable */ -#define PMC_PCER1_PID63 (0x1 << 31) /**< \brief (PMC_PCER1) Peripheral Clock 63 Enable */ -/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ -#define PMC_PCDR1_PID32 (0x1 << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ -#define PMC_PCDR1_PID33 (0x1 << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ -#define PMC_PCDR1_PID34 (0x1 << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ -#define PMC_PCDR1_PID35 (0x1 << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ -#define PMC_PCDR1_PID36 (0x1 << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */ -#define PMC_PCDR1_PID37 (0x1 << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ -#define PMC_PCDR1_PID38 (0x1 << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */ -#define PMC_PCDR1_PID39 (0x1 << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ -#define PMC_PCDR1_PID40 (0x1 << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ -#define PMC_PCDR1_PID41 (0x1 << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ -#define PMC_PCDR1_PID42 (0x1 << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ -#define PMC_PCDR1_PID43 (0x1 << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ -#define PMC_PCDR1_PID44 (0x1 << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ -#define PMC_PCDR1_PID45 (0x1 << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ -#define PMC_PCDR1_PID46 (0x1 << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ -#define PMC_PCDR1_PID47 (0x1 << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ -#define PMC_PCDR1_PID48 (0x1 << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */ -#define PMC_PCDR1_PID49 (0x1 << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */ -#define PMC_PCDR1_PID50 (0x1 << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */ -#define PMC_PCDR1_PID51 (0x1 << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */ -#define PMC_PCDR1_PID52 (0x1 << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */ -#define PMC_PCDR1_PID53 (0x1 << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */ -#define PMC_PCDR1_PID54 (0x1 << 22) /**< \brief (PMC_PCDR1) Peripheral Clock 54 Disable */ -#define PMC_PCDR1_PID55 (0x1 << 23) /**< \brief (PMC_PCDR1) Peripheral Clock 55 Disable */ -#define PMC_PCDR1_PID56 (0x1 << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */ -#define PMC_PCDR1_PID57 (0x1 << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */ -#define PMC_PCDR1_PID58 (0x1 << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */ -#define PMC_PCDR1_PID59 (0x1 << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */ -#define PMC_PCDR1_PID60 (0x1 << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */ -#define PMC_PCDR1_PID61 (0x1 << 29) /**< \brief (PMC_PCDR1) Peripheral Clock 61 Disable */ -#define PMC_PCDR1_PID62 (0x1 << 30) /**< \brief (PMC_PCDR1) Peripheral Clock 62 Disable */ -#define PMC_PCDR1_PID63 (0x1 << 31) /**< \brief (PMC_PCDR1) Peripheral Clock 63 Disable */ -/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ -#define PMC_PCSR1_PID32 (0x1 << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ -#define PMC_PCSR1_PID33 (0x1 << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ -#define PMC_PCSR1_PID34 (0x1 << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ -#define PMC_PCSR1_PID35 (0x1 << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ -#define PMC_PCSR1_PID36 (0x1 << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */ -#define PMC_PCSR1_PID37 (0x1 << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ -#define PMC_PCSR1_PID38 (0x1 << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */ -#define PMC_PCSR1_PID39 (0x1 << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ -#define PMC_PCSR1_PID40 (0x1 << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ -#define PMC_PCSR1_PID41 (0x1 << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ -#define PMC_PCSR1_PID42 (0x1 << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ -#define PMC_PCSR1_PID43 (0x1 << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ -#define PMC_PCSR1_PID44 (0x1 << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ -#define PMC_PCSR1_PID45 (0x1 << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ -#define PMC_PCSR1_PID46 (0x1 << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ -#define PMC_PCSR1_PID47 (0x1 << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ -#define PMC_PCSR1_PID48 (0x1 << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */ -#define PMC_PCSR1_PID49 (0x1 << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */ -#define PMC_PCSR1_PID50 (0x1 << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */ -#define PMC_PCSR1_PID51 (0x1 << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */ -#define PMC_PCSR1_PID52 (0x1 << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */ -#define PMC_PCSR1_PID53 (0x1 << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */ -#define PMC_PCSR1_PID54 (0x1 << 22) /**< \brief (PMC_PCSR1) Peripheral Clock 54 Status */ -#define PMC_PCSR1_PID55 (0x1 << 23) /**< \brief (PMC_PCSR1) Peripheral Clock 55 Status */ -#define PMC_PCSR1_PID56 (0x1 << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */ -#define PMC_PCSR1_PID57 (0x1 << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */ -#define PMC_PCSR1_PID58 (0x1 << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */ -#define PMC_PCSR1_PID59 (0x1 << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */ -#define PMC_PCSR1_PID60 (0x1 << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */ -#define PMC_PCSR1_PID61 (0x1 << 29) /**< \brief (PMC_PCSR1) Peripheral Clock 61 Status */ -#define PMC_PCSR1_PID62 (0x1 << 30) /**< \brief (PMC_PCSR1) Peripheral Clock 62 Status */ -#define PMC_PCSR1_PID63 (0x1 << 31) /**< \brief (PMC_PCSR1) Peripheral Clock 63 Status */ -/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ -#define PMC_OCR_CAL4 (0x7f << 0) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 Mhz */ -#define PMC_OCR_SEL4 (0x1 << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 Mhz */ -#define PMC_OCR_CAL8 (0x7f << 8) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 Mhz */ -#define PMC_OCR_SEL8 (0x1 << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 Mhz */ -#define PMC_OCR_CAL12 (0x7f << 16) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 Mhz */ -#define PMC_OCR_SEL12 (0x1 << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 Mhz */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PWM Pulse Width Modulation Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief PwmCh_num hardware registers */ -typedef struct { - RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ - RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ - RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ - RwReg PWM_CPDR; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ - RwReg PWM_CPDRUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ - RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ - RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ - RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ -} PwmCh_num; -/** \brief Pwm hardware registers */ -typedef struct { - RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ - WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ - WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ - RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ - WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ - WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ - RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ - RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ - RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ - RwReg Reserved1[1]; - RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ - RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ - WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ - WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ - WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ - RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ - RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ - RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ - RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ - WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ - WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ - WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ - WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ - RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ - RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ - WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ - RwReg PWM_FPV; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */ - RwReg PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ - RwReg Reserved2[3]; - RwReg PWM_ELxMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ - RwReg Reserved3[11]; - RwReg PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */ - RwReg Reserved4[12]; - WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */ - RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */ - RwReg Reserved5[5]; - RwReg PWM_RPR; /**< \brief (Pwm Offset: 0x100) Receive Pointer Register */ - RwReg PWM_RCR; /**< \brief (Pwm Offset: 0x104) Receive Counter Register */ - RwReg PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */ - RwReg PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */ - RwReg PWM_RNPR; /**< \brief (Pwm Offset: 0x110) Receive Next Pointer Register */ - RwReg PWM_RNCR; /**< \brief (Pwm Offset: 0x114) Receive Next Counter Register */ - RwReg PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */ - RwReg PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */ - WoReg PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */ - RoReg PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */ - RwReg Reserved6[2]; - RwReg PWM_CMP0V; /**< \brief (Pwm Offset: 0x130) PWM Comparison 0 Value Register */ - WoReg PWM_CMP0VUPD; /**< \brief (Pwm Offset: 0x134) PWM Comparison 0 Value Update Register */ - RwReg PWM_CMP0M; /**< \brief (Pwm Offset: 0x138) PWM Comparison 0 Mode Register */ - WoReg PWM_CMP0MUPD; /**< \brief (Pwm Offset: 0x13C) PWM Comparison 0 Mode Update Register */ - RwReg PWM_CMP1V; /**< \brief (Pwm Offset: 0x140) PWM Comparison 1 Value Register */ - WoReg PWM_CMP1VUPD; /**< \brief (Pwm Offset: 0x144) PWM Comparison 1 Value Update Register */ - RwReg PWM_CMP1M; /**< \brief (Pwm Offset: 0x148) PWM Comparison 1 Mode Register */ - WoReg PWM_CMP1MUPD; /**< \brief (Pwm Offset: 0x14C) PWM Comparison 1 Mode Update Register */ - RwReg PWM_CMP2V; /**< \brief (Pwm Offset: 0x150) PWM Comparison 2 Value Register */ - WoReg PWM_CMP2VUPD; /**< \brief (Pwm Offset: 0x154) PWM Comparison 2 Value Update Register */ - RwReg PWM_CMP2M; /**< \brief (Pwm Offset: 0x158) PWM Comparison 2 Mode Register */ - WoReg PWM_CMP2MUPD; /**< \brief (Pwm Offset: 0x15C) PWM Comparison 2 Mode Update Register */ - RwReg PWM_CMP3V; /**< \brief (Pwm Offset: 0x160) PWM Comparison 3 Value Register */ - WoReg PWM_CMP3VUPD; /**< \brief (Pwm Offset: 0x164) PWM Comparison 3 Value Update Register */ - RwReg PWM_CMP3M; /**< \brief (Pwm Offset: 0x168) PWM Comparison 3 Mode Register */ - WoReg PWM_CMP3MUPD; /**< \brief (Pwm Offset: 0x16C) PWM Comparison 3 Mode Update Register */ - RwReg PWM_CMP4V; /**< \brief (Pwm Offset: 0x170) PWM Comparison 4 Value Register */ - WoReg PWM_CMP4VUPD; /**< \brief (Pwm Offset: 0x174) PWM Comparison 4 Value Update Register */ - RwReg PWM_CMP4M; /**< \brief (Pwm Offset: 0x178) PWM Comparison 4 Mode Register */ - WoReg PWM_CMP4MUPD; /**< \brief (Pwm Offset: 0x17C) PWM Comparison 4 Mode Update Register */ - RwReg PWM_CMP5V; /**< \brief (Pwm Offset: 0x180) PWM Comparison 5 Value Register */ - WoReg PWM_CMP5VUPD; /**< \brief (Pwm Offset: 0x184) PWM Comparison 5 Value Update Register */ - RwReg PWM_CMP5M; /**< \brief (Pwm Offset: 0x188) PWM Comparison 5 Mode Register */ - WoReg PWM_CMP5MUPD; /**< \brief (Pwm Offset: 0x18C) PWM Comparison 5 Mode Update Register */ - RwReg PWM_CMP6V; /**< \brief (Pwm Offset: 0x190) PWM Comparison 6 Value Register */ - WoReg PWM_CMP6VUPD; /**< \brief (Pwm Offset: 0x194) PWM Comparison 6 Value Update Register */ - RwReg PWM_CMP6M; /**< \brief (Pwm Offset: 0x198) PWM Comparison 6 Mode Register */ - WoReg PWM_CMP6MUPD; /**< \brief (Pwm Offset: 0x19C) PWM Comparison 6 Mode Update Register */ - RwReg PWM_CMP7V; /**< \brief (Pwm Offset: 0x1A0) PWM Comparison 7 Value Register */ - WoReg PWM_CMP7VUPD; /**< \brief (Pwm Offset: 0x1A4) PWM Comparison 7 Value Update Register */ - RwReg PWM_CMP7M; /**< \brief (Pwm Offset: 0x1A8) PWM Comparison 7 Mode Register */ - WoReg PWM_CMP7MUPD; /**< \brief (Pwm Offset: 0x1AC) PWM Comparison 7 Mode Update Register */ - RwReg Reserved7[20]; - PwmCh_num PWM_CH_NUM[4]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ -} Pwm; -#endif /* __ASSEMBLY__ */ -/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ -#define PWM_CLK_DIVA (0xff << 0) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ -#define PWM_CLK_PREA (0xf << 8) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ -#define PWM_CLK_DIVB (0xff << 16) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ -#define PWM_CLK_PREB (0xf << 24) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ -/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ -#define PWM_ENA_CHID0 (0x1 << 0) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID1 (0x1 << 1) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID2 (0x1 << 2) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID3 (0x1 << 3) /**< \brief (PWM_ENA) Channel ID */ -/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ -#define PWM_DIS_CHID0 (0x1 << 0) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID1 (0x1 << 1) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID2 (0x1 << 2) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID3 (0x1 << 3) /**< \brief (PWM_DIS) Channel ID */ -/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ -#define PWM_SR_CHID0 (0x1 << 0) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID1 (0x1 << 1) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID2 (0x1 << 2) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID3 (0x1 << 3) /**< \brief (PWM_SR) Channel ID */ -/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ -#define PWM_IER1_CHID0 (0x1 << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ -#define PWM_IER1_CHID1 (0x1 << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ -#define PWM_IER1_CHID2 (0x1 << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ -#define PWM_IER1_CHID3 (0x1 << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ -#define PWM_IER1_FCHID0 (0x1 << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ -#define PWM_IER1_FCHID1 (0x1 << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ -#define PWM_IER1_FCHID2 (0x1 << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ -#define PWM_IER1_FCHID3 (0x1 << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ -/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ -#define PWM_IDR1_CHID0 (0x1 << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ -#define PWM_IDR1_CHID1 (0x1 << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ -#define PWM_IDR1_CHID2 (0x1 << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ -#define PWM_IDR1_CHID3 (0x1 << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ -#define PWM_IDR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ -#define PWM_IDR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ -#define PWM_IDR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ -#define PWM_IDR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ -/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ -#define PWM_IMR1_CHID0 (0x1 << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ -#define PWM_IMR1_CHID1 (0x1 << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ -#define PWM_IMR1_CHID2 (0x1 << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ -#define PWM_IMR1_CHID3 (0x1 << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ -#define PWM_IMR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ -#define PWM_IMR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ -#define PWM_IMR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ -#define PWM_IMR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ -/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ -#define PWM_ISR1_CHID0 (0x1 << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ -#define PWM_ISR1_CHID1 (0x1 << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ -#define PWM_ISR1_CHID2 (0x1 << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ -#define PWM_ISR1_CHID3 (0x1 << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ -#define PWM_ISR1_FCHID0 (0x1 << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ -#define PWM_ISR1_FCHID1 (0x1 << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ -#define PWM_ISR1_FCHID2 (0x1 << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ -#define PWM_ISR1_FCHID3 (0x1 << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ -/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ -#define PWM_SCM_SYNC0 (0x1 << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ -#define PWM_SCM_SYNC1 (0x1 << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ -#define PWM_SCM_SYNC2 (0x1 << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ -#define PWM_SCM_SYNC3 (0x1 << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ -#define PWM_SCM_UPDM (0x3 << 16) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ -#define PWM_SCM_PTRM (0x1 << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */ -#define PWM_SCM_PTRCS (0x7 << 21) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */ -/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ -#define PWM_SCUC_UPDULOCK (0x1 << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ -/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ -#define PWM_SCUP_UPR (0xf << 0) /**< \brief (PWM_SCUP) Update Period */ -#define PWM_SCUP_UPRCNT (0xf << 4) /**< \brief (PWM_SCUP) Update Period Counter */ -/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ -#define PWM_SCUPUPD_UPRUPD (0xf << 0) /**< \brief (PWM_SCUPUPD) Update Period Update */ -/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ -#define PWM_IER2_WRDY (0x1 << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ -#define PWM_IER2_ENDTX (0x1 << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */ -#define PWM_IER2_TXBUFE (0x1 << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */ -#define PWM_IER2_UNRE (0x1 << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ -#define PWM_IER2_CMPM0 (0x1 << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ -#define PWM_IER2_CMPM1 (0x1 << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ -#define PWM_IER2_CMPM2 (0x1 << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ -#define PWM_IER2_CMPM3 (0x1 << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ -#define PWM_IER2_CMPM4 (0x1 << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ -#define PWM_IER2_CMPM5 (0x1 << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ -#define PWM_IER2_CMPM6 (0x1 << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ -#define PWM_IER2_CMPM7 (0x1 << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ -#define PWM_IER2_CMPU0 (0x1 << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ -#define PWM_IER2_CMPU1 (0x1 << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ -#define PWM_IER2_CMPU2 (0x1 << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ -#define PWM_IER2_CMPU3 (0x1 << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ -#define PWM_IER2_CMPU4 (0x1 << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ -#define PWM_IER2_CMPU5 (0x1 << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ -#define PWM_IER2_CMPU6 (0x1 << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ -#define PWM_IER2_CMPU7 (0x1 << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ -/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ -#define PWM_IDR2_WRDY (0x1 << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ -#define PWM_IDR2_ENDTX (0x1 << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */ -#define PWM_IDR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */ -#define PWM_IDR2_UNRE (0x1 << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ -#define PWM_IDR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ -#define PWM_IDR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ -#define PWM_IDR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ -#define PWM_IDR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ -#define PWM_IDR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ -#define PWM_IDR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ -#define PWM_IDR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ -#define PWM_IDR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ -#define PWM_IDR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ -#define PWM_IDR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ -#define PWM_IDR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ -#define PWM_IDR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ -#define PWM_IDR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ -#define PWM_IDR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ -#define PWM_IDR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ -#define PWM_IDR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ -/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ -#define PWM_IMR2_WRDY (0x1 << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ -#define PWM_IMR2_ENDTX (0x1 << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */ -#define PWM_IMR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */ -#define PWM_IMR2_UNRE (0x1 << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ -#define PWM_IMR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ -#define PWM_IMR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ -#define PWM_IMR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ -#define PWM_IMR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ -#define PWM_IMR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ -#define PWM_IMR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ -#define PWM_IMR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ -#define PWM_IMR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ -#define PWM_IMR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ -#define PWM_IMR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ -#define PWM_IMR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ -#define PWM_IMR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ -#define PWM_IMR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ -#define PWM_IMR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ -#define PWM_IMR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ -#define PWM_IMR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ -/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ -#define PWM_ISR2_WRDY (0x1 << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ -#define PWM_ISR2_ENDTX (0x1 << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */ -#define PWM_ISR2_TXBUFE (0x1 << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */ -#define PWM_ISR2_UNRE (0x1 << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ -#define PWM_ISR2_CMPM0 (0x1 << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ -#define PWM_ISR2_CMPM1 (0x1 << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ -#define PWM_ISR2_CMPM2 (0x1 << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ -#define PWM_ISR2_CMPM3 (0x1 << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ -#define PWM_ISR2_CMPM4 (0x1 << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ -#define PWM_ISR2_CMPM5 (0x1 << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ -#define PWM_ISR2_CMPM6 (0x1 << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ -#define PWM_ISR2_CMPM7 (0x1 << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ -#define PWM_ISR2_CMPU0 (0x1 << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ -#define PWM_ISR2_CMPU1 (0x1 << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ -#define PWM_ISR2_CMPU2 (0x1 << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ -#define PWM_ISR2_CMPU3 (0x1 << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ -#define PWM_ISR2_CMPU4 (0x1 << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ -#define PWM_ISR2_CMPU5 (0x1 << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ -#define PWM_ISR2_CMPU6 (0x1 << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ -#define PWM_ISR2_CMPU7 (0x1 << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ -/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ -#define PWM_OOV_OOVH0 (0x1 << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ -#define PWM_OOV_OOVH1 (0x1 << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ -#define PWM_OOV_OOVH2 (0x1 << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ -#define PWM_OOV_OOVH3 (0x1 << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ -#define PWM_OOV_OOVL0 (0x1 << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ -#define PWM_OOV_OOVL1 (0x1 << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ -#define PWM_OOV_OOVL2 (0x1 << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ -#define PWM_OOV_OOVL3 (0x1 << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ -/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ -#define PWM_OS_OSH0 (0x1 << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ -#define PWM_OS_OSH1 (0x1 << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ -#define PWM_OS_OSH2 (0x1 << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ -#define PWM_OS_OSH3 (0x1 << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ -#define PWM_OS_OSL0 (0x1 << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ -#define PWM_OS_OSL1 (0x1 << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ -#define PWM_OS_OSL2 (0x1 << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ -#define PWM_OS_OSL3 (0x1 << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ -/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ -#define PWM_OSS_OSSH0 (0x1 << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ -#define PWM_OSS_OSSH1 (0x1 << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ -#define PWM_OSS_OSSH2 (0x1 << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ -#define PWM_OSS_OSSH3 (0x1 << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ -#define PWM_OSS_OSSL0 (0x1 << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ -#define PWM_OSS_OSSL1 (0x1 << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ -#define PWM_OSS_OSSL2 (0x1 << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ -#define PWM_OSS_OSSL3 (0x1 << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ -/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ -#define PWM_OSC_OSCH0 (0x1 << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ -#define PWM_OSC_OSCH1 (0x1 << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ -#define PWM_OSC_OSCH2 (0x1 << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ -#define PWM_OSC_OSCH3 (0x1 << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ -#define PWM_OSC_OSCL0 (0x1 << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ -#define PWM_OSC_OSCL1 (0x1 << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ -#define PWM_OSC_OSCL2 (0x1 << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ -#define PWM_OSC_OSCL3 (0x1 << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ -/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ -#define PWM_OSSUPD_OSSUPH0 (0x1 << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ -#define PWM_OSSUPD_OSSUPH1 (0x1 << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ -#define PWM_OSSUPD_OSSUPH2 (0x1 << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ -#define PWM_OSSUPD_OSSUPH3 (0x1 << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ -#define PWM_OSSUPD_OSSUPL0 (0x1 << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ -#define PWM_OSSUPD_OSSUPL1 (0x1 << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ -#define PWM_OSSUPD_OSSUPL2 (0x1 << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ -#define PWM_OSSUPD_OSSUPL3 (0x1 << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ -/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ -#define PWM_OSCUPD_OSCUPH0 (0x1 << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ -#define PWM_OSCUPD_OSCUPH1 (0x1 << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ -#define PWM_OSCUPD_OSCUPH2 (0x1 << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ -#define PWM_OSCUPD_OSCUPH3 (0x1 << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ -#define PWM_OSCUPD_OSCUPL0 (0x1 << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ -#define PWM_OSCUPD_OSCUPL1 (0x1 << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ -#define PWM_OSCUPD_OSCUPL2 (0x1 << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ -#define PWM_OSCUPD_OSCUPL3 (0x1 << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ -/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ -#define PWM_FMR_FPOL0 (0x1 << 0) /**< \brief (PWM_FMR) Fault 0 Polarity */ -#define PWM_FMR_FPOL1 (0x1 << 1) /**< \brief (PWM_FMR) Fault 1 Polarity */ -#define PWM_FMR_FPOL2 (0x1 << 2) /**< \brief (PWM_FMR) Fault 2 Polarity */ -#define PWM_FMR_FPOL3 (0x1 << 3) /**< \brief (PWM_FMR) Fault 3 Polarity */ -#define PWM_FMR_FMOD0 (0x1 << 8) /**< \brief (PWM_FMR) Fault 0 Activation Mode */ -#define PWM_FMR_FMOD1 (0x1 << 9) /**< \brief (PWM_FMR) Fault 1 Activation Mode */ -#define PWM_FMR_FMOD2 (0x1 << 10) /**< \brief (PWM_FMR) Fault 2 Activation Mode */ -#define PWM_FMR_FMOD3 (0x1 << 11) /**< \brief (PWM_FMR) Fault 3 Activation Mode */ -#define PWM_FMR_FFIL0 (0x1 << 16) /**< \brief (PWM_FMR) Fault 0 Filtering */ -#define PWM_FMR_FFIL1 (0x1 << 17) /**< \brief (PWM_FMR) Fault 1 Filtering */ -#define PWM_FMR_FFIL2 (0x1 << 18) /**< \brief (PWM_FMR) Fault 2 Filtering */ -#define PWM_FMR_FFIL3 (0x1 << 19) /**< \brief (PWM_FMR) Fault 3 Filtering */ -/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ -#define PWM_FSR_FIV0 (0x1 << 0) /**< \brief (PWM_FSR) Fault Input 0 Value */ -#define PWM_FSR_FIV1 (0x1 << 1) /**< \brief (PWM_FSR) Fault Input 1 Value */ -#define PWM_FSR_FIV2 (0x1 << 2) /**< \brief (PWM_FSR) Fault Input 2 Value */ -#define PWM_FSR_FIV3 (0x1 << 3) /**< \brief (PWM_FSR) Fault Input 3 Value */ -#define PWM_FSR_FS0 (0x1 << 8) /**< \brief (PWM_FSR) Fault 0 Status */ -#define PWM_FSR_FS1 (0x1 << 9) /**< \brief (PWM_FSR) Fault 1 Status */ -#define PWM_FSR_FS2 (0x1 << 10) /**< \brief (PWM_FSR) Fault 2 Status */ -#define PWM_FSR_FS3 (0x1 << 11) /**< \brief (PWM_FSR) Fault 3 Status */ -/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ -#define PWM_FCR_FCLR0 (0x1 << 0) /**< \brief (PWM_FCR) Fault 0 Clear */ -#define PWM_FCR_FCLR1 (0x1 << 1) /**< \brief (PWM_FCR) Fault 1 Clear */ -#define PWM_FCR_FCLR2 (0x1 << 2) /**< \brief (PWM_FCR) Fault 2 Clear */ -#define PWM_FCR_FCLR3 (0x1 << 3) /**< \brief (PWM_FCR) Fault 3 Clear */ -/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */ -#define PWM_FPV_FPVH0 (0x1 << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */ -#define PWM_FPV_FPVH1 (0x1 << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */ -#define PWM_FPV_FPVH2 (0x1 << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */ -#define PWM_FPV_FPVH3 (0x1 << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */ -#define PWM_FPV_FPVL0 (0x1 << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */ -#define PWM_FPV_FPVL1 (0x1 << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */ -#define PWM_FPV_FPVL2 (0x1 << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */ -#define PWM_FPV_FPVL3 (0x1 << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */ -/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ -#define PWM_FPE_FPE0 (0xff << 0) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 0 for channel x */ -#define PWM_FPE_FPE1 (0xff << 8) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 1 for channel x */ -#define PWM_FPE_FPE2 (0xff << 16) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 2 for channel x */ -#define PWM_FPE_FPE3 (0xff << 24) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 3 for channel x */ -/* -------- PWM_ELxMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ -#define PWM_ELxMR_CSEL0 (0x1 << 0) /**< \brief (PWM_ELxMR[2]) Comparison 0 Selection */ -#define PWM_ELxMR_CSEL1 (0x1 << 1) /**< \brief (PWM_ELxMR[2]) Comparison 1 Selection */ -#define PWM_ELxMR_CSEL2 (0x1 << 2) /**< \brief (PWM_ELxMR[2]) Comparison 2 Selection */ -#define PWM_ELxMR_CSEL3 (0x1 << 3) /**< \brief (PWM_ELxMR[2]) Comparison 3 Selection */ -#define PWM_ELxMR_CSEL4 (0x1 << 4) /**< \brief (PWM_ELxMR[2]) Comparison 4 Selection */ -#define PWM_ELxMR_CSEL5 (0x1 << 5) /**< \brief (PWM_ELxMR[2]) Comparison 5 Selection */ -#define PWM_ELxMR_CSEL6 (0x1 << 6) /**< \brief (PWM_ELxMR[2]) Comparison 6 Selection */ -#define PWM_ELxMR_CSEL7 (0x1 << 7) /**< \brief (PWM_ELxMR[2]) Comparison 7 Selection */ -/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */ -#define PWM_SMMR_GCEN0 (0x1 << 0) /**< \brief (PWM_SMMR) Gray Count ENable */ -#define PWM_SMMR_GCEN1 (0x1 << 1) /**< \brief (PWM_SMMR) Gray Count ENable */ -#define PWM_SMMR_DOWN0 (0x1 << 16) /**< \brief (PWM_SMMR) DOWN Count */ -#define PWM_SMMR_DOWN1 (0x1 << 17) /**< \brief (PWM_SMMR) DOWN Count */ -/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */ -#define PWM_WPCR_WPCMD (0x3 << 0) /**< \brief (PWM_WPCR) Write Protect Command */ -#define PWM_WPCR_WPRG0 (0x1 << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */ -#define PWM_WPCR_WPRG1 (0x1 << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */ -#define PWM_WPCR_WPRG2 (0x1 << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */ -#define PWM_WPCR_WPRG3 (0x1 << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */ -#define PWM_WPCR_WPRG4 (0x1 << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */ -#define PWM_WPCR_WPRG5 (0x1 << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */ -#define PWM_WPCR_WPKEY (0xffffff << 8) /**< \brief (PWM_WPCR) Write Protect Key */ -/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */ -#define PWM_WPSR_WPSWS0 (0x1 << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS1 (0x1 << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS2 (0x1 << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS3 (0x1 << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS4 (0x1 << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS5 (0x1 << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPVS (0x1 << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ -#define PWM_WPSR_WPHWS0 (0x1 << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS1 (0x1 << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS2 (0x1 << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS3 (0x1 << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS4 (0x1 << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS5 (0x1 << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPVSRC (0xffff << 16) /**< \brief (PWM_WPSR) Write Protect Violation Source */ -/* -------- PWM_RPR : (PWM Offset: 0x100) Receive Pointer Register -------- */ -#define PWM_RPR_RXPTR (0xffffffff << 0) /**< \brief (PWM_RPR) Receive Pointer Register */ -/* -------- PWM_RCR : (PWM Offset: 0x104) Receive Counter Register -------- */ -#define PWM_RCR_RXCTR (0xffff << 0) /**< \brief (PWM_RCR) Receive Counter Register */ -/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */ -#define PWM_TPR_TXPTR (0xffffffff << 0) /**< \brief (PWM_TPR) Transmit Counter Register */ -/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */ -#define PWM_TCR_TXCTR (0xffff << 0) /**< \brief (PWM_TCR) Transmit Counter Register */ -/* -------- PWM_RNPR : (PWM Offset: 0x110) Receive Next Pointer Register -------- */ -#define PWM_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PWM_RNPR) Receive Next Pointer */ -/* -------- PWM_RNCR : (PWM Offset: 0x114) Receive Next Counter Register -------- */ -#define PWM_RNCR_RXNCTR (0xffff << 0) /**< \brief (PWM_RNCR) Receive Next Counter */ -/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */ -#define PWM_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PWM_TNPR) Transmit Next Pointer */ -/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */ -#define PWM_TNCR_TXNCTR (0xffff << 0) /**< \brief (PWM_TNCR) Transmit Counter Next */ -/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */ -#define PWM_PTCR_RXTEN (0x1 << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */ -#define PWM_PTCR_RXTDIS (0x1 << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */ -#define PWM_PTCR_TXTEN (0x1 << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */ -#define PWM_PTCR_TXTDIS (0x1 << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */ -/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */ -#define PWM_PTSR_RXTEN (0x1 << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */ -#define PWM_PTSR_TXTEN (0x1 << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */ -/* -------- PWM_CMP0V : (PWM Offset: 0x130) PWM Comparison 0 Value Register -------- */ -#define PWM_CMP0V_CV (0xffffff << 0) /**< \brief (PWM_CMP0V) Comparison x Value */ -#define PWM_CMP0V_CVM (0x1 << 24) /**< \brief (PWM_CMP0V) Comparison x Value Mode */ -/* -------- PWM_CMP0VUPD : (PWM Offset: 0x134) PWM Comparison 0 Value Update Register -------- */ -#define PWM_CMP0VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP0VUPD) Comparison x Value Update */ -#define PWM_CMP0VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP0VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP0M : (PWM Offset: 0x138) PWM Comparison 0 Mode Register -------- */ -#define PWM_CMP0M_CEN (0x1 << 0) /**< \brief (PWM_CMP0M) Comparison x Enable */ -#define PWM_CMP0M_CTR (0xf << 4) /**< \brief (PWM_CMP0M) Comparison x Trigger */ -#define PWM_CMP0M_CPR (0xf << 8) /**< \brief (PWM_CMP0M) Comparison x Period */ -#define PWM_CMP0M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP0M) Comparison x Period Counter */ -#define PWM_CMP0M_CUPR (0xf << 16) /**< \brief (PWM_CMP0M) Comparison x Update Period */ -#define PWM_CMP0M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP0M) Comparison x Update Period Counter */ -/* -------- PWM_CMP0MUPD : (PWM Offset: 0x13C) PWM Comparison 0 Mode Update Register -------- */ -#define PWM_CMP0MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP0MUPD) Comparison x Enable Update */ -#define PWM_CMP0MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP0MUPD) Comparison x Trigger Update */ -#define PWM_CMP0MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP0MUPD) Comparison x Period Update */ -#define PWM_CMP0MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP0MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP1V : (PWM Offset: 0x140) PWM Comparison 1 Value Register -------- */ -#define PWM_CMP1V_CV (0xffffff << 0) /**< \brief (PWM_CMP1V) Comparison x Value */ -#define PWM_CMP1V_CVM (0x1 << 24) /**< \brief (PWM_CMP1V) Comparison x Value Mode */ -/* -------- PWM_CMP1VUPD : (PWM Offset: 0x144) PWM Comparison 1 Value Update Register -------- */ -#define PWM_CMP1VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP1VUPD) Comparison x Value Update */ -#define PWM_CMP1VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP1VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP1M : (PWM Offset: 0x148) PWM Comparison 1 Mode Register -------- */ -#define PWM_CMP1M_CEN (0x1 << 0) /**< \brief (PWM_CMP1M) Comparison x Enable */ -#define PWM_CMP1M_CTR (0xf << 4) /**< \brief (PWM_CMP1M) Comparison x Trigger */ -#define PWM_CMP1M_CPR (0xf << 8) /**< \brief (PWM_CMP1M) Comparison x Period */ -#define PWM_CMP1M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP1M) Comparison x Period Counter */ -#define PWM_CMP1M_CUPR (0xf << 16) /**< \brief (PWM_CMP1M) Comparison x Update Period */ -#define PWM_CMP1M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP1M) Comparison x Update Period Counter */ -/* -------- PWM_CMP1MUPD : (PWM Offset: 0x14C) PWM Comparison 1 Mode Update Register -------- */ -#define PWM_CMP1MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP1MUPD) Comparison x Enable Update */ -#define PWM_CMP1MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP1MUPD) Comparison x Trigger Update */ -#define PWM_CMP1MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP1MUPD) Comparison x Period Update */ -#define PWM_CMP1MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP1MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP2V : (PWM Offset: 0x150) PWM Comparison 2 Value Register -------- */ -#define PWM_CMP2V_CV (0xffffff << 0) /**< \brief (PWM_CMP2V) Comparison x Value */ -#define PWM_CMP2V_CVM (0x1 << 24) /**< \brief (PWM_CMP2V) Comparison x Value Mode */ -/* -------- PWM_CMP2VUPD : (PWM Offset: 0x154) PWM Comparison 2 Value Update Register -------- */ -#define PWM_CMP2VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP2VUPD) Comparison x Value Update */ -#define PWM_CMP2VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP2VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP2M : (PWM Offset: 0x158) PWM Comparison 2 Mode Register -------- */ -#define PWM_CMP2M_CEN (0x1 << 0) /**< \brief (PWM_CMP2M) Comparison x Enable */ -#define PWM_CMP2M_CTR (0xf << 4) /**< \brief (PWM_CMP2M) Comparison x Trigger */ -#define PWM_CMP2M_CPR (0xf << 8) /**< \brief (PWM_CMP2M) Comparison x Period */ -#define PWM_CMP2M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP2M) Comparison x Period Counter */ -#define PWM_CMP2M_CUPR (0xf << 16) /**< \brief (PWM_CMP2M) Comparison x Update Period */ -#define PWM_CMP2M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP2M) Comparison x Update Period Counter */ -/* -------- PWM_CMP2MUPD : (PWM Offset: 0x15C) PWM Comparison 2 Mode Update Register -------- */ -#define PWM_CMP2MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP2MUPD) Comparison x Enable Update */ -#define PWM_CMP2MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP2MUPD) Comparison x Trigger Update */ -#define PWM_CMP2MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP2MUPD) Comparison x Period Update */ -#define PWM_CMP2MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP2MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP3V : (PWM Offset: 0x160) PWM Comparison 3 Value Register -------- */ -#define PWM_CMP3V_CV (0xffffff << 0) /**< \brief (PWM_CMP3V) Comparison x Value */ -#define PWM_CMP3V_CVM (0x1 << 24) /**< \brief (PWM_CMP3V) Comparison x Value Mode */ -/* -------- PWM_CMP3VUPD : (PWM Offset: 0x164) PWM Comparison 3 Value Update Register -------- */ -#define PWM_CMP3VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP3VUPD) Comparison x Value Update */ -#define PWM_CMP3VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP3VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP3M : (PWM Offset: 0x168) PWM Comparison 3 Mode Register -------- */ -#define PWM_CMP3M_CEN (0x1 << 0) /**< \brief (PWM_CMP3M) Comparison x Enable */ -#define PWM_CMP3M_CTR (0xf << 4) /**< \brief (PWM_CMP3M) Comparison x Trigger */ -#define PWM_CMP3M_CPR (0xf << 8) /**< \brief (PWM_CMP3M) Comparison x Period */ -#define PWM_CMP3M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP3M) Comparison x Period Counter */ -#define PWM_CMP3M_CUPR (0xf << 16) /**< \brief (PWM_CMP3M) Comparison x Update Period */ -#define PWM_CMP3M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP3M) Comparison x Update Period Counter */ -/* -------- PWM_CMP3MUPD : (PWM Offset: 0x16C) PWM Comparison 3 Mode Update Register -------- */ -#define PWM_CMP3MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP3MUPD) Comparison x Enable Update */ -#define PWM_CMP3MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP3MUPD) Comparison x Trigger Update */ -#define PWM_CMP3MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP3MUPD) Comparison x Period Update */ -#define PWM_CMP3MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP3MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP4V : (PWM Offset: 0x170) PWM Comparison 4 Value Register -------- */ -#define PWM_CMP4V_CV (0xffffff << 0) /**< \brief (PWM_CMP4V) Comparison x Value */ -#define PWM_CMP4V_CVM (0x1 << 24) /**< \brief (PWM_CMP4V) Comparison x Value Mode */ -/* -------- PWM_CMP4VUPD : (PWM Offset: 0x174) PWM Comparison 4 Value Update Register -------- */ -#define PWM_CMP4VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP4VUPD) Comparison x Value Update */ -#define PWM_CMP4VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP4VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP4M : (PWM Offset: 0x178) PWM Comparison 4 Mode Register -------- */ -#define PWM_CMP4M_CEN (0x1 << 0) /**< \brief (PWM_CMP4M) Comparison x Enable */ -#define PWM_CMP4M_CTR (0xf << 4) /**< \brief (PWM_CMP4M) Comparison x Trigger */ -#define PWM_CMP4M_CPR (0xf << 8) /**< \brief (PWM_CMP4M) Comparison x Period */ -#define PWM_CMP4M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP4M) Comparison x Period Counter */ -#define PWM_CMP4M_CUPR (0xf << 16) /**< \brief (PWM_CMP4M) Comparison x Update Period */ -#define PWM_CMP4M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP4M) Comparison x Update Period Counter */ -/* -------- PWM_CMP4MUPD : (PWM Offset: 0x17C) PWM Comparison 4 Mode Update Register -------- */ -#define PWM_CMP4MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP4MUPD) Comparison x Enable Update */ -#define PWM_CMP4MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP4MUPD) Comparison x Trigger Update */ -#define PWM_CMP4MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP4MUPD) Comparison x Period Update */ -#define PWM_CMP4MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP4MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP5V : (PWM Offset: 0x180) PWM Comparison 5 Value Register -------- */ -#define PWM_CMP5V_CV (0xffffff << 0) /**< \brief (PWM_CMP5V) Comparison x Value */ -#define PWM_CMP5V_CVM (0x1 << 24) /**< \brief (PWM_CMP5V) Comparison x Value Mode */ -/* -------- PWM_CMP5VUPD : (PWM Offset: 0x184) PWM Comparison 5 Value Update Register -------- */ -#define PWM_CMP5VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP5VUPD) Comparison x Value Update */ -#define PWM_CMP5VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP5VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP5M : (PWM Offset: 0x188) PWM Comparison 5 Mode Register -------- */ -#define PWM_CMP5M_CEN (0x1 << 0) /**< \brief (PWM_CMP5M) Comparison x Enable */ -#define PWM_CMP5M_CTR (0xf << 4) /**< \brief (PWM_CMP5M) Comparison x Trigger */ -#define PWM_CMP5M_CPR (0xf << 8) /**< \brief (PWM_CMP5M) Comparison x Period */ -#define PWM_CMP5M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP5M) Comparison x Period Counter */ -#define PWM_CMP5M_CUPR (0xf << 16) /**< \brief (PWM_CMP5M) Comparison x Update Period */ -#define PWM_CMP5M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP5M) Comparison x Update Period Counter */ -/* -------- PWM_CMP5MUPD : (PWM Offset: 0x18C) PWM Comparison 5 Mode Update Register -------- */ -#define PWM_CMP5MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP5MUPD) Comparison x Enable Update */ -#define PWM_CMP5MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP5MUPD) Comparison x Trigger Update */ -#define PWM_CMP5MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP5MUPD) Comparison x Period Update */ -#define PWM_CMP5MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP5MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP6V : (PWM Offset: 0x190) PWM Comparison 6 Value Register -------- */ -#define PWM_CMP6V_CV (0xffffff << 0) /**< \brief (PWM_CMP6V) Comparison x Value */ -#define PWM_CMP6V_CVM (0x1 << 24) /**< \brief (PWM_CMP6V) Comparison x Value Mode */ -/* -------- PWM_CMP6VUPD : (PWM Offset: 0x194) PWM Comparison 6 Value Update Register -------- */ -#define PWM_CMP6VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP6VUPD) Comparison x Value Update */ -#define PWM_CMP6VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP6VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP6M : (PWM Offset: 0x198) PWM Comparison 6 Mode Register -------- */ -#define PWM_CMP6M_CEN (0x1 << 0) /**< \brief (PWM_CMP6M) Comparison x Enable */ -#define PWM_CMP6M_CTR (0xf << 4) /**< \brief (PWM_CMP6M) Comparison x Trigger */ -#define PWM_CMP6M_CPR (0xf << 8) /**< \brief (PWM_CMP6M) Comparison x Period */ -#define PWM_CMP6M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP6M) Comparison x Period Counter */ -#define PWM_CMP6M_CUPR (0xf << 16) /**< \brief (PWM_CMP6M) Comparison x Update Period */ -#define PWM_CMP6M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP6M) Comparison x Update Period Counter */ -/* -------- PWM_CMP6MUPD : (PWM Offset: 0x19C) PWM Comparison 6 Mode Update Register -------- */ -#define PWM_CMP6MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP6MUPD) Comparison x Enable Update */ -#define PWM_CMP6MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP6MUPD) Comparison x Trigger Update */ -#define PWM_CMP6MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP6MUPD) Comparison x Period Update */ -#define PWM_CMP6MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP6MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP7V : (PWM Offset: 0x1A0) PWM Comparison 7 Value Register -------- */ -#define PWM_CMP7V_CV (0xffffff << 0) /**< \brief (PWM_CMP7V) Comparison x Value */ -#define PWM_CMP7V_CVM (0x1 << 24) /**< \brief (PWM_CMP7V) Comparison x Value Mode */ -/* -------- PWM_CMP7VUPD : (PWM Offset: 0x1A4) PWM Comparison 7 Value Update Register -------- */ -#define PWM_CMP7VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP7VUPD) Comparison x Value Update */ -#define PWM_CMP7VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP7VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP7M : (PWM Offset: 0x1A8) PWM Comparison 7 Mode Register -------- */ -#define PWM_CMP7M_CEN (0x1 << 0) /**< \brief (PWM_CMP7M) Comparison x Enable */ -#define PWM_CMP7M_CTR (0xf << 4) /**< \brief (PWM_CMP7M) Comparison x Trigger */ -#define PWM_CMP7M_CPR (0xf << 8) /**< \brief (PWM_CMP7M) Comparison x Period */ -#define PWM_CMP7M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP7M) Comparison x Period Counter */ -#define PWM_CMP7M_CUPR (0xf << 16) /**< \brief (PWM_CMP7M) Comparison x Update Period */ -#define PWM_CMP7M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP7M) Comparison x Update Period Counter */ -/* -------- PWM_CMP7MUPD : (PWM Offset: 0x1AC) PWM Comparison 7 Mode Update Register -------- */ -#define PWM_CMP7MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP7MUPD) Comparison x Enable Update */ -#define PWM_CMP7MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP7MUPD) Comparison x Trigger Update */ -#define PWM_CMP7MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP7MUPD) Comparison x Period Update */ -#define PWM_CMP7MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP7MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMR0 : (PWM Offset: 0x200) PWM Channel Mode Register (ch_num = 0) -------- */ -#define PWM_CMR0_CPRE (0xf << 0) /**< \brief (PWM_CMR0) Channel Pre-scaler */ -#define PWM_CMR0_CALG (0x1 << 8) /**< \brief (PWM_CMR0) Channel Alignment */ -#define PWM_CMR0_CPOL (0x1 << 9) /**< \brief (PWM_CMR0) Channel Polarity */ -#define PWM_CMR0_CES (0x1 << 10) /**< \brief (PWM_CMR0) Counter Event Selection */ -#define PWM_CMR0_DTE (0x1 << 16) /**< \brief (PWM_CMR0) Dead-Time Generator Enable */ -#define PWM_CMR0_DTHI (0x1 << 17) /**< \brief (PWM_CMR0) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR0_DTLI (0x1 << 18) /**< \brief (PWM_CMR0) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY0 : (PWM Offset: 0x204) PWM Channel Duty Cycle Register (ch_num = 0) -------- */ -#define PWM_CDTY0_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY0) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD0 : (PWM Offset: 0x208) PWM Channel Duty Cycle Update Register (ch_num = 0) -------- */ -#define PWM_CDTYUPD0_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD0) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD0 : (PWM Offset: 0x20C) PWM Channel Period Register (ch_num = 0) -------- */ -#define PWM_CPRD0_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD0) Channel Period */ -/* -------- PWM_CPRDUPD0 : (PWM Offset: 0x210) PWM Channel Period Update Register (ch_num = 0) -------- */ -#define PWM_CPRDUPD0_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD0) Channel Period Update */ -/* -------- PWM_CCNT0 : (PWM Offset: 0x214) PWM Channel Counter Register (ch_num = 0) -------- */ -#define PWM_CCNT0_CNT (0xffffff << 0) /**< \brief (PWM_CCNT0) Channel Counter Register */ -/* -------- PWM_DT0 : (PWM Offset: 0x218) PWM Channel Dead Time Register (ch_num = 0) -------- */ -#define PWM_DT0_DTH (0xffff << 0) /**< \brief (PWM_DT0) Dead-Time Value for PWMHx Output */ -#define PWM_DT0_DTL (0xffff << 16) /**< \brief (PWM_DT0) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD0 : (PWM Offset: 0x21C) PWM Channel Dead Time Update Register (ch_num = 0) -------- */ -#define PWM_DTUPD0_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD0_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR1 : (PWM Offset: 0x220) PWM Channel Mode Register (ch_num = 1) -------- */ -#define PWM_CMR1_CPRE (0xf << 0) /**< \brief (PWM_CMR1) Channel Pre-scaler */ -#define PWM_CMR1_CALG (0x1 << 8) /**< \brief (PWM_CMR1) Channel Alignment */ -#define PWM_CMR1_CPOL (0x1 << 9) /**< \brief (PWM_CMR1) Channel Polarity */ -#define PWM_CMR1_CES (0x1 << 10) /**< \brief (PWM_CMR1) Counter Event Selection */ -#define PWM_CMR1_DTE (0x1 << 16) /**< \brief (PWM_CMR1) Dead-Time Generator Enable */ -#define PWM_CMR1_DTHI (0x1 << 17) /**< \brief (PWM_CMR1) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR1_DTLI (0x1 << 18) /**< \brief (PWM_CMR1) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY1 : (PWM Offset: 0x224) PWM Channel Duty Cycle Register (ch_num = 1) -------- */ -#define PWM_CDTY1_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY1) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD1 : (PWM Offset: 0x228) PWM Channel Duty Cycle Update Register (ch_num = 1) -------- */ -#define PWM_CDTYUPD1_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD1) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD1 : (PWM Offset: 0x22C) PWM Channel Period Register (ch_num = 1) -------- */ -#define PWM_CPRD1_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD1) Channel Period */ -/* -------- PWM_CPRDUPD1 : (PWM Offset: 0x230) PWM Channel Period Update Register (ch_num = 1) -------- */ -#define PWM_CPRDUPD1_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD1) Channel Period Update */ -/* -------- PWM_CCNT1 : (PWM Offset: 0x234) PWM Channel Counter Register (ch_num = 1) -------- */ -#define PWM_CCNT1_CNT (0xffffff << 0) /**< \brief (PWM_CCNT1) Channel Counter Register */ -/* -------- PWM_DT1 : (PWM Offset: 0x238) PWM Channel Dead Time Register (ch_num = 1) -------- */ -#define PWM_DT1_DTH (0xffff << 0) /**< \brief (PWM_DT1) Dead-Time Value for PWMHx Output */ -#define PWM_DT1_DTL (0xffff << 16) /**< \brief (PWM_DT1) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD1 : (PWM Offset: 0x23C) PWM Channel Dead Time Update Register (ch_num = 1) -------- */ -#define PWM_DTUPD1_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD1_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR2 : (PWM Offset: 0x240) PWM Channel Mode Register (ch_num = 2) -------- */ -#define PWM_CMR2_CPRE (0xf << 0) /**< \brief (PWM_CMR2) Channel Pre-scaler */ -#define PWM_CMR2_CALG (0x1 << 8) /**< \brief (PWM_CMR2) Channel Alignment */ -#define PWM_CMR2_CPOL (0x1 << 9) /**< \brief (PWM_CMR2) Channel Polarity */ -#define PWM_CMR2_CES (0x1 << 10) /**< \brief (PWM_CMR2) Counter Event Selection */ -#define PWM_CMR2_DTE (0x1 << 16) /**< \brief (PWM_CMR2) Dead-Time Generator Enable */ -#define PWM_CMR2_DTHI (0x1 << 17) /**< \brief (PWM_CMR2) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR2_DTLI (0x1 << 18) /**< \brief (PWM_CMR2) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY2 : (PWM Offset: 0x244) PWM Channel Duty Cycle Register (ch_num = 2) -------- */ -#define PWM_CDTY2_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY2) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD2 : (PWM Offset: 0x248) PWM Channel Duty Cycle Update Register (ch_num = 2) -------- */ -#define PWM_CDTYUPD2_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD2) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD2 : (PWM Offset: 0x24C) PWM Channel Period Register (ch_num = 2) -------- */ -#define PWM_CPRD2_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD2) Channel Period */ -/* -------- PWM_CPRDUPD2 : (PWM Offset: 0x250) PWM Channel Period Update Register (ch_num = 2) -------- */ -#define PWM_CPRDUPD2_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD2) Channel Period Update */ -/* -------- PWM_CCNT2 : (PWM Offset: 0x254) PWM Channel Counter Register (ch_num = 2) -------- */ -#define PWM_CCNT2_CNT (0xffffff << 0) /**< \brief (PWM_CCNT2) Channel Counter Register */ -/* -------- PWM_DT2 : (PWM Offset: 0x258) PWM Channel Dead Time Register (ch_num = 2) -------- */ -#define PWM_DT2_DTH (0xffff << 0) /**< \brief (PWM_DT2) Dead-Time Value for PWMHx Output */ -#define PWM_DT2_DTL (0xffff << 16) /**< \brief (PWM_DT2) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD2 : (PWM Offset: 0x25C) PWM Channel Dead Time Update Register (ch_num = 2) -------- */ -#define PWM_DTUPD2_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD2_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR3 : (PWM Offset: 0x260) PWM Channel Mode Register (ch_num = 3) -------- */ -#define PWM_CMR3_CPRE (0xf << 0) /**< \brief (PWM_CMR3) Channel Pre-scaler */ -#define PWM_CMR3_CALG (0x1 << 8) /**< \brief (PWM_CMR3) Channel Alignment */ -#define PWM_CMR3_CPOL (0x1 << 9) /**< \brief (PWM_CMR3) Channel Polarity */ -#define PWM_CMR3_CES (0x1 << 10) /**< \brief (PWM_CMR3) Counter Event Selection */ -#define PWM_CMR3_DTE (0x1 << 16) /**< \brief (PWM_CMR3) Dead-Time Generator Enable */ -#define PWM_CMR3_DTHI (0x1 << 17) /**< \brief (PWM_CMR3) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR3_DTLI (0x1 << 18) /**< \brief (PWM_CMR3) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY3 : (PWM Offset: 0x264) PWM Channel Duty Cycle Register (ch_num = 3) -------- */ -#define PWM_CDTY3_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY3) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD3 : (PWM Offset: 0x268) PWM Channel Duty Cycle Update Register (ch_num = 3) -------- */ -#define PWM_CDTYUPD3_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD3) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD3 : (PWM Offset: 0x26C) PWM Channel Period Register (ch_num = 3) -------- */ -#define PWM_CPRD3_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD3) Channel Period */ -/* -------- PWM_CPRDUPD3 : (PWM Offset: 0x270) PWM Channel Period Update Register (ch_num = 3) -------- */ -#define PWM_CPRDUPD3_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD3) Channel Period Update */ -/* -------- PWM_CCNT3 : (PWM Offset: 0x274) PWM Channel Counter Register (ch_num = 3) -------- */ -#define PWM_CCNT3_CNT (0xffffff << 0) /**< \brief (PWM_CCNT3) Channel Counter Register */ -/* -------- PWM_DT3 : (PWM Offset: 0x278) PWM Channel Dead Time Register (ch_num = 3) -------- */ -#define PWM_DT3_DTH (0xffff << 0) /**< \brief (PWM_DT3) Dead-Time Value for PWMHx Output */ -#define PWM_DT3_DTL (0xffff << 16) /**< \brief (PWM_DT3) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD3 : (PWM Offset: 0x27C) PWM Channel Dead Time Update Register (ch_num = 3) -------- */ -#define PWM_DTUPD3_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD3_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMLx Output */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Reset Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_RSTC Reset Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rstc hardware registers */ -typedef struct { - WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ - RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ - RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ -} Rstc; -#endif /* __ASSEMBLY__ */ -/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ -#define RSTC_CR_PROCRST (0x1 << 0) /**< \brief (RSTC_CR) Processor Reset */ -#define RSTC_CR_PERRST (0x1 << 2) /**< \brief (RSTC_CR) Peripheral Reset */ -#define RSTC_CR_EXTRST (0x1 << 3) /**< \brief (RSTC_CR) External Reset */ -#define RSTC_CR_KEY (0xff << 24) /**< \brief (RSTC_CR) Password */ -/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ -#define RSTC_SR_URSTS (0x1 << 0) /**< \brief (RSTC_SR) User Reset Status */ -#define RSTC_SR_RSTTYP (0x7 << 8) /**< \brief (RSTC_SR) Reset Type */ -#define RSTC_SR_NRSTL (0x1 << 16) /**< \brief (RSTC_SR) NRST Pin Level */ -#define RSTC_SR_SRCMP (0x1 << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ -/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ -#define RSTC_MR_URSTEN (0x1 << 0) /**< \brief (RSTC_MR) User Reset Enable */ -#define RSTC_MR_URSTIEN (0x1 << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ -#define RSTC_MR_ERSTL (0xf << 8) /**< \brief (RSTC_MR) External Reset Length */ -#define RSTC_MR_KEY (0xff << 24) /**< \brief (RSTC_MR) Password */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Real-time Clock */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_RTC Real-time Clock */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rtc hardware registers */ -typedef struct { - RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ - RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ - RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ - RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ - RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ - RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ - RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ - WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ - WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ - WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ - RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ - RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ -} Rtc; -#endif /* __ASSEMBLY__ */ -/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ -#define RTC_CR_UPDTIM (0x1 << 0) /**< \brief (RTC_CR) Update Request Time Register */ -#define RTC_CR_UPDCAL (0x1 << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ -#define RTC_CR_TIMEVSEL (0x3 << 8) /**< \brief (RTC_CR) Time Event Selection */ -#define RTC_CR_TIMEVSEL_MINUTE (0x0 << 8) /**< \brief (RTC_CR) Minute change. */ -#define RTC_CR_TIMEVSEL_HOUR (0x1 << 8) /**< \brief (RTC_CR) Hour change. */ -#define RTC_CR_TIMEVSEL_DAY24 (0x2 << 8) /**< \brief (RTC_CR) Every day at midnight. */ -#define RTC_CR_TIMEVSEL_DAY12 (0x3 << 8) /**< \brief (RTC_CR) Every day at noon. */ -#define RTC_CR_CALEVSEL (0x3 << 16) /**< \brief (RTC_CR) Calendar Event Selection */ -#define RTC_CR_CALEVSEL_WEEK (0x0 << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00). */ -#define RTC_CR_CALEVSEL_MONTH (0x1 << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00). */ -/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ -#define RTC_MR_HRMOD (0x1 << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ -/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ -#define RTC_TIMR_SEC (0x7f << 0) /**< \brief (RTC_TIMR) Current Second */ -#define RTC_TIMR_MIN (0x7f << 8) /**< \brief (RTC_TIMR) Current Minute */ -#define RTC_TIMR_HOUR (0x3f << 16) /**< \brief (RTC_TIMR) Current Hour */ -#define RTC_TIMR_AMPM (0x1 << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ -/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ -#define RTC_CALR_CENT (0x7f << 0) /**< \brief (RTC_CALR) Current Century */ -#define RTC_CALR_YEAR (0xff << 8) /**< \brief (RTC_CALR) Current Year */ -#define RTC_CALR_MONTH (0x1f << 16) /**< \brief (RTC_CALR) Current Month */ -#define RTC_CALR_DAY (0x7 << 21) /**< \brief (RTC_CALR) Current Day in Current Week */ -#define RTC_CALR_DATE (0x3f << 24) /**< \brief (RTC_CALR) Current Day in Current Month */ -/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ -#define RTC_TIMALR_SEC (0x7f << 0) /**< \brief (RTC_TIMALR) Second Alarm */ -#define RTC_TIMALR_SECEN (0x1 << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ -#define RTC_TIMALR_MIN (0x7f << 8) /**< \brief (RTC_TIMALR) Minute Alarm */ -#define RTC_TIMALR_MINEN (0x1 << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ -#define RTC_TIMALR_HOUR (0x3f << 16) /**< \brief (RTC_TIMALR) Hour Alarm */ -#define RTC_TIMALR_AMPM (0x1 << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ -#define RTC_TIMALR_HOUREN (0x1 << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ -/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ -#define RTC_CALALR_MONTH (0x1f << 16) /**< \brief (RTC_CALALR) Month Alarm */ -#define RTC_CALALR_MTHEN (0x1 << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ -#define RTC_CALALR_DATE (0x3f << 24) /**< \brief (RTC_CALALR) Date Alarm */ -#define RTC_CALALR_DATEEN (0x1 << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ -/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ -#define RTC_SR_ACKUPD (0x1 << 0) /**< \brief (RTC_SR) Acknowledge for Update */ -#define RTC_SR_ALARM (0x1 << 1) /**< \brief (RTC_SR) Alarm Flag */ -#define RTC_SR_SEC (0x1 << 2) /**< \brief (RTC_SR) Second Event */ -#define RTC_SR_TIMEV (0x1 << 3) /**< \brief (RTC_SR) Time Event */ -#define RTC_SR_CALEV (0x1 << 4) /**< \brief (RTC_SR) Calendar Event */ -/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ -#define RTC_SCCR_ACKCLR (0x1 << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ -#define RTC_SCCR_ALRCLR (0x1 << 1) /**< \brief (RTC_SCCR) Alarm Clear */ -#define RTC_SCCR_SECCLR (0x1 << 2) /**< \brief (RTC_SCCR) Second Clear */ -#define RTC_SCCR_TIMCLR (0x1 << 3) /**< \brief (RTC_SCCR) Time Clear */ -#define RTC_SCCR_CALCLR (0x1 << 4) /**< \brief (RTC_SCCR) Calendar Clear */ -/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ -#define RTC_IER_ACKEN (0x1 << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ -#define RTC_IER_ALREN (0x1 << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ -#define RTC_IER_SECEN (0x1 << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ -#define RTC_IER_TIMEN (0x1 << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ -#define RTC_IER_CALEN (0x1 << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ -/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ -#define RTC_IDR_ACKDIS (0x1 << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ -#define RTC_IDR_ALRDIS (0x1 << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ -#define RTC_IDR_SECDIS (0x1 << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ -#define RTC_IDR_TIMDIS (0x1 << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ -#define RTC_IDR_CALDIS (0x1 << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ -/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ -#define RTC_IMR_ACK (0x1 << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ -#define RTC_IMR_ALR (0x1 << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ -#define RTC_IMR_SEC (0x1 << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ -#define RTC_IMR_TIM (0x1 << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ -#define RTC_IMR_CAL (0x1 << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ -/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ -#define RTC_VER_NVTIM (0x1 << 0) /**< \brief (RTC_VER) Non-valid Time */ -#define RTC_VER_NVCAL (0x1 << 1) /**< \brief (RTC_VER) Non-valid Calendar */ -#define RTC_VER_NVTIMALR (0x1 << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ -#define RTC_VER_NVCALALR (0x1 << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Real-time Timer */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_RTT Real-time Timer */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rtt hardware registers */ -typedef struct { - RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ - RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ - RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ - RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ -} Rtt; -#endif /* __ASSEMBLY__ */ -/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ -#define RTT_MR_RTPRES (0xffff << 0) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ -#define RTT_MR_ALMIEN (0x1 << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ -#define RTT_MR_RTTINCIEN (0x1 << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ -#define RTT_MR_RTTRST (0x1 << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ -/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ -#define RTT_AR_ALMV (0xffffffff << 0) /**< \brief (RTT_AR) Alarm Value */ -/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ -#define RTT_VR_CRTV (0xffffffff << 0) /**< \brief (RTT_VR) Current Real-time Value */ -/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ -#define RTT_SR_ALMS (0x1 << 0) /**< \brief (RTT_SR) Real-time Alarm Status */ -#define RTT_SR_RTTINC (0x1 << 1) /**< \brief (RTT_SR) Real-time Timer Increment */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Static Memory Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SMC Static Memory Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief SmcCs_number hardware registers */ -typedef struct { - RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ - RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ - RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ - RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */ -} SmcCs_number; -/** \brief Smc hardware registers */ -typedef struct { - SmcCs_number SMC_CS_NUMBER[5]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 4 */ - RwReg Reserved1[12]; - RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */ - WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */ - WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */ - RwReg Reserved2[22]; - RwReg SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */ - RoReg SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */ -} Smc; -#endif /* __ASSEMBLY__ */ -/* -------- SMC_SETUP0 : (SMC Offset: 0x0) SMC Setup Register (CS_number = 0) -------- */ -#define SMC_SETUP0_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP0) NWE Setup Length */ -#define SMC_SETUP0_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP0) NCS Setup Length in WRITE Access */ -#define SMC_SETUP0_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP0) NRD Setup Length */ -#define SMC_SETUP0_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP0) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE0 : (SMC Offset: 0x4) SMC Pulse Register (CS_number = 0) -------- */ -#define SMC_PULSE0_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE0) NWE Pulse Length */ -#define SMC_PULSE0_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE0) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE0_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE0) NRD Pulse Length */ -#define SMC_PULSE0_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE0) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE0 : (SMC Offset: 0x8) SMC Cycle Register (CS_number = 0) -------- */ -#define SMC_CYCLE0_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE0) Total Write Cycle Length */ -#define SMC_CYCLE0_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE0) Total Read Cycle Length */ -/* -------- SMC_MODE0 : (SMC Offset: 0xC) SMC Mode Register (CS_number = 0) -------- */ -#define SMC_MODE0_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE0) */ -#define SMC_MODE0_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE0) */ -#define SMC_MODE0_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE0) NWAIT Mode */ -#define SMC_MODE0_DBW (0x3 << 12) /**< \brief (SMC_MODE0) Data Bus Width */ -#define SMC_MODE0_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE0) Data Float Time */ -#define SMC_MODE0_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE0) TDF Optimization */ -#define SMC_MODE0_PMEN (0x1 << 24) /**< \brief (SMC_MODE0) Page Mode Enabled */ -#define SMC_MODE0_PS (0x3 << 28) /**< \brief (SMC_MODE0) Page Size */ -/* -------- SMC_SETUP1 : (SMC Offset: 0x10) SMC Setup Register (CS_number = 1) -------- */ -#define SMC_SETUP1_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP1) NWE Setup Length */ -#define SMC_SETUP1_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP1) NCS Setup Length in WRITE Access */ -#define SMC_SETUP1_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP1) NRD Setup Length */ -#define SMC_SETUP1_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP1) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE1 : (SMC Offset: 0x14) SMC Pulse Register (CS_number = 1) -------- */ -#define SMC_PULSE1_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE1) NWE Pulse Length */ -#define SMC_PULSE1_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE1) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE1_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE1) NRD Pulse Length */ -#define SMC_PULSE1_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE1) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE1 : (SMC Offset: 0x18) SMC Cycle Register (CS_number = 1) -------- */ -#define SMC_CYCLE1_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE1) Total Write Cycle Length */ -#define SMC_CYCLE1_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE1) Total Read Cycle Length */ -/* -------- SMC_MODE1 : (SMC Offset: 0x1C) SMC Mode Register (CS_number = 1) -------- */ -#define SMC_MODE1_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE1) */ -#define SMC_MODE1_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE1) */ -#define SMC_MODE1_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE1) NWAIT Mode */ -#define SMC_MODE1_DBW (0x3 << 12) /**< \brief (SMC_MODE1) Data Bus Width */ -#define SMC_MODE1_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE1) Data Float Time */ -#define SMC_MODE1_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE1) TDF Optimization */ -#define SMC_MODE1_PMEN (0x1 << 24) /**< \brief (SMC_MODE1) Page Mode Enabled */ -#define SMC_MODE1_PS (0x3 << 28) /**< \brief (SMC_MODE1) Page Size */ -/* -------- SMC_SETUP2 : (SMC Offset: 0x20) SMC Setup Register (CS_number = 2) -------- */ -#define SMC_SETUP2_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP2) NWE Setup Length */ -#define SMC_SETUP2_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP2) NCS Setup Length in WRITE Access */ -#define SMC_SETUP2_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP2) NRD Setup Length */ -#define SMC_SETUP2_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP2) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE2 : (SMC Offset: 0x24) SMC Pulse Register (CS_number = 2) -------- */ -#define SMC_PULSE2_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE2) NWE Pulse Length */ -#define SMC_PULSE2_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE2) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE2_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE2) NRD Pulse Length */ -#define SMC_PULSE2_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE2) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE2 : (SMC Offset: 0x28) SMC Cycle Register (CS_number = 2) -------- */ -#define SMC_CYCLE2_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE2) Total Write Cycle Length */ -#define SMC_CYCLE2_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE2) Total Read Cycle Length */ -/* -------- SMC_MODE2 : (SMC Offset: 0x2C) SMC Mode Register (CS_number = 2) -------- */ -#define SMC_MODE2_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE2) */ -#define SMC_MODE2_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE2) */ -#define SMC_MODE2_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE2) NWAIT Mode */ -#define SMC_MODE2_DBW (0x3 << 12) /**< \brief (SMC_MODE2) Data Bus Width */ -#define SMC_MODE2_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE2) Data Float Time */ -#define SMC_MODE2_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE2) TDF Optimization */ -#define SMC_MODE2_PMEN (0x1 << 24) /**< \brief (SMC_MODE2) Page Mode Enabled */ -#define SMC_MODE2_PS (0x3 << 28) /**< \brief (SMC_MODE2) Page Size */ -/* -------- SMC_SETUP3 : (SMC Offset: 0x30) SMC Setup Register (CS_number = 3) -------- */ -#define SMC_SETUP3_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP3) NWE Setup Length */ -#define SMC_SETUP3_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP3) NCS Setup Length in WRITE Access */ -#define SMC_SETUP3_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP3) NRD Setup Length */ -#define SMC_SETUP3_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP3) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE3 : (SMC Offset: 0x34) SMC Pulse Register (CS_number = 3) -------- */ -#define SMC_PULSE3_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE3) NWE Pulse Length */ -#define SMC_PULSE3_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE3) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE3_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE3) NRD Pulse Length */ -#define SMC_PULSE3_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE3) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE3 : (SMC Offset: 0x38) SMC Cycle Register (CS_number = 3) -------- */ -#define SMC_CYCLE3_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE3) Total Write Cycle Length */ -#define SMC_CYCLE3_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE3) Total Read Cycle Length */ -/* -------- SMC_MODE3 : (SMC Offset: 0x3C) SMC Mode Register (CS_number = 3) -------- */ -#define SMC_MODE3_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE3) */ -#define SMC_MODE3_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE3) */ -#define SMC_MODE3_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE3) NWAIT Mode */ -#define SMC_MODE3_DBW (0x3 << 12) /**< \brief (SMC_MODE3) Data Bus Width */ -#define SMC_MODE3_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE3) Data Float Time */ -#define SMC_MODE3_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE3) TDF Optimization */ -#define SMC_MODE3_PMEN (0x1 << 24) /**< \brief (SMC_MODE3) Page Mode Enabled */ -#define SMC_MODE3_PS (0x3 << 28) /**< \brief (SMC_MODE3) Page Size */ -/* -------- SMC_SETUP4 : (SMC Offset: 0x40) SMC Setup Register (CS_number = 4) -------- */ -#define SMC_SETUP4_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP4) NWE Setup Length */ -#define SMC_SETUP4_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP4) NCS Setup Length in WRITE Access */ -#define SMC_SETUP4_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP4) NRD Setup Length */ -#define SMC_SETUP4_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP4) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE4 : (SMC Offset: 0x44) SMC Pulse Register (CS_number = 4) -------- */ -#define SMC_PULSE4_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE4) NWE Pulse Length */ -#define SMC_PULSE4_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE4) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE4_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE4) NRD Pulse Length */ -#define SMC_PULSE4_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE4) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE4 : (SMC Offset: 0x48) SMC Cycle Register (CS_number = 4) -------- */ -#define SMC_CYCLE4_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE4) Total Write Cycle Length */ -#define SMC_CYCLE4_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE4) Total Read Cycle Length */ -/* -------- SMC_MODE4 : (SMC Offset: 0x4C) SMC Mode Register (CS_number = 4) -------- */ -#define SMC_MODE4_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE4) */ -#define SMC_MODE4_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE4) */ -#define SMC_MODE4_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE4) NWAIT Mode */ -#define SMC_MODE4_DBW (0x3 << 12) /**< \brief (SMC_MODE4) Data Bus Width */ -#define SMC_MODE4_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE4) Data Float Time */ -#define SMC_MODE4_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE4) TDF Optimization */ -#define SMC_MODE4_PMEN (0x1 << 24) /**< \brief (SMC_MODE4) Page Mode Enabled */ -#define SMC_MODE4_PS (0x3 << 28) /**< \brief (SMC_MODE4) Page Size */ -/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */ -#define SMC_OCMS_SMSE (0x1 << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ -#define SMC_OCMS_CS0SE (0x1 << 16) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -#define SMC_OCMS_CS1SE (0x1 << 17) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -#define SMC_OCMS_CS2SE (0x1 << 18) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -#define SMC_OCMS_CS3SE (0x1 << 19) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */ -#define SMC_KEY1_KEY1 (0xffffffff << 0) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ -/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */ -#define SMC_KEY2_KEY2 (0xffffffff << 0) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ -/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */ -#define SMC_WPMR_WPEN (0x1 << 0) /**< \brief (SMC_WPMR) Write Protect Enable */ -#define SMC_WPMR_WPKEY (0xffffff << 8) /**< \brief (SMC_WPMR) Write Protect KEY */ -/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */ -#define SMC_WPSR_WPVS (0x1 << 0) /**< \brief (SMC_WPSR) Write Protect Enable */ -#define SMC_WPSR_WPVSRC (0xffff << 8) /**< \brief (SMC_WPSR) Write Protect Violation Source */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SPI Serial Peripheral Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Spi hardware registers */ -typedef struct { - WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ - RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ - RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ - WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ - RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ - WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ - WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ - RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ - RwReg Reserved1[4]; - RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ - RwReg Reserved2[41]; - RwReg SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */ - RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ - RwReg Reserved3[5]; - RwReg SPI_RPR; /**< \brief (Spi Offset: 0x100) Receive Pointer Register */ - RwReg SPI_RCR; /**< \brief (Spi Offset: 0x104) Receive Counter Register */ - RwReg SPI_TPR; /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */ - RwReg SPI_TCR; /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */ - RwReg SPI_RNPR; /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */ - RwReg SPI_RNCR; /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */ - RwReg SPI_TNPR; /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */ - RwReg SPI_TNCR; /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */ - WoReg SPI_PTCR; /**< \brief (Spi Offset: 0x120) Transfer Control Register */ - RoReg SPI_PTSR; /**< \brief (Spi Offset: 0x124) Transfer Status Register */ -} Spi, AT91S_SPI, *AT91PS_SPI; -#endif /* __ASSEMBLY__ */ -/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ -#define SPI_CR_SPIEN (0x1 << 0) /**< \brief (SPI_CR) SPI Enable */ -#define SPI_CR_SPIDIS (0x1 << 1) /**< \brief (SPI_CR) SPI Disable */ -#define SPI_CR_SWRST (0x1 << 7) /**< \brief (SPI_CR) SPI Software Reset */ -#define SPI_CR_LASTXFER (0x1 << 24) /**< \brief (SPI_CR) Last Transfer */ -/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ -#define SPI_MR_MSTR (0x1 << 0) /**< \brief (SPI_MR) Master/Slave Mode */ -#define SPI_MR_PS (0x1 << 1) /**< \brief (SPI_MR) Peripheral Select */ -#define SPI_MR_PS_FIXED (0x0 << 1) /**< \brief (SPI_MR) Fixed Peripheral Select. */ -#define SPI_MR_PS_VARIABLE (0x1 << 1) /**< \brief (SPI_MR) Variable Peripheral Select. */ -#define SPI_MR_PCSDEC (0x1 << 2) /**< \brief (SPI_MR) Chip Select Decode */ -#define SPI_MR_MODFDIS (0x1 << 4) /**< \brief (SPI_MR) Mode Fault Detection */ -#define SPI_MR_WDRBT (0x1 << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ -#define SPI_MR_LLB (0x1 << 7) /**< \brief (SPI_MR) Local Loopback Enable */ -#define SPI_MR_PCS (0xf << 16) /**< \brief (SPI_MR) Peripheral Chip Select */ -#define SPI_MR_DLYBCS (0xff << 24) /**< \brief (SPI_MR) Delay Between Chip Selects */ -/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ -#define SPI_RDR_RD (0xffff << 0) /**< \brief (SPI_RDR) Receive Data */ -#define SPI_RDR_PCS (0xf << 16) /**< \brief (SPI_RDR) Peripheral Chip Select */ -/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ -#define SPI_TDR_TD (0xffff << 0) /**< \brief (SPI_TDR) Transmit Data */ -#define SPI_TDR_PCS (0xf << 16) /**< \brief (SPI_TDR) Peripheral Chip Select */ -#define SPI_TDR_LASTXFER (0x1 << 24) /**< \brief (SPI_TDR) Last Transfer */ -/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ -#define SPI_SR_RDRF (0x1 << 0) /**< \brief (SPI_SR) Receive Data Register Full */ -#define SPI_SR_TDRE (0x1 << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */ -#define SPI_SR_MODF (0x1 << 2) /**< \brief (SPI_SR) Mode Fault Error */ -#define SPI_SR_OVRES (0x1 << 3) /**< \brief (SPI_SR) Overrun Error Status */ -#define SPI_SR_ENDRX (0x1 << 4) /**< \brief (SPI_SR) End of RX buffer */ -#define SPI_SR_ENDTX (0x1 << 5) /**< \brief (SPI_SR) End of TX buffer */ -#define SPI_SR_RXBUFF (0x1 << 6) /**< \brief (SPI_SR) RX Buffer Full */ -#define SPI_SR_TXBUFE (0x1 << 7) /**< \brief (SPI_SR) TX Buffer Empty */ -#define SPI_SR_NSSR (0x1 << 8) /**< \brief (SPI_SR) NSS Rising */ -#define SPI_SR_TXEMPTY (0x1 << 9) /**< \brief (SPI_SR) Transmission Registers Empty */ -#define SPI_SR_UNDES (0x1 << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */ -#define SPI_SR_SPIENS (0x1 << 16) /**< \brief (SPI_SR) SPI Enable Status */ -/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ -#define SPI_IER_RDRF (0x1 << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ -#define SPI_IER_TDRE (0x1 << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ -#define SPI_IER_MODF (0x1 << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ -#define SPI_IER_OVRES (0x1 << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ -#define SPI_IER_ENDRX (0x1 << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */ -#define SPI_IER_ENDTX (0x1 << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */ -#define SPI_IER_RXBUFF (0x1 << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */ -#define SPI_IER_TXBUFE (0x1 << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */ -#define SPI_IER_NSSR (0x1 << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ -#define SPI_IER_TXEMPTY (0x1 << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ -#define SPI_IER_UNDES (0x1 << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ -/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ -#define SPI_IDR_RDRF (0x1 << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ -#define SPI_IDR_TDRE (0x1 << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ -#define SPI_IDR_MODF (0x1 << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ -#define SPI_IDR_OVRES (0x1 << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ -#define SPI_IDR_ENDRX (0x1 << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */ -#define SPI_IDR_ENDTX (0x1 << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */ -#define SPI_IDR_RXBUFF (0x1 << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */ -#define SPI_IDR_TXBUFE (0x1 << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */ -#define SPI_IDR_NSSR (0x1 << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ -#define SPI_IDR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ -#define SPI_IDR_UNDES (0x1 << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ -/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ -#define SPI_IMR_RDRF (0x1 << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ -#define SPI_IMR_TDRE (0x1 << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ -#define SPI_IMR_MODF (0x1 << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ -#define SPI_IMR_OVRES (0x1 << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ -#define SPI_IMR_ENDRX (0x1 << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */ -#define SPI_IMR_ENDTX (0x1 << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */ -#define SPI_IMR_RXBUFF (0x1 << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */ -#define SPI_IMR_TXBUFE (0x1 << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */ -#define SPI_IMR_NSSR (0x1 << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ -#define SPI_IMR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ -#define SPI_IMR_UNDES (0x1 << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ -/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ -#define SPI_CSR_CPOL (0x1 << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ -#define SPI_CSR_NCPHA (0x1 << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ -#define SPI_CSR_CSNAAT (0x1 << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ -#define SPI_CSR_CSAAT (0x1 << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ -#define SPI_CSR_BITS (0xf << 4) /**< \brief (SPI_CSR[4]) Bits Per Transfer (See the (Note:) below the register table; Section 9.9 "SPI Chip Select Register" on page 35.) */ -#define SPI_CSR_BITS_8 (0x0 << 4) /**< \brief (SPI_CSR[4]) 8 */ -#define SPI_CSR_BITS_9 (0x1 << 4) /**< \brief (SPI_CSR[4]) 9 */ -#define SPI_CSR_BITS_10 (0x2 << 4) /**< \brief (SPI_CSR[4]) 10 */ -#define SPI_CSR_BITS_11 (0x3 << 4) /**< \brief (SPI_CSR[4]) 11 */ -#define SPI_CSR_BITS_12 (0x4 << 4) /**< \brief (SPI_CSR[4]) 12 */ -#define SPI_CSR_BITS_13 (0x5 << 4) /**< \brief (SPI_CSR[4]) 13 */ -#define SPI_CSR_BITS_14 (0x6 << 4) /**< \brief (SPI_CSR[4]) 14 */ -#define SPI_CSR_BITS_15 (0x7 << 4) /**< \brief (SPI_CSR[4]) 15 */ -#define SPI_CSR_BITS_16 (0x8 << 4) /**< \brief (SPI_CSR[4]) 16 */ -#define SPI_CSR_SCBR (0xff << 8) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */ -#define SPI_CSR_DLYBS (0xff << 16) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ -#define SPI_CSR_DLYBCT (0xff << 24) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ -/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */ -#define SPI_WPMR_SPIWPEN (0x1 << 0) /**< \brief (SPI_WPMR) SPI Write Protection Enable */ -#define SPI_WPMR_SPIWPKEY (0xffffff << 8) /**< \brief (SPI_WPMR) SPI Write Protection Key Password */ -/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ -#define SPI_WPSR_SPIWPVS (0x7 << 0) /**< \brief (SPI_WPSR) SPI Write Protection Violation Status */ -#define SPI_WPSR_SPIWPVSRC (0xff << 8) /**< \brief (SPI_WPSR) SPI Write Protection Violation Source */ -/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */ -#define SPI_RPR_RXPTR (0xffffffff << 0) /**< \brief (SPI_RPR) Receive Pointer Register */ -/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */ -#define SPI_RCR_RXCTR (0xffff << 0) /**< \brief (SPI_RCR) Receive Counter Register */ -/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */ -#define SPI_TPR_TXPTR (0xffffffff << 0) /**< \brief (SPI_TPR) Transmit Counter Register */ -/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */ -#define SPI_TCR_TXCTR (0xffff << 0) /**< \brief (SPI_TCR) Transmit Counter Register */ -/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */ -#define SPI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (SPI_RNPR) Receive Next Pointer */ -/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */ -#define SPI_RNCR_RXNCTR (0xffff << 0) /**< \brief (SPI_RNCR) Receive Next Counter */ -/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define SPI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (SPI_TNPR) Transmit Next Pointer */ -/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define SPI_TNCR_TXNCTR (0xffff << 0) /**< \brief (SPI_TNCR) Transmit Counter Next */ -/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */ -#define SPI_PTCR_RXTEN (0x1 << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */ -#define SPI_PTCR_RXTDIS (0x1 << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */ -#define SPI_PTCR_TXTEN (0x1 << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */ -#define SPI_PTCR_TXTDIS (0x1 << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */ -/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */ -#define SPI_PTSR_RXTEN (0x1 << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */ -#define SPI_PTSR_TXTEN (0x1 << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SSC Synchronous Serial Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Ssc hardware registers */ -typedef struct { - WoReg SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ - RwReg SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ - RwReg Reserved1[2]; - RwReg SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ - RwReg SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ - RwReg SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ - RwReg SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ - RoReg SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ - WoReg SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ - RwReg Reserved2[2]; - RoReg SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ - RwReg SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ - RwReg SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ - RwReg SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ - RoReg SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ - WoReg SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ - WoReg SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ - RoReg SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ - RwReg Reserved3[37]; - RwReg SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */ - RoReg SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */ - RwReg Reserved4[5]; - RwReg SSC_RPR; /**< \brief (Ssc Offset: 0x100) Receive Pointer Register */ - RwReg SSC_RCR; /**< \brief (Ssc Offset: 0x104) Receive Counter Register */ - RwReg SSC_TPR; /**< \brief (Ssc Offset: 0x108) Transmit Pointer Register */ - RwReg SSC_TCR; /**< \brief (Ssc Offset: 0x10C) Transmit Counter Register */ - RwReg SSC_RNPR; /**< \brief (Ssc Offset: 0x110) Receive Next Pointer Register */ - RwReg SSC_RNCR; /**< \brief (Ssc Offset: 0x114) Receive Next Counter Register */ - RwReg SSC_TNPR; /**< \brief (Ssc Offset: 0x118) Transmit Next Pointer Register */ - RwReg SSC_TNCR; /**< \brief (Ssc Offset: 0x11C) Transmit Next Counter Register */ - WoReg SSC_PTCR; /**< \brief (Ssc Offset: 0x120) Transfer Control Register */ - RoReg SSC_PTSR; /**< \brief (Ssc Offset: 0x124) Transfer Status Register */ -} Ssc; -#endif /* __ASSEMBLY__ */ -/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ -#define SSC_CR_RXEN (0x1 << 0) /**< \brief (SSC_CR) Receive Enable */ -#define SSC_CR_RXDIS (0x1 << 1) /**< \brief (SSC_CR) Receive Disable */ -#define SSC_CR_TXEN (0x1 << 8) /**< \brief (SSC_CR) Transmit Enable */ -#define SSC_CR_TXDIS (0x1 << 9) /**< \brief (SSC_CR) Transmit Disable */ -#define SSC_CR_SWRST (0x1 << 15) /**< \brief (SSC_CR) Software Reset */ -/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ -#define SSC_CMR_DIV (0xfff << 0) /**< \brief (SSC_CMR) Clock Divider */ -/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ -#define SSC_RCMR_CKS (0x3 << 0) /**< \brief (SSC_RCMR) Receive Clock Selection */ -#define SSC_RCMR_CKS_DIV (0x0 << 0) /**< \brief (SSC_RCMR) Divided Clock */ -#define SSC_RCMR_CKS_TK (0x1 << 0) /**< \brief (SSC_RCMR) TK Clock signal */ -#define SSC_RCMR_CKS_RK (0x2 << 0) /**< \brief (SSC_RCMR) RK pin */ -#define SSC_RCMR_CKO (0x7 << 2) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ -#define SSC_RCMR_CKI (0x1 << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ -#define SSC_RCMR_CKG (0x3 << 6) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ -#define SSC_RCMR_CKG_NONE (0x0 << 6) /**< \brief (SSC_RCMR) None, continuous clock */ -#define SSC_RCMR_CKG_LOW (0x1 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */ -#define SSC_RCMR_CKG_HIGH (0x2 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */ -#define SSC_RCMR_START (0xf << 8) /**< \brief (SSC_RCMR) Receive Start Selection */ -#define SSC_RCMR_STOP (0x1 << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ -#define SSC_RCMR_STTDLY (0xff << 16) /**< \brief (SSC_RCMR) Receive Start Delay */ -#define SSC_RCMR_PERIOD (0xff << 24) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ -/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ -#define SSC_RFMR_DATLEN (0x1f << 0) /**< \brief (SSC_RFMR) Data Length */ -#define SSC_RFMR_LOOP (0x1 << 5) /**< \brief (SSC_RFMR) Loop Mode */ -#define SSC_RFMR_MSBF (0x1 << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ -#define SSC_RFMR_DATNB (0xf << 8) /**< \brief (SSC_RFMR) Data Number per Frame */ -#define SSC_RFMR_FSLEN (0xf << 16) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ -#define SSC_RFMR_FSOS (0x7 << 20) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ -#define SSC_RFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ -#define SSC_RFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_RFMR) FSLEN Field Extension */ -/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ -#define SSC_TCMR_CKS (0x3 << 0) /**< \brief (SSC_TCMR) Transmit Clock Selection */ -#define SSC_TCMR_CKO (0x7 << 2) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ -#define SSC_TCMR_CKI (0x1 << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ -#define SSC_TCMR_CKG (0x3 << 6) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ -#define SSC_TCMR_START (0xf << 8) /**< \brief (SSC_TCMR) Transmit Start Selection */ -#define SSC_TCMR_STTDLY (0xff << 16) /**< \brief (SSC_TCMR) Transmit Start Delay */ -#define SSC_TCMR_PERIOD (0xff << 24) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ -/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ -#define SSC_TFMR_DATLEN (0x1f << 0) /**< \brief (SSC_TFMR) Data Length */ -#define SSC_TFMR_DATDEF (0x1 << 5) /**< \brief (SSC_TFMR) Data Default Value */ -#define SSC_TFMR_MSBF (0x1 << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ -#define SSC_TFMR_DATNB (0xf << 8) /**< \brief (SSC_TFMR) Data Number per frame */ -#define SSC_TFMR_FSLEN (0xf << 16) /**< \brief (SSC_TFMR) Transmit Frame Syn Length */ -#define SSC_TFMR_FSOS (0x7 << 20) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ -#define SSC_TFMR_FSDEN (0x1 << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ -#define SSC_TFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ -#define SSC_TFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_TFMR) FSLEN Field Extension */ -/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ -#define SSC_RHR_RDAT (0xffffffff << 0) /**< \brief (SSC_RHR) Receive Data */ -/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ -#define SSC_THR_TDAT (0xffffffff << 0) /**< \brief (SSC_THR) Transmit Data */ -/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ -#define SSC_RSHR_RSDAT (0xffff << 0) /**< \brief (SSC_RSHR) Receive Synchronization Data */ -/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ -#define SSC_TSHR_TSDAT (0xffff << 0) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ -/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ -#define SSC_RC0R_CP0 (0xffff << 0) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ -/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ -#define SSC_RC1R_CP1 (0xffff << 0) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ -/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ -#define SSC_SR_TXRDY (0x1 << 0) /**< \brief (SSC_SR) Transmit Ready */ -#define SSC_SR_TXEMPTY (0x1 << 1) /**< \brief (SSC_SR) Transmit Empty */ -#define SSC_SR_ENDTX (0x1 << 2) /**< \brief (SSC_SR) End of Transmission */ -#define SSC_SR_TXBUFE (0x1 << 3) /**< \brief (SSC_SR) Transmit Buffer Empty */ -#define SSC_SR_RXRDY (0x1 << 4) /**< \brief (SSC_SR) Receive Ready */ -#define SSC_SR_OVRUN (0x1 << 5) /**< \brief (SSC_SR) Receive Overrun */ -#define SSC_SR_ENDRX (0x1 << 6) /**< \brief (SSC_SR) End of Reception */ -#define SSC_SR_RXBUFF (0x1 << 7) /**< \brief (SSC_SR) Receive Buffer Full */ -#define SSC_SR_CP0 (0x1 << 8) /**< \brief (SSC_SR) Compare 0 */ -#define SSC_SR_CP1 (0x1 << 9) /**< \brief (SSC_SR) Compare 1 */ -#define SSC_SR_TXSYN (0x1 << 10) /**< \brief (SSC_SR) Transmit Sync */ -#define SSC_SR_RXSYN (0x1 << 11) /**< \brief (SSC_SR) Receive Sync */ -#define SSC_SR_TXEN (0x1 << 16) /**< \brief (SSC_SR) Transmit Enable */ -#define SSC_SR_RXEN (0x1 << 17) /**< \brief (SSC_SR) Receive Enable */ -/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ -#define SSC_IER_TXRDY (0x1 << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ -#define SSC_IER_TXEMPTY (0x1 << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ -#define SSC_IER_ENDTX (0x1 << 2) /**< \brief (SSC_IER) End of Transmission Interrupt Enable */ -#define SSC_IER_TXBUFE (0x1 << 3) /**< \brief (SSC_IER) Transmit Buffer Empty Interrupt Enable */ -#define SSC_IER_RXRDY (0x1 << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ -#define SSC_IER_OVRUN (0x1 << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ -#define SSC_IER_ENDRX (0x1 << 6) /**< \brief (SSC_IER) End of Reception Interrupt Enable */ -#define SSC_IER_RXBUFF (0x1 << 7) /**< \brief (SSC_IER) Receive Buffer Full Interrupt Enable */ -#define SSC_IER_CP0 (0x1 << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ -#define SSC_IER_CP1 (0x1 << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ -#define SSC_IER_TXSYN (0x1 << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ -#define SSC_IER_RXSYN (0x1 << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ -/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ -#define SSC_IDR_TXRDY (0x1 << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ -#define SSC_IDR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ -#define SSC_IDR_ENDTX (0x1 << 2) /**< \brief (SSC_IDR) End of Transmission Interrupt Disable */ -#define SSC_IDR_TXBUFE (0x1 << 3) /**< \brief (SSC_IDR) Transmit Buffer Empty Interrupt Disable */ -#define SSC_IDR_RXRDY (0x1 << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ -#define SSC_IDR_OVRUN (0x1 << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ -#define SSC_IDR_ENDRX (0x1 << 6) /**< \brief (SSC_IDR) End of Reception Interrupt Disable */ -#define SSC_IDR_RXBUFF (0x1 << 7) /**< \brief (SSC_IDR) Receive Buffer Full Interrupt Disable */ -#define SSC_IDR_CP0 (0x1 << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ -#define SSC_IDR_CP1 (0x1 << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ -#define SSC_IDR_TXSYN (0x1 << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ -#define SSC_IDR_RXSYN (0x1 << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ -/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ -#define SSC_IMR_TXRDY (0x1 << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ -#define SSC_IMR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ -#define SSC_IMR_ENDTX (0x1 << 2) /**< \brief (SSC_IMR) End of Transmission Interrupt Mask */ -#define SSC_IMR_TXBUFE (0x1 << 3) /**< \brief (SSC_IMR) Transmit Buffer Empty Interrupt Mask */ -#define SSC_IMR_RXRDY (0x1 << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ -#define SSC_IMR_OVRUN (0x1 << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ -#define SSC_IMR_ENDRX (0x1 << 6) /**< \brief (SSC_IMR) End of Reception Interrupt Mask */ -#define SSC_IMR_RXBUFF (0x1 << 7) /**< \brief (SSC_IMR) Receive Buffer Full Interrupt Mask */ -#define SSC_IMR_CP0 (0x1 << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ -#define SSC_IMR_CP1 (0x1 << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ -#define SSC_IMR_TXSYN (0x1 << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ -#define SSC_IMR_RXSYN (0x1 << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ -/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */ -#define SSC_WPMR_WPEN (0x1 << 0) /**< \brief (SSC_WPMR) Write Protect Enable */ -#define SSC_WPMR_WPKEY (0xffffff << 8) /**< \brief (SSC_WPMR) Write Protect KEY */ -/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */ -#define SSC_WPSR_WPVS (0x1 << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */ -#define SSC_WPSR_WPVSRC (0xffff << 8) /**< \brief (SSC_WPSR) Write Protect Violation Source */ -/* -------- SSC_RPR : (SSC Offset: 0x100) Receive Pointer Register -------- */ -#define SSC_RPR_RXPTR (0xffffffff << 0) /**< \brief (SSC_RPR) Receive Pointer Register */ -/* -------- SSC_RCR : (SSC Offset: 0x104) Receive Counter Register -------- */ -#define SSC_RCR_RXCTR (0xffff << 0) /**< \brief (SSC_RCR) Receive Counter Register */ -/* -------- SSC_TPR : (SSC Offset: 0x108) Transmit Pointer Register -------- */ -#define SSC_TPR_TXPTR (0xffffffff << 0) /**< \brief (SSC_TPR) Transmit Counter Register */ -/* -------- SSC_TCR : (SSC Offset: 0x10C) Transmit Counter Register -------- */ -#define SSC_TCR_TXCTR (0xffff << 0) /**< \brief (SSC_TCR) Transmit Counter Register */ -/* -------- SSC_RNPR : (SSC Offset: 0x110) Receive Next Pointer Register -------- */ -#define SSC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (SSC_RNPR) Receive Next Pointer */ -/* -------- SSC_RNCR : (SSC Offset: 0x114) Receive Next Counter Register -------- */ -#define SSC_RNCR_RXNCTR (0xffff << 0) /**< \brief (SSC_RNCR) Receive Next Counter */ -/* -------- SSC_TNPR : (SSC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define SSC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (SSC_TNPR) Transmit Next Pointer */ -/* -------- SSC_TNCR : (SSC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define SSC_TNCR_TXNCTR (0xffff << 0) /**< \brief (SSC_TNCR) Transmit Counter Next */ -/* -------- SSC_PTCR : (SSC Offset: 0x120) Transfer Control Register -------- */ -#define SSC_PTCR_RXTEN (0x1 << 0) /**< \brief (SSC_PTCR) Receiver Transfer Enable */ -#define SSC_PTCR_RXTDIS (0x1 << 1) /**< \brief (SSC_PTCR) Receiver Transfer Disable */ -#define SSC_PTCR_TXTEN (0x1 << 8) /**< \brief (SSC_PTCR) Transmitter Transfer Enable */ -#define SSC_PTCR_TXTDIS (0x1 << 9) /**< \brief (SSC_PTCR) Transmitter Transfer Disable */ -/* -------- SSC_PTSR : (SSC Offset: 0x124) Transfer Status Register -------- */ -#define SSC_PTSR_RXTEN (0x1 << 0) /**< \brief (SSC_PTSR) Receiver Transfer Enable */ -#define SSC_PTSR_TXTEN (0x1 << 8) /**< \brief (SSC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Supply Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SUPC Supply Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Supc hardware registers */ -typedef struct { - WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ - RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ - RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ - RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */ - RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */ - RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ -} Supc; -#endif /* __ASSEMBLY__ */ -/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ -#define SUPC_CR_VROFF (0x1 << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ -#define SUPC_CR_VROFF_NO_EFFECT (0x0 << 2) /**< \brief (SUPC_CR) no effect. */ -#define SUPC_CR_VROFF_STOP_VREG (0x1 << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */ -#define SUPC_CR_XTALSEL (0x1 << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ -#define SUPC_CR_XTALSEL_NO_EFFECT (0x0 << 3) /**< \brief (SUPC_CR) no effect. */ -#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1 << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */ -#define SUPC_CR_KEY (0xff << 24) /**< \brief (SUPC_CR) Password */ -/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ -#define SUPC_SMMR_SMTH (0xf << 0) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ -#define SUPC_SMMR_SMTH_1_9V (0x0 << 0) /**< \brief (SUPC_SMMR) 1.9 V */ -#define SUPC_SMMR_SMTH_2_0V (0x1 << 0) /**< \brief (SUPC_SMMR) 2.0 V */ -#define SUPC_SMMR_SMTH_2_1V (0x2 << 0) /**< \brief (SUPC_SMMR) 2.1 V */ -#define SUPC_SMMR_SMTH_2_2V (0x3 << 0) /**< \brief (SUPC_SMMR) 2.2 V */ -#define SUPC_SMMR_SMTH_2_3V (0x4 << 0) /**< \brief (SUPC_SMMR) 2.3 V */ -#define SUPC_SMMR_SMTH_2_4V (0x5 << 0) /**< \brief (SUPC_SMMR) 2.4 V */ -#define SUPC_SMMR_SMTH_2_5V (0x6 << 0) /**< \brief (SUPC_SMMR) 2.5 V */ -#define SUPC_SMMR_SMTH_2_6V (0x7 << 0) /**< \brief (SUPC_SMMR) 2.6 V */ -#define SUPC_SMMR_SMTH_2_7V (0x8 << 0) /**< \brief (SUPC_SMMR) 2.7 V */ -#define SUPC_SMMR_SMTH_2_8V (0x9 << 0) /**< \brief (SUPC_SMMR) 2.8 V */ -#define SUPC_SMMR_SMTH_2_9V (0xA << 0) /**< \brief (SUPC_SMMR) 2.9 V */ -#define SUPC_SMMR_SMTH_3_0V (0xB << 0) /**< \brief (SUPC_SMMR) 3.0 V */ -#define SUPC_SMMR_SMTH_3_1V (0xC << 0) /**< \brief (SUPC_SMMR) 3.1 V */ -#define SUPC_SMMR_SMTH_3_2V (0xD << 0) /**< \brief (SUPC_SMMR) 3.2 V */ -#define SUPC_SMMR_SMTH_3_3V (0xE << 0) /**< \brief (SUPC_SMMR) 3.3 V */ -#define SUPC_SMMR_SMTH_3_4V (0xF << 0) /**< \brief (SUPC_SMMR) 3.4 V */ -#define SUPC_SMMR_SMSMPL (0x7 << 8) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ -#define SUPC_SMMR_SMSMPL_SMD (0x0 << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ -#define SUPC_SMMR_SMSMPL_CSM (0x1 << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ -#define SUPC_SMMR_SMSMPL_32SLCK (0x2 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ -#define SUPC_SMMR_SMSMPL_256SLCK (0x3 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ -#define SUPC_SMMR_SMSMPL_2048SLCK (0x4 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ -#define SUPC_SMMR_SMRSTEN (0x1 << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ -#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMIEN (0x1 << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ -#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMIEN_ENABLE (0x1 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */ -/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ -#define SUPC_MR_BODRSTEN (0x1 << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ -#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */ -#define SUPC_MR_BODRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ -#define SUPC_MR_BODDIS (0x1 << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ -#define SUPC_MR_BODDIS_ENABLE (0x0 << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */ -#define SUPC_MR_BODDIS_DISABLE (0x1 << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */ -#define SUPC_MR_ONREG (0x1 << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */ -#define SUPC_MR_ONREG_ONREG_UNUSED (0x0 << 14) /**< \brief (SUPC_MR) Voltage Regulator is not used */ -#define SUPC_MR_ONREG_ONREG_USED (0x1 << 14) /**< \brief (SUPC_MR) Voltage Regulator is used */ -#define SUPC_MR_OSCBYPASS (0x1 << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ -#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0 << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */ -#define SUPC_MR_OSCBYPASS_BYPASS (0x1 << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */ -#define SUPC_MR_KEY (0xff << 24) /**< \brief (SUPC_MR) Password Key */ -/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */ -#define SUPC_WUMR_SMEN (0x1 << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */ -#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */ -#define SUPC_WUMR_SMEN_ENABLE (0x1 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */ -#define SUPC_WUMR_RTTEN (0x1 << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */ -#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */ -#define SUPC_WUMR_RTTEN_ENABLE (0x1 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */ -#define SUPC_WUMR_RTCEN (0x1 << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */ -#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */ -#define SUPC_WUMR_RTCEN_ENABLE (0x1 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */ -#define SUPC_WUMR_WKUPDBC (0x7 << 12) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer */ -#define SUPC_WUMR_WKUPDBC_1SCLK (0x0 << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ -#define SUPC_WUMR_WKUPDBC_3SCLK (0x1 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 3 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_32SCLK (0x2 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_512SCLK (0x3 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 512 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_4096SCLK (0x4 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 4,096 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_32768SCLK (0x5 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32,768 SLCK periods */ -/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */ -#define SUPC_WUIR_WKUPEN0 (0x1 << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */ -#define SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN0_ENABLE (0x1 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN1 (0x1 << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */ -#define SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN1_ENABLE (0x1 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN2 (0x1 << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */ -#define SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN2_ENABLE (0x1 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN3 (0x1 << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */ -#define SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN3_ENABLE (0x1 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN4 (0x1 << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */ -#define SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN4_ENABLE (0x1 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN5 (0x1 << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */ -#define SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN5_ENABLE (0x1 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN6 (0x1 << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */ -#define SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN6_ENABLE (0x1 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN7 (0x1 << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */ -#define SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN7_ENABLE (0x1 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN8 (0x1 << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */ -#define SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN8_ENABLE (0x1 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN9 (0x1 << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */ -#define SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN9_ENABLE (0x1 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN10 (0x1 << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */ -#define SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN10_ENABLE (0x1 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN11 (0x1 << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */ -#define SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN11_ENABLE (0x1 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN12 (0x1 << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */ -#define SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN12_ENABLE (0x1 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN13 (0x1 << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */ -#define SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN13_ENABLE (0x1 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN14 (0x1 << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */ -#define SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN14_ENABLE (0x1 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN15 (0x1 << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */ -#define SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN15_ENABLE (0x1 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT0 (0x1 << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */ -#define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0 << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1 << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT1 (0x1 << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */ -#define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0 << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1 << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT2 (0x1 << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */ -#define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0 << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1 << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT3 (0x1 << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */ -#define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0 << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1 << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT4 (0x1 << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */ -#define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0 << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1 << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT5 (0x1 << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */ -#define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0 << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1 << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT6 (0x1 << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */ -#define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0 << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1 << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT7 (0x1 << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */ -#define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0 << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1 << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT8 (0x1 << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */ -#define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0 << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1 << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT9 (0x1 << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */ -#define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0 << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1 << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT10 (0x1 << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */ -#define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0 << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1 << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT11 (0x1 << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */ -#define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0 << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1 << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT12 (0x1 << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */ -#define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0 << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1 << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT13 (0x1 << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */ -#define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0 << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1 << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT14 (0x1 << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */ -#define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0 << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1 << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT15 (0x1 << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */ -#define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0 << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1 << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ -#define SUPC_SR_WKUPS (0x1 << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */ -#define SUPC_SR_WKUPS_NO (0x0 << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_WKUPS_PRESENT (0x1 << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_SMWS (0x1 << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */ -#define SUPC_SR_SMWS_NO (0x0 << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_SMWS_PRESENT (0x1 << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_BODRSTS (0x1 << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */ -#define SUPC_SR_BODRSTS_NO (0x0 << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */ -#define SUPC_SR_BODRSTS_PRESENT (0x1 << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ -#define SUPC_SR_SMRSTS (0x1 << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */ -#define SUPC_SR_SMRSTS_NO (0x0 << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ -#define SUPC_SR_SMRSTS_PRESENT (0x1 << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ -#define SUPC_SR_SMS (0x1 << 5) /**< \brief (SUPC_SR) Supply Monitor Status */ -#define SUPC_SR_SMS_NO (0x0 << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */ -#define SUPC_SR_SMS_PRESENT (0x1 << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */ -#define SUPC_SR_SMOS (0x1 << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ -#define SUPC_SR_SMOS_HIGH (0x0 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */ -#define SUPC_SR_SMOS_LOW (0x1 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */ -#define SUPC_SR_OSCSEL (0x1 << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ -#define SUPC_SR_OSCSEL_RC (0x0 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */ -#define SUPC_SR_OSCSEL_CRYST (0x1 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */ -#define SUPC_SR_WKUPIS0 (0x1 << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */ -#define SUPC_SR_WKUPIS0_DIS (0x0 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS0_EN (0x1 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS1 (0x1 << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */ -#define SUPC_SR_WKUPIS1_DIS (0x0 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS1_EN (0x1 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS2 (0x1 << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */ -#define SUPC_SR_WKUPIS2_DIS (0x0 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS2_EN (0x1 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS3 (0x1 << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */ -#define SUPC_SR_WKUPIS3_DIS (0x0 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS3_EN (0x1 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS4 (0x1 << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */ -#define SUPC_SR_WKUPIS4_DIS (0x0 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS4_EN (0x1 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS5 (0x1 << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */ -#define SUPC_SR_WKUPIS5_DIS (0x0 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS5_EN (0x1 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS6 (0x1 << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */ -#define SUPC_SR_WKUPIS6_DIS (0x0 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS6_EN (0x1 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS7 (0x1 << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */ -#define SUPC_SR_WKUPIS7_DIS (0x0 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS7_EN (0x1 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS8 (0x1 << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */ -#define SUPC_SR_WKUPIS8_DIS (0x0 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS8_EN (0x1 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS9 (0x1 << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */ -#define SUPC_SR_WKUPIS9_DIS (0x0 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS9_EN (0x1 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS10 (0x1 << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */ -#define SUPC_SR_WKUPIS10_DIS (0x0 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS10_EN (0x1 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS11 (0x1 << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */ -#define SUPC_SR_WKUPIS11_DIS (0x0 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS11_EN (0x1 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS12 (0x1 << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */ -#define SUPC_SR_WKUPIS12_DIS (0x0 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS12_EN (0x1 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS13 (0x1 << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */ -#define SUPC_SR_WKUPIS13_DIS (0x0 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS13_EN (0x1 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS14 (0x1 << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */ -#define SUPC_SR_WKUPIS14_DIS (0x0 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS14_EN (0x1 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS15 (0x1 << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */ -#define SUPC_SR_WKUPIS15_DIS (0x0 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS15_EN (0x1 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Timer Counter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_TC Timer Counter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief TcChannel hardware registers */ -typedef struct { - RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ - RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ - RwReg Reserved1[2]; - RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ - RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ - RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ - RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ - RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ - RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ - RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ - RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ - RwReg Reserved2[4]; -} TcChannel; -/** \brief Tc hardware registers */ -typedef struct { - TcChannel TC_CHANNEL[3]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ - WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ - RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ - WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ - WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ - RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ - RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ - RwReg TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ - RwReg Reserved1[2]; - RwReg TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */ - RwReg Reserved2[5]; - RoReg TC_VER; /**< \brief (Tc Offset: 0xFC) Version Register */ -} Tc; -#endif /* __ASSEMBLY__ */ -/* -------- TC_CCR0 : (TC Offset: 0x0) Channel Control Register (channel = 0) -------- */ - -#define TC_CCR_CLKEN TC_CCR0_CLKEN /**< \brief (TC_CCR) Counter Clock Enable Command */ -#define TC_CCR_CLKDIS TC_CCR0_CLKDIS /**< \brief (TC_CCR) Counter Clock Disable Command */ -#define TC_CCR_SWTRG TC_CCR0_SWTRG /**< \brief (TC_CCR) Software Trigger Command */ - -#define TC_CCR0_CLKEN (0x1 << 0) /**< \brief (TC_CCR0) Counter Clock Enable Command */ -#define TC_CCR0_CLKDIS (0x1 << 1) /**< \brief (TC_CCR0) Counter Clock Disable Command */ -#define TC_CCR0_SWTRG (0x1 << 2) /**< \brief (TC_CCR0) Software Trigger Command */ -/* -------- TC_CMR0 : (TC Offset: 0x4) Channel Mode Register (channel = 0) -------- */ -#define TC_CMR0_TCCLKS (0x7 << 0) /**< \brief (TC_CMR0) Clock Selection */ -#define TC_CM0_TCCLKS_TIMER_DIV1_CLOCK (0x0 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV1_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV2_CLOCK (0x1 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV2_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV3_CLOCK (0x2 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV3_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV4_CLOCK (0x3 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV4_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV5_CLOCK (0x4 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV5_CLOCK*/ -#define TC_CM0_TCCLKS_XC0 (0x5 << 0) /**< (TC_CMR0) Clock selected: XC0*/ -#define TC_CM0_TCCLKS_XC1 (0x6 << 0) /**< (TC_CMR0) Clock selected: XC1*/ -#define TC_CM0_TCCLKS_XC2 (0x7 << 0) /**< (TC_CMR0) Clock selected: XC2*/ -#define TC_CMR0_CLKI (0x1 << 3) /**< \brief (TC_CMR0) Clock Invert */ -#define TC_CMR0_BURST (0x3 << 4) /**< \brief (TC_CMR0) Burst Signal Selection */ -#define TC_CMR0_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR0) The clock is not gated by an external signal. */ -#define TC_CMR0_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR0) XC0 is ANDed with the selected clock. */ -#define TC_CMR0_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR0) XC1 is ANDed with the selected clock. */ -#define TC_CMR0_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR0) XC2 is ANDed with the selected clock. */ -#define TC_CMR0_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR0) Counter Clock Stopped with RB Loading */ -#define TC_CMR0_LDBDIS (0x1 << 7) /**< \brief (TC_CMR0) Counter Clock Disable with RB Loading */ -#define TC_CMR0_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR0) External Trigger Edge Selection */ -#define TC_CMR0_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR0) rising edge */ -#define TC_CMR0_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR0) falling edge */ -#define TC_CMR0_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR0) each edge */ -#define TC_CMR0_ABETRG (0x1 << 10) /**< \brief (TC_CMR0) TIOA or TIOB External Trigger Selection */ - -#define TC_CMR_CPCTRG TC_CMR0_CPCTRG -#define TC_CMR0_CPCTRG (0x1 << 14) /**< \brief (TC_CMR0) RC Compare Trigger Enable */ -#define TC_CMR0_WAVE (0x1 << 15) /**< \brief (TC_CMR0) */ -#define TC_CMR0_LDRA (0x3 << 16) /**< \brief (TC_CMR0) RA Loading Selection */ -#define TC_CMR0_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR0) rising edge of TIOA */ -#define TC_CMR0_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR0) falling edge of TIOA */ -#define TC_CMR0_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR0) each edge of TIOA */ -#define TC_CMR0_LDRB (0x3 << 18) /**< \brief (TC_CMR0) RB Loading Selection */ -#define TC_CMR0_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR0) rising edge of TIOA */ -#define TC_CMR0_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR0) falling edge of TIOA */ -#define TC_CMR0_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR0) each edge of TIOA */ - -#define TC_CMR0_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define TC_CMR0_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define TC_CMR0_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define TC_CMR0_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle - -#define TC_CMR0_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define TC_CMR0_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define TC_CMR0_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define TC_CMR0_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -/* -------- TC_CV0 : (TC Offset: 0x10) Counter Value (channel = 0) -------- */ -#define TC_CV0_CV (0xffff << 0) /**< \brief (TC_CV0) Counter Value */ -/* -------- TC_RA0 : (TC Offset: 0x14) Register A (channel = 0) -------- */ -#define TC_RA0_RA (0xffff << 0) /**< \brief (TC_RA0) Register A */ -/* -------- TC_RB0 : (TC Offset: 0x18) Register B (channel = 0) -------- */ -#define TC_RB0_RB (0xffff << 0) /**< \brief (TC_RB0) Register B */ -/* -------- TC_RC0 : (TC Offset: 0x1C) Register C (channel = 0) -------- */ -#define TC_RC0_RC (0xffff << 0) /**< \brief (TC_RC0) Register C */ -/* -------- TC_SR0 : (TC Offset: 0x20) Status Register (channel = 0) -------- */ -#define TC_SR0_COVFS (0x1 << 0) /**< \brief (TC_SR0) Counter Overflow Status */ -#define TC_SR0_LOVRS (0x1 << 1) /**< \brief (TC_SR0) Load Overrun Status */ -#define TC_SR0_CPAS (0x1 << 2) /**< \brief (TC_SR0) RA Compare Status */ -#define TC_SR0_CPBS (0x1 << 3) /**< \brief (TC_SR0) RB Compare Status */ -#define TC_SR0_CPCS (0x1 << 4) /**< \brief (TC_SR0) RC Compare Status */ -#define TC_SR0_LDRAS (0x1 << 5) /**< \brief (TC_SR0) RA Loading Status */ -#define TC_SR0_LDRBS (0x1 << 6) /**< \brief (TC_SR0) RB Loading Status */ -#define TC_SR0_ETRGS (0x1 << 7) /**< \brief (TC_SR0) External Trigger Status */ -#define TC_SR0_CLKSTA (0x1 << 16) /**< \brief (TC_SR0) Clock Enabling Status */ -#define TC_SR0_MTIOA (0x1 << 17) /**< \brief (TC_SR0) TIOA Mirror */ -#define TC_SR0_MTIOB (0x1 << 18) /**< \brief (TC_SR0) TIOB Mirror */ -/* -------- TC_IER0 : (TC Offset: 0x24) Interrupt Enable Register (channel = 0) -------- */ -#define TC_IER0_COVFS (0x1 << 0) /**< \brief (TC_IER0) Counter Overflow */ -#define TC_IER0_LOVRS (0x1 << 1) /**< \brief (TC_IER0) Load Overrun */ -#define TC_IER0_CPAS (0x1 << 2) /**< \brief (TC_IER0) RA Compare */ -#define TC_IER0_CPBS (0x1 << 3) /**< \brief (TC_IER0) RB Compare */ - -#define TC_IER_CPCS TC_IER0_CPCS -#define TC_IER0_CPCS (0x1 << 4) /**< \brief (TC_IER0) RC Compare */ -#define TC_IER0_LDRAS (0x1 << 5) /**< \brief (TC_IER0) RA Loading */ -#define TC_IER0_LDRBS (0x1 << 6) /**< \brief (TC_IER0) RB Loading */ -#define TC_IER0_ETRGS (0x1 << 7) /**< \brief (TC_IER0) External Trigger */ -/* -------- TC_IDR0 : (TC Offset: 0x28) Interrupt Disable Register (channel = 0) -------- */ -#define TC_IDR0_COVFS (0x1 << 0) /**< \brief (TC_IDR0) Counter Overflow */ -#define TC_IDR0_LOVRS (0x1 << 1) /**< \brief (TC_IDR0) Load Overrun */ -#define TC_IDR0_CPAS (0x1 << 2) /**< \brief (TC_IDR0) RA Compare */ -#define TC_IDR0_CPBS (0x1 << 3) /**< \brief (TC_IDR0) RB Compare */ -#define TC_IDR0_CPCS (0x1 << 4) /**< \brief (TC_IDR0) RC Compare */ -#define TC_IDR0_LDRAS (0x1 << 5) /**< \brief (TC_IDR0) RA Loading */ -#define TC_IDR0_LDRBS (0x1 << 6) /**< \brief (TC_IDR0) RB Loading */ -#define TC_IDR0_ETRGS (0x1 << 7) /**< \brief (TC_IDR0) External Trigger */ -/* -------- TC_IMR0 : (TC Offset: 0x2C) Interrupt Mask Register (channel = 0) -------- */ -#define TC_IMR0_COVFS (0x1 << 0) /**< \brief (TC_IMR0) Counter Overflow */ -#define TC_IMR0_LOVRS (0x1 << 1) /**< \brief (TC_IMR0) Load Overrun */ -#define TC_IMR0_CPAS (0x1 << 2) /**< \brief (TC_IMR0) RA Compare */ -#define TC_IMR0_CPBS (0x1 << 3) /**< \brief (TC_IMR0) RB Compare */ -#define TC_IMR0_CPCS (0x1 << 4) /**< \brief (TC_IMR0) RC Compare */ -#define TC_IMR0_LDRAS (0x1 << 5) /**< \brief (TC_IMR0) RA Loading */ -#define TC_IMR0_LDRBS (0x1 << 6) /**< \brief (TC_IMR0) RB Loading */ -#define TC_IMR0_ETRGS (0x1 << 7) /**< \brief (TC_IMR0) External Trigger */ -/* -------- TC_CCR1 : (TC Offset: 0x40) Channel Control Register (channel = 1) -------- */ -#define TC_CCR1_CLKEN (0x1 << 0) /**< \brief (TC_CCR1) Counter Clock Enable Command */ -#define TC_CCR1_CLKDIS (0x1 << 1) /**< \brief (TC_CCR1) Counter Clock Disable Command */ -#define TC_CCR1_SWTRG (0x1 << 2) /**< \brief (TC_CCR1) Software Trigger Command */ -/* -------- TC_CMR1 : (TC Offset: 0x44) Channel Mode Register (channel = 1) -------- */ -#define TC_CMR1_TCCLKS (0x7 << 0) /**< \brief (TC_CMR1) Clock Selection */ -#define TC_CMR1_CLKI (0x1 << 3) /**< \brief (TC_CMR1) Clock Invert */ -#define TC_CMR1_BURST (0x3 << 4) /**< \brief (TC_CMR1) Burst Signal Selection */ -#define TC_CMR1_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR1) The clock is not gated by an external signal. */ -#define TC_CMR1_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR1) XC0 is ANDed with the selected clock. */ -#define TC_CMR1_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR1) XC1 is ANDed with the selected clock. */ -#define TC_CMR1_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR1) XC2 is ANDed with the selected clock. */ -#define TC_CMR1_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR1) Counter Clock Stopped with RB Loading */ -#define TC_CMR1_LDBDIS (0x1 << 7) /**< \brief (TC_CMR1) Counter Clock Disable with RB Loading */ -#define TC_CMR1_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR1) External Trigger Edge Selection */ -#define TC_CMR1_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR1) rising edge */ -#define TC_CMR1_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR1) falling edge */ -#define TC_CMR1_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR1) each edge */ -#define TC_CMR1_ABETRG (0x1 << 10) /**< \brief (TC_CMR1) TIOA or TIOB External Trigger Selection */ -#define TC_CMR1_CPCTRG (0x1 << 14) /**< \brief (TC_CMR1) RC Compare Trigger Enable */ -#define TC_CMR1_WAVE (0x1 << 15) /**< \brief (TC_CMR1) */ -#define TC_CMR1_LDRA (0x3 << 16) /**< \brief (TC_CMR1) RA Loading Selection */ -#define TC_CMR1_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR1) rising edge of TIOA */ -#define TC_CMR1_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR1) falling edge of TIOA */ -#define TC_CMR1_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR1) each edge of TIOA */ -#define TC_CMR1_LDRB (0x3 << 18) /**< \brief (TC_CMR1) RB Loading Selection */ -#define TC_CMR1_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR1) rising edge of TIOA */ -#define TC_CMR1_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR1) falling edge of TIOA */ -#define TC_CMR1_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR1) each edge of TIOA */ -/* -------- TC_CV1 : (TC Offset: 0x50) Counter Value (channel = 1) -------- */ -#define TC_CV1_CV (0xffff << 0) /**< \brief (TC_CV1) Counter Value */ -/* -------- TC_RA1 : (TC Offset: 0x54) Register A (channel = 1) -------- */ -#define TC_RA1_RA (0xffff << 0) /**< \brief (TC_RA1) Register A */ -/* -------- TC_RB1 : (TC Offset: 0x58) Register B (channel = 1) -------- */ -#define TC_RB1_RB (0xffff << 0) /**< \brief (TC_RB1) Register B */ -/* -------- TC_RC1 : (TC Offset: 0x5C) Register C (channel = 1) -------- */ -#define TC_RC1_RC (0xffff << 0) /**< \brief (TC_RC1) Register C */ -/* -------- TC_SR1 : (TC Offset: 0x60) Status Register (channel = 1) -------- */ -#define TC_SR1_COVFS (0x1 << 0) /**< \brief (TC_SR1) Counter Overflow Status */ -#define TC_SR1_LOVRS (0x1 << 1) /**< \brief (TC_SR1) Load Overrun Status */ -#define TC_SR1_CPAS (0x1 << 2) /**< \brief (TC_SR1) RA Compare Status */ -#define TC_SR1_CPBS (0x1 << 3) /**< \brief (TC_SR1) RB Compare Status */ -#define TC_SR1_CPCS (0x1 << 4) /**< \brief (TC_SR1) RC Compare Status */ -#define TC_SR1_LDRAS (0x1 << 5) /**< \brief (TC_SR1) RA Loading Status */ -#define TC_SR1_LDRBS (0x1 << 6) /**< \brief (TC_SR1) RB Loading Status */ -#define TC_SR1_ETRGS (0x1 << 7) /**< \brief (TC_SR1) External Trigger Status */ -#define TC_SR1_CLKSTA (0x1 << 16) /**< \brief (TC_SR1) Clock Enabling Status */ -#define TC_SR1_MTIOA (0x1 << 17) /**< \brief (TC_SR1) TIOA Mirror */ -#define TC_SR1_MTIOB (0x1 << 18) /**< \brief (TC_SR1) TIOB Mirror */ -/* -------- TC_IER1 : (TC Offset: 0x64) Interrupt Enable Register (channel = 1) -------- */ -#define TC_IER1_COVFS (0x1 << 0) /**< \brief (TC_IER1) Counter Overflow */ -#define TC_IER1_LOVRS (0x1 << 1) /**< \brief (TC_IER1) Load Overrun */ -#define TC_IER1_CPAS (0x1 << 2) /**< \brief (TC_IER1) RA Compare */ -#define TC_IER1_CPBS (0x1 << 3) /**< \brief (TC_IER1) RB Compare */ -#define TC_IER1_CPCS (0x1 << 4) /**< \brief (TC_IER1) RC Compare */ -#define TC_IER1_LDRAS (0x1 << 5) /**< \brief (TC_IER1) RA Loading */ -#define TC_IER1_LDRBS (0x1 << 6) /**< \brief (TC_IER1) RB Loading */ -#define TC_IER1_ETRGS (0x1 << 7) /**< \brief (TC_IER1) External Trigger */ -/* -------- TC_IDR1 : (TC Offset: 0x68) Interrupt Disable Register (channel = 1) -------- */ -#define TC_IDR1_COVFS (0x1 << 0) /**< \brief (TC_IDR1) Counter Overflow */ -#define TC_IDR1_LOVRS (0x1 << 1) /**< \brief (TC_IDR1) Load Overrun */ -#define TC_IDR1_CPAS (0x1 << 2) /**< \brief (TC_IDR1) RA Compare */ -#define TC_IDR1_CPBS (0x1 << 3) /**< \brief (TC_IDR1) RB Compare */ -#define TC_IDR1_CPCS (0x1 << 4) /**< \brief (TC_IDR1) RC Compare */ -#define TC_IDR1_LDRAS (0x1 << 5) /**< \brief (TC_IDR1) RA Loading */ -#define TC_IDR1_LDRBS (0x1 << 6) /**< \brief (TC_IDR1) RB Loading */ -#define TC_IDR1_ETRGS (0x1 << 7) /**< \brief (TC_IDR1) External Trigger */ -/* -------- TC_IMR1 : (TC Offset: 0x6C) Interrupt Mask Register (channel = 1) -------- */ -#define TC_IMR1_COVFS (0x1 << 0) /**< \brief (TC_IMR1) Counter Overflow */ -#define TC_IMR1_LOVRS (0x1 << 1) /**< \brief (TC_IMR1) Load Overrun */ -#define TC_IMR1_CPAS (0x1 << 2) /**< \brief (TC_IMR1) RA Compare */ -#define TC_IMR1_CPBS (0x1 << 3) /**< \brief (TC_IMR1) RB Compare */ -#define TC_IMR1_CPCS (0x1 << 4) /**< \brief (TC_IMR1) RC Compare */ -#define TC_IMR1_LDRAS (0x1 << 5) /**< \brief (TC_IMR1) RA Loading */ -#define TC_IMR1_LDRBS (0x1 << 6) /**< \brief (TC_IMR1) RB Loading */ -#define TC_IMR1_ETRGS (0x1 << 7) /**< \brief (TC_IMR1) External Trigger */ -/* -------- TC_CCR2 : (TC Offset: 0x80) Channel Control Register (channel = 2) -------- */ -#define TC_CCR2_CLKEN (0x1 << 0) /**< \brief (TC_CCR2) Counter Clock Enable Command */ -#define TC_CCR2_CLKDIS (0x1 << 1) /**< \brief (TC_CCR2) Counter Clock Disable Command */ -#define TC_CCR2_SWTRG (0x1 << 2) /**< \brief (TC_CCR2) Software Trigger Command */ -/* -------- TC_CMR2 : (TC Offset: 0x84) Channel Mode Register (channel = 2) -------- */ -#define TC_CMR2_TCCLKS (0x7 << 0) /**< \brief (TC_CMR2) Clock Selection */ -#define TC_CMR2_CLKI (0x1 << 3) /**< \brief (TC_CMR2) Clock Invert */ -#define TC_CMR2_BURST (0x3 << 4) /**< \brief (TC_CMR2) Burst Signal Selection */ -#define TC_CMR2_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR2) The clock is not gated by an external signal. */ -#define TC_CMR2_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR2) XC0 is ANDed with the selected clock. */ -#define TC_CMR2_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR2) XC1 is ANDed with the selected clock. */ -#define TC_CMR2_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR2) XC2 is ANDed with the selected clock. */ -#define TC_CMR2_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR2) Counter Clock Stopped with RB Loading */ -#define TC_CMR2_LDBDIS (0x1 << 7) /**< \brief (TC_CMR2) Counter Clock Disable with RB Loading */ -#define TC_CMR2_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR2) External Trigger Edge Selection */ -#define TC_CMR2_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR2) rising edge */ -#define TC_CMR2_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR2) falling edge */ -#define TC_CMR2_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR2) each edge */ -#define TC_CMR2_ABETRG (0x1 << 10) /**< \brief (TC_CMR2) TIOA or TIOB External Trigger Selection */ -#define TC_CMR2_CPCTRG (0x1 << 14) /**< \brief (TC_CMR2) RC Compare Trigger Enable */ -#define TC_CMR2_WAVE (0x1 << 15) /**< \brief (TC_CMR2) */ -#define TC_CMR2_LDRA (0x3 << 16) /**< \brief (TC_CMR2) RA Loading Selection */ -#define TC_CMR2_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR2) rising edge of TIOA */ -#define TC_CMR2_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR2) falling edge of TIOA */ -#define TC_CMR2_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR2) each edge of TIOA */ -#define TC_CMR2_LDRB (0x3 << 18) /**< \brief (TC_CMR2) RB Loading Selection */ -#define TC_CMR2_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR2) rising edge of TIOA */ -#define TC_CMR2_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR2) falling edge of TIOA */ -#define TC_CMR2_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR2) each edge of TIOA */ -/* -------- TC_CV2 : (TC Offset: 0x90) Counter Value (channel = 2) -------- */ -#define TC_CV2_CV (0xffff << 0) /**< \brief (TC_CV2) Counter Value */ -/* -------- TC_RA2 : (TC Offset: 0x94) Register A (channel = 2) -------- */ -#define TC_RA2_RA (0xffff << 0) /**< \brief (TC_RA2) Register A */ -/* -------- TC_RB2 : (TC Offset: 0x98) Register B (channel = 2) -------- */ -#define TC_RB2_RB (0xffff << 0) /**< \brief (TC_RB2) Register B */ -/* -------- TC_RC2 : (TC Offset: 0x9C) Register C (channel = 2) -------- */ -#define TC_RC2_RC (0xffff << 0) /**< \brief (TC_RC2) Register C */ -/* -------- TC_SR2 : (TC Offset: 0xA0) Status Register (channel = 2) -------- */ -#define TC_SR2_COVFS (0x1 << 0) /**< \brief (TC_SR2) Counter Overflow Status */ -#define TC_SR2_LOVRS (0x1 << 1) /**< \brief (TC_SR2) Load Overrun Status */ -#define TC_SR2_CPAS (0x1 << 2) /**< \brief (TC_SR2) RA Compare Status */ -#define TC_SR2_CPBS (0x1 << 3) /**< \brief (TC_SR2) RB Compare Status */ -#define TC_SR2_CPCS (0x1 << 4) /**< \brief (TC_SR2) RC Compare Status */ -#define TC_SR2_LDRAS (0x1 << 5) /**< \brief (TC_SR2) RA Loading Status */ -#define TC_SR2_LDRBS (0x1 << 6) /**< \brief (TC_SR2) RB Loading Status */ -#define TC_SR2_ETRGS (0x1 << 7) /**< \brief (TC_SR2) External Trigger Status */ -#define TC_SR2_CLKSTA (0x1 << 16) /**< \brief (TC_SR2) Clock Enabling Status */ -#define TC_SR2_MTIOA (0x1 << 17) /**< \brief (TC_SR2) TIOA Mirror */ -#define TC_SR2_MTIOB (0x1 << 18) /**< \brief (TC_SR2) TIOB Mirror */ -/* -------- TC_IER2 : (TC Offset: 0xA4) Interrupt Enable Register (channel = 2) -------- */ -#define TC_IER2_COVFS (0x1 << 0) /**< \brief (TC_IER2) Counter Overflow */ -#define TC_IER2_LOVRS (0x1 << 1) /**< \brief (TC_IER2) Load Overrun */ -#define TC_IER2_CPAS (0x1 << 2) /**< \brief (TC_IER2) RA Compare */ -#define TC_IER2_CPBS (0x1 << 3) /**< \brief (TC_IER2) RB Compare */ -#define TC_IER2_CPCS (0x1 << 4) /**< \brief (TC_IER2) RC Compare */ -#define TC_IER2_LDRAS (0x1 << 5) /**< \brief (TC_IER2) RA Loading */ -#define TC_IER2_LDRBS (0x1 << 6) /**< \brief (TC_IER2) RB Loading */ -#define TC_IER2_ETRGS (0x1 << 7) /**< \brief (TC_IER2) External Trigger */ -/* -------- TC_IDR2 : (TC Offset: 0xA8) Interrupt Disable Register (channel = 2) -------- */ -#define TC_IDR2_COVFS (0x1 << 0) /**< \brief (TC_IDR2) Counter Overflow */ -#define TC_IDR2_LOVRS (0x1 << 1) /**< \brief (TC_IDR2) Load Overrun */ -#define TC_IDR2_CPAS (0x1 << 2) /**< \brief (TC_IDR2) RA Compare */ -#define TC_IDR2_CPBS (0x1 << 3) /**< \brief (TC_IDR2) RB Compare */ -#define TC_IDR2_CPCS (0x1 << 4) /**< \brief (TC_IDR2) RC Compare */ -#define TC_IDR2_LDRAS (0x1 << 5) /**< \brief (TC_IDR2) RA Loading */ -#define TC_IDR2_LDRBS (0x1 << 6) /**< \brief (TC_IDR2) RB Loading */ -#define TC_IDR2_ETRGS (0x1 << 7) /**< \brief (TC_IDR2) External Trigger */ -/* -------- TC_IMR2 : (TC Offset: 0xAC) Interrupt Mask Register (channel = 2) -------- */ -#define TC_IMR2_COVFS (0x1 << 0) /**< \brief (TC_IMR2) Counter Overflow */ -#define TC_IMR2_LOVRS (0x1 << 1) /**< \brief (TC_IMR2) Load Overrun */ -#define TC_IMR2_CPAS (0x1 << 2) /**< \brief (TC_IMR2) RA Compare */ -#define TC_IMR2_CPBS (0x1 << 3) /**< \brief (TC_IMR2) RB Compare */ -#define TC_IMR2_CPCS (0x1 << 4) /**< \brief (TC_IMR2) RC Compare */ -#define TC_IMR2_LDRAS (0x1 << 5) /**< \brief (TC_IMR2) RA Loading */ -#define TC_IMR2_LDRBS (0x1 << 6) /**< \brief (TC_IMR2) RB Loading */ -#define TC_IMR2_ETRGS (0x1 << 7) /**< \brief (TC_IMR2) External Trigger */ -/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ -#define TC_BCR_SYNC (0x1 << 0) /**< \brief (TC_BCR) Synchro Command */ -/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ -#define TC_BMR_TC0XC0S (0x3 << 0) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ -#define TC_BMR_TC0XC0S_TCLK0 (0x0 << 0) /**< \brief (TC_BMR) TCLK0 */ -#define TC_BMR_TC0XC0S_NONE (0x1 << 0) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC0XC0S_TIOA1 (0x2 << 0) /**< \brief (TC_BMR) TIOA1 */ -#define TC_BMR_TC0XC0S_TIOA2 (0x3 << 0) /**< \brief (TC_BMR) TIOA2 */ -#define TC_BMR_TC1XC1S (0x3 << 2) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ -#define TC_BMR_TC1XC1S_TCLK1 (0x0 << 2) /**< \brief (TC_BMR) TCLK1 */ -#define TC_BMR_TC1XC1S_NONE (0x1 << 2) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC1XC1S_TIOA0 (0x2 << 2) /**< \brief (TC_BMR) TIOA0 */ -#define TC_BMR_TC1XC1S_TIOA2 (0x3 << 2) /**< \brief (TC_BMR) TIOA2 */ -#define TC_BMR_TC2XC2S (0x3 << 4) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ -#define TC_BMR_TC2XC2S_TCLK2 (0x0 << 4) /**< \brief (TC_BMR) TCLK2 */ -#define TC_BMR_TC2XC2S_NONE (0x1 << 4) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC2XC2S_TIOA0 (0x2 << 4) /**< \brief (TC_BMR) TIOA0 */ -#define TC_BMR_TC2XC2S_TIOA1 (0x3 << 4) /**< \brief (TC_BMR) TIOA1 */ -#define TC_BMR_QDEN (0x1 << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */ -#define TC_BMR_POSEN (0x1 << 9) /**< \brief (TC_BMR) POSition ENabled */ -#define TC_BMR_SPEEDEN (0x1 << 10) /**< \brief (TC_BMR) SPEED ENabled */ -#define TC_BMR_QDTRANS (0x1 << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */ -#define TC_BMR_EDGPHA (0x1 << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */ -#define TC_BMR_INVA (0x1 << 13) /**< \brief (TC_BMR) INVerted phA */ -#define TC_BMR_INVB (0x1 << 14) /**< \brief (TC_BMR) INVerted phB */ -#define TC_BMR_INVIDX (0x1 << 15) /**< \brief (TC_BMR) INVerted InDeX */ -#define TC_BMR_SWAP (0x1 << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */ -#define TC_BMR_IDXPHB (0x1 << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */ -#define TC_BMR_FILTER (0x1 << 19) /**< \brief (TC_BMR) */ -#define TC_BMR_MAXFILT (0x3f << 20) /**< \brief (TC_BMR) MAXimum FILTer */ -/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ -#define TC_QIER_IDX (0x1 << 0) /**< \brief (TC_QIER) InDeX */ -#define TC_QIER_DIRCHG (0x1 << 1) /**< \brief (TC_QIER) DIRection CHanGe */ -#define TC_QIER_QERR (0x1 << 2) /**< \brief (TC_QIER) Quadrature ERRor */ -/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ -#define TC_QIDR_IDX (0x1 << 0) /**< \brief (TC_QIDR) InDeX */ -#define TC_QIDR_DIRCHG (0x1 << 1) /**< \brief (TC_QIDR) DIRection CHanGe */ -#define TC_QIDR_QERR (0x1 << 2) /**< \brief (TC_QIDR) Quadrature ERRor */ -/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ -#define TC_QIMR_IDX (0x1 << 0) /**< \brief (TC_QIMR) InDeX */ -#define TC_QIMR_DIRCHG (0x1 << 1) /**< \brief (TC_QIMR) DIRection CHanGe */ -#define TC_QIMR_QERR (0x1 << 2) /**< \brief (TC_QIMR) Quadrature ERRor */ -/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ -#define TC_QISR_IDX (0x1 << 0) /**< \brief (TC_QISR) InDeX */ -#define TC_QISR_DIRCHG (0x1 << 1) /**< \brief (TC_QISR) DIRection CHanGe */ -#define TC_QISR_QERR (0x1 << 2) /**< \brief (TC_QISR) Quadrature ERRor */ -#define TC_QISR_DIR (0x1 << 8) /**< \brief (TC_QISR) Direction */ -/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ -#define TC_FMR_ENCF0 (0x1 << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */ -#define TC_FMR_ENCF1 (0x1 << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */ -/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */ -#define TC_WPMR_WPEN (0x1 << 0) /**< \brief (TC_WPMR) Write Protect Enable */ -#define TC_WPMR_WPKEY (0xffffff << 8) /**< \brief (TC_WPMR) Write Protect KEY */ -/* -------- TC_VER : (TC Offset: 0xFC) Version Register -------- */ -#define TC_VER_VERSION (0xfff << 0) /**< \brief (TC_VER) */ -#define TC_VER_MFN (0x7 << 16) /**< \brief (TC_VER) */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Two-wire Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_TWI Two-wire Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Twi hardware registers */ -typedef struct { - WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */ - RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */ - RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */ - RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */ - RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */ - RwReg Reserved1[3]; - RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */ - WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */ - WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */ - RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */ - RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */ - WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */ - RwReg Reserved2[50]; - RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */ - RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */ - RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */ - RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */ - RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */ - RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */ - RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */ - RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */ - WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */ - RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */ -} Twi; -#endif /* __ASSEMBLY__ */ -/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */ -#define TWI_CR_START (0x1 << 0) /**< \brief (TWI_CR) Send a START Condition */ -#define TWI_CR_STOP (0x1 << 1) /**< \brief (TWI_CR) Send a STOP Condition */ -#define TWI_CR_MSEN (0x1 << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */ -#define TWI_CR_MSDIS (0x1 << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */ -#define TWI_CR_SVEN (0x1 << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */ -#define TWI_CR_SVDIS (0x1 << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */ -#define TWI_CR_QUICK (0x1 << 6) /**< \brief (TWI_CR) SMBUS Quick Command */ -#define TWI_CR_SWRST (0x1 << 7) /**< \brief (TWI_CR) Software Reset */ -/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */ -#define TWI_MMR_IADRSZ (0x3 << 8) /**< \brief (TWI_MMR) Internal Device Address Size */ -#define TWI_MMR_IADRSZ_NO (0x0 << 8) /**< \brief (TWI_MMR) No internal device address */ -#define TWI_MMR_IADRSZ_1_BYTE (0x1 << 8) /**< \brief (TWI_MMR) One-byte internal device address */ -#define TWI_MMR_IADRSZ_2_BYTE (0x2 << 8) /**< \brief (TWI_MMR) Two-byte internal device address */ -#define TWI_MMR_IADRSZ_3_BYTE (0x3 << 8) /**< \brief (TWI_MMR) Three-byte internal device address */ -#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) -#define TWI_MMR_IADRSZ_Pos 8 -#define TWI_MMR_MREAD (0x1 << 12) /**< \brief (TWI_MMR) Master Read Direction */ -#define TWI_MMR_DADR_Pos 16 -#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */ -#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos))) -/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */ -#define TWI_SMR_SADR_Pos 16 -#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */ -#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos))) -/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */ -#define TWI_IADR_IADR_Pos 0 -#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */ -#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos))) -/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */ -#define TWI_CWGR_CLDIV_Pos 0 -#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */ -#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos))) -#define TWI_CWGR_CHDIV_Pos 8 -#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */ -#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos))) -#define TWI_CWGR_CKDIV_Pos 16 -#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */ -#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos))) -/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */ -#define TWI_SR_TXCOMP (0x1 << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */ -#define TWI_SR_RXRDY (0x1 << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */ -#define TWI_SR_TXRDY (0x1 << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */ -#define TWI_SR_SVREAD (0x1 << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */ -#define TWI_SR_SVACC (0x1 << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */ -#define TWI_SR_GACC (0x1 << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */ -#define TWI_SR_OVRE (0x1 << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */ -#define TWI_SR_NACK (0x1 << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */ -#define TWI_SR_ARBLST (0x1 << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */ -#define TWI_SR_SCLWS (0x1 << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */ -#define TWI_SR_EOSACC (0x1 << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */ -#define TWI_SR_ENDRX (0x1 << 12) /**< \brief (TWI_SR) End of RX buffer */ -#define TWI_SR_ENDTX (0x1 << 13) /**< \brief (TWI_SR) End of TX buffer */ -#define TWI_SR_RXBUFF (0x1 << 14) /**< \brief (TWI_SR) RX Buffer Full */ -#define TWI_SR_TXBUFE (0x1 << 15) /**< \brief (TWI_SR) TX Buffer Empty */ -/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */ -#define TWI_IER_TXCOMP (0x1 << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */ -#define TWI_IER_RXRDY (0x1 << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */ -#define TWI_IER_TXRDY (0x1 << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */ -#define TWI_IER_SVACC (0x1 << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */ -#define TWI_IER_GACC (0x1 << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */ -#define TWI_IER_OVRE (0x1 << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */ -#define TWI_IER_NACK (0x1 << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */ -#define TWI_IER_ARBLST (0x1 << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */ -#define TWI_IER_SCL_WS (0x1 << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */ -#define TWI_IER_EOSACC (0x1 << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */ -#define TWI_IER_ENDRX (0x1 << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */ -#define TWI_IER_ENDTX (0x1 << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */ -#define TWI_IER_RXBUFF (0x1 << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */ -#define TWI_IER_TXBUFE (0x1 << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */ -/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */ -#define TWI_IDR_TXCOMP (0x1 << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */ -#define TWI_IDR_RXRDY (0x1 << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */ -#define TWI_IDR_TXRDY (0x1 << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */ -#define TWI_IDR_SVACC (0x1 << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */ -#define TWI_IDR_GACC (0x1 << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */ -#define TWI_IDR_OVRE (0x1 << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */ -#define TWI_IDR_NACK (0x1 << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */ -#define TWI_IDR_ARBLST (0x1 << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */ -#define TWI_IDR_SCL_WS (0x1 << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */ -#define TWI_IDR_EOSACC (0x1 << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */ -#define TWI_IDR_ENDRX (0x1 << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */ -#define TWI_IDR_ENDTX (0x1 << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */ -#define TWI_IDR_RXBUFF (0x1 << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */ -#define TWI_IDR_TXBUFE (0x1 << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */ -/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */ -#define TWI_IMR_TXCOMP (0x1 << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */ -#define TWI_IMR_RXRDY (0x1 << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */ -#define TWI_IMR_TXRDY (0x1 << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */ -#define TWI_IMR_SVACC (0x1 << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */ -#define TWI_IMR_GACC (0x1 << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */ -#define TWI_IMR_OVRE (0x1 << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */ -#define TWI_IMR_NACK (0x1 << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */ -#define TWI_IMR_ARBLST (0x1 << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */ -#define TWI_IMR_SCL_WS (0x1 << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */ -#define TWI_IMR_EOSACC (0x1 << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */ -#define TWI_IMR_ENDRX (0x1 << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */ -#define TWI_IMR_ENDTX (0x1 << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */ -#define TWI_IMR_RXBUFF (0x1 << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */ -#define TWI_IMR_TXBUFE (0x1 << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */ -/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */ -#define TWI_RHR_RXDATA (0xff << 0) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */ -/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */ -#define TWI_THR_TXDATA (0xff << 0) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */ -/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */ -#define TWI_RPR_RXPTR (0xffffffff << 0) /**< \brief (TWI_RPR) Receive Pointer Register */ -/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */ -#define TWI_RCR_RXCTR (0xffff << 0) /**< \brief (TWI_RCR) Receive Counter Register */ -/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */ -#define TWI_TPR_TXPTR (0xffffffff << 0) /**< \brief (TWI_TPR) Transmit Counter Register */ -/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */ -#define TWI_TCR_TXCTR (0xffff << 0) /**< \brief (TWI_TCR) Transmit Counter Register */ -/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */ -#define TWI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (TWI_RNPR) Receive Next Pointer */ -/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */ -#define TWI_RNCR_RXNCTR (0xffff << 0) /**< \brief (TWI_RNCR) Receive Next Counter */ -/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define TWI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (TWI_TNPR) Transmit Next Pointer */ -/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define TWI_TNCR_TXNCTR (0xffff << 0) /**< \brief (TWI_TNCR) Transmit Counter Next */ -/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */ -#define TWI_PTCR_RXTEN (0x1 << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */ -#define TWI_PTCR_RXTDIS (0x1 << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */ -#define TWI_PTCR_TXTEN (0x1 << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */ -#define TWI_PTCR_TXTDIS (0x1 << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */ -/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */ -#define TWI_PTSR_RXTEN (0x1 << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */ -#define TWI_PTSR_TXTEN (0x1 << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_UART Universal Asynchronous Receiver Transmitter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Uart hardware registers */ -typedef struct { - WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ - RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ - WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ - WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ - RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ - RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ - RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ - WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ - RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ - RwReg Reserved1[55]; - RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */ - RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */ - RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */ - RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */ - RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */ - RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */ - RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */ - RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */ - WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */ - RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */ -} Uart; -#endif /* __ASSEMBLY__ */ -/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ -#define UART_CR_RSTRX (0x1 << 2) /**< \brief (UART_CR) Reset Receiver */ -#define UART_CR_RSTTX (0x1 << 3) /**< \brief (UART_CR) Reset Transmitter */ -#define UART_CR_RXEN (0x1 << 4) /**< \brief (UART_CR) Receiver Enable */ -#define UART_CR_RXDIS (0x1 << 5) /**< \brief (UART_CR) Receiver Disable */ -#define UART_CR_TXEN (0x1 << 6) /**< \brief (UART_CR) Transmitter Enable */ -#define UART_CR_TXDIS (0x1 << 7) /**< \brief (UART_CR) Transmitter Disable */ -#define UART_CR_RSTSTA (0x1 << 8) /**< \brief (UART_CR) Reset Status Bits */ -/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ -#define UART_MR_PAR (0x7 << 9) /**< \brief (UART_MR) Parity Type */ -#define UART_MR_CHMODE (0x3 << 14) /**< \brief (UART_MR) Channel Mode */ -/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ -#define UART_IER_RXRDY (0x1 << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ -#define UART_IER_TXRDY (0x1 << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ -#define UART_IER_ENDRX (0x1 << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */ -#define UART_IER_ENDTX (0x1 << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */ -#define UART_IER_OVRE (0x1 << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ -#define UART_IER_FRAME (0x1 << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ -#define UART_IER_PARE (0x1 << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ -#define UART_IER_TXEMPTY (0x1 << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ -#define UART_IER_TXBUFE (0x1 << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */ -#define UART_IER_RXBUFF (0x1 << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */ -/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ -#define UART_IDR_RXRDY (0x1 << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ -#define UART_IDR_TXRDY (0x1 << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ -#define UART_IDR_ENDRX (0x1 << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */ -#define UART_IDR_ENDTX (0x1 << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */ -#define UART_IDR_OVRE (0x1 << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ -#define UART_IDR_FRAME (0x1 << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ -#define UART_IDR_PARE (0x1 << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ -#define UART_IDR_TXEMPTY (0x1 << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ -#define UART_IDR_TXBUFE (0x1 << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */ -#define UART_IDR_RXBUFF (0x1 << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */ -/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ -#define UART_IMR_RXRDY (0x1 << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ -#define UART_IMR_TXRDY (0x1 << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ -#define UART_IMR_ENDRX (0x1 << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */ -#define UART_IMR_ENDTX (0x1 << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */ -#define UART_IMR_OVRE (0x1 << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ -#define UART_IMR_FRAME (0x1 << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ -#define UART_IMR_PARE (0x1 << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ -#define UART_IMR_TXEMPTY (0x1 << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ -#define UART_IMR_TXBUFE (0x1 << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */ -#define UART_IMR_RXBUFF (0x1 << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */ -/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ -#define UART_SR_RXRDY (0x1 << 0) /**< \brief (UART_SR) Receiver Ready */ -#define UART_SR_TXRDY (0x1 << 1) /**< \brief (UART_SR) Transmitter Ready */ -#define UART_SR_ENDRX (0x1 << 3) /**< \brief (UART_SR) End of Receiver Transfer */ -#define UART_SR_ENDTX (0x1 << 4) /**< \brief (UART_SR) End of Transmitter Transfer */ -#define UART_SR_OVRE (0x1 << 5) /**< \brief (UART_SR) Overrun Error */ -#define UART_SR_FRAME (0x1 << 6) /**< \brief (UART_SR) Framing Error */ -#define UART_SR_PARE (0x1 << 7) /**< \brief (UART_SR) Parity Error */ -#define UART_SR_TXEMPTY (0x1 << 9) /**< \brief (UART_SR) Transmitter Empty */ -#define UART_SR_TXBUFE (0x1 << 11) /**< \brief (UART_SR) Transmission Buffer Empty */ -#define UART_SR_RXBUFF (0x1 << 12) /**< \brief (UART_SR) Receive Buffer Full */ -/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ -#define UART_RHR_RXCHR (0xff << 0) /**< \brief (UART_RHR) Received Character */ -/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ -#define UART_THR_TXCHR (0xff << 0) /**< \brief (UART_THR) Character to be Transmitted */ -/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ -#define UART_BRGR_CD (0xffff << 0) /**< \brief (UART_BRGR) Clock Divisor */ -/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */ -#define UART_RPR_RXPTR (0xffffffff << 0) /**< \brief (UART_RPR) Receive Pointer Register */ -/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */ -#define UART_RCR_RXCTR (0xffff << 0) /**< \brief (UART_RCR) Receive Counter Register */ -/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */ -#define UART_TPR_TXPTR (0xffffffff << 0) /**< \brief (UART_TPR) Transmit Counter Register */ -/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */ -#define UART_TCR_TXCTR (0xffff << 0) /**< \brief (UART_TCR) Transmit Counter Register */ -/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */ -#define UART_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (UART_RNPR) Receive Next Pointer */ -/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */ -#define UART_RNCR_RXNCTR (0xffff << 0) /**< \brief (UART_RNCR) Receive Next Counter */ -/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */ -#define UART_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (UART_TNPR) Transmit Next Pointer */ -/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */ -#define UART_TNCR_TXNCTR (0xffff << 0) /**< \brief (UART_TNCR) Transmit Counter Next */ -/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */ -#define UART_PTCR_RXTEN (0x1 << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */ -#define UART_PTCR_RXTDIS (0x1 << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */ -#define UART_PTCR_TXTEN (0x1 << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */ -#define UART_PTCR_TXTDIS (0x1 << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */ -/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */ -#define UART_PTSR_RXTEN (0x1 << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */ -#define UART_PTSR_TXTEN (0x1 << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR USB Device Port */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_UDP USB Device Port */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Udp hardware registers */ -typedef struct { - RoReg UDP_FRM_NUM; /**< \brief (Udp Offset: 0x000) Frame Number Register */ - RwReg UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */ - RwReg UDP_FADDR; /**< \brief (Udp Offset: 0x008) Function Address Register */ - RwReg Reserved1[1]; - WoReg UDP_IER; /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */ - WoReg UDP_IDR; /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */ - RoReg UDP_IMR; /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */ - RoReg UDP_ISR; /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */ - WoReg UDP_ICR; /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */ - RwReg Reserved2[1]; - RwReg UDP_RST_EP; /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */ - RwReg Reserved3[1]; - RwReg UDP_CSR[8]; /**< \brief (Udp Offset: 0x30) Endpoint Control and Status Register (ept_num = 0) */ - RwReg UDP_FDR[8]; /**< \brief (Udp Offset: 0x50) Endpoint FIFO Data Register (ept_num = 0) */ - RwReg Reserved4[1]; - RwReg UDP_TXVC; /**< \brief (Udp Offset: 0x074) Transceiver Control Register */ -} Udp; -#endif /* __ASSEMBLY__ */ -/* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */ -#define UDP_FRM_NUM_FRM_NUM (0x7ff << 0) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */ -#define UDP_FRM_NUM_FRM_ERR (0x1 << 16) /**< \brief (UDP_FRM_NUM) Frame Error */ -#define UDP_FRM_NUM_FRM_OK (0x1 << 17) /**< \brief (UDP_FRM_NUM) Frame OK */ -/* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */ -#define UDP_GLB_STAT_FADDEN (0x1 << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */ -#define UDP_GLB_STAT_CONFG (0x1 << 1) /**< \brief (UDP_GLB_STAT) Configured */ -#define UDP_GLB_STAT_ESR (0x1 << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */ -#define UDP_GLB_STAT_RSMINPR (0x1 << 3) /**< \brief (UDP_GLB_STAT) */ -#define UDP_GLB_STAT_RMWUPE (0x1 << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */ -/* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */ -#define UDP_FADDR_FADD_Pos 0 -#define UDP_FADDR_FADD_Msk (0x7fu << UDP_FADDR_FADD_Pos) /**< \brief (UDP_FADDR) Function Address Value */ -#define UDP_FADDR_FADD(value) ((UDP_FADDR_FADD_Msk & ((value) << UDP_FADDR_FADD_Pos))) -#define UDP_FADDR_FEN (0x1u << 8) /**< \brief (UDP_FADDR) Function Enable */ -/* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */ -#define UDP_IER_EP0INT (0x1 << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */ -#define UDP_IER_EP1INT (0x1 << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */ -#define UDP_IER_EP2INT (0x1 << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */ -#define UDP_IER_EP3INT (0x1 << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */ -#define UDP_IER_EP4INT (0x1 << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */ -#define UDP_IER_EP5INT (0x1 << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */ -#define UDP_IER_EP6INT (0x1 << 6) /**< \brief (UDP_IER) Enable Endpoint 6 Interrupt */ -#define UDP_IER_EP7INT (0x1 << 7) /**< \brief (UDP_IER) Enable Endpoint 7 Interrupt */ -#define UDP_IER_RXSUSP (0x1 << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */ -#define UDP_IER_RXRSM (0x1 << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */ -#define UDP_IER_EXTRSM (0x1 << 10) /**< \brief (UDP_IER) */ -#define UDP_IER_SOFINT (0x1 << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */ -#define UDP_IER_WAKEUP (0x1 << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */ -/* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */ -#define UDP_IDR_EP0INT (0x1 << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */ -#define UDP_IDR_EP1INT (0x1 << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */ -#define UDP_IDR_EP2INT (0x1 << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */ -#define UDP_IDR_EP3INT (0x1 << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */ -#define UDP_IDR_EP4INT (0x1 << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */ -#define UDP_IDR_EP5INT (0x1 << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */ -#define UDP_IDR_EP6INT (0x1 << 6) /**< \brief (UDP_IDR) Disable Endpoint 6 Interrupt */ -#define UDP_IDR_EP7INT (0x1 << 7) /**< \brief (UDP_IDR) Disable Endpoint 7 Interrupt */ -#define UDP_IDR_RXSUSP (0x1 << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */ -#define UDP_IDR_RXRSM (0x1 << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */ -#define UDP_IDR_EXTRSM (0x1 << 10) /**< \brief (UDP_IDR) */ -#define UDP_IDR_SOFINT (0x1 << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */ -#define UDP_IDR_WAKEUP (0x1 << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */ -/* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */ -#define UDP_IMR_EP0INT (0x1 << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */ -#define UDP_IMR_EP1INT (0x1 << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */ -#define UDP_IMR_EP2INT (0x1 << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */ -#define UDP_IMR_EP3INT (0x1 << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */ -#define UDP_IMR_EP4INT (0x1 << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */ -#define UDP_IMR_EP5INT (0x1 << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */ -#define UDP_IMR_EP6INT (0x1 << 6) /**< \brief (UDP_IMR) Mask Endpoint 6 Interrupt */ -#define UDP_IMR_EP7INT (0x1 << 7) /**< \brief (UDP_IMR) Mask Endpoint 7 Interrupt */ -#define UDP_IMR_RXSUSP (0x1 << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */ -#define UDP_IMR_RXRSM (0x1 << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */ -#define UDP_IMR_EXTRSM (0x1 << 10) /**< \brief (UDP_IMR) */ -#define UDP_IMR_SOFINT (0x1 << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */ -#define UDP_IMR_BIT12 (0x1 << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */ -#define UDP_IMR_WAKEUP (0x1 << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */ -/* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */ -#define UDP_ISR_EP0INT (0x1 << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */ -#define UDP_ISR_EP1INT (0x1 << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */ -#define UDP_ISR_EP2INT (0x1 << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */ -#define UDP_ISR_EP3INT (0x1 << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */ -#define UDP_ISR_EP4INT (0x1 << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */ -#define UDP_ISR_EP5INT (0x1 << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */ -#define UDP_ISR_EP6INT (0x1 << 6) /**< \brief (UDP_ISR) Endpoint 6 Interrupt Status */ -#define UDP_ISR_EP7INT (0x1 << 7) /**< \brief (UDP_ISR) Endpoint 7Interrupt Status */ -#define UDP_ISR_RXSUSP (0x1 << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */ -#define UDP_ISR_RXRSM (0x1 << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ -#define UDP_ISR_EXTRSM (0x1 << 10) /**< \brief (UDP_ISR) */ -#define UDP_ISR_SOFINT (0x1 << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */ -#define UDP_ISR_ENDBUSRES (0x1 << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */ -#define UDP_ISR_WAKEUP (0x1 << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ -/* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */ -#define UDP_ICR_RXSUSP (0x1 << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */ -#define UDP_ICR_RXRSM (0x1 << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */ -#define UDP_ICR_EXTRSM (0x1 << 10) /**< \brief (UDP_ICR) */ -#define UDP_ICR_SOFINT (0x1 << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */ -#define UDP_ICR_ENDBUSRES (0x1 << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */ -#define UDP_ICR_WAKEUP (0x1 << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */ -/* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */ -#define UDP_RST_EP_EP0 (0x1 << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */ -#define UDP_RST_EP_EP1 (0x1 << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */ -#define UDP_RST_EP_EP2 (0x1 << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */ -#define UDP_RST_EP_EP3 (0x1 << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */ -#define UDP_RST_EP_EP4 (0x1 << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */ -#define UDP_RST_EP_EP5 (0x1 << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */ -#define UDP_RST_EP_EP6 (0x1 << 6) /**< \brief (UDP_RST_EP) Reset Endpoint 6 */ -#define UDP_RST_EP_EP7 (0x1 << 7) /**< \brief (UDP_RST_EP) Reset Endpoint 7 */ -/* -------- UDP_CSR[8] : (UDP Offset: 0x2C) Endpoint Control and Status Register (ept_num = 0) -------- */ -#define UDP_CSR_TXCOMP (0x1 << 0) /**< \brief (UDP_CSR[8]) Generates an IN Packet with Data Previously Written in the DPR */ -#define UDP_CSR_RX_DATA_BK0 (0x1 << 1) /**< \brief (UDP_CSR[8]) Receive Data Bank 0 */ -#define UDP_CSR_RXSETUP (0x1 << 2) /**< \brief (UDP_CSR[8]) Received Setup */ -#define UDP_CSR_STALLSENTISOERROR (0x1 << 3) /**< \brief (UDP_CSR[8]) */ -#define UDP_CSR_TXPKTRDY (0x1 << 4) /**< \brief (UDP_CSR[8]) Transmit Packet Ready */ -#define UDP_CSR_FORCESTALL (0x1 << 5) /**< \brief (UDP_CSR[8]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */ -#define UDP_CSR_RX_DATA_BK1 (0x1 << 6) /**< \brief (UDP_CSR[8]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */ -#define UDP_CSR_DIR (0x1 << 7) /**< \brief (UDP_CSR[8]) Transfer Direction (only available for control endpoints) */ -#define UDP_CSR_EPTYPE_Pos 8 -#define UDP_CSR_EPTYPE_Msk (0x7u << UDP_CSR_EPTYPE_Pos) /**< \brief (UDP_CSR[8]) Endpoint Type */ -#define UDP_CSR_EPTYPE_CTRL (0x0u << 8) /**< \brief (UDP_CSR[8]) Control */ -#define UDP_CSR_EPTYPE_ISO_OUT (0x1u << 8) /**< \brief (UDP_CSR[8]) Isochronous OUT */ -#define UDP_CSR_EPTYPE_BULK_OUT (0x2u << 8) /**< \brief (UDP_CSR[8]) Bulk OUT */ -#define UDP_CSR_EPTYPE_INT_OUT (0x3u << 8) /**< \brief (UDP_CSR[8]) Interrupt OUT */ -#define UDP_CSR_EPTYPE_ISO_IN (0x5u << 8) /**< \brief (UDP_CSR[8]) Isochronous IN */ -#define UDP_CSR_EPTYPE_BULK_IN (0x6u << 8) /**< \brief (UDP_CSR[8]) Bulk IN */ -#define UDP_CSR_EPTYPE_INT_IN (0x7u << 8) /**< \brief (UDP_CSR[8]) Interrupt IN */ -#define UDP_CSR_DTGLE (0x1 << 11) /**< \brief (UDP_CSR[8]) Data Toggle */ -#define UDP_CSR_EPEDS (0x1 << 15) /**< \brief (UDP_CSR[8]) Endpoint Enable Disable */ -#define UDP_CSR_RXBYTECNT_Pos 16 -#define UDP_CSR_RXBYTECNT_Msk (0x7ffu << UDP_CSR_RXBYTECNT_Pos) /**< \brief (UDP_CSR[8]) Number of Bytes Available in the FIFO */ -#define UDP_CSR_RXBYTECNT(value) ((UDP_CSR_RXBYTECNT_Msk & ((value) << UDP_CSR_RXBYTECNT_Pos))) -/* -------- UDP_FDR[8] : (UDP Offset: 0x4C) Endpoint FIFO Data Register (ept_num = 0) -------- */ -#define UDP_FDR_FIFO_DATA (0xff << 0) /**< \brief (UDP_FDR[8]) FIFO Data Value */ -/* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */ -#define UDP_TXVC_TXVDIS (0x1 << 8) /**< \brief (UDP_TXVC) Transceiver Disable */ -#define UDP_TXVC_PUON (0x1 << 9) /**< \brief (UDP_TXVC) Pullup On */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_USART Universal Synchronous Asynchronous Receiver Transmitter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Usart hardware registers */ -typedef struct { - WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ - RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ - WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ - WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ - RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ - RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ - RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */ - WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */ - RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ - RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ - RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ - RwReg Reserved1[5]; - RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ - RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ - RwReg Reserved2[1]; - RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ - RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */ - RwReg Reserved3[36]; - RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */ - RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */ - RwReg Reserved4[4]; - RoReg US_VERSION; /**< \brief (Usart Offset: 0xFC) Version Register */ - RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */ - RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */ - RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */ - RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */ - RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */ - RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */ - RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */ - RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */ - WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */ - RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */ -} Usart; -#endif /* __ASSEMBLY__ */ -/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ -#define US_CR_RSTRX (0x1 << 2) /**< \brief (US_CR) Reset Receiver */ -#define US_CR_RSTTX (0x1 << 3) /**< \brief (US_CR) Reset Transmitter */ -#define US_CR_RXEN (0x1 << 4) /**< \brief (US_CR) Receiver Enable */ -#define US_CR_RXDIS (0x1 << 5) /**< \brief (US_CR) Receiver Disable */ -#define US_CR_TXEN (0x1 << 6) /**< \brief (US_CR) Transmitter Enable */ -#define US_CR_TXDIS (0x1 << 7) /**< \brief (US_CR) Transmitter Disable */ -#define US_CR_RSTSTA (0x1 << 8) /**< \brief (US_CR) Reset Status Bits */ -#define US_CR_STTBRK (0x1 << 9) /**< \brief (US_CR) Start Break */ -#define US_CR_STPBRK (0x1 << 10) /**< \brief (US_CR) Stop Break */ -#define US_CR_STTTO (0x1 << 11) /**< \brief (US_CR) Start Time-out */ -#define US_CR_SENDA (0x1 << 12) /**< \brief (US_CR) Send Address */ -#define US_CR_RSTIT (0x1 << 13) /**< \brief (US_CR) Reset Iterations */ -#define US_CR_RSTNACK (0x1 << 14) /**< \brief (US_CR) Reset Non Acknowledge */ -#define US_CR_RETTO (0x1 << 15) /**< \brief (US_CR) Rearm Time-out */ -#define US_CR_DTREN (0x1 << 16) /**< \brief (US_CR) Data Terminal Ready Enable */ -#define US_CR_DTRDIS (0x1 << 17) /**< \brief (US_CR) Data Terminal Ready Disable */ -#define US_CR_RTSEN__FCS (0x1 << 18) /**< \brief (US_CR) Request to Send Enable/Force SPI Chip Select */ -#define US_CR_RTSDIS__RCS (0x1 << 19) /**< \brief (US_CR) Request to Send Disable/Release SPI Chip Select */ -/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ -#define US_MR_USART_MODE (0xf << 0) /**< \brief (US_MR) */ -#define US_MR_USART_MODE_NORMAL (0x0) /**< (USART) Normal*/ -#define US_MR_USART_MODE_RS485 (0x1) /**< (USART) RS485*/ -#define US_MR_USART_MODE_HWHSH (0x2) /**< (USART) Hardware Handshaking*/ -#define US_MR_USART_MODE_ISO7816_0 (0x4) /**< (USART) ISO7816 protocol: T = 0*/ -#define US_MR_USART_MODE_ISO7816_1 (0x6) /**< (USART) ISO7816 protocol: T = 1*/ -#define US_MR_USART_MODE_IRDA (0x8) /**< (USART) IrDA*/ -#define US_MR_USART_MODE_SPIM (0xE) /**< (USART) SPI Master*/ -#define US_MR_USART_MODE_SPIS (0xF) /**< (USART) SPI Slave*/ -#define US_MR_USCLKS (0x3 << 4) /**< \brief (US_MR) Clock Selection */ -#define US_MR_USCLKS_CLOCK (0x0 << 4) /**< (USART) MCK*/ -#define US_MR_USCLKS_FDIV1 (0x1 << 4) /**< (USART) MCK/DIV(DIV=8)*/ -#define US_MR_USCLKS_SLOW (0x2 << 4) /**< (USART) Reserved*/ -#define US_MR_USCLKS_EXT (0x3 << 4) /**< (USART) SCK*/ -#define US_MR_CHRL (0x3 << 6) /**< \brief (US_MR) Character Length. */ -#define US_MR_CHRL_5_BITS (0x0 << 6) /**< (USART) Character Length: 5 bits*/ -#define US_MR_CHRL_6_BITS (0x1 << 6) /**< (USART) Character Length: 6 bits*/ -#define US_MR_CHRL_7_BITS (0x2 << 6) /**< (USART) Character Length: 7 bits*/ -#define US_MR_CHRL_8_BITS (0x3 << 6) /**< (USART) Character Length: 8 bits*/ -#define US_MR_SYNC__CPHA (0x1 << 8) /**< \brief (US_MR) Synchronous Mode Select or SPI Clock Phase */ -#define US_MR_PAR (0x7 << 9) /**< \brief (US_MR) Parity Type */ -#define US_MR_PAR_EVEN (0x0 << 9) /**< (USART) Even Parity*/ -#define US_MR_PAR_ODD (0x1 << 9) /**< (USART) Odd Parity*/ -#define US_MR_PAR_SPACE (0x2 << 9) /**< (USART) Parity forced to 0 (Space)*/ -#define US_MR_PAR_MARK (0x3 << 9) /**< (USART) Parity forced to 1 (Mark)*/ -#define US_MR_PAR_NONE (0x4 << 9) /**< (USART) No Parity*/ -#define US_MR_PAR_MULTI_DROP (0x6 << 9) /**< (USART) Multi-drop mode*/ -#define US_MR_NBSTOP (0x3 << 12) /**< \brief (US_MR) Number of Stop Bits */ -#define US_MR_NBSTOP_1_BIT (0x0 << 12) /**< (USART) 1 stop bit*/ -#define US_MR_NBSTOP_15_BIT (0x1 << 12) /**< (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits*/ -#define US_MR_NBSTOP_2_BIT (0x2 << 12) /**< (USART) 2 stop bits*/ -#define US_MR_CHMODE (0x3 << 14) /**< \brief (US_MR) Channel Mode */ -#define US_MR_CHMODE_NORMAL (0x0 << 14) /**< (USART) Normal Mode: The USART channel operates as an RX/TX USART.*/ -#define US_MR_CHMODE_AUTO (0x1 << 14) /**< (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin.*/ -#define US_MR_CHMODE_LOCAL (0x2 << 14) /**< (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.*/ -#define US_MR_CHMODE_REMOTE (0x3 << 14) /**< (USART) Remote Loopback: RXD pin is internally connected to TXD pin.*/ -#define US_MR_MSBF__CPOL (0x1 << 16) /**< \brief (US_MR) Bit Order or SPI Clock Polarity */ -#define US_MR_MODE9 (0x1 << 17) /**< \brief (US_MR) 9-bit Character Length */ -#define US_MR_CLKO (0x1 << 18) /**< \brief (US_MR) Clock Output Select */ -#define US_MR_OVER (0x1 << 19) /**< \brief (US_MR) Oversampling Mode */ -#define US_MR_INACK (0x1 << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ -#define US_MR_DSNACK (0x1 << 21) /**< \brief (US_MR) Disable Successive NACK */ -#define US_MR_VAR_SYNC (0x1 << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ -#define US_MR_INVDATA (0x1 << 23) /**< \brief (US_MR) INverted Data */ -#define US_MR_MAX_ITERATION (0x7 << 24) /**< \brief (US_MR) */ -#define US_MR_FILTER (0x1 << 28) /**< \brief (US_MR) Infrared Receive Line Filter */ -#define US_MR_MAN (0x1 << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ -#define US_MR_MODSYNC_ (0x1 << 30) /**< \brief (US_MR) */ -#define US_MR_ONEBIT (0x1 << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ -/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ -#define US_IER_RXRDY (0x1 << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ -#define US_IER_TXRDY (0x1 << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ -#define US_IER_RXBRK (0x1 << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ -#define US_IER_ENDRX (0x1 << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */ -#define US_IER_ENDTX (0x1 << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */ -#define US_IER_OVRE (0x1 << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ -#define US_IER_FRAME (0x1 << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ -#define US_IER_PARE (0x1 << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ -#define US_IER_TIMEOUT (0x1 << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ -#define US_IER_TXEMPTY (0x1 << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ -#define US_IER_ITER__UNRE (0x1 << 10) /**< \brief (US_IER) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IER_TXBUFE (0x1 << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */ -#define US_IER_RXBUFF (0x1 << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */ -#define US_IER_NACK (0x1 << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */ -#define US_IER_RIIC (0x1 << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */ -#define US_IER_DSRIC (0x1 << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */ -#define US_IER_DCDIC (0x1 << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */ -#define US_IER_CTSIC (0x1 << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ -#define US_IER_MANE (0x1 << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ -/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ -#define US_IDR_RXRDY (0x1 << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ -#define US_IDR_TXRDY (0x1 << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ -#define US_IDR_RXBRK (0x1 << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ -#define US_IDR_ENDRX (0x1 << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */ -#define US_IDR_ENDTX (0x1 << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */ -#define US_IDR_OVRE (0x1 << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */ -#define US_IDR_FRAME (0x1 << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ -#define US_IDR_PARE (0x1 << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ -#define US_IDR_TIMEOUT (0x1 << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ -#define US_IDR_TXEMPTY (0x1 << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ -#define US_IDR_ITER__UNRE (0x1 << 10) /**< \brief (US_IDR) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IDR_TXBUFE (0x1 << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */ -#define US_IDR_RXBUFF (0x1 << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */ -#define US_IDR_NACK (0x1 << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */ -#define US_IDR_RIIC (0x1 << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */ -#define US_IDR_DSRIC (0x1 << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */ -#define US_IDR_DCDIC (0x1 << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */ -#define US_IDR_CTSIC (0x1 << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ -#define US_IDR_MANE (0x1 << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ -/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ -#define US_IMR_RXRDY (0x1 << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ -#define US_IMR_TXRDY (0x1 << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ -#define US_IMR_RXBRK (0x1 << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ -#define US_IMR_ENDRX (0x1 << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */ -#define US_IMR_ENDTX (0x1 << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */ -#define US_IMR_OVRE (0x1 << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ -#define US_IMR_FRAME (0x1 << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ -#define US_IMR_PARE (0x1 << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ -#define US_IMR_TIMEOUT (0x1 << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ -#define US_IMR_TXEMPTY (0x1 << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ -#define US_IMR_ITER__UNRE (0x1 << 10) /**< \brief (US_IMR) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IMR_TXBUFE (0x1 << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */ -#define US_IMR_RXBUFF (0x1 << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */ -#define US_IMR_NACK (0x1 << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */ -#define US_IMR_RIIC (0x1 << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */ -#define US_IMR_DSRIC (0x1 << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */ -#define US_IMR_DCDIC (0x1 << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */ -#define US_IMR_CTSIC (0x1 << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ -#define US_IMR_MANE (0x1 << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ -/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ -#define US_CSR_RXRDY (0x1 << 0) /**< \brief (US_CSR) Receiver Ready */ -#define US_CSR_TXRDY (0x1 << 1) /**< \brief (US_CSR) Transmitter Ready */ -#define US_CSR_RXBRK (0x1 << 2) /**< \brief (US_CSR) Break Received/End of Break */ -#define US_CSR_ENDRX (0x1 << 3) /**< \brief (US_CSR) End of Receiver Transfer */ -#define US_CSR_ENDTX (0x1 << 4) /**< \brief (US_CSR) End of Transmitter Transfer */ -#define US_CSR_OVRE (0x1 << 5) /**< \brief (US_CSR) Overrun Error */ -#define US_CSR_FRAME (0x1 << 6) /**< \brief (US_CSR) Framing Error */ -#define US_CSR_PARE (0x1 << 7) /**< \brief (US_CSR) Parity Error */ -#define US_CSR_TIMEOUT (0x1 << 8) /**< \brief (US_CSR) Receiver Time-out */ -#define US_CSR_TXEMPTY (0x1 << 9) /**< \brief (US_CSR) Transmitter Empty */ -#define US_CSR_ITER__UNRE (0x1 << 10) /**< \brief (US_CSR) Max number of Repetitions Reached or SPI Underrun Error */ -#define US_CSR_TXBUFE (0x1 << 11) /**< \brief (US_CSR) Transmission Buffer Empty */ -#define US_CSR_RXBUFF (0x1 << 12) /**< \brief (US_CSR) Reception Buffer Full */ -#define US_CSR_NACK (0x1 << 13) /**< \brief (US_CSR) */ -#define US_CSR_RIIC (0x1 << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */ -#define US_CSR_DSRIC (0x1 << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */ -#define US_CSR_DCDIC (0x1 << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */ -#define US_CSR_CTSIC (0x1 << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */ -#define US_CSR_RI (0x1 << 20) /**< \brief (US_CSR) Image of RI Input */ -#define US_CSR_DSR (0x1 << 21) /**< \brief (US_CSR) Image of DSR Input */ -#define US_CSR_DCD (0x1 << 22) /**< \brief (US_CSR) Image of DCD Input */ -#define US_CSR_CTS (0x1 << 23) /**< \brief (US_CSR) Image of CTS Input */ -#define US_CSR_MANERR (0x1 << 24) /**< \brief (US_CSR) Manchester Error */ -/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */ -#define US_RHR_RXCHR (0x1ff << 0) /**< \brief (US_RHR) Received Character */ -#define US_RHR_RXSYNH (0x1 << 15) /**< \brief (US_RHR) Received Sync */ -/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */ -#define US_THR_TXCHR (0x1ff << 0) /**< \brief (US_THR) Character to be Transmitted */ -#define US_THR_TXSYNH (0x1 << 15) /**< \brief (US_THR) Sync Field to be transmitted */ -/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ -#define US_BRGR_CD (0xffff << 0) /**< \brief (US_BRGR) Clock Divider */ -#define US_BRGR_FP (0x7 << 16) /**< \brief (US_BRGR) Fractional Part */ -/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ -#define US_RTOR_TO (0xffff << 0) /**< \brief (US_RTOR) Time-out Value */ -/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ -#define US_TTGR_TG (0xff << 0) /**< \brief (US_TTGR) Timeguard Value */ -/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ -#define US_FIDI_FI_DI_RATIO (0x7ff << 0) /**< \brief (US_FIDI) FI Over DI Ratio Value */ -/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ -#define US_NER_NB_ERRORS (0xff << 0) /**< \brief (US_NER) Number of Errors */ -/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ -#define US_IF_IRDA_FILTER (0xff << 0) /**< \brief (US_IF) IrDA Filter */ -/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */ -#define US_MAN_TX_PL (0xf << 0) /**< \brief (US_MAN) Transmitter Preamble Length */ -#define US_MAN_TX_PP (0x3 << 8) /**< \brief (US_MAN) Transmitter Preamble Pattern */ -#define US_MAN_TX_MPOL (0x1 << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ -#define US_MAN_RX_PL (0xf << 16) /**< \brief (US_MAN) Receiver Preamble Length */ -#define US_MAN_RX_PP (0x3 << 24) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ -#define US_MAN_RX_MPOL (0x1 << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ -#define US_MAN_STUCKTO1 (0x1 << 29) /**< \brief (US_MAN) */ -#define US_MAN_DRIFT (0x1 << 30) /**< \brief (US_MAN) Drift compensation */ -/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */ -#define US_WPMR_WPEN (0x1 << 0) /**< \brief (US_WPMR) Write Protect Enable */ -#define US_WPMR_WPKEY (0xffffff << 8) /**< \brief (US_WPMR) Write Protect KEY */ -/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */ -#define US_WPSR_WPVS (0x1 << 0) /**< \brief (US_WPSR) Write Protect Violation Status */ -#define US_WPSR_WPVSRC (0xffff << 8) /**< \brief (US_WPSR) Write Protect Violation Source */ -/* -------- US_VERSION : (USART Offset: 0xFC) Version Register -------- */ -#define US_VERSION_VERSION (0xfff << 0) /**< \brief (US_VERSION) */ -#define US_VERSION_MFN (0x7 << 16) /**< \brief (US_VERSION) */ -/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */ -#define US_RPR_RXPTR (0xffffffff << 0) /**< \brief (US_RPR) Receive Pointer Register */ -/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */ -#define US_RCR_RXCTR (0xffff << 0) /**< \brief (US_RCR) Receive Counter Register */ -/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */ -#define US_TPR_TXPTR (0xffffffff << 0) /**< \brief (US_TPR) Transmit Counter Register */ -/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */ -#define US_TCR_TXCTR (0xffff << 0) /**< \brief (US_TCR) Transmit Counter Register */ -/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */ -#define US_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (US_RNPR) Receive Next Pointer */ -/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */ -#define US_RNCR_RXNCTR (0xffff << 0) /**< \brief (US_RNCR) Receive Next Counter */ -/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */ -#define US_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (US_TNPR) Transmit Next Pointer */ -/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */ -#define US_TNCR_TXNCTR (0xffff << 0) /**< \brief (US_TNCR) Transmit Counter Next */ -/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */ -#define US_PTCR_RXTEN (0x1 << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */ -#define US_PTCR_RXTDIS (0x1 << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */ -#define US_PTCR_TXTEN (0x1 << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */ -#define US_PTCR_TXTDIS (0x1 << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */ -/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */ -#define US_PTSR_RXTEN (0x1 << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */ -#define US_PTSR_TXTEN (0x1 << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Watchdog Timer */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_WDT Watchdog Timer */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Wdt hardware registers */ -typedef struct { - WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ - RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ - RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ -} Wdt; -#endif /* __ASSEMBLY__ */ -/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ -#define WDT_CR_WDRSTT (0x1 << 0) /**< \brief (WDT_CR) Watchdog Restart */ -#define WDT_CR_KEY (0xff << 24) /**< \brief (WDT_CR) Password */ -/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ -#define WDT_MR_WDV (0xfff << 0) /**< \brief (WDT_MR) Watchdog Counter Value */ -#define WDT_MR_WDFIEN (0x1 << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ -#define WDT_MR_WDRSTEN (0x1 << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ -#define WDT_MR_WDRPROC (0x1 << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */ -#define WDT_MR_WDDIS (0x1 << 15) /**< \brief (WDT_MR) Watchdog Disable */ -#define WDT_MR_WDD (0xfff << 16) /**< \brief (WDT_MR) Watchdog Delta Value */ -#define WDT_MR_WDDBGHLT (0x1 << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ -#define WDT_MR_WDIDLEHLT (0x1 << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ -/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ -#define WDT_SR_WDUNF (0x1 << 0) /**< \brief (WDT_SR) Watchdog Underflow */ -#define WDT_SR_WDERR (0x1 << 1) /**< \brief (WDT_SR) Watchdog Error */ - -/*@}*/ - -/*@}*/ - -/* ***************************************************************************** */ -/* REGISTER ACCESS DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_reg Registers Access Definitions */ -/*@{*/ - -/* ========== Register definition for HSMCI peripheral ========== */ -#define REG_HSMCI_CR REG_ACCESS(WoReg, 0x40000000U) /**< \brief (HSMCI) Control Register */ -#define REG_HSMCI_MR REG_ACCESS(RwReg, 0x40000004U) /**< \brief (HSMCI) Mode Register */ -#define REG_HSMCI_DTOR REG_ACCESS(RwReg, 0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ -#define REG_HSMCI_SDCR REG_ACCESS(RwReg, 0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ -#define REG_HSMCI_ARGR REG_ACCESS(RwReg, 0x40000010U) /**< \brief (HSMCI) Argument Register */ -#define REG_HSMCI_CMDR REG_ACCESS(WoReg, 0x40000014U) /**< \brief (HSMCI) Command Register */ -#define REG_HSMCI_BLKR REG_ACCESS(RwReg, 0x40000018U) /**< \brief (HSMCI) Block Register */ -#define REG_HSMCI_CSTOR REG_ACCESS(RwReg, 0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ -#define REG_HSMCI_RSPR REG_ACCESS(RoReg, 0x40000020U) /**< \brief (HSMCI) Response Register */ -#define REG_HSMCI_RDR REG_ACCESS(RoReg, 0x40000030U) /**< \brief (HSMCI) Receive Data Register */ -#define REG_HSMCI_TDR REG_ACCESS(WoReg, 0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ -#define REG_HSMCI_SR REG_ACCESS(RoReg, 0x40000040U) /**< \brief (HSMCI) Status Register */ -#define REG_HSMCI_IER REG_ACCESS(WoReg, 0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ -#define REG_HSMCI_IDR REG_ACCESS(WoReg, 0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ -#define REG_HSMCI_IMR REG_ACCESS(RoReg, 0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ -#define REG_HSMCI_CFG REG_ACCESS(RwReg, 0x40000054U) /**< \brief (HSMCI) Configuration Register */ -#define REG_HSMCI_WPMR REG_ACCESS(RwReg, 0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ -#define REG_HSMCI_WPSR REG_ACCESS(RoReg, 0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ -#define REG_HSMCI_RPR REG_ACCESS(RwReg, 0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */ -#define REG_HSMCI_RCR REG_ACCESS(RwReg, 0x40000104U) /**< \brief (HSMCI) Receive Counter Register */ -#define REG_HSMCI_TPR REG_ACCESS(RwReg, 0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */ -#define REG_HSMCI_TCR REG_ACCESS(RwReg, 0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */ -#define REG_HSMCI_RNPR REG_ACCESS(RwReg, 0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */ -#define REG_HSMCI_RNCR REG_ACCESS(RwReg, 0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */ -#define REG_HSMCI_TNPR REG_ACCESS(RwReg, 0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */ -#define REG_HSMCI_TNCR REG_ACCESS(RwReg, 0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */ -#define REG_HSMCI_PTCR REG_ACCESS(WoReg, 0x40000120U) /**< \brief (HSMCI) Transfer Control Register */ -#define REG_HSMCI_PTSR REG_ACCESS(RoReg, 0x40000124U) /**< \brief (HSMCI) Transfer Status Register */ -/* ========== Register definition for SSC peripheral ========== */ -#define REG_SSC_CR REG_ACCESS(WoReg, 0x40004000U) /**< \brief (SSC) Control Register */ -#define REG_SSC_CMR REG_ACCESS(RwReg, 0x40004004U) /**< \brief (SSC) Clock Mode Register */ -#define REG_SSC_RCMR REG_ACCESS(RwReg, 0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ -#define REG_SSC_RFMR REG_ACCESS(RwReg, 0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ -#define REG_SSC_TCMR REG_ACCESS(RwReg, 0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ -#define REG_SSC_TFMR REG_ACCESS(RwReg, 0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ -#define REG_SSC_RHR REG_ACCESS(RoReg, 0x40004020U) /**< \brief (SSC) Receive Holding Register */ -#define REG_SSC_THR REG_ACCESS(WoReg, 0x40004024U) /**< \brief (SSC) Transmit Holding Register */ -#define REG_SSC_RSHR REG_ACCESS(RoReg, 0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ -#define REG_SSC_TSHR REG_ACCESS(RwReg, 0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ -#define REG_SSC_RC0R REG_ACCESS(RwReg, 0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ -#define REG_SSC_RC1R REG_ACCESS(RwReg, 0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ -#define REG_SSC_SR REG_ACCESS(RoReg, 0x40004040U) /**< \brief (SSC) Status Register */ -#define REG_SSC_IER REG_ACCESS(WoReg, 0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ -#define REG_SSC_IDR REG_ACCESS(WoReg, 0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ -#define REG_SSC_IMR REG_ACCESS(RoReg, 0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ -#define REG_SSC_WPMR REG_ACCESS(RwReg, 0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */ -#define REG_SSC_WPSR REG_ACCESS(RoReg, 0x400040E8U) /**< \brief (SSC) Write Protect Status Register */ -#define REG_SSC_RPR REG_ACCESS(RwReg, 0x40004100U) /**< \brief (SSC) Receive Pointer Register */ -#define REG_SSC_RCR REG_ACCESS(RwReg, 0x40004104U) /**< \brief (SSC) Receive Counter Register */ -#define REG_SSC_TPR REG_ACCESS(RwReg, 0x40004108U) /**< \brief (SSC) Transmit Pointer Register */ -#define REG_SSC_TCR REG_ACCESS(RwReg, 0x4000410CU) /**< \brief (SSC) Transmit Counter Register */ -#define REG_SSC_RNPR REG_ACCESS(RwReg, 0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */ -#define REG_SSC_RNCR REG_ACCESS(RwReg, 0x40004114U) /**< \brief (SSC) Receive Next Counter Register */ -#define REG_SSC_TNPR REG_ACCESS(RwReg, 0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */ -#define REG_SSC_TNCR REG_ACCESS(RwReg, 0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */ -#define REG_SSC_PTCR REG_ACCESS(WoReg, 0x40004120U) /**< \brief (SSC) Transfer Control Register */ -#define REG_SSC_PTSR REG_ACCESS(RoReg, 0x40004124U) /**< \brief (SSC) Transfer Status Register */ -/* ========== Register definition for SPI peripheral ========== */ -#define REG_SPI_CR REG_ACCESS(WoReg, 0x40008000U) /**< \brief (SPI) Control Register */ -#define REG_SPI_MR REG_ACCESS(RwReg, 0x40008004U) /**< \brief (SPI) Mode Register */ -#define REG_SPI_RDR REG_ACCESS(RoReg, 0x40008008U) /**< \brief (SPI) Receive Data Register */ -#define REG_SPI_TDR REG_ACCESS(WoReg, 0x4000800CU) /**< \brief (SPI) Transmit Data Register */ -#define REG_SPI_SR REG_ACCESS(RoReg, 0x40008010U) /**< \brief (SPI) Status Register */ -#define REG_SPI_IER REG_ACCESS(WoReg, 0x40008014U) /**< \brief (SPI) Interrupt Enable Register */ -#define REG_SPI_IDR REG_ACCESS(WoReg, 0x40008018U) /**< \brief (SPI) Interrupt Disable Register */ -#define REG_SPI_IMR REG_ACCESS(RoReg, 0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */ -#define REG_SPI_CSR REG_ACCESS(RwReg, 0x40008030U) /**< \brief (SPI) Chip Select Register */ -#define REG_SPI_WPMR REG_ACCESS(RwReg, 0x400080E4U) /**< \brief (SPI) Write Protection Control Register */ -#define REG_SPI_WPSR REG_ACCESS(RoReg, 0x400080E8U) /**< \brief (SPI) Write Protection Status Register */ -#define REG_SPI_RPR REG_ACCESS(RwReg, 0x40008100U) /**< \brief (SPI) Receive Pointer Register */ -#define REG_SPI_RCR REG_ACCESS(RwReg, 0x40008104U) /**< \brief (SPI) Receive Counter Register */ -#define REG_SPI_TPR REG_ACCESS(RwReg, 0x40008108U) /**< \brief (SPI) Transmit Pointer Register */ -#define REG_SPI_TCR REG_ACCESS(RwReg, 0x4000810CU) /**< \brief (SPI) Transmit Counter Register */ -#define REG_SPI_RNPR REG_ACCESS(RwReg, 0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */ -#define REG_SPI_RNCR REG_ACCESS(RwReg, 0x40008114U) /**< \brief (SPI) Receive Next Counter Register */ -#define REG_SPI_TNPR REG_ACCESS(RwReg, 0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */ -#define REG_SPI_TNCR REG_ACCESS(RwReg, 0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */ -#define REG_SPI_PTCR REG_ACCESS(WoReg, 0x40008120U) /**< \brief (SPI) Transfer Control Register */ -#define REG_SPI_PTSR REG_ACCESS(RoReg, 0x40008124U) /**< \brief (SPI) Transfer Status Register */ -/* ========== Register definition for TC0 peripheral ========== */ -#define REG_TC0_CCR0 REG_ACCESS(WoReg, 0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ -#define REG_TC0_CMR0 REG_ACCESS(RwReg, 0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ -#define REG_TC0_CV0 REG_ACCESS(RoReg, 0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */ -#define REG_TC0_RA0 REG_ACCESS(RwReg, 0x40010014U) /**< \brief (TC0) Register A (channel = 0) */ -#define REG_TC0_RB0 REG_ACCESS(RwReg, 0x40010018U) /**< \brief (TC0) Register B (channel = 0) */ -#define REG_TC0_RC0 REG_ACCESS(RwReg, 0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */ -#define REG_TC0_SR0 REG_ACCESS(RoReg, 0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */ -#define REG_TC0_IER0 REG_ACCESS(WoReg, 0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ -#define REG_TC0_IDR0 REG_ACCESS(WoReg, 0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ -#define REG_TC0_IMR0 REG_ACCESS(RoReg, 0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ -#define REG_TC0_CCR1 REG_ACCESS(WoReg, 0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ -#define REG_TC0_CMR1 REG_ACCESS(RwReg, 0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ -#define REG_TC0_CV1 REG_ACCESS(RoReg, 0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */ -#define REG_TC0_RA1 REG_ACCESS(RwReg, 0x40010054U) /**< \brief (TC0) Register A (channel = 1) */ -#define REG_TC0_RB1 REG_ACCESS(RwReg, 0x40010058U) /**< \brief (TC0) Register B (channel = 1) */ -#define REG_TC0_RC1 REG_ACCESS(RwReg, 0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */ -#define REG_TC0_SR1 REG_ACCESS(RoReg, 0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */ -#define REG_TC0_IER1 REG_ACCESS(WoReg, 0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ -#define REG_TC0_IDR1 REG_ACCESS(WoReg, 0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ -#define REG_TC0_IMR1 REG_ACCESS(RoReg, 0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ -#define REG_TC0_CCR2 REG_ACCESS(WoReg, 0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ -#define REG_TC0_CMR2 REG_ACCESS(RwReg, 0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ -#define REG_TC0_CV2 REG_ACCESS(RoReg, 0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */ -#define REG_TC0_RA2 REG_ACCESS(RwReg, 0x40010094U) /**< \brief (TC0) Register A (channel = 2) */ -#define REG_TC0_RB2 REG_ACCESS(RwReg, 0x40010098U) /**< \brief (TC0) Register B (channel = 2) */ -#define REG_TC0_RC2 REG_ACCESS(RwReg, 0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */ -#define REG_TC0_SR2 REG_ACCESS(RoReg, 0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */ -#define REG_TC0_IER2 REG_ACCESS(WoReg, 0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ -#define REG_TC0_IDR2 REG_ACCESS(WoReg, 0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ -#define REG_TC0_IMR2 REG_ACCESS(RoReg, 0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ -#define REG_TC0_BCR REG_ACCESS(WoReg, 0x400100C0U) /**< \brief (TC0) Block Control Register */ -#define REG_TC0_BMR REG_ACCESS(RwReg, 0x400100C4U) /**< \brief (TC0) Block Mode Register */ -#define REG_TC0_QIER REG_ACCESS(WoReg, 0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ -#define REG_TC0_QIDR REG_ACCESS(WoReg, 0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ -#define REG_TC0_QIMR REG_ACCESS(RoReg, 0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ -#define REG_TC0_QISR REG_ACCESS(RoReg, 0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ -#define REG_TC0_FMR REG_ACCESS(RwReg, 0x400100D8U) /**< \brief (TC0) Fault Mode Register */ -#define REG_TC0_WPMR REG_ACCESS(RwReg, 0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */ -#define REG_TC0_VER REG_ACCESS(RoReg, 0x400100FCU) /**< \brief (TC0) Version Register */ -/* ========== Register definition for TC1 peripheral ========== */ -#define REG_TC1_CCR0 REG_ACCESS(WoReg, 0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ -#define REG_TC1_CMR0 REG_ACCESS(RwReg, 0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ -#define REG_TC1_CV0 REG_ACCESS(RoReg, 0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */ -#define REG_TC1_RA0 REG_ACCESS(RwReg, 0x40014014U) /**< \brief (TC1) Register A (channel = 0) */ -#define REG_TC1_RB0 REG_ACCESS(RwReg, 0x40014018U) /**< \brief (TC1) Register B (channel = 0) */ -#define REG_TC1_RC0 REG_ACCESS(RwReg, 0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */ -#define REG_TC1_SR0 REG_ACCESS(RoReg, 0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */ -#define REG_TC1_IER0 REG_ACCESS(WoReg, 0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ -#define REG_TC1_IDR0 REG_ACCESS(WoReg, 0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ -#define REG_TC1_IMR0 REG_ACCESS(RoReg, 0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ -#define REG_TC1_CCR1 REG_ACCESS(WoReg, 0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ -#define REG_TC1_CMR1 REG_ACCESS(RwReg, 0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ -#define REG_TC1_CV1 REG_ACCESS(RoReg, 0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */ -#define REG_TC1_RA1 REG_ACCESS(RwReg, 0x40014054U) /**< \brief (TC1) Register A (channel = 1) */ -#define REG_TC1_RB1 REG_ACCESS(RwReg, 0x40014058U) /**< \brief (TC1) Register B (channel = 1) */ -#define REG_TC1_RC1 REG_ACCESS(RwReg, 0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */ -#define REG_TC1_SR1 REG_ACCESS(RoReg, 0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */ -#define REG_TC1_IER1 REG_ACCESS(WoReg, 0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ -#define REG_TC1_IDR1 REG_ACCESS(WoReg, 0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ -#define REG_TC1_IMR1 REG_ACCESS(RoReg, 0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ -#define REG_TC1_CCR2 REG_ACCESS(WoReg, 0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ -#define REG_TC1_CMR2 REG_ACCESS(RwReg, 0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ -#define REG_TC1_CV2 REG_ACCESS(RoReg, 0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */ -#define REG_TC1_RA2 REG_ACCESS(RwReg, 0x40014094U) /**< \brief (TC1) Register A (channel = 2) */ -#define REG_TC1_RB2 REG_ACCESS(RwReg, 0x40014098U) /**< \brief (TC1) Register B (channel = 2) */ -#define REG_TC1_RC2 REG_ACCESS(RwReg, 0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */ -#define REG_TC1_SR2 REG_ACCESS(RoReg, 0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */ -#define REG_TC1_IER2 REG_ACCESS(WoReg, 0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ -#define REG_TC1_IDR2 REG_ACCESS(WoReg, 0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ -#define REG_TC1_IMR2 REG_ACCESS(RoReg, 0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ -#define REG_TC1_BCR REG_ACCESS(WoReg, 0x400140C0U) /**< \brief (TC1) Block Control Register */ -#define REG_TC1_BMR REG_ACCESS(RwReg, 0x400140C4U) /**< \brief (TC1) Block Mode Register */ -#define REG_TC1_QIER REG_ACCESS(WoReg, 0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ -#define REG_TC1_QIDR REG_ACCESS(WoReg, 0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ -#define REG_TC1_QIMR REG_ACCESS(RoReg, 0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ -#define REG_TC1_QISR REG_ACCESS(RoReg, 0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ -#define REG_TC1_FMR REG_ACCESS(RwReg, 0x400140D8U) /**< \brief (TC1) Fault Mode Register */ -#define REG_TC1_WPMR REG_ACCESS(RwReg, 0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */ -#define REG_TC1_VER REG_ACCESS(RoReg, 0x400140FCU) /**< \brief (TC1) Version Register */ -/* ========== Register definition for TWI0 peripheral ========== */ -#define REG_TWI0_CR REG_ACCESS(WoReg, 0x40018000U) /**< \brief (TWI0) Control Register */ -#define REG_TWI0_MMR REG_ACCESS(RwReg, 0x40018004U) /**< \brief (TWI0) Master Mode Register */ -#define REG_TWI0_SMR REG_ACCESS(RwReg, 0x40018008U) /**< \brief (TWI0) Slave Mode Register */ -#define REG_TWI0_IADR REG_ACCESS(RwReg, 0x4001800CU) /**< \brief (TWI0) Internal Address Register */ -#define REG_TWI0_CWGR REG_ACCESS(RwReg, 0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */ -#define REG_TWI0_SR REG_ACCESS(RoReg, 0x40018020U) /**< \brief (TWI0) Status Register */ -#define REG_TWI0_IER REG_ACCESS(WoReg, 0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */ -#define REG_TWI0_IDR REG_ACCESS(WoReg, 0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */ -#define REG_TWI0_IMR REG_ACCESS(RoReg, 0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */ -#define REG_TWI0_RHR REG_ACCESS(RoReg, 0x40018030U) /**< \brief (TWI0) Receive Holding Register */ -#define REG_TWI0_THR REG_ACCESS(WoReg, 0x40018034U) /**< \brief (TWI0) Transmit Holding Register */ -#define REG_TWI0_RPR REG_ACCESS(RwReg, 0x40018100U) /**< \brief (TWI0) Receive Pointer Register */ -#define REG_TWI0_RCR REG_ACCESS(RwReg, 0x40018104U) /**< \brief (TWI0) Receive Counter Register */ -#define REG_TWI0_TPR REG_ACCESS(RwReg, 0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */ -#define REG_TWI0_TCR REG_ACCESS(RwReg, 0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */ -#define REG_TWI0_RNPR REG_ACCESS(RwReg, 0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */ -#define REG_TWI0_RNCR REG_ACCESS(RwReg, 0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */ -#define REG_TWI0_TNPR REG_ACCESS(RwReg, 0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */ -#define REG_TWI0_TNCR REG_ACCESS(RwReg, 0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */ -#define REG_TWI0_PTCR REG_ACCESS(WoReg, 0x40018120U) /**< \brief (TWI0) Transfer Control Register */ -#define REG_TWI0_PTSR REG_ACCESS(RoReg, 0x40018124U) /**< \brief (TWI0) Transfer Status Register */ -/* ========== Register definition for TWI1 peripheral ========== */ -#define REG_TWI1_CR REG_ACCESS(WoReg, 0x4001C000U) /**< \brief (TWI1) Control Register */ -#define REG_TWI1_MMR REG_ACCESS(RwReg, 0x4001C004U) /**< \brief (TWI1) Master Mode Register */ -#define REG_TWI1_SMR REG_ACCESS(RwReg, 0x4001C008U) /**< \brief (TWI1) Slave Mode Register */ -#define REG_TWI1_IADR REG_ACCESS(RwReg, 0x4001C00CU) /**< \brief (TWI1) Internal Address Register */ -#define REG_TWI1_CWGR REG_ACCESS(RwReg, 0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */ -#define REG_TWI1_SR REG_ACCESS(RoReg, 0x4001C020U) /**< \brief (TWI1) Status Register */ -#define REG_TWI1_IER REG_ACCESS(WoReg, 0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */ -#define REG_TWI1_IDR REG_ACCESS(WoReg, 0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */ -#define REG_TWI1_IMR REG_ACCESS(RoReg, 0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */ -#define REG_TWI1_RHR REG_ACCESS(RoReg, 0x4001C030U) /**< \brief (TWI1) Receive Holding Register */ -#define REG_TWI1_THR REG_ACCESS(WoReg, 0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */ -#define REG_TWI1_RPR REG_ACCESS(RwReg, 0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */ -#define REG_TWI1_RCR REG_ACCESS(RwReg, 0x4001C104U) /**< \brief (TWI1) Receive Counter Register */ -#define REG_TWI1_TPR REG_ACCESS(RwReg, 0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */ -#define REG_TWI1_TCR REG_ACCESS(RwReg, 0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */ -#define REG_TWI1_RNPR REG_ACCESS(RwReg, 0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */ -#define REG_TWI1_RNCR REG_ACCESS(RwReg, 0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */ -#define REG_TWI1_TNPR REG_ACCESS(RwReg, 0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */ -#define REG_TWI1_TNCR REG_ACCESS(RwReg, 0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */ -#define REG_TWI1_PTCR REG_ACCESS(WoReg, 0x4001C120U) /**< \brief (TWI1) Transfer Control Register */ -#define REG_TWI1_PTSR REG_ACCESS(RoReg, 0x4001C124U) /**< \brief (TWI1) Transfer Status Register */ -/* ========== Register definition for PWM peripheral ========== */ -#define REG_PWM_CLK REG_ACCESS(RwReg, 0x40020000U) /**< \brief (PWM) PWM Clock Register */ -#define REG_PWM_ENA REG_ACCESS(WoReg, 0x40020004U) /**< \brief (PWM) PWM Enable Register */ -#define REG_PWM_DIS REG_ACCESS(WoReg, 0x40020008U) /**< \brief (PWM) PWM Disable Register */ -#define REG_PWM_SR REG_ACCESS(RoReg, 0x4002000CU) /**< \brief (PWM) PWM Status Register */ -#define REG_PWM_IER1 REG_ACCESS(WoReg, 0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ -#define REG_PWM_IDR1 REG_ACCESS(WoReg, 0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ -#define REG_PWM_IMR1 REG_ACCESS(RoReg, 0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ -#define REG_PWM_ISR1 REG_ACCESS(RoReg, 0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ -#define REG_PWM_SCM REG_ACCESS(RwReg, 0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ -#define REG_PWM_SCUC REG_ACCESS(RwReg, 0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ -#define REG_PWM_SCUP REG_ACCESS(RwReg, 0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ -#define REG_PWM_SCUPUPD REG_ACCESS(WoReg, 0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ -#define REG_PWM_IER2 REG_ACCESS(WoReg, 0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ -#define REG_PWM_IDR2 REG_ACCESS(WoReg, 0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ -#define REG_PWM_IMR2 REG_ACCESS(RoReg, 0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ -#define REG_PWM_ISR2 REG_ACCESS(RoReg, 0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ -#define REG_PWM_OOV REG_ACCESS(RwReg, 0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */ -#define REG_PWM_OS REG_ACCESS(RwReg, 0x40020048U) /**< \brief (PWM) PWM Output Selection Register */ -#define REG_PWM_OSS REG_ACCESS(WoReg, 0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */ -#define REG_PWM_OSC REG_ACCESS(WoReg, 0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */ -#define REG_PWM_OSSUPD REG_ACCESS(WoReg, 0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ -#define REG_PWM_OSCUPD REG_ACCESS(WoReg, 0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ -#define REG_PWM_FMR REG_ACCESS(RwReg, 0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */ -#define REG_PWM_FSR REG_ACCESS(RoReg, 0x40020060U) /**< \brief (PWM) PWM Fault Status Register */ -#define REG_PWM_FCR REG_ACCESS(WoReg, 0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */ -#define REG_PWM_FPV REG_ACCESS(RwReg, 0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */ -#define REG_PWM_FPE REG_ACCESS(RwReg, 0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ -#define REG_PWM_ELxMR REG_ACCESS(RwReg, 0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ -#define REG_PWM_SMMR REG_ACCESS(RwReg, 0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */ -#define REG_PWM_WPCR REG_ACCESS(WoReg, 0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */ -#define REG_PWM_WPSR REG_ACCESS(RoReg, 0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */ -#define REG_PWM_RPR REG_ACCESS(RwReg, 0x40020100U) /**< \brief (PWM) Receive Pointer Register */ -#define REG_PWM_RCR REG_ACCESS(RwReg, 0x40020104U) /**< \brief (PWM) Receive Counter Register */ -#define REG_PWM_TPR REG_ACCESS(RwReg, 0x40020108U) /**< \brief (PWM) Transmit Pointer Register */ -#define REG_PWM_TCR REG_ACCESS(RwReg, 0x4002010CU) /**< \brief (PWM) Transmit Counter Register */ -#define REG_PWM_RNPR REG_ACCESS(RwReg, 0x40020110U) /**< \brief (PWM) Receive Next Pointer Register */ -#define REG_PWM_RNCR REG_ACCESS(RwReg, 0x40020114U) /**< \brief (PWM) Receive Next Counter Register */ -#define REG_PWM_TNPR REG_ACCESS(RwReg, 0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */ -#define REG_PWM_TNCR REG_ACCESS(RwReg, 0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */ -#define REG_PWM_PTCR REG_ACCESS(WoReg, 0x40020120U) /**< \brief (PWM) Transfer Control Register */ -#define REG_PWM_PTSR REG_ACCESS(RoReg, 0x40020124U) /**< \brief (PWM) Transfer Status Register */ -#define REG_PWM_CMP0V REG_ACCESS(RwReg, 0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ -#define REG_PWM_CMP0VUPD REG_ACCESS(WoReg, 0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ -#define REG_PWM_CMP0M REG_ACCESS(RwReg, 0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ -#define REG_PWM_CMP0MUPD REG_ACCESS(WoReg, 0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ -#define REG_PWM_CMP1V REG_ACCESS(RwReg, 0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ -#define REG_PWM_CMP1VUPD REG_ACCESS(WoReg, 0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ -#define REG_PWM_CMP1M REG_ACCESS(RwReg, 0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ -#define REG_PWM_CMP1MUPD REG_ACCESS(WoReg, 0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ -#define REG_PWM_CMP2V REG_ACCESS(RwReg, 0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ -#define REG_PWM_CMP2VUPD REG_ACCESS(WoReg, 0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ -#define REG_PWM_CMP2M REG_ACCESS(RwReg, 0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ -#define REG_PWM_CMP2MUPD REG_ACCESS(WoReg, 0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ -#define REG_PWM_CMP3V REG_ACCESS(RwReg, 0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ -#define REG_PWM_CMP3VUPD REG_ACCESS(WoReg, 0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ -#define REG_PWM_CMP3M REG_ACCESS(RwReg, 0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ -#define REG_PWM_CMP3MUPD REG_ACCESS(WoReg, 0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ -#define REG_PWM_CMP4V REG_ACCESS(RwReg, 0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ -#define REG_PWM_CMP4VUPD REG_ACCESS(WoReg, 0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ -#define REG_PWM_CMP4M REG_ACCESS(RwReg, 0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ -#define REG_PWM_CMP4MUPD REG_ACCESS(WoReg, 0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ -#define REG_PWM_CMP5V REG_ACCESS(RwReg, 0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ -#define REG_PWM_CMP5VUPD REG_ACCESS(WoReg, 0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ -#define REG_PWM_CMP5M REG_ACCESS(RwReg, 0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ -#define REG_PWM_CMP5MUPD REG_ACCESS(WoReg, 0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ -#define REG_PWM_CMP6V REG_ACCESS(RwReg, 0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ -#define REG_PWM_CMP6VUPD REG_ACCESS(WoReg, 0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ -#define REG_PWM_CMP6M REG_ACCESS(RwReg, 0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ -#define REG_PWM_CMP6MUPD REG_ACCESS(WoReg, 0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ -#define REG_PWM_CMP7V REG_ACCESS(RwReg, 0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ -#define REG_PWM_CMP7VUPD REG_ACCESS(WoReg, 0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ -#define REG_PWM_CMP7M REG_ACCESS(RwReg, 0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ -#define REG_PWM_CMP7MUPD REG_ACCESS(WoReg, 0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ -#define REG_PWM_CMR0 REG_ACCESS(RwReg, 0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ -#define REG_PWM_CDTY0 REG_ACCESS(RwReg, 0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ -#define REG_PWM_CDTYUPD0 REG_ACCESS(WoReg, 0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ -#define REG_PWM_CPRD0 REG_ACCESS(RwReg, 0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ -#define REG_PWM_CPRDUPD0 REG_ACCESS(WoReg, 0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ -#define REG_PWM_CCNT0 REG_ACCESS(RoReg, 0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ -#define REG_PWM_DT0 REG_ACCESS(RwReg, 0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ -#define REG_PWM_DTUPD0 REG_ACCESS(WoReg, 0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ -#define REG_PWM_CMR1 REG_ACCESS(RwReg, 0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ -#define REG_PWM_CDTY1 REG_ACCESS(RwReg, 0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ -#define REG_PWM_CDTYUPD1 REG_ACCESS(WoReg, 0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ -#define REG_PWM_CPRD1 REG_ACCESS(RwReg, 0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ -#define REG_PWM_CPRDUPD1 REG_ACCESS(WoReg, 0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ -#define REG_PWM_CCNT1 REG_ACCESS(RoReg, 0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ -#define REG_PWM_DT1 REG_ACCESS(RwReg, 0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ -#define REG_PWM_DTUPD1 REG_ACCESS(WoReg, 0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ -#define REG_PWM_CMR2 REG_ACCESS(RwReg, 0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ -#define REG_PWM_CDTY2 REG_ACCESS(RwReg, 0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ -#define REG_PWM_CDTYUPD2 REG_ACCESS(WoReg, 0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ -#define REG_PWM_CPRD2 REG_ACCESS(RwReg, 0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ -#define REG_PWM_CPRDUPD2 REG_ACCESS(WoReg, 0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ -#define REG_PWM_CCNT2 REG_ACCESS(RoReg, 0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ -#define REG_PWM_DT2 REG_ACCESS(RwReg, 0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ -#define REG_PWM_DTUPD2 REG_ACCESS(WoReg, 0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ -#define REG_PWM_CMR3 REG_ACCESS(RwReg, 0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ -#define REG_PWM_CDTY3 REG_ACCESS(RwReg, 0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ -#define REG_PWM_CDTYUPD3 REG_ACCESS(WoReg, 0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ -#define REG_PWM_CPRD3 REG_ACCESS(RwReg, 0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ -#define REG_PWM_CPRDUPD3 REG_ACCESS(WoReg, 0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ -#define REG_PWM_CCNT3 REG_ACCESS(RoReg, 0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ -#define REG_PWM_DT3 REG_ACCESS(RwReg, 0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ -#define REG_PWM_DTUPD3 REG_ACCESS(WoReg, 0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ -/* ========== Register definition for USART0 peripheral ========== */ -#define REG_USART0_CR REG_ACCESS(WoReg, 0x40024000U) /**< \brief (USART0) Control Register */ -#define REG_USART0_MR REG_ACCESS(RwReg, 0x40024004U) /**< \brief (USART0) Mode Register */ -#define REG_USART0_IER REG_ACCESS(WoReg, 0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ -#define REG_USART0_IDR REG_ACCESS(WoReg, 0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ -#define REG_USART0_IMR REG_ACCESS(RoReg, 0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ -#define REG_USART0_CSR REG_ACCESS(RoReg, 0x40024014U) /**< \brief (USART0) Channel Status Register */ -#define REG_USART0_RHR REG_ACCESS(RoReg, 0x40024018U) /**< \brief (USART0) Receiver Holding Register */ -#define REG_USART0_THR REG_ACCESS(WoReg, 0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */ -#define REG_USART0_BRGR REG_ACCESS(RwReg, 0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ -#define REG_USART0_RTOR REG_ACCESS(RwReg, 0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ -#define REG_USART0_TTGR REG_ACCESS(RwReg, 0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ -#define REG_USART0_FIDI REG_ACCESS(RwReg, 0x40024040U) /**< \brief (USART0) FI DI Ratio Register */ -#define REG_USART0_NER REG_ACCESS(RoReg, 0x40024044U) /**< \brief (USART0) Number of Errors Register */ -#define REG_USART0_IF REG_ACCESS(RwReg, 0x4002404CU) /**< \brief (USART0) IrDA Filter Register */ -#define REG_USART0_MAN REG_ACCESS(RwReg, 0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ -#define REG_USART0_WPMR REG_ACCESS(RwReg, 0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */ -#define REG_USART0_WPSR REG_ACCESS(RoReg, 0x400240E8U) /**< \brief (USART0) Write Protect Status Register */ -#define REG_USART0_VERSION REG_ACCESS(RoReg, 0x400240FCU) /**< \brief (USART0) Version Register */ -#define REG_USART0_RPR REG_ACCESS(RwReg, 0x40024100U) /**< \brief (USART0) Receive Pointer Register */ -#define REG_USART0_RCR REG_ACCESS(RwReg, 0x40024104U) /**< \brief (USART0) Receive Counter Register */ -#define REG_USART0_TPR REG_ACCESS(RwReg, 0x40024108U) /**< \brief (USART0) Transmit Pointer Register */ -#define REG_USART0_TCR REG_ACCESS(RwReg, 0x4002410CU) /**< \brief (USART0) Transmit Counter Register */ -#define REG_USART0_RNPR REG_ACCESS(RwReg, 0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */ -#define REG_USART0_RNCR REG_ACCESS(RwReg, 0x40024114U) /**< \brief (USART0) Receive Next Counter Register */ -#define REG_USART0_TNPR REG_ACCESS(RwReg, 0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */ -#define REG_USART0_TNCR REG_ACCESS(RwReg, 0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */ -#define REG_USART0_PTCR REG_ACCESS(WoReg, 0x40024120U) /**< \brief (USART0) Transfer Control Register */ -#define REG_USART0_PTSR REG_ACCESS(RoReg, 0x40024124U) /**< \brief (USART0) Transfer Status Register */ -/* ========== Register definition for USART1 peripheral ========== */ -#define REG_USART1_CR REG_ACCESS(WoReg, 0x40028000U) /**< \brief (USART1) Control Register */ -#define REG_USART1_MR REG_ACCESS(RwReg, 0x40028004U) /**< \brief (USART1) Mode Register */ -#define REG_USART1_IER REG_ACCESS(WoReg, 0x40028008U) /**< \brief (USART1) Interrupt Enable Register */ -#define REG_USART1_IDR REG_ACCESS(WoReg, 0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */ -#define REG_USART1_IMR REG_ACCESS(RoReg, 0x40028010U) /**< \brief (USART1) Interrupt Mask Register */ -#define REG_USART1_CSR REG_ACCESS(RoReg, 0x40028014U) /**< \brief (USART1) Channel Status Register */ -#define REG_USART1_RHR REG_ACCESS(RoReg, 0x40028018U) /**< \brief (USART1) Receiver Holding Register */ -#define REG_USART1_THR REG_ACCESS(WoReg, 0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */ -#define REG_USART1_BRGR REG_ACCESS(RwReg, 0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */ -#define REG_USART1_RTOR REG_ACCESS(RwReg, 0x40028024U) /**< \brief (USART1) Receiver Time-out Register */ -#define REG_USART1_TTGR REG_ACCESS(RwReg, 0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */ -#define REG_USART1_FIDI REG_ACCESS(RwReg, 0x40028040U) /**< \brief (USART1) FI DI Ratio Register */ -#define REG_USART1_NER REG_ACCESS(RoReg, 0x40028044U) /**< \brief (USART1) Number of Errors Register */ -#define REG_USART1_IF REG_ACCESS(RwReg, 0x4002804CU) /**< \brief (USART1) IrDA Filter Register */ -#define REG_USART1_MAN REG_ACCESS(RwReg, 0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ -#define REG_USART1_WPMR REG_ACCESS(RwReg, 0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */ -#define REG_USART1_WPSR REG_ACCESS(RoReg, 0x400280E8U) /**< \brief (USART1) Write Protect Status Register */ -#define REG_USART1_VERSION REG_ACCESS(RoReg, 0x400280FCU) /**< \brief (USART1) Version Register */ -#define REG_USART1_RPR REG_ACCESS(RwReg, 0x40028100U) /**< \brief (USART1) Receive Pointer Register */ -#define REG_USART1_RCR REG_ACCESS(RwReg, 0x40028104U) /**< \brief (USART1) Receive Counter Register */ -#define REG_USART1_TPR REG_ACCESS(RwReg, 0x40028108U) /**< \brief (USART1) Transmit Pointer Register */ -#define REG_USART1_TCR REG_ACCESS(RwReg, 0x4002810CU) /**< \brief (USART1) Transmit Counter Register */ -#define REG_USART1_RNPR REG_ACCESS(RwReg, 0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */ -#define REG_USART1_RNCR REG_ACCESS(RwReg, 0x40028114U) /**< \brief (USART1) Receive Next Counter Register */ -#define REG_USART1_TNPR REG_ACCESS(RwReg, 0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */ -#define REG_USART1_TNCR REG_ACCESS(RwReg, 0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */ -#define REG_USART1_PTCR REG_ACCESS(WoReg, 0x40028120U) /**< \brief (USART1) Transfer Control Register */ -#define REG_USART1_PTSR REG_ACCESS(RoReg, 0x40028124U) /**< \brief (USART1) Transfer Status Register */ -/* ========== Register definition for UDP peripheral ========== */ -#define REG_UDP_FRM_NUM REG_ACCESS(RoReg, 0x40034000U) /**< \brief (UDP) Frame Number Register */ -#define REG_UDP_GLB_STAT REG_ACCESS(RwReg, 0x40034004U) /**< \brief (UDP) Global State Register */ -#define REG_UDP_FADDR REG_ACCESS(RwReg, 0x40034008U) /**< \brief (UDP) Function Address Register */ -#define REG_UDP_IER REG_ACCESS(WoReg, 0x40034010U) /**< \brief (UDP) Interrupt Enable Register */ -#define REG_UDP_IDR REG_ACCESS(WoReg, 0x40034014U) /**< \brief (UDP) Interrupt Disable Register */ -#define REG_UDP_IMR REG_ACCESS(RoReg, 0x40034018U) /**< \brief (UDP) Interrupt Mask Register */ -#define REG_UDP_ISR REG_ACCESS(RoReg, 0x4003401CU) /**< \brief (UDP) Interrupt Status Register */ -#define REG_UDP_ICR REG_ACCESS(WoReg, 0x40034020U) /**< \brief (UDP) Interrupt Clear Register */ -#define REG_UDP_RST_EP REG_ACCESS(RwReg, 0x40034028U) /**< \brief (UDP) Reset Endpoint Register */ -#define REG_UDP_CSR REG_ACCESS(RwReg, 0x4003402CU) /**< \brief (UDP) Endpoint Control and Status Register (ept_num = 0) */ -#define REG_UDP_FDR REG_ACCESS(RwReg, 0x4003404CU) /**< \brief (UDP) Endpoint FIFO Data Register (ept_num = 0) */ -#define REG_UDP_TXVC REG_ACCESS(RwReg, 0x40034074U) /**< \brief (UDP) Transceiver Control Register */ -/* ========== Register definition for ADC peripheral ========== */ -#define REG_ADC_CR REG_ACCESS(WoReg, 0x40038000U) /**< \brief (ADC) Control Register */ -#define REG_ADC_MR REG_ACCESS(RwReg, 0x40038004U) /**< \brief (ADC) Mode Register */ -#define REG_ADC_SEQ1R REG_ACCESS(RwReg, 0x40038008U) /**< \brief (ADC) Channel Sequence 1Register */ -#define REG_ADC_SEQ2R REG_ACCESS(RwReg, 0x4003800CU) /**< \brief (ADC) Channel Sequence 2 Register */ -#define REG_ADC_CHER REG_ACCESS(WoReg, 0x40038010U) /**< \brief (ADC) Channel Enable Register */ -#define REG_ADC_CHDR REG_ACCESS(WoReg, 0x40038014U) /**< \brief (ADC) Channel Disable Register */ -#define REG_ADC_CHSR REG_ACCESS(RoReg, 0x40038018U) /**< \brief (ADC) Channel Status Register */ -#define REG_ADC_LCDR REG_ACCESS(RoReg, 0x40038020U) /**< \brief (ADC) Last Converted Data Register */ -#define REG_ADC_IER REG_ACCESS(WoReg, 0x40038024U) /**< \brief (ADC) Interrupt Enable Register */ -#define REG_ADC_IDR REG_ACCESS(WoReg, 0x40038028U) /**< \brief (ADC) Interrupt Disable Register */ -#define REG_ADC_IMR REG_ACCESS(RoReg, 0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */ -#define REG_ADC_ISR REG_ACCESS(RoReg, 0x40038030U) /**< \brief (ADC) Interrupt Status Register */ -#define REG_ADC_OVER REG_ACCESS(RoReg, 0x4003803CU) /**< \brief (ADC) Overrun Status Register */ -#define REG_ADC_EMR REG_ACCESS(RwReg, 0x40038040U) /**< \brief (ADC) Extended Mode Register */ -#define REG_ADC_CWR REG_ACCESS(RwReg, 0x40038044U) /**< \brief (ADC) Compare Window Register */ -#define REG_ADC_CGR REG_ACCESS(RwReg, 0x40038048U) /**< \brief (ADC) Channel Gain Register */ -#define REG_ADC_COR REG_ACCESS(RwReg, 0x4003804CU) /**< \brief (ADC) Channel Offset Register */ -#define REG_ADC_CDR0 REG_ACCESS(RoReg, 0x40038050U) /**< \brief (ADC) Channel Data Register 0 */ -#define REG_ADC_CDR1 REG_ACCESS(RoReg, 0x40038054U) /**< \brief (ADC) Channel Data Register 1 */ -#define REG_ADC_CDR2 REG_ACCESS(RoReg, 0x40038058U) /**< \brief (ADC) Channel Data Register 2 */ -#define REG_ADC_CDR3 REG_ACCESS(RoReg, 0x4003805CU) /**< \brief (ADC) Channel Data Register 3 */ -#define REG_ADC_CDR4 REG_ACCESS(RoReg, 0x40038060U) /**< \brief (ADC) Channel Data Register 4 */ -#define REG_ADC_CDR5 REG_ACCESS(RoReg, 0x40038064U) /**< \brief (ADC) Channel Data Register 5 */ -#define REG_ADC_CDR6 REG_ACCESS(RoReg, 0x40038068U) /**< \brief (ADC) Channel Data Register 6 */ -#define REG_ADC_CDR15 REG_ACCESS(RoReg, 0x4003806CU) /**< \brief (ADC) Channel Data Register 15 */ -#define REG_ADC_ACR REG_ACCESS(RwReg, 0x40038094U) /**< \brief (ADC) Analog Control Register */ -#define REG_ADC_WPMR REG_ACCESS(RwReg, 0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */ -#define REG_ADC_WPSR REG_ACCESS(RoReg, 0x400380E8U) /**< \brief (ADC) Write Protect Status Register */ -#define REG_ADC_RPR REG_ACCESS(RwReg, 0x40038100U) /**< \brief (ADC) Receive Pointer Register */ -#define REG_ADC_RCR REG_ACCESS(RwReg, 0x40038104U) /**< \brief (ADC) Receive Counter Register */ -#define REG_ADC_TPR REG_ACCESS(RwReg, 0x40038108U) /**< \brief (ADC) Transmit Pointer Register */ -#define REG_ADC_TCR REG_ACCESS(RwReg, 0x4003810CU) /**< \brief (ADC) Transmit Counter Register */ -#define REG_ADC_RNPR REG_ACCESS(RwReg, 0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */ -#define REG_ADC_RNCR REG_ACCESS(RwReg, 0x40038114U) /**< \brief (ADC) Receive Next Counter Register */ -#define REG_ADC_TNPR REG_ACCESS(RwReg, 0x40038118U) /**< \brief (ADC) Transmit Next Pointer Register */ -#define REG_ADC_TNCR REG_ACCESS(RwReg, 0x4003811CU) /**< \brief (ADC) Transmit Next Counter Register */ -#define REG_ADC_PTCR REG_ACCESS(WoReg, 0x40038120U) /**< \brief (ADC) Transfer Control Register */ -#define REG_ADC_PTSR REG_ACCESS(RoReg, 0x40038124U) /**< \brief (ADC) Transfer Status Register */ -/* ========== Register definition for DACC peripheral ========== */ -#define REG_DACC_CR REG_ACCESS(WoReg, 0x4003C000U) /**< \brief (DACC) Control Register */ -#define REG_DACC_MR REG_ACCESS(RwReg, 0x4003C004U) /**< \brief (DACC) Mode Register */ -#define REG_DACC_CHER REG_ACCESS(WoReg, 0x4003C010U) /**< \brief (DACC) Channel Enable Register */ -#define REG_DACC_CHDR REG_ACCESS(WoReg, 0x4003C014U) /**< \brief (DACC) Channel Disable Register */ -#define REG_DACC_CHSR REG_ACCESS(RoReg, 0x4003C018U) /**< \brief (DACC) Channel Status Register */ -#define REG_DACC_CDR REG_ACCESS(WoReg, 0x4003C020U) /**< \brief (DACC) Conversion Data Register */ -#define REG_DACC_IER REG_ACCESS(WoReg, 0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */ -#define REG_DACC_IDR REG_ACCESS(WoReg, 0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */ -#define REG_DACC_IMR REG_ACCESS(RoReg, 0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */ -#define REG_DACC_ISR REG_ACCESS(RoReg, 0x4003C030U) /**< \brief (DACC) Interrupt Status Register */ -#define REG_DACC_ACR REG_ACCESS(RwReg, 0x4003C094U) /**< \brief (DACC) Analog Current Register */ -#define REG_DACC_WPMR REG_ACCESS(RwReg, 0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */ -#define REG_DACC_WPSR REG_ACCESS(RoReg, 0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */ -#define REG_DACC_RPR REG_ACCESS(RwReg, 0x4003C100U) /**< \brief (DACC) Receive Pointer Register */ -#define REG_DACC_RCR REG_ACCESS(RwReg, 0x4003C104U) /**< \brief (DACC) Receive Counter Register */ -#define REG_DACC_TPR REG_ACCESS(RwReg, 0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */ -#define REG_DACC_TCR REG_ACCESS(RwReg, 0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */ -#define REG_DACC_RNPR REG_ACCESS(RwReg, 0x4003C110U) /**< \brief (DACC) Receive Next Pointer Register */ -#define REG_DACC_RNCR REG_ACCESS(RwReg, 0x4003C114U) /**< \brief (DACC) Receive Next Counter Register */ -#define REG_DACC_TNPR REG_ACCESS(RwReg, 0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */ -#define REG_DACC_TNCR REG_ACCESS(RwReg, 0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */ -#define REG_DACC_PTCR REG_ACCESS(WoReg, 0x4003C120U) /**< \brief (DACC) Transfer Control Register */ -#define REG_DACC_PTSR REG_ACCESS(RoReg, 0x4003C124U) /**< \brief (DACC) Transfer Status Register */ -/* ========== Register definition for ACC peripheral ========== */ -#define REG_ACC_CR REG_ACCESS(WoReg, 0x40040000U) /**< \brief (ACC) Control Register */ -#define REG_ACC_MR REG_ACCESS(RwReg, 0x40040004U) /**< \brief (ACC) Mode Register */ -#define REG_ACC_IER REG_ACCESS(WoReg, 0x40040024U) /**< \brief (ACC) Interrupt Enable Register */ -#define REG_ACC_IDR REG_ACCESS(WoReg, 0x40040028U) /**< \brief (ACC) Interrupt Disable Register */ -#define REG_ACC_IMR REG_ACCESS(RoReg, 0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */ -#define REG_ACC_ISR REG_ACCESS(RoReg, 0x40040030U) /**< \brief (ACC) Interrupt Status Register */ -#define REG_ACC_ACR REG_ACCESS(RwReg, 0x40040094U) /**< \brief (ACC) Analog Control Register */ -#define REG_ACC_WPMR REG_ACCESS(RwReg, 0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */ -#define REG_ACC_WPSR REG_ACCESS(RoReg, 0x400400E8U) /**< \brief (ACC) Write Protect Status Register */ -/* ========== Register definition for CRCCU peripheral ========== */ -#define REG_CRCCU_DSCR REG_ACCESS(RwReg, 0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */ -#define REG_CRCCU_DMA_EN REG_ACCESS(WoReg, 0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */ -#define REG_CRCCU_DMA_DIS REG_ACCESS(WoReg, 0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */ -#define REG_CRCCU_DMA_SR REG_ACCESS(RoReg, 0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */ -#define REG_CRCCU_DMA_IER REG_ACCESS(WoReg, 0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */ -#define REG_CRCCU_DMA_IDR REG_ACCESS(WoReg, 0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */ -#define REG_CRCCU_DMA_IMR REG_ACCESS(RoReg, 0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */ -#define REG_CRCCU_DMA_ISR REG_ACCESS(RoReg, 0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */ -#define REG_CRCCU_CR REG_ACCESS(WoReg, 0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */ -#define REG_CRCCU_MR REG_ACCESS(RwReg, 0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */ -#define REG_CRCCU_SR REG_ACCESS(RoReg, 0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */ -#define REG_CRCCU_IER REG_ACCESS(WoReg, 0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */ -#define REG_CRCCU_IDR REG_ACCESS(WoReg, 0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */ -#define REG_CRCCU_IMR REG_ACCESS(RoReg, 0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */ -#define REG_CRCCU_ISR REG_ACCESS(RoReg, 0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */ -/* ========== Register definition for SMC peripheral ========== */ -#define REG_SMC_SETUP0 REG_ACCESS(RwReg, 0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ -#define REG_SMC_PULSE0 REG_ACCESS(RwReg, 0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ -#define REG_SMC_CYCLE0 REG_ACCESS(RwReg, 0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ -#define REG_SMC_MODE0 REG_ACCESS(RwReg, 0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ -#define REG_SMC_SETUP1 REG_ACCESS(RwReg, 0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ -#define REG_SMC_PULSE1 REG_ACCESS(RwReg, 0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ -#define REG_SMC_CYCLE1 REG_ACCESS(RwReg, 0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ -#define REG_SMC_MODE1 REG_ACCESS(RwReg, 0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ -#define REG_SMC_SETUP2 REG_ACCESS(RwReg, 0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ -#define REG_SMC_PULSE2 REG_ACCESS(RwReg, 0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ -#define REG_SMC_CYCLE2 REG_ACCESS(RwReg, 0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ -#define REG_SMC_MODE2 REG_ACCESS(RwReg, 0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ -#define REG_SMC_SETUP3 REG_ACCESS(RwReg, 0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ -#define REG_SMC_PULSE3 REG_ACCESS(RwReg, 0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ -#define REG_SMC_CYCLE3 REG_ACCESS(RwReg, 0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ -#define REG_SMC_MODE3 REG_ACCESS(RwReg, 0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ -#define REG_SMC_SETUP4 REG_ACCESS(RwReg, 0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */ -#define REG_SMC_PULSE4 REG_ACCESS(RwReg, 0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */ -#define REG_SMC_CYCLE4 REG_ACCESS(RwReg, 0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */ -#define REG_SMC_MODE4 REG_ACCESS(RwReg, 0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */ -#define REG_SMC_OCMS REG_ACCESS(RwReg, 0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */ -#define REG_SMC_KEY1 REG_ACCESS(WoReg, 0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */ -#define REG_SMC_KEY2 REG_ACCESS(WoReg, 0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */ -#define REG_SMC_WPMR REG_ACCESS(RwReg, 0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */ -#define REG_SMC_WPSR REG_ACCESS(RoReg, 0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */ -/* ========== Register definition for MATRIX peripheral ========== */ -#define REG_MATRIX_MCFG REG_ACCESS(RwReg, 0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ -#define REG_MATRIX_SCFG REG_ACCESS(RwReg, 0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ -#define REG_MATRIX_PRAS0 REG_ACCESS(RwReg, 0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ -#define REG_MATRIX_PRAS1 REG_ACCESS(RwReg, 0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ -#define REG_MATRIX_PRAS2 REG_ACCESS(RwReg, 0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ -#define REG_MATRIX_PRAS3 REG_ACCESS(RwReg, 0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ -#define REG_MATRIX_PRAS4 REG_ACCESS(RwReg, 0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ -#define REG_MATRIX_SYSIO REG_ACCESS(RwReg, 0x400E0314U) /**< \brief (MATRIX) System IO Configuration register */ -#define REG_MATRIX_SMCNFCS REG_ACCESS(RwReg, 0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */ -#define REG_MATRIX_WPMR REG_ACCESS(RwReg, 0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */ -#define REG_MATRIX_WPSR REG_ACCESS(RoReg, 0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */ -/* ========== Register definition for PMC peripheral ========== */ -#define REG_PMC_SCER REG_ACCESS(WoReg, 0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ -#define REG_PMC_SCDR REG_ACCESS(WoReg, 0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ -#define REG_PMC_SCSR REG_ACCESS(RoReg, 0x400E0408U) /**< \brief (PMC) System Clock Status Register */ -#define REG_PMC_PCER0 REG_ACCESS(WoReg, 0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ -#define REG_PMC_PCDR0 REG_ACCESS(WoReg, 0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ -#define REG_PMC_PCSR0 REG_ACCESS(RoReg, 0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ -#define REG_PMC_MOR REG_ACCESS(RwReg, 0x400E0420U) /**< \brief (PMC) Main Oscillator Register */ -#define REG_PMC_MCFR REG_ACCESS(RoReg, 0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */ -#define REG_PMC_PLLAR REG_ACCESS(RwReg, 0x400E0428U) /**< \brief (PMC) PLLA Register */ -#define REG_PMC_PLLBR REG_ACCESS(RwReg, 0x400E042CU) /**< \brief (PMC) PLLB Register */ -#define REG_PMC_MCKR REG_ACCESS(RwReg, 0x400E0430U) /**< \brief (PMC) Master Clock Register */ -#define REG_PMC_USB REG_ACCESS(RwReg, 0x400E0438U) /**< \brief (PMC) USB Clock Register */ -#define REG_PMC_PCK REG_ACCESS(RwReg, 0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */ -#define REG_PMC_IER REG_ACCESS(WoReg, 0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */ -#define REG_PMC_IDR REG_ACCESS(WoReg, 0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */ -#define REG_PMC_SR REG_ACCESS(RoReg, 0x400E0468U) /**< \brief (PMC) Status Register */ -#define REG_PMC_IMR REG_ACCESS(RoReg, 0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */ -#define REG_PMC_FSMR REG_ACCESS(RwReg, 0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */ -#define REG_PMC_FSPR REG_ACCESS(RwReg, 0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */ -#define REG_PMC_FOCR REG_ACCESS(WoReg, 0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ -#define REG_PMC_WPMR REG_ACCESS(RwReg, 0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */ -#define REG_PMC_WPSR REG_ACCESS(RoReg, 0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */ -#define REG_PMC_PCER1 REG_ACCESS(WoReg, 0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ -#define REG_PMC_PCDR1 REG_ACCESS(WoReg, 0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ -#define REG_PMC_PCSR1 REG_ACCESS(RoReg, 0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ -#define REG_PMC_OCR REG_ACCESS(RwReg, 0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */ -/* ========== Register definition for UART0 peripheral ========== */ -#define REG_UART0_CR REG_ACCESS(WoReg, 0x400E0600U) /**< \brief (UART0) Control Register */ -#define REG_UART0_MR REG_ACCESS(RwReg, 0x400E0604U) /**< \brief (UART0) Mode Register */ -#define REG_UART0_IER REG_ACCESS(WoReg, 0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */ -#define REG_UART0_IDR REG_ACCESS(WoReg, 0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */ -#define REG_UART0_IMR REG_ACCESS(RoReg, 0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */ -#define REG_UART0_SR REG_ACCESS(RoReg, 0x400E0614U) /**< \brief (UART0) Status Register */ -#define REG_UART0_RHR REG_ACCESS(RoReg, 0x400E0618U) /**< \brief (UART0) Receive Holding Register */ -#define REG_UART0_THR REG_ACCESS(WoReg, 0x400E061CU) /**< \brief (UART0) Transmit Holding Register */ -#define REG_UART0_BRGR REG_ACCESS(RwReg, 0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */ -#define REG_UART0_RPR REG_ACCESS(RwReg, 0x400E0700U) /**< \brief (UART0) Receive Pointer Register */ -#define REG_UART0_RCR REG_ACCESS(RwReg, 0x400E0704U) /**< \brief (UART0) Receive Counter Register */ -#define REG_UART0_TPR REG_ACCESS(RwReg, 0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */ -#define REG_UART0_TCR REG_ACCESS(RwReg, 0x400E070CU) /**< \brief (UART0) Transmit Counter Register */ -#define REG_UART0_RNPR REG_ACCESS(RwReg, 0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */ -#define REG_UART0_RNCR REG_ACCESS(RwReg, 0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */ -#define REG_UART0_TNPR REG_ACCESS(RwReg, 0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */ -#define REG_UART0_TNCR REG_ACCESS(RwReg, 0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */ -#define REG_UART0_PTCR REG_ACCESS(WoReg, 0x400E0720U) /**< \brief (UART0) Transfer Control Register */ -#define REG_UART0_PTSR REG_ACCESS(RoReg, 0x400E0724U) /**< \brief (UART0) Transfer Status Register */ -/* ========== Register definition for CHIPID peripheral ========== */ -#define REG_CHIPID_CIDR REG_ACCESS(RoReg, 0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ -#define REG_CHIPID_EXID REG_ACCESS(RoReg, 0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ -/* ========== Register definition for UART1 peripheral ========== */ -#define REG_UART1_CR REG_ACCESS(WoReg, 0x400E0800U) /**< \brief (UART1) Control Register */ -#define REG_UART1_MR REG_ACCESS(RwReg, 0x400E0804U) /**< \brief (UART1) Mode Register */ -#define REG_UART1_IER REG_ACCESS(WoReg, 0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */ -#define REG_UART1_IDR REG_ACCESS(WoReg, 0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */ -#define REG_UART1_IMR REG_ACCESS(RoReg, 0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */ -#define REG_UART1_SR REG_ACCESS(RoReg, 0x400E0814U) /**< \brief (UART1) Status Register */ -#define REG_UART1_RHR REG_ACCESS(RoReg, 0x400E0818U) /**< \brief (UART1) Receive Holding Register */ -#define REG_UART1_THR REG_ACCESS(WoReg, 0x400E081CU) /**< \brief (UART1) Transmit Holding Register */ -#define REG_UART1_BRGR REG_ACCESS(RwReg, 0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */ -#define REG_UART1_RPR REG_ACCESS(RwReg, 0x400E0900U) /**< \brief (UART1) Receive Pointer Register */ -#define REG_UART1_RCR REG_ACCESS(RwReg, 0x400E0904U) /**< \brief (UART1) Receive Counter Register */ -#define REG_UART1_TPR REG_ACCESS(RwReg, 0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */ -#define REG_UART1_TCR REG_ACCESS(RwReg, 0x400E090CU) /**< \brief (UART1) Transmit Counter Register */ -#define REG_UART1_RNPR REG_ACCESS(RwReg, 0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */ -#define REG_UART1_RNCR REG_ACCESS(RwReg, 0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */ -#define REG_UART1_TNPR REG_ACCESS(RwReg, 0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */ -#define REG_UART1_TNCR REG_ACCESS(RwReg, 0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */ -#define REG_UART1_PTCR REG_ACCESS(WoReg, 0x400E0920U) /**< \brief (UART1) Transfer Control Register */ -#define REG_UART1_PTSR REG_ACCESS(RoReg, 0x400E0924U) /**< \brief (UART1) Transfer Status Register */ -/* ========== Register definition for EFC peripheral ========== */ -#define REG_EFC_FMR REG_ACCESS(RwReg, 0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */ -#define REG_EFC_FCR REG_ACCESS(WoReg, 0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */ -#define REG_EFC_FSR REG_ACCESS(RoReg, 0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */ -#define REG_EFC_FRR REG_ACCESS(RoReg, 0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */ -/* ========== Register definition for PIOA peripheral ========== */ -#define REG_PIOA_PER REG_ACCESS(WoReg, 0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ -#define REG_PIOA_PDR REG_ACCESS(WoReg, 0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ -#define REG_PIOA_PSR REG_ACCESS(RoReg, 0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ -#define REG_PIOA_OER REG_ACCESS(WoReg, 0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ -#define REG_PIOA_ODR REG_ACCESS(WoReg, 0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ -#define REG_PIOA_OSR REG_ACCESS(RoReg, 0x400E0E18U) /**< \brief (PIOA) Output Status Register */ -#define REG_PIOA_IFER REG_ACCESS(WoReg, 0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ -#define REG_PIOA_IFDR REG_ACCESS(WoReg, 0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ -#define REG_PIOA_IFSR REG_ACCESS(RoReg, 0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ -#define REG_PIOA_SODR REG_ACCESS(WoReg, 0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ -#define REG_PIOA_CODR REG_ACCESS(WoReg, 0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ -#define REG_PIOA_ODSR REG_ACCESS(RwReg, 0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ -#define REG_PIOA_PDSR REG_ACCESS(RoReg, 0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ -#define REG_PIOA_IER REG_ACCESS(WoReg, 0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ -#define REG_PIOA_IDR REG_ACCESS(WoReg, 0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ -#define REG_PIOA_IMR REG_ACCESS(RoReg, 0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ -#define REG_PIOA_ISR REG_ACCESS(RoReg, 0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ -#define REG_PIOA_MDER REG_ACCESS(WoReg, 0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ -#define REG_PIOA_MDDR REG_ACCESS(WoReg, 0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ -#define REG_PIOA_MDSR REG_ACCESS(RoReg, 0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ -#define REG_PIOA_PUDR REG_ACCESS(WoReg, 0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ -#define REG_PIOA_PUER REG_ACCESS(WoReg, 0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ -#define REG_PIOA_PUSR REG_ACCESS(RoReg, 0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ -#define REG_PIOA_ABCDSR REG_ACCESS(RwReg, 0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ -#define REG_PIOA_SCIFSR REG_ACCESS(WoReg, 0x400E0E80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */ -#define REG_PIOA_DIFSR REG_ACCESS(WoReg, 0x400E0E84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */ -#define REG_PIOA_IFDGSR REG_ACCESS(RoReg, 0x400E0E88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOA_SCDR REG_ACCESS(RwReg, 0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ -#define REG_PIOA_PPDDR REG_ACCESS(WoReg, 0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ -#define REG_PIOA_PPDER REG_ACCESS(WoReg, 0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ -#define REG_PIOA_PPDSR REG_ACCESS(RoReg, 0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ -#define REG_PIOA_OWER REG_ACCESS(WoReg, 0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ -#define REG_PIOA_OWDR REG_ACCESS(WoReg, 0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ -#define REG_PIOA_OWSR REG_ACCESS(RoReg, 0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ -#define REG_PIOA_AIMER REG_ACCESS(WoReg, 0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ -#define REG_PIOA_AIMDR REG_ACCESS(WoReg, 0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ -#define REG_PIOA_AIMMR REG_ACCESS(RoReg, 0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ -#define REG_PIOA_ESR REG_ACCESS(WoReg, 0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ -#define REG_PIOA_LSR REG_ACCESS(WoReg, 0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ -#define REG_PIOA_ELSR REG_ACCESS(RoReg, 0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ -#define REG_PIOA_FELLSR REG_ACCESS(WoReg, 0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ -#define REG_PIOA_REHLSR REG_ACCESS(WoReg, 0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ -#define REG_PIOA_FRLHSR REG_ACCESS(RoReg, 0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ -#define REG_PIOA_LOCKSR REG_ACCESS(RoReg, 0x400E0EE0U) /**< \brief (PIOA) Lock Status */ -#define REG_PIOA_WPMR REG_ACCESS(RwReg, 0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */ -#define REG_PIOA_WPSR REG_ACCESS(RoReg, 0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */ -#define REG_PIOA_SCHMITT REG_ACCESS(RwReg, 0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ -#define REG_PIOA_PCMR REG_ACCESS(RwReg, 0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */ -#define REG_PIOA_PCIER REG_ACCESS(WoReg, 0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */ -#define REG_PIOA_PCIDR REG_ACCESS(WoReg, 0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */ -#define REG_PIOA_PCIMR REG_ACCESS(RoReg, 0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */ -#define REG_PIOA_PCISR REG_ACCESS(RoReg, 0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */ -#define REG_PIOA_PCRHR REG_ACCESS(RoReg, 0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */ -/* ========== Register definition for PIOB peripheral ========== */ -#define REG_PIOB_PER REG_ACCESS(WoReg, 0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ -#define REG_PIOB_PDR REG_ACCESS(WoReg, 0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ -#define REG_PIOB_PSR REG_ACCESS(RoReg, 0x400E1008U) /**< \brief (PIOB) PIO Status Register */ -#define REG_PIOB_OER REG_ACCESS(WoReg, 0x400E1010U) /**< \brief (PIOB) Output Enable Register */ -#define REG_PIOB_ODR REG_ACCESS(WoReg, 0x400E1014U) /**< \brief (PIOB) Output Disable Register */ -#define REG_PIOB_OSR REG_ACCESS(RoReg, 0x400E1018U) /**< \brief (PIOB) Output Status Register */ -#define REG_PIOB_IFER REG_ACCESS(WoReg, 0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ -#define REG_PIOB_IFDR REG_ACCESS(WoReg, 0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ -#define REG_PIOB_IFSR REG_ACCESS(RoReg, 0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ -#define REG_PIOB_SODR REG_ACCESS(WoReg, 0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ -#define REG_PIOB_CODR REG_ACCESS(WoReg, 0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ -#define REG_PIOB_ODSR REG_ACCESS(RwReg, 0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ -#define REG_PIOB_PDSR REG_ACCESS(RoReg, 0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ -#define REG_PIOB_IER REG_ACCESS(WoReg, 0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ -#define REG_PIOB_IDR REG_ACCESS(WoReg, 0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ -#define REG_PIOB_IMR REG_ACCESS(RoReg, 0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ -#define REG_PIOB_ISR REG_ACCESS(RoReg, 0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ -#define REG_PIOB_MDER REG_ACCESS(WoReg, 0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ -#define REG_PIOB_MDDR REG_ACCESS(WoReg, 0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ -#define REG_PIOB_MDSR REG_ACCESS(RoReg, 0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ -#define REG_PIOB_PUDR REG_ACCESS(WoReg, 0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ -#define REG_PIOB_PUER REG_ACCESS(WoReg, 0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ -#define REG_PIOB_PUSR REG_ACCESS(RoReg, 0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ -#define REG_PIOB_ABCDSR REG_ACCESS(RwReg, 0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ -#define REG_PIOB_SCIFSR REG_ACCESS(WoReg, 0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */ -#define REG_PIOB_DIFSR REG_ACCESS(WoReg, 0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */ -#define REG_PIOB_IFDGSR REG_ACCESS(RoReg, 0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOB_SCDR REG_ACCESS(RwReg, 0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ -#define REG_PIOB_PPDDR REG_ACCESS(WoReg, 0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ -#define REG_PIOB_PPDER REG_ACCESS(WoReg, 0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ -#define REG_PIOB_PPDSR REG_ACCESS(RoReg, 0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ -#define REG_PIOB_OWER REG_ACCESS(WoReg, 0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ -#define REG_PIOB_OWDR REG_ACCESS(WoReg, 0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ -#define REG_PIOB_OWSR REG_ACCESS(RoReg, 0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ -#define REG_PIOB_AIMER REG_ACCESS(WoReg, 0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ -#define REG_PIOB_AIMDR REG_ACCESS(WoReg, 0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ -#define REG_PIOB_AIMMR REG_ACCESS(RoReg, 0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ -#define REG_PIOB_ESR REG_ACCESS(WoReg, 0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ -#define REG_PIOB_LSR REG_ACCESS(WoReg, 0x400E10C4U) /**< \brief (PIOB) Level Select Register */ -#define REG_PIOB_ELSR REG_ACCESS(RoReg, 0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ -#define REG_PIOB_FELLSR REG_ACCESS(WoReg, 0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ -#define REG_PIOB_REHLSR REG_ACCESS(WoReg, 0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ -#define REG_PIOB_FRLHSR REG_ACCESS(RoReg, 0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ -#define REG_PIOB_LOCKSR REG_ACCESS(RoReg, 0x400E10E0U) /**< \brief (PIOB) Lock Status */ -#define REG_PIOB_WPMR REG_ACCESS(RwReg, 0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */ -#define REG_PIOB_WPSR REG_ACCESS(RoReg, 0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */ -#define REG_PIOB_SCHMITT REG_ACCESS(RwReg, 0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ -#define REG_PIOB_PCMR REG_ACCESS(RwReg, 0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */ -#define REG_PIOB_PCIER REG_ACCESS(WoReg, 0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */ -#define REG_PIOB_PCIDR REG_ACCESS(WoReg, 0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */ -#define REG_PIOB_PCIMR REG_ACCESS(RoReg, 0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */ -#define REG_PIOB_PCISR REG_ACCESS(RoReg, 0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */ -#define REG_PIOB_PCRHR REG_ACCESS(RoReg, 0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */ -/* ========== Register definition for PIOC peripheral ========== */ -#define REG_PIOC_PER REG_ACCESS(WoReg, 0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ -#define REG_PIOC_PDR REG_ACCESS(WoReg, 0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ -#define REG_PIOC_PSR REG_ACCESS(RoReg, 0x400E1208U) /**< \brief (PIOC) PIO Status Register */ -#define REG_PIOC_OER REG_ACCESS(WoReg, 0x400E1210U) /**< \brief (PIOC) Output Enable Register */ -#define REG_PIOC_ODR REG_ACCESS(WoReg, 0x400E1214U) /**< \brief (PIOC) Output Disable Register */ -#define REG_PIOC_OSR REG_ACCESS(RoReg, 0x400E1218U) /**< \brief (PIOC) Output Status Register */ -#define REG_PIOC_IFER REG_ACCESS(WoReg, 0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ -#define REG_PIOC_IFDR REG_ACCESS(WoReg, 0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ -#define REG_PIOC_IFSR REG_ACCESS(RoReg, 0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ -#define REG_PIOC_SODR REG_ACCESS(WoReg, 0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ -#define REG_PIOC_CODR REG_ACCESS(WoReg, 0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ -#define REG_PIOC_ODSR REG_ACCESS(RwReg, 0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ -#define REG_PIOC_PDSR REG_ACCESS(RoReg, 0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ -#define REG_PIOC_IER REG_ACCESS(WoReg, 0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ -#define REG_PIOC_IDR REG_ACCESS(WoReg, 0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ -#define REG_PIOC_IMR REG_ACCESS(RoReg, 0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ -#define REG_PIOC_ISR REG_ACCESS(RoReg, 0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ -#define REG_PIOC_MDER REG_ACCESS(WoReg, 0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ -#define REG_PIOC_MDDR REG_ACCESS(WoReg, 0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ -#define REG_PIOC_MDSR REG_ACCESS(RoReg, 0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ -#define REG_PIOC_PUDR REG_ACCESS(WoReg, 0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ -#define REG_PIOC_PUER REG_ACCESS(WoReg, 0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ -#define REG_PIOC_PUSR REG_ACCESS(RoReg, 0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ -#define REG_PIOC_ABCDSR REG_ACCESS(RwReg, 0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */ -#define REG_PIOC_SCIFSR REG_ACCESS(WoReg, 0x400E1280U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */ -#define REG_PIOC_DIFSR REG_ACCESS(WoReg, 0x400E1284U) /**< \brief (PIOC) Debouncing Input Filter Select Register */ -#define REG_PIOC_IFDGSR REG_ACCESS(RoReg, 0x400E1288U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOC_SCDR REG_ACCESS(RwReg, 0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ -#define REG_PIOC_PPDDR REG_ACCESS(WoReg, 0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */ -#define REG_PIOC_PPDER REG_ACCESS(WoReg, 0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */ -#define REG_PIOC_PPDSR REG_ACCESS(RoReg, 0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */ -#define REG_PIOC_OWER REG_ACCESS(WoReg, 0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ -#define REG_PIOC_OWDR REG_ACCESS(WoReg, 0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ -#define REG_PIOC_OWSR REG_ACCESS(RoReg, 0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ -#define REG_PIOC_AIMER REG_ACCESS(WoReg, 0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ -#define REG_PIOC_AIMDR REG_ACCESS(WoReg, 0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ -#define REG_PIOC_AIMMR REG_ACCESS(RoReg, 0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ -#define REG_PIOC_ESR REG_ACCESS(WoReg, 0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ -#define REG_PIOC_LSR REG_ACCESS(WoReg, 0x400E12C4U) /**< \brief (PIOC) Level Select Register */ -#define REG_PIOC_ELSR REG_ACCESS(RoReg, 0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ -#define REG_PIOC_FELLSR REG_ACCESS(WoReg, 0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ -#define REG_PIOC_REHLSR REG_ACCESS(WoReg, 0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ -#define REG_PIOC_FRLHSR REG_ACCESS(RoReg, 0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ -#define REG_PIOC_LOCKSR REG_ACCESS(RoReg, 0x400E12E0U) /**< \brief (PIOC) Lock Status */ -#define REG_PIOC_WPMR REG_ACCESS(RwReg, 0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */ -#define REG_PIOC_WPSR REG_ACCESS(RoReg, 0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */ -#define REG_PIOC_SCHMITT REG_ACCESS(RwReg, 0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */ -#define REG_PIOC_PCMR REG_ACCESS(RwReg, 0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */ -#define REG_PIOC_PCIER REG_ACCESS(WoReg, 0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */ -#define REG_PIOC_PCIDR REG_ACCESS(WoReg, 0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */ -#define REG_PIOC_PCIMR REG_ACCESS(RoReg, 0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */ -#define REG_PIOC_PCISR REG_ACCESS(RoReg, 0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */ -#define REG_PIOC_PCRHR REG_ACCESS(RoReg, 0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */ -/* ========== Register definition for RSTC peripheral ========== */ -#define REG_RSTC_CR REG_ACCESS(WoReg, 0x400E1400U) /**< \brief (RSTC) Control Register */ -#define REG_RSTC_SR REG_ACCESS(RoReg, 0x400E1404U) /**< \brief (RSTC) Status Register */ -#define REG_RSTC_MR REG_ACCESS(RwReg, 0x400E1408U) /**< \brief (RSTC) Mode Register */ -/* ========== Register definition for SUPC peripheral ========== */ -#define REG_SUPC_CR REG_ACCESS(WoReg, 0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */ -#define REG_SUPC_SMMR REG_ACCESS(RwReg, 0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ -#define REG_SUPC_MR REG_ACCESS(RwReg, 0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */ -#define REG_SUPC_WUMR REG_ACCESS(RwReg, 0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */ -#define REG_SUPC_WUIR REG_ACCESS(RwReg, 0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */ -#define REG_SUPC_SR REG_ACCESS(RoReg, 0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */ -/* ========== Register definition for RTT peripheral ========== */ -#define REG_RTT_MR REG_ACCESS(RwReg, 0x400E1430U) /**< \brief (RTT) Mode Register */ -#define REG_RTT_AR REG_ACCESS(RwReg, 0x400E1434U) /**< \brief (RTT) Alarm Register */ -#define REG_RTT_VR REG_ACCESS(RoReg, 0x400E1438U) /**< \brief (RTT) Value Register */ -#define REG_RTT_SR REG_ACCESS(RoReg, 0x400E143CU) /**< \brief (RTT) Status Register */ -/* ========== Register definition for WDT peripheral ========== */ -#define REG_WDT_CR REG_ACCESS(WoReg, 0x400E1450U) /**< \brief (WDT) Control Register */ -#define REG_WDT_MR REG_ACCESS(RwReg, 0x400E1454U) /**< \brief (WDT) Mode Register */ -#define REG_WDT_SR REG_ACCESS(RoReg, 0x400E1458U) /**< \brief (WDT) Status Register */ -/* ========== Register definition for RTC peripheral ========== */ -#define REG_RTC_CR REG_ACCESS(RwReg, 0x400E1460U) /**< \brief (RTC) Control Register */ -#define REG_RTC_MR REG_ACCESS(RwReg, 0x400E1464U) /**< \brief (RTC) Mode Register */ -#define REG_RTC_TIMR REG_ACCESS(RwReg, 0x400E1468U) /**< \brief (RTC) Time Register */ -#define REG_RTC_CALR REG_ACCESS(RwReg, 0x400E146CU) /**< \brief (RTC) Calendar Register */ -#define REG_RTC_TIMALR REG_ACCESS(RwReg, 0x400E1470U) /**< \brief (RTC) Time Alarm Register */ -#define REG_RTC_CALALR REG_ACCESS(RwReg, 0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */ -#define REG_RTC_SR REG_ACCESS(RoReg, 0x400E1478U) /**< \brief (RTC) Status Register */ -#define REG_RTC_SCCR REG_ACCESS(WoReg, 0x400E147CU) /**< \brief (RTC) Status Clear Command Register */ -#define REG_RTC_IER REG_ACCESS(WoReg, 0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */ -#define REG_RTC_IDR REG_ACCESS(WoReg, 0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */ -#define REG_RTC_IMR REG_ACCESS(RoReg, 0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */ -#define REG_RTC_VER REG_ACCESS(RoReg, 0x400E148CU) /**< \brief (RTC) Valid Entry Register */ -/* ========== Register definition for GPBR peripheral ========== */ -#define REG_GPBR_GPBR0 REG_ACCESS(RwReg, 0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register 0 */ -#define REG_GPBR_GPBR1 REG_ACCESS(RwReg, 0x400E1494U) /**< \brief (GPBR) General Purpose Backup Register 1 */ -#define REG_GPBR_GPBR2 REG_ACCESS(RwReg, 0x400E1498U) /**< \brief (GPBR) General Purpose Backup Register 2 */ -#define REG_GPBR_GPBR3 REG_ACCESS(RwReg, 0x400E149CU) /**< \brief (GPBR) General Purpose Backup Register 3 */ -/*@}*/ - -/* ***************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_id Peripheral Ids Definitions */ -/*@{*/ - -#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ -#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ -#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ -#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ -#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ -#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ -#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */ -#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ -#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ -#define ID_SMC (10) /**< \brief Static Memory Controller (SMC) */ -#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ -#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ -#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ -#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ -#define ID_USART1 (15) /**< \brief USART 1 (USART1) */ -#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ -#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ -#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ -#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ -#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */ -#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ -#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ -#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ -#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ -#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ -#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ -#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ -#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ -#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ -#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ -#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ -#define ID_UDP (34) /**< \brief USB Device Port (UDP) */ -/*@}*/ - -/* ***************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_base Peripheral Base Address Definitions */ -/*@{*/ - -#define HSMCI CAST(Hsmci , 0x40000000U) /**< \brief (HSMCI ) Base Address */ -#define PDC_HSMCI CAST(Pdc , 0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ -#define SSC CAST(Ssc , 0x40004000U) /**< \brief (SSC ) Base Address */ -#define PDC_SSC CAST(Pdc , 0x40004100U) /**< \brief (PDC_SSC ) Base Address */ -#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */ -#define PDC_SPI CAST(Pdc , 0x40008100U) /**< \brief (PDC_SPI ) Base Address */ -#define TC0 CAST(Tc , 0x40010000U) /**< \brief (TC0 ) Base Address */ -#define TC1 CAST(Tc , 0x40014000U) /**< \brief (TC1 ) Base Address */ -#define TWI0 CAST(Twi , 0x40018000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 CAST(Pdc , 0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 CAST(Twi , 0x4001C000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 CAST(Pdc , 0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define PWM CAST(Pwm , 0x40020000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM CAST(Pdc , 0x40020100U) /**< \brief (PDC_PWM ) Base Address */ -#define USART0 CAST(Usart , 0x40024000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 CAST(Pdc , 0x40024100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 CAST(Usart , 0x40028000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 CAST(Pdc , 0x40028100U) /**< \brief (PDC_USART1) Base Address */ -#define UDP CAST(Udp , 0x40034000U) /**< \brief (UDP ) Base Address */ -#define ADC CAST(Adc , 0x40038000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC CAST(Pdc , 0x40038100U) /**< \brief (PDC_ADC ) Base Address */ -#define DACC CAST(Dacc , 0x4003C000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC CAST(Pdc , 0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ -#define ACC CAST(Acc , 0x40040000U) /**< \brief (ACC ) Base Address */ -#define CRCCU CAST(Crccu , 0x40044000U) /**< \brief (CRCCU ) Base Address */ -#define SMC CAST(Smc , 0x400E0000U) /**< \brief (SMC ) Base Address */ -#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */ -#define UART0 CAST(Uart , 0x400E0600U) /**< \brief (UART0 ) Base Address */ -#define PDC_UART0 CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ -#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define UART1 CAST(Uart , 0x400E0800U) /**< \brief (UART1 ) Base Address */ -#define PDC_UART1 CAST(Pdc , 0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ -#define EFC CAST(Efc , 0x400E0A00U) /**< \brief (EFC ) Base Address */ -#define PIOA CAST(Pio , 0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB CAST(Pio , 0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC CAST(Pio , 0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define RSTC CAST(Rstc , 0x400E1400U) /**< \brief (RSTC ) Base Address */ -#define SUPC CAST(Supc , 0x400E1410U) /**< \brief (SUPC ) Base Address */ -#define RTT CAST(Rtt , 0x400E1430U) /**< \brief (RTT ) Base Address */ -#define WDT CAST(Wdt , 0x400E1450U) /**< \brief (WDT ) Base Address */ -#define RTC CAST(Rtc , 0x400E1460U) /**< \brief (RTC ) Base Address */ -#define GPBR CAST(Gpbr , 0x400E1490U) /**< \brief (GPBR ) Base Address */ - -// indices for three pio structures -#define iPIOA 0 -#define iPIOB 1 -#define iPIOC 2 -/*@}*/ - -/* ***************************************************************************** */ -/* PIO DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_pio Peripheral Pio Definitions */ -/*@{*/ - -#define PIO_PA0 (1 << 0) /**< \brief Pin Controlled by PA0 */ -#define PIO_PA1 (1 << 1) /**< \brief Pin Controlled by PA1 */ -#define PIO_PA2 (1 << 2) /**< \brief Pin Controlled by PA2 */ -#define PIO_PA3 (1 << 3) /**< \brief Pin Controlled by PA3 */ -#define PIO_PA4 (1 << 4) /**< \brief Pin Controlled by PA4 */ -#define PIO_PA5 (1 << 5) /**< \brief Pin Controlled by PA5 */ -#define PIO_PA6 (1 << 6) /**< \brief Pin Controlled by PA6 */ -#define PIO_PA7 (1 << 7) /**< \brief Pin Controlled by PA7 */ -#define PIO_PA8 (1 << 8) /**< \brief Pin Controlled by PA8 */ -#define PIO_PA9 (1 << 9) /**< \brief Pin Controlled by PA9 */ -#define PIO_PA10 (1 << 10) /**< \brief Pin Controlled by PA10 */ -#define PIO_PA11 (1 << 11) /**< \brief Pin Controlled by PA11 */ -#define PIO_PA12 (1 << 12) /**< \brief Pin Controlled by PA12 */ -#define PIO_PA13 (1 << 13) /**< \brief Pin Controlled by PA13 */ -#define PIO_PA14 (1 << 14) /**< \brief Pin Controlled by PA14 */ -#define PIO_PA15 (1 << 15) /**< \brief Pin Controlled by PA15 */ -#define PIO_PA16 (1 << 16) /**< \brief Pin Controlled by PA16 */ -#define PIO_PA17 (1 << 17) /**< \brief Pin Controlled by PA17 */ -#define PIO_PA18 (1 << 18) /**< \brief Pin Controlled by PA18 */ -#define PIO_PA19 (1 << 19) /**< \brief Pin Controlled by PA19 */ -#define PIO_PA20 (1 << 20) /**< \brief Pin Controlled by PA20 */ -#define PIO_PA21 (1 << 21) /**< \brief Pin Controlled by PA21 */ -#define PIO_PA22 (1 << 22) /**< \brief Pin Controlled by PA22 */ -#define PIO_PA23 (1 << 23) /**< \brief Pin Controlled by PA23 */ -#define PIO_PA24 (1 << 24) /**< \brief Pin Controlled by PA24 */ -#define PIO_PA25 (1 << 25) /**< \brief Pin Controlled by PA25 */ -#define PIO_PA26 (1 << 26) /**< \brief Pin Controlled by PA26 */ -#define PIO_PA27 (1 << 27) /**< \brief Pin Controlled by PA27 */ -#define PIO_PA28 (1 << 28) /**< \brief Pin Controlled by PA28 */ -#define PIO_PA29 (1 << 29) /**< \brief Pin Controlled by PA29 */ -#define PIO_PA30 (1 << 30) /**< \brief Pin Controlled by PA30 */ -#define PIO_PA31 (1 << 31) /**< \brief Pin Controlled by PA31 */ -#define PIO_PB0 (1 << 0) /**< \brief Pin Controlled by PB0 */ -#define PIO_PB1 (1 << 1) /**< \brief Pin Controlled by PB1 */ -#define PIO_PB2 (1 << 2) /**< \brief Pin Controlled by PB2 */ -#define PIO_PB3 (1 << 3) /**< \brief Pin Controlled by PB3 */ -#define PIO_PB4 (1 << 4) /**< \brief Pin Controlled by PB4 */ -#define PIO_PB5 (1 << 5) /**< \brief Pin Controlled by PB5 */ -#define PIO_PB6 (1 << 6) /**< \brief Pin Controlled by PB6 */ -#define PIO_PB7 (1 << 7) /**< \brief Pin Controlled by PB7 */ -#define PIO_PB8 (1 << 8) /**< \brief Pin Controlled by PB8 */ -#define PIO_PB9 (1 << 9) /**< \brief Pin Controlled by PB9 */ -#define PIO_PB10 (1 << 10) /**< \brief Pin Controlled by PB10 */ -#define PIO_PB11 (1 << 11) /**< \brief Pin Controlled by PB11 */ -#define PIO_PB12 (1 << 12) /**< \brief Pin Controlled by PB12 */ -#define PIO_PB13 (1 << 13) /**< \brief Pin Controlled by PB13 */ -#define PIO_PB14 (1 << 14) /**< \brief Pin Controlled by PB14 */ -#define PIO_PC0 (1 << 0) /**< \brief Pin Controlled by PC0 */ -#define PIO_PC1 (1 << 1) /**< \brief Pin Controlled by PC1 */ -#define PIO_PC2 (1 << 2) /**< \brief Pin Controlled by PC2 */ -#define PIO_PC3 (1 << 3) /**< \brief Pin Controlled by PC3 */ -#define PIO_PC4 (1 << 4) /**< \brief Pin Controlled by PC4 */ -#define PIO_PC5 (1 << 5) /**< \brief Pin Controlled by PC5 */ -#define PIO_PC6 (1 << 6) /**< \brief Pin Controlled by PC6 */ -#define PIO_PC7 (1 << 7) /**< \brief Pin Controlled by PC7 */ -#define PIO_PC8 (1 << 8) /**< \brief Pin Controlled by PC8 */ -#define PIO_PC9 (1 << 9) /**< \brief Pin Controlled by PC9 */ -#define PIO_PC10 (1 << 10) /**< \brief Pin Controlled by PC10 */ -#define PIO_PC11 (1 << 11) /**< \brief Pin Controlled by PC11 */ -#define PIO_PC12 (1 << 12) /**< \brief Pin Controlled by PC12 */ -#define PIO_PC13 (1 << 13) /**< \brief Pin Controlled by PC13 */ -#define PIO_PC14 (1 << 14) /**< \brief Pin Controlled by PC14 */ -#define PIO_PC15 (1 << 15) /**< \brief Pin Controlled by PC15 */ -#define PIO_PC16 (1 << 16) /**< \brief Pin Controlled by PC16 */ -#define PIO_PC17 (1 << 17) /**< \brief Pin Controlled by PC17 */ -#define PIO_PC18 (1 << 18) /**< \brief Pin Controlled by PC18 */ -#define PIO_PC19 (1 << 19) /**< \brief Pin Controlled by PC19 */ -#define PIO_PC20 (1 << 20) /**< \brief Pin Controlled by PC20 */ -#define PIO_PC21 (1 << 21) /**< \brief Pin Controlled by PC21 */ -#define PIO_PC22 (1 << 22) /**< \brief Pin Controlled by PC22 */ -#define PIO_PC23 (1 << 23) /**< \brief Pin Controlled by PC23 */ -#define PIO_PC24 (1 << 24) /**< \brief Pin Controlled by PC24 */ -#define PIO_PC25 (1 << 25) /**< \brief Pin Controlled by PC25 */ -#define PIO_PC26 (1 << 26) /**< \brief Pin Controlled by PC26 */ -#define PIO_PC27 (1 << 27) /**< \brief Pin Controlled by PC27 */ -#define PIO_PC28 (1 << 28) /**< \brief Pin Controlled by PC28 */ -#define PIO_PC29 (1 << 29) /**< \brief Pin Controlled by PC29 */ -#define PIO_PC30 (1 << 30) /**< \brief Pin Controlled by PC30 */ -#define PIO_PC31 (1 << 31) /**< \brief Pin Controlled by PC31 */ -/* ========== Pio definition for HSMCI peripheral ========== */ -#define PIO_PA28C_MCCDA (1 << 28) /**< \brief Hsmci signal: MCCDA */ -#define PIO_PA29C_MCCK (1 << 29) /**< \brief Hsmci signal: MCCK */ -#define PIO_PA30C_MCDA0 (1 << 30) /**< \brief Hsmci signal: MCDA0 */ -#define PIO_PA31C_MCDA1 (1 << 31) /**< \brief Hsmci signal: MCDA1 */ -#define PIO_PA26C_MCDA2 (1 << 26) /**< \brief Hsmci signal: MCDA2 */ -#define PIO_PA27C_MCDA3 (1 << 27) /**< \brief Hsmci signal: MCDA3 */ -/* ========== Pio definition for SSC peripheral ========== */ -#define PIO_PA18A_RD (1 << 18) /**< \brief Ssc signal: RD */ -#define PIO_PA20A_RF (1 << 20) /**< \brief Ssc signal: RF */ -#define PIO_PA19A_RK (1 << 19) /**< \brief Ssc signal: RK */ -#define PIO_PA17A_TD (1 << 17) /**< \brief Ssc signal: TD */ -#define PIO_PA15A_TF (1 << 15) /**< \brief Ssc signal: TF */ -#define PIO_PA16A_TK (1 << 16) /**< \brief Ssc signal: TK */ -/* ========== Pio definition for SPI peripheral ========== */ -#define PIO_PA12A_MISO (1 << 12) /**< \brief Spi signal: MISO */ -#define PIO_PA13A_MOSI (1 << 13) /**< \brief Spi signal: MOSI */ -#define PIO_PA11A_NPCS0 (1 << 11) /**< \brief Spi signal: NPCS0 */ -#define PIO_PA31A_NPCS1 (1 << 31) /**< \brief Spi signal: NPCS1 */ -#define PIO_PA9B_NPCS1 (1 << 9) /**< \brief Spi signal: NPCS1 */ -#define PIO_PB14A_NPCS1 (1 << 14) /**< \brief Spi signal: NPCS1 */ -#define PIO_PC4B_NPCS1 (1 << 4) /**< \brief Spi signal: NPCS1 */ -#define PIO_PA10B_NPCS2 (1 << 10) /**< \brief Spi signal: NPCS2 */ -#define PIO_PA30B_NPCS2 (1 << 30) /**< \brief Spi signal: NPCS2 */ -#define PIO_PB2B_NPCS2 (1 << 2) /**< \brief Spi signal: NPCS2 */ -#define PIO_PA22B_NPCS3 (1 << 22) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA3B_NPCS3 (1 << 3) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA5B_NPCS3 (1 << 5) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA14A_SPCK (1 << 14) /**< \brief Spi signal: SPCK */ -/* ========== Pio definition for TC0 peripheral ========== */ -#define PIO_PA4B_TCLK0 (1 << 4) /**< \brief Tc0 signal: TCLK0 */ -#define PIO_PA28B_TCLK1 (1 << 28) /**< \brief Tc0 signal: TCLK1 */ -#define PIO_PA29B_TCLK2 (1 << 29) /**< \brief Tc0 signal: TCLK2 */ -#define PIO_PA0B_TIOA0 (1 << 0) /**< \brief Tc0 signal: TIOA0 */ -#define PIO_PA15B_TIOA1 (1 << 15) /**< \brief Tc0 signal: TIOA1 */ -#define PIO_PA26B_TIOA2 (1 << 26) /**< \brief Tc0 signal: TIOA2 */ -#define PIO_PA1B_TIOB0 (1 << 1) /**< \brief Tc0 signal: TIOB0 */ -#define PIO_PA16B_TIOB1 (1 << 16) /**< \brief Tc0 signal: TIOB1 */ -#define PIO_PA27B_TIOB2 (1 << 27) /**< \brief Tc0 signal: TIOB2 */ -/* ========== Pio definition for TC1 peripheral ========== */ -#define PIO_PC25B_TCLK3 (1 << 25) /**< \brief Tc1 signal: TCLK3 */ -#define PIO_PC28B_TCLK4 (1 << 28) /**< \brief Tc1 signal: TCLK4 */ -#define PIO_PC31B_TCLK5 (1 << 31) /**< \brief Tc1 signal: TCLK5 */ -#define PIO_PC23B_TIOA3 (1 << 23) /**< \brief Tc1 signal: TIOA3 */ -#define PIO_PC26B_TIOA4 (1 << 26) /**< \brief Tc1 signal: TIOA4 */ -#define PIO_PC29B_TIOA5 (1 << 29) /**< \brief Tc1 signal: TIOA5 */ -#define PIO_PC24B_TIOB3 (1 << 24) /**< \brief Tc1 signal: TIOB3 */ -#define PIO_PC27B_TIOB4 (1 << 27) /**< \brief Tc1 signal: TIOB4 */ -#define PIO_PC30B_TIOB5 (1 << 30) /**< \brief Tc1 signal: TIOB5 */ -/* ========== Pio definition for TWI0 peripheral ========== */ -#define PIO_PA4A_TWCK0 (1 << 4) /**< \brief Twi0 signal: TWCK0 */ -#define PIO_PA3A_TWD0 (1 << 3) /**< \brief Twi0 signal: TWD0 */ -/* ========== Pio definition for TWI1 peripheral ========== */ -#define PIO_PB5A_TWCK1 (1 << 5) /**< \brief Twi1 signal: TWCK1 */ -#define PIO_PB4A_TWD1 (1 << 4) /**< \brief Twi1 signal: TWD1 */ -/* ========== Pio definition for PWM peripheral ========== */ -#define PIO_PA9C_PWMFI0 (1 << 9) /**< \brief Pwm signal: PWMFI0 */ -#define PIO_PA0A_PWMH0 (1 << 0) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA11B_PWMH0 (1 << 11) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA23B_PWMH0 (1 << 23) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PB0A_PWMH0 (1 << 0) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PC18B_PWMH0 (1 << 18) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA1A_PWMH1 (1 << 1) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA12B_PWMH1 (1 << 12) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA24B_PWMH1 (1 << 24) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PB1A_PWMH1 (1 << 1) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PC19B_PWMH1 (1 << 19) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA13B_PWMH2 (1 << 13) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA2A_PWMH2 (1 << 2) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA25B_PWMH2 (1 << 25) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PB4B_PWMH2 (1 << 4) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PC20B_PWMH2 (1 << 20) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA14B_PWMH3 (1 << 14) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA17C_PWMH3 (1 << 17) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA7B_PWMH3 (1 << 7) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PB14B_PWMH3 (1 << 14) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC21B_PWMH3 (1 << 21) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA19B_PWML0 (1 << 19) /**< \brief Pwm signal: PWML0 */ -#define PIO_PB5B_PWML0 (1 << 5) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC0B_PWML0 (1 << 0) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC13B_PWML0 (1 << 13) /**< \brief Pwm signal: PWML0 */ -#define PIO_PA20B_PWML1 (1 << 20) /**< \brief Pwm signal: PWML1 */ -#define PIO_PB12A_PWML1 (1 << 12) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC1B_PWML1 (1 << 1) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC15B_PWML1 (1 << 15) /**< \brief Pwm signal: PWML1 */ -#define PIO_PA16C_PWML2 (1 << 16) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA30A_PWML2 (1 << 30) /**< \brief Pwm signal: PWML2 */ -#define PIO_PB13A_PWML2 (1 << 13) /**< \brief Pwm signal: PWML2 */ -#define PIO_PC2B_PWML2 (1 << 2) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA15C_PWML3 (1 << 15) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC22B_PWML3 (1 << 22) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC3B_PWML3 (1 << 3) /**< \brief Pwm signal: PWML3 */ -/* ========== Pio definition for USART0 peripheral ========== */ -#define PIO_PA8A_CTS0 (1 << 8) /**< \brief Usart0 signal: CTS0 */ -#define PIO_PA7A_RTS0 (1 << 7) /**< \brief Usart0 signal: RTS0 */ -#define PIO_PA5A_RXD0 (1 << 5) /**< \brief Usart0 signal: RXD0 */ -#define PIO_PA2B_SCK0 (1 << 2) /**< \brief Usart0 signal: SCK0 */ -#define PIO_PA6A_TXD0 (1 << 6) /**< \brief Usart0 signal: TXD0 */ -/* ========== Pio definition for USART1 peripheral ========== */ -#define PIO_PA25A_CTS1 (1 << 25) /**< \brief Usart1 signal: CTS1 */ -#define PIO_PA26A_DCD1 (1 << 26) /**< \brief Usart1 signal: DCD1 */ -#define PIO_PA28A_DSR1 (1 << 28) /**< \brief Usart1 signal: DSR1 */ -#define PIO_PA27A_DTR1 (1 << 27) /**< \brief Usart1 signal: DTR1 */ -#define PIO_PA29A_RI1 (1 << 29) /**< \brief Usart1 signal: RI1 */ -#define PIO_PA24A_RTS1 (1 << 24) /**< \brief Usart1 signal: RTS1 */ -#define PIO_PA21A_RXD1 (1 << 21) /**< \brief Usart1 signal: RXD1 */ -#define PIO_PA23A_SCK1 (1 << 23) /**< \brief Usart1 signal: SCK1 */ -#define PIO_PA22A_TXD1 (1 << 22) /**< \brief Usart1 signal: TXD1 */ -/* ========== Pio definition for ADC peripheral ========== */ -#define PIO_PA17X1_AD0 (1 << 17) /**< \brief Adc signal: AD0 */ -#define PIO_PA18X1_AD1 (1 << 18) /**< \brief Adc signal: AD1 */ -#define PIO_PC13X1_AD10 (1 << 13) /**< \brief Adc signal: AD10 */ -#define PIO_PC15X1_AD11 (1 << 15) /**< \brief Adc signal: AD11 */ -#define PIO_PC12X1_AD12 (1 << 12) /**< \brief Adc signal: AD12 */ -#define PIO_PC29X1_AD13 (1 << 29) /**< \brief Adc signal: AD13 */ -#define PIO_PC30X1_AD14 (1 << 30) /**< \brief Adc signal: AD14 */ -#define PIO_PA19X1_AD2 (1 << 19) /**< \brief Adc signal: AD2 */ -#define PIO_PA20X1_AD3 (1 << 20) /**< \brief Adc signal: AD3 */ -#define PIO_PB0X1_AD4 (1 << 0) /**< \brief Adc signal: AD4 */ -#define PIO_PB1X1_AD5 (1 << 1) /**< \brief Adc signal: AD5 */ -#define PIO_PB2X1_AD6 (1 << 2) /**< \brief Adc signal: AD6 */ -#define PIO_PB3X1_AD7 (1 << 3) /**< \brief Adc signal: AD7 */ -#define PIO_PA21X1_AD8 (1 << 21) /**< \brief Adc signal: AD8 */ -#define PIO_PA22X1_AD9 (1 << 22) /**< \brief Adc signal: AD9 */ -#define PIO_PA8B_ADTRG (1 << 8) /**< \brief Adc signal: ADTRG */ -/* ========== Pio definition for DACC peripheral ========== */ -#define PIO_PB13X1_DAC0 (1 << 13) /**< \brief Dacc signal: DAC0 */ -#define PIO_PB14X1_DAC1 (1 << 14) /**< \brief Dacc signal: DAC1 */ -#define PIO_PA2C_DATRG (1 << 2) /**< \brief Dacc signal: DATRG */ -/* ========== Pio definition for PMC peripheral ========== */ -#define PIO_PA6B_PCK0 (1 << 6) /**< \brief Pmc signal: PCK0 */ -#define PIO_PB13B_PCK0 (1 << 13) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA17B_PCK1 (1 << 17) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA21B_PCK1 (1 << 21) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA18B_PCK2 (1 << 18) /**< \brief Pmc signal: PCK2 */ -#define PIO_PA31B_PCK2 (1 << 31) /**< \brief Pmc signal: PCK2 */ -#define PIO_PB3B_PCK2 (1 << 3) /**< \brief Pmc signal: PCK2 */ -/* ========== Pio definition for UART0 peripheral ========== */ -#define PIO_PA9A_URXD0 (1 << 9) /**< \brief Uart0 signal: URXD0 */ -#define PIO_PA10A_UTXD0 (1 << 10) /**< \brief Uart0 signal: UTXD0 */ -/* ========== Pio definition for UART1 peripheral ========== */ -#define PIO_PB2A_URXD1 (1 << 2) /**< \brief Uart1 signal: URXD1 */ -#define PIO_PB3A_UTXD1 (1 << 3) /**< \brief Uart1 signal: UTXD1 */ -/* ========== Pio definition for PIOA peripheral ========== */ -#define PIO_PA24X1_PIODC0 (1 << 24) /**< \brief Pioa signal: PIODC0 */ -#define PIO_PA25X1_PIODC1 (1 << 25) /**< \brief Pioa signal: PIODC1 */ -#define PIO_PA26X1_PIODC2 (1 << 26) /**< \brief Pioa signal: PIODC2 */ -#define PIO_PA27X1_PIODC3 (1 << 27) /**< \brief Pioa signal: PIODC3 */ -#define PIO_PA28X1_PIODC4 (1 << 28) /**< \brief Pioa signal: PIODC4 */ -#define PIO_PA29X1_PIODC5 (1 << 29) /**< \brief Pioa signal: PIODC5 */ -#define PIO_PA30X1_PIODC6 (1 << 30) /**< \brief Pioa signal: PIODC6 */ -#define PIO_PA31X1_PIODC7 (1 << 31) /**< \brief Pioa signal: PIODC7 */ -#define PIO_PA23X1_PIODCCLK (1 << 23) /**< \brief Pioa signal: PIODCCLK */ -#define PIO_PA15X1_PIODCEN1 (1 << 15) /**< \brief Pioa signal: PIODCEN1 */ -#define PIO_PA16X1_PIODCEN2 (1 << 16) /**< \brief Pioa signal: PIODCEN2 */ -/*@}*/ - -/* ***************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ - -#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */ -#define AT91C_IFLASH (0x00400000) /**< Internal Flash base address */ -#define AT91C_IROM (0x00800000) /**< Internal ROM base address */ -#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */ -#define AT91C_EBI_CS0 (0x60000000) /**< EBI Chip Select 0 base address */ -#define AT91C_EBI_CS1 (0x61000000) /**< EBI Chip Select 1 base address */ -#define AT91C_EBI_CS2 (0x62000000) /**< EBI Chip Select 2 base address */ -#define AT91C_EBI_CS3 (0x63000000) /**< EBI Chip Select 3 base address */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif // _AT91SAM3S4_H_ diff --git a/radio/src/targets/sky9x/CMakeLists.txt b/radio/src/targets/sky9x/CMakeLists.txt deleted file mode 100644 index 04185fd03..000000000 --- a/radio/src/targets/sky9x/CMakeLists.txt +++ /dev/null @@ -1,151 +0,0 @@ -set(ARCH ARM) -set(LUA NO) -set(MCU cortex-m3) -set(SDCARD YES) -set(HAPTIC YES) -set(STORAGE EEPROM) -set(STORAGE_FORMAT RAW) -set(GUI_DIR 128x64) -set(BITMAPS_DIR 128x64) -set(NAVIGATION_TYPE 9x) -set(BITMAPS_TARGET 9x_bitmaps) -set(TARGET_DIR sky9x) -set(RADIO_DEPENDENCIES ${RADIO_DEPENDENCIES} 9x_bitmaps) -set(PPM_LIMITS_SYMETRICAL YES) -set(PXX1 YES) -set(AFHDS3 NO) -set(GHOST NO) -add_definitions(-DHARDWARE_EXTERNAL_MODULE) -add_definitions(-DDISABLE_MULTI_UPDATE) - -if(PCB STREQUAL 9XRPRO) - add_definitions(-Dat91sam3s8 -DREVX) - set(FLAVOUR 9xrpro) - set(LINKER_SCRIPT targets/sky9x/sam3s8c_flash.ld) - set(FIRMWARE_TARGET_SRC - ${FIRMWARE_TARGET_SRC} - rtc_driver.cpp - ) - set(OPENRC_BOOTLOADER bootflash8.lbm) - set(CPU_TYPE_FULL ATSAM3S8C) # for size report -elseif(PCB STREQUAL AR9X) - add_definitions(-Dat91sam3s8 -DPCBAR9X -DSOFTWARE_VOLUME) - set(FLAVOUR ar9x) - include_directories(${THIRDPARTY_DIR}/xdk-asf-3.31.0/sam/drivers/twi) - set(FIRMWARE_TARGET_SRC - ${FIRMWARE_TARGET_SRC} - ../../${THIRDPARTY_DIR}/xdk-asf-3.31.0/sam/drivers/twi/twi.c - i2c_driver.cpp - rtc_ds3231_driver.cpp - ) - set(LINKER_SCRIPT targets/sky9x/sam3s8c_flash.ld) - set(OPENRC_BOOTLOADER bootflash8.lbm) - set(CPU_TYPE_FULL ATSAM3S8C) # for size report -else() - set(FLAVOUR sky9x) - set(PCBREV "REVC" CACHE STRING "PCB Revision (REVB/REVC)") - set_property(CACHE PCBREV PROPERTY STRINGS "REVB" "REVC") - set(FIRMWARE_TARGET_SRC - ${FIRMWARE_TARGET_SRC} - coproc_driver.cpp - rotary_encoder_driver.cpp - rtc_driver.cpp - ) - set(OPENRC_BOOTLOADER bootflash4.lbm) - if(PCBREV STREQUAL REVB) - add_definitions(-DDREVB) - elseif(PCBREV STREQUAL REVC) - add_definitions(-DDREVC) - else() - message(SEND_ERROR "Unknown PCB Revision '${PCBREV}'") - endif() - add_definitions(-DCOPROCESSOR) - set(LINKER_SCRIPT targets/sky9x/sam3s4c_flash.ld) - set(CPU_TYPE_FULL ATSAM3S4C) # for size report -endif() - -add_definitions(-DPCBSKY9X -DPPM_PIN_SERIAL -DAUDIO_DUAL_BUFFER) -add_definitions(-DAUDIO -DVOICE -DRTCLOCK -DVARIO) -add_definitions(-DEEPROM_VARIANT=0) - -set(GUI_SRC - ${GUI_SRC} - model_input_edit.cpp - model_mix_edit.cpp - model_display.cpp - radio_diagkeys.cpp - radio_diaganas.cpp - view_telemetry.cpp - view_about.cpp - view_channels.cpp - ) - -if(GVARS) - set(GUI_SRC - ${GUI_SRC} - model_gvars.cpp - ) -endif() - -set(FIRMWARE_TARGET_SRC - ${FIRMWARE_TARGET_SRC} - ../common/arm/loadboot.cpp - board.cpp - core_cm3.c - board_lowlevel.c - crt.c - vectors_sam3s.c - eeprom_driver.cpp - lcd_driver.cpp - pwr_driver.cpp - joystick.cpp - massstorage.cpp - keys_driver.cpp - usb/device/core/USBD_UDP.c - usb/device/core/USBDDriver.c - usb_driver.cpp - usb/device/massstorage/MSDDriver.c - usb/device/massstorage/MSDDStateMachine.c - usb/device/massstorage/MSDLun.c - usb/device/massstorage/MSDDriverDescriptors.c - usb/device/massstorage/SBCMethods.c - usb/device/hid-joystick/HIDDJoystickDriver.c - usb/device/hid-joystick/HIDDJoystickDriverDescriptors.c - usb/device/hid-joystick/HIDDJoystickInputReport.c - usb/common/core/USBEndpointDescriptor.c - usb/common/core/USBGenericRequest.c - usb/common/core/USBFeatureRequest.c - usb/common/core/USBInterfaceRequest.c - usb/common/core/USBGetDescriptorRequest.c - usb/common/core/USBSetAddressRequest.c - usb/common/core/USBSetConfigurationRequest.c - usb/common/core/USBConfigurationDescriptor.c - usb/common/core/USBGenericDescriptor.c - usb/common/hid/HIDIdleRequest.c - usb/common/hid/HIDReportRequest.c - MEDSdcard.c - ) - -set(FIRMWARE_TARGET_SRC - ${FIRMWARE_TARGET_SRC} - telemetry_driver.cpp - ) - -set(TARGET_SRC - ${TARGET_SRC} - adc_driver.cpp - pulses_driver.cpp - audio_driver.cpp - buzzer_driver.cpp - haptic_driver.cpp - sdcard_driver.cpp - aux_serial_driver.cpp - audio_driver.cpp - trainer_driver.cpp - ) - -set(SRC - ${SRC} - debug.cpp - ) - diff --git a/radio/src/targets/sky9x/MEDSdcard.c b/radio/src/targets/sky9x/MEDSdcard.c deleted file mode 100644 index 07324917d..000000000 --- a/radio/src/targets/sky9x/MEDSdcard.c +++ /dev/null @@ -1,246 +0,0 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include -#include "debug.h" -#include "diskio.h" -#include "board_lowlevel.h" -#include "Media.h" - -//------------------------------------------------------------------------------ -// Constants -//------------------------------------------------------------------------------ - -/// Number of SD Slots -#define NUM_SD_SLOTS 1 - -//------------------------------------------------------------------------------ -/// Checks if the device is write protected. -/// \return 1 if protected. -//------------------------------------------------------------------------------ -#if 0 -static unsigned char CardIsProtected(unsigned char slot) -{ - if (slot == 0) { - #ifdef BOARD_SD_PIN_WP - PIO_Configure(&pinMciWriteProtect, 1); - return (PIO_Get(&pinMciWriteProtect) != 0); - #else - return 0; - #endif - } - - if (slot == 1) { - #ifdef BOARD_SD_MCI1_PIN_WP - PIO_Configure(&pinMciWriteProtect1, 1); - return (PIO_Get(&pinMciWriteProtect1) != 0); - #else - return 0; - #endif - } - - return 0; -} -#endif - -//------------------------------------------------------------------------------ -/// Configure the PIO for SD -//------------------------------------------------------------------------------ -#if 0 -static void ConfigurePIO(unsigned char mciID) -{ - #ifdef BOARD_SD_PINS - const Pin pinSd0[] = {BOARD_SD_PINS}; - #endif - - #ifdef BOARD_SD_MCI1_PINS - const Pin pinSd1[] = {BOARD_SD_MCI1_PINS}; - #endif - - if(mciID == 0) { - #ifdef BOARD_SD_PINS - PIO_Configure(pinSd0, PIO_LISTSIZE(pinSd0)); - #endif - } else { - #ifdef BOARD_SD_MCI1_PINS - PIO_Configure(pinSd1, PIO_LISTSIZE(pinSd1)); - #endif - } -} -#endif - -//------------------------------------------------------------------------------ -//! \brief Reads a specified amount of data from a SDCARD memory -//! \param media Pointer to a Media instance -//! \param address Address of the data to read -//! \param data Pointer to the buffer in which to store the retrieved -//! data -//! \param length Length of the buffer -//! \param callback Optional pointer to a callback function to invoke when -//! the operation is finished -//! \param argument Optional pointer to an argument for the callback -//! \return Operation result code -//------------------------------------------------------------------------------ -static unsigned char MEDSdcard_Read(Media *media, - unsigned int address, - void *data, - unsigned int length, - MediaCallback callback, - void *argument) -{ - TRACE_DEBUG("MEDSdcard_Read(address=%d length=%d)\n\r", address, length); - - // Check that the media is ready - if (media->state != MED_STATE_READY) { - - TRACE_INFO("Media busy\n\r"); - return MED_STATUS_BUSY; - } - - // Check that the data to read is not too big - if ((length + address) > media->size) { - - TRACE_WARNING("MEDSdcard_Read: Data too big: %d, %d\n\r", - (int)length, (int)address); - return MED_STATUS_ERROR; - } - - // Enter Busy state - media->state = MED_STATE_BUSY; - - disk_read (0, data, address, length); - - // Leave the Busy state - media->state = MED_STATE_READY; - - // Invoke callback - if (callback != 0) { - - callback(argument, MED_STATUS_SUCCESS, 0, 0); - } - - return MED_STATUS_SUCCESS; -} - -//------------------------------------------------------------------------------ -//! \brief Writes data on a SDRAM media -//! \param media Pointer to a Media instance -//! \param address Address at which to write -//! \param data Pointer to the data to write -//! \param length Size of the data buffer -//! \param callback Optional pointer to a callback function to invoke when -//! the write operation terminates -//! \param argument Optional argument for the callback function -//! \return Operation result code -//! \see Media -//! \see MediaCallback -//------------------------------------------------------------------------------ -static unsigned char MEDSdcard_Write(Media *media, - unsigned int address, - void *data, - unsigned int length, - MediaCallback callback, - void *argument) -{ - - TRACE_DEBUG("MEDSdcard_Write(address=%d length=%d)\n\r", address, length); - - // Check that the media if ready - if (media->state != MED_STATE_READY) { - - TRACE_WARNING("MEDSdcard_Write: Media is busy\n\r"); - return MED_STATUS_BUSY; - } - - // Check that the data to write is not too big - if ((length + address) > media->size) { - - TRACE_WARNING("MEDSdcard_Write: Data too big\n\r"); - return MED_STATUS_ERROR; - } - - // Put the media in Busy state - media->state = MED_STATE_BUSY; - - disk_write(0, data, address, length); - - // Leave the Busy state - media->state = MED_STATE_READY; - - // Invoke the callback if it exists - if (callback != 0) { - - callback(argument, MED_STATUS_SUCCESS, 0, 0); - } - - return MED_STATUS_SUCCESS; -} - - -//------------------------------------------------------------------------------ -/// Initializes a Media instance and the associated physical interface -/// \param media Pointer to the Media instance to initialize -/// \return 1 if success. -//------------------------------------------------------------------------------ - -unsigned char MEDSdcard_Initialize(Media *media, unsigned char mciID) -{ - TRACE_INFO("MEDSdcard init\n\r"); - - // Initialize SDcard - //-------------------------------------------------------------------------- - - if ( !SD_CARD_PRESENT( ) ) - { - return 0; - } - - media->write = MEDSdcard_Write; - media->read = MEDSdcard_Read; - media->lock = 0; - media->unlock = 0; - media->handler = 0; - media->flush = 0; - - media->blockSize = BLOCK_SIZE; - media->baseAddress = 0; - - media->size = SD_GET_BLOCKNR(); - - media->mappedRD = 0; - media->mappedWR = 0; - media->protected = 0; - media->removable = 1; - - media->state = MED_STATE_READY; - - media->transfer.data = 0; - media->transfer.address = 0; - media->transfer.length = 0; - media->transfer.callback = 0; - media->transfer.argument = 0; - - return 1; -} - diff --git a/radio/src/targets/sky9x/Media.h b/radio/src/targets/sky9x/Media.h deleted file mode 100644 index 78d54948a..000000000 --- a/radio/src/targets/sky9x/Media.h +++ /dev/null @@ -1,280 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Generic Media type, which provides transparent access to all types of -/// memories. -/// -/// \note The physical or HW related media operations (physical device -/// connection & protection detecting, PIO configurations and interface -/// driver initialization) are excluded. -/// -/// !Usage -/// -# Do PIO initialization for peripheral interfaces. -/// -# Initialize peripheral interface driver & device driver. -/// -# Initialize specific media interface and link to this initialized driver. -/// -//------------------------------------------------------------------------------ - -#ifndef _MEDIA_H_ -#define _MEDIA_H_ - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//! \brief Operation result code returned by media methods -#define MED_STATUS_SUCCESS 0x00 -#define MED_STATUS_ERROR 0x01 -#define MED_STATUS_BUSY 0x02 -#define MED_STATUS_PROTECTED 0x04 - -//! \brief Media statuses -#define MED_STATE_READY 0x00 /// Media is ready for access -#define MED_STATE_BUSY 0x01 /// Media is busy - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ -typedef struct _Media Media; - -typedef void (*MediaCallback)(void *argument, - unsigned char status, - unsigned int transferred, - unsigned int remaining); - -typedef unsigned char (*Media_write)(Media *media, - unsigned int address, - void *data, - unsigned int length, - MediaCallback callback, - void *argument); - -typedef unsigned char (*Media_read)(Media *media, - unsigned int address, - void *data, - unsigned int length, - MediaCallback callback, - void *argument); - -typedef unsigned char (*Media_cancelIo)(Media *media); - -typedef unsigned char (*Media_lock)(Media *media, - unsigned int start, - unsigned int end, - unsigned int *pActualStart, - unsigned int *pActualEnd); - -typedef unsigned char (*Media_unlock)(Media *media, - unsigned int start, - unsigned int end, - unsigned int *pActualStart, - unsigned int *pActualEnd); - -typedef unsigned char (*Media_ioctl)(Media *media, - unsigned char ctrl, - void *buff); - -typedef unsigned char (*Media_flush)(Media *media); - -typedef void (*Media_handler)(Media *media); - -//! \brief Media transfer -//! \see TransferCallback -typedef struct { - - void *data; //!< Pointer to the data buffer - unsigned int address; //!< Address where to read/write the data - unsigned int length; //!< Size of the data to read/write - MediaCallback callback; //!< Callback to invoke when the transfer done - void *argument; //!< Callback argument - -} MEDTransfer; - -//! \brief Media object -//! \see MEDTransfer -struct _Media { - - Media_write write; //!< Write method - Media_read read; //!< Read method - Media_cancelIo cancelIo; //!< Cancel pending IO method - Media_lock lock; //!< lock method if possible - Media_unlock unlock; //!< unlock method if possible - Media_flush flush; //!< Flush method - Media_handler handler; //!< Interrupt handler - unsigned int blockSize; //!< Block size in bytes (1, 512, 1K, 2K ...) - unsigned int baseAddress; //!< Base address of media in number of blocks - unsigned int size; //!< Size of media in number of blocks - MEDTransfer transfer; //!< Current transfer operation - void *interface; //!< Pointer to the physical interface used - unsigned char bReserved:4, - mappedRD:1, //!< Mapped to memory space to read - mappedWR:1, //!< Mapped to memory space to write -#ifdef __cplusplus - protectd:1, //!< Protected media? -#else - protected:1, //!< Protected media? -#endif - removable:1; //!< Removable/Fixed media? - unsigned char state; //!< Status of media - unsigned short reserved; -}; - -/// Available medias. -extern Media medias[]; - -/// Number of medias which are effectively used. -/// Defined by Media, shared usage by USB MSD & FS ... -extern unsigned int numMedias; - -//------------------------------------------------------------------------------ -// Inline Functions -//------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -//! \brief Writes data on a media -//! \param media Pointer to a Media instance -//! \param address Address at which to write -//! \param data Pointer to the data to write -//! \param length Size of the data buffer -//! \param callback Optional pointer to a callback function to invoke when -//! the write operation terminates -//! \param argument Optional argument for the callback function -//! \return Operation result code -//! \see TransferCallback -//------------------------------------------------------------------------------ -static inline unsigned char MED_Write(Media *media, - unsigned int address, - void *data, - unsigned int length, - MediaCallback callback, - void *argument) -{ - return media->write(media, address, data, length, callback, argument); -} - -//------------------------------------------------------------------------------ -//! \brief Reads a specified amount of data from a media -//! \param media Pointer to a Media instance -//! \param address Address of the data to read -//! \param data Pointer to the buffer in which to store the retrieved -//! data -//! \param length Length of the buffer -//! \param callback Optional pointer to a callback function to invoke when -//! the operation is finished -//! \param argument Optional pointer to an argument for the callback -//! \return Operation result code -//! \see TransferCallback -//------------------------------------------------------------------------------ -static inline unsigned char MED_Read(Media *media, - unsigned int address, - void *data, - unsigned int length, - MediaCallback callback, - void *argument) -{ - return media->read(media, address, data, length, callback, argument); -} - -//------------------------------------------------------------------------------ -//! \brief Locks all the regions in the given address range. -//! \param media Pointer to a Media instance -/// \param start Start address of lock range. -/// \param end End address of lock range. -/// \param pActualStart Start address of the actual lock range (optional). -/// \param pActualEnd End address of the actual lock range (optional). -/// \return 0 if successful; otherwise returns an error code. -//------------------------------------------------------------------------------ -static inline unsigned char MED_Lock(Media *media, - unsigned int start, - unsigned int end, - unsigned int *pActualStart, - unsigned int *pActualEnd) -{ - if( media->lock ) { - return media->lock(media, start, end, pActualStart, pActualEnd); - } - else { - return MED_STATUS_SUCCESS; - } -} - -//------------------------------------------------------------------------------ -//! \brief Unlocks all the regions in the given address range -//! \param media Pointer to a Media instance -/// \param start Start address of unlock range. -/// \param end End address of unlock range. -/// \param pActualStart Start address of the actual unlock range (optional). -/// \param pActualEnd End address of the actual unlock range (optional). -/// \return 0 if successful; otherwise returns an error code. -//------------------------------------------------------------------------------ -static inline unsigned char MED_Unlock(Media *media, - unsigned int start, - unsigned int end, - unsigned int *pActualStart, - unsigned int *pActualEnd) -{ - if( media->unlock ) { - return media->unlock(media, start, end, pActualStart, pActualEnd); - } - else { - return MED_STATUS_SUCCESS; - } -} - -//------------------------------------------------------------------------------ -//! \brief -//! \param media Pointer to the Media instance to use -//------------------------------------------------------------------------------ -static inline unsigned char MED_Flush(Media *media) -{ - if (media->flush) { - - return media->flush(media); - } - else { - - return MED_STATUS_SUCCESS; - } -} - -//------------------------------------------------------------------------------ -//! \brief Invokes the interrupt handler of the specified media -//! \param media Pointer to the Media instance to use -//------------------------------------------------------------------------------ -static inline void MED_Handler(Media *media) -{ - if (media->handler) { - - media->handler(media); - } -} - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern void MED_HandleAll(Media *medias, unsigned char numMedias); - -#endif // _MEDIA_H_ - diff --git a/radio/src/targets/sky9x/adc_driver.cpp b/radio/src/targets/sky9x/adc_driver.cpp deleted file mode 100644 index d947ce842..000000000 --- a/radio/src/targets/sky9x/adc_driver.cpp +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -uint16_t adcValues[NUM_ANALOGS]; - -#if defined(FRSKY_STICKS) -const char ana_direction[NUM_ANALOGS] = {1, 1, 0, 1 ,0 ,1 ,0, 0, 0}; -#endif - - -// Settings for mode register ADC_MR -// USEQ off - silicon problem, doesn't work -// TRANSFER = 3 -// TRACKTIM = 15 (16 clock periods) -// ANACH = 1 -// SETTLING = 6 (not used if ANACH = 0) -// STARTUP = 6 (96 clock periods) -// PRESCAL = 9.0 MHz clock (between 1 and 20MHz) -// FREERUN = 0 -// FWUP = 0 -// SLEEP = 0 -// LOWRES = 0 -// TRGSEL = 0 -// TRGEN = 0 (software trigger only) -void adcInit() -{ - Adc *padc ; - uint32_t timer ; - - timer = ( Master_frequency / (3600000*2) ) << 8 ; - // Enable peripheral clock ADC = bit 29 - PMC->PMC_PCER0 |= 0x20000000L ; // Enable peripheral clock to ADC - padc = ADC ; - padc->ADC_MR = 0x3FB60000 | timer ; // 0011 1111 1011 0110 xxxx xxxx 0000 0000 - padc->ADC_ACR = ADC_ACR_TSON ; // Turn on temp sensor - padc->ADC_CHER = 0x0000E33E ; // channels 1,2,3,4,5,8,9,13,14,15 - padc->ADC_CGR = 0 ; // Gain = 1, all channels - padc->ADC_COR = 0 ; // Single ended, 0 offset, all channels -} - -// Read 8 (9 for REVB) ADC channels -// Documented bug, must do them 1 by 1 -void adcSingleRead() -{ - Adc *padc; - uint32_t y; - uint32_t x; - - for (uint8_t i=0; i<4; i++) - padc = ADC; - y = padc->ADC_ISR; // Clear EOC flags - for (y = NUM_ANALOGS+1; --y > 0;) { - padc->ADC_CR = 2; // Start conversion - x = 0; - while ((padc->ADC_ISR & 0x01000000) == 0) { - // wait for DRDY flag - if (++x > 1000000) { - break; // Software timeout - } - } - x = padc->ADC_LCDR; // Clear DRSY flag - } - // Next bit may be done using the PDC - adcValues[0] = ADC->ADC_CDR1; - adcValues[1] = ADC->ADC_CDR2; - adcValues[2] = ADC->ADC_CDR3; - adcValues[3] = ADC->ADC_CDR4; - adcValues[4] = ADC->ADC_CDR5; - adcValues[5] = ADC->ADC_CDR9; - adcValues[6] = ADC->ADC_CDR13; - adcValues[7] = ADC->ADC_CDR14; - adcValues[8] = ADC->ADC_CDR8 ; - - // adc direction correct -#if defined(FRSKY_STICKS) - uint32_t i ; - for (i=0; i> 2; - } -} - - -#if !defined(SIMU) -uint16_t getAnalogValue(uint8_t index) -{ -#if defined(PCBSKY9X) - static const uint8_t mapping[] = {1,5,7,0,4,6,2,3}; - index = mapping[index]; -#endif - return adcValues[index]; -} -#endif // #if !defined(SIMU) diff --git a/radio/src/targets/sky9x/audio_driver.cpp b/radio/src/targets/sky9x/audio_driver.cpp deleted file mode 100644 index d6959afeb..000000000 --- a/radio/src/targets/sky9x/audio_driver.cpp +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -volatile uint8_t dacStarted = false; - -#if !defined(SIMU) - -#if !defined(SOFTWARE_VOLUME) -const int8_t volumeScale[VOLUME_LEVEL_MAX+1] = -{ - 0, 2, 4, 6, 8, 10, 13, 17, 22, 27, 33, 40, - 64, 82, 96, 105, 112, 117, 120, 122, 124, 125, 126, 127 -} ; -#endif - -void setSampleRate(uint32_t frequency) -{ - Tc *ptc ; - uint32_t timer ; - - timer = Master_frequency / (8 * frequency) ; // MCK/8 and 100 000 Hz - if (timer > 65535) - timer = 65535 ; - if (timer < 2) - timer = 2 ; - - ptc = TC0 ; // Tc block 0 (TC0-2) - ptc->TC_CHANNEL[1].TC_CCR = TC_CCR0_CLKDIS ; // Stop clock - ptc->TC_CHANNEL[1].TC_RC = timer ; // 100 000 Hz - ptc->TC_CHANNEL[1].TC_RA = timer >> 1 ; - ptc->TC_CHANNEL[1].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) -} - -// Start TIMER1 at 100000Hz, used for DACC trigger -void dacTimerStart() -{ - Tc *ptc ; - uint32_t timer ; - - // Enable peripheral clock TC0 = bit 23 thru TC5 = bit 28 - PMC->PMC_PCER0 |= 0x01000000L ; // Enable peripheral clock to TC1 - - timer = Master_frequency / 800000 ; // MCK/8 and 100 000 Hz - ptc = TC0 ; // Tc block 0 (TC0-2) - ptc->TC_BCR = 0 ; // No sync - ptc->TC_BMR = 0 ; - ptc->TC_CHANNEL[1].TC_CMR = 0x00008000 ; // Waveform mode - ptc->TC_CHANNEL[1].TC_RC = timer ; // 100 000 Hz - ptc->TC_CHANNEL[1].TC_RA = timer >> 1 ; - ptc->TC_CHANNEL[1].TC_CMR = 0x0009C001 ; // 0000 0000 0000 1001 1100 0000 0000 0001 - // MCK/8, set @ RA, Clear @ RC waveform - ptc->TC_CHANNEL[1].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) - // Sound_g.Frequency = 1000 ; -} - -// Configure DAC0 -// Not sure why PB14 has not be allocated to the DAC, although it is an EXTRA function -// So maybe it is automatically done -void dacInit() -{ - dacTimerStart() ; - - PMC->PMC_PCER0 |= 0x40000000L ; // Enable peripheral clock to DAC - - Dacc *dacptr = DACC; - - dacptr->DACC_MR = 0x0B000215L ; // 0000 1011 0000 0001 0000 0010 0001 0101 - dacptr->DACC_CHER = 1 ; // Enable channel 0 - dacptr->DACC_CDR = 2048 ; // Half amplitude - dacptr->DACC_PTCR = DACC_PTCR_TXTEN ; - - NVIC_EnableIRQ(DACC_IRQn) ; -} - -inline void dacStart() -{ - PMC->PMC_PCER0 |= 0x40000000L ; // Enable peripheral clock to DAC - DACC->DACC_IER = DACC_IER_ENDTX ; - dacStarted = true; -} - -inline void dacStop() -{ - DACC->DACC_IDR = DACC_IDR_ENDTX ; // Disable interrupt - dacStarted = false; -} - -void audioConsumeCurrentBuffer() -{ - if (!dacStarted) { - dacStart(); - } -} - - -extern "C" void DAC_IRQHandler() -{ - uint32_t sr = DACC->DACC_ISR; - if (sr & DACC_ISR_ENDTX) { - audioQueue.buffersFifo.freeNextFilledBuffer(); - const AudioBuffer * nextBuffer = audioQueue.buffersFifo.getNextFilledBuffer(); - if (nextBuffer) { - // Try the first PDC buffer - if ((DACC->DACC_TCR == 0) && (DACC->DACC_TNCR == 0)) { - DACC->DACC_TPR = CONVERT_PTR_UINT(nextBuffer->data); - DACC->DACC_TCR = nextBuffer->size/2; - DACC->DACC_PTCR = DACC_PTCR_TXTEN; - return; - } - // Try the second PDC buffer - if (DACC->DACC_TNCR == 0) { - DACC->DACC_TNPR = CONVERT_PTR_UINT(nextBuffer->data); - DACC->DACC_TNCR = nextBuffer->size/2; - DACC->DACC_PTCR = DACC_PTCR_TXTEN; - return; - } - } - else { - dacStop(); - } - } -} - -// Sound routines -void audioInit() -{ - Pio * pioptr ; - - dacInit() ; - - pioptr = PIOA ; - pioptr->PIO_CODR = 0x02000000L ; // Set bit A25 OFF - pioptr->PIO_PER = 0x02000000L ; // Enable bit A25 (Stock buzzer) - pioptr->PIO_OER = 0x02000000L ; // Set bit A25 as output - -#if defined(REVX) - configure_pins( PIO_PC26, PIN_ENABLE | PIN_LOW | PIN_OUTPUT | PIN_PORTC | PIN_NO_PULLUP ) ; - PIOC->PIO_CODR = PIO_PC26 ; -#endif -} - -void audioEnd() -{ - DACC->DACC_IDR = DACC_IDR_ENDTX ; - DACC->DACC_IDR = DACC_IDR_TXBUFE ; - NVIC_DisableIRQ(DACC_IRQn) ; - TWI0->TWI_IDR = TWI_IDR_TXCOMP ; - NVIC_DisableIRQ(TWI0_IRQn) ; - PMC->PMC_PCER0 &= ~0x00080000L ; // Disable peripheral clock to TWI0 - PMC->PMC_PCER0 &= ~0x40000000L ; // Disable peripheral clock to DAC -} - -#if !defined(SOFTWARE_VOLUME) -void setScaledVolume(uint8_t volume) -{ - volumeRequired = volumeScale[min(volume, VOLUME_LEVEL_MAX)]; - __disable_irq() ; - i2cCheck() ; - __enable_irq() ; -} -#endif - -#endif // #if !defined(SIMU) - diff --git a/radio/src/targets/sky9x/audio_driver.h b/radio/src/targets/sky9x/audio_driver.h deleted file mode 100644 index 75f018dfa..000000000 --- a/radio/src/targets/sky9x/audio_driver.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _AUDIO_DRIVER_H_ -#define _AUDIO_DRIVER_H_ - -#include - -void audioInit() ; -void audioEnd() ; -void audioConsumeCurrentBuffer(); -#define audioDisableIrq() __disable_irq() -#define audioEnableIrq() __enable_irq() - -void setSampleRate( uint32_t frequency ) ; - -#define VOLUME_LEVEL_MAX 23 -#define VOLUME_LEVEL_DEF 12 - -void setScaledVolume(uint8_t volume); - -#define audioWaitReady() - -#endif // _AUDIO_DRIVER_H_ diff --git a/radio/src/targets/sky9x/aux_serial_driver.cpp b/radio/src/targets/sky9x/aux_serial_driver.cpp deleted file mode 100644 index 0ed19df61..000000000 --- a/radio/src/targets/sky9x/aux_serial_driver.cpp +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" -#include - -/** Usart Hw interface used by the console (UART0). */ -#define SECOND_SERIAL_UART UART0 -/** Usart Hw ID used by the console (UART0). */ -#define SECOND_SERIAL_ID ID_UART0 -/** Pins description corresponding to Rxd,Txd, (UART pins) */ -#define SECOND_SERIAL_PINS {PINS_UART} - -Fifo auxSerialRxFifo; - -#if !defined(SIMU) -/* - * Outputs a character on the UART line. - * - * This function is synchronous (i.e. uses polling). - * c Character to send. - */ -void auxSerialPutc(const unsigned char c) -{ - Uart *pUart = SECOND_SERIAL_UART; - - /* Wait for the transmitter to be ready */ - while ( (pUart->UART_SR & UART_SR_TXRDY) == 0 ) ; - - /* Send character */ - pUart->UART_THR = c; -} - -uint8_t auxSerialTracesEnabled() -{ - return false; -} - -/** - * Configures a UART peripheral with the specified parameters. - * - * baudrate Baudrate at which the UART should operate (in Hz). - * masterClock Frequency of the system master clock (in Hz). - * uses PA9 and PA10, RXD2 and TXD2 - */ -void SECOND_UART_Configure(uint32_t baudrate, uint32_t masterClock) -{ - Uart *pUart = SECOND_SERIAL_UART; - - /* Configure PIO */ - configure_pins( (PIO_PA9 | PIO_PA10), PIN_PERIPHERAL | PIN_INPUT | PIN_PER_A | PIN_PORTA | PIN_NO_PULLUP ) ; - - /* Configure PMC */ - PMC->PMC_PCER0 = 1 << SECOND_SERIAL_ID; - - /* Reset and disable receiver & transmitter */ - pUart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX - | UART_CR_RXDIS | UART_CR_TXDIS; - - /* Configure mode */ - pUart->UART_MR = 0x800 ; // NORMAL, No Parity - - /* Configure baudrate */ - /* Asynchronous, no oversampling */ - pUart->UART_BRGR = (masterClock / baudrate) / 16; - - /* Disable PDC channel */ - pUart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS; - - /* Enable receiver and transmitter */ - pUart->UART_CR = UART_CR_RXEN | UART_CR_TXEN; - - pUart->UART_IER = UART_IER_RXRDY; - NVIC_EnableIRQ(UART0_IRQn); -} - -void SECOND_UART_Stop() -{ - SECOND_SERIAL_UART->UART_IDR = UART_IDR_RXRDY ; - NVIC_DisableIRQ(UART0_IRQn) ; -} - -extern "C" void UART0_IRQHandler() -{ - if (SECOND_SERIAL_UART->UART_SR & UART_SR_RXRDY) { - auxSerialRxFifo.push(SECOND_SERIAL_UART->UART_RHR); - } -} - -#else -#define SECOND_UART_Configure(...) -#endif - -void auxSerialTelemetryInit(unsigned int /*protocol*/) -{ - SECOND_UART_Configure(FRSKY_D_BAUDRATE, Master_frequency); -} - -bool telemetrySecondPortReceive(uint8_t & data) -{ - return auxSerialRxFifo.pop(data); -} - -#if defined(DEBUG) && !defined(SIMU) -void serialPrintf(const char*, ... ) {} -#endif diff --git a/radio/src/targets/sky9x/bluetooth.cpp b/radio/src/targets/sky9x/bluetooth.cpp deleted file mode 100644 index 52621e426..000000000 --- a/radio/src/targets/sky9x/bluetooth.cpp +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -void btSetBaudrate(uint32_t index) -{ - uint32_t baudrate = (index==0 ? 115200 : (index==1 ? 9600 : 19200)); - UART3_Configure(baudrate, Master_frequency); -} - -void btInit() -{ - btSetBaudrate(g_eeGeneral.bluetoothBaudrate); -} - -OS_FlagID btFlag; -Fifo<32> btTxFifo; -Fifo<32> btRxFifo; - -struct t_serial_tx btTx ; -uint8_t btTxBuffer[32] ; - -struct t_serial_tx * Current_bt ; - -uint32_t txPdcBt(struct t_serial_tx *data) -{ -#ifndef SIMU - Uart *pUart = BT_USART ; - - if (pUart->UART_TNCR == 0) { - Current_bt = data; - data->ready = 1; - pUart->UART_TPR = (uint32_t) data->buffer; - pUart->UART_TCR = data->size; - pUart->UART_PTCR = US_PTCR_TXTEN; - pUart->UART_IER = UART_IER_TXBUFE; - NVIC_EnableIRQ(UART1_IRQn); - return 1; // Sent OK - } -#endif - return 0 ; // Busy -} - -extern "C" void UART1_IRQHandler() -{ - Uart *pUart = BT_USART ; - if ( pUart->UART_SR & UART_SR_TXBUFE ) { - pUart->UART_IDR = UART_IDR_TXBUFE ; - pUart->UART_PTCR = US_PTCR_TXTDIS ; - Current_bt->ready = 0 ; - } - if ( pUart->UART_SR & UART_SR_RXRDY ) { - btRxFifo.push(pUart->UART_RHR); - } -} - -uint16_t rxBtuart() -{ - uint8_t result; - if (!btRxFifo.pop(result)) - return 0xffff; - - return result; -} - -void btSendBuffer() -{ - btTx.buffer = btTxBuffer; - txPdcBt(&btTx); - while (btTx.ready == 1) { - RTOS_WAIT_TICKS(1); - } - btTx.size = 0; -} - -#define BT_POLL_TIMEOUT 500 - -uint32_t btChangeBaudrate( uint32_t baudIndex ) -{ - uint16_t x ; - uint32_t y ; - uint16_t rxchar ; - - x = 4 ; // 9600 - if ( baudIndex == 0 ) - { - x = 8 ; // 115200 - } - else if ( baudIndex == 2 ) - { - x = 5 ; // 19200 - } - btTxBuffer[0] = 'A' ; - btTxBuffer[1] = 'T' ; - btTxBuffer[2] = '+' ; - btTxBuffer[3] = 'B' ; - btTxBuffer[4] = 'A' ; - btTxBuffer[5] = 'U' ; - btTxBuffer[6] = 'D' ; - btTxBuffer[7] = '0' + x ; - btTx.size = 8 ; - btSendBuffer() ; - x = 'O' ; - for( y = 0 ; y < BT_POLL_TIMEOUT ; y += 1 ) { - if ( ( rxchar = rxBtuart() ) != 0xFFFF ) { - if ( rxchar == x ) { - if ( x == 'O' ) { - x = 'K' ; - } - else { - break ; // Found "OK" - } - } - } - else { - RTOS_WAIT_TICKS(1); - } - } - - if ( y < BT_POLL_TIMEOUT ) { - return 1 ; - } - else { - return 0 ; - } -} - -uint32_t btPollDevice() -{ - uint16_t x ; - uint32_t y ; - uint16_t rxchar ; - - x = 'O' ; - btTxBuffer[0] = 'A' ; - btTxBuffer[1] = 'T' ; - btTx.size = 2 ; - btSendBuffer() ; - - for( y = 0 ; y < BT_POLL_TIMEOUT ; y++) { - if ( ( rxchar = rxBtuart() ) != 0xFFFF ) { - if ( rxchar == x ) { - if ( x == 'O' ) { - x = 'K' ; - } - else { - break ; // Found "OK" - } - } - } - else { - RTOS_WAIT_TICKS(1) ; // 2mS - } - } - - if ( y < BT_POLL_TIMEOUT ) { - return 1 ; - } - else { - return 0 ; - } -} - -/* -Commands to BT module -AT+VERSION Returns the software version of the module -AT+BAUDx Sets the baud rate of the module: -1 1200 -2 2400 -3 4800 -4 9600 (Default) -5 19200 -6 38400 -7 57600 -8 115200 -9 230400 -AT+NAME Sets the name of the module - -Any name can be specified up to 20 characters -AT+PINxxxx Sets the pairing password of the device - -Any 4 digit number can be used, the default pincode is 1234 -AT+PN Sets the parity of the module - -So we could send AT+VERSION at different baudrates until we get a response -Then we can change the baudrate to the required value. -Or maybe just AT and get OK back -*/ - -uint32_t btStatus; - -void bluetoothTask(void * pdata) -{ - uint8_t byte; - - btFlag = CoCreateFlag(true, false); - btTx.size = 0; - - // Look for BT module baudrate, try 115200, and 9600 - // Already initialised to g_eeGeneral.bt_baudrate - // 0 : 115200, 1 : 9600, 2 : 19200 - - uint32_t x = g_eeGeneral.bluetoothBaudrate; - - btStatus = btPollDevice() ; // Do we get a response? - - for (int y=0; y<2; y++) { - if (btStatus == 0) { - x += 1 ; - if (x > 2) { - x = 0 ; - } - btSetBaudrate(x) ; - RTOS_WAIT_TICKS(1) ; // 2mS - btStatus = btPollDevice() ; // Do we get a response? - } - } - - if (btStatus) { - btStatus = x + 1 ; - if ( x != g_eeGeneral.bluetoothBaudrate ) { - x = g_eeGeneral.bluetoothBaudrate ; - // Need to change Bt Baudrate - btChangeBaudrate( x ) ; - btStatus += (x+1) * 10 ; - btSetBaudrate( x ) ; - } - } - else { - btInit(); - } - - RTOS_WAIT_TICKS(1) ; - - btPollDevice(); // Do we get a response? - - while (1) { - uint32_t x = CoWaitForSingleFlag(btFlag, 10); // Wait for data in Fifo - if (x == E_OK) { - // We have some data in the Fifo - while (btTxFifo.pop(byte)) { - btTxBuffer[btTx.size++] = byte; - if (btTx.size > 31) { - btSendBuffer(); - } - } - } - else if (btTx.size) { - btSendBuffer(); - } - } -} - -void btPushByte(uint8_t data) -{ - btTxFifo.push(data); - CoSetFlag(btFlag); // Tell the Bt task something to do -} diff --git a/radio/src/targets/sky9x/board.cpp b/radio/src/targets/sky9x/board.cpp deleted file mode 100644 index 0327688b5..000000000 --- a/radio/src/targets/sky9x/board.cpp +++ /dev/null @@ -1,494 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -#if defined(PCBAR9X) -#include "i2c_driver.h" -#endif - -uint16_t ResetReason; -uint32_t Master_frequency ; -volatile uint8_t lcdLock; -volatile uint32_t lcdInputs; - -uint16_t Current_analogue; -uint16_t Current_max; -uint32_t Current_accumulator; -uint32_t Current_used; - -extern "C" void sam_boot( void ) ; - -// Prototype -// Free pins (PA16 is stock buzzer) -// PA23, PA24, PA25, PB7, PB13 -// PC20, PC21(labelled 17), PC22, PC24 -// REVB -// PA25, use for stock buzzer -// PB14, PB6 -// PC21, PC19, PC15 (PPM2 output) -inline void config_free_pins() -{ - configure_pins( PIO_PB14, PIN_ENABLE | PIN_INPUT | PIN_PORTB | PIN_PULLUP ) ; -} - -// Assumes PMC has already enabled clocks to ports -inline void setup_switches() -{ - configure_pins( 0x01808087, PIN_ENABLE | PIN_INPUT | PIN_PORTA | PIN_PULLUP ) ; - configure_pins( 0x00000030, PIN_ENABLE | PIN_INPUT | PIN_PORTB | PIN_PULLUP ) ; - configure_pins( 0x91114900, PIN_ENABLE | PIN_INPUT | PIN_PORTC | PIN_PULLUP ) ; -} - -inline void UART3_Configure(uint32_t baudrate, uint32_t masterClock) -{ - Uart *pUart = BT_USART; - - /* Configure PIO */ - configure_pins( (PIO_PB2 | PIO_PB3), PIN_PERIPHERAL | PIN_INPUT | PIN_PER_A | PIN_PORTB | PIN_NO_PULLUP ) ; - - /* Configure PMC */ - PMC->PMC_PCER0 = 1 << BT_ID; - - /* Reset and disable receiver & transmitter */ - pUart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX - | UART_CR_RXDIS | UART_CR_TXDIS; - - /* Configure mode */ - pUart->UART_MR = 0x800 ; // NORMAL, No Parity - - /* Configure baudrate */ - /* Asynchronous, no oversampling */ - pUart->UART_BRGR = ( (masterClock / baudrate) + 8 ) / 16; - - /* Disable PDC channel */ - pUart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS; - - /* Enable receiver and transmitter */ - pUart->UART_CR = UART_CR_RXEN | UART_CR_TXEN; - -#if 0 - pUart->UART_IER = UART_IER_RXRDY ; - NVIC_EnableIRQ(UART1_IRQn) ; -#endif -} - -void UART3_Stop() -{ - BT_USART->UART_IDR = UART_IDR_RXRDY ; - NVIC_DisableIRQ(UART1_IRQn) ; -} - -// Starts TIMER0 at full speed (MCK/2) for delay timing -// @ 36MHz this is 18MHz -// This was 6 MHz, we may need to slow it to TIMER_CLOCK2 (MCK/8=4.5 MHz) -inline void start_timer0() -{ - Tc *ptc ; - - // Enable peripheral clock TC0 = bit 23 thru TC5 = bit 28 - PMC->PMC_PCER0 |= 0x00800000L ; // Enable peripheral clock to TC0 - - ptc = TC0 ; // Tc block 0 (TC0-2) - ptc->TC_BCR = 0 ; // No sync - ptc->TC_BMR = 2 ; - ptc->TC_CHANNEL[0].TC_CMR = 0x00008001 ; // Waveform mode MCK/8 for 36MHz osc. - ptc->TC_CHANNEL[0].TC_RC = 0xFFF0 ; - ptc->TC_CHANNEL[0].TC_RA = 0 ; - ptc->TC_CHANNEL[0].TC_CMR = 0x00008040 ; // 0000 0000 0000 0000 1000 0000 0100 0000, stop at regC - ptc->TC_CHANNEL[0].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) -} - -// TIMER2 at 200Hz, provides 5mS for sound and 10mS tick on interrupt -// Starts TIMER2 at 200Hz, commentd out drive of TIOA2 (A26, EXT2) -inline void start_timer2() -{ - Tc *ptc ; - uint32_t timer ; - - // Enable peripheral clock TC0 = bit 23 thru TC5 = bit 28 - PMC->PMC_PCER0 |= 0x02000000L ; // Enable peripheral clock to TC2 - - timer = Master_frequency / 12800 / 2; // MCK/128 and 200 Hz - - ptc = TC0 ; // Tc block 0 (TC0-2) - ptc->TC_BCR = 0 ; // No sync - ptc->TC_BMR = 0 ; - ptc->TC_CHANNEL[2].TC_CMR = 0x00008000 ; // Waveform mode - ptc->TC_CHANNEL[2].TC_RC = timer ; // 10 Hz - ptc->TC_CHANNEL[2].TC_RA = timer >> 1 ; - ptc->TC_CHANNEL[2].TC_CMR = 0x0009C003 ; // 0000 0000 0000 1001 1100 0000 0000 0011 - ptc->TC_CHANNEL[2].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) - - NVIC_EnableIRQ(TC2_IRQn) ; - TC0->TC_CHANNEL[2].TC_IER = TC_IER0_CPCS ; -} - -void interrupt5ms() -{ - static uint32_t pre_scale ; // Used to get 10 Hz counter - - HAPTIC_HEARTBEAT(); - - if ( ++pre_scale >= 2 ) { - BUZZER_HEARTBEAT(); - pre_scale = 0 ; - per10ms(); - } -} - -extern "C" void TC2_IRQHandler() -{ - uint32_t dummy; - - /* Clear status bit to acknowledge interrupt */ - dummy = TC0->TC_CHANNEL[2].TC_SR; - (void) dummy ; // Discard value - prevents compiler warning - - interrupt5ms(); -} - -// PWM used for PPM generation, and LED Backlight -// Output pin PB5 not used, PA17 used as PWMH3 peripheral C -// PWM peripheral ID = 31 (0x80000000) -// Ensure PB5 is three state/input, used on REVB for MENU KEY - -// Configure PWM3 as PPM drive, -// PWM0 is LED backlight PWM on PWMH0 -// This is PC18 peripheral B, Also enable PC22 peripheral B, this is PPM-JACK (PWML3) -// -// REVB board: -// PWML2, output as peripheral C on PA16, is for HAPTIC -// For testing, just drive it out with PWM -// PWML1 for PPM2 output as peripheral B on PC15 -// For testing, just drive it out with PWM -void init_pwm() -{ - Pwm *pwmptr ; - uint32_t timer ; - - PMC->PMC_PCER0 |= ( 1 << ID_PWM ) ; // Enable peripheral clock to PWM - - MATRIX->CCFG_SYSIO |= 0x00000020L ; // Disable TDO let PB5 work! - - /* Configure PIO */ - configure_pins( PIO_PA16, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_C | PIN_PORTA | PIN_NO_PULLUP ) ; - - configure_pins( PIO_PC18, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_B | PIN_PORTC | PIN_NO_PULLUP ) ; - configure_pins( PIO_PC22, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_B | PIN_PORTC | PIN_NO_PULLUP ) ; - - // Configure clock - depends on MCK frequency - timer = Master_frequency / 2000000 ; - timer |= ( Master_frequency / ( 32* 10000 ) ) << 16 ; - timer &= 0x00FF00FF ; - - pwmptr = PWM ; - pwmptr->PWM_CLK = 0x05000000 | timer ; // MCK for DIVA, DIVA = 18 gives 0.5uS clock period @35MHz // MCK/32 / timer = 10000Hz for CLKB - - // PWM0 for LED backlight - pwmptr->PWM_CH_NUM[0].PWM_CMR = 0x0000000C ; // CLKB - pwmptr->PWM_CH_NUM[0].PWM_CPDR = 100 ; // Period - pwmptr->PWM_CH_NUM[0].PWM_CPDRUPD = 100 ; // Period - pwmptr->PWM_CH_NUM[0].PWM_CDTY = 40 ; // Duty - pwmptr->PWM_CH_NUM[0].PWM_CDTYUPD = 40 ; // Duty - pwmptr->PWM_ENA = PWM_ENA_CHID0 ; // Enable channel 0 - - // PWM2 for HAPTIC drive 100Hz test - pwmptr->PWM_CH_NUM[2].PWM_CMR = 0x0000000C ; // CLKB - pwmptr->PWM_CH_NUM[2].PWM_CPDR = 100 ; // Period - pwmptr->PWM_CH_NUM[2].PWM_CPDRUPD = 100 ; // Period - pwmptr->PWM_CH_NUM[2].PWM_CDTY = 40 ; // Duty - pwmptr->PWM_CH_NUM[2].PWM_CDTYUPD = 40 ; // Duty - pwmptr->PWM_OOV &= ~0x00040000 ; // Force low - pwmptr->PWM_OSS = 0x00040000 ; // Force low - // pwmptr->PWM_ENA = PWM_ENA_CHID2 ; // Enable channel 2 -} - -// LCD i/o pins -// LCD_RES PC27 -// LCD_CS1 PC26 -// LCD_E PC12 -// LCD_RnW PC13 -// LCD_A0 PC15 -// LCD_D0 PC0 -// LCD_D1 PC7 -// LCD_D2 PC6 -// LCD_D3 PC5 -// LCD_D4 PC4 -// LCD_D5 PC3 -// LCD_D6 PC2 -// LCD_D7 PC1 - -#define LCD_DATA 0x000000FFL -#define LCD_A0 0x00000080L -#define LCD_RnW 0x00002000L -#define LCD_E 0x00001000L -#define LCD_CS1 0x04000000L -#define LCD_RES 0x08000000L - -void configure_pins( uint32_t pins, uint16_t config ) -{ - Pio * pioptr; - - pioptr = PIOA + ((config & PIN_PORT_MASK) >> 6); - if (config & PIN_PULLUP) { - pioptr->PIO_PPDDR = pins; - pioptr->PIO_PUER = pins; - } - else { - pioptr->PIO_PUDR = pins; - } - - if (config & PIN_PULLDOWN) { - pioptr->PIO_PUDR = pins; - pioptr->PIO_PPDER = pins; - } - else { - pioptr->PIO_PPDDR = pins; - } - - if (config & PIN_HIGH) { - pioptr->PIO_SODR = pins; - } - else { - pioptr->PIO_CODR = pins; - } - - if (config & PIN_INPUT) { - pioptr->PIO_ODR = pins; - } - else { - pioptr->PIO_OER = pins; - } - - if (config & PIN_PERI_MASK_L) { - pioptr->PIO_ABCDSR[0] |= pins; - } - else { - pioptr->PIO_ABCDSR[0] &= ~pins; - } - - if (config & PIN_PERI_MASK_H) { - pioptr->PIO_ABCDSR[1] |= pins; - } - else { - pioptr->PIO_ABCDSR[1] &= ~pins; - } - - if (config & PIN_ENABLE) { - pioptr->PIO_PER = pins; - } - else { - pioptr->PIO_PDR = pins; - } -} - -void opentxBootloader(); - -// Set up for volume control (TWI0) -// Need PA3 and PA4 set to peripheral A -#if !defined(PCBAR9X) -void i2cInit() -{ - Pio *pioptr; - uint32_t timing; - - PMC->PMC_PCER0 |= 0x00080000L ; // Enable peripheral clock to TWI0 - - TWI0->TWI_CR = TWI_CR_SWRST ; // Reset in case we are restarting - - /* Configure PIO */ - pioptr = PIOA ; - pioptr->PIO_ABCDSR[0] &= ~0x00000018 ; // Peripheral A - pioptr->PIO_ABCDSR[1] &= ~0x00000018 ; // Peripheral A - pioptr->PIO_PDR = 0x00000018 ; // Assign to peripheral - - timing = Master_frequency * 5 / 1000000 ; // 5uS high and low - timing += 15 - 4 ; - timing /= 16 ; - timing |= timing << 8 ; - - TWI0->TWI_CWGR = 0x00040000 | timing ; // TWI clock set - TWI0->TWI_CR = TWI_CR_MSEN | TWI_CR_SVDIS ; // Master mode enable - TWI0->TWI_MMR = 0x002F0000 ; // Device 5E (>>1) and master is writing - NVIC_EnableIRQ(TWI0_IRQn) ; -} -#endif - -void boardInit() -{ - Pio *pioptr ; - - ResetReason = RSTC->RSTC_SR; - - MATRIX->CCFG_SYSIO |= 0x000000F0L ; // Disable syspins, enable B4,5,6,7 - - PMC->PMC_PCER0 = (1<PIO_PER = PIO_PC25 ; // Enable bit C25 (USB-detect) - - pwrInit() ; - - config_free_pins() ; - - // Next section configures the key inputs on the LCD data - pioptr = PIOC; - pioptr->PIO_PER = 0x0000003BL ; // Enable bits 1,3,4,5, 0 - pioptr->PIO_OER = PIO_PC0 ; // Set bit 0 output - pioptr->PIO_ODR = 0x0000003AL ; // Set bits 1, 3, 4, 5 input - pioptr->PIO_PUER = 0x0000003AL ; // Set bits 1, 3, 4, 5 with pullups - - pioptr = PIOB ; - pioptr->PIO_PUER = PIO_PB5 ; // Enable pullup on bit B5 (MENU) - pioptr->PIO_PER = PIO_PB5 ; // Enable bit B5 - - setup_switches() ; - - // Enable PCK2 on PB3, This is for testing of Timer 2 working - // It will be used as serial data to the Bluetooth module - pioptr->PIO_ABCDSR[0] |= PIO_PB3 ; // Peripheral B - pioptr->PIO_ABCDSR[1] &= ~PIO_PB3 ; // Peripheral B - pioptr->PIO_PDR = PIO_PB3 ; // Assign to peripheral - PMC->PMC_SCER |= 0x0400 ; // PCK2 enabled - PMC->PMC_PCK[2] = 2 ; // PCK2 is PLLA - - start_timer2() ; - start_timer0() ; - adcInit() ; - init_pwm() ; - - __enable_irq(); - - audioInit(); - - i2cInit(); - - eepromInit(); - -#if defined(ROTARY_ENCODER_NAVIGATION) - rotaryEncoderInit(); -#endif - - lcdInit(); - - init_SDcard(); - -#if defined(PCBAR9X) - rtcInit(); -#endif -} - -uint8_t temperature = 0; // Raw temp reading -uint8_t maxTemperature = 0 ; // Raw temp reading - -void end_bt_tx_interrupt() -{ - Uart *pUart = BT_USART ; - pUart->UART_IDR = UART_IDR_TXBUFE ; - NVIC_DisableIRQ(UART1_IRQn) ; -} - -uint16_t getCurrent() -{ - static uint16_t Current ; - static uint32_t Current_sum ; - static uint8_t Current_count ; - - Current_sum += anaIn(TX_CURRENT); - if (++Current_count >= 50) { - Current = Current_sum / 5 ; - Current_sum = 0 ; - Current_count = 0 ; - } - - uint32_t current_scale = 488 + g_eeGeneral.txCurrentCalibration ; - return (current_scale * Current) / 8192; -} - -#define STICK_LV_GAIN 0x01 -#define STICK_LH_GAIN 0x02 -#define STICK_RV_GAIN 0x04 -#define STICK_RH_GAIN 0x08 - -#define GAIN_LV 0x00080000 -#define GAIN_LH 0x00000020 -#define GAIN_RV 0x20000000 -#define GAIN_RH 0x00000008 - -#define OFF_LV 0x00000200 -#define OFF_LH 0x00000004 -#define OFF_RV 0x00004000 -#define OFF_RH 0x00000002 - -void setSticksGain(uint8_t gains) -{ - Adc *padc ; - uint32_t gain ; - uint32_t offset ; - - gain = 0 ; - offset = 0 ; - padc = ADC ; - - if ( gains & STICK_LV_GAIN ) { - gain |= GAIN_LV ; - offset |= OFF_LV ; - } - if ( gains & STICK_LH_GAIN ) { - gain |= GAIN_LH ; - offset |= OFF_LH ; - } - if ( gains & STICK_RV_GAIN ) { - gain |= GAIN_RV ; - offset |= OFF_RV ; - } - if ( gains & STICK_RH_GAIN ) { - gain |= GAIN_RH ; - offset |= OFF_RH ; - } - - padc->ADC_CGR = gain; - padc->ADC_COR = offset; -} - -void calcConsumption() -{ - Current_accumulator += Current_analogue ; - static uint32_t OneSecTimer; - if (++OneSecTimer >= 100) { - OneSecTimer -= 100 ; - Current_used += Current_accumulator / 100 ; // milliAmpSeconds (but scaled) - Current_accumulator = 0 ; - } -} - -uint16_t getBatteryVoltage() -{ - int32_t instant_vbat = anaIn(TX_VOLTAGE); // using filtered ADC value on purpose - instant_vbat = (instant_vbat + instant_vbat*(g_eeGeneral.txVoltageCalibration)/128) * 4191; - instant_vbat /= 5530; - return (uint16_t)instant_vbat; -} - -void boardOff() -{ - pwrOff(); -} diff --git a/radio/src/targets/sky9x/board.h b/radio/src/targets/sky9x/board.h deleted file mode 100644 index 7ac83b00b..000000000 --- a/radio/src/targets/sky9x/board.h +++ /dev/null @@ -1,425 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BOARD_SKY9X_H_ -#define _BOARD_SKY9X_H_ - -#include -#include -#include -#include "board_lowlevel.h" -#include "audio_driver.h" -#include "../opentx_constants.h" - -#define CPU_FREQ 36000000 - -extern uint16_t ResetReason; - -#define BOOTLOADER_SIZE 0x8000 -#define FIRMWARE_SIZE (256*1024) -#define FIRMWARE_ADDRESS 0x00400000 - -// Board driver -void boardInit(); -void boardOff(); - -// Rotary Encoder driver -void rotaryEncoderInit(); -void rotaryEncoderEnd(); - -#if !defined(REVX) && !defined(PCBAR9X) - #define ROTARY_ENCODER_NAVIGATION - #define REA_DOWN() (!(PIOB->PIO_PDSR & 0x40)) -#else - #define REA_DOWN() (0) -#endif - -// Keys driver -#define NUM_SWITCHES 7 -#define STORAGE_NUM_SWITCHES NUM_SWITCHES -#define NUM_SWITCHES_POSITIONS 9 - -#if !defined(NUM_FUNCTIONS_SWITCHES) -#define NUM_FUNCTIONS_SWITCHES 0 -#endif - -enum EnumKeys -{ - KEY_MENU, - KEY_ENTER=KEY_MENU, - KEY_EXIT, - KEY_DOWN, - KEY_MINUS = KEY_DOWN, - KEY_UP, - KEY_PLUS = KEY_UP, - KEY_RIGHT, - KEY_LEFT, - - KEY_COUNT, - KEY_MAX = KEY_COUNT - 1, - - TRM_BASE, - TRM_LH_DWN = TRM_BASE, - TRM_LH_UP, - TRM_LV_DWN, - TRM_LV_UP, - TRM_RV_DWN, - TRM_RV_UP, - TRM_RH_DWN, - TRM_RH_UP, - TRM_LAST = TRM_RH_UP, - - NUM_KEYS -}; - -#define IS_SHIFT_KEY(index) (false) -#define IS_SHIFT_PRESSED() (false) - -enum EnumSwitches -{ - SW_ID0, - SW_ID1, - SW_ID2, - SW_THR, - SW_RUD, - SW_ELE, - SW_AIL, - SW_GEA, - SW_TRN, -}; -#define IS_3POS(sw) ((sw) == 0) -#define IS_TOGGLE(sw) ((sw) == SWSRC_TRN) - -#define KEYS_GPIO_REG_MENU PIOB->PIO_PDSR -#define KEYS_GPIO_REG_EXIT PIOC->PIO_PDSR -#define KEYS_GPIO_REG_UP PIOC->PIO_PDSR -#define KEYS_GPIO_REG_DOWN PIOC->PIO_PDSR -#define KEYS_GPIO_REG_RIGHT PIOC->PIO_PDSR -#define KEYS_GPIO_REG_LEFT PIOC->PIO_PDSR -#define KEYS_GPIO_PIN_MENU 0x00000020 -#define KEYS_GPIO_PIN_EXIT 0x01000000 -#define KEYS_GPIO_PIN_UP 0x00000002 -#define KEYS_GPIO_PIN_DOWN 0x00000020 -#define KEYS_GPIO_PIN_RIGHT 0x00000010 -#define KEYS_GPIO_PIN_LEFT 0x00000008 - -#if defined(REVX) - #define TRIMS_GPIO_REG_LHL PIOB->PIO_PDSR - #define TRIMS_GPIO_REG_LVD PIOA->PIO_PDSR - #define TRIMS_GPIO_REG_RVU PIOC->PIO_PDSR - #define TRIMS_GPIO_REG_RHL PIOA->PIO_PDSR - #define TRIMS_GPIO_REG_LHR PIOA->PIO_PDSR - #define TRIMS_GPIO_REG_LVU PIOC->PIO_PDSR - #define TRIMS_GPIO_REG_RVD PIOA->PIO_PDSR - #define TRIMS_GPIO_REG_RHR PIOC->PIO_PDSR -#else - #define TRIMS_GPIO_REG_LHL PIOA->PIO_PDSR - #define TRIMS_GPIO_REG_LVD PIOA->PIO_PDSR - #define TRIMS_GPIO_REG_RVU PIOA->PIO_PDSR - #define TRIMS_GPIO_REG_RHL PIOA->PIO_PDSR - #define TRIMS_GPIO_REG_LHR PIOB->PIO_PDSR - #define TRIMS_GPIO_REG_LVU PIOC->PIO_PDSR - #define TRIMS_GPIO_REG_RVD PIOC->PIO_PDSR - #define TRIMS_GPIO_REG_RHR PIOC->PIO_PDSR -#endif - -#if defined(REVX) - #define TRIMS_GPIO_PIN_LHL 0x00000010 - #define TRIMS_GPIO_PIN_LVD 0x01000000 - #define TRIMS_GPIO_PIN_RVU 0x00000400 - #define TRIMS_GPIO_PIN_RHL 0x00000001 - #define TRIMS_GPIO_PIN_LHR 0x00800000 - #define TRIMS_GPIO_PIN_LVU 0x10000000 - #define TRIMS_GPIO_PIN_RVD 0x00000002 - #define TRIMS_GPIO_PIN_RHR 0x00000200 -#else - #define TRIMS_GPIO_PIN_LHL 0x00800000 - #define TRIMS_GPIO_PIN_LVD 0x01000000 - #define TRIMS_GPIO_PIN_RVU 0x00000002 - #define TRIMS_GPIO_PIN_RHL 0x00000001 - #define TRIMS_GPIO_PIN_LHR 0x00000010 - #define TRIMS_GPIO_PIN_LVU 0x10000000 - #define TRIMS_GPIO_PIN_RVD 0x00000400 - #define TRIMS_GPIO_PIN_RHR 0x00000200 -#endif - -// LCD driver -#define LCD_W 128 -#define LCD_H 64 -#define LCD_DEPTH 1 -#define LCD_CONTRAST_MIN 10 -#define LCD_CONTRAST_MAX 45 -#define LCD_CONTRAST_DEFAULT 25 -void lcdInit(); -void lcdRefresh(); -#define lcdRefreshWait() -void lcdSetRefVolt(uint8_t val); -void lcdSetContrast(); - -// USB driver -void usbMassStorage(); - -#if !defined(SIMU) -void usbJoystickUpdate(); -#endif - -#define PIN_ENABLE 0x001 -#define PIN_PERIPHERAL 0x000 -#define PIN_INPUT 0x002 -#define PIN_OUTPUT 0x000 -#define PIN_PULLUP 0x004 -#define PIN_NO_PULLUP 0x000 -#define PIN_PULLDOWN 0x008 -#define PIN_NO_PULLDOWN 0x000 -#define PIN_PERI_MASK_L 0x010 -#define PIN_PERI_MASK_H 0x020 -#define PIN_PER_A 0x000 -#define PIN_PER_B 0x010 -#define PIN_PER_C 0x020 -#define PIN_PER_D 0x030 -#define PIN_PORT_MASK 0x0C0 -#define PIN_PORTA 0x000 -#define PIN_PORTB 0x040 -#define PIN_PORTC 0x080 -#define PIN_LOW 0x000 -#define PIN_HIGH 0x100 - -// Telemetry port -#define SECOND_USART USART0 -#define SECOND_ID ID_USART0 -#define SECOND_PINS { PINS_USART0 } - -void configure_pins( uint32_t pins, uint16_t config ); -uint16_t getCurrent(); - -extern uint16_t Current_analogue; -extern uint16_t Current_max; -extern uint32_t Current_accumulator; -extern uint32_t Current_used; -extern uint16_t sessionTimer; -void calcConsumption(); - -// Trainer driver -#define SLAVE_MODE() (pwrCheck() == e_power_trainer) -void init_trainer_capture(); -void stop_trainer_capture(); -#define TRAINER_DETECT_GPIO PIOA -#define TRAINER_DETECT_GPIO_PIN PIO_PA8 -#define TRAINER_CONNECTED() (TRAINER_DETECT_GPIO->PIO_PDSR & TRAINER_DETECT_GPIO_PIN) - -// Write Flash driver -#define FLASH_PAGESIZE 256 -void flashWrite(uint32_t * address, const uint32_t * buffer); - -// Keys driver -uint32_t switchState(uint8_t index); -uint32_t readKeys(); -uint32_t readTrims(); -#define NUM_TRIMS 4 -#define NUM_TRIMS_KEYS (NUM_TRIMS * 2) -#define TRIMS_PRESSED() readTrims() -#define KEYS_PRESSED() readKeys() - -// Pulses driver -void extmoduleSerialStart(uint32_t baudrate, uint32_t period_half_us, bool inverted); -void extmoduleSendNextFrame(); -void module_output_active(); -inline void EXTERNAL_MODULE_ON() -{ - module_output_active(); -} - -// SD driver -#if defined(SIMU) -#define sdInit() -#define sdDone() -#else -#define sdPoll10ms() -#if defined(__cplusplus) -extern "C" { -#endif - void init_SDcard(); - void sdInit(); - void sdDone(); - uint32_t sd_card_ready(); - uint32_t sdMounted(); -#if defined(__cplusplus) -} -#endif -#endif - -// WDT driver -#if !defined(WATCHDOG) || defined(SIMU) - #define WDG_ENABLE(x) - #define WDG_RESET() - #define IS_RESET_REASON_WATCHDOG() false -#else - #define WDG_ENABLE(x) WDT->WDT_MR = 0x3FFF207F - #define WDG_RESET() WDT->WDT_CR = 0xA5000001 - #define IS_RESET_REASON_WATCHDOG() ((ResetReason & RSTC_SR_RSTTYP) == (2 << 8)) -#endif - -// Backlight driver -#define backlightEnable() (PWM->PWM_CH_NUM[0].PWM_CDTY = currentBacklightBright) -#define backlightDisable() (PWM->PWM_CH_NUM[0].PWM_CDTY = 100) -#define isBacklightEnabled() (PWM->PWM_CH_NUM[0].PWM_CDTY != 100) -#define BACKLIGHT_ENABLE() backlightEnable() -#define BACKLIGHT_DISABLE() backlightDisable() -#define BACKLIGHT_FORCED_ON 101 - -// ADC driver -#define NUM_POTS 3 -#define STORAGE_NUM_POTS 3 -#define NUM_SLIDERS 0 -#define STORAGE_NUM_SLIDERS 0 -#define NUM_XPOTS 0 -#define NUM_MOUSE_ANALOGS 0 -#define STORAGE_NUM_MOUSE_ANALOGS 0 -enum Analogs { - STICK1, - STICK2, - STICK3, - STICK4, - POT_FIRST, - POT1 = POT_FIRST, - POT2, - POT3, - POT_LAST = POT3, - TX_VOLTAGE, - TX_CURRENT, - NUM_ANALOGS -}; -enum CalibratedAnalogs { - CALIBRATED_STICK1, - CALIBRATED_STICK2, - CALIBRATED_STICK3, - CALIBRATED_STICK4, - CALIBRATED_POT_FIRST, - CALIBRATED_POT1 = CALIBRATED_POT_FIRST, - CALIBRATED_POT2, - CALIBRATED_POT3, - CALIBRATED_POT_LAST = CALIBRATED_POT3, - NUM_CALIBRATED_ANALOGS -}; -#define IS_POT(x) ((x)>=POT_FIRST && (x)<=POT_LAST) -#define IS_SLIDER(x) false -#define STICKS_PWM_ENABLED() false -void adcInit(); -void adcRead(); -uint16_t getAnalogValue(uint8_t index); -void setSticksGain(uint8_t gains); -inline void enableVBatBridge() -{ -} -inline void disableVBatBridge() -{ -} - -// Battery driver -uint16_t getBatteryVoltage(); // returns current battery voltage in 10mV steps -#define BATTERY_MIN 90 // 9V -#define BATTERY_MAX 120 // 12V -#define BATTERY_WARN 90 // 9V - -// Buzzer driver -void buzzerSound(uint8_t duration); -void buzzerHeartbeat(); -#define BUZZER_HEARTBEAT buzzerHeartbeat - -// i2c driver -void i2cCheck(); - -// Coproc driver -void coprocInit(); -void coprocWriteData(uint8_t *data, uint32_t size); -#if defined(__cplusplus) -void coprocReadData(bool onlytemp=false); -#endif -extern int8_t volumeRequired; - -#if defined(COPROCESSOR) -typedef struct { - uint8_t read; - int8_t valid; - int8_t temp; - int8_t maxtemp; -} CoprocData; - -extern CoprocData coprocData; -#endif - -// Haptic driver -#define HAPTIC_PWM -void hapticOff(); -void hapticOn(uint32_t pwmPercent); - -// BlueTooth driver -#if defined(BLUETOOTH) -void btInit(); -void bluetoothTask(void * pdata); -void btPushByte(uint8_t data); -#endif - -// Power driver -#define TRAINER_PWR -#define SOFT_PWR_CTRL -void pwrInit(); -void pwrOff(); -void pwrOn(); -uint32_t pwrCheck(); -bool pwrPressed(); -#define UNEXPECTED_SHUTDOWN() (g_eeGeneral.unexpectedShutdown) -#define pwrForcePressed() (false) - -// EEPROM driver -#define EEPROM_SIZE (4*1024*1024/8) -#define EEPROM_BLOCK_SIZE (4*1024) -void eepromInit(); -uint8_t eepromReadStatus(); -uint8_t eepromIsTransferComplete(); -void eepromBlockErase(uint32_t address); -void eepromStartRead(uint8_t * buffer, size_t address, size_t size); -void eepromStartWrite(uint8_t * buffer, size_t address, size_t size); - -// Debug driver -void debugPutc(const char c); - -// Telemetry driver -void telemetryPortInit(uint32_t baudrate, uint8_t mode); -void telemetryPortSetDirectionOutput(); -void telemetryPortSetDirectionInput(); -void telemetryTransmitBuffer(const uint8_t * buffer, uint32_t size); -void rxPdcUsart( void (*pChProcess)(uint8_t x) ); -void sportSendBuffer(const uint8_t * buffer, uint32_t size); - -// Second UART driver -void auxSerialTelemetryInit(unsigned int protocol); -void auxSerialPutc(const unsigned char c); -#if defined(__cplusplus) -bool telemetrySecondPortReceive(uint8_t & data); -#endif - -extern const uint8_t BootCode[]; - -// Pulses driver -#define HARDWARE_EXTRA_MODULE - -#endif // _BOARD_SKY9X_H_ diff --git a/radio/src/targets/sky9x/board_lowlevel.c b/radio/src/targets/sky9x/board_lowlevel.c deleted file mode 100644 index 15d47661a..000000000 --- a/radio/src/targets/sky9x/board_lowlevel.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/** - * \file - * - * \par Purpose - * - * Provides the low-level initialization function that gets called on chip startup. - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "board_lowlevel.h" - -/*---------------------------------------------------------------------------- - * Local definitions - *----------------------------------------------------------------------------*/ -/** Define clock timeout */ -#define CLOCK_TIMEOUT 5000 -/** Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.*/ -#define PMC_PLLA_SET_BIT29 (0x1 << 29) -/** Specifies the number of Slow Clock cycles x8 before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.*/ -#define PMC_PLLA_COUNT (0xBF << 8) -/** The PLLA Clock frequency is the PLLA input frequency multiplied by 8*/ -#define PMC_PLLA_MULTIPIER (0x07 << 16) -/** PLLA Divider is bypassed.*/ -#define PMC_PLLA_DIV (0x01) - -void revert_osc( void ) ; - - -/*---------------------------------------------------------------------------- - * Local functions - * returns master_frequency - *----------------------------------------------------------------------------*/ - -// *** WARNING, this is called BEFORE .data and .bss have been initialised -// *** GLOBAL variables are NOT useable - -static uint32_t BOARD_ConfigurePmc(void) -{ -/* TODO: configurate PLL in new way */ -//#if 0 -// uint32_t timeout = 0; -// /** 1: Checking the Main Oscillator Frequency (Optional) and Initialize main oscillator */ -// /** 1.1 Initialize main oscillator */ -// // TODO: - -// /** 2. Setting PLL and Divider*/ -// /** 2.1 Initialize PLLA*/ -// PMC->CKGR_PLLAR = ( PMC_PLLA_SET_BIT29 | -// PMC_PLLA_MULTIPIER | -// PMC_PLLA_COUNT | -// PMC_PLLA_DIV -// ); -// timeout = 0; -// /** 2.2 Wait for the LOCKA bit to be set by polling the status register.*/ -// while (!(PMC->PMC_SR & PMC_SR_LOCKA) && (timeout++ < CLOCK_TIMEOUT)); -// /** 2.3 wait for the MCKRDY bit to be set by polling the status register*/ -// timeout = 0; -// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); - -// /** 3. Selection of Master Clock and Processor Clock*/ -// PMC->PMC_MCKR |= PMC_MCKR_PRES_CLK_2; - -// /** 3.1 wait for the MCKRDY bit to be set by polling the status register*/ -// timeout = 0; -// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); - -// /** 3.2 PLLA Clock is selected */ -// PMC->PMC_MCKR = PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK; - -// /** 3.3 wait for the MCKRDY bit to be set by polling the status register*/ -// timeout = 0; -// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); -//#endif - -#if 1 // old as sam3u -#define AT91C_CKGR_MUL_SHIFT 16 -//#define AT91C_CKGR_OUT_SHIFT 14 -#define AT91C_CKGR_PLLCOUNT_SHIFT 8 -#define AT91C_CKGR_DIV_SHIFT 0 - -// Settings at 72MHz/2 = 36MHz -#define BOARD_OSCOUNT (CKGR_MOR_MOSCXTST & (0x8 << 8)) -#define BOARD_PLLR ((1 << 29) | (0x5 << AT91C_CKGR_MUL_SHIFT) \ - | (0x1 << AT91C_CKGR_PLLCOUNT_SHIFT) | (0x2 << AT91C_CKGR_DIV_SHIFT)) -#define BOARD_MCKR (PMC_MCKR_CSS_PLLA_CLK) - -// Define clock timeout -#undef CLOCK_TIMEOUT -#define CLOCK_TIMEOUT 0xFFFFFFFF - - uint32_t timeout = 0 ; - Pmc *pmcptr ; - - pmcptr = PMC ; - - /* Enable NRST reset - ************************************/ - //AT91C_BASE_RSTC->RSTC_RMR |= AT91C_RSTC_URSTEN; - - /* Select external slow clock - ****************************/ - - -// if ((SUPC->SUPC_SR & SUPC_SR_OSCSEL) != SUPC_SR_OSCSEL_CRYST) { -// SUPC->SUPC_CR = SUPC_CR_XTALSEL_CRYSTAL_SEL | ((uint32_t)0xA5 << 24); -// timeout = 0; -// while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL_CRYST) ); -// } - - - /* Initialize main oscillator - ****************************/ - if(!(pmcptr->CKGR_MOR & CKGR_MOR_MOSCSEL)) - { - - pmcptr->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; - timeout = 0; - while (!(pmcptr->PMC_SR & PMC_SR_MOSCXTS) && (++timeout < CLOCK_TIMEOUT)); - - } - - /* Switch to 3-20MHz Xtal oscillator */ - pmcptr->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL; - timeout = 0; - while (!(pmcptr->PMC_SR & PMC_SR_MOSCSELS) && (++timeout < CLOCK_TIMEOUT)); - - pmcptr->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK; - timeout = 0; - while (!(pmcptr->PMC_SR & PMC_SR_MCKRDY) && (++timeout < CLOCK_TIMEOUT)); - - /* Initialize PLLA 72 MHz */ - pmcptr->CKGR_PLLAR = BOARD_PLLR; - timeout = 0; - while (!(pmcptr->PMC_SR & PMC_SR_LOCKA) && (++timeout < CLOCK_TIMEOUT)); - - - /* Initialize UTMI for USB usage, can be disabled if not using USB for the sake of saving power*/ - //AT91C_BASE_CKGR->CKGR_UCKR |= (AT91C_CKGR_UPLLCOUNT & (3 << 20)) | AT91C_CKGR_UPLLEN; - //timeout = 0; - //while (!(PMC->PMC_SR & AT91C_PMC_LOCKU) && (timeout++ < CLOCK_TIMEOUT)); - - /* Switch to fast clock - **********************/ -// PMC->PMC_MCKR = (BOARD_MCKR & ~PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK; -// timeout = 0; -// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); - - // Switch to PLLA as main clock 36MHz - PMC->PMC_MCKR = BOARD_MCKR; - timeout = 0; - while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); - -#endif - return 36000000L; // Master_frequency -} - -void revert_osc() -{ - uint32_t timeout = 0; - Pmc *pmcptr; - - pmcptr = PMC; - - // Switch back to the internal oscillator - pmcptr->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; - timeout = 0; - while (!(pmcptr->PMC_SR & PMC_SR_MOSCSELS) && (++timeout < CLOCK_TIMEOUT)); - - pmcptr->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS) | PMC_MCKR_CSS_SLOW_CLK; - timeout = 0; - while (!(pmcptr->PMC_SR & PMC_SR_MCKRDY) && (++timeout < CLOCK_TIMEOUT)); - - pmcptr->CKGR_PLLAR = 1 << 29; // Stop PLLA -} - -#if defined(BOOT) -// extern void sam_bootx( void ) ; -// extern void dispUSB( void ) ; -// extern uint32_t init -// ReadTrims( void ) ; -// extern void run_application( void ) ; - -static void lowLevelUsbCheck( void ) -{ - PMC->PMC_PCER0 = (1<PIO_PER = PIO_PC25 ; // Enable bit C25 (USB-detect) - - uint32_t i ; - for ( i = 0 ; i < 50 ; i += 1 ) { - __asm("nop") ; - } - - for ( i = 0 ; i < 10 ; i += 1 ) { - if ( PIOC->PIO_PDSR & 0x02000000 ) { - PMC->PMC_PCDR0 = (1<EEFC_FMR = (1 << 8) ; - - // Configure PMC - return BOARD_ConfigurePmc(); -} diff --git a/radio/src/targets/sky9x/board_lowlevel.h b/radio/src/targets/sky9x/board_lowlevel.h deleted file mode 100644 index be81f37d7..000000000 --- a/radio/src/targets/sky9x/board_lowlevel.h +++ /dev/null @@ -1,634 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// TODO merge this file with board_sky9x.h - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -#include -#include "chip.h" -#include "AT91SAM3S4.h" - -#if !defined(SIMU) -#include "core_cm3.h" -#endif - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par -/// This page lists several definition related to the board description. -/// -/// Definitions -/// - BOARD_NAME - -/// Name of the board. -// #define BOARD_NAME "AT91SAM3S-EK" -/// Board definition. -#define at91sam3sek -/// Family definition (already defined). -#define at91sam3s -/// Core definition -#define cortexm3 - -// TODO remove these definitions -//#define BOARD_REV_A -#define BOARD_REV_B - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par sam3s_ek_opfreq "SAM3S-EK - Operating frequencies" -/// This page lists several definition related to the board operating frequency -/// (when using the initialization done by board_lowlevel.c). -/// -/// !Definitions -/// - BOARD_MAINOSC -/// - BOARD_MCK - -/// Frequency of the board main oscillator. -#define BOARD_MAINOSC 12000000 - -/// Master clock frequency (when using board_lowlevel.c). -// #define BOARD_MCK 64000000 - -//------------------------------------------------------------------------------ -// ADC -//------------------------------------------------------------------------------ - -/// Startup time max, return from Idle mode (in �s) -#define ADC_STARTUP_TIME_MAX 15 -/// Track and hold Acquisition Time min (in ns) -#define ADC_TRACK_HOLD_TIME_MIN 1200 - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// USB attributes configuration descriptor (bus or self powered, remote wakeup) -//#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_RWAKEUP -#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par sam3s_ek_piodef "SAM3S-EK - PIO definitions" -/// This pages lists all the pio definitions contained in board.h. The constants -/// are named using the following convention: PIN_* for a constant which defines -/// a single Pin instance (but may include several PIOs sharing the same -/// controller), and PINS_* for a list of Pin instances. -/// -/// !ADC -/// - PIN_ADC0_AD0 -/// - PIN_ADC0_AD1 -/// - PIN_ADC0_AD2 -/// - PIN_ADC0_AD3 -/// - PIN_ADC0_AD4 -/// - PIN_ADC0_AD5 -/// - PIN_ADC0_AD6 -/// - PIN_ADC0_AD7 -/// - PINS_ADC0 -/// -/// !UART -/// - PINS_UART -/// -/// !EBI -/// - PIN_EBI_DATA_BUS -/// - PIN_EBI_NCS0 -/// - PIN_EBI_NRD -/// - PIN_EBI_NWE -/// - PIN_EBI_ADDR_BUS -/// - PIN_EBI_PSRAM_NBS -/// - PIN_EBI_A1 -/// - PIN_EBI_LCD_RS -/// -/// !LEDs -/// - PIN_LED_0 -/// - PIN_LED_1 -/// - PIN_LED_2 -/// - PINS_LEDS -/// -/// !MCI -/// - PINS_MCI -/// -/// !Push buttons -/// - PIN_PUSHBUTTON_1 -/// - PIN_PUSHBUTTON_2 -/// - PINS_PUSHBUTTONS -/// - PUSHBUTTON_BP1 -/// - PUSHBUTTON_BP2 -/// -/// !PWMC -/// - PIN_PWMC_PWMH0 -/// - PIN_PWMC_PWML0 -/// - PIN_PWMC_PWMH1 -/// - PIN_PWMC_PWML1 -/// - PIN_PWMC_PWMH2 -/// - PIN_PWMC_PWML2 -/// - PIN_PWMC_PWMH3 -/// - PIN_PWMC_PWML3 -/// - PIN_PWM_LED0 -/// - PIN_PWM_LED1 -/// - PIN_PWM_LED2 -/// - CHANNEL_PWM_LED0 -/// - CHANNEL_PWM_LED1 -/// - CHANNEL_PWM_LED2 -/// -/// !SPI -/// - PIN_SPI_MISO -/// - PIN_SPI_MOSI -/// - PIN_SPI_SPCK -/// - PINS_SPI -/// - PIN_SPI_NPCS0_PA11 -/// -/// ! SSC -/// - PIN_SSC_TD -/// - PIN_SSC_TK -/// - PIN_SSC_TF -/// - PINS_SSC_CODEC -/// -/// ! PCK0 -/// - PIN_PCK0 -/// -/// !TWI -/// - PIN_TWI_TWD0 -/// - PIN_TWI_TWCK0 -/// - PINS_TWI -/// -/// !USART0 -/// - PIN_USART0_RXD -/// - PIN_USART0_TXD -/// - PIN_USART0_CTS -/// - PIN_USART0_RTS -/// - PIN_USART0_SCK -/// -/// !USB -/// - PIN_USB_PULLUP -/// - -/// ADC_AD0 pin definition. -#define PIN_ADC0_AD0 {1 << 21, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD1 pin definition. -#define PIN_ADC0_AD1 {1 << 30, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD2 pin definition. -#define PIN_ADC0_AD2 {1 << 3, PIOB, ID_PIOB, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD3 pin definition. -#define PIN_ADC0_AD3 {1 << 4, PIOB, ID_PIOB, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD4 pin definition. -#define PIN_ADC0_AD4 {1 << 15, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD5 pin definition. -#define PIN_ADC0_AD5 {1 << 16, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD6 pin definition. -#define PIN_ADC0_AD6 {1 << 17, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD7 pin definition. -#define PIN_ADC0_AD7 {1 << 18, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} - -/// Pins ADC -#define PINS_ADC PIN_ADC0_AD0, PIN_ADC0_AD1, PIN_ADC0_AD2, PIN_ADC0_AD3, PIN_ADC0_AD4, PIN_ADC0_AD5, PIN_ADC0_AD6, PIN_ADC0_AD7 - -/** UART pins (UTXD0 and URXD0) definitions, PA9,10. */ -#define PINS_UART {0x00000600, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} - -/// EBI -#define PIN_EBI_DATA_BUS {0xFF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NRD {1 << 11, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NWE {1 << 8, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} - -#define PIN_EBI_NCS0 {1 << 20, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_PSRAM_ADDR_BUS {0x3f00fff, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_PSRAM_NBS {1 << 7, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_PULLUP}, \ - {1 << 15, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_A1 {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} - -#define PIN_EBI_NCS1 {1 << 15, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} /* LCD CS pin */ -#define PIN_EBI_LCD_RS {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} /* LCD RS pin */ - -#ifdef BOARD_REV_A -/** LED #0 pin definition. */ -#define PIN_LED_0 {1 << 20, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -/** LED #1 pin definition. */ -#define PIN_LED_1 {1 << 21, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -/** LED #2 pin definition. */ -#define PIN_LED_2 {1 << 22, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -#endif -#ifdef BOARD_REV_B -/** LED #0 pin definition. */ -#define PIN_LED_0 {1 << 19, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} -/** LED #1 pin definition. */ -#define PIN_LED_1 {1 << 20, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} -/** LED #2 pin definition. */ -#define PIN_LED_2 {1 << 20, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -#endif - -/** List of all LEDs definitions. */ -#define PINS_LEDS PIN_LED_0, PIN_LED_1, PIN_LED_2 - -/** MCI pins definition. */ -#define PINS_MCI {0x3fUL << 26, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_PULLUP} -/** MCI pin Card Detect. */ -#define PIN_MCI_CD {PIO_PB7, PIOB, ID_PIOB, PIO_INPUT, PIO_PULLUP} - -/** Push button #0 definition. Attributes = pull-up + debounce + interrupt on rising edge. */ -#define PIN_PUSHBUTTON_1 {1 << 3, PIOB, ID_PIOB, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE} -/** Push button #1 definition. Attributes = pull-up + debounce + interrupt on falling edge. */ -#define PIN_PUSHBUTTON_2 {1 << 12, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE} -/** List of all push button definitions. */ -#define PINS_PUSHBUTTONS PIN_PUSHBUTTON_1, PIN_PUSHBUTTON_2 - -/** Push button #1 index. */ -#define PUSHBUTTON_BP1 0 -/** Push button #2 index. */ -#define PUSHBUTTON_BP2 1 - -/// Simulated joystick LEFT index. -#define JOYSTICK_LEFT 0 -/// Simulated joystick RIGHT index. -#define JOYSTICK_RIGHT 1 - -/** PWMC PWM0 pin definition. */ -#define PIN_PWMC_PWMH0 {1 << 18, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} -#define PIN_PWMC_PWML0 {1 << 19, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} -/** PWMC PWM1 pin definition. */ -#define PIN_PWMC_PWMH1 {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} -#define PIN_PWMC_PWML1 {1 << 20, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} -/** PWMC PWM2 pin definition. */ -#define PIN_PWMC_PWMH2 {1 << 20, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} -#define PIN_PWMC_PWML2 {1 << 16, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT} -/** PWMC PWM3 pin definition. */ -#define PIN_PWMC_PWMH3 {1 << 21, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} -#define PIN_PWMC_PWML3 {1 << 15, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT} -/** PWM pin definition for LED0 */ -#define PIN_PWM_LED0 PIN_PWMC_PWMH0, PIN_PWMC_PWML0 -/** PWM pin definition for LED1 */ -#define PIN_PWM_LED1 PIN_PWMC_PWMH2, PIN_PWMC_PWML2 -/** PWM pin definition for LED2 */ -#define PIN_PWM_LED2 PIN_PWMC_PWMH3, PIN_PWMC_PWML3 -/** PWM channel for LED0 */ -#define CHANNEL_PWM_LED0 0 -/** PWM channel for LED1 */ -#define CHANNEL_PWM_LED1 2 -/** PWM channel for LED2 */ -#define CHANNEL_PWM_LED2 3 - -/** SPI MISO pin definition. */ -#define PIN_SPI_MISO {1 << 12, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -/** SPI MOSI pin definition. */ -#define PIN_SPI_MOSI {1 << 13, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -/** SPI SPCK pin definition. */ -#define PIN_SPI_SPCK {1 << 14, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -/** SPI chip select pin definition. */ -#define PIN_SPI_NPCS0_PA11 {1 << 11, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -/** List of SPI pin definitions (MISO, MOSI & SPCK). */ -#define PINS_SPI PIN_SPI_MISO, PIN_SPI_MOSI, PIN_SPI_SPCK - -/// SSC pins definition. -#define PIN_SSC_TD {0x1 << 26, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_SSC_TK {0x1 << 28, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_SSC_TF {0x1 << 30, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PINS_SSC_CODEC PIN_SSC_TD, PIN_SSC_TK, PIN_SSC_TF - -/// PCK0 -#define PIN_PCK0 {0x1 << 21, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} - -/// TWI pins definition. -#define TWI_V3XX -#define PIN_TWI_TWD0 {0x1 << 9, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_TWI_TWCK0 {0x1 << 10, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PINS_TWI0 PIN_TWI_TWD0, PIN_TWI_TWCK0 -#define PIN_TWI_TWD1 {0x1 << 24, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_TWI_TWCK1 {0x1 << 25, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PINS_TWI1 PIN_TWI_TWD1, PIN_TWI_TWCK1 - -/// USART0 -#define PIN_USART0_RXD {0x1 << 19, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART0_TXD {0x1 << 18, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART0_CTS {0x1 << 8, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART0_RTS {0x1 << 7, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART0_SCK {0x1 << 17, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} - -/// USART1 -#define PIN_USART1_RXD {0x1 << 21, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART1_TXD {0x1 << 22, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART1_CTS {0x1 << 25, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART1_RTS {0x1 << 24, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART1_EN {0x1 << 23, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT} - -/// USB VBus monitoring pin definition. -#ifdef BOARD_REV_A -#define PIN_USB_VBUS {1 << 23, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} -#endif -#ifdef BOARD_REV_B -#define PIN_USB_VBUS {1 << 21, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} -#endif - -#define usbPlugged() (PIOC->PIO_PDSR & PIO_PC25) - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par sam3s_ek_extcomp "SAM3S-EK - External components" -/// This page lists the definitions related to external on-board components -/// located in the board.h file for the AT91SAM3S-EK. -/// -/// !AT45 Dataflash Card -/// - BOARD_AT45_A_SPI_BASE -/// - BOARD_AT45_A_SPI_ID -/// - BOARD_AT45_A_SPI_PINS -/// - BOARD_AT45_A_SPI -/// - BOARD_AT45_A_NPCS -/// - BOARD_AT45_A_NPCS_PIN -/// -/// !AT45 Dataflash (serial onboard DataFlash) -/// - BOARD_AT45_B_SPI_BASE -/// - BOARD_AT45_B_SPI_ID -/// - BOARD_AT45_B_SPI_PINS -/// - BOARD_AT45_B_SPI -/// - BOARD_AT45_B_NPCS -/// - BOARD_AT45_B_NPCS_PIN -/// -/// !AT26 Serial Flash -/// - BOARD_AT26_A_SPI_BASE -/// - BOARD_AT26_A_SPI_ID -/// - BOARD_AT26_A_SPI_PINS -/// - BOARD_AT26_A_SPI -/// - BOARD_AT26_A_NPCS -/// - BOARD_AT26_A_NPCS_PIN -/// -/// !SD Card -/// - MCI2_INTERFACE -/// - BOARD_SD_MCI_BASE -/// - BOARD_SD_MCI_ID -/// - BOARD_SD_PINS -/// - BOARD_SD_SLOT -/// -/// !PSRAM -/// - BOARD_PSRAM_PINS -/// -/// !LCD -/// - BOARD_LCD_ILI9325 -/// - BOARD_LCD_PINS -/// - BOARD_BACKLIGHT_PIN -/// - BOARD_LCD_BASE -/// - BOARD_LCD_RS -/// - BOARD_LCD_WIDTH -/// - BOARD_LCD_HEIGHT -/// -/// !TouchScreen -/// - BOARD_TSC_ADS7843 -/// - PIN_TCS_IRQ -/// - PIN_TCS_BUSY -/// - BOARD_TSC_SPI_BASE -/// - BOARD_TSC_SPI_ID -/// - BOARD_TSC_SPI_PINS -/// - BOARD_TSC_NPCS -/// - BOARD_TSC_NPCS_PIN -/// -/// Base address of SPI peripheral connected to the dataflash. -//#define BOARD_AT45_A_SPI_BASE SPI0 -///// Identifier of SPI peripheral connected to the dataflash. -//#define BOARD_AT45_A_SPI_ID ID_SPI0 -///// Pins of the SPI peripheral connected to the dataflash. -//#define BOARD_AT45_A_SPI_PINS PINS_SPI0 -///// Dataflahs SPI number. -//#define BOARD_AT45_A_SPI 0 -///// Chip select connected to the dataflash. -//#define BOARD_AT45_A_NPCS 3 -///// Chip select pin connected to the dataflash. -//#define BOARD_AT45_A_NPCS_PIN PIN_SPI0_NPCS3 - -/// Base address of SPI peripheral connected to the dataflash. -//#define BOARD_AT45_B_SPI_BASE SPI1 -///// Identifier of SPI peripheral connected to the dataflash. -//#define BOARD_AT45_B_SPI_ID ID_SPI1 -///// Pins of the SPI peripheral connected to the dataflash. -//#define BOARD_AT45_B_SPI_PINS PINS_SPI1 -///// Dataflahs SPI number. -//#define BOARD_AT45_B_SPI 1 -///// Chip select connected to the dataflash. -//#define BOARD_AT45_B_NPCS 3 -///// Chip select pin connected to the dataflash. -//#define BOARD_AT45_B_NPCS_PIN PIN_SPI1_NPCS3 - -/// Base address of SPI peripheral connected to the serialflash. -//#define BOARD_AT26_A_SPI_BASE SPI0 -///// Identifier of SPI peripheral connected to the serialflash. -//#define BOARD_AT26_A_SPI_ID ID_SPI0 -///// Pins of the SPI peripheral connected to the serialflash. -//#define BOARD_AT26_A_SPI_PINS PINS_SPI0 -///// Serialflash SPI number. -//#define BOARD_AT26_A_SPI 0 -///// Chip select connected to the serialflash. -//#define BOARD_AT26_A_NPCS 3 -///// Chip select pin connected to the serialflash. -//#define BOARD_AT26_A_NPCS_PIN PIN_SPI0_NPCS3 - -/// ISO7816 -/// - PIN_SMARTCARD_CONNECT -/// - PIN_ISO7816_RSTMC -/// - PINS_ISO7816 - -/// Smartcard detection pin -//#define PIN_SMARTCARD_CONNECT {1 << 5, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} -/// PIN used for reset the smartcard -//#define PIN_ISO7816_RSTMC {1 << 7, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT} -/// Pins used for connect the smartcard -//#define PINS_ISO7816 PIN_USART0_TXD, PIN_USART0_SCK, PIN_ISO7816_RSTMC - -/// Dma channel number -#define BOARD_MCI_DMA_CHANNEL 0 -/// MCI0 DMA hardware handshaking ID -#define DMA_HW_SRC_REQ_ID_MCI0 AT91C_HDMA_SRC_PER_0 -#define DMA_HW_DEST_REQ_ID_MCI0 AT91C_HDMA_DST_PER_0 -/// MCI1 DMA hardware handshaking ID -#define DMA_HW_SRC_REQ_ID_MCI1 AT91C_HDMA_SRC_PER_13 -#define DMA_HW_DEST_REQ_ID_MCI1 AT91C_HDMA_DST_PER_13 -/// SD DMA hardware handshaking ID -#define BOARD_SD_DMA_HW_SRC_REQ_ID DMA_HW_SRC_REQ_ID_MCI0 -#define BOARD_SD_DMA_HW_DEST_REQ_ID DMA_HW_DEST_REQ_ID_MCI0 - - -/// HS MCI interface -#define MCI2_INTERFACE -/// Base address of the MCI peripheral connected to the SD card. -#define BOARD_SD_MCI_BASE MCI0//MCI -///// Peripheral identifier of the MCI connected to the SD card. -#define BOARD_SD_MCI_ID AT91C_ID_MCI0 ID_MCI0 //ID_MCI -///// MCI pins that shall be configured to access the SD card. -#define BOARD_SD_PINS PINS_MCI -///// MCI slot to which the SD card is connected to. -#define BOARD_SD_SLOT MCI_SD_SLOTA -///// MCI Card Detect pin. -#define BOARD_SD_PIN_CD PIN_MCI_CD - -#define BLOCK_SIZE 512 -#define MSD_BUFFER_SIZE (12*BLOCK_SIZE) // Size of the MSD IO buffer in bytes (6K, more the better) -#define SD_CARD_PRESENT() ( (PIOB->PIO_PDSR & PIO_PB7) == 0 ) - -// States for initialising card -#define SD_ST_ERR -1 -#define SD_ST_STARTUP 0 -#define SD_ST_EMPTY 1 -#define SD_ST_INIT1 2 -#define SD_ST_INIT2 3 -#define SD_ST_IDLE 4 -#define SD_ST_READY 5 -#define SD_ST_IDENT 6 -#define SD_ST_STBY 7 -#define SD_ST_TRAN 8 -#define SD_ST_DATA 9 -#define SD_ST_MOUNTED 10 - -extern uint32_t Cmd_A41_resp; -extern int32_t Card_state; -extern volatile uint32_t Card_initialized; -extern uint32_t Card_CSD[4]; -extern uint32_t transSpeed; - -#define OCR_SD_CCS (1UL << 30) - -#define SD_CSD(csd, bitfield, bits) ((csd[3-(bitfield)/32] >> ((bitfield)%32)) & ((1 << (bits)) - 1)) - -#define SD_CSD_TRAN_SPEED(pSd) SD_CSD(pSd, 96, 8) ///< Max. data transfer rate - -#define SD_CSD_C_SIZE(pSd) ((SD_CSD(pSd, 72, 2) << 10) + \ - (SD_CSD(pSd, 64, 8) << 2) + \ - SD_CSD(pSd, 62, 2)) ///< Device size - -#define SD_CSD_C_SIZE_HC(csd) ((SD_CSD(csd, 64, 6) << 16) + \ - (SD_CSD(csd, 56, 8) << 8) + \ - SD_CSD(csd, 48, 8)) ///< Device size v2.0 High Capacity - -#define SD_CSD_C_SIZE_MULT(pSd) SD_CSD(pSd, 47, 3) ///< Device size multiplier - -#define SD_CSD_MULT(pSd) (1 << (SD_CSD_C_SIZE_MULT(pSd) + 2)) - -#define SD_CSD_READ_BL_LEN(pSd) SD_CSD(pSd, 80, 4) ///< Max. read data block length - -#define SD_CSD_BLKLEN(pSd) (1 << (SD_CSD_READ_BL_LEN(pSd) - 9)) - -#define SD_CSD_BLOCKNR(pSd) ((SD_CSD_C_SIZE(pSd) + 1) * SD_CSD_MULT(pSd)) * SD_CSD_BLKLEN(pSd) - -#define SD_CSD_BLOCKNR_HC(pSd) ((SD_CSD_C_SIZE_HC(pSd) + 1) * 1024) - -#if !defined(SIMU) - #define SD_IS_HC() (Cmd_A41_resp & OCR_SD_CCS) - #define SD_GET_BLOCKNR() (SD_IS_HC() ? (SD_CSD_BLOCKNR_HC(Card_CSD)) : (SD_CSD_BLOCKNR(Card_CSD))) - #define SD_GET_SPEED() (transSpeed) -#else - #define SD_IS_HC() (0) - #define SD_GET_BLOCKNR() (0) - #define SD_GET_SPEED() (0) -#endif - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par sam3s_ek_mem "SAM3S-EK - Memories" -/// This page lists definitions related to internal & external on-board memories. -/// -/// !Embedded Flash -/// - BOARD_FLASH_EFC - -/// Internal SRAM address -#define AT91C_ISRAM AT91C_IRAM -#define AT91C_ISRAM_SIZE 0x00008000 - -#define AT91C_IFLASH_SIZE (0x40000) -#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH 0 Page Size: 256 bytes -#define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH 0 Number of Pages: 512 -#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH 0 Lock Region Size: 16 Kbytes -#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH 0 Number of Lock Bits: 16 - -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -/// \section sam3s_ek_extcomp "SAM3S-EK - External components" -/// This page lists the definitions related to external on-board components -/// located in the board.h file for the SAM3S-EK. -/// -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par sam3s_ek_chipdef "SAM3S-EK - Individual chip definition" -/// This page lists the definitions related to different chip's definition -/// located in the board.h file for the SAM3S-EK. - -/// DBGU -#define BOARD_DBGU_ID ID_DBGU - -/// Rtc -#define BOARD_RTC_ID ID_RTC - -/// Twi eeprom -#define BOARD_ID_TWI_EEPROM ID_TWI1 -#define BOARD_BASE_TWI_EEPROM TWI1 -#define BOARD_PINS_TWI_EEPROM PINS_TWI1 - -/// USART -#define BOARD_PIN_USART_RXD PIN_USART1_RXD -#define BOARD_PIN_USART_TXD PIN_USART1_TXD -#define BOARD_PIN_USART_CTS PIN_USART1_CTS -#define BOARD_PIN_USART_RTS PIN_USART1_RTS -#define BOARD_PIN_USART_EN PIN_USART1_EN -#define BOARD_USART_BASE USART1 -#define BOARD_ID_USART ID_USART1 - -// BlueTooth -#define BT_USART UART1 -#define BT_ID ID_UART1 - -//------------------------------------------------------------------------------ - - -#define PIN_EBI_NANDOE {1 << 9, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NANDWE {1 << 10, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NANDCLE {1 << 17, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NANDALE {1 << 16, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NANDIO {0x000000FF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} - -/// Nandflash chip enable pin definition. -#define BOARD_NF_CE_PIN {1 << 14, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -/// Nandflash ready/busy pin definition. -#define BOARD_NF_RB_PIN {1 << 18, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP} - -/// Nandflash controller peripheral pins definition. -#define PINS_NANDFLASH PIN_EBI_NANDIO, BOARD_NF_CE_PIN, BOARD_NF_RB_PIN, PIN_EBI_NANDOE, \ - PIN_EBI_NANDWE, PIN_EBI_NANDCLE, PIN_EBI_NANDALE - -/// Address for transferring command bytes to the nandflash. -#define BOARD_NF_COMMAND_ADDR 0x60400000 -/// Address for transferring address bytes to the nandflash. -#define BOARD_NF_ADDRESS_ADDR 0x60200000 -/// Address for transferring data bytes to the nandflash. -#define BOARD_NF_DATA_ADDR 0x60000000 - -extern uint32_t Master_frequency ; - -struct t_serial_tx -{ - uint8_t *buffer ; - uint16_t size ; - volatile uint16_t ready ; -}; - -#endif // _BOARD_H_ diff --git a/radio/src/targets/sky9x/buzzer_driver.cpp b/radio/src/targets/sky9x/buzzer_driver.cpp deleted file mode 100644 index d258d8bd9..000000000 --- a/radio/src/targets/sky9x/buzzer_driver.cpp +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -volatile uint8_t buzzerCount ; - -void buzzerOn() -{ - PIOA->PIO_SODR = 0x02000000L ; // Set bit A25 ON -} - -void buzzerOff() -{ - PIOA->PIO_CODR = 0x02000000L ; // Set bit A25 ON -} - -void buzzerSound(uint8_t duration) -{ - buzzerOn(); - buzzerCount = duration; -} - -void buzzerHeartbeat() -{ - if (buzzerCount) { - if (--buzzerCount == 0) - buzzerOff(); - } -} diff --git a/radio/src/targets/sky9x/chip.h b/radio/src/targets/sky9x/chip.h deleted file mode 100644 index d3f669a04..000000000 --- a/radio/src/targets/sky9x/chip.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Definition of AT91SAM3S4 characteristics and features -/// -/// !Usage -/// -# For ARM core feature, see "AT91SAM3S4 - ARM core features". -/// -# For IP features, see "AT91SAM3S4 - IP features". -/// -# For misc, see "AT91SAM3S4 - Misc". -//------------------------------------------------------------------------------ - -#ifndef _CHIP_H_ -#define _CHIP_H_ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "AT91SAM3S4 - ARM core features" -/// This page lists several characteristics related to the ARM core -/// - -//ARM core features - -/// ARM core definition. -#define cortexm3 - -/// family definition. -#define at91sam3s - -//------------------------------------------------------------------------------ -/// \page "AT91SAM3S4 - IP features" -/// This page lists several characteristics related to the embedded IP -/// - -//IP FEATURES - -// EFC GPNVM number -#define CHIP_EFC_NUM_GPNVMS 3 - -/// Indicates chip has an Enhanced EFC. -#define CHIP_FLASH_EEFC - -// DMA channels number -#define CHIP_DMA_CHANNEL_NUM 4 - -// Indicate chip's MCI interface. -#define MCI2_INTERFACE - -// Indicate chip SSC has DMA interface. -#define CHIP_SSC_DMA - -// Indicate chip SPI has DMA interface. -#define CHIP_SPI_DMA - -/// Indicates chip has an UDP Full Speed. -#define CHIP_USB_UDP - -/// Indicates chip has an internal pull-up. -#define CHIP_USB_PULLUP_INTERNAL - -/// Number of USB endpoints -#define CHIP_USB_NUMENDPOINTS 8 - -/// Endpoints max paxcket size -#define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(i) \ - ((i == 0) ? 64 : \ - ((i == 1) ? 64 : \ - ((i == 2) ? 64 : \ - ((i == 3) ? 64 : \ - ((i == 4) ? 512 : \ - ((i == 5) ? 512 : \ - ((i == 6) ? 64 : \ - ((i == 7) ? 64 : 0 )))))))) - -/// Endpoints Number of Bank -#define CHIP_USB_ENDPOINTS_BANKS(i) \ - ((i == 0) ? 1 : \ - ((i == 1) ? 2 : \ - ((i == 2) ? 2 : \ - ((i == 3) ? 1 : \ - ((i == 4) ? 2 : \ - ((i == 5) ? 2 : \ - ((i == 6) ? 2 : \ - ((i == 7) ? 2 : 0 )))))))) - -//------------------------------------------------------------------------------ -/// \page "AT91SAM3S4 - Misc " -/// This page lists misc features -/// - -//Misc - -#endif // _CHIP_H_ - diff --git a/radio/src/targets/sky9x/coproc_driver.cpp b/radio/src/targets/sky9x/coproc_driver.cpp deleted file mode 100644 index 8040cc0c8..000000000 --- a/radio/src/targets/sky9x/coproc_driver.cpp +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -int8_t volumeRequired ; -uint8_t coprocReadDataPending ; -uint8_t coprocWriteDataPending ; -uint8_t CoProc_appgo_pending ; -uint8_t Volume_read ; -CoprocData coprocData; -bool get_onlytemp; -#if !defined(SIMU) -// TODO not used? static uint8_t *Twi_read_address ; -#endif -static uint8_t TwiOperation ; - -#define TWI_NONE 0 -#define TWI_WRITE_VOL 2 -#define TWI_READ_COPROC 3 -#define TWI_COPROC_APPGO 4 -#define TWI_WAIT_STOP 5 -#define TWI_WRITE_COPROC 6 - -// Commands to the coprocessor bootloader/application -#define TWI_CMD_PAGEUPDATE 0x01 // TWI Command to program a flash page -#define TWI_CMD_EXECUTEAPP 0x02 // TWI Command to jump to the application program -#define TWI_CMD_SETREAD_ADDRESS 0x03 // TWI Command to set address to read from -#define TWI_CMD_WRITE_DATA 0x04 // TWI Command send data to the application -#define COPROC_RX_BUXSIZE 22 -uint8_t Co_proc_status[COPROC_RX_BUXSIZE] ; -uint8_t *coprocWriteDataPtr ; -uint32_t coprocWriteDataSize ; - - -// This is called from an interrupt routine, or -// interrupts must be disabled while it is called -// from elsewhere. -void i2cCheck() -{ - if ( TWI0->TWI_IMR & TWI_IMR_TXCOMP ) { - return ; // Busy - } - - if ( volumeRequired >= 0 ) { // Set volume to this value - TWI0->TWI_MMR = 0x002F0000 ; // Device 5E (>>1) and master is writing - TwiOperation = TWI_WRITE_VOL ; - TWI0->TWI_THR = volumeRequired ; // Send data - volumeRequired = -1 ; - TWI0->TWI_IER = TWI_IER_TXCOMP ; - TWI0->TWI_CR = TWI_CR_STOP ; // Stop Tx - } - else if (coprocReadDataPending) { - coprocData.valid = 0 ; - coprocReadDataPending = 0 ; - TWI0->TWI_MMR = 0x00351000 ; // Device 35 and master is reading - TwiOperation = TWI_READ_COPROC ; -#ifndef SIMU - TWI0->TWI_RPR = (uint32_t)&Co_proc_status[0] ; -#endif - TWI0->TWI_RCR = COPROC_RX_BUXSIZE - 1 ; - if ( TWI0->TWI_SR & TWI_SR_RXRDY ) { - (void) TWI0->TWI_RHR ; - } - TWI0->TWI_PTCR = TWI_PTCR_RXTEN ; // Start transfers - TWI0->TWI_CR = TWI_CR_START ; // Start Rx - TWI0->TWI_IER = TWI_IER_RXBUFF | TWI_IER_TXCOMP ; - } - else if ( CoProc_appgo_pending ) { - CoProc_appgo_pending = 0 ; - TWI0->TWI_MMR = 0x00350000 ; // Device 35 and master is writing - TwiOperation = TWI_COPROC_APPGO ; - TWI0->TWI_THR = TWI_CMD_EXECUTEAPP ; // Send appgo command - TWI0->TWI_IER = TWI_IER_TXCOMP ; - TWI0->TWI_CR = TWI_CR_STOP ; // Stop Tx - } - else if ( coprocWriteDataPending ) { - coprocWriteDataPending = 0 ; - TWI0->TWI_MMR = 0x00350000 ; // Device 35 and master is writing - TwiOperation = TWI_WRITE_COPROC ; -#ifndef SIMU - TWI0->TWI_TPR = (uint32_t)coprocWriteDataPtr ; -#endif - TWI0->TWI_TCR = coprocWriteDataSize ; - TWI0->TWI_THR = TWI_CMD_WRITE_DATA ; // Send write command - TWI0->TWI_PTCR = TWI_PTCR_TXTEN ; // Start data transfer - TWI0->TWI_IER = TWI_IER_TXBUFE | TWI_IER_TXCOMP ; - } -} - -void coprocReadData(bool onlytemp) -{ - get_onlytemp = onlytemp; - coprocReadDataPending = 1 ; - __disable_irq() ; - i2cCheck() ; - __enable_irq() ; -} - -void coprocWriteData(uint8_t *data, uint32_t size) -{ - coprocWriteDataPtr = data; - coprocWriteDataSize = size; - coprocWriteDataPending = 1; - __disable_irq(); - i2cCheck(); - __enable_irq(); -} - -#if !defined(SIMU) -extern "C" void TWI0_IRQHandler() -{ - if ( TwiOperation == TWI_READ_COPROC ) - { - if ( TWI0->TWI_SR & TWI_SR_RXBUFF ) - { - TWI0->TWI_IDR = TWI_IDR_RXBUFF ; - TwiOperation = TWI_WAIT_STOP ; - TWI0->TWI_CR = TWI_CR_STOP ; // Stop Rx - TWI0->TWI_RCR = 1 ; // Last byte - return ; - } - else - { - coprocData.valid = -1 ; - } - } - - if ( TwiOperation == TWI_WAIT_STOP ) - { - coprocData.valid = 1 ; - coprocData.read = Co_proc_status[0] ; - if ( coprocData.read & 0x80 ) { - // Bootloader - CoProc_appgo_pending = 1 ; // Action application - } - else { - // Got data from tiny app - // Set the date and time - struct gtm utm; - if (!get_onlytemp) { - utm.tm_sec = Co_proc_status[1] ; - utm.tm_min = Co_proc_status[2] ; - utm.tm_hour = Co_proc_status[3] ; - utm.tm_mday = Co_proc_status[4] ; - utm.tm_mon = Co_proc_status[5] - 1; - utm.tm_year = (Co_proc_status[6] + ( Co_proc_status[7] << 8 )) - TM_YEAR_BASE; - g_rtcTime = gmktime(&utm); - } - coprocData.temp = Co_proc_status[8]; - if (coprocData.temp > coprocData.maxtemp) - coprocData.maxtemp = coprocData.temp; - } - TWI0->TWI_PTCR = TWI_PTCR_RXTDIS ; // Stop transfers - if ( TWI0->TWI_SR & TWI_SR_RXRDY ) { - (void) TWI0->TWI_RHR ; // Discard any rubbish data - } - } - -// if ( TwiOperation == TWI_WRITE_VOL ) -// { - -// } - - if ( TwiOperation == TWI_WRITE_COPROC ) - { - if ( TWI0->TWI_SR & TWI_SR_TXBUFE ) - { - TWI0->TWI_IDR = TWI_IDR_TXBUFE ; - TWI0->TWI_CR = TWI_CR_STOP ; // Stop Tx - TWI0->TWI_PTCR = TWI_PTCR_TXTDIS ; // Stop transfers - TwiOperation = TWI_NONE ; - return ; - } - } - - TWI0->TWI_IDR = TWI_IDR_TXCOMP | TWI_IDR_TXBUFE | TWI_IDR_RXBUFF ; - TWI0->TWI_PTCR = TWI_PTCR_TXTDIS | TWI_PTCR_RXTDIS ; // Stop transfers - if ( TWI0->TWI_SR & TWI_SR_NACK ) - { - } - TwiOperation = TWI_NONE ; - i2cCheck() ; -} -#endif diff --git a/radio/src/targets/sky9x/core_cm3.c b/radio/src/targets/sky9x/core_cm3.c deleted file mode 100644 index 0137855da..000000000 --- a/radio/src/targets/sky9x/core_cm3.c +++ /dev/null @@ -1,868 +0,0 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - -uint32_t __get_PSP(void) ; -void __set_PSP(uint32_t topOfProcStack) ; -uint32_t __get_MSP(void) ; -void __set_MSP(uint32_t mainStackPointer) ; -uint32_t __REV16(uint16_t value) ; -int32_t __REVSH(int16_t value) ; -uint32_t __RBIT(uint32_t value) ; -uint8_t __LDREXB(uint8_t *addr) ; -uint16_t __LDREXH(uint16_t *addr) ; -uint32_t __LDREXW(uint32_t *addr) ; -uint32_t __STREXB(uint8_t value, uint8_t *addr) ; -uint32_t __STREXH(uint16_t value, uint16_t *addr) ; -uint32_t __STREXW(uint32_t value, uint32_t *addr) ; - -uint32_t __get_BASEPRI(void) ; -void __set_BASEPRI(uint32_t basePri) ; -uint32_t __get_PRIMASK(void) ; -void __set_PRIMASK(uint32_t priMask) ; -uint32_t __get_FAULTMASK(void) ; -void __set_FAULTMASK(uint32_t faultMask) ; -uint32_t __get_CONTROL(void) ; -void __set_CONTROL(uint32_t control) ; -uint32_t __REV(uint32_t value) ; - -void revert_osc( void ) ; -void sam_boot( void ) ; -void sam_bootx( void ) ; -void run_application( void ) ; - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -__ASM uint32_t __get_PSP(void) -{ - mrs r0, psp - bx lr -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -__ASM void __set_PSP(uint32_t topOfProcStack) -{ - msr psp, r0 - bx lr -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -__ASM uint32_t __get_MSP(void) -{ - mrs r0, msp - bx lr -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -__ASM void __set_MSP(uint32_t mainStackPointer) -{ - msr msp, r0 - bx lr -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -__ASM uint32_t __REV16(uint16_t value) -{ - rev16 r0, r0 - bx lr -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -__ASM int32_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -__ASM void __CLREX(void) -{ - clrex -} - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -__ASM uint32_t __get_BASEPRI(void) -{ - mrs r0, basepri - bx lr -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -__ASM void __set_BASEPRI(uint32_t basePri) -{ - msr basepri, r0 - bx lr -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -__ASM uint32_t __get_PRIMASK(void) -{ - mrs r0, primask - bx lr -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -__ASM void __set_PRIMASK(uint32_t priMask) -{ - msr primask, r0 - bx lr -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -__ASM uint32_t __get_FAULTMASK(void) -{ - mrs r0, faultmask - bx lr -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -__ASM void __set_FAULTMASK(uint32_t faultMask) -{ - msr faultmask, r0 - bx lr -} - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -__ASM uint32_t __get_CONTROL(void) -{ - mrs r0, control - bx lr -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -__ASM void __set_CONTROL(uint32_t control) -{ - msr control, r0 - bx lr -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#pragma diag_suppress=Pe940 - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) -{ - __ASM("mrs r0, psp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM("msr psp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) -{ - __ASM("mrs r0, msp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM("msr msp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - __ASM("rev16 r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - __ASM("rbit r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit values) - */ -uint8_t __LDREXB(uint8_t *addr) -{ - __ASM("ldrexb r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -uint16_t __LDREXH(uint16_t *addr) -{ - __ASM("ldrexh r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -uint32_t __LDREXW(uint32_t *addr) -{ - __ASM("ldrex r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - __ASM("strexb r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - __ASM("strexh r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - __ASM("strex r0, r0, [r1]"); - __ASM("bx lr"); -} - -#pragma diag_default=Pe940 - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -#if !defined(BOOT) -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -/*extern uint32_t __get_PSP(void) __attribute__( ( naked ) ); */ -uint32_t __get_PSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, psp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -/*void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); */ -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n\t" - "BX lr \n\t" : : "r" (topOfProcStack) ); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -/*uint32_t __get_MSP(void) __attribute__( ( naked ) ); */ -uint32_t __get_MSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, msp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -/*void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); */ -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n\t" - "BX lr \n\t" : : "r" (topOfMainStack) ); -} - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -uint32_t __get_BASEPRI(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -uint32_t __get_PRIMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -uint32_t __get_FAULTMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -uint32_t __get_CONTROL(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} -#endif - -/** - * @brief Reverse byte order in integer value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -uint32_t __REV(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#if !defined(BOOT) -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -int32_t __REVSH(int16_t value) -{ - uint32_t result=0; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -uint8_t __LDREXB(uint8_t *addr) -{ - uint8_t result=0; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -uint16_t __LDREXH(uint16_t *addr) -{ - uint16_t result=0; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -uint32_t __LDREXW(uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} -#endif - -#if defined(BOOT) -void run_application() -{ - __ASM(" mov.w r1, #4227072"); // 0x408000 - __ASM(" movw r0, #60680"); // 0xED08 - __ASM(" movt r0, #57344"); // 0xE000 - __ASM(" str r1, [r0, #0]"); // Set the VTOR - __ASM("ldr r0, [r1, #0]"); // Stack pointer value - __ASM("msr msp, r0"); // Set it - __ASM("ldr r0, [r1, #4]"); // Reset address - __ASM("mov.w r1, #1"); - __ASM("orr r0, r1"); // Set lsbit - __ASM("bx r0"); // Execute application -} -#endif - -#if !defined(BOOT) -void sam_boot() -{ - revert_osc() ; - - __ASM(" mov.w r1, #8388608"); - __ASM(" movw r0, #60680"); - __ASM(" movt r0, #57344"); - __ASM(" str r1, [r0, #0]"); // Set the VTOR - - __ASM("mov.w r3, #0"); - __ASM("movt r3, #128"); - __ASM("ldr r0, [r3, #0]"); - __ASM("msr msp, r0"); - __ASM("ldr r0, [r3, #4]"); - __ASM("mov.w r3, #1"); - __ASM("orr r0, r3"); - __ASM("bx r0"); -} -#endif - -#if defined(BOOT) -void sam_bootx() -{ - __ASM(" mov.w r1, #8388608"); - __ASM(" movw r0, #60680"); - __ASM(" movt r0, #57344"); - __ASM(" str r1, [r0, #0]"); // Set the VTOR - - __ASM("mov.w r3, #0"); - __ASM("movt r3, #128"); - __ASM("ldr r0, [r3, #0]"); - __ASM("msr msp, r0"); - __ASM("ldr r0, [r3, #4]"); - __ASM("mov.w r3, #1"); - __ASM("orr r0, r3"); - __ASM("bx r0"); -} -#endif - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif diff --git a/radio/src/targets/sky9x/core_cm3.h b/radio/src/targets/sky9x/core_cm3.h deleted file mode 100644 index 4e51e5c64..000000000 --- a/radio/src/targets/sky9x/core_cm3.h +++ /dev/null @@ -1,1816 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _CORE_CM3_H_ -#define _CORE_CM3_H_ - -/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration - * - * List of Lint messages which will be suppressed and not shown: - * - Error 10: \n - * register uint32_t __regBasePri __asm("basepri"); \n - * Error 10: Expecting ';' - * . - * - Error 530: \n - * return(__regBasePri); \n - * Warning 530: Symbol '__regBasePri' (line 264) not initialized - * . - * - Error 550: \n - * __regBasePri = (basePri & 0x1ff); \n - * Warning 550: Symbol '__regBasePri' (line 271) not accessed - * . - * - Error 754: \n - * uint32_t RESERVED0[24]; \n - * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced - * . - * - Error 750: \n - * #define __CM3_CORE_H__ \n - * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced - * . - * - Error 528: \n - * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n - * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced - * . - * - Error 751: \n - * } InterruptType_Type; \n - * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced - * . - * Note: To re-enable a Message, insert a space before 'lint' * - * - */ - -/*lint -save */ -/*lint -e10 */ -/*lint -e530 */ -/*lint -e550 */ -/*lint -e754 */ -/*lint -e750 */ -/*lint -e528 */ -/*lint -e751 */ - - -/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core registers and bitfields - - Cortex-M core peripheral base address - @{ - */ - -#ifdef __cplusplus - extern "C" { -#endif - -#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - -#include /* Include standard types */ - -#if defined (__ICCARM__) - #include /* IAR Intrinsics */ -#endif - - -#ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ -#endif - - - - -/** - * IO definitions - * - * define access restrictions to peripheral registers - */ - -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register - @{ -*/ - - -/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC - memory mapped structure for Nested Vectored Interrupt Controller (NVIC) - @{ - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ -} NVIC_Type; -/*@}*/ /* end of group CMSIS_CM3_NVIC */ - - -/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB - memory mapped structure for System Control Block (SCB) - @{ - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (0x1ul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ -/*@}*/ /* end of group CMSIS_CM3_SCB */ - - -/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick - memory mapped structure for SysTick - @{ - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ -/*@}*/ /* end of group CMSIS_CM3_SysTick */ - - -/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM - memory mapped structure for Instrumentation Trace Macrocell (ITM) - @{ - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ - __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ - __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ -/*@}*/ /* end of group CMSIS_CM3_ITM */ - - -/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type - memory mapped structure for Interrupt Type - @{ - */ -typedef struct -{ - uint32_t RESERVED0; - __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ -#else - uint32_t RESERVED1; -#endif -} InterruptType_Type; - -/* Interrupt Controller Type Register Definitions */ -#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ -#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ -#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ - -#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ -#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ - -#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ -#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ -/*@}*/ /* end of group CMSIS_CM3_InterruptType */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) -/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU - memory mapped structure for Memory Protection Unit (MPU) - @{ - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ -#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ -#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ -#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ -#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ -#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ -#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@}*/ /* end of group CMSIS_CM3_MPU */ -#endif - - -/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug - memory mapped structure for Core Debug Register - @{ - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ -/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ - - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ - -#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ -#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_register */ - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#define __enable_fault_irq __enable_fiq -#define __disable_fault_irq __disable_fiq - -#define __NOP __nop -#define __WFI __wfi -#define __WFE __wfe -#define __SEV __sev -#define __ISB() __isb(0) -#define __DSB() __dsb(0) -#define __DMB() __dmb(0) -#define __REV __rev -#define __RBIT __rbit -#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) -#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) -#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) -#define __STREXB(value, ptr) __strex(value, ptr) -#define __STREXH(value, ptr) __strex(value, ptr) -#define __STREXW(value, ptr) __strex(value, ptr) - - -/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ -/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -extern void __CLREX(void); - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -#else /* (__ARMCC_VERSION >= 400000) */ - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -#define __CLREX __clrex - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -static __INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & 1); -} - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -static __INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ -#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ - -static __INLINE void __enable_fault_irq( void ) { __ASM ("cpsie f"); } -static __INLINE void __disable_fault_irq( void ) { __ASM ("cpsid f"); } - -#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ -static __INLINE void __WFI( void ) { __ASM ("wfi"); } -static __INLINE void __WFE( void ) { __ASM ("wfe"); } -static __INLINE void __SEV( void ) { __ASM ("sev"); } -static __INLINE void __CLREX( void ) { __ASM ("clrex"); } - -/* intrinsic void __ISB(void) */ -/* intrinsic void __DSB(void) */ -/* intrinsic void __DMB(void) */ -/* intrinsic void __set_PRIMASK(); */ -/* intrinsic void __get_PRIMASK(); */ -/* intrinsic void __set_FAULTMASK(); */ -/* intrinsic void __get_FAULTMASK(); */ -/* intrinsic uint32_t __REV(uint32_t value); */ -/* intrinsic uint32_t __REVSH(uint32_t value); */ -/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ -/* intrinsic unsigned long __LDREX(unsigned long *); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit values) - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -static __INLINE void __enable_irq(void) { __ASM volatile ("cpsie i"); } -static __INLINE void __disable_irq(void) { __ASM volatile ("cpsid i"); } - -static __INLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f"); } -static __INLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f"); } - -static __INLINE void __NOP(void) { __ASM volatile ("nop"); } -static __INLINE void __WFI(void) { __ASM volatile ("wfi"); } -static __INLINE void __WFE(void) { __ASM volatile ("wfe"); } -static __INLINE void __SEV(void) { __ASM volatile ("sev"); } -static __INLINE void __ISB(void) { __ASM volatile ("isb"); } -static __INLINE void __DSB(void) { __ASM volatile ("dsb"); } -static __INLINE void __DMB(void) { __ASM volatile ("dmb"); } -static __INLINE void __CLREX(void) { __ASM volatile ("clrex"); } - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -/** - * @brief Reverse byte order in integer value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -extern uint32_t __REV(uint32_t value); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - - -/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface - Core Function Interface containing: - - Core NVIC Functions - - Core SysTick Functions - - Core Reset Functions -*/ -/*@{*/ - -/* ########################## NVIC functions #################################### */ - -/** - * @brief Set the Priority Grouping in NVIC Interrupt Controller - * - * @param PriorityGroup is priority grouping field - * - * Set the priority grouping field using the required unlock sequence. - * The parameter priority_grouping is assigned to the field - * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - (0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - -/** - * @brief Get the Priority Grouping from NVIC Interrupt Controller - * - * @return priority grouping field - * - * Get the priority grouping from NVIC Interrupt Controller. - * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - -/** - * @brief Enable Interrupt in NVIC Interrupt Controller - * - * @param IRQn The positive number of the external interrupt to enable - * - * Enable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - -/** - * @brief Disable the interrupt line for external interrupt specified - * - * @param IRQn The positive number of the external interrupt to disable - * - * Disable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - -/** - * @brief Read the interrupt pending bit for a device specific interrupt source - * - * @param IRQn The number of the device specifc interrupt - * @return 1 = interrupt pending, 0 = interrupt not pending - * - * Read the pending register in NVIC and return 1 if its status is pending, - * otherwise it returns 0 - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - -/** - * @brief Set the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for set pending - * - * Set the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - -/** - * @brief Clear the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for clear pending - * - * Clear the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - -/** - * @brief Read the active bit for an external interrupt - * - * @param IRQn The number of the interrupt for read active bit - * @return 1 = interrupt active, 0 = interrupt not active - * - * Read the active register in NVIC and returns 1 if its status is active, - * otherwise it returns 0. - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - -/** - * @brief Set the priority for an interrupt - * - * @param IRQn The number of the interrupt for set priority - * @param priority The priority to set - * - * Set the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - -/** - * @brief Read the priority for an interrupt - * - * @param IRQn The number of the interrupt for get priority - * @return The priority for the interrupt - * - * Read the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * The returned priority value is automatically aligned to the implemented - * priority bits of the microcontroller. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** - * @brief Encode the priority for an interrupt - * - * @param PriorityGroup The used priority group - * @param PreemptPriority The preemptive priority value (starting from 0) - * @param SubPriority The sub priority value (starting from 0) - * @return The encoded priority for the interrupt - * - * Encode the priority for an interrupt with the given priority group, - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The returned priority value can be used for NVIC_SetPriority(...) function - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** - * @brief Decode the priority of an interrupt - * - * @param Priority The priority for the interrupt - * @param PriorityGroup The used priority group - * @param pPreemptPriority The preemptive priority value (starting from 0) - * @param pSubPriority The sub priority value (starting from 0) - * - * Decode an interrupt priority value with the given priority group to - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The priority value can be retrieved with NVIC_GetPriority(...) function - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - - -/* ################################## SysTick function ############################################ */ - -#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) - -/** - * @brief Initialize and start the SysTick counter and its interrupt. - * - * @param ticks number of ticks between two interrupts - * @return 1 = failed, 0 = successful - * - * Initialise the system tick timer and its interrupt and start the - * system tick timer / counter in free running mode to generate - * periodical interrupts. - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - - - - -/* ################################## Reset function ############################################ */ - -/** - * @brief Initiate a system reset request. - * - * Initiate a system reset request to reset the MCU - */ -static __INLINE void NVIC_SystemReset(void) -{ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ - - - -/* ##################################### Debug In/Output function ########################################### */ - -/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface - Core Debug Interface containing: - - Core Debug Receive / Transmit Functions - - Core Debug Defines - - Core Debug Variables -*/ -/*@{*/ - -extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** - * @brief Outputs a character via the ITM channel 0 - * - * @param ch character to output - * @return character to output - * - * The function outputs a character via the ITM channel 0. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** - * @brief Inputs a character via variable ITM_RxBuffer - * - * @return received character, -1 = no character received - * - * The function inputs a character via variable ITM_RxBuffer. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE int ITM_ReceiveChar (void) { - int ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - * @brief Check if a character via variable ITM_RxBuffer is available - * - * @return 1 = character available, 0 = no character available - * - * The function checks variable ITM_RxBuffer whether a character is available or not. - * The function returns '1' if a character is available and '0' if no character is available. - */ -static __INLINE int ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_definitions */ - -#endif // _CORE_CM3_H_ - -/*lint -restore */ diff --git a/radio/src/targets/sky9x/crt.c b/radio/src/targets/sky9x/crt.c deleted file mode 100644 index 48784b6e3..000000000 --- a/radio/src/targets/sky9x/crt.c +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __CRT_C__ - -#include - -/*=========================================================================*/ -/* DEFINE: All extern Data */ -/*=========================================================================*/ -/* - * The next data are defined by the linker script. - */ -extern unsigned long _stext; -extern unsigned long _etext; -extern unsigned long _sdata; -extern unsigned long _edata; -extern unsigned long _sbss; -extern unsigned long _ebss; -extern unsigned long _estack; - -/* This is the main */ -extern int main (void); - -/*=========================================================================*/ -/* DEFINE: Prototypes */ -/*=========================================================================*/ -extern uint32_t SystemInit (void) ; // __attribute__((weak)); - -/*=========================================================================*/ -/* DEFINE: All code exported */ -/*=========================================================================*/ - -/***************************************************************************/ -/* SystemInit */ -/* */ -/* SystemInit is a function which is provided by the CMSIS interface. */ -/* If this function is not available, we need a function here to prevent */ -/* an error of the linker. Therefore this function is declared as weak. */ -/***************************************************************************/ -//uint32_t SystemInit (void) -//{ - -//} /* SystemInit */ - -extern uint32_t Master_frequency ; - -/***************************************************************************/ -/* ResetHandler */ -/* */ -/* This function is used for the C runtime initialisation, */ -/* for handling the .data and .bss segments. */ -/***************************************************************************/ -void ResetHandler (void) -{ - { - uint32_t *pSrc; - uint32_t *pDest; - uint32_t m_freq ; - - /* - * Call the SystemInit code from CMSIS interface if available. - * SystemInit is a week function which can be override - * by an external function. - */ - m_freq = SystemInit(); - - /* - * Set the "Vector Table Offset Register". From the ARM - * documentation, we got the following information: - * - * Use the Vector Table Offset Register to determine: - * - if the vector table is in RAM or code memory - * - the vector table offset. - */ - *((uint32_t*)0xE000ED08) = (uint32_t)&_stext; - - /* - * Copy the initialized data of the ".data" segment - * from the flash to the are in the ram. - */ - pSrc = &_etext; - pDest = &_sdata; - while(pDest < &_edata) - { - *pDest++ = *pSrc++; - } - - /* - * Clear the ".bss" segment. - */ - pDest = &_sbss; - while(pDest < &_ebss) - { - *pDest++ = 0; - } - Master_frequency = m_freq ; - } - - /* - * And now the main function can be called. - * Scotty, energie... - */ - main(); - - /* - * In case there are problems with the - * "warp drive", stop here. - */ - while(1) {}; - -} /* ResetHandler */ - -/*** EOF ***/ diff --git a/radio/src/targets/sky9x/diskio.cpp b/radio/src/targets/sky9x/diskio.cpp deleted file mode 100644 index e3ab4ca4f..000000000 --- a/radio/src/targets/sky9x/diskio.cpp +++ /dev/null @@ -1,1381 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/*-----------------------------------------------------------------------*/ -/* MMCv3/SDv1/SDv2 (in SPI mode) control module (C)ChaN, 2010 */ -/*-----------------------------------------------------------------------*/ -/* Only rcvr_spi(), xmit_spi(), sdPoll10ms() and some macros */ -/* are platform dependent. */ -/*-----------------------------------------------------------------------*/ - -#include "opentx.h" -#include "diskio.h" - -#define CARD_TYPE_bmHC (1 << 0) /**< Bit for High-Capacity(Density) */ -#define CARD_TYPE_bmSDMMC (0x3 << 1) /**< Bits mask for SD/MMC */ -#define CARD_TYPE_bmUNKNOWN (0x0 << 1) /**< Bits for Unknown card */ -#define CARD_TYPE_bmSD (0x1 << 1) /**< Bits for SD */ -#define CARD_TYPE_bmMMC (0x2 << 1) /**< Bits for MMC */ -#define CARD_TYPE_bmSDIO (1 << 3) /**< Bit for SDIO */ -/** Card can not be identified */ -#define CARD_UNKNOWN (0) -/** SD Card (0x2) */ -#define CARD_SD (CARD_TYPE_bmSD) -/** SD High Capacity Card (0x3) */ -#define CARD_SDHC (CARD_TYPE_bmSD|CARD_TYPE_bmHC) -/** MMC Card (0x4) */ -#define CARD_MMC (CARD_TYPE_bmMMC) -/** MMC High-Density Card (0x5) */ -#define CARD_MMCHD (CARD_TYPE_bmMMC|CARD_TYPE_bmHC) -/** SDIO only card (0x8) */ -#define CARD_SDIO (CARD_TYPE_bmSDIO) -/** SDIO Combo, with SD embedded (0xA) */ -#define CARD_SDCOMBO (CARD_TYPE_bmSDIO|CARD_SD) -/** SDIO Combo, with SDHC embedded (0xB) */ -#define CARD_SDHCCOMBO (CARD_TYPE_bmSDIO|CARD_SDHC) - -#define STATUS_READY_FOR_DATA (1UL << 8) -#define STATUS_TRAN (4UL << 9) -#define STATUS_STATE (0xFUL << 9) - -/** Bit mask for data errors */ -#define STATUS_ERRORS_DATA ((uint32_t)(HSMCI_SR_UNRE \ - | HSMCI_SR_OVRE \ - /*| HSMCI_SR_BLKOVRE*/ \ - /*| HSMCI_SR_CSTOE*/ \ - | HSMCI_SR_DTOE \ - | HSMCI_SR_DCRCE)) - - -uint32_t Card_ID[4] ; -uint32_t Card_SCR[2] ; -uint32_t Card_CSD[4] ; -int32_t Card_state = SD_ST_STARTUP ; -volatile uint32_t Card_initialized = 0; -uint32_t Sd_rca ; -uint32_t Cmd_A41_resp ; -uint8_t cardType; -uint32_t transSpeed; - -/*-----------------------------------------------------------------------*/ -/* Lock / unlock functions */ -/*-----------------------------------------------------------------------*/ - -#if !defined(BOOT) -static RTOS_MUTEX_HANDLE ioMutex; -volatile int mutexCheck = 0; -int ff_cre_syncobj (BYTE vol, FF_SYNC_t *mutex) -{ - *mutex = ioMutex; - return 1; -} - -int ff_req_grant (FF_SYNC_t mutex) -{ - RTOS_LOCK_MUTEX(mutex); - return 1; -} - -void ff_rel_grant (FF_SYNC_t mutex) -{ - CoLeaveMutexSection(mutex); -} - -int ff_del_syncobj (FF_SYNC_t mutex) -{ - return 1; -} -#endif - -//------------------------------------------------------------------------------ -/// Get Trans Speed Value (Kbit/s) -/// \param tranSpeed The TRAN_SPEED value from SD(IO)/MMC enum information. -/// \param unitList Transfer rate units (Kbit/s), 4 units listed. -/// \param nbUnits Transfer rate units list size. -/// \param codeList Time value codes list, 16 codes listed. -//------------------------------------------------------------------------------ -static unsigned int MmcGetTranSpeed(unsigned int tranSpeed, - const unsigned int* unitList, unsigned int nbUnits, - const unsigned int* codeList) -{ - unsigned int unit, value; - unit = tranSpeed & 0x7; - if (unit < nbUnits) unit = unitList[unit]; - else return 0; - value = (tranSpeed >> 3) & 0xF; - if (value < 16) value = codeList[value]; - else return 0; - return (unit * value); -} - -//------------------------------------------------------------------------------ -/// Get Trans Speed Value -/// \param pSd -//------------------------------------------------------------------------------ -uint32_t GetTransSpeedValue() -{ - // CSD register, TRANS_SPEED bit - const unsigned int units[4] = {10, 100, 1000, 10000 }; // *Kbit/s -/* const unsigned int values_emmc[16] = {0, 10, 12, 13, 15, 20, - 26, 30, 35, 40, 45, 52, - 55, 60, 70, 80}; */ - const unsigned int values_sdmmc[16] = {0, 10, 12, 13, 15, 20, - 25, 30, 35, 40, 45, 50, - 55, 60, 70, 80}; - #if 0 - unsigned int unit, value; - unit = (SD_CSD_TRAN_SPEED(pSd) & 0x7); - if(unit < 4) unit = units[unit]; - else return; - value = (SD_CSD_TRAN_SPEED(pSd) >> 3) & 0xF; - if (value < 16) { - if (pSd->cardType >= CARD_MMC && SD_CID_BGA(pSd) == 1) { - value = values_emmc[value]; - } - else - value = values_sdmmc[value]; - } - else return; - pSd->transSpeed = (unit * value); - #else - transSpeed = MmcGetTranSpeed(SD_CSD_TRAN_SPEED(Card_CSD), - units, 4, - values_sdmmc); - #endif - /*if (pSd->cardType >= CARD_MMC && SD_EXTCSD_HS_TIMING(pSd)) { - pSd->transSpeed *= 2; - }*/ - TRACE_ERROR("-I- SD/MMC TRANS SPEED %d KBit/s\r\n", transSpeed); - transSpeed *= 1000; - return transSpeed; -} - -/** - * Configure the MCI CLKDIV in the MCI_MR register. The max. for MCI clock is - * MCK/2 and corresponds to CLKDIV = 0 - * \param mciSpeed MCI clock speed in Hz, 0 will not change current speed. - * \return The actual speed used, 0 for fail. - */ -uint32_t sdSetSpeed(uint32_t mciSpeed ) -{ - uint32_t mciMr; - uint32_t clkdiv, divLimit; - - mciMr = HSMCI->HSMCI_MR & (~(uint32_t)HSMCI_MR_CLKDIV_Msk); - /* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK) - * divided by (2*(CLKDIV+1)) - * mciSpeed = MCK / (2*(CLKDIV+1)) */ - if (mciSpeed > 0) { - -#if 1 - divLimit = (Master_frequency / 2 / mciSpeed); - if ((Master_frequency / 2) % mciSpeed) divLimit ++; - - clkdiv = (Master_frequency / 2 / mciSpeed); - if (mciSpeed && clkdiv < divLimit) - clkdiv = divLimit; - if (clkdiv > 0) - clkdiv -= 1; -#else - clkdiv = (Master_frequency / 2 / mciSpeed); - /* Speed should not bigger than expired one */ - if (mciSpeed < Master_frequency / 2 / clkdiv) { - clkdiv++; - } - if (clkdiv > 0) { - clkdiv -= 1; - } -#endif - } - else { - clkdiv = 0; - } - - /* Actual MCI speed */ - mciSpeed = Master_frequency / 2 / (clkdiv + 1); - /* Modify MR */ - HSMCI->HSMCI_MR = mciMr | clkdiv; - - return mciSpeed; -} - -#if 0 -void SD_SetBlklen( uint32_t blklen ) -{ - uint32_t mciMr; - uint32_t clkdiv; - - mciMr = HSMCI->HSMCI_MR & (~(uint32_t)HSMCI_MR_BLKLEN); - /* Modify MR */ - HSMCI->HSMCI_MR = mciMr | blklen << 16 ; -} -#endif - -#if 0 -/** - * Reset MCI HW interface and disable it. - * \param keepSettings Keep old register settings, including - * _MR, _SDCR, _DTOR, _CSTOR, _DMA and _CFG. - */ -void SD_Reset( uint8_t keepSettings) -{ - Hsmci *pMciHw = HSMCI ; - - if (keepSettings) - { - uint32_t mr, sdcr, dtor, cstor; - uint32_t cfg; - mr = pMciHw->HSMCI_MR; - sdcr = pMciHw->HSMCI_SDCR; - dtor = pMciHw->HSMCI_DTOR; - cstor = pMciHw->HSMCI_CSTOR; - cfg = pMciHw->HSMCI_CFG; - pMciHw->HSMCI_CR = HSMCI_CR_SWRST ; // Reset - pMciHw->HSMCI_CR = HSMCI_CR_MCIDIS; // Disable - pMciHw->HSMCI_MR = mr; - pMciHw->HSMCI_SDCR = sdcr; - pMciHw->HSMCI_DTOR = dtor; - pMciHw->HSMCI_CSTOR = cstor; - pMciHw->HSMCI_CFG = cfg; - } - else - { - pMciHw->HSMCI_CR = HSMCI_CR_SWRST ; // Reset - pMciHw->HSMCI_CR = HSMCI_CR_MCIDIS; // Disable - } -} -#endif - -const char SD_NORESPONSE[] = "No response"; - -const char * sdCommand(uint32_t cmd, uint32_t arg) -{ - uint32_t i; - Hsmci *phsmci = HSMCI; - - if (SD_CARD_PRESENT()) { - phsmci->HSMCI_ARGR = arg; - phsmci->HSMCI_CMDR = cmd; - - for (i = 0; i < 50000; i += 1) { - if (phsmci->HSMCI_SR & HSMCI_SR_CMDRDY) { - return 0; - } - } - return SD_NORESPONSE; - } - else { - return "No Sdcard"; - } -} - -#define SDMMC_POWER_ON_INIT (0 | HSMCI_CMDR_TRCMD_NO_DATA \ - | HSMCI_CMDR_SPCMD_INIT \ - | HSMCI_CMDR_OPDCMD ) - -const char * sdPowerOn() -{ - return sdCommand(SDMMC_POWER_ON_INIT, 0); -} - -#define SDMMC_GO_IDLE_STATE (0 | HSMCI_CMDR_TRCMD_NO_DATA \ - | HSMCI_CMDR_SPCMD_STD ) - -const char * sdCmd0() -{ - return sdCommand(SDMMC_GO_IDLE_STATE, 0); -} - -#if 0 -#define SDIO_SEND_OP_COND (5 | HSMCI_CMDR_SPCMD_STD \ - | HSMCI_CMDR_TRCMD_NO_DATA \ - | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_OPDCMD ) - -const char * sdCmd5(uint32_t *pIo) -{ - const char * result = sdCommand(SDIO_SEND_OP_COND, *pIo); - if (result) - return result; - *pIo = HSMCI->HSMCI_RSPR[0]; - return 0; -} -#endif - -#define SD_SEND_IF_COND (8 | HSMCI_CMDR_TRCMD_NO_DATA \ - | HSMCI_CMDR_SPCMD_STD \ - | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_OPDCMD /* BSS difference */ \ - | HSMCI_CMDR_MAXLAT ) - -const char * sdCmd8(uint8_t supplyVoltage) -{ - return sdCommand(SD_SEND_IF_COND, (supplyVoltage << 8) | (0xAA)); -} - -#define SDMMC_APP_CMD (55| HSMCI_CMDR_SPCMD_STD \ - | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_TRCMD_NO_DATA \ - | HSMCI_CMDR_MAXLAT) - -const char * sdCmd55() -{ - return sdCommand(SDMMC_APP_CMD, Sd_rca); -} - -#define SDMMC_SEND_STATUS_CMD (13 | HSMCI_CMDR_TRCMD_NO_DATA \ - | HSMCI_CMDR_SPCMD_STD \ - | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_MAXLAT ) - -const char * sdCmd13(unsigned int *status) -{ - const char *result = sdCommand(SDMMC_SEND_STATUS_CMD, Sd_rca); - if (result) - return result; - *status = HSMCI->HSMCI_RSPR[0]; - return 0; -} - -#define SDMMC_SET_BLOCKLEN (16 | HSMCI_CMDR_TRCMD_NO_DATA \ - | HSMCI_CMDR_SPCMD_STD \ - | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_MAXLAT_64 ) - -uint32_t sdCmd16() -{ - Hsmci *phsmci = HSMCI; - - if (SD_CARD_PRESENT()) { - phsmci->HSMCI_BLKR = ( ( 512 ) << 16 ) | 1 ; - phsmci->HSMCI_ARGR = 512; - phsmci->HSMCI_CMDR = SDMMC_SET_BLOCKLEN; - - while(1) { - if (phsmci->HSMCI_SR & HSMCI_SR_CMDRDY) { - break; - } - } - return phsmci->HSMCI_RSPR[0]; - } - else { - return 0; - } -} - -#define SD_SD_SEND_OP_COND (41| HSMCI_CMDR_SPCMD_STD \ - | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_TRCMD_NO_DATA \ - /*| HSMCI_CMDR_OPDCMD_OPENDRAIN */ ) - -const char * sdCmd41(uint32_t arg, uint32_t * status) -{ - const char * result = sdCommand(SD_SD_SEND_OP_COND, arg); - if (result) - return result; - *status = HSMCI->HSMCI_RSPR[0]; - return 0; -} - -#define OCR_VDD_27_28 ((uint32_t)(1 << 15)) -#define OCR_VDD_28_29 ((uint32_t)(1 << 16)) -#define OCR_VDD_29_30 ((uint32_t)(1 << 17)) -#define OCR_VDD_30_31 ((uint32_t)(1 << 18)) -#define OCR_VDD_31_32 ((uint32_t)(1 << 19)) -#define OCR_VDD_32_33 ((uint32_t)(1 << 20)) -#define OCR_VDD_33_34 ((uint32_t)(1 << 21)) - -#define SDMMC_HOST_VOLTAGE_RANGE (OCR_VDD_27_28 +\ - OCR_VDD_28_29 +\ - OCR_VDD_29_30 +\ - OCR_VDD_30_31 +\ - OCR_VDD_31_32 +\ - OCR_VDD_32_33 +\ - OCR_VDD_32_33) /* not in SAM3S reference code */ - -#define OCR_POWER_UP_BUSY (1UL << 31) - -const char * sdMemInit(uint8_t hcs, uint32_t *pCCS) -{ - const char * result; - uint32_t arg; - uint32_t status; - do { - result = sdCmd55(); - if (result) - return result; - arg = SDMMC_HOST_VOLTAGE_RANGE; - if (hcs) arg |= OCR_SD_CCS; - result = sdCmd41(arg, &status); - if (result) - return result; - *pCCS = (status & OCR_SD_CCS); - } while ((status & OCR_POWER_UP_BUSY) != OCR_POWER_UP_BUSY); - return 0; -} - -// Get Card ID -const char * sdCmd2() -{ - const char * result = sdCommand(0x00001082, 0); - if (result) - return result; - - Hsmci *phsmci = HSMCI ; - Card_ID[0] = phsmci->HSMCI_RSPR[0] ; - Card_ID[1] = phsmci->HSMCI_RSPR[1] ; - Card_ID[2] = phsmci->HSMCI_RSPR[2] ; - Card_ID[3] = phsmci->HSMCI_RSPR[3] ; - return 0; -} - -// Get new RCA -const char * sdCmd3() -{ - const char * result = sdCommand(0x00001043, 0); - if (result) - return result; - Sd_rca = HSMCI->HSMCI_RSPR[0]; - return 0; -} - -// Get CSD -const char * sdCmd9() -{ - const char * result = sdCommand(0x00001089, Sd_rca); - if (result) - return result; - - Hsmci *phsmci = HSMCI ; - Card_CSD[0] = phsmci->HSMCI_RSPR[0] ; - Card_CSD[1] = phsmci->HSMCI_RSPR[1] ; - Card_CSD[2] = phsmci->HSMCI_RSPR[2] ; - Card_CSD[3] = phsmci->HSMCI_RSPR[3] ; - return 0; -} - -/** Cmd7 MCI, ac, R1/R1b */ -#define SDMMC_SELECT_CARD (7 | HSMCI_CMDR_TRCMD_NO_DATA \ - | HSMCI_CMDR_SPCMD_STD \ - | HSMCI_CMDR_RSPTYP_R1B \ - | HSMCI_CMDR_MAXLAT ) - -const char * sdCmd7() -{ - return sdCommand(SDMMC_SELECT_CARD, Sd_rca); -} - -#define SD_SEND_SCR (51 | HSMCI_CMDR_SPCMD_STD | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRDIR_READ \ - | HSMCI_CMDR_TRTYP_SINGLE | HSMCI_CMDR_MAXLAT) - -#define SD_READ_SINGLE_BLOCK (17 | HSMCI_CMDR_SPCMD_STD | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRDIR_READ \ - | HSMCI_CMDR_TRTYP_SINGLE | HSMCI_CMDR_MAXLAT) - -#define SD_WRITE_SINGLE_BLOCK (24 | HSMCI_CMDR_SPCMD_STD \ - | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_TRCMD_START_DATA \ - | HSMCI_CMDR_TRDIR_WRITE \ - | HSMCI_CMDR_TRTYP_SINGLE \ - | HSMCI_CMDR_MAXLAT) - -// Get SCR -const char * sdAcmd51() -{ - const char * result; - result = sdCmd55(); - if (result) - return result; - - Hsmci *phsmci = HSMCI ; - // Block size = 64/ 8, nblocks = 1 - phsmci->HSMCI_BLKR = ( ( 64 / 8 ) << 16 ) | 1 ; - phsmci->HSMCI_ARGR = 0 ; - phsmci->HSMCI_CMDR = SD_SEND_SCR ; - - uint8_t scrLen = 0; - uint32_t i; - for ( i = 0 ; i < 50000 ; i += 1 ) { - if ( phsmci->HSMCI_SR & HSMCI_SR_RXRDY ) - Card_SCR[scrLen++] = __REV(phsmci->HSMCI_RDR) ; - if ( ( phsmci->HSMCI_SR & ( HSMCI_SR_CMDRDY | HSMCI_SR_XFRDONE ) ) == ( HSMCI_SR_CMDRDY | HSMCI_SR_XFRDONE ) ) - return 0; - } - return "No response"; -} - -#define SD_SET_BUS_WIDTH (6 | HSMCI_CMDR_SPCMD_STD | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_MAXLAT) - -void sdEnableHsMode(uint8_t enable) -{ - Hsmci *phsmci = HSMCI; - if (enable) - phsmci->HSMCI_CFG |= HSMCI_CFG_HSMODE; - else - phsmci->HSMCI_CFG &= ~HSMCI_CFG_HSMODE; -} - -void sdSetBusWidth(uint32_t busWidth) -{ - Hsmci *phsmci = HSMCI; - phsmci->HSMCI_SDCR = (HSMCI->HSMCI_SDCR & ~HSMCI_SDCR_SDCBUS_Msk) | busWidth; -} - -// Set bus width to 4 bits, set speed to 9 MHz -const char * sdAcmd6() -{ - const char * result; - result = sdCmd55() ; - if (result) - return result; - - result = sdCommand(SD_SET_BUS_WIDTH, 2); - if (result) - return result; - - sdSetBusWidth( HSMCI_SDCR_SDCBUS_4 ) ; - - GetTransSpeedValue(); - sdSetSpeed(transSpeed/*9000000*/); - - // TODO + Cmd6? sdEnableHsMode(1); - - if (Cmd_A41_resp & OCR_SD_CCS) - sdCmd16(); - - return 0; -} - -#if 0 -/** SDIO CMD52, R5 */ -#define SDIO_IO_RW_DIRECT (52| HSMCI_CMDR_SPCMD_STD \ - | HSMCI_CMDR_TRCMD_NO_DATA \ - | HSMCI_CMDR_RSPTYP_48_BIT \ - | HSMCI_CMDR_MAXLAT) - -static const char * sdCmd52(uint8_t wrFlag, - uint8_t funcNb, - uint8_t rdAfterWr, - uint32_t addr, - uint32_t *status) -{ - typedef struct - { - uint32_t data:8, /**< [ 7: 0] data for writing */ - stuff0:1, /**< [ 8] reserved */ - regAddress:17, /**< [25: 9] register address */ - stuff1:1, /**< [ 26] reserved */ - rawFlag:1, /**< [ 27] Read after Write flag */ - functionNum:3, /**< [30:28] Number of the function */ - rwFlag:1; /**< [ 31] Direction, 1:write, 0:read. */ - } SdioCmd52Arg; - - SdioCmd52Arg pArg52; - pArg52.rwFlag = wrFlag; - pArg52.functionNum = funcNb; - pArg52.rawFlag = rdAfterWr; - pArg52.regAddress = addr; - - const char * result = sdCommand(SDIO_IO_RW_DIRECT, *(uint32_t*)&pArg52); - if (result) - return result; - *status = HSMCI->HSMCI_RSPR[0]; - return 0; -} - -const char * sdSwReset(uint32_t retry) -{ - uint32_t i; - const char * result = 0; - - for (i = 0; i < retry; i++) { - result = sdCmd0(0); - if (result != SD_NORESPONSE) - break; - } - return result; -} -#endif - -/** - * \brief Run the SD/MMC/SDIO Mode initialization sequence. - * This function runs the initialization procedure and the identification - * process. Then it leaves the card in ready state. The following procedure must - * check the card type and continue to put the card into tran(for memory card) - * or cmd(for io card) state for data exchange. - * \param pSd Pointer to a SD card driver instance. - * \return 0 if successful; otherwise returns an \ref sdmmc_rc "SD_ERROR code". - */ - -#define SDIO_CIA 0 /**< SDIO Function 0 (CIA) */ -#define SDIO_IOA_REG 0x06 /**< I/O Abort */ - -/** SDIO state (in R5) */ -#define SDIO_R5_ERROR (1UL << 11)/**< General error */ -#define SDIO_R5_FUNC_NUM (1UL << 10)/**< Invalid function number */ -#define SDIO_R5_OUT_OF_RANGE (1UL << 9) /**< Argument out of range */ - -/** Status bits mask for SDIO R5 */ -#define STATUS_SDIO_R5 (0/*SDIO_R5_STATE*/ \ - | SDIO_R5_ERROR \ - | SDIO_R5_FUNC_NUM \ - | SDIO_R5_OUT_OF_RANGE) - - -#define OCR_SDIO_MP (1UL << 27) -#define OCR_SDIO_NF (7UL << 28) - -#if 0 -const char * sdIdentify() -{ - uint8_t mem = 0, io = 0, f8 = 0, mp = 1; - uint32_t status, ccs=0; - const char * result; - - /* Reset HC to default HS and BusMode */ - sdEnableHsMode(0); - sdSetBusWidth(HSMCI_SDCR_SDCBUS_1); - -#if 0 - /* Reset SDIO: CMD52, write 1 to RES bit in CCCR (bit 3 of register 6) */ - result = sdCmd52(1, SDIO_CIA, 0, SDIO_IOA_REG, &status); - if (result) - return result; - if (status & STATUS_SDIO_R5) - return "Identify.52 error"; -#endif - - /* Reset MEM: CMD0 */ - result = sdSwReset(1); - if (result) - return result; - - /* CMD8 is newly added in the Physical Layer Specification Version 2.00 to - * support multiple voltage ranges and used to check whether the card - * supports supplied voltage. The version 2.00 host shall issue CMD8 and - * verify voltage before card initialization. - * The host that does not support CMD8 shall supply high voltage range... */ - result = sdCmd8(1); - if (result == 0) f8 = 1; - else if (result == SD_NORESPONSE) RTOS_WAIT_MS(2); /* 2ms delay after "no response" */ - else return "Identify.8 error"; - -#if 0 - /* CMD5 is newly added for SDIO initialize & power on */ - status = 0; - result = sdCmd5(&status); - if (!result && (status & OCR_SDIO_NF) > 0) { - unsigned int cmd5Retries = 10000; - do { - status &= SDMMC_HOST_VOLTAGE_RANGE; - result = sdCmd5(&status); - if (status & OCR_POWER_UP_BUSY) break; - } while(!result && cmd5Retries --); - if (result) - return "Identify.5 error"; - io = 1; - /* IO only ?*/ - mp = ((status & OCR_SDIO_MP) > 0); - } -#endif - - /* Has memory: SD/MMC/COMBO */ - /*if (mp) */ - { - /* Try SD memory initialize */ - result = sdMemInit(f8, &ccs); - if (result) { - //unsigned int cmd1Retries = 10000; - /* Try MMC initialize */ - result = sdSwReset(10); - if (result) - return "Reset error"; - /* TODO ccs = 1; - do { result = sdCmd1(&ccs); } while(result && cmd1Retries -- > 0); - if (error) { - TRACE_ERROR("SdMmcIdentify.Cmd1: %u\n\r", error); - return SDMMC_ERROR; - } - else if (ccs) cardType = CARD_MMCHD; - else cardType = CARD_MMC; - */ - return "TODO error"; - /* MMC card identification OK */ - return 0; - } - // mem = 1; - } - /* SD(IO) + MEM ? */ - /* if (!mem) { - if (io) cardType = CARD_SDIO; - else - return "Unknown SD"; - } */ - /* SD(HC) combo */ - /*else if (io) - cardType = ccs ? CARD_SDHCCOMBO : CARD_SDCOMBO;*/ - /* SD(HC) */ - //else - cardType = ccs ? CARD_SDHC : CARD_SD; - - return 0; -} - -const char * sdEnum() -{ - uint8_t mem , io; - const char * result; - uint32_t ioSpeed = 0, memSpeed = 0; - uint8_t hsExec = 0, bwExec = 0; - - /* - has Memory/IO/High-Capacity - */ - mem = ((cardType & CARD_TYPE_bmSDMMC) > 0); - io = ((cardType & CARD_TYPE_bmSDIO) > 0); - - /* For MEMORY cards: - * The host then issues the command ALL_SEND_CID (CMD2) to the card to get - * its unique card identification (CID) number. - * Card that is unidentified (i.e. which is in Ready State) sends its CID - * number as the response (on the CMD line). */ - if (mem) { - result = sdCmd2(); - if (result) - return result; - } - - /* For MEMORY and SDIO cards: - * Thereafter, the host issues CMD3 (SEND_RELATIVE_ADDR) asks the - * card to publish a new relative card address (RCA), which is shorter than - * CID and which is used to address the card in the future data transfer - * mode. Once the RCA is received the card state changes to the Stand-by - * State. At this point, if the host wants to assign another RCA number, it - * can ask the card to publish a new number by sending another CMD3 command - * to the card. The last published RCA is the actual RCA number of the - * card. */ - result = sdCmd3(); - if (result) - return result; - - /* For MEMORY cards: - * SEND_CSD (CMD9) to obtain the Card Specific Data (CSD register), - * e.g. block length, card storage capacity, etc... */ - if (mem) { - result = sdCmd9(); - if (result) - return result; - } - - /* Now select the card, to TRAN state */ - error = MmcSelectCard(pSd, pSd->cardAddress, 0); - if (error) { - TRACE_ERROR("SdMmcInit.SelCard(%d)\n\r", error); - return error; - } - - /* - Now in TRAN, obtain extended setup information - */ - - /* If the card support EXT_CSD, read it! */ - TRACE_INFO("Card Type %d, CSD_STRUCTURE %d\n\r", - pSd->cardType, SD_CSD_STRUCTURE(pSd)); - - /* Get extended information of the card */ - SdMmcUpdateInformation(pSd, 0, 1); - - /* Calculate transfer speed */ - if (io) ioSpeed = SdioGetMaxSpeed(pSd); - if (mem) memSpeed = SdmmcGetMaxSpeed(pSd); - /* Combo, min speed */ - if (io && mem) { - pSd->transSpeed = (ioSpeed > memSpeed) ? memSpeed : ioSpeed; - } - /* SDIO only */ - else if (io) { - pSd->transSpeed = ioSpeed; - } - /* Memory card only */ - else if (mem) { - pSd->transSpeed = memSpeed; - } - pSd->transSpeed *= 1000; - - /* Enable more bus width Mode */ - error = SdMmcDesideBuswidth(pSd); - if (!error) bwExec = 1; - else if (error != SDMMC_ERROR_NOT_SUPPORT) { - TRACE_ERROR("SdmmcEnum.DesideBusWidth: %u\n\r", error); - return SDMMC_ERROR; - } - - /* Enable High-Speed Mode */ - error = SdMmcEnableHighSpeed(pSd); - if (!error) hsExec = 1; - else if (error != SDMMC_ERROR_NOT_SUPPORT) { - TRACE_ERROR("SdmmcEnum.EnableHS: %u\n\r", error); - return SDMMC_ERROR; - } - - /* In HS mode transfer speed *2 */ - if (hsExec) pSd->transSpeed *= 2; - - /* Update card information since status changed */ - if (bwExec || hsExec) SdMmcUpdateInformation(pSd, hsExec, 1); - return 0; -} - -void sdInit() -{ - TRACE("sdInit"); - - const char * result; - uint8_t i; - - /* Clear CID, CSD, EXT_CSD data */ - for (i = 0; i < 4; i++) Card_ID[i] = 0; - for (i = 0; i < 4; i++) Card_CSD[i] = 0; - // TODO for (i = 0; i < 512/4; i++) pSd->extData[i] = 0; - - /* Set low speed for device identification (LS device max speed) */ - sdSetSpeed(400000); - - /* Initialization delay: The maximum of 1 msec, 74 clock cycles and supply - * ramp up time. Supply ramp up time provides the time that the power is - * built up to the operating level (the bus master supply voltage) and the - * time to wait until the SD card can accept the first command. - */ - - /* Power On Init Special Command */ - result = sdPowerOn(); - if (result) - return; - - /* After power-on or CMD0, all cards? - * CMD lines are in input mode, waiting for start bit of the next command. - * The cards are initialized with a default relative card address - * (RCA=0x0000) and with a default driver stage register setting - * (lowest speed, highest driving current capability). - */ - result = sdIdentify(); - if (result) { - return; - } - -#if 0 - result = sdEnum(); - if (result) { - return; - } - - /* In the case of a Standard Capacity SD Memory Card, this command sets the - * block length (in bytes) for all following block commands - * (read, write, lock). - * Default block length is fixed to 512 Bytes. - * Set length is valid for memory access commands only if partial block read - * operation are allowed in CSD. - * In the case of a High Capacity SD Memory Card, block length set by CMD16 - * command does not affect the memory read and write commands. Always 512 - * Bytes fixed block length is used. This command is effective for - * LOCK_UNLOCK command. - * In both cases, if block length is set larger than 512Bytes, the card sets - * the BLOCK_LEN_ERROR bit. */ - if (pSd->cardType == CARD_SD) { - error = Cmd16(pSd, SDMMC_BLOCK_SIZE); - if (error) { - pSd->optCmdBitMap &= ~SD_CMD16_SUPPORT; - TRACE_INFO("SD_Init.Cmd16 (%d)\n\r", error); - TRACE_INFO("Fail to set BLK_LEN, default is 512\n\r"); - } - } - - /* Reset status for R/W */ - pSd->state = SD_STATE_READY; - - /* If MMC Card & get size from EXT_CSD */ - if ((pSd->cardType & CARD_TYPE_bmSDMMC) == CARD_TYPE_bmMMC - && SD_CSD_C_SIZE(pSd) == 0xFFF) { - pSd->blockNr = SD_EXTCSD_BLOCKNR(pSd); - /* Block number less than 0x100000000/512 */ - if (pSd->blockNr > 0x800000) - pSd->totalSize = 0xFFFFFFFF; - else - pSd->totalSize = SD_EXTCSD_TOTAL_SIZE(pSd); - } - /* If SD CSD v2.0 */ - else if((pSd->cardType & CARD_TYPE_bmSDMMC) == CARD_TYPE_bmSD - && SD_CSD_STRUCTURE(pSd) >= 1) { - pSd->blockNr = SD_CSD_BLOCKNR_HC(pSd); - pSd->totalSize = 0xFFFFFFFF; - } - /* Normal SD/MMC card */ - else if (pSd->cardType & CARD_TYPE_bmSDMMC) { - pSd->totalSize = SD_CSD_TOTAL_SIZE(pSd); - pSd->blockNr = SD_CSD_BLOCKNR(pSd); - } - - if (pSd->cardType == CARD_UNKNOWN) { - return SDMMC_ERROR_NOT_INITIALIZED; - } - /* Automatically select the max clock */ - clock = SdmmcSetSpeed(pSd, pSd->transSpeed); - TRACE_WARNING_WP("-I- Set SD/MMC clock to %dK\n\r", clock/1000); - pSd->accSpeed = clock; -#endif -} -#endif - -uint8_t sdErrorCount = 0; -FATFS g_FATFS_Obj = { 0 }; - -void sdInit() -{ - Sd_rca = 0; - sdErrorCount = 0; - - if (!SD_CARD_PRESENT()) { - Card_state = SD_ST_EMPTY; - Card_initialized = 1; - return; - } - - sdCmd0(); - RTOS_WAIT_MS(10); // 10ms - sdCmd8(1); - -#if 0 - uint8_t i; - uint32_t status; - for (i=0; i<100; i++) - sdCmd5(&status); -#endif - - sdMemInit(1, &Cmd_A41_resp); - - uint8_t retry; - for (retry=0; retry<10; retry++) { - if (!sdCmd2()) break; - RTOS_WAIT_MS(2); // 2ms - } - - if (retry == 10) { - Card_state = SD_ST_READY; - Card_initialized = 1; - return; - } - - for (retry=0; retry<10; retry++) { - if (!sdCmd3()) break; - RTOS_WAIT_MS(2); // 2ms - } - - if (retry == 10) { - Card_state = SD_ST_IDENT; - Card_initialized = 1; - return; - } - - sdCmd9(); - sdCmd7(); // Select Card - - sdAcmd51(); - sdAcmd6(); // Set bus width to 4 bits, and speed to 9 MHz - - // Should check the card can do this **** - Card_state = SD_ST_DATA; - - if (f_mount(&g_FATFS_Obj, "", 1) == FR_OK) { - // call sdGetFreeSectors() now because f_getfree() takes a long time first time it's called - sdGetFreeSectors(); - Card_state = SD_ST_MOUNTED; - } - - Card_initialized = 1; -} - -void sdDone() -{ - if (sdMounted()) { - audioQueue.stopSD(); - f_mount(nullptr, "", 0); // unmount SD - } -} - -// Checks for card ready for read/write -// returns 1 for YES, 0 for NO -uint32_t sd_card_ready( void ) -{ - return SD_CARD_PRESENT() && Card_state >= SD_ST_DATA; -} - -uint32_t sdMounted( void ) -{ - return SD_CARD_PRESENT() && Card_state == SD_ST_MOUNTED; -} - -uint32_t sd_read_block(uint32_t block_no, uint32_t *data) -{ - unsigned int status = 0; - - // TRACE_ERROR("read block %d", block_no); - - if (sd_card_ready()) { - - // Wait for card to be ready for data transfers - do { - sdCmd13(&status); - } - while (((status & STATUS_READY_FOR_DATA) == 0) - || ((status & STATUS_STATE) != STATUS_TRAN) ); - - // Block size = 512, nblocks = 1 - HSMCI->HSMCI_BLKR = ((512) << 16) | 1; - HSMCI->HSMCI_MR = (HSMCI->HSMCI_MR & (~(HSMCI_MR_BLKLEN_Msk|HSMCI_MR_FBYTE))) | (HSMCI_MR_PDCMODE|HSMCI_MR_WRPROOF|HSMCI_MR_RDPROOF) | (512 << 16); - HSMCI->HSMCI_ARGR = (Cmd_A41_resp & OCR_SD_CCS ? block_no : (block_no << 9)); - HSMCI->HSMCI_RPR = (uint32_t)data; - HSMCI->HSMCI_RCR = 512 / 4; - HSMCI->HSMCI_PTCR = HSMCI_PTCR_RXTEN; - HSMCI->HSMCI_CMDR = SD_READ_SINGLE_BLOCK; - - while (!(HSMCI->HSMCI_SR & HSMCI_SR_CMDRDY)); - - (void) HSMCI->HSMCI_RSPR[0]; - - while (1) { - if ((HSMCI->HSMCI_SR & (HSMCI_SR_ENDRX|HSMCI_SR_XFRDONE)) == (HSMCI_SR_ENDRX|HSMCI_SR_XFRDONE)) { - break; - } - } - - /* Disable PDC */ - HSMCI->HSMCI_MR &= ~(uint32_t)HSMCI_MR_PDCMODE; - HSMCI->HSMCI_PTCR = HSMCI_PTCR_RXTDIS | HSMCI_PTCR_TXTDIS; - - return 1; - } - - // TRACE_ERROR("ok %.2X %.4Xd\n\r", HSMCI->HSMCI_SR, HSMCI->HSMCI_RSPR[0]); - - return 0; -} - -uint32_t sd_write_block( uint32_t block_no, uint32_t *data ) -{ - unsigned int status = 0; - - if (sd_card_ready()) { - -// TRACE_ERROR("write block %d", block_no); - - // Wait for card to be ready for data transfers - do { - sdCmd13(&status); - } while ((status & STATUS_READY_FOR_DATA) == 0); - - // Block size = 512, nblocks = 1 - HSMCI->HSMCI_BLKR = ((512) << 16) | 1; - HSMCI->HSMCI_MR = (HSMCI->HSMCI_MR & (~(HSMCI_MR_BLKLEN_Msk|HSMCI_MR_FBYTE))) | (HSMCI_MR_PDCMODE|HSMCI_MR_WRPROOF) | (512 << 16); - HSMCI->HSMCI_ARGR = (Cmd_A41_resp & OCR_SD_CCS ? block_no : (block_no << 9)); - HSMCI->HSMCI_TPR = (uint32_t)data; - HSMCI->HSMCI_TCR = 512 / 4; - HSMCI->HSMCI_CMDR = SD_WRITE_SINGLE_BLOCK; - - while (!(HSMCI->HSMCI_SR & HSMCI_SR_CMDRDY)); - - (void) HSMCI->HSMCI_RSPR[0]; - - HSMCI->HSMCI_PTCR = HSMCI_PTCR_TXTEN; - - while (1) { - if ((HSMCI->HSMCI_SR & (HSMCI_SR_NOTBUSY|HSMCI_SR_XFRDONE)) == (HSMCI_SR_NOTBUSY|HSMCI_SR_XFRDONE)) { - break; - } - } - - /* Disable PDC */ - HSMCI->HSMCI_PTCR = HSMCI_PTCR_RXTDIS | HSMCI_PTCR_TXTDIS; - HSMCI->HSMCI_MR &= ~(uint32_t)HSMCI_MR_PDCMODE; - - return 1; - } - - return 0; -} - -/* - Notes on SD card: - -1) CMD8 fails and CMD58 fails: must be MMC, thus initialize using CMD1 -2) CMD8 fails and CMD58 passes: must be Ver1.x Standard Capacity SD Memory Card -3) CMD8 passes and CMD58 passes (CCS = 0): must be Ver2.00 or later Standard Capacity SD Memory Card -4) CMD8 passes and CMD58 passes (CCS = 1): must be Ver2.00 or later High Capacity SD Memory Card -5) CMD8 passes and CMD58 passes but indicates non compatible voltage range: unusable card - -On card present -1. Send CMD 55 (resp 48bit) - followed by ACMD41 (resp48bit) - until bit 31 of response is '1' - -2. Send CMD 2 (resp 136bit) - card ID - -3. Send CMD 3 (resp 48 bit) - new RCA returned - -4. Send CMD 9 (resp 136) - CSD - -5. Send CMD 7 (resp 48) - - -6. Send CMD 55 (resp 48bit) - followed by ACMD51 (resp48bit) - SCR stored as 2 32 bit values - -Now decide what the card can do! - -7. Set block length - -8. Set bus width - -9. Read block 0 - -*/ - -/*-----------------------------------------------------------------------*/ -/* Initialize Disk Drive */ -/*-----------------------------------------------------------------------*/ - -DSTATUS disk_initialize ( - BYTE drv /* Physical drive nmuber (0) */ - ) -{ - if (drv) return STA_NOINIT; /* Supports only single drive */ - if ( sd_card_ready() == 0 ) return RES_NOTRDY; - return RES_OK; -} - -/*-----------------------------------------------------------------------*/ -/* Get Disk Status */ -/*-----------------------------------------------------------------------*/ - -DSTATUS disk_status ( - BYTE drv /* Physical drive number (0) */ - ) -{ - if (drv) return STA_NOINIT; /* Supports only single drive */ - if ( sd_card_ready() == 0 ) return RES_NOTRDY; - return RES_OK; -} - -/*-----------------------------------------------------------------------*/ -/* Read Sector(s) */ -/*-----------------------------------------------------------------------*/ - -uint32_t dma_sd_buffer[512/4]; - -DRESULT disk_read ( - BYTE drv, /* Physical drive nmuber (0) */ - BYTE *buff, /* Pointer to the data buffer to store read data */ - DWORD sector, /* Start sector number (LBA) */ - UINT count /* Sector count (1..255) */ - ) -{ - uint32_t result ; - - if (drv || !count) return RES_PARERR; - - if ( sd_card_ready() == 0 ) return RES_NOTRDY; - - do { - result = sd_read_block(sector, dma_sd_buffer) ; - if (result) { - memcpy(buff, dma_sd_buffer, 512); - sector += 1 ; - buff += 512 ; - count -= 1 ; - } - else { - count = 1 ; // Flag error - break ; - } - } while ( count ) ; - - if (!count) - return RES_OK; - - if (++sdErrorCount > 3) - Card_state = SD_ST_ERR; - - return RES_ERROR; -} - - -/*-----------------------------------------------------------------------*/ -/* Write Sector(s) */ -/*-----------------------------------------------------------------------*/ - -extern const char * warningText; - -DRESULT disk_write ( - BYTE drv, /* Physical drive nmuber (0) */ - const BYTE *buff, /* Pointer to the data to be written */ - DWORD sector, /* Start sector number (LBA) */ - UINT count /* Sector count (1..255) */ - ) -{ - uint32_t result ; - - if (drv || !count) return RES_PARERR; - - if ( sd_card_ready() == 0 ) return RES_NOTRDY; - - do { - - while (1) { - - memcpy(dma_sd_buffer, buff, 512); - - result = sd_write_block(sector, dma_sd_buffer) ; - - sd_read_block(sector, dma_sd_buffer) ; - - if (!memcmp(dma_sd_buffer, buff, 512)) - break; - else { - TRACE_ERROR("Block %d ko SR=%.2X\r\n", sector, HSMCI->HSMCI_SR); - // DUMP(buff, 512); - // DUMP(copy, 512); - } - } - - if (result) { - sector += 1 ; - buff += 512 ; - count -= 1 ; - } - else { - count = 1 ; // Flag error - break ; - } - } while ( count ) ; - - if (!count) { - return RES_OK; - } - - if (++sdErrorCount > 3) - Card_state = SD_ST_ERR; - - return RES_ERROR; -} - - - -/*-----------------------------------------------------------------------*/ -/* Miscellaneous Functions */ -/*-----------------------------------------------------------------------*/ - -DRESULT disk_ioctl ( - BYTE drv, /* Physical drive nmuber (0) */ - BYTE ctrl, /* Control code */ - void *buff /* Buffer to send/receive control data */ - ) -{ - DRESULT res; - - if (drv) return RES_PARERR; - - res = RES_ERROR; - - if (ctrl == CTRL_POWER) { -#if 0 - switch (ptr[0]) { - case 0: /* Sub control code (POWER_OFF) */ - power_off(); /* Power off */ - res = RES_OK; - break; - case 1: /* Sub control code (POWER_GET) */ - ptr[1] = (BYTE)power_status(); - res = RES_OK; - break; - default : - res = RES_PARERR; - } -#endif - } - else { - switch (ctrl) { - case CTRL_SYNC : /* Make sure that no pending write process. Do not remove this or written sector might not left updated. */ - res = RES_OK; - break; - - case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */ - *(DWORD*)buff = SD_GET_BLOCKNR(); - res = RES_OK; - break; - - case GET_SECTOR_SIZE : /* Get R/W sector size (WORD) */ - *(WORD*)buff = 512; - res = RES_OK; - break; - - case GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */ - *(WORD*)buff = 1; - res = RES_OK; - break; - -#if 0 - case MMC_GET_TYPE : /* Get card type flags (1 byte) */ - *ptr = CardType; - res = RES_OK; - break; - - case MMC_GET_CSD : /* Receive CSD as a data block (16 bytes) */ - if (send_cmd(CMD9, 0) == 0 /* READ_CSD */ - && rcvr_datablock(ptr, 16)) - res = RES_OK; - break; - - case MMC_GET_CID : /* Receive CID as a data block (16 bytes) */ - if (send_cmd(CMD10, 0) == 0 /* READ_CID */ - && rcvr_datablock(ptr, 16)) - res = RES_OK; - break; - - case MMC_GET_OCR : /* Receive OCR as an R3 resp (4 bytes) */ - if (send_cmd(CMD58, 0) == 0) { /* READ_OCR */ - for (n = 4; n; n--) *ptr++ = rcvr_spi(); - res = RES_OK; - } - break; - - case MMC_GET_SDSTAT : /* Receive SD statsu as a data block (64 bytes) */ - if (send_cmd(ACMD13, 0) == 0) { /* SD_STATUS */ - rcvr_spi(); - if (rcvr_datablock(ptr, 64)) - res = RES_OK; - } - break; -#endif - default: - res = RES_PARERR; - break; - } - // BSS deselect(); - } - - return res; -} diff --git a/radio/src/targets/sky9x/eeprom_driver.cpp b/radio/src/targets/sky9x/eeprom_driver.cpp deleted file mode 100644 index b6785eaa1..000000000 --- a/radio/src/targets/sky9x/eeprom_driver.cpp +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -volatile uint8_t Spi_complete = 1; -uint8_t Spi_tx_buf[24]; - -uint8_t eepromIsTransferComplete() -{ - return Spi_complete; -} - -uint32_t eepromTransmitData(uint8_t *command, uint8_t *tx, uint8_t *rx, uint32_t comlen, uint32_t count) -{ - Spi * spiptr = SPI; - uint32_t condition; - static uint8_t discard_rx_command[4]; - - if (comlen > 4) { - return 0x4FFFF; - } - - Spi_complete = 0; - condition = SPI_SR_TXEMPTY; - spiptr->SPI_CR = 1; // Enable - (void) spiptr->SPI_RDR; // Dump any rx data - (void) spiptr->SPI_SR; // Clear error flags - spiptr->SPI_RPR = (uint32_t)discard_rx_command; - spiptr->SPI_RCR = comlen; - if (rx) { - spiptr->SPI_RNPR = (uint32_t)rx; - spiptr->SPI_RNCR = count; - condition = SPI_SR_RXBUFF; - } - spiptr->SPI_TPR = (uint32_t)command; - spiptr->SPI_TCR = comlen; - if (tx) { - spiptr->SPI_TNPR = (uint32_t)tx; - } - else { - spiptr->SPI_TNPR = (uint32_t)rx; - } - spiptr->SPI_TNCR = count; - - spiptr->SPI_PTCR = SPI_PTCR_RXTEN | SPI_PTCR_TXTEN; // Start transfers - - // Wait for things to get started, avoids early interrupt - for (count = 0; count < 1000; count += 1) { - if ((spiptr->SPI_SR & SPI_SR_TXEMPTY) == 0) - { - break; - } - } - spiptr->SPI_IER = condition; - - return 0; -} - -uint8_t eepromTransmitByte(uint8_t out, bool skipFirst) -{ - Spi * spiptr = SPI; - uint32_t delay; - - spiptr->SPI_CR = 1; // Enable - (void) spiptr->SPI_RDR; // Dump any rx data - - spiptr->SPI_TDR = out; - - delay = 0; - while ((spiptr->SPI_SR & SPI_SR_RDRF) == 0) { - // wait for received - if (++delay > 10000) { - break; - } - } - - if (skipFirst) { - (void) spiptr->SPI_RDR; // Dump the rx data - spiptr->SPI_TDR = 0; - delay = 0; - while ((spiptr->SPI_SR & SPI_SR_RDRF) == 0) { - // wait for received - if (++delay > 10000) { - break; - } - } - } - - spiptr->SPI_CR = 2; // Disable - return spiptr->SPI_RDR; -} - -enum EepromCommand { - COMMAND_WRITE_STATUS_REGISTER = 0x01, - COMMAND_BYTE_PROGRAM = 0x02, - COMMAND_READ_ARRAY = 0x03, - COMMAND_READ_STATUS = 0x05, - COMMAND_WRITE_ENABLE = 0x06, - COMMAND_BLOCK_ERASE = 0x20, -}; - -void eepromPrepareCommand(EepromCommand command, uint32_t address) -{ - uint8_t * p = Spi_tx_buf; - *p = command; - *(p+1) = address >> 16; - *(p+2) = address >> 8; - *(p+3) = address; -} - -uint8_t eepromReadStatus() -{ - uint8_t read_status = eepromTransmitByte(COMMAND_READ_STATUS, true); - return !(read_status & 1); -} - -void eepromWriteStatusRegister() -{ - eepromTransmitByte(COMMAND_WRITE_STATUS_REGISTER, true); -} - -void eepromWriteEnable() -{ - eepromTransmitByte(COMMAND_WRITE_ENABLE, false); -} - -void eepromStartWrite(uint8_t * buffer, size_t address, size_t size) -{ - eepromWriteEnable(); - eepromPrepareCommand(COMMAND_BYTE_PROGRAM, address); - eepromTransmitData(Spi_tx_buf, buffer, 0, 4, size); -} - -void eepromStartRead(uint8_t * buffer, size_t address, size_t size) -{ - eepromPrepareCommand(COMMAND_READ_ARRAY, address); - eepromTransmitData(Spi_tx_buf, 0, buffer, 4, size); -} - -void eepromBlockErase(uint32_t address) -{ - eepromWriteEnable(); - eepromPrepareCommand(COMMAND_BLOCK_ERASE, address); - eepromTransmitData(Spi_tx_buf, 0, 0, 4, 0); -} - -// SPI i/f to EEPROM (4Mb) -// Peripheral ID 21 (0x00200000) -// Connections: -// SS PA11 (peripheral A) -// MISO PA12 (peripheral A) -// MOSI PA13 (peripheral A) -// SCK PA14 (peripheral A) -// Set clock to 3 MHz, AT25 device is rated to 70MHz, 18MHz would be better -void eepromInit() -{ - Spi * spiptr = SPI; - uint32_t timer; - - PMC->PMC_PCER0 |= 0x00200000L; // Enable peripheral clock to SPI - /* Configure PIO */ - configure_pins(0x00007800, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_A | PIN_PORTA | PIN_NO_PULLUP); - - timer = (Master_frequency / 3000000) << 8; // Baud rate 3Mb/s - spiptr->SPI_MR = 0x14000011; // 0001 0100 0000 0000 0000 0000 0001 0001 Master - spiptr->SPI_CSR[0] = 0x01180009 | timer; // 0000 0001 0001 1000 xxxx xxxx 0000 1001 - NVIC_EnableIRQ(SPI_IRQn); - - eepromWriteEnable(); - eepromWriteStatusRegister(); -} - -extern "C" void SPI_IRQHandler() -{ - Spi * spiptr = SPI; - SPI->SPI_IDR = 0x07FF; // All interrupts off - spiptr->SPI_CR = 2; // Disable - (void) spiptr->SPI_RDR; // Dump any rx data - (void) spiptr->SPI_SR; // Clear error flags - spiptr->SPI_PTCR = SPI_PTCR_RXTDIS | SPI_PTCR_TXTDIS; // Stop tramsfers - Spi_complete = 1; // Indicate completion -} diff --git a/radio/src/targets/sky9x/flash_driver.cpp b/radio/src/targets/sky9x/flash_driver.cpp deleted file mode 100644 index 831dec93d..000000000 --- a/radio/src/targets/sky9x/flash_driver.cpp +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -uint32_t (*IAP_Function)(uint32_t, uint32_t); - -void flashWrite(uint32_t * address, const uint32_t * buffer) // size is 256 bytes -{ - uint32_t FlashSectorNum; - uint32_t flash_cmd = 0; - - // Always initialise this here, setting a default doesn't seem to work - IAP_Function = (uint32_t (*)(uint32_t, uint32_t)) *(( uint32_t *)0x00800008); - FlashSectorNum = (uint32_t) address; - FlashSectorNum >>= 8;// page size is 256 bytes - FlashSectorNum &= 2047;// max page number - - /* Send data to the sector here */ - for (int i=0; iEEFC_FRR; -} - -void clearLockBits() -{ - uint32_t i; - uint32_t flash_cmd = 0; - - // Always initialise this here, setting a default doesn't seem to work - IAP_Function = (uint32_t (*)(uint32_t, uint32_t)) *(( uint32_t *)0x00800008); - for ( i = 0; i < 16; i += 1 ) - { - flash_cmd = (0x5A << 24) | ((128*i) << 8) | 0x09; //AT91C_MC_FCMD_CLB ; - __disable_irq(); - /* Call the IAP function with appropriate command */ - (void) IAP_Function( 0, flash_cmd ); - __enable_irq(); - } -} - -uint32_t isFirmwareStart(const uint8_t * buffer) -{ - const uint32_t * block = (const uint32_t *)buffer; - - if ((block[0] & 0xFFFE3000) != 0x20000000 ) { - return 0; - } - if ((block[1] & 0xFFF80000) != 0x00400000) { - return 0; - } - if ((block[2] & 0xFFF80000) != 0x00400000) { - return 0; - } - return 1; -} diff --git a/radio/src/targets/sky9x/haptic_driver.cpp b/radio/src/targets/sky9x/haptic_driver.cpp deleted file mode 100644 index 9c5016007..000000000 --- a/radio/src/targets/sky9x/haptic_driver.cpp +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -void hapticOff() -{ - PWM->PWM_DIS = PWM_DIS_CHID2 ; // Disable channel 2 - PWM->PWM_OOV &= ~0x00040000 ; // Force low - PWM->PWM_OSS |= 0x00040000 ; // Force low -} - -// pwmPercent 0-100 -void hapticOn( uint32_t pwmPercent ) -{ - Pwm *pwmptr ; - - pwmptr = PWM ; - - if (pwmPercent > 100) { - pwmPercent = 100 ; - } - - pwmptr->PWM_CH_NUM[2].PWM_CDTYUPD = pwmPercent ; // Duty - pwmptr->PWM_ENA = PWM_ENA_CHID2 ; // Enable channel 2 - pwmptr->PWM_OSC = 0x00040000 ; // Enable output -} diff --git a/radio/src/targets/sky9x/i2c_driver.cpp b/radio/src/targets/sky9x/i2c_driver.cpp deleted file mode 100644 index d0d914573..000000000 --- a/radio/src/targets/sky9x/i2c_driver.cpp +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" -#include "twi.h" - -#define I2C_CLK_FAST 400000 - -uint32_t fromBCD(uint8_t bcd_value) -{ - return (((bcd_value & 0xF0) * 10) >> 4) + (bcd_value & 0x0F); -} - -uint8_t toBCD(uint32_t value) -{ - div_t qr = div(value, 10); - return (qr.quot << 4) + qr.rem; -} - -twi_packet getPacket(uint8_t chip, uint8_t* addr, uint8_t addr_len, uint8_t *buffer, uint32_t length) -{ - twi_packet packet; - packet.chip = chip; - for (uint8_t i = 0; i < addr_len; ++i) - packet.addr[i] = addr[i]; - packet.addr_length = addr_len; - packet.buffer = buffer; - packet.length = length; - return packet; -} - -bool i2cInit() -{ - //Enable Peripheral Clock - PMC->PMC_PCER0 |= 0x00080000L; - //Enable TWI PIOs - Pio *pioptr; - pioptr = PIOA; - pioptr->PIO_ABCDSR[0] &= ~0x00000018; // Peripheral A - pioptr->PIO_ABCDSR[1] &= ~0x00000018; // Peripheral A - pioptr->PIO_PDR = 0x00000018; // Assign to peripheral - - twi_enable_master_mode(TWI0); - twi_options_t opt; - opt.master_clk = Master_frequency; - opt.speed = I2C_CLK_FAST; - return twi_master_init(TWI0, &opt) == TWI_SUCCESS; -} - -void i2cCheck() -{ -} - -uint32_t i2cReadBuffer(uint8_t chip, uint8_t* addr, uint8_t addr_len, uint8_t *buffer, uint32_t length) -{ - twi_packet packet(getPacket(chip, addr, addr_len, buffer, length)); - return twi_master_read(TWI0, &packet); -} - -uint32_t i2cWriteBuffer(uint8_t chip, uint8_t* addr, uint8_t addr_len, uint8_t *buffer, uint32_t length) -{ - twi_packet packet(getPacket(chip, addr, addr_len, buffer, length)); - return twi_master_write(TWI0, &packet); -} diff --git a/radio/src/targets/sky9x/i2c_driver.h b/radio/src/targets/sky9x/i2c_driver.h deleted file mode 100644 index 85bbec856..000000000 --- a/radio/src/targets/sky9x/i2c_driver.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _I2C_DRIVER_H_ -#define _I2C_DRIVER_H_ - -#include "stdint.h" - -uint32_t fromBCD(uint8_t bcd_value); -uint8_t toBCD(uint32_t value); - -bool i2cInit(); -uint32_t i2cReadBuffer(uint8_t chip, uint8_t *addr, uint8_t addr_len, uint8_t *buffer, uint32_t length); -uint32_t i2cWriteBuffer(uint8_t chip, uint8_t *addr, uint8_t addr_len, uint8_t *buffer, uint32_t length); - -#endif diff --git a/radio/src/targets/sky9x/joystick.cpp b/radio/src/targets/sky9x/joystick.cpp deleted file mode 100644 index 877da2481..000000000 --- a/radio/src/targets/sky9x/joystick.cpp +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -extern "C" { -#include "usb/device/hid-joystick/HIDDJoystickDriver.h" -extern void HIDDJoystickDriver_Initialize(); -unsigned char HIDDJoystickDriver_ChangeJoystickState(const HIDDJoystickInputReport *report); -extern void USBD_Connect(void); -} - -static void ConfigureUsbClock(void) -{ - /* Enable PLLB for USB */ - PMC->CKGR_PLLBR = CKGR_PLLBR_DIVB(1) - | CKGR_PLLBR_MULB(7) - | CKGR_PLLBR_PLLBCOUNT_Msk; - while((PMC->PMC_SR & PMC_SR_LOCKB) == 0); // TODO && (timeout++ < CLOCK_TIMEOUT)); - /* USB Clock uses PLLB */ - PMC->PMC_USB = PMC_USB_USBDIV(1) /* /2 */ - | PMC_USB_USBS; /* PLLB */ -} - -void usbJoystickUpdate() -{ - static bool initialized = false; - - if (usbPlugged()) { - TRACE_DEBUG("usbJoystick\n\r"); - - if (!initialized) { - ConfigureUsbClock(); - - HIDDJoystickDriver_Initialize(); - - // VBus_Configure(); - USBD_Connect(); - - initialized = true; - } - - static uint8_t HID_Buffer[11]; - - HID_Buffer[0] = 0; - HID_Buffer[1] = 0; - HID_Buffer[2] = 0; - for (int i = 0; i < 8; ++i) { - if ( channelOutputs[i+8] > 0 ) { - HID_Buffer[0] |= (1 << i); - } - if ( channelOutputs[i+16] > 0 ) { - HID_Buffer[1] |= (1 << i); - } - if ( channelOutputs[i+24] > 0 ) { - HID_Buffer[2] |= (1 << i); - } - } - - //analog values - //uint8_t * p = HID_Buffer + 1; - for (int i = 0; i < 8; ++i) { - int16_t value = channelOutputs[i] / 8; - if ( value > 127 ) value = 127; - else if ( value < -127 ) value = -127; - HID_Buffer[i+3] = static_cast(value); - } - - HIDDJoystickDriver_ChangeJoystickState((HIDDJoystickInputReport*)&HID_Buffer); - } -} diff --git a/radio/src/targets/sky9x/keys_driver.cpp b/radio/src/targets/sky9x/keys_driver.cpp deleted file mode 100644 index fb24c16f6..000000000 --- a/radio/src/targets/sky9x/keys_driver.cpp +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - - -// keys: -// KEY_EXIT PA31 (PC24) -// KEY_MENU PB6 (PB5) -// KEY_DOWN LCD5 PC3 (PC5) -// KEY_UP LCD6 PC2 (PC1) -// KEY_RIGHT LCD4 PC4 (PC4) -// KEY_LEFT LCD3 PC5 (PC3) -// Reqd. bit 6 LEFT, 5 RIGHT, 4 UP, 3 DOWN 2 EXIT 1 MENU -// LCD pins 5 DOWN, 4 RIGHT, 3 LEFT, 1 UP -uint32_t readKeys() -{ - uint32_t x; - uint32_t result = 0; - - x = lcdLock ? lcdInputs : PIOC->PIO_PDSR; // 6 LEFT, 5 RIGHT, 4 DOWN, 3 UP () - x = ~x; - - if (x & KEYS_GPIO_PIN_RIGHT) - result |= 0x02 << KEY_RIGHT; - if (x & KEYS_GPIO_PIN_UP) - result |= 0x02 << KEY_UP; - if (x & KEYS_GPIO_PIN_LEFT) - result |= 0x02 << KEY_LEFT; - if (x & KEYS_GPIO_PIN_DOWN) - result |= 0x02 << KEY_DOWN; - if (x & KEYS_GPIO_PIN_EXIT) - result |= 0x02 << KEY_EXIT; - if (~KEYS_GPIO_REG_MENU & KEYS_GPIO_PIN_MENU) - result |= 0x02 << KEY_MENU; - - // TRACE("readKeys(): %x => %x", x, result); - - return result; -} - -uint32_t readTrims() -{ - uint32_t result = 0; - - if (~TRIMS_GPIO_REG_LHL & TRIMS_GPIO_PIN_LHL) - result |= 0x01; - if (~TRIMS_GPIO_REG_LVD & TRIMS_GPIO_PIN_LVD) - result |= 0x04; - if (~TRIMS_GPIO_REG_RVU & TRIMS_GPIO_PIN_RVU) - result |= 0x20; - if (~TRIMS_GPIO_REG_RHL & TRIMS_GPIO_PIN_RHL) - result |= 0x40; - if (~TRIMS_GPIO_REG_LHR & TRIMS_GPIO_PIN_LHR) - result |= 0x02; - if (~TRIMS_GPIO_REG_LVU & TRIMS_GPIO_PIN_LVU) - result |= 0x08; - if (~TRIMS_GPIO_REG_RVD & TRIMS_GPIO_PIN_RVD) - result |= 0x10; - if (~TRIMS_GPIO_REG_RHR & TRIMS_GPIO_PIN_RHR) - result |= 0x80; - - return result; -} - -bool trimDown(uint8_t idx) -{ - return readTrims() & (1 << idx); -} - -bool keyDown() -{ - return readKeys() || REA_DOWN(); -} - -void readKeysAndTrims() -{ - uint32_t i; - - uint8_t index = 0; - uint8_t keys_input = readKeys(); - for (i = 1; i < 7; i++) { - keys[index].input(keys_input & (1 << i)); - ++index; - } - - uint8_t trims_input = readTrims(); - for (i = 1; i < 256; i <<= 1) { - keys[index].input(trims_input & i); - ++index; - } - - if ((keys_input || trims_input) && (g_eeGeneral.backlightMode & e_backlight_mode_keys)) { - // on keypress turn the light on - resetBacklightTimeout(); - } -} - -uint32_t switchState(uint8_t index) -{ - uint32_t a = PIOA->PIO_PDSR; - uint32_t c = PIOC->PIO_PDSR; - - uint32_t xxx = 0; - - switch (index) { - case SW_ELE: - xxx = c & 0x80000000; // ELE_DR PC31 - break; - - case SW_AIL: - xxx = a & 0x00000004; // AIL-DR PA2 - break; - - case SW_RUD: - xxx = a & 0x00008000; // RUN_DR PA15 - break; - // INP_G_ID1 INP_E_ID2 - // id0 0 1 - // id1 1 1 - // id2 1 0 - case SW_ID0: - xxx = ~c & 0x00004000; // SW_IDL1 PC14 - break; - case SW_ID1: - xxx = (c & 0x00004000); - if (xxx) xxx = (c & 0x00000800); - break; - case SW_ID2: - xxx = ~c & 0x00000800; // SW_IDL2 PC11 - break; - - case SW_GEA: - xxx = c & 0x00010000; // SW_GEAR PC16 - break; - - case SW_THR: - xxx = c & 0x00100000; // SW_TCUT PC20 - break; - - case SW_TRN: - xxx = c & 0x00000100; // SW-TRAIN PC8 - break; - - default: - break; - } - - return xxx; -} diff --git a/radio/src/targets/sky9x/lcd_driver.cpp b/radio/src/targets/sky9x/lcd_driver.cpp deleted file mode 100644 index 330fa0e3c..000000000 --- a/radio/src/targets/sky9x/lcd_driver.cpp +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -// LCD i/o pins -// LCD_RES PC27 -// LCD_CS1 PC26 -// LCD_E PC12 -// LCD_RnW PC13 -// LCD_A0 PC15 -// LCD_D0 PC0 -// LCD_D1 PC7 -// LCD_D2 PC6 -// LCD_D3 PC5 -// LCD_D4 PC4 -// LCD_D5 PC3 -// LCD_D6 PC2 -// LCD_D7 PC1 - -#define LCD_DATA 0x000000FFL -#define LCD_A0 0x00000080L -#define LCD_RnW 0x00002000L -#define LCD_E 0x00001000L -#define LCD_CS1 0x04000000L -#define LCD_RES 0x08000000L - -void lcdSendCtl(uint8_t val) -{ - Pio *pioptr; - - pioptr = PIOC; -#if !defined(REVX) - pioptr->PIO_CODR = LCD_CS1; // Select LCD -#endif - PIOA->PIO_CODR = LCD_A0; -#if !defined(REVX) - pioptr->PIO_CODR = LCD_RnW; // Write -#endif - pioptr->PIO_ODSR = val; - - pioptr->PIO_SODR = LCD_E; // Start E pulse - // Need a delay here (250nS) - TC0->TC_CHANNEL[0].TC_CCR = 5; // Enable clock and trigger it (may only need trigger) - while ( TC0->TC_CHANNEL[0].TC_CV < 9 ) // Value depends on MCK/2 (used 18MHz) - { - // Wait - } - pioptr->PIO_CODR = LCD_E; // End E pulse - PIOA->PIO_SODR = LCD_A0; // Data - -#if !defined(REVX) - pioptr->PIO_SODR = LCD_CS1; // Deselect LCD -#endif -} - -void lcdInit() -{ - Pio *pioptr; - // /home/thus/txt/datasheets/lcd/KS0713.pdf - // ~/txt/flieger/ST7565RV17.pdf from http://www.glyn.de/content.asp?wdid=132&sid= - - // read the inputs, and lock the LCD lines - lcdInputs = PIOC->PIO_PDSR; // 6 LEFT, 5 RIGHT, 4 DOWN, 3 UP () - lcdLock = 1; - - configure_pins( LCD_A0, PIN_ENABLE | PIN_LOW | PIN_OUTPUT | PIN_PORTA | PIN_NO_PULLUP ); - pioptr = PIOC; -#if defined(REVX) - pioptr->PIO_PER = PIO_PC27 | PIO_PC12 | 0xFF; - pioptr->PIO_CODR = LCD_E; - pioptr->PIO_CODR = LCD_RnW | LCD_CS1; // No longer needed, used elsewhere -#else - pioptr->PIO_PER = PIO_PC27 | PIO_PC26 | PIO_PC13 | PIO_PC12 | 0xFF; - pioptr->PIO_CODR = LCD_E | LCD_RnW | LCD_CS1; -#endif - pioptr->PIO_SODR = LCD_RES; - pioptr->PIO_OER = PIO_PC27 | PIO_PC26 | PIO_PC13 | PIO_PC12 | 0xFF; // Set bits 27,26,13,12,7-0 output - pioptr->PIO_OWER = 0x000000FFL; // Allow write to ls 8 bits in ODSR - - TC0->TC_CHANNEL[0].TC_CCR = 5; // Enable clock and trigger it (may only need trigger) - pioptr->PIO_CODR = LCD_RES; // Reset LCD - while ( TC0->TC_CHANNEL[0].TC_CV < 500 ) ; // > 10us, Value depends on MCK/2 (used 18MHz) - TC0->TC_CHANNEL[0].TC_CCR = 5; // Enable clock and trigger it (may only need trigger) - pioptr->PIO_SODR = LCD_RES; // Remove LCD reset - while ( TC0->TC_CHANNEL[0].TC_CV < 27000 ) ; // 1500us, Value depends on MCK/2 (used 18MHz) - lcdSendCtl(0xe2); //Initialize the internal functions - lcdSendCtl(0xae); //DON = 0: display OFF - lcdSendCtl(0xa1); //ADC = 1: reverse direction(SEG132->SEG1) - lcdSendCtl(0xA6); //REV = 0: non-reverse display - lcdSendCtl(0xA4); //EON = 0: normal display. non-entire - lcdSendCtl(0xA2); // Select LCD bias=0 - lcdSendCtl(0xC0); //SHL = 0: normal direction (COM1->COM64) - lcdSendCtl(0x2F); //Control power circuit operation VC=VR=VF=1 - lcdSendCtl(0x25); //Select int resistance ratio R2 R1 R0 =5 - lcdSendCtl(0x81); //Set reference voltage Mode - lcdSendCtl(0x22); // 24 SV5 SV4 SV3 SV2 SV1 SV0 = 0x18 - -#if defined(REVX) - // 200mS delay (only if not wdt reset) - if ( ( ( ResetReason & RSTC_SR_RSTTYP ) != (2 << 8) ) && !globalData.unexpectedShutdown ) { - for (uint32_t j = 0; j < 100; j += 1 ) { - TC0->TC_CHANNEL[0].TC_CCR = 5; // Enable clock and trigger it (may only need trigger) - while ( TC0->TC_CHANNEL[0].TC_CV < 36000 ) { - // Value depends on MCK/2 (used 18MHz) give 2mS delay - WDG_RESET(); // Wait - } - } - } -#endif - - lcdSendCtl(0xAF); // DON = 1: display ON - - pioptr->PIO_ODR = 0x0000003AL; // Set bits 1, 3, 4, 5 input - pioptr->PIO_PUER = 0x0000003AL; // Set bits 1, 3, 4, 5 with pullups - pioptr->PIO_ODSR = 0; // Drive D0 low - - lcdLock = 0; -} - -void lcdSetRefVolt(uint8_t val) -{ - Pio *pioptr; - pioptr = PIOC; - - // read the inputs, and lock the LCD lines - lcdInputs = PIOC->PIO_PDSR; // 6 LEFT, 5 RIGHT, 4 DOWN, 3 UP () - lcdLock = 1; - - pioptr->PIO_OER = 0x0C00B0FFL; // Set bits 27,26,15,13,12,7-0 output - - lcdSendCtl(0x81); - if ( val == 0 ) - { - val = 0x22; - } - lcdSendCtl(val); - - pioptr->PIO_ODR = 0x000000FEL; // Set bits 1, 3, 4, 5 input - pioptr->PIO_PUER = 0x000000FEL; // Set bits 1, 3, 4, 5 with pullups - pioptr->PIO_ODSR = 0; // Drive D0 low - - lcdLock = 0; -} - -void lcdRefresh() -{ - Pio *pioptr; - uint8_t *p = displayBuf; - uint32_t y; - uint32_t x; - uint32_t z; - uint32_t ebit; - - ebit = LCD_E; - - pioptr = PIOA; - pioptr->PIO_PER = 0x00000080; // Enable bit 7 (LCD-A0) - pioptr->PIO_OER = 0x00000080;// Set bit 7 output - - // read the inputs, and lock the LCD lines - lcdInputs = PIOC->PIO_PDSR; // 6 LEFT, 5 RIGHT, 4 DOWN, 3 UP () - lcdLock = 1; - - pioptr = PIOC; - pioptr->PIO_OER = 0x0C0030FFL; // Set bits 27,26,15,13,12,7-0 output - for (y = 0; y < 8; y++) { - lcdSendCtl(g_eeGeneral.optrexDisplay ? 0 : 0x04); - lcdSendCtl(0x10); //column addr 0 - lcdSendCtl(y | 0xB0); //page addr y - -#if !defined(REVX) - pioptr->PIO_CODR = LCD_CS1; // Select LCD -#endif - PIOA->PIO_SODR = LCD_A0; // Data -#if !defined(REVX) - pioptr->PIO_CODR = LCD_RnW; // Write -#endif - - x = *p; - for (z = 0; z < LCD_W; z += 1) { - pioptr->PIO_ODSR = x; - pioptr->PIO_SODR = ebit; // Start E pulse - // Need a delay here (250nS) - p += 1; - x = *p; -// TC0->TC_CHANNEL[0].TC_CCR = 5; // Enable clock and trigger it (may only need trigger) -// while ( TC0->TC_CHANNEL[0].TC_CV < 3 ) // Value depends on MCK/2 (used 6MHz) -// { -// // Wait -// } - pioptr->PIO_CODR = ebit; // End E pulse - } -#if !defined(REVX) - pioptr->PIO_SODR = LCD_CS1; // Deselect LCD -#endif - } - - pioptr->PIO_ODSR = 0xFF; // Drive lines high - pioptr->PIO_PUER = 0x000000FEL; // Set bits 1, 3, 4, 5 with pullups - pioptr->PIO_ODR = 0x000000FEL; // Set bits 1, 3, 4, 5 input - pioptr->PIO_ODSR = 0xFE; // Drive D0 low - lcdLock = 0; -} diff --git a/radio/src/targets/sky9x/massstorage.cpp b/radio/src/targets/sky9x/massstorage.cpp deleted file mode 100644 index 1f71a43c8..000000000 --- a/radio/src/targets/sky9x/massstorage.cpp +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -#ifndef SIMU - -extern "C" { -#include "usb/device/massstorage/MSDDriver.h" -extern unsigned char MEDSdcard_Initialize(Media *media, unsigned char mciID); -} - -/** LUN read/write buffer. */ -unsigned char msdBuffer[MSD_BUFFER_SIZE]; - -unsigned int msdReadTotal=0, msdWriteTotal=0; - -static void ConfigureUsbClock(void) -{ - /* Enable PLLB for USB */ - PMC->CKGR_PLLBR = CKGR_PLLBR_DIVB(1) - | CKGR_PLLBR_MULB(7) - | CKGR_PLLBR_PLLBCOUNT_Msk; - while((PMC->PMC_SR & PMC_SR_LOCKB) == 0); // TODO && (timeout++ < CLOCK_TIMEOUT)); - /* USB Clock uses PLLB */ - PMC->PMC_USB = PMC_USB_USBDIV(1) /* /2 */ - | PMC_USB_USBS; /* PLLB */ -} - -/** Maximum number of LUNs which can be defined. */ -#define MAX_LUNS 1 - -/** Media index for different disks */ -#define DRV_SDMMC 0 /** SD card */ - -Media medias[MAX_LUNS]; - -/*---------------------------------------------------------------------------- - * Local variables - *----------------------------------------------------------------------------*/ - -/** Device LUNs. */ -MSDLun luns[MAX_LUNS]; - -int itoa(int val, char* buf) -{ - const unsigned int radix = 10; - - char* p; - unsigned int a; //every digit - int len; - char* b; //start of the digit char - char temp; - unsigned int u; - - p = buf; - -#if 0 - if (val < 0) - { - *p++ = '-'; - val = 0 - val; - } -#endif - - u = (unsigned int)val; - - b = p; - - do - { - a = u % radix; - u /= radix; - - *p++ = a + '0'; - - } while (u > 0); - - len = (int)(p - buf); - - *p-- = 0; - - //swap - do - { - temp = *p; - *p = *b; - *b = temp; - --p; - ++b; - - } while (b < p); - - return len; -} - -uint8_t write_bytes(char *str, uint32_t bytes) -{ - uint8_t len; - if (bytes < 1024*100) { - len = itoa(bytes / 1024, str); - str[len] = '.'; - str[len+1] = '0' + ((bytes % 1024) / 103); - str[len+2] = 'K'; - str[len+3] = '\0'; - len += 3; - } - else if (bytes < 1024*1024) { - len = itoa(bytes / 1024, str); - str[len] = 'K'; - str[len+1] = '\0'; - len += 1; - } - else if (bytes < 1024*1024*100) { - len = itoa(bytes / (1024*1024), str); - str[len] = '.'; - str[len+1] = '0' + ((bytes % (1024*1024)) / 104858); - str[len+2] = 'M'; - str[len+3] = '\0'; - len += 3; - } - else { - len = itoa(bytes / (1024*1024), str); - str[len] = 'M'; - str[len+1] = '\0'; - len += 1; - } - return len; -} - -static void MSDCallbacks_Data( unsigned char flowDirection, unsigned int dataLength, - unsigned int fifoNullCount, unsigned int fifoFullCount ) -{ - if (flowDirection) - msdReadTotal += dataLength; - else - msdWriteTotal += dataLength; - - strcpy(statusLineMsg, "USB Rd:"); - uint8_t len = write_bytes(statusLineMsg+7, msdReadTotal); - strcpy(statusLineMsg+7+len, " Wr:"); - write_bytes(statusLineMsg+7+len+4, msdWriteTotal); - showStatusLine(); -} - -void usbMassStorage() -{ - static bool initialized = false; - - if (usbPlugged() && sd_card_ready()) { - TRACE_DEBUG("usbMassStorage\n\r"); - - if (sdMounted()) { - Card_state = SD_ST_DATA; - audioQueue.stopSD(); - logsClose(); - f_mount(nullptr, "", 0); // unmount SD - } - - if (!initialized) { - - ConfigureUsbClock(); - - /* Initialize LUN */ - MEDSdcard_Initialize(&(medias[DRV_SDMMC]), 0); - - LUN_Init(&(luns[DRV_SDMMC]), &(medias[DRV_SDMMC]), - msdBuffer, MSD_BUFFER_SIZE, - 0, 0, 0, 0, - MSDCallbacks_Data); - - /* BOT driver initialization */ - MSDDriver_Initialize(luns, 1); - - // VBus_Configure(); - USBD_Connect(); - - initialized = true; - } - - /* Mass storage state machine */ - for (uint8_t i=0; i<50; i++) - MSDDriver_StateMachine(); - } - else { - msdReadTotal = 0; - msdWriteTotal = 0; - } -} - -#endif diff --git a/radio/src/targets/sky9x/pulses_driver.cpp b/radio/src/targets/sky9x/pulses_driver.cpp deleted file mode 100644 index 351170813..000000000 --- a/radio/src/targets/sky9x/pulses_driver.cpp +++ /dev/null @@ -1,313 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -void setExternalModulePolarity() -{ - Pwm * pwmptr = PWM; - pwmptr->PWM_CH_NUM[3].PWM_CDTYUPD = GET_MODULE_PPM_DELAY(EXTERNAL_MODULE) * 2; // Duty in half uS - if (GET_MODULE_PPM_POLARITY(EXTERNAL_MODULE)) - pwmptr->PWM_CH_NUM[3].PWM_CMR &= ~0x00000200; // CPOL - else - pwmptr->PWM_CH_NUM[3].PWM_CMR |= 0x00000200; // CPOL -} - -void setExtraModulePolarity() -{ - Pwm * pwmptr = PWM; - pwmptr->PWM_CH_NUM[1].PWM_CDTYUPD = GET_MODULE_PPM_DELAY(EXTRA_MODULE) * 2; // Duty in half uS - if (GET_MODULE_PPM_POLARITY(EXTRA_MODULE)) - pwmptr->PWM_CH_NUM[1].PWM_CMR &= ~0x00000200; // CPOL - else - pwmptr->PWM_CH_NUM[1].PWM_CMR |= 0x00000200; // CPOL -} - -void module_output_active() -{ - Pio *pioptr = PIOA; - pioptr->PIO_ABCDSR[0] &= ~PIO_PA17; // Peripheral C - pioptr->PIO_ABCDSR[1] |= PIO_PA17; // Peripheral C - pioptr->PIO_PDR = PIO_PA17; // Disable bit A17 Assign to peripheral -#if defined(REVX) - if (g_model.moduleData[EXTERNAL_MODULE].ppm.outputType) { - pioptr->PIO_MDDR = PIO_PA17; // Push Pull O/p in A17 - } - else { - pioptr->PIO_MDER = PIO_PA17; // Open Drain O/p in A17 - } -#else - pioptr->PIO_MDDR = PIO_PA17; // Push Pull O/p in A17 -#endif - pioptr->PIO_PUER = PIO_PA17; // With pull up -} - -void init_main_ppm(uint32_t period, uint32_t out_enable) -{ - Pwm * pwmptr; - - if (out_enable) { - module_output_active(); - } - - pwmptr = PWM; - // PWM3 for PPM output - pwmptr->PWM_CH_NUM[3].PWM_CMR = 0x0004000B; // CLKA - pwmptr->PWM_CH_NUM[3].PWM_CPDR = period; // Period in half uS - pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period; // Period in half uS - pwmptr->PWM_CH_NUM[3].PWM_CDTY = GET_MODULE_PPM_DELAY(EXTERNAL_MODULE) * 2; // Duty in half uS - pwmptr->PWM_ENA = PWM_ENA_CHID3; // Enable channel 3 - pwmptr->PWM_IER1 = PWM_IER1_CHID3; - - setExternalModulePolarity(); - - NVIC_SetPriority(PWM_IRQn, 3); - NVIC_EnableIRQ(PWM_IRQn); -} - -void disable_main_ppm() -{ - Pio * pioptr = PIOA; - pioptr->PIO_PER = PIO_PA17; // Assign A17 to PIO - PWM->PWM_IDR1 = PWM_IDR1_CHID3; -} - -void init_second_ppm(uint32_t period) -{ - // PWM1 for PPM2 - Pwm * pwmptr = PWM; - configure_pins(PIO_PC15, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_B | PIN_PORTC | PIN_NO_PULLUP); - pwmptr->PWM_CH_NUM[1].PWM_CMR = 0x0000000B; // CLKB - if (!GET_MODULE_PPM_POLARITY(EXTRA_MODULE)) { - pwmptr->PWM_CH_NUM[1].PWM_CMR |= 0x00000200; // CPOL - } - pwmptr->PWM_CH_NUM[1].PWM_CPDR = period; // Period - pwmptr->PWM_CH_NUM[1].PWM_CPDRUPD = period; // Period - pwmptr->PWM_CH_NUM[1].PWM_CDTY = GET_MODULE_PPM_DELAY(EXTRA_MODULE)*2; // Duty - pwmptr->PWM_CH_NUM[1].PWM_CDTYUPD = GET_MODULE_PPM_DELAY(EXTRA_MODULE)*2; // Duty - pwmptr->PWM_ENA = PWM_ENA_CHID1; // Enable channel 1 - pwmptr->PWM_IER1 = PWM_IER1_CHID1; - - setExtraModulePolarity(); -} - -/* -// TODO re-add it later -void disable_second_ppm() -{ - Pio * pioptr = PIOC; - pioptr->PIO_PER = PIO_PC15; // Assign C17 to PIO - PWM->PWM_IDR1 = PWM_IDR1_CHID1; -} - -void init_module_timer(uint32_t port, uint32_t period, uint8_t state) -{ - if (port == EXTERNAL_MODULE) { - // TODO use period here - init_main_ppm(3000, 0); - } -} -*/ - -void extmodulePpmStart() -{ - init_main_ppm(3000, 1); -} - -void extramodulePpmStart() -{ - init_second_ppm(3000); -} - -// Initialise the SSC to allow PXX output. -// TD is on PA17, peripheral A -void init_ssc(uint8_t baudrateDiv1000) -{ - Ssc *sscptr; - - PMC->PMC_PCER0 |= 0x00400000L; // Enable peripheral clock to SSC - - configure_pins(PIO_PA17, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_A | PIN_PORTA); - - sscptr = SSC; - sscptr->SSC_THR = 0xFF; // Make the output high. - sscptr->SSC_TFMR = 0x00000027; // 0000 0000 0000 0000 0000 0000 1010 0111 (8 bit data, lsb) - sscptr->SSC_CMR = Master_frequency / (1000 * baudrateDiv1000 * 2); - sscptr->SSC_TCMR = 0; - sscptr->SSC_CR = SSC_CR_TXEN; - -#if defined(REVX) - if (isModuleMultimodule(EXTERNAL_MODULE)) { - PIOA->PIO_MDDR = PIO_PA17; // Push Pull O/p in A17 - } else { - PIOA->PIO_MDER = PIO_PA17; // Open Drain O/p in A17 - } -#else - PIOA->PIO_MDDR = PIO_PA17; // Push Pull O/p in A17 -#endif -} - -void disable_ssc() -{ - Pio *pioptr; - Ssc *sscptr; - - // Revert back to pwm output - pioptr = PIOA; - pioptr->PIO_PER = PIO_PA17; // Assign A17 to PIO - - sscptr = SSC; - sscptr->SSC_CR = SSC_CR_TXDIS; -} - -void extmodulePxx1PulsesStart() -{ - init_main_ppm(2500 * 2, 0); - init_ssc(125); // 8us per bit -} - -void extmoduleStop() -{ - disable_ssc(); - disable_main_ppm(); -} - -void extmoduleSerialStart(uint32_t baudrate, uint32_t period_half_us, bool inverted) -{ - if (baudrate == 125000) { - // TODO init_main_ppm could take the period as parameter? - init_main_ppm(2500 * 2, 0); - init_ssc(125); - } - else { - init_main_ppm(3500 * 2, 0); - init_ssc(100); - } -} - -void extmoduleSendNextFrame() -{ -} - -#if !defined(SIMU) -extern "C" void PWM_IRQHandler(void) -{ - Pwm * pwmptr = PWM; - uint32_t reason = pwmptr->PWM_ISR1; - uint32_t period; - - if (reason & PWM_ISR1_CHID3) { - // Use the current protocol, don't switch until set_up_pulses - switch (moduleState[EXTERNAL_MODULE].protocol) { - case PROTOCOL_CHANNELS_PXX1_PULSES: - // Alternate periods of 6.5mS and 2.5 mS - period = pwmptr->PWM_CH_NUM[3].PWM_CPDR; - if (period == 2500 * 2) { - period = 6500 * 2; - } - else { - period = 2500 * 2; - } - pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period; // Period in half uS - if (period != 2500 * 2) { - setupPulsesExternalModule(); - setExternalModulePolarity(); - } - else { - // Kick off serial output here - Ssc * sscptr = SSC; - sscptr->SSC_TPR = CONVERT_PTR_UINT(extmodulePulsesData.pxx.getData()); - sscptr->SSC_TCR = extmodulePulsesData.pxx.getSize(); - sscptr->SSC_PTCR = SSC_PTCR_TXTEN; // Start transfers - } - break; - - case PROTOCOL_CHANNELS_DSM2_LP45: - case PROTOCOL_CHANNELS_DSM2_DSM2: - case PROTOCOL_CHANNELS_DSM2_DSMX: - // Alternate periods of 19.5mS and 2.5 mS - period = pwmptr->PWM_CH_NUM[3].PWM_CPDR; - if (period == 2500 * 2) { - period = 19500 * 2; - } - else { - period = 2500 * 2; - } - pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period; // Period in half uS - if (period != 2500 * 2) { - setupPulsesExternalModule(); - } - else { - // Kick off serial output here - Ssc * sscptr = SSC; - sscptr->SSC_TPR = CONVERT_PTR_UINT(extmodulePulsesData.dsm2.pulses); - sscptr->SSC_TCR = (uint8_t *)extmodulePulsesData.dsm2.ptr - (uint8_t *)extmodulePulsesData.dsm2.pulses; - sscptr->SSC_PTCR = SSC_PTCR_TXTEN; // Start transfers - } - break; - -#if defined(MULTIMODULE) - case PROTOCOL_CHANNELS_MULTIMODULE: -#endif - case PROTOCOL_CHANNELS_SBUS: - // Todo: how to do inverted polarity on this platform? - // Alternate periods of 5.5mS and 3.5 mS - period = pwmptr->PWM_CH_NUM[3].PWM_CPDR; - if (period == 3500 * 2) { - period = 5500 * 2; - } - else { - period = 3500 * 2; - } - pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period; // Period in half uS - if (period != 3500 * 2) { - setupPulsesExternalModule(); - } - else { - // Kick off serial output here - Ssc * sscptr = SSC; - sscptr->SSC_TPR = CONVERT_PTR_UINT(extmodulePulsesData.dsm2.pulses); - sscptr->SSC_TCR = (uint8_t *)extmodulePulsesData.dsm2.ptr - (uint8_t *)extmodulePulsesData.dsm2.pulses; - sscptr->SSC_PTCR = SSC_PTCR_TXTEN; // Start transfers - } - break; - - default: - pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = *extmodulePulsesData.ppm.ptr++; - if (*extmodulePulsesData.ppm.ptr == 0) { - setExternalModulePolarity(); - setupPulsesExternalModule(); - } - break; - - } - } - - if (reason & PWM_ISR1_CHID1) { - // TODO EXTRA_MODULE will be broken - /*pwmptr->PWM_CH_NUM[1].PWM_CPDRUPD = *modulePulsesData[EXTRA_MODULE].ppm.ptr++; - if (*modulePulsesData[EXTRA_MODULE].ppm.ptr == 0) { - setupPulses(EXTRA_MODULE); - setExtraModulePolarity(); - }*/ - } -} -#endif diff --git a/radio/src/targets/sky9x/pwr_driver.cpp b/radio/src/targets/sky9x/pwr_driver.cpp deleted file mode 100644 index 2cb8bc9c8..000000000 --- a/radio/src/targets/sky9x/pwr_driver.cpp +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -void pwrInit() -{ - // Configure RF_power (PC17) - configure_pins(PIO_PC17, PIN_ENABLE | PIN_INPUT | PIN_PORTC | PIN_NO_PULLUP | PIN_PULLDOWN); - configure_pins(PIO_PA8, PIN_ENABLE | PIN_INPUT | PIN_PORTA | PIN_PULLUP); // Enable bit A8 (Soft Power) -} - -bool pwrPressed() -{ -#if defined(SIMU) - return true; -#else - return PIOC->PIO_PDSR & PIO_PC17; -#endif -} - -void pwrOn() -{ -} - -// turn off soft power -void pwrOff() -{ - configure_pins(PIO_PA8, PIN_ENABLE | PIN_OUTPUT | PIN_LOW | PIN_PORTA | PIN_NO_PULLUP); -} diff --git a/radio/src/targets/sky9x/rotary_encoder_driver.cpp b/radio/src/targets/sky9x/rotary_encoder_driver.cpp deleted file mode 100644 index 1641e307d..000000000 --- a/radio/src/targets/sky9x/rotary_encoder_driver.cpp +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -void rotaryEncoderInit() -{ - configure_pins(PIO_PC19 | PIO_PC21, PIN_ENABLE | PIN_INPUT | PIN_PORTC | PIN_PULLUP); // 19 and 21 are rotary encoder - configure_pins(PIO_PB6, PIN_ENABLE | PIN_INPUT | PIN_PORTB | PIN_PULLUP); // rotary encoder switch - PIOC->PIO_IER = PIO_PC19 | PIO_PC21; - NVIC_EnableIRQ(PIOC_IRQn); -} - -void rotaryEncoderEnd() -{ - NVIC_DisableIRQ(PIOC_IRQn); - PIOC->PIO_IDR = PIO_PC19 | PIO_PC21; -} - -volatile uint32_t Rotary_position; -extern "C" void PIOC_IRQHandler() -{ - uint32_t dummy; - - dummy = PIOC->PIO_ISR; // Read and clear status register - (void) dummy; // Discard value - prevents compiler warning - - dummy = PIOC->PIO_PDSR; // Read Rotary encoder (PC19, PC21) - dummy >>= 19; - dummy &= 0x05; // pick out the three bits - if (dummy != (Rotary_position & 0x05)) { - if ((Rotary_position & 0x01) ^ ((dummy & 0x04) >> 2)) - rotencValue -= 1; - else - rotencValue += 1; - - Rotary_position &= ~0x45; - Rotary_position |= dummy; - } -} diff --git a/radio/src/targets/sky9x/rtc_driver.cpp b/radio/src/targets/sky9x/rtc_driver.cpp deleted file mode 100644 index 3e516ae8f..000000000 --- a/radio/src/targets/sky9x/rtc_driver.cpp +++ /dev/null @@ -1,288 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -#if defined(REVX) -// TODO change this, not the right place -#define TWI_NONE 0 -#define TWI_WRITE_VOL 2 -#define TWI_WAIT_COMP 7 -#define TWI_READ_RTC 8 -#define TWI_WRITE_RTC 9 -#define TWI_WAIT_RTCSTOP 10 -#define TWI_WRITE_MFP 11 -int8_t volumeRequired ; -int8_t Rtc_read_pending; -uint8_t Rtc_write_pending ; -int8_t Rtc_valid ; -uint8_t MFPsetting = 0 ; -uint8_t CALsetting = 0 ; -uint8_t *Twi_read_address ; -uint8_t TwiOperation ; -#define RTC_RX_BUXSIZE 10 -#define RTC_SIZE 7 -uint8_t Rtc_status[RTC_RX_BUXSIZE] ; -uint8_t *Rtc_write_ptr ; -uint32_t Rtc_write_count ; -uint8_t RtcConfig[8] ; // For initial config and writing to RTC -// 0x80, 0, 0, 0x08, 0, 0, 0, 0x80 - -uint32_t fromBCD(uint8_t bcd_value) -{ - return (((bcd_value & 0xF0) * 10) >> 4) + (bcd_value & 0x0F); -} - -uint32_t toBCD(uint32_t value) -{ - div_t qr = div(value, 10); - return (qr.quot << 4) + qr.rem; -} - -// This is called from an interrupt routine, or -// interrupts must be disabled while it is called -// from elsewhere. -void i2cCheck() -{ - if ( TWI0->TWI_IMR & TWI_IMR_TXCOMP ) { - return ; // Busy - } - - if ( volumeRequired >= 0 ) // Set volume to this value - { - TWI0->TWI_MMR = 0x002F0000 ; // Device 5E (>>1) and master is writing - TwiOperation = TWI_WRITE_VOL ; - TWI0->TWI_THR = volumeRequired ; // Send data - volumeRequired = -1 ; - TWI0->TWI_IER = TWI_IER_TXCOMP ; - TWI0->TWI_CR = TWI_CR_STOP ; // Stop Tx - } - else if ( Rtc_read_pending ) - { - Rtc_valid = 0 ; - Rtc_read_pending = 0 ; - TWI0->TWI_MMR = 0x006F1100 ; // Device 6F and master is reading, 1 byte addr - TWI0->TWI_IADR = 0 ; - TwiOperation = TWI_READ_RTC ; -#ifndef SIMU - TWI0->TWI_RPR = (uint32_t)&Rtc_status[0] ; -#endif - TWI0->TWI_RCR = RTC_SIZE - 1 ; - if ( TWI0->TWI_SR & TWI_SR_RXRDY ) - { - (void) TWI0->TWI_RHR ; - } - - TWI0->TWI_PTCR = TWI_PTCR_RXTEN ; // Start transfers - TWI0->TWI_CR = TWI_CR_START ; // Start Rx - TWI0->TWI_IER = TWI_IER_RXBUFF | TWI_IER_TXCOMP ; - } - else if ( Rtc_write_pending ) - { - if ( Rtc_write_pending & (2|4) ) - { - TWI0->TWI_MMR = 0x006F0100 ; // Device 6F and master is writing, 1 byte addr - TwiOperation = TWI_WRITE_MFP ; - if ( Rtc_write_pending & 2 ) - { - TWI0->TWI_IADR = 7 ; - TWI0->TWI_THR = MFPsetting ; // Send data - Rtc_write_pending &= ~2 ; - } - else - { - TWI0->TWI_IADR = 8 ; - TWI0->TWI_THR = CALsetting ; // Send data - Rtc_write_pending &= ~4 ; - } - TWI0->TWI_IER = TWI_IER_TXCOMP ; - TWI0->TWI_CR = TWI_CR_STOP ; // Stop Tx - } - else - { - Rtc_write_pending &= ~1 ; - TWI0->TWI_MMR = 0x006F0100 ; // Device 6F and master is writing, 1 byte addr - TWI0->TWI_IADR = 0 ; - TwiOperation = TWI_WRITE_RTC ; -#ifndef SIMU - TWI0->TWI_TPR = (uint32_t)Rtc_write_ptr+1 ; -#endif - TWI0->TWI_TCR = Rtc_write_count-1 ; - TWI0->TWI_THR = *Rtc_write_ptr ; // First byte - TWI0->TWI_PTCR = TWI_PTCR_TXTEN ; // Start data transfer - TWI0->TWI_IER = TWI_IER_TXBUFE | TWI_IER_TXCOMP ; - } - } -} - -void writeRTC(uint8_t *ptr) -{ - uint32_t year; - RtcConfig[0] = 0x80 | toBCD(*ptr++); - RtcConfig[1] = toBCD(*ptr++); - RtcConfig[2] = toBCD(*ptr++); - RtcConfig[3] = 0x08; - RtcConfig[4] = toBCD(*ptr++); - RtcConfig[5] = toBCD( *ptr++); - year = *ptr++; - year |= *ptr << 8; - RtcConfig[6] = toBCD(year - 2000); - RtcConfig[7] = MFPsetting; - Rtc_write_ptr = RtcConfig; - Rtc_write_count = 8; - __disable_irq(); - Rtc_write_pending |= 1; - i2cCheck(); - __enable_irq(); -} - -void readRTC() -{ - Rtc_read_pending = 1 ; - __disable_irq() ; - i2cCheck() ; - __enable_irq() ; -} - -// TODO should be inside an i2c_driver.cpp -#ifndef SIMU -extern "C" void TWI0_IRQHandler() -{ - uint32_t status ; - status = TWI0->TWI_SR ; // Read only once, some bits cleared on read - - if ( TwiOperation == TWI_READ_RTC ) - { - if ( status & TWI_SR_RXBUFF ) - { - TWI0->TWI_IDR = TWI_IDR_RXBUFF ; - TwiOperation = TWI_WAIT_RTCSTOP ; - TWI0->TWI_CR = TWI_CR_STOP ; // Stop Rx - TWI0->TWI_RCR = 1 ; // Last byte - return ; - } - else - { - // must be TXCOMP, prob. NAK in data - if ( TWI0->TWI_RCR > 0 ) - { - Rtc_valid = -1 ; - TWI0->TWI_CR = TWI_CR_STOP ; // Stop Rx - } - } - } - - if ( TwiOperation == TWI_WAIT_RTCSTOP ) - { - Rtc_valid = 1 ; - // Set the date and time - struct gtm utm; - - utm.tm_sec = fromBCD( Rtc_status[0] & 0x7F ) ; - utm.tm_min = fromBCD( Rtc_status[1] & 0x7F ) ; - utm.tm_hour = fromBCD( Rtc_status[2] & 0x3F ) ; - utm.tm_mday = fromBCD( Rtc_status[4] & 0x3F ) ; - utm.tm_mon = fromBCD( Rtc_status[5] & 0x1F ) - 1; - utm.tm_year = fromBCD( Rtc_status[6] ) + 100 ; - g_rtcTime = gmktime(&utm); - - TWI0->TWI_PTCR = TWI_PTCR_RXTDIS ; // Stop transfers - if ( status & TWI_SR_RXRDY ) - { - (void) TWI0->TWI_RHR ; // Discard any rubbish data - } - } - - if ( status & TWI_SR_NACK ) - { - TWI0->TWI_CR = TWI_CR_STOP ; // Stop Tx - } - - TWI0->TWI_IDR = TWI_IDR_TXCOMP | TWI_IDR_TXBUFE | TWI_IDR_RXBUFF ; - TWI0->TWI_PTCR = TWI_PTCR_TXTDIS | TWI_PTCR_RXTDIS ; // Stop transfers - if ( ( status & TWI_SR_TXCOMP ) == 0 ) - { - TWI0->TWI_IER = TWI_IER_TXCOMP ; - TwiOperation = TWI_WAIT_COMP ; - return ; - } - - TwiOperation = TWI_NONE ; - i2cCheck() ; -} -#endif -#endif - -struct t_i2cTime -{ - uint8_t setCode ; - uint8_t Time[7] ; -} I2CTime ; - -void rtcSetTime(const struct gtm * t) -{ - g_ms100 = 0; // start of next second begins now - - I2CTime.setCode = 0x74 ; // Tiny SET TIME CODE command - I2CTime.Time[0] = t->tm_sec ; - I2CTime.Time[1] = t->tm_min ; - I2CTime.Time[2] = t->tm_hour ; - I2CTime.Time[3] = t->tm_mday ; - I2CTime.Time[4] = t->tm_mon+1 ; - I2CTime.Time[5] = (uint8_t) (t->tm_year+TM_YEAR_BASE); - I2CTime.Time[6] = (t->tm_year+TM_YEAR_BASE) >> 8; -#if defined(REVX) - writeRTC((uint8_t *)&I2CTime.Time[0]) ; -#elif defined(COPROCESSOR) - coprocWriteData((uint8_t *) &I2CTime, 8); -#endif -} - -void rtcInit() -{ -#if defined(REVX) - readRTC(); -#elif defined(COPROCESSOR) - coprocReadData(); -#endif -} - -#if defined(REVX) -void writeMFP() -{ - __disable_irq(); - Rtc_write_pending |= 2; - i2cCheck(); - __enable_irq(); -} - -void setMFP() -{ - MFPsetting = 0x80; - writeMFP(); -} - -void clearMFP() -{ - MFPsetting = 0; - writeMFP(); -} -#endif diff --git a/radio/src/targets/sky9x/rtc_ds3231_driver.cpp b/radio/src/targets/sky9x/rtc_ds3231_driver.cpp deleted file mode 100644 index 229da8d05..000000000 --- a/radio/src/targets/sky9x/rtc_ds3231_driver.cpp +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" -#include "i2c_driver.h" - -#define DS3231_I2C_CHIPID 0x68 - -void readRtc() -{ - uint8_t buffer[7]; - uint8_t address[]= {0}; - gtm utm; - int res = i2cReadBuffer(DS3231_I2C_CHIPID, address, 1, buffer, 7); - if (res != 0) - return; - - // Set the date and time - utm.tm_sec = fromBCD(buffer[0] & 0x7F); - utm.tm_min = fromBCD(buffer[1] & 0x7F); - utm.tm_hour = fromBCD(buffer[2] & 0x3F); - utm.tm_mday = fromBCD(buffer[4] & 0x3F); - utm.tm_mon = fromBCD(buffer[5] & 0x1F) - 1; - utm.tm_year = fromBCD(buffer[6]) + 100; - g_rtcTime = gmktime(&utm); -} - -void writeRtc(const gtm* ptr) -{ - g_ms100 = 0; // start of next second begins now - uint8_t buffer[7]; - uint8_t address[]= {0}; - - buffer[0] = toBCD(ptr->tm_sec); - buffer[1] = toBCD(ptr->tm_min); - buffer[2] = toBCD(ptr->tm_hour); - buffer[3] = toBCD(ptr->tm_wday); - buffer[4] = toBCD(ptr->tm_mday); - buffer[5] = toBCD(ptr->tm_mon + 1); - uint8_t offset = ptr->tm_year >= 100 ? 100 : 0; - buffer[6] = toBCD(ptr->tm_year - offset); - i2cWriteBuffer(DS3231_I2C_CHIPID, address, 1, buffer, 7); -} - -void rtcSetTime(const struct gtm * t) -{ - writeRtc(t); -} - -void rtcInit() -{ - readRtc(); -} diff --git a/radio/src/targets/sky9x/sam3s4c_flash.ld b/radio/src/targets/sky9x/sam3s4c_flash.ld deleted file mode 100644 index c6ad73882..000000000 --- a/radio/src/targets/sky9x/sam3s4c_flash.ld +++ /dev/null @@ -1,162 +0,0 @@ -/**************************************************************************** -* Copyright (c) 2011 by Michael Fischer. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* 1. Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* 3. Neither the name of the author nor the names of its contributors may -* be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL -* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -* SUCH DAMAGE. -* -***************************************************************************** -* History: -* -* 22.05.2011 mifi First Version -****************************************************************************/ - - -/* - * In this linker script there is no heap available. - * The stack start at the end of the ram segment. - */ - - -/* - * Take a look in the "The GNU linker" manual, here you get - * the following information about the "MEMORY": - * - * "The MEMORY command describes the location and size of - * blocks of memory in the target." - */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00400000, LENGTH = 256K - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 48K -} - - -/* - * And the "SECTION" is used for: - * - * "The SECTIONS command tells the linker how to map input - * sections into output sections, and how to place the output - * sections in memory. - */ -SECTIONS -{ - - /* - * The ".text" section is used for the code, and - * read only (.rodata) data. Even the vectors (.vectors) - * MUST be saved at the start of this section. - */ - .text : - { - FILL(0xFFFF) - - CREATE_OBJECT_SYMBOLS - - KEEP(*(.bootloader)) /* Bootloader code */ - - . = 0x8000; /* Set the start of the main program */ - _stext = .; /* Provide the name for the start of this section */ - - KEEP(*(.vectors)) - - *(.text) - *(.text.*) - - . = ALIGN(4); /* Align the start of the rodata part */ - *(.rodata) - *(.rodata.*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); /* Align the end of the section */ - } > FLASH = 0 - _etext = .; /* Provide the name for the end of this section */ - - .ARM.extab : { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > FLASH - - _sidata = .; - - /* - * The ".data" section is used for initialized data - * and for functions (.fastrun) which should be copied - * from flash to ram. This functions will later be - * executed from ram instead of flash. - */ - .data : AT (_sidata) - { - . = ALIGN(4); /* Align the start of the section */ - _sdata = .; /* Provide the name for the start of this section */ - - *(.data) - *(.data.*) - - . = ALIGN(4); /* Align the start of the fastrun part */ - *(.fastrun) - *(.fastrun.*) - - . = ALIGN(4); /* Align the end of the section */ - } > RAM - _edata = .; /* Provide the name for the end of this section */ - - /* - * The ".bss" section is used for uninitialized data. - * This section will be cleared by the startup code. - */ - .bss : - { - . = ALIGN(4); /* Align the start of the section */ - _sbss = .; /* Provide the name for the start of this section */ - - *(.bss) - *(.bss.*) - - . = ALIGN(4); /* Align the end of the section */ - } > RAM - _ebss = .; /* Provide the name for the end of this section */ - - . = ALIGN(4); /* Align the end of the section */ - __end = .; - _end = .; - - /* - * The ".stack" section is our stack. - * Here this section starts at the end of the ram segment. - */ - _estack = ORIGIN(RAM) + LENGTH(RAM); - -} - -/*** EOF **/ - diff --git a/radio/src/targets/sky9x/sam3s8c_flash.ld b/radio/src/targets/sky9x/sam3s8c_flash.ld deleted file mode 100644 index 5dc75f285..000000000 --- a/radio/src/targets/sky9x/sam3s8c_flash.ld +++ /dev/null @@ -1,162 +0,0 @@ -/**************************************************************************** -* Copyright (c) 2011 by Michael Fischer. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* 1. Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* 3. Neither the name of the author nor the names of its contributors may -* be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL -* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -* SUCH DAMAGE. -* -***************************************************************************** -* History: -* -* 22.05.2011 mifi First Version -****************************************************************************/ - - -/* - * In this linker script there is no heap available. - * The stack start at the end of the ram segment. - */ - - -/* - * Take a look in the "The GNU linker" manual, here you get - * the following information about the "MEMORY": - * - * "The MEMORY command describes the location and size of - * blocks of memory in the target." - */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00400000, LENGTH = 512K - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - - -/* - * And the "SECTION" is used for: - * - * "The SECTIONS command tells the linker how to map input - * sections into output sections, and how to place the output - * sections in memory. - */ -SECTIONS -{ - - /* - * The ".text" section is used for the code, and - * read only (.rodata) data. Even the vectors (.vectors) - * MUST be saved at the start of this section. - */ - .text : - { - FILL(0xFFFF) - - CREATE_OBJECT_SYMBOLS - - KEEP(*(.bootloader)) /* Bootloader code */ - - . = 0x8000; /* Set the start of the main program */ - _stext = .; /* Provide the name for the start of this section */ - - KEEP(*(.vectors)) - - *(.text) - *(.text.*) - - . = ALIGN(4); /* Align the start of the rodata part */ - *(.rodata) - *(.rodata.*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); /* Align the end of the section */ - } > FLASH = 0 - _etext = .; /* Provide the name for the end of this section */ - - .ARM.extab : { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > FLASH - - _sidata = .; - - /* - * The ".data" section is used for initialized data - * and for functions (.fastrun) which should be copied - * from flash to ram. This functions will later be - * executed from ram instead of flash. - */ - .data : AT (_sidata) - { - . = ALIGN(4); /* Align the start of the section */ - _sdata = .; /* Provide the name for the start of this section */ - - *(.data) - *(.data.*) - - . = ALIGN(4); /* Align the start of the fastrun part */ - *(.fastrun) - *(.fastrun.*) - - . = ALIGN(4); /* Align the end of the section */ - } > RAM - _edata = .; /* Provide the name for the end of this section */ - - /* - * The ".bss" section is used for uninitialized data. - * This section will be cleared by the startup code. - */ - .bss : - { - . = ALIGN(4); /* Align the start of the section */ - _sbss = .; /* Provide the name for the start of this section */ - - *(.bss) - *(.bss.*) - - . = ALIGN(4); /* Align the end of the section */ - } > RAM - _ebss = .; /* Provide the name for the end of this section */ - - . = ALIGN(4); /* Align the end of the section */ - __end = .; - _end = .; - - /* - * The ".stack" section is our stack. - * Here this section starts at the end of the ram segment. - */ - _estack = ORIGIN(RAM) + LENGTH(RAM); - -} - -/*** EOF **/ - diff --git a/radio/src/targets/sky9x/sdcard_driver.cpp b/radio/src/targets/sky9x/sdcard_driver.cpp deleted file mode 100644 index aef98b7a5..000000000 --- a/radio/src/targets/sky9x/sdcard_driver.cpp +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -#define MCI_INITIAL_SPEED 400000 - -void init_SDcard() -{ -#ifndef SIMU - configure_pins( 0xFC000000, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_C | PIN_PORTA | PIN_NO_PULLUP ) ; - configure_pins( PIO_PB7, PIN_INPUT | PIN_PORTB | PIN_NO_PULLUP | PIN_NO_PULLDOWN ) ; - - unsigned short clkDiv; - Hsmci *pMciHw = HSMCI ; - - /* Enable the MCI peripheral */ - PMC->PMC_PCER0 |= 1 << ID_HSMCI ; // Enable peripheral clock to HSMCI - pMciHw->HSMCI_CR = HSMCI_CR_SWRST; /* Reset the MCI */ - pMciHw->HSMCI_CR = HSMCI_CR_MCIDIS | HSMCI_CR_PWSDIS; /* Disable the MCI */ - pMciHw->HSMCI_IDR = 0xFFFFFFFF; /* Disable all the interrupts */ - pMciHw->HSMCI_DTOR = HSMCI_DTOR_DTOCYC_Msk | HSMCI_DTOR_DTOMUL_Msk ; /* Set the Data Timeout Register */ - pMciHw->HSMCI_CSTOR = HSMCI_CSTOR_CSTOCYC_Msk | HSMCI_CSTOR_CSTOMUL_Msk ; /* CSTOR ? */ - /* Set the Mode Register: 400KHz for MCK = 48MHz (CLKDIV = 58) */ - clkDiv = 45; // (Master_frequency / (MCI_INITIAL_SPEED * 2)) - 1; - pMciHw->HSMCI_MR = clkDiv | (7 << 8) ; - - /* Set the SDCard Register 1-bit, slot A */ - pMciHw->HSMCI_SDCR = HSMCI_SDCR_SDCSEL_SLOTA | HSMCI_SDCR_SDCBUS_1 ; - /* Enable the MCI and the Power Saving */ - pMciHw->HSMCI_CR = HSMCI_CR_MCIEN/* | HSMCI_CR_PWSEN */; - /* Configure MCI */ - pMciHw->HSMCI_CFG = HSMCI_CFG_FIFOMODE | HSMCI_CFG_FERRCTRL; -#endif -} diff --git a/radio/src/targets/sky9x/telemetry_driver.cpp b/radio/src/targets/sky9x/telemetry_driver.cpp deleted file mode 100644 index 558965914..000000000 --- a/radio/src/targets/sky9x/telemetry_driver.cpp +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -#define RX_UART_BUFFER_SIZE 128 - -struct t_rxUartBuffer -{ - uint8_t fifo[RX_UART_BUFFER_SIZE] ; - uint8_t *outPtr ; -}; - -struct t_rxUartBuffer TelemetryInBuffer ; -uint16_t DsmRxTimeout; - -// USART0 configuration -// Work in Progress, UNTESTED -// Uses PA5 and PA6 (RXD and TXD) -void UART2_Configure(uint32_t baudrate, uint32_t masterClock, int mode) -{ - Usart *pUsart = SECOND_USART; - - // Configure PIO - configure_pins( (PIO_PA5 | PIO_PA6), PIN_PERIPHERAL | PIN_INPUT | PIN_PER_A | PIN_PORTA | PIN_NO_PULLUP ) ; - - // Configure PMC - PMC->PMC_PCER0 = 1 << SECOND_ID; - - // Reset and disable receiver & transmitter */ - pUsart->US_CR = US_CR_RSTRX | US_CR_RSTTX | US_CR_RXDIS | US_CR_TXDIS; - - // Configure mode - if (mode & TELEMETRY_SERIAL_8E2) - pUsart->US_MR = 0x000020C0 ; - else - pUsart->US_MR = 0x000008C0 ; // NORMAL, No Parity, 8 bit - - // Configure baudrate - // Asynchronous, no oversampling - pUsart->US_BRGR = (masterClock / baudrate) / 16; - - // Disable PDC channel - pUsart->US_PTCR = US_PTCR_RXTDIS | US_PTCR_TXTDIS; - - // Enable receiver and transmitter - pUsart->US_CR = US_CR_RXEN | US_CR_TXEN; -} - -void UART2_timeout_enable() -{ - Usart *pUsart = SECOND_USART; - pUsart->US_CR = US_CR_STTTO ; - pUsart->US_RTOR = 115 ; // Bits @ 115200 ~= 1mS - pUsart->US_IER = US_IER_TIMEOUT ; - DsmRxTimeout = 0 ; - NVIC_EnableIRQ(USART0_IRQn); -} - -void UART2_timeout_disable() -{ - Usart *pUsart = SECOND_USART; - pUsart->US_RTOR = 0 ; - pUsart->US_IDR = US_IDR_TIMEOUT ; - NVIC_DisableIRQ(USART0_IRQn); -} - -extern "C" void USART0_IRQHandler() -{ - Usart *pUsart = SECOND_USART; - pUsart->US_CR = US_CR_STTTO ; // Clears timeout bit - DsmRxTimeout = 1; -} - -void startPdcUsartReceive() -{ - Usart *pUsart = SECOND_USART; - TelemetryInBuffer.outPtr = TelemetryInBuffer.fifo ; - pUsart->US_RPR = (uint32_t)TelemetryInBuffer.fifo ; - pUsart->US_RNPR = (uint32_t)TelemetryInBuffer.fifo ; - pUsart->US_RCR = RX_UART_BUFFER_SIZE ; - pUsart->US_RNCR = RX_UART_BUFFER_SIZE ; - pUsart->US_PTCR = US_PTCR_RXTEN ; -} - -void rxPdcUsart( void (*pChProcess)(uint8_t x) ) -{ - Usart *pUsart = SECOND_USART; - uint8_t *ptr ; - uint8_t *endPtr ; - - // Find out where the DMA has got to - endPtr = (uint8_t *)pUsart->US_RPR ; - // Check for DMA passed end of buffer - if ( endPtr > &TelemetryInBuffer.fifo[RX_UART_BUFFER_SIZE-1] ) - { - endPtr = TelemetryInBuffer.fifo ; - } - ptr = TelemetryInBuffer.outPtr ; - while ( ptr != endPtr ) - { - (*pChProcess)(*ptr++) ; - if ( ptr > &TelemetryInBuffer.fifo[RX_UART_BUFFER_SIZE-1] ) // last byte - { - ptr = TelemetryInBuffer.fifo ; - } - } - TelemetryInBuffer.outPtr = ptr ; - - if ( pUsart->US_RNCR == 0 ) - { - pUsart->US_RNPR = (uint32_t)TelemetryInBuffer.fifo ; - pUsart->US_RNCR = RX_UART_BUFFER_SIZE ; - } -} - -uint32_t txPdcUsart(const uint8_t * buffer, uint32_t size) -{ - Usart * pUsart = SECOND_USART; - - if (pUsart->US_TNCR == 0) { - pUsart->US_TNPR = (uint32_t)buffer ; - pUsart->US_TNCR = size ; - pUsart->US_PTCR = US_PTCR_TXTEN ; - return 1 ; - } - return 0 ; -} - -/* -uint32_t telemetryTransmitPending() -{ - Usart *pUsart = SECOND_USART; - uint32_t x ; - - __disable_irq() ; - pUsart->US_PTCR = US_PTCR_TXTDIS ; // Freeze DMA - x = pUsart->US_TNCR ; // Total - x += pUsart->US_TCR ; // Still to send - pUsart->US_PTCR = US_PTCR_TXTEN ; // DMA active again - __enable_irq() ; - - return x ; -} -*/ - -void telemetryPortSetDirectionOutput() -{ -} - -void telemetryPortSetDirectionInput() -{ -} - -void telemetryPortInit(uint32_t baudrate, uint8_t mode) -{ - UART2_Configure(baudrate, Master_frequency, mode); - startPdcUsartReceive(); -} - -void sportSendBuffer(const uint8_t * buffer, uint32_t size) -{ - telemetryTransmitBuffer(buffer, size); -} - -void telemetryTransmitBuffer(const uint8_t * buffer, uint32_t size) -{ - txPdcUsart(buffer, size); -} diff --git a/radio/src/targets/sky9x/trainer_driver.cpp b/radio/src/targets/sky9x/trainer_driver.cpp deleted file mode 100644 index c7019537a..000000000 --- a/radio/src/targets/sky9x/trainer_driver.cpp +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "opentx.h" - -// Start TIMER3 for input capture -inline void start_timer3() -{ - Tc *ptc ; - - // Enable peripheral clock TC0 = bit 23 thru TC5 = bit 28 - PMC->PMC_PCER0 |= 0x04000000L ; // Enable peripheral clock to TC3 - - ptc = TC1 ; // Tc block 1 (TC3-5) - ptc->TC_BCR = 0 ; // No sync - ptc->TC_BMR = 2 ; - ptc->TC_CHANNEL[0].TC_CMR = 0x00000000 ; // Capture mode - ptc->TC_CHANNEL[0].TC_CMR = 0x00090005 ; // 0000 0000 0000 1001 0000 0000 0000 0101, XC0, A rise, b fall - ptc->TC_CHANNEL[0].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) - - configure_pins( PIO_PC23, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_B | PIN_PORTC | PIN_PULLUP ) ; - - NVIC_SetPriority( TC3_IRQn, 14 ) ; // Low priority interrupt - NVIC_EnableIRQ(TC3_IRQn) ; - ptc->TC_CHANNEL[0].TC_IER = TC_IER0_LDRAS ; -} - -// Start Timer4 to provide 0.5uS clock for input capture -void start_timer4() -{ - Tc *ptc ; - uint32_t timer ; - - timer = Master_frequency / (2*2000000) ; // MCK/2 and 2MHz - - // Enable peripheral clock TC0 = bit 23 thru TC5 = bit 28 - PMC->PMC_PCER0 |= 0x08000000L ; // Enable peripheral clock to TC4 - - ptc = TC1 ; // Tc block 1 (TC3-5) - ptc->TC_BCR = 0 ; // No sync - ptc->TC_BMR = 0 ; - ptc->TC_CHANNEL[1].TC_CMR = 0x00008000 ; // Waveform mode - ptc->TC_CHANNEL[1].TC_RC = timer ; - ptc->TC_CHANNEL[1].TC_RA = timer >> 1 ; - ptc->TC_CHANNEL[1].TC_CMR = 0x0009C000 ; // 0000 0000 0000 1001 1100 0000 0100 0000 - // MCK/2, set @ RA, Clear @ RC waveform - ptc->TC_CHANNEL[1].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) -} - -// Timer3 used for PPM_IN pulse width capture. Counter running at 16MHz / 8 = 2MHz -// equating to one count every half millisecond. (2 counts = 1ms). Control channel -// count delta values thus can range from about 1600 to 4400 counts (800us to 2200us), -// corresponding to a PPM signal in the range 0.8ms to 2.2ms (1.5ms at center). -// (The timer is free-running and is thus not reset to zero at each capture interval.) -// Timer 4 generates the 2MHz clock to clock Timer 3 - -extern "C" void TC3_IRQHandler() //capture ppm in at 2MHz -{ - uint32_t status = TC1->TC_CHANNEL[0].TC_SR; - if (status & TC_SR0_LDRAS) { - uint16_t capture = TC1->TC_CHANNEL[0].TC_RA ; - captureTrainerPulses(capture); - } -} - -void init_trainer_capture() -{ - PIOC->PIO_PER = PIO_PC22; - start_timer4() ; - start_timer3() ; -} - -void stop_trainer_capture() -{ - PIOC->PIO_PDR = PIO_PC22; - TC1->TC_CHANNEL[0].TC_IDR = TC_IDR0_LDRAS ; - NVIC_DisableIRQ(TC3_IRQn) ; -} diff --git a/radio/src/targets/sky9x/usb/common/core/USBConfigurationDescriptor.c b/radio/src/targets/sky9x/usb/common/core/USBConfigurationDescriptor.c deleted file mode 100644 index e812682d1..000000000 --- a/radio/src/targets/sky9x/usb/common/core/USBConfigurationDescriptor.c +++ /dev/null @@ -1,162 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBConfigurationDescriptor implementation - - About: Purpose - Implementation of the USBConfigurationDescriptor class. -*/ - -//----------------------------------------------------------------------------- -// Headers -//----------------------------------------------------------------------------- - -#include "../../../usb/common/core/USBConfigurationDescriptor.h" - -//----------------------------------------------------------------------------- -// Exported functions -//----------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -/// Returns the total length of a configuration, i.e. including the -/// descriptors following it. -/// \param configuration Pointer to a USBConfigurationDescriptor instance. -/// \return Total length (in bytes) of the configuration. -//----------------------------------------------------------------------------- -unsigned int USBConfigurationDescriptor_GetTotalLength( - const USBConfigurationDescriptor *configuration) -{ - return configuration->wTotalLength; -} - -//----------------------------------------------------------------------------- -/// Returns the number of interfaces in a configuration. -/// \param configuration Pointer to a USBConfigurationDescriptor instance. -/// \return Number of interfaces in configuration. -//----------------------------------------------------------------------------- -unsigned char USBConfigurationDescriptor_GetNumInterfaces( - const USBConfigurationDescriptor *configuration) -{ - return configuration->bNumInterfaces; -} - -//----------------------------------------------------------------------------- -/// Indicates if the device is self-powered when in a given configuration. -/// \param configuration Pointer to a USBConfigurationDescriptor instance. -/// \return 1 if the device is self-powered when in the given configuration; -/// otherwise 0. -//----------------------------------------------------------------------------- -unsigned char USBConfigurationDescriptor_IsSelfPowered( - const USBConfigurationDescriptor *configuration) -{ - if ((configuration->bmAttributes & (1 << 6)) != 0) { - - return 1; - } - else { - - return 0; - } -} - -//----------------------------------------------------------------------------- -/// Parses the given Configuration descriptor (followed by relevant -/// interface, endpoint and class-specific descriptors) into three arrays. -/// *Each array must have its size equal or greater to the number of -/// descriptors it stores plus one*. A null-value is inserted after the last -/// descriptor of each type to indicate the array end. -/// -/// Note that if the pointer to an array is null (0), nothing is stored in -/// it. -/// \param configuration Pointer to the start of the whole Configuration -/// descriptor. -/// \param interfaces Pointer to the Interface descriptor array. -/// \param endpoints Pointer to the Endpoint descriptor array. -/// \param others Pointer to the class-specific descriptor array. -//----------------------------------------------------------------------------- -void USBConfigurationDescriptor_Parse( - const USBConfigurationDescriptor *configuration, - USBInterfaceDescriptor **interfaces, - USBEndpointDescriptor **endpoints, - USBGenericDescriptor **others) -{ - // Get size of configuration to parse - int size = USBConfigurationDescriptor_GetTotalLength(configuration); - size -= sizeof(USBConfigurationDescriptor); - - // Start parsing descriptors - USBGenericDescriptor *descriptor = (USBGenericDescriptor *) configuration; - while (size > 0) { - - // Get next descriptor - descriptor = USBGenericDescriptor_GetNextDescriptor(descriptor); - size -= USBGenericDescriptor_GetLength(descriptor); - - // Store descriptor in correponding array - if (USBGenericDescriptor_GetType(descriptor) - == USBGenericDescriptor_INTERFACE) { - - if (interfaces) { - - *interfaces = (USBInterfaceDescriptor *) descriptor; - interfaces++; - } - } - else if (USBGenericDescriptor_GetType(descriptor) - == USBGenericDescriptor_ENDPOINT) { - - if (endpoints) { - - *endpoints = (USBEndpointDescriptor *) descriptor; - endpoints++; - } - } - else if (others) { - - *others = descriptor; - others++; - } - } - - // Null-terminate arrays - if (interfaces) { - - *interfaces = 0; - } - if (endpoints) { - - *endpoints = 0; - } - if (others) { - - *others = 0; - } -} - diff --git a/radio/src/targets/sky9x/usb/common/core/USBConfigurationDescriptor.h b/radio/src/targets/sky9x/usb/common/core/USBConfigurationDescriptor.h deleted file mode 100644 index 445ff4b9a..000000000 --- a/radio/src/targets/sky9x/usb/common/core/USBConfigurationDescriptor.h +++ /dev/null @@ -1,150 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - !!!Purpose - - Definitions and methods for USB configuration descriptor structures - described by the USB specification. - - !!!Usage - - -# Declare USBConfigurationDescriptor instance as a part - of the configuration descriptors of a USB device. - -# To get useful information (field values) from the defined USB device - configuration descriptor, use - - USBConfigurationDescriptor_GetTotalLength - - USBConfigurationDescriptor_GetNumInterfaces - - USBConfigurationDescriptor_IsSelfPowered - -# To pase the defined USB device configuration descriptor, use - - USBConfigurationDescriptor_Parse -*/ - -#ifndef USBCONFIGURATIONDESCRIPTOR_H -#define USBCONFIGURATIONDESCRIPTOR_H - -//----------------------------------------------------------------------------- -// Headers -//----------------------------------------------------------------------------- - -#include "../../../usb/common/core/USBEndpointDescriptor.h" -#include "../../../usb/common/core/USBGenericDescriptor.h" -#include "../../../usb/common/core/USBInterfaceDescriptor.h" - -//----------------------------------------------------------------------------- -// Definitions -//----------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -/// \page "USB device Attributes" -/// -/// This page lists the codes of the usb attributes. -/// -/// !Attributes -/// - USBConfigurationDescriptor_BUSPOWERED_NORWAKEUP -/// - USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP -/// - USBConfigurationDescriptor_BUSPOWERED_RWAKEUP -/// - USBConfigurationDescriptor_SELFPOWERED_RWAKEUP -/// - USBConfigurationDescriptor_POWER - -/// Device is bus-powered and not support remote wake-up. -#define USBConfigurationDescriptor_BUSPOWERED_NORWAKEUP 0x80 -/// Device is self-powered and not support remote wake-up. -#define USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP 0xC0 -/// Device is bus-powered and supports remote wake-up. -#define USBConfigurationDescriptor_BUSPOWERED_RWAKEUP 0xA0 -/// Device is self-powered and supports remote wake-up. -#define USBConfigurationDescriptor_SELFPOWERED_RWAKEUP 0xE0 - -/// Calculates the value of the power consumption field given the value in mA. -/// \param power The power consumption value in mA -/// \return The value that should be set to the field in descriptor -#define USBConfigurationDescriptor_POWER(power) (power / 2) -//----------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -// Types -//----------------------------------------------------------------------------- - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//----------------------------------------------------------------------------- -/// USB standard configuration descriptor structure. -//----------------------------------------------------------------------------- -typedef struct { - - /// Size of the descriptor in bytes. - unsigned char bLength; - /// Descriptor type (USBDESC_CONFIGURATION of "USB Descriptor types"). - unsigned char bDescriptorType; - /// Length of all descriptors returned along with this configuration - /// descriptor. - unsigned short wTotalLength; - /// Number of interfaces in this configuration. - unsigned char bNumInterfaces; - /// Value for selecting this configuration. - unsigned char bConfigurationValue; - /// Index of the configuration string descriptor. - unsigned char iConfiguration; - /// Configuration characteristics. - unsigned char bmAttributes; - /// Maximum power consumption of the device when in this configuration. - unsigned char bMaxPower; - -} __attribute__ ((packed)) USBConfigurationDescriptor; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -//----------------------------------------------------------------------------- -// Exported functions -//----------------------------------------------------------------------------- - -extern unsigned int USBConfigurationDescriptor_GetTotalLength( - const USBConfigurationDescriptor *configuration); - -extern unsigned char USBConfigurationDescriptor_GetNumInterfaces( - const USBConfigurationDescriptor *configuration); - -extern unsigned char USBConfigurationDescriptor_IsSelfPowered( - const USBConfigurationDescriptor *configuration); - -extern void USBConfigurationDescriptor_Parse( - const USBConfigurationDescriptor *configuration, - USBInterfaceDescriptor **interfaces, - USBEndpointDescriptor **endpoints, - USBGenericDescriptor **others); - -#endif //#ifndef USBCONFIGURATIONDESCRIPTOR_H - diff --git a/radio/src/targets/sky9x/usb/common/core/USBDeviceDescriptor.h b/radio/src/targets/sky9x/usb/common/core/USBDeviceDescriptor.h deleted file mode 100644 index 8a8186ce7..000000000 --- a/radio/src/targets/sky9x/usb/common/core/USBDeviceDescriptor.h +++ /dev/null @@ -1,125 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - !!!Purpose - - Class for manipulating USB device descriptors. - - !!!Usage - - - Declare a USBDeviceDescriptor instance as the device descriptor of a - USB device. -*/ - -#ifndef USBDEVICEDESCRIPTOR_H -#define USBDEVICEDESCRIPTOR_H - -#include "board_lowlevel.h" -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB release numbers" -/// -/// This page lists the codes of USB release numbers. -/// -/// !Code -/// - USBDeviceDescriptor_USB2_00 - -/// The device supports USB 2.00. -#define USBDeviceDescriptor_USB2_00 0x0200 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// USB standard device descriptor structure. -//------------------------------------------------------------------------------ -typedef struct { - - /// Size of this descriptor in bytes. - unsigned char bLength; - /// Descriptor type (USBGenericDescriptor_DEVICE). - unsigned char bDescriptorType; - /// USB specification release number in BCD format. - unsigned short bcdUSB; - /// Device class code. - unsigned char bDeviceClass; - /// Device subclass code. - unsigned char bDeviceSubClass; - /// Device protocol code. - unsigned char bDeviceProtocol; - /// Maximum packet size of endpoint 0 (in bytes). - unsigned char bMaxPacketSize0; - /// Vendor ID. - unsigned short idVendor; - /// Product ID. - unsigned short idProduct; - /// Device release number in BCD format. - unsigned short bcdDevice; - /// Index of the manufacturer string descriptor. - unsigned char iManufacturer; - /// Index of the product string descriptor. - unsigned char iProduct; - /// Index of the serial number string descriptor. - unsigned char iSerialNumber; - /// Number of possible configurations for the device. - unsigned char bNumConfigurations; - -} __attribute__ ((packed)) USBDeviceDescriptor; // GCC - -#if defined(CHIP_USB_OTGHS) -typedef struct { - - /// Size of this descriptor in bytes. - unsigned char bLength; - /// Descriptor type (USBGenericDescriptor_OTG). - unsigned char bDescriptorType; - /// Attribute Fields D7�2: Reserved D1: HNP support D0: SRP support - unsigned char bmAttributes; - -} __attribute__ ((packed)) USBOtgDescriptor; // GCC -#endif - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -#endif //#ifndef USBDEVICEDESCRIPTOR_H - diff --git a/radio/src/targets/sky9x/usb/common/core/USBDeviceQualifierDescriptor.h b/radio/src/targets/sky9x/usb/common/core/USBDeviceQualifierDescriptor.h deleted file mode 100644 index 5632e18c5..000000000 --- a/radio/src/targets/sky9x/usb/common/core/USBDeviceQualifierDescriptor.h +++ /dev/null @@ -1,89 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Class for manipulating USB device qualifier descriptors. - - !!!Usage - - - Declare a USBDeviceQualifierDescriptor instance as the device qualifier - descriptor of a USB device. -*/ - -#ifndef USBDEVICEQUALIFIERDESCRIPTOR_H -#define USBDEVICEQUALIFIERDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// Alternate device descriptor indicating the capabilities of the device -/// in full-speed, if currently in high-speed; or in high-speed, if it is -/// currently in full-speed. Only relevant for devices supporting the -/// high-speed mode. -//------------------------------------------------------------------------------ -typedef struct { - - /// Size of the descriptor in bytes. - unsigned char bLength; - /// Descriptor type (USBDESC_DEVICE_QUALIFIER or "USB device types"). - unsigned char bDescriptorType; - /// USB specification release number (in BCD format). - unsigned short bcdUSB; - /// Device class code. - unsigned char bDeviceClass; - /// Device subclass code. - unsigned char bDeviceSubClass; - /// Device protocol code. - unsigned char bDeviceProtocol; - /// Maximum packet size of endpoint 0. - unsigned char bMaxPacketSize0; - /// Number of possible configurations for the device. - unsigned char bNumConfigurations; - /// Reserved. - unsigned char bReserved; - -} __attribute__ ((packed)) USBDeviceQualifierDescriptor; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -#endif //#ifndef USBDEVICEQUALIFIERDESCRIPTOR_H - diff --git a/radio/src/targets/sky9x/usb/common/core/USBEndpointDescriptor.c b/radio/src/targets/sky9x/usb/common/core/USBEndpointDescriptor.c deleted file mode 100644 index e20176d3c..000000000 --- a/radio/src/targets/sky9x/usb/common/core/USBEndpointDescriptor.c +++ /dev/null @@ -1,109 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBEndpointDescriptor implementation - - About: Purpose - Implementation of the USBEndpointDescriptor class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBEndpointDescriptor.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Returns the number of an endpoint given its descriptor. -/// \param endpoint Pointer to a USBEndpointDescriptor instance. -/// \return Endpoint number. -//------------------------------------------------------------------------------ -unsigned char USBEndpointDescriptor_GetNumber( - const USBEndpointDescriptor *endpoint) -{ - return endpoint->bEndpointAddress & 0xF; -} - -//------------------------------------------------------------------------------ -/// Returns the direction of an endpoint given its descriptor. -/// \param endpoint Pointer to a USBEndpointDescriptor instance. -/// \return Endpoint direction (see ). -//------------------------------------------------------------------------------ -unsigned char USBEndpointDescriptor_GetDirection( - const USBEndpointDescriptor *endpoint) -{ - if ((endpoint->bEndpointAddress & 0x80) != 0) { - - return USBEndpointDescriptor_IN; - } - else { - - return USBEndpointDescriptor_OUT; - } -} - -//------------------------------------------------------------------------------ -/// Returns the type of an endpoint given its descriptor. -/// \param endpoint Pointer to a USBEndpointDescriptor instance. -/// \return Endpoint type (see ). -//------------------------------------------------------------------------------ -unsigned char USBEndpointDescriptor_GetType( - const USBEndpointDescriptor *endpoint) -{ - return endpoint->bmAttributes & 0x3; -} - -//------------------------------------------------------------------------------ -/// Returns the maximum size of a packet (in bytes) on an endpoint given -/// its descriptor. -/// \param endpoint - Pointer to a USBEndpointDescriptor instance. -/// \return Maximum packet size of endpoint. -//------------------------------------------------------------------------------ -unsigned short USBEndpointDescriptor_GetMaxPacketSize( - const USBEndpointDescriptor *endpoint) -{ - return endpoint->wMaxPacketSize; -} - -//------------------------------------------------------------------------------ -/// Returns the polling interval on an endpoint given its descriptor. -/// \param endpoint - Pointer to a USBEndpointDescriptor instance. -/// \return Polling interval of endpoint. -//------------------------------------------------------------------------------ -unsigned char USBEndpointDescriptor_GetInterval( - const USBEndpointDescriptor *endpoint) -{ - return endpoint->bInterval; -} - diff --git a/radio/src/targets/sky9x/usb/common/core/USBEndpointDescriptor.h b/radio/src/targets/sky9x/usb/common/core/USBEndpointDescriptor.h deleted file mode 100644 index 8a691eec2..000000000 --- a/radio/src/targets/sky9x/usb/common/core/USBEndpointDescriptor.h +++ /dev/null @@ -1,224 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of a class for handling USB endpoint descriptors. - - !!!Usage - - -# Declare USBEndpointDescriptor instance as a part of the - configuration descriptors of a USB device. - -# To get useful information (field values) from the defined USB device - endpoint descriptor (to configure hardware for endpoints, etc), use - - USBEndpointDescriptor_GetNumber - - USBEndpointDescriptor_GetDirection - - USBEndpointDescriptor_GetType - - USBEndpointDescriptor_GetMaxPacketSize -*/ - -#ifndef USBENDPOINTDESCRIPTOR_H -#define USBENDPOINTDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Endpoint definitions" -/// -/// This page lists definitions and macro for endpoint descriptors. -/// -/// - USB Endpoint directions -/// - USBEndpointDescriptor_OUT -/// - USBEndpointDescriptor_IN -/// -/// - USB Endpoint types -/// - USBEndpointDescriptor_CONTROL -/// - USBEndpointDescriptor_ISOCHRONOUS -/// - USBEndpointDescriptor_BULK -/// - USBEndpointDescriptor_INTERRUPT -/// -/// - USB Endpoint maximun sizes -/// - USBEndpointDescriptor_MAXCTRLSIZE_FS -/// - USBEndpointDescriptor_MAXCTRLSIZE_HS -/// - USBEndpointDescriptor_MAXBULKSIZE_FS -/// - USBEndpointDescriptor_MAXBULKSIZE_HS -/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_FS -/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_HS -/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_FS -/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_HS -/// -/// - USB Endpoint address define -/// - USBEndpointDescriptor_ADDRESS -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Endpoint directions" -/// -/// This page lists definitions of USB endpoint directions. -/// -/// !Directions -/// - USBEndpointDescriptor_OUT -/// - USBEndpointDescriptor_IN - -/// Endpoint receives data from the host. -#define USBEndpointDescriptor_OUT 0 -/// Endpoint sends data to the host. -#define USBEndpointDescriptor_IN 1 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Endpoint types" -/// -/// This page lists definitions of USB endpoint types. -/// -/// !Types -/// - USBEndpointDescriptor_CONTROL -/// - USBEndpointDescriptor_ISOCHRONOUS -/// - USBEndpointDescriptor_BULK -/// - USBEndpointDescriptor_INTERRUPT - -/// Control endpoint type. -#define USBEndpointDescriptor_CONTROL 0 -/// Isochronous endpoint type. -#define USBEndpointDescriptor_ISOCHRONOUS 1 -/// Bulk endpoint type. -#define USBEndpointDescriptor_BULK 2 -/// Interrupt endpoint type. -#define USBEndpointDescriptor_INTERRUPT 3 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Endpoint maximun sizes" -/// -/// This page lists definitions of USB endpoint maximun sizes. -/// -/// !Sizes -/// - USBEndpointDescriptor_MAXCTRLSIZE_FS -/// - USBEndpointDescriptor_MAXCTRLSIZE_HS -/// - USBEndpointDescriptor_MAXBULKSIZE_FS -/// - USBEndpointDescriptor_MAXBULKSIZE_HS -/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_FS -/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_HS -/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_FS -/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_HS - -/// Maximum size for a full-speed control endpoint. -#define USBEndpointDescriptor_MAXCTRLSIZE_FS 64 -/// Maximum size for a high-speed control endpoint. -#define USBEndpointDescriptor_MAXCTRLSIZE_HS 64 -/// Maximum size for a full-speed bulk endpoint. -#define USBEndpointDescriptor_MAXBULKSIZE_FS 64 -/// Maximum size for a high-speed bulk endpoint. -#define USBEndpointDescriptor_MAXBULKSIZE_HS 512 -/// Maximum size for a full-speed interrupt endpoint. -#define USBEndpointDescriptor_MAXINTERRUPTSIZE_FS 64 -/// Maximum size for a high-speed interrupt endpoint. -#define USBEndpointDescriptor_MAXINTERRUPTSIZE_HS 1024 -/// Maximum size for a full-speed isochronous endpoint. -#define USBEndpointDescriptor_MAXISOCHRONOUSSIZE_FS 1023 -/// Maximum size for a high-speed isochronous endpoint. -#define USBEndpointDescriptor_MAXISOCHRONOUSSIZE_HS 1024 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Endpoint address define" -/// -/// This page lists macro for USB endpoint address definition. -/// -/// !Macro -/// - USBEndpointDescriptor_ADDRESS - -/// Calculates the address of an endpoint given its number and direction -/// \param direction USB endpoint direction definition -/// \param number USB endpoint number -/// \return The value used to set the endpoint descriptor based on input number -/// and direction -#define USBEndpointDescriptor_ADDRESS(direction, number) \ - (((direction & 0x01) << 7) | (number & 0xF)) -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// USB standard endpoint descriptor structure. -//------------------------------------------------------------------------------ -typedef struct { - - /// Size of the descriptor in bytes. - unsigned char bLength; - /// Descriptor type (). - unsigned char bDescriptorType; - /// Address and direction of the endpoint. - unsigned char bEndpointAddress; - /// Endpoint type and additional characteristics (for isochronous endpoints). - unsigned char bmAttributes; - /// Maximum packet size (in bytes) of the endpoint. - unsigned short wMaxPacketSize; - /// Polling rate of the endpoint. - unsigned char bInterval; - -} __attribute__ ((packed)) USBEndpointDescriptor; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBEndpointDescriptor_GetNumber( - const USBEndpointDescriptor *endpoint); - -extern unsigned char USBEndpointDescriptor_GetDirection( - const USBEndpointDescriptor *endpoint); - -extern unsigned char USBEndpointDescriptor_GetType( - const USBEndpointDescriptor *endpoint); - -extern unsigned short USBEndpointDescriptor_GetMaxPacketSize( - const USBEndpointDescriptor *endpoint); - -extern unsigned char USBEndpointDescriptor_GetInterval( - const USBEndpointDescriptor *endpoint); - -#endif //#ifndef USBENDPOINTDESCRIPTOR_H - diff --git a/radio/src/targets/sky9x/usb/common/core/USBFeatureRequest.c b/radio/src/targets/sky9x/usb/common/core/USBFeatureRequest.c deleted file mode 100644 index 55d6cba48..000000000 --- a/radio/src/targets/sky9x/usb/common/core/USBFeatureRequest.c +++ /dev/null @@ -1,70 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBFeatureRequest implementation - - About: Purpose - Implementation of the USBFeatureRequest class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBFeatureRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Returns the feature selector of a given CLEAR_FEATURE or SET_FEATURE -/// request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Feature selector. -//------------------------------------------------------------------------------ -unsigned char USBFeatureRequest_GetFeatureSelector( - const USBGenericRequest *request) -{ - return USBGenericRequest_GetValue(request); -} - -//------------------------------------------------------------------------------ -/// Indicates the test that the device must undertake following a -/// SET_FEATURE request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Test selector. -//------------------------------------------------------------------------------ -unsigned char USBFeatureRequest_GetTestSelector( - const USBGenericRequest *request) -{ - return (USBGenericRequest_GetIndex(request) >> 8) & 0xFF; -} - diff --git a/radio/src/targets/sky9x/usb/common/core/USBFeatureRequest.h b/radio/src/targets/sky9x/usb/common/core/USBFeatureRequest.h deleted file mode 100644 index 16fbbc318..000000000 --- a/radio/src/targets/sky9x/usb/common/core/USBFeatureRequest.h +++ /dev/null @@ -1,146 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of a class for manipulating CLEAR_FEATURE and SET_FEATURE - requests. - - !!!Usage - - - To get USB feature request information (field values) from the - USBGenericRequest instance, use - - USBFeatureRequest_GetFeatureSelector - - USBFeatureRequest_GetTestSelector -*/ - -#ifndef USBFEATUREREQUEST_H -#define USBFEATUREREQUEST_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBGenericRequest.h" - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Feature Request definitions" -/// -/// This page lists codes of USB Feature Request -/// -/// - USB Feature selectors -/// - USBFeatureRequest_ENDPOINTHALT -/// - USBFeatureRequest_DEVICEREMOTEWAKEUP -/// - USBFeatureRequest_TESTMODE -/// -/// - USB Test mode selectors -/// - USBFeatureRequest_TESTJ -/// - USBFeatureRequest_TESTK -/// - USBFeatureRequest_TESTSE0NAK -/// - USBFeatureRequest_TESTPACKET -/// - USBFeatureRequest_TESTFORCEENABLE -/// - USBFeatureRequest_TESTSENDZLP -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Feature selectors" -/// -/// This page lists codes of USB feature selectors. -/// -/// !Selectors -/// - USBFeatureRequest_ENDPOINTHALT -/// - USBFeatureRequest_DEVICEREMOTEWAKEUP -/// - USBFeatureRequest_TESTMODE - -/// Halt feature of an endpoint. -#define USBFeatureRequest_ENDPOINTHALT 0 -/// Remote wake-up feature of the device. -#define USBFeatureRequest_DEVICEREMOTEWAKEUP 1 -/// Test mode of the device. -#define USBFeatureRequest_TESTMODE 2 -/// OTG set feature -#define USBFeatureRequest_OTG 0x0B -//------------------------------------------------------------------------------ - -/// On The Go Feature Selectors -/// b_hnp_enable 3 -/// a_hnp_support 4 -/// a_alt_hnp_support 5 -#define USBFeatureRequest_OTG_B_HNP_ENABLE 3 -#define USBFeatureRequest_OTG_A_HNP_SUPPORT 4 -#define USBFeatureRequest_OTG_A_ALT_HNP_SUPPORT 5 - -//------------------------------------------------------------------------------ -/// \page "USB Test mode selectors" -/// -/// This page lists codes of USB high speed test mode selectors. -/// -/// !Selectors -/// - USBFeatureRequest_TESTJ -/// - USBFeatureRequest_TESTK -/// - USBFeatureRequest_TESTSE0NAK -/// - USBFeatureRequest_TESTPACKET -/// - USBFeatureRequest_TESTFORCEENABLE -/// - USBFeatureRequest_TESTSENDZLP - -/// Tests the high-output drive level on the D+ line. -#define USBFeatureRequest_TESTJ 1 -/// Tests the high-output drive level on the D- line. -#define USBFeatureRequest_TESTK 2 -/// Tests the output impedance, low-level output voltage and loading -/// characteristics. -#define USBFeatureRequest_TESTSE0NAK 3 -/// Tests rise and fall times, eye patterns and jitter. -#define USBFeatureRequest_TESTPACKET 4 -/// Tests the hub disconnect detection. -#define USBFeatureRequest_TESTFORCEENABLE 5 -/// Send a ZLP in Test Mode. -#define USBFeatureRequest_TESTSENDZLP 6 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBFeatureRequest_GetFeatureSelector( - const USBGenericRequest *request); - - -extern unsigned char USBFeatureRequest_GetTestSelector( - const USBGenericRequest *request); - -#endif //#ifndef USBFEATUREREQUEST_H - diff --git a/radio/src/targets/sky9x/usb/common/core/USBGenericDescriptor.c b/radio/src/targets/sky9x/usb/common/core/USBGenericDescriptor.c deleted file mode 100644 index acda2a413..000000000 --- a/radio/src/targets/sky9x/usb/common/core/USBGenericDescriptor.c +++ /dev/null @@ -1,80 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBGenericDescriptor implementation - - About: Purpose - Implementation of the USBGenericDescriptor class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBGenericDescriptor.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Returns the length of a descriptor. -/// \param descriptor Pointer to a USBGenericDescriptor instance. -/// \return Length of descriptor in bytes. -//------------------------------------------------------------------------------ -unsigned int USBGenericDescriptor_GetLength( - const USBGenericDescriptor *descriptor) -{ - return descriptor->bLength; -} - -//------------------------------------------------------------------------------ -/// Returns the type of a descriptor. -/// \param descriptor Pointer to a USBGenericDescriptor instance. -/// \return Type of descriptor. -//------------------------------------------------------------------------------ -unsigned char USBGenericDescriptor_GetType( - const USBGenericDescriptor *descriptor) -{ - return descriptor->bDescriptorType; -} - -//------------------------------------------------------------------------------ -/// Returns a pointer to the descriptor right after the given one, when -/// parsing a Configuration descriptor. -/// \param descriptor - Pointer to a USBGenericDescriptor instance. -/// \return Pointer to the next descriptor. -//------------------------------------------------------------------------------ -USBGenericDescriptor *USBGenericDescriptor_GetNextDescriptor( - const USBGenericDescriptor *descriptor) -{ - return (USBGenericDescriptor *) - (((char *) descriptor) + USBGenericDescriptor_GetLength(descriptor)); -} diff --git a/radio/src/targets/sky9x/usb/common/core/USBGenericDescriptor.h b/radio/src/targets/sky9x/usb/common/core/USBGenericDescriptor.h deleted file mode 100644 index 01318f431..000000000 --- a/radio/src/targets/sky9x/usb/common/core/USBGenericDescriptor.h +++ /dev/null @@ -1,133 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !!!Purpose -/// -/// Definition of a generic USB descriptor class. -/// -/// !!!Usage -/// -/// -# Declare or access USB descriptors by USBGenericDescriptor instance. -/// -# To get usful information (field values) from the USB descriptors, use -/// - USBGenericDescriptor_GetLength -/// - USBGenericDescriptor_GetType -/// -# To scan the descriptors, use -/// - USBGenericDescriptor_GetNextDescriptor -//------------------------------------------------------------------------------ - -#ifndef USBGENERICDESCRIPTOR_H -#define USBGENERICDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Descriptor types" -/// -/// This page lists the codes of the usb descriptor types -/// -/// !Types -/// - USBGenericDescriptor_DEVICE -/// - USBGenericDescriptor_CONFIGURATION -/// - USBGenericDescriptor_STRING -/// - USBGenericDescriptor_INTERFACE -/// - USBGenericDescriptor_ENDPOINT -/// - USBGenericDescriptor_DEVICEQUALIFIER -/// - USBGenericDescriptor_OTHERSPEEDCONFIGURATION -/// - USBGenericDescriptor_INTERFACEPOWER -/// - USBGenericDescriptor_OTG -/// - USBGenericDescriptor_DEBUG -/// - USBGenericDescriptor_INTERFACEASSOCIATION - -/// Device descriptor type. -#define USBGenericDescriptor_DEVICE 1 -/// Configuration descriptor type. -#define USBGenericDescriptor_CONFIGURATION 2 -/// String descriptor type. -#define USBGenericDescriptor_STRING 3 -/// Interface descriptor type. -#define USBGenericDescriptor_INTERFACE 4 -/// Endpoint descriptor type. -#define USBGenericDescriptor_ENDPOINT 5 -/// Device qualifier descriptor type. -#define USBGenericDescriptor_DEVICEQUALIFIER 6 -/// Other speed configuration descriptor type. -#define USBGenericDescriptor_OTHERSPEEDCONFIGURATION 7 -/// Interface power descriptor type. -#define USBGenericDescriptor_INTERFACEPOWER 8 -/// On-The-Go descriptor type. -#define USBGenericDescriptor_OTG 9 -/// Debug descriptor type. -#define USBGenericDescriptor_DEBUG 10 -/// Interface association descriptor type. -#define USBGenericDescriptor_INTERFACEASSOCIATION 11 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -/// Holds the few fields shared by all USB descriptors. -typedef struct { - - /// Length of the descriptor in bytes. - unsigned char bLength; - /// Descriptor type. - unsigned char bDescriptorType; - -} __attribute__ ((packed)) USBGenericDescriptor; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned int USBGenericDescriptor_GetLength( - const USBGenericDescriptor *descriptor); - -extern unsigned char USBGenericDescriptor_GetType( - const USBGenericDescriptor *descriptor); - -extern USBGenericDescriptor *USBGenericDescriptor_GetNextDescriptor( - const USBGenericDescriptor *descriptor); - -#endif //#ifndef USBGENERICDESCRIPTOR_H - diff --git a/radio/src/targets/sky9x/usb/common/core/USBGenericRequest.c b/radio/src/targets/sky9x/usb/common/core/USBGenericRequest.c deleted file mode 100644 index 9017a8ac3..000000000 --- a/radio/src/targets/sky9x/usb/common/core/USBGenericRequest.c +++ /dev/null @@ -1,138 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBGenericRequest implementation - - About: Purpose - Implementation of the USBGenericRequest class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBGenericRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -/// Returns the type of the given request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return "USB Request Types" -//------------------------------------------------------------------------------ -extern unsigned char USBGenericRequest_GetType(const USBGenericRequest *request) -{ - return ((request->bmRequestType >> 5) & 0x3); -} - -//------------------------------------------------------------------------------ -/// Returns the request code of the given request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Request code. -/// \sa "USB Request Codes" -//------------------------------------------------------------------------------ -unsigned char USBGenericRequest_GetRequest(const USBGenericRequest *request) -{ - return request->bRequest; -} - -//------------------------------------------------------------------------------ -/// Returns the wValue field of the given request. -/// \param request - Pointer to a USBGenericRequest instance. -/// \return Request value. -//------------------------------------------------------------------------------ -unsigned short USBGenericRequest_GetValue(const USBGenericRequest *request) -{ - return request->wValue; -} - -//------------------------------------------------------------------------------ -/// Returns the wIndex field of the given request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Request index; -//------------------------------------------------------------------------------ -unsigned short USBGenericRequest_GetIndex(const USBGenericRequest *request) -{ - return request->wIndex; -} - -//------------------------------------------------------------------------------ -/// Returns the expected length of the data phase following a request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Length of data phase. -//------------------------------------------------------------------------------ -unsigned short USBGenericRequest_GetLength(const USBGenericRequest *request) -{ - return request->wLength; -} - -//------------------------------------------------------------------------------ -/// Returns the endpoint number targetted by a given request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Endpoint number. -//------------------------------------------------------------------------------ -unsigned char USBGenericRequest_GetEndpointNumber( - const USBGenericRequest *request) -{ - return USBGenericRequest_GetIndex(request) & 0xF; -} - -//------------------------------------------------------------------------------ -/// Returns the intended recipient of a given request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Request recipient. -/// \sa "USB Request Recipients" -//------------------------------------------------------------------------------ -unsigned char USBGenericRequest_GetRecipient(const USBGenericRequest *request) -{ - // Recipient is in bits [0..4] of the bmRequestType field - return request->bmRequestType & 0xF; -} - -//------------------------------------------------------------------------------ -/// Returns the direction of the data transfer following the given request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Transfer direction. -/// \sa "USB Request Directions" -//------------------------------------------------------------------------------ -unsigned char USBGenericRequest_GetDirection(const USBGenericRequest *request) -{ - // Transfer direction is located in bit D7 of the bmRequestType field - if ((request->bmRequestType & 0x80) != 0) { - - return USBGenericRequest_IN; - } - else { - - return USBGenericRequest_OUT; - } -} - diff --git a/radio/src/targets/sky9x/usb/common/core/USBGenericRequest.h b/radio/src/targets/sky9x/usb/common/core/USBGenericRequest.h deleted file mode 100644 index 0e7895436..000000000 --- a/radio/src/targets/sky9x/usb/common/core/USBGenericRequest.h +++ /dev/null @@ -1,244 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of the USBGenericRequest class and its methods. - - !!!Usage - - -# Declare or access USB requests by USBGenericRequest instance. - -# To get usful information (field values) from the USB requests, use - - USBGenericRequest_GetType - - USBGenericRequest_GetRequest - - USBGenericRequest_GetValue - - USBGenericRequest_GetIndex - - USBGenericRequest_GetLength - - USBGenericRequest_GetEndpointNumber - - USBGenericRequest_GetRecipient - - USBGenericRequest_GetDirection -*/ - -#ifndef USBGENERICREQUEST_H -#define USBGENERICREQUEST_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Generic Request definitions" -/// -/// This page lists the codes of USB generic request. -/// -/// - USB Request codes -/// - USBGenericRequest_GETSTATUS -/// - USBGenericRequest_CLEARFEATURE -/// - USBGenericRequest_SETFEATURE -/// - USBGenericRequest_SETADDRESS -/// - USBGenericRequest_GETDESCRIPTOR -/// - USBGenericRequest_SETDESCRIPTOR -/// - USBGenericRequest_GETCONFIGURATION -/// - USBGenericRequest_SETCONFIGURATION -/// - USBGenericRequest_GETINTERFACE -/// - USBGenericRequest_SETINTERFACE -/// - USBGenericRequest_SYNCHFRAME -/// -/// - USB Request Recipients -/// - USBGenericRequest_DEVICE -/// - USBGenericRequest_INTERFACE -/// - USBGenericRequest_ENDPOINT -/// - USBGenericRequest_OTHER -/// -/// - USB Request Types -/// - USBGenericRequest_STANDARD -/// - USBGenericRequest_CLASS -/// - USBGenericRequest_VENDOR -/// -/// - USB Request Directions -/// - USBGenericRequest_IN -/// - USBGenericRequest_OUT -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Request codes" -/// -/// This page lists the USB generic request codes. -/// -/// !Codes -/// - USBGenericRequest_GETSTATUS -/// - USBGenericRequest_CLEARFEATURE -/// - USBGenericRequest_SETFEATURE -/// - USBGenericRequest_SETADDRESS -/// - USBGenericRequest_GETDESCRIPTOR -/// - USBGenericRequest_SETDESCRIPTOR -/// - USBGenericRequest_GETCONFIGURATION -/// - USBGenericRequest_SETCONFIGURATION -/// - USBGenericRequest_GETINTERFACE -/// - USBGenericRequest_SETINTERFACE -/// - USBGenericRequest_SYNCHFRAME - -/// GET_STATUS request code. -#define USBGenericRequest_GETSTATUS 0 -/// CLEAR_FEATURE request code. -#define USBGenericRequest_CLEARFEATURE 1 -/// SET_FEATURE request code. -#define USBGenericRequest_SETFEATURE 3 -/// SET_ADDRESS request code. -#define USBGenericRequest_SETADDRESS 5 -/// GET_DESCRIPTOR request code. -#define USBGenericRequest_GETDESCRIPTOR 6 -/// SET_DESCRIPTOR request code. -#define USBGenericRequest_SETDESCRIPTOR 7 -/// GET_CONFIGURATION request code. -#define USBGenericRequest_GETCONFIGURATION 8 -/// SET_CONFIGURATION request code. -#define USBGenericRequest_SETCONFIGURATION 9 -/// GET_INTERFACE request code. -#define USBGenericRequest_GETINTERFACE 10 -/// SET_INTERFACE request code. -#define USBGenericRequest_SETINTERFACE 11 -/// SYNCH_FRAME request code. -#define USBGenericRequest_SYNCHFRAME 12 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Request Recipients" -/// -/// This page lists codes of USB request recipients. -/// -/// !Recipients -/// - USBGenericRequest_DEVICE -/// - USBGenericRequest_INTERFACE -/// - USBGenericRequest_ENDPOINT -/// - USBGenericRequest_OTHER - -/// Recipient is the whole device. -#define USBGenericRequest_DEVICE 0 -/// Recipient is an interface. -#define USBGenericRequest_INTERFACE 1 -/// Recipient is an endpoint. -#define USBGenericRequest_ENDPOINT 2 -/// Recipient is another entity. -#define USBGenericRequest_OTHER 3 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Request Types" -/// -/// This page lists codes of USB request types. -/// -/// !Types -/// - USBGenericRequest_STANDARD -/// - USBGenericRequest_CLASS -/// - USBGenericRequest_VENDOR - -/// Request is standard. -#define USBGenericRequest_STANDARD 0 -/// Request is class-specific. -#define USBGenericRequest_CLASS 1 -/// Request is vendor-specific. -#define USBGenericRequest_VENDOR 2 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB Request Directions" -/// -/// This page lists codes of USB request directions. -/// -/// !Directions -/// - USBGenericRequest_IN -/// - USBGenericRequest_OUT - -/// Transfer occurs from device to the host. -#define USBGenericRequest_OUT 0 -/// Transfer occurs from the host to the device. -#define USBGenericRequest_IN 1 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Generic USB SETUP request sent over Control endpoints. -//------------------------------------------------------------------------------ -typedef struct { - - /// Type of request - /// \sa "USB Request Recipients" - /// \sa "USB Request Types" - /// \sa "USB Request Directions" - unsigned char bmRequestType:8; - /// Request code - /// \sa "USB Request Codes" - unsigned char bRequest:8; - /// Request-specific value parameter. - unsigned short wValue:16; - /// Request-specific index parameter. - unsigned short wIndex:16; - /// Expected length (in bytes) of the data phase. - unsigned short wLength:16; - -} USBGenericRequest; - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBGenericRequest_GetType( - const USBGenericRequest *request); - - -extern unsigned char USBGenericRequest_GetRequest( - const USBGenericRequest *request); - -extern unsigned short USBGenericRequest_GetValue( - const USBGenericRequest *request); - -extern unsigned short USBGenericRequest_GetIndex( - const USBGenericRequest *request); - -extern unsigned short USBGenericRequest_GetLength( - const USBGenericRequest *request); - -extern unsigned char USBGenericRequest_GetEndpointNumber( - const USBGenericRequest *request); - -extern unsigned char USBGenericRequest_GetRecipient( - const USBGenericRequest *request); - -extern unsigned char USBGenericRequest_GetDirection( - const USBGenericRequest *request); - -#endif //#ifndef USBGENERICREQUEST_H - diff --git a/radio/src/targets/sky9x/usb/common/core/USBGetDescriptorRequest.c b/radio/src/targets/sky9x/usb/common/core/USBGetDescriptorRequest.c deleted file mode 100644 index c5416dbee..000000000 --- a/radio/src/targets/sky9x/usb/common/core/USBGetDescriptorRequest.c +++ /dev/null @@ -1,72 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBGetDescriptorRequest implementation - - About: Purpose - Implementation of the USBGetDescriptorRequest class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBGetDescriptorRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Returns the type of the descriptor requested by the host given the -/// corresponding GET_DESCRIPTOR request. -/// \param request Pointer to a USBGenericDescriptor instance. -/// \return Type of the requested descriptor. -//------------------------------------------------------------------------------ -unsigned char USBGetDescriptorRequest_GetDescriptorType( - const USBGenericRequest *request) -{ - // Requested descriptor type is in the high-byte of the wValue field - return (USBGenericRequest_GetValue(request) >> 8) & 0xFF; -} - -//------------------------------------------------------------------------------ -/// Returns the index of the requested descriptor, given the corresponding -/// GET_DESCRIPTOR request. -/// \param request Pointer to a USBGenericDescriptor instance. -/// \return Index of the requested descriptor. -//------------------------------------------------------------------------------ -unsigned char USBGetDescriptorRequest_GetDescriptorIndex( - const USBGenericRequest *request) -{ - // Requested descriptor index if in the low byte of the wValue field - return USBGenericRequest_GetValue(request) & 0xFF; -} - diff --git a/radio/src/targets/sky9x/usb/common/core/USBGetDescriptorRequest.h b/radio/src/targets/sky9x/usb/common/core/USBGetDescriptorRequest.h deleted file mode 100644 index af5c4edc8..000000000 --- a/radio/src/targets/sky9x/usb/common/core/USBGetDescriptorRequest.h +++ /dev/null @@ -1,67 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of the USBGetDescriptorRequest class. - - !!!Usage - - - After a GET_DESCRIPTOR request has been received, retrive the useful - values with following functions: - - USBGetDescriptorRequest_GetDescriptorType: the descriptor type - - USBGetDescriptorRequest_GetDescriptorIndex: the index of the requested - descriptor - -*/ - -#ifndef USBGETDESCRIPTORREQUEST_H -#define USBGETDESCRIPTORREQUEST_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBGenericRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBGetDescriptorRequest_GetDescriptorType( - const USBGenericRequest *request); - -extern unsigned char USBGetDescriptorRequest_GetDescriptorIndex( - const USBGenericRequest *request); - -#endif //#ifndef USBGETDESCRIPTORREQUEST_H - diff --git a/radio/src/targets/sky9x/usb/common/core/USBInterfaceAssociationDescriptor.h b/radio/src/targets/sky9x/usb/common/core/USBInterfaceAssociationDescriptor.h deleted file mode 100644 index 7f3376d01..000000000 --- a/radio/src/targets/sky9x/usb/common/core/USBInterfaceAssociationDescriptor.h +++ /dev/null @@ -1,86 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \page USBInterfaceAssociateDescriptor - * !!!Purpose - * - * Class for manipulating USB IAD descriptors. - * - * !!!Usage - * - * -# Test - */ - -#ifndef USBDIADDESCRIPTOR_H -#define USBDIADDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -/* - Type: USBDeviceDescriptor - USB standard device descriptor structure. - - Variables: - bLength - Size of this descriptor in bytes. - bDescriptorType - Descriptor type (). - bFirstInterface - Interface number of the first interface that is - associated with this function. - bInterfaceCount - Number of contiguous interfaces that are - associated with this function. - bFunctionClass - Class code (assigned by USB-IF). - bFunctionSubClass - Subclass code (assigned by USB-IF). - bFunctionProtocol - Protocol code (assigned by USB-IF) - iFunction - Index of string descriptor describing this function. -*/ -typedef struct { - - unsigned char bLength; - unsigned char bDescriptorType; - unsigned char bFirstInterface; - unsigned char bInterfaceCount; - unsigned char bFunctionClass; - unsigned char bFunctionSubClass; - unsigned char bFunctionProtocol; - unsigned char iFunction; -} __attribute__ ((packed)) USBInterfaceAssociationDescriptor; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -#endif //#ifndef USBDIADDESCRIPTOR_H - diff --git a/radio/src/targets/sky9x/usb/common/core/USBInterfaceDescriptor.h b/radio/src/targets/sky9x/usb/common/core/USBInterfaceDescriptor.h deleted file mode 100644 index 0d897a865..000000000 --- a/radio/src/targets/sky9x/usb/common/core/USBInterfaceDescriptor.h +++ /dev/null @@ -1,87 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of a class for manipulating USB interface descriptors. - - !!!Usage - - - Declare USBInterfaceDescriptor instance as a part of the configuration - descriptors of a USB device. - -*/ - -#ifndef USBINTERFACEDESCRIPTOR_H -#define USBINTERFACEDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// USB standard interface descriptor structure. -//------------------------------------------------------------------------------ -typedef struct { - - /// Size of the descriptor in bytes. - unsigned char bLength; - /// Descriptor type (USBGenericDescriptor_INTERFACE). - unsigned char bDescriptorType; - /// Number of the interface in its configuration. - unsigned char bInterfaceNumber; - /// Value to select this alternate interface setting. - unsigned char bAlternateSetting; - /// Number of endpoints used by the inteface (excluding endpoint 0). - unsigned char bNumEndpoints; - /// Interface class code. - unsigned char bInterfaceClass; - /// Interface subclass code. - unsigned char bInterfaceSubClass; - /// Interface protocol code. - unsigned char bInterfaceProtocol; - /// Index of the interface string descriptor. - unsigned char iInterface; - -} __attribute__ ((packed)) USBInterfaceDescriptor; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -#endif //#ifndef USBINTERFACEDESCRIPTOR_H - diff --git a/radio/src/targets/sky9x/usb/common/core/USBInterfaceRequest.c b/radio/src/targets/sky9x/usb/common/core/USBInterfaceRequest.c deleted file mode 100644 index 280d8c54e..000000000 --- a/radio/src/targets/sky9x/usb/common/core/USBInterfaceRequest.c +++ /dev/null @@ -1,69 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBInterfaceRequest - - About: Purpose - Implementation of USBInterfaceRequest class methods. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBInterfaceRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Indicates which interface is targetted by a GET_INTERFACE or -/// SET_INTERFACE request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Interface number. -//------------------------------------------------------------------------------ -unsigned char USBInterfaceRequest_GetInterface(const USBGenericRequest *request) -{ - return (USBGenericRequest_GetIndex(request) & 0xFF); -} - -//------------------------------------------------------------------------------ -/// Indicates the new alternate setting that the interface targetted by a -/// SET_INTERFACE request should use. -/// \param request Pointer to a USBGenericRequest instance. -/// \return New active setting for the interface. -//------------------------------------------------------------------------------ -unsigned char USBInterfaceRequest_GetAlternateSetting( - const USBGenericRequest *request) -{ - return (USBGenericRequest_GetValue(request) & 0xFF); -} - diff --git a/radio/src/targets/sky9x/usb/common/core/USBInterfaceRequest.h b/radio/src/targets/sky9x/usb/common/core/USBInterfaceRequest.h deleted file mode 100644 index 8805a80ff..000000000 --- a/radio/src/targets/sky9x/usb/common/core/USBInterfaceRequest.h +++ /dev/null @@ -1,68 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definitions for manipulating SET_INTERFACE and GET_INTERFACE request. - - !!!Usage - - -# After a SET_INTERFACE request has been received, retrieve the - target interface using USBInterfaceRequest_GetInterface and its - new alternate setting with USBInterfaceRequest_GetAlternateSetting. - -# After a GET_INTERFACE request has been received, retrieve the target - interface using USBInterfaceRequest_GetInterface. - -*/ - -#ifndef USBINTERFACEREQUEST_H -#define USBINTERFACEREQUEST_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBGenericRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBInterfaceRequest_GetInterface( - const USBGenericRequest *request); - - -extern unsigned char USBInterfaceRequest_GetAlternateSetting( - const USBGenericRequest *request); - -#endif //#ifndef USBINTERFACEREQUEST_H - diff --git a/radio/src/targets/sky9x/usb/common/core/USBIrqHandler.c b/radio/src/targets/sky9x/usb/common/core/USBIrqHandler.c deleted file mode 100644 index 5a8a943ab..000000000 --- a/radio/src/targets/sky9x/usb/common/core/USBIrqHandler.c +++ /dev/null @@ -1,62 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBIrqHandler implementation - - About: Purpose - Implementation of the USB Interrupt Handler. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ -#include - -#include "radio/src/targets/sky9x/board_lowlevel.h" -#include "../../../usb/device/core/USBD.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -/// Call Arbitrer, device and host interrupt handler. -/// The IRQ functions are defined with weak and can be surcharged if needed. -//------------------------------------------------------------------------------ -void USB_IrqHandler( void ) -{ - // Most arbitrer interrupt - usb_general_interrupt(); - // Device interrupt - USBD_IrqHandler(); - // Host interrupt - usb_pipe_interrupt(); -} - - diff --git a/radio/src/targets/sky9x/usb/common/core/USBIrqHandler.h b/radio/src/targets/sky9x/usb/common/core/USBIrqHandler.h deleted file mode 100644 index 3e6771ddc..000000000 --- a/radio/src/targets/sky9x/usb/common/core/USBIrqHandler.h +++ /dev/null @@ -1,52 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Implementation of the USB Interrupt Handler. - - !!!Usage - - -# The IRQ functions are defined with weak and can be surcharged if needed. - -*/ - -#ifndef USBIRQHANDLER_H -#define USBIRQHANDLER_H - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -extern void USB_IrqHandler( void ); - -#endif //#ifndef USBIRQHANDLER_H - diff --git a/radio/src/targets/sky9x/usb/common/core/USBSetAddressRequest.c b/radio/src/targets/sky9x/usb/common/core/USBSetAddressRequest.c deleted file mode 100644 index 2e548abe6..000000000 --- a/radio/src/targets/sky9x/usb/common/core/USBSetAddressRequest.c +++ /dev/null @@ -1,56 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBSetAddressRequest implementation - - About: Purpose - Implementation of the USBSetAddressRequest class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBSetAddressRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -/// Returns the address that the device must take in response to a -/// SET_ADDRESS request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return New device address. -//------------------------------------------------------------------------------ -unsigned char USBSetAddressRequest_GetAddress(const USBGenericRequest *request) -{ - return USBGenericRequest_GetValue(request) & 0x7F; -} - diff --git a/radio/src/targets/sky9x/usb/common/core/USBSetAddressRequest.h b/radio/src/targets/sky9x/usb/common/core/USBSetAddressRequest.h deleted file mode 100644 index e3dab7ee1..000000000 --- a/radio/src/targets/sky9x/usb/common/core/USBSetAddressRequest.h +++ /dev/null @@ -1,60 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of a class for manipulating SET_ADDRESS USB requests. - - !!!Usage - - - After a SET_ADDRESS request has been received, retrive the new address - value with USBSetAddressRequest_GetAddress. -*/ - -#ifndef USBSETADDRESSREQUEST_H -#define USBSETADDRESSREQUEST_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBGenericRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBSetAddressRequest_GetAddress( - const USBGenericRequest *request); - -#endif //#ifndef USBSETADDRESSREQUEST_H - diff --git a/radio/src/targets/sky9x/usb/common/core/USBSetConfigurationRequest.c b/radio/src/targets/sky9x/usb/common/core/USBSetConfigurationRequest.c deleted file mode 100644 index 269d03cf1..000000000 --- a/radio/src/targets/sky9x/usb/common/core/USBSetConfigurationRequest.c +++ /dev/null @@ -1,58 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: USBSetConfigurationRequest implementation - - About: Purpose - Implementation of the USBSetConfigurationRequest class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBSetConfigurationRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Returns the number of the configuration that should be set in response -/// to the given SET_CONFIGURATION request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Number of the requested configuration. -//------------------------------------------------------------------------------ -unsigned char USBSetConfigurationRequest_GetConfiguration( - const USBGenericRequest *request) -{ - return USBGenericRequest_GetValue(request); -} - diff --git a/radio/src/targets/sky9x/usb/common/core/USBSetConfigurationRequest.h b/radio/src/targets/sky9x/usb/common/core/USBSetConfigurationRequest.h deleted file mode 100644 index d69f3ae65..000000000 --- a/radio/src/targets/sky9x/usb/common/core/USBSetConfigurationRequest.h +++ /dev/null @@ -1,61 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of a class for the Set Configuration request. - - !!!Usage - - - After a SET_CONFIGURATION request has been received, retrive the new - configuration value with USBSetConfigurationRequest_GetConfiguration. - -*/ - -#ifndef USBSETCONFIGURATIONREQUEST_H -#define USBSETCONFIGURATIONREQUEST_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBGenericRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char USBSetConfigurationRequest_GetConfiguration( - const USBGenericRequest *request); - -#endif //#ifndef USBSETCONFIGURATIONREQUEST_H - diff --git a/radio/src/targets/sky9x/usb/common/core/USBStringDescriptor.h b/radio/src/targets/sky9x/usb/common/core/USBStringDescriptor.h deleted file mode 100644 index e3da4b405..000000000 --- a/radio/src/targets/sky9x/usb/common/core/USBStringDescriptor.h +++ /dev/null @@ -1,74 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !!!Purpose -/// -/// Definition of a class for manipulating String descriptors. -//------------------------------------------------------------------------------ - -#ifndef USBSTRINGDESCRIPTOR_H -#define USBSTRINGDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB String Descriptor definitions" -/// -/// This page lists the codes and macros for USB string descriptor definition. -/// -/// !Language IDs -/// - USBStringDescriptor_ENGLISH_US -/// -/// !String Descriptor Length -/// - USBStringDescriptor_LENGTH -/// -/// !ASCII to UNICODE convertion -/// - USBStringDescriptor_UNICODE - -/// Language ID for US english. -#define USBStringDescriptor_ENGLISH_US 0x09, 0x04 - -/// Calculates the length of a string descriptor given the number of ascii -/// characters/language IDs in it. -/// \param length The ascii format string length. -/// \return The actual data length in bytes. -#define USBStringDescriptor_LENGTH(length) ((length) * 2 + 2) -/// Converts an ascii character to its unicode representation. -/// \param ascii The ASCII character to convert -/// \return A 2-byte-array for the UNICODE based on given ASCII -#define USBStringDescriptor_UNICODE(ascii) (ascii), 0 -//------------------------------------------------------------------------------ - -#endif //#ifndef USBSTRINGDESCRIPTOR_H - diff --git a/radio/src/targets/sky9x/usb/common/hid/HIDButton.h b/radio/src/targets/sky9x/usb/common/hid/HIDButton.h deleted file mode 100644 index 5003586b7..000000000 --- a/radio/src/targets/sky9x/usb/common/hid/HIDButton.h +++ /dev/null @@ -1,55 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: HIDButton - - About: Purpose - Definitions of constants and methods for the HID Button usage page. - - About: Usage - 1 - Use the constants declared in this file when instanciating a - Report descriptor instance. - 2 - When implementing the functionality of an HID Mouse, use the - key codes defined here to indicate keys that are being pressed and - released. -*/ - -#ifndef _HIDBUTTON_H -#define _HIDBUTTON_H - -//------------------------------------------------------------------------------ -// Constants -//------------------------------------------------------------------------------ - -/// Identifier for the HID button usage page -#define HIDButton_PAGEID 0x09 - - -#endif diff --git a/radio/src/targets/sky9x/usb/common/hid/HIDDescriptor.h b/radio/src/targets/sky9x/usb/common/hid/HIDDescriptor.h deleted file mode 100644 index 1a5df6b12..000000000 --- a/radio/src/targets/sky9x/usb/common/hid/HIDDescriptor.h +++ /dev/null @@ -1,93 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Methods and definitions for manipulating a HID descriptor. -*/ - -#ifndef HIDDESCRIPTOR_H -#define HIDDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "HID Release Numbers" -/// ... -/// -/// !Numbers -/// - HIDDescriptor_HID1_11 - -/// Identifies version 1.11 of the HID specification. -#define HIDDescriptor_HID1_11 0x0111 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// Identifies the length of type of subordinate descriptors of a HID -/// device. This particular type only supports one subordinate descriptor. -//------------------------------------------------------------------------------ -typedef struct { - - /// Size of descriptor in bytes. - unsigned char bLength; - /// Descriptor type (HIDGenericDescriptor_HID). - unsigned char bDescriptorType; - /// HID class specification release number in BCD format. - unsigned short bcdHID; - /// Country code of the device if it is localized. - unsigned char bCountryCode; - /// Number of subordinate descriptors. - unsigned char bNumDescriptors; - /// Type of the first subordinate descriptor. - unsigned char bDescriptorType0; - /// Size in bytes of the first subordinate descriptor. - unsigned short wDescriptorLength0; - -} __attribute__ ((packed)) HIDDescriptor; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -#endif //#ifndef HIDDESCRIPTOR_H - diff --git a/radio/src/targets/sky9x/usb/common/hid/HIDDeviceDescriptor.h b/radio/src/targets/sky9x/usb/common/hid/HIDDeviceDescriptor.h deleted file mode 100644 index 41c510481..000000000 --- a/radio/src/targets/sky9x/usb/common/hid/HIDDeviceDescriptor.h +++ /dev/null @@ -1,68 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definitions used for declaring the device descriptor of a HID device. - - !!!Usage - - Use this constants when defining an instance of USBDeviceDescriptor for - an HID device. -*/ - -#ifndef HIDDEVICEDESCRIPTOR_H -#define HIDDEVICEDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "HID Device Descriptor Codes" -/// This page lists HID device class, subclass and protocol codes. -/// -/// !Codes -/// - HIDDeviceDescriptor_CLASS -/// - HIDDeviceDescriptor_SUBCLASS -/// - HIDDeviceDescriptor_PROTOCOL - -/// Class code for a HID device. -#define HIDDeviceDescriptor_CLASS 0 -/// Subclass code for a HID device. -#define HIDDeviceDescriptor_SUBCLASS 0 -/// Protocol code for a HID device. -#define HIDDeviceDescriptor_PROTOCOL 0 -//------------------------------------------------------------------------------ - -#endif //#ifndef HIDDEVICEDESCRIPTOR_H - diff --git a/radio/src/targets/sky9x/usb/common/hid/HIDGenericDescriptor.h b/radio/src/targets/sky9x/usb/common/hid/HIDGenericDescriptor.h deleted file mode 100644 index 0848872f6..000000000 --- a/radio/src/targets/sky9x/usb/common/hid/HIDGenericDescriptor.h +++ /dev/null @@ -1,63 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definitions for using HID-specific descriptors. -*/ - -#ifndef HIDGENERICDESCRIPTOR_H -#define HIDGENERICDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "HID Descriptors Types" -/// ... -/// -/// !Types -/// - HIDGenericDescriptor_HID -/// - HIDGenericDescriptor_REPORT -/// - HIDGenericDescriptor_PHYSICAL - -/// HID descriptor type. -#define HIDGenericDescriptor_HID 0x21 -/// Report descriptor type. -#define HIDGenericDescriptor_REPORT 0x22 -/// Physical descriptor type. -#define HIDGenericDescriptor_PHYSICAL 0x23 -//------------------------------------------------------------------------------ - -#endif //#ifndef HIDGENERICDESCRIPTOR_H - diff --git a/radio/src/targets/sky9x/usb/common/hid/HIDGenericDesktop.h b/radio/src/targets/sky9x/usb/common/hid/HIDGenericDesktop.h deleted file mode 100644 index 7ca5b46f6..000000000 --- a/radio/src/targets/sky9x/usb/common/hid/HIDGenericDesktop.h +++ /dev/null @@ -1,109 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Constants for using the HID generic desktop usage page. - - !!!Usage - - Use these constants when declaring a Report descriptor which references - the generic desktop page. -*/ - -#ifndef HIDGENERICDESKTOP_H -#define HIDGENERICDESKTOP_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "HID GenericDesktop Page ID" -/// ... -/// -/// !ID -/// - HIDGenericDesktop_PAGEID - -/// ID for the HID generic desktop usage page. -#define HIDGenericDesktop_PAGEID 0x01 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "HID GenericDesktop Usages" -/// ... -/// -/// !Usages -/// - HIDGenericDesktop_POINTER -/// - HIDGenericDesktop_MOUSE -/// - HIDGenericDesktop_JOYSTICK -/// - HIDGenericDesktop_GAMEPAD -/// - HIDGenericDesktop_KEYBOARD -/// - HIDGenericDesktop_KEYPAD -/// - HIDGenericDesktop_MULTIAXIS -/// - HIDGenericDesktop_X -/// - HIDGenericDesktop_Y -/// - HIDGenericDesktop_Z - -/// Pointer usage ID. -#define HIDGenericDesktop_POINTER 0x01 -/// Mouse usage ID. -#define HIDGenericDesktop_MOUSE 0x02 -/// Joystick usage ID. -#define HIDGenericDesktop_JOYSTICK 0x04 -/// Gamepad usage ID. -#define HIDGenericDesktop_GAMEPAD 0x05 -/// Keyboard usage ID. -#define HIDGenericDesktop_KEYBOARD 0x06 -/// Keypad usage ID. -#define HIDGenericDesktop_KEYPAD 0x07 -/// Multi-axis controller usage ID. -#define HIDGenericDesktop_MULTIAXIS 0x08 - -/// Axis Usage X direction ID. -#define HIDGenericDesktop_X_AXIS 0x30 -/// Axis Usage Y direction ID. -#define HIDGenericDesktop_Y_AXIS 0x31 -/// Axis Usage Z direction ID. -#define HIDGenericDesktop_Z_AXIS 0x32 -/// Rotation Usage X direction ID. -#define HIDGenericDesktop_X_ROTATION 0x33 -/// Rotation Usage Y direction ID. -#define HIDGenericDesktop_Y_ROTATION 0x34 -/// Rotation Usage Z direction ID. -#define HIDGenericDesktop_Z_ROTATION 0x35 -/// Slider usage ID. -#define HIDGenericDesktop_SLIDER 0x36 -//------------------------------------------------------------------------------ - -#endif //#ifndef HIDGENERICDESKTOP_H - diff --git a/radio/src/targets/sky9x/usb/common/hid/HIDGenericRequest.h b/radio/src/targets/sky9x/usb/common/hid/HIDGenericRequest.h deleted file mode 100644 index ea3cfee83..000000000 --- a/radio/src/targets/sky9x/usb/common/hid/HIDGenericRequest.h +++ /dev/null @@ -1,75 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: HIDGenericRequest - - About: Purpose - Definition of constants for using HID-specific requests. - - About: Usage - When constructing or receiving an HID SETUP request, use the request - codes provided by this header file. -*/ - -#ifndef HIDGENERICREQUEST_H -#define HIDGENERICREQUEST_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "HID Request Codes" -/// ... -/// -/// !Codes -/// - HIDGenericRequest_GETREPORT -/// - HIDGenericRequest_GETIDLE -/// - HIDGenericRequest_GETPROTOCOL -/// - HIDGenericRequest_SETREPORT -/// - HIDGenericRequest_SETIDLE -/// - HIDGenericRequest_SETPROTOCOL - -/// GetReport request code. -#define HIDGenericRequest_GETREPORT 0x01 -/// GetIdle request code. -#define HIDGenericRequest_GETIDLE 0x02 -/// GetProtocol request code. -#define HIDGenericRequest_GETPROTOCOL 0x03 -/// SetReport request code. -#define HIDGenericRequest_SETREPORT 0x09 -/// SetIdle request code. -#define HIDGenericRequest_SETIDLE 0x0A -/// SetProtocol request code. -#define HIDGenericRequest_SETPROTOCOL 0x0B -//------------------------------------------------------------------------------ - -#endif //#ifndef HIDGENERICREQUEST_H - diff --git a/radio/src/targets/sky9x/usb/common/hid/HIDIdleRequest.c b/radio/src/targets/sky9x/usb/common/hid/HIDIdleRequest.c deleted file mode 100644 index 17fc4875f..000000000 --- a/radio/src/targets/sky9x/usb/common/hid/HIDIdleRequest.c +++ /dev/null @@ -1,56 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: HIDIdleRequest implementation - - About: Purpose - Implementation of the HIDIdleRequest methods. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "HIDIdleRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Retrieves the Idle rate (in milliseconds) indicated by a SET_IDLE -/// request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return New idle rate for the report. -//------------------------------------------------------------------------------ -unsigned char HIDIdleRequest_GetIdleRate(const USBGenericRequest *request) -{ - return ((USBGenericRequest_GetValue(request) >> 8) & 0xFF); -} diff --git a/radio/src/targets/sky9x/usb/common/hid/HIDIdleRequest.h b/radio/src/targets/sky9x/usb/common/hid/HIDIdleRequest.h deleted file mode 100644 index 7a16d7a6f..000000000 --- a/radio/src/targets/sky9x/usb/common/hid/HIDIdleRequest.h +++ /dev/null @@ -1,68 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Methods and constants for manipulating HID-specific GET_IDLE and SET_IDLE - requests. - - !!!Usage - - -# Retrieve the idle rate indicated by a GET_IDLE or SET_IDLE request - with HIDIdleRequest_GetIdleRate. -*/ - -#ifndef HIDIDLEREQUEST_H -#define HIDIDLEREQUEST_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -/// Infinite idle rate. -#define HIDIdleRequest_INFINITE 0 - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char HIDIdleRequest_GetIdleRate( - const USBGenericRequest *request); - -#endif //#ifndef HIDIDLEREQUEST_H - diff --git a/radio/src/targets/sky9x/usb/common/hid/HIDInterfaceDescriptor.h b/radio/src/targets/sky9x/usb/common/hid/HIDInterfaceDescriptor.h deleted file mode 100644 index 32e0dbcc1..000000000 --- a/radio/src/targets/sky9x/usb/common/hid/HIDInterfaceDescriptor.h +++ /dev/null @@ -1,77 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Constants used when declaring an HID interface. - - !!!Usage - - Use the constants defined here when declaring a USBInterfaceDescriptor - instance for a HID interface. -*/ - -#ifndef HIDINTERFACEDESCRIPTOR_H -#define HIDINTERFACEDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "HID Interface Descriptor Codes" -/// This page lists HID Interface class, subclass and protocol codes. -/// -/// !Codes -/// - HIDInterfaceDescriptor_CLASS -/// - HIDInterfaceDescriptor_SUBCLASS_NONE -/// - HIDInterfaceDescriptor_SUBCLASS_BOOT -/// - HIDInterfaceDescriptor_PROTOCOL_NONE -/// - HIDInterfaceDescriptor_PROTOCOL_KEYBOARD -/// - HIDInterfaceDescriptor_PROTOCOL_MOUSE - -/// HID interface class code. -#define HIDInterfaceDescriptor_CLASS 0x03 -/// Indicates the interface does not implement a particular subclass. -#define HIDInterfaceDescriptor_SUBCLASS_NONE 0x00 -/// Indicates the interface is compliant with the boot specification. -#define HIDInterfaceDescriptor_SUBCLASS_BOOT 0x01 -/// Indicates the interface does not implement a particular protocol. -#define HIDInterfaceDescriptor_PROTOCOL_NONE 0x00 -/// Indicates the interface supports the boot specification as a keyboard. -#define HIDInterfaceDescriptor_PROTOCOL_KEYBOARD 0x01 -/// Indicates the interface supports the boot specification as a mouse. -#define HIDInterfaceDescriptor_PROTOCOL_MOUSE 0x02 -//------------------------------------------------------------------------------ - -#endif //#ifndef HIDINTERFACEDESCRIPTOR_H - diff --git a/radio/src/targets/sky9x/usb/common/hid/HIDReport.h b/radio/src/targets/sky9x/usb/common/hid/HIDReport.h deleted file mode 100644 index d63a93023..000000000 --- a/radio/src/targets/sky9x/usb/common/hid/HIDReport.h +++ /dev/null @@ -1,231 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definitions used when declaring an HID report descriptor. - - !!!Usage - - Use the definitions provided here when declaring a report descriptor, - which shall be an unsigned char array. -*/ - -#ifndef HIDREPORT_H -#define HIDREPORT_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "HID Main Item Tags" -/// This page lists the Main Item Tags defined for HID %device. -/// ( HID Spec. 6.2.2 ) -/// -/// !Tags -/// - HIDReport_INPUT -/// - HIDReport_OUPUT -/// - HIDReport_FEATURE -/// - HIDReport_COLLECTION -/// - HIDReport_ENDCOLLECTION - -/// Input item. -#define HIDReport_INPUT 0x80 -/// Output item. -#define HIDReport_OUTPUT 0x90 -/// Feature item. -#define HIDReport_FEATURE 0xB0 -/// Collection item. -#define HIDReport_COLLECTION 0xA0 -/// End of collection item. -#define HIDReport_ENDCOLLECTION 0xC0 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "HID Items for Data Fields" -/// This page lists defintions for HID Input, Output and Feature items that -/// are used to create the data fields within a report. -/// ( HID Spec. 6.2.2.5 ) -/// -/// !Items -/// - HIDReport_CONSTANT -/// - HIDReport_VARIABLE -/// - HIDReport_RELATIVE -/// - HIDReport_WRAP -/// - HIDReport_NONLINEAR -/// - HIDReport_NOPREFERRED -/// - HIDReport_NULLSTATE -/// - HIDReport_VOLATILE -/// - HIDReport_BUFFEREDBYTES - -/// The report value is constant (vs. variable). -#define HIDReport_CONSTANT (1 << 0) -/// Data reported is a variable (vs. array). -#define HIDReport_VARIABLE (1 << 1) -/// Data is relative (vs. absolute). -#define HIDReport_RELATIVE (1 << 2) -/// Value rolls over when it reach a maximum/minimum. -#define HIDReport_WRAP (1 << 3) -/// Indicates that the data reported has been processed and is no longuer -/// linear with the original measurements. -#define HIDReport_NONLINEAR (1 << 4) -/// Device has no preferred state to which it automatically returns. -#define HIDReport_NOPREFERRED (1 << 5) -/// Device has a null state, in which it does not report meaningful -/// information. -#define HIDReport_NULLSTATE (1 << 6) -/// Indicates data can change without the host intervention. -#define HIDReport_VOLATILE (1 << 7) -/// Indicates the device produces a fixed-length stream of bytes. -#define HIDReport_BUFFEREDBYTES (1 << 8) -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "HID Collection Items" -/// This page lists definitions for HID Collection Items. -/// ( HID Spec. 6.2.2.6 ) -/// -/// !Items -/// - HIDReport_COLLECTION_PHYSICAL -/// - HIDReport_COLLECTION_APPLICATION -/// - HIDReport_COLLECTION_LOGICAL -/// - HIDReport_COLLECTION_REPORT -/// - HIDReport_COLLECTION_NAMEDARRAY -/// - HIDReport_COLLECTION_USAGESWITCH -/// - HIDReport_COLLECTION_USAGEMODIFIER - -/// Physical collection. -#define HIDReport_COLLECTION_PHYSICAL 0x00 -/// Application collection. -#define HIDReport_COLLECTION_APPLICATION 0x01 -/// Logical collection. -#define HIDReport_COLLECTION_LOGICAL 0x02 -/// Report collection. -#define HIDReport_COLLECTION_REPORT 0x03 -/// Named array collection. -#define HIDReport_COLLECTION_NAMEDARRAY 0x04 -/// Usage switch collection. -#define HIDReport_COLLECTION_USAGESWITCH 0x05 -/// Usage modifier collection -#define HIDReport_COLLECTION_USAGEMODIFIER 0x06 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "HID Global Items" -/// This page lists HID Global Items. -/// ( HID Spec. 6.2.2.7 ) -/// -/// !Items -/// - HIDReport_GLOBAL_USAGEPAGE -/// - HIDReport_GLOBAL_LOGICALMINIMUM -/// - HIDReport_GLOBAL_LOGICALMAXIMUM -/// - HIDReport_GLOBAL_PHYSICALMINIMUM -/// - HIDReport_GLOBAL_PHYSICALMAXIMUM -/// - HIDReport_GLOBAL_UNITEXPONENT -/// - HIDReport_GLOBAL_UNIT -/// - HIDReport_GLOBAL_REPORTSIZE -/// - HIDReport_GLOBAL_REPORTID -/// - HIDReport_GLOBAL_REPORTCOUNT -/// - HIDReport_GLOBAL_PUSH -/// - HIDReport_GLOBAL_POP - -/// Current usage page. -#define HIDReport_GLOBAL_USAGEPAGE 0x04 -/// Minimum value that a variable or array item will report. -#define HIDReport_GLOBAL_LOGICALMINIMUM 0x14 -/// Maximum value that a variable or array item will report. -#define HIDReport_GLOBAL_LOGICALMAXIMUM 0x24 -/// Minimum value for the physical extent of a variable item. -#define HIDReport_GLOBAL_PHYSICALMINIMUM 0x34 -/// Maximum value for the physical extent of a variable item. -#define HIDReport_GLOBAL_PHYSICALMAXIMUM 0x44 -/// Value of the unit exponent in base 10. -#define HIDReport_GLOBAL_UNITEXPONENT 0x54 -/// Unit values. -#define HIDReport_GLOBAL_UNIT 0x64 -/// Size of the report fields in bits. -#define HIDReport_GLOBAL_REPORTSIZE 0x74 -/// Specifies the report ID. -#define HIDReport_GLOBAL_REPORTID 0x84 -/// Number of data fields for an item. -#define HIDReport_GLOBAL_REPORTCOUNT 0x94 -/// Places a copy of the global item state table on the stack. -#define HIDReport_GLOBAL_PUSH 0xA4 -/// Replaces the item state table with the top structure from the stack. -#define HIDReport_GLOBAL_POP 0xB4 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "HID Local Items" -/// This page lists definitions for HID Local Items. -/// -/// !Items -/// - HIDReport_LOCAL_USAGE -/// - HIDReport_LOCAL_USAGEMINIMUM -/// - HIDReport_LOCAL_USAGEMAXIMUM -/// - HIDReport_LOCAL_DESIGNATORINDEX -/// - HIDReport_LOCAL_DESIGNATORMINIMUM -/// - HIDReport_LOCAL_DESIGNATORMAXIMUM -/// - HIDReport_LOCAL_STRINGINDEX -/// - HIDReport_LOCAL_STRINGMINIMUM -/// - HIDReport_LOCAL_STRINGMAXIMUM -/// - HIDReport_LOCAL_DELIMITER - -/// Suggested usage for an item or collection. -#define HIDReport_LOCAL_USAGE 0x08 -/// Defines the starting usage associated with an array or bitmap. -#define HIDReport_LOCAL_USAGEMINIMUM 0x18 -/// Defines the ending usage associated with an array or bitmap. -#define HIDReport_LOCAL_USAGEMAXIMUM 0x28 -/// Determines the body part used for a control. -#define HIDReport_LOCAL_DESIGNATORINDEX 0x38 -/// Defines the index of the starting designator associated with an array or -/// bitmap. -#define HIDReport_LOCAL_DESIGNATORMINIMUM 0x48 -/// Defines the index of the ending designator associated with an array or -/// bitmap. -#define HIDReport_LOCAL_DESIGNATORMAXIMUM 0x58 -/// String index for a string descriptor. -#define HIDReport_LOCAL_STRINGINDEX 0x78 -/// Specifies the first string index when assigning a group of sequential -/// strings to controls in an array or bitmap. -#define HIDReport_LOCAL_STRINGMINIMUM 0x88 -/// Specifies the last string index when assigning a group of sequential -/// strings to controls in an array or bitmap. -#define HIDReport_LOCAL_STRINGMAXIMUM 0x98 -/// Defines the beginning or end of a set of local items. -#define HIDReport_LOCAL_DELIMITER 0xA8 -//------------------------------------------------------------------------------ - -#endif //#ifndef HIDREPORT_H - diff --git a/radio/src/targets/sky9x/usb/common/hid/HIDReportRequest.c b/radio/src/targets/sky9x/usb/common/hid/HIDReportRequest.c deleted file mode 100644 index c707f6811..000000000 --- a/radio/src/targets/sky9x/usb/common/hid/HIDReportRequest.c +++ /dev/null @@ -1,68 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: HIDReportRequest implementation - - About: Purpose - Implementation of the HIDReportRequest methods. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "HIDReportRequest.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Indicates the type of report targetted by a SET_REPORT or GET_REPORT -/// request. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Requested report type (see "HID Report Types"). -//------------------------------------------------------------------------------ -unsigned char HIDReportRequest_GetReportType(const USBGenericRequest *request) -{ - return ((USBGenericRequest_GetValue(request) >> 8) & 0xFF); -} - -//------------------------------------------------------------------------------ -/// Indicates the ID of the report targetted by a SET_REPORT or GET_REPORT -/// request. This value should be 0 if report IDs are not used. -/// \param request Pointer to a USBGenericRequest instance. -/// \return Requested report ID. -//------------------------------------------------------------------------------ -unsigned char HIDReportRequest_GetReportId(const USBGenericRequest *request) -{ - return (USBGenericRequest_GetValue(request) & 0xFF); -} - diff --git a/radio/src/targets/sky9x/usb/common/hid/HIDReportRequest.h b/radio/src/targets/sky9x/usb/common/hid/HIDReportRequest.h deleted file mode 100644 index a879e61b7..000000000 --- a/radio/src/targets/sky9x/usb/common/hid/HIDReportRequest.h +++ /dev/null @@ -1,86 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of a class for manipulating HID-specific GET_REPORT and - SET_REPORT requests. - - !!!Usage - - -# Receive a GET_REPORT or SET_REPORT request from the host. - -# Retrieve the report type using HIDReportRequest_GetReportType. - -# Retrieve the report ID using HIDReportRequest_GetReportId. -*/ - -#ifndef HIDREPORTREQUEST_H -#define HIDREPORTREQUEST_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "HID Report Types" -/// This page lists the types for USB HID Reports. -/// -/// !Types -/// - HIDReportRequest_INPUT -/// - HIDReportRequest_OUTPUT -/// - HIDReportRequest_FEATURE - -/// Input report. -#define HIDReportRequest_INPUT 1 -/// Output report. -#define HIDReportRequest_OUTPUT 2 -/// Feature report. -#define HIDReportRequest_FEATURE 3 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char HIDReportRequest_GetReportType( - const USBGenericRequest *request); - -extern unsigned char HIDReportRequest_GetReportId( - const USBGenericRequest *request); - -#endif //#ifndef HIDREPORTREQUEST_H - diff --git a/radio/src/targets/sky9x/usb/common/massstorage/MSDeviceDescriptor.h b/radio/src/targets/sky9x/usb/common/massstorage/MSDeviceDescriptor.h deleted file mode 100644 index f85833ee0..000000000 --- a/radio/src/targets/sky9x/usb/common/massstorage/MSDeviceDescriptor.h +++ /dev/null @@ -1,73 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Declaration of constants for using Device Descriptors with a Mass Storage -/// driver. -/// -/// !Usage -/// -/// - For a USB device: -/// -# When declaring a USBDeviceDescriptor instance, use the Mass Storage -/// codes defined in this file (see "MS device codes"). -//------------------------------------------------------------------------------ - -#ifndef MSDEVICEDESCRIPTOR_H -#define MSDEVICEDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MS device codes" -/// This page lists the class, subclass & protocol codes used by a device with -/// a Mass Storage driver. -/// -/// !Codes -/// -/// - MSDeviceDescriptor_CLASS -/// - MSDeviceDescriptor_SUBCLASS -/// - MSDeviceDescriptor_PROTOCOL - -/// Class code for a Mass Storage device. -#define MSDeviceDescriptor_CLASS 0 - -/// Subclass code for a Mass Storage device. -#define MSDeviceDescriptor_SUBCLASS 0 - -/// Protocol code for a Mass Storage device. -#define MSDeviceDescriptor_PROTOCOL 0 -//------------------------------------------------------------------------------ - -#endif //#ifndef MSDEVICEDESCRIPTOR_H - diff --git a/radio/src/targets/sky9x/usb/common/massstorage/MSInterfaceDescriptor.h b/radio/src/targets/sky9x/usb/common/massstorage/MSInterfaceDescriptor.h deleted file mode 100644 index b5033e24e..000000000 --- a/radio/src/targets/sky9x/usb/common/massstorage/MSInterfaceDescriptor.h +++ /dev/null @@ -1,75 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Definition of several constants used when manipulating Mass Storage interface -/// descriptors. -/// -/// !Usage -/// -/// - For a USB device: -/// -# When declaring an interface descriptor for a Mass Storage device, use -/// the class, subclass and protocol codes defined here (see -/// "MS interface codes"). -//------------------------------------------------------------------------------ - -#ifndef MSINTERFACEDESCRIPTOR_H -#define MSINTERFACEDESCRIPTOR_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MS interface codes" -/// This page lists the available class, subclass & protocol codes for a Mass -/// Storage interface. -/// -/// !Codes -/// -/// - MSInterfaceDescriptor_CLASS -/// - MSInterfaceDescriptor_SCSI -/// - MSInterfaceDescriptor_BULKONLY - -/// Class code for a Mass Storage interface. -#define MSInterfaceDescriptor_CLASS 0x08 - -/// Subclass code for a Mass Storage interface using the SCSI protocol. -#define MSInterfaceDescriptor_SCSI 0x06 - -/// Protocol code for a Mass Storage interface using Bulk-Only Transport. -#define MSInterfaceDescriptor_BULKONLY 0x50 -//------------------------------------------------------------------------------ - - -#endif //#ifndef MSINTERFACEDESCRIPTOR_H - diff --git a/radio/src/targets/sky9x/usb/device/core/USBD.h b/radio/src/targets/sky9x/usb/device/core/USBD.h deleted file mode 100644 index 76ce7a028..000000000 --- a/radio/src/targets/sky9x/usb/device/core/USBD.h +++ /dev/null @@ -1,290 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !!!Purpose -/// -/// Collection of methods for using the USB device controller on AT91 -/// microcontrollers. -/// -/// !!!Usage -/// -/// Please refer to the corresponding application note. -/// - "AT91 USB device framework" -/// - "USBD API" . "USBD API Methods" -//------------------------------------------------------------------------------ - -#ifndef USBD_H -#define USBD_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -// #include -#include "../../../usb/common/core/USBEndpointDescriptor.h" -#include "../../../usb/common/core/USBGenericRequest.h" - -//------------------------------------------------------------------------------ -// Compile Options -//------------------------------------------------------------------------------ - -/// Compile option for HS or OTG, use DMA. Remove this define for not use DMA. -#if defined(CHIP_USB_OTGHS) || defined(CHIP_USB_UDPHS) -#define DMA -#endif - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB device API return values" -/// -/// This page lists the return values of the USB %device driver API -/// -/// !Return codes -/// - USBD_STATUS_SUCCESS -/// - USBD_STATUS_LOCKED -/// - USBD_STATUS_ABORTED -/// - USBD_STATUS_RESET - -/// Indicates the operation was successful. -#define USBD_STATUS_SUCCESS 0 -/// Endpoint/device is already busy. -#define USBD_STATUS_LOCKED 1 -/// Operation has been aborted. -#define USBD_STATUS_ABORTED 2 -/// Operation has been aborted because the device has been reset. -#define USBD_STATUS_RESET 3 -/// Part ot operation successfully done. -#define USBD_STATUS_PARTIAL_DONE 4 -/// Operation failed because parameter error -#define USBD_STATUS_INVALID_PARAMETER 5 -/// Operation failed because in unexpected state -#define USBD_STATUS_WRONG_STATE 6 -/// Operation failed because HW not supported -#define USBD_STATUS_HW_NOT_SUPPORTED 0xFE -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB device states" -/// -/// This page lists the %device states of the USB %device driver. -/// -/// !States -/// - USBD_STATE_SUSPENDED -/// - USBD_STATE_ATTACHED -/// - USBD_STATE_POWERED -/// - USBD_STATE_DEFAULT -/// - USBD_STATE_ADDRESS -/// - USBD_STATE_CONFIGURED - -/// The device is currently suspended. -#define USBD_STATE_SUSPENDED 0 -/// USB cable is plugged into the device. -#define USBD_STATE_ATTACHED 1 -/// Host is providing +5V through the USB cable. -#define USBD_STATE_POWERED 2 -/// Device has been reset. -#define USBD_STATE_DEFAULT 3 -/// The device has been given an address on the bus. -#define USBD_STATE_ADDRESS 4 -/// A valid configuration has been selected. -#define USBD_STATE_CONFIGURED 5 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "USB device LEDs" -/// -/// This page lists the LEDs used in the USB %device driver. -/// -/// !LEDs -/// - USBD_LEDPOWER -/// - USBD_LEDUSB -/// - USBD_LEDOTHER - -/// LED for indicating that the device is powered. -#define USBD_LEDPOWER 0 -/// LED for indicating USB activity. -#define USBD_LEDUSB 1 -/// LED for custom usage. -#define USBD_LEDOTHER 2 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Buffer struct used for multi-buffer-listed transfer. -/// The driver can process 255 bytes of buffers or buffer list window. -//------------------------------------------------------------------------------ -typedef struct _USBDTransferBuffer { - /// Pointer to frame buffer - unsigned char * pBuffer; - /// Size of the frame (up to 64K-1) - unsigned short size; - /// Bytes transferred - unsigned short transferred; - /// Bytes in FIFO - unsigned short buffered; - /// Bytes remaining - unsigned short remaining; -} USBDTransferBuffer; - -#ifdef __ICCARM__ // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// Struct used for USBD DMA Link List Transfer Descriptor, must be 16-bytes -/// aligned. -/// (For USB, DMA transfer is linked to EPs and FIFO address is EP defined) -//------------------------------------------------------------------------------ -typedef struct _USBDDmaDescriptor { - /// Pointer to Next Descriptor - void* pNxtDesc; - /// Pointer to data buffer address - void* pDataAddr; - /// DMA Control setting register value - unsigned int ctrlSettings:8, /// Control settings - reserved:8, /// Not used - bufferLength:16; /// Length of buffer - /// Loaded to DMA register, OK to modify - unsigned int used; -} __attribute__((aligned(16))) USBDDmaDescriptor; - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// Callback used by transfer functions (USBD_Read & USBD_Write) to notify -/// that a transaction is complete. -//------------------------------------------------------------------------------ -typedef void (*TransferCallback)(void *pArg, - unsigned char status, - unsigned int transferred, - unsigned int remaining); - -//------------------------------------------------------------------------------ -/// Callback used by MBL transfer functions (USBD_Read & USBD_Write) to notify -/// that a transaction is complete. -/// \param pArg Pointer to callback arguments. -/// \param status USBD status. -/// \param nbFreed Number of buffers that is freed since last callback. -//------------------------------------------------------------------------------ -typedef void (*MblTransferCallback)(void *pArg, - unsigned char status, - unsigned int nbFreed); - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern void USBD_IrqHandler(void); - -extern void USBD_Init(void); - -extern void USBD_ConfigureSpeed(unsigned char forceFS); - -extern void USBD_Connect(void); - -extern void USBD_Disconnect(void); - -extern char USBD_Write( - unsigned char bEndpoint, - const void *pData, - unsigned int size, - TransferCallback callback, - void *pArg); - -extern char USBD_MblWrite( - unsigned char bEndpoint, - void * pMbl, - unsigned short wListSize, - unsigned char bCircList, - unsigned short wStartNdx, - MblTransferCallback fCallback, - void * pArgument); - -extern char USBD_MblReuse( - unsigned char bEndpoint, - unsigned char * pNewBuffer, - unsigned short wNewSize); - -extern char USBD_Read( - unsigned char bEndpoint, - void *pData, - unsigned int dLength, - TransferCallback fCallback, - void *pArg); - -extern unsigned char USBD_Stall(unsigned char bEndpoint); - -extern void USBD_Halt(unsigned char bEndpoint); - -extern void USBD_Unhalt(unsigned char bEndpoint); - -extern void USBD_ConfigureEndpoint(const USBEndpointDescriptor *pDescriptor); - -extern unsigned char USBD_IsHalted(unsigned char bEndpoint); - -extern void USBD_RemoteWakeUp(void); - -extern void USBD_SetAddress(unsigned char address); - -extern void USBD_SetConfiguration(unsigned char cfgnum); - -extern unsigned char USBD_GetState(void); - -extern unsigned char USBD_IsHighSpeed(void); - -extern void USBD_Test(unsigned char bIndex); - -/* USBD Callbacks */ - -#define USBDCallbacks_Reset() - -#define USBDCallbacks_Suspended() - -#define USBDCallbacks_Resumed() - -extern void USBDCallbacks_RequestReceived(const USBGenericRequest *request); - -extern void USBDDriverCallbacks_ConfigurationChanged(unsigned char cfgnum); - -extern void USBDDriverCallbacks_InterfaceSettingChanged(unsigned char interface, - unsigned char setting); - -#endif //#ifndef USBD_H - diff --git a/radio/src/targets/sky9x/usb/device/core/USBDDriver.c b/radio/src/targets/sky9x/usb/device/core/USBDDriver.c deleted file mode 100644 index d0ee0bb78..000000000 --- a/radio/src/targets/sky9x/usb/device/core/USBDDriver.c +++ /dev/null @@ -1,754 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/device/core/USBDDriver.h" - -#include "debug.h" -#include - -#include "../../../usb/common/core/USBFeatureRequest.h" -#include "../../../usb/common/core/USBGetDescriptorRequest.h" -#include "../../../usb/common/core/USBInterfaceRequest.h" -#include "../../../usb/common/core/USBSetAddressRequest.h" -#include "../../../usb/common/core/USBSetConfigurationRequest.h" -#include "../../../usb/device/core/USBD.h" -#include "board_lowlevel.h" -#include "../../../usb/common/core/USBConfigurationDescriptor.h" -#include "../../../usb/common/core/USBDeviceDescriptor.h" -#include "../../../usb/common/core/USBDeviceQualifierDescriptor.h" -#include "../../../usb/common/core/USBEndpointDescriptor.h" -#include "../../../usb/common/core/USBGenericDescriptor.h" - -//------------------------------------------------------------------------------ -// Local functions -//------------------------------------------------------------------------------ -#if defined(CHIP_USB_OTGHS) -static unsigned char otg_features_supported = 0; -#endif - -//------------------------------------------------------------------------------ -/// Send a NULL packet -//------------------------------------------------------------------------------ -static void TerminateCtrlInWithNull(void *pArg, - unsigned char status, - unsigned int transferred, - unsigned int remaining) -{ - USBD_Write(0, // Endpoint #0 - 0, // No data buffer - 0, // No data buffer - (TransferCallback) 0, - (void *) 0); -} - -//------------------------------------------------------------------------------ -/// Configures the device by setting it into the Configured state and -/// initializing all endpoints. -/// \param pDriver Pointer to a USBDDriver instance. -/// \param cfgnum Configuration number to set. -//------------------------------------------------------------------------------ -static void SetConfiguration(USBDDriver *pDriver, unsigned char cfgnum) -{ - USBEndpointDescriptor *pEndpoints[CHIP_USB_NUMENDPOINTS+1]; - const USBConfigurationDescriptor *pConfiguration; - - // Use different descriptor depending on device speed - if (USBD_IsHighSpeed()) { - - pConfiguration = pDriver->pDescriptors->pHsConfiguration; - } - else { - - pConfiguration = pDriver->pDescriptors->pFsConfiguration; - } - - // Set & save the desired configuration - USBD_SetConfiguration(cfgnum); - pDriver->cfgnum = cfgnum; - - // If the configuration is not 0, configure endpoints - if (cfgnum != 0) { - - // Parse configuration to get endpoint descriptors - USBConfigurationDescriptor_Parse(pConfiguration, 0, pEndpoints, 0); - - // Configure endpoints - int i = 0; - while (pEndpoints[i] != 0) { - - USBD_ConfigureEndpoint(pEndpoints[i]); - i++; - } - } - // Should be done before send the ZLP - USBDDriverCallbacks_ConfigurationChanged(cfgnum); - - // Acknowledge the request - USBD_Write(0, // Endpoint #0 - 0, // No data buffer - 0, // No data buffer - (TransferCallback) 0, - (void *) 0); -} - -//------------------------------------------------------------------------------ -/// Sends the current configuration number to the host. -/// \param pDriver Pointer to a USBDDriver instance. -//------------------------------------------------------------------------------ -static void GetConfiguration(const USBDDriver *pDriver) -{ - USBD_Write(0, &(pDriver->cfgnum), 1, 0, 0); -} - -//------------------------------------------------------------------------------ -/// Sends the current status of the device to the host. -/// \param pDriver Pointer to a USBDDriver instance. -//------------------------------------------------------------------------------ -static void GetDeviceStatus(const USBDDriver *pDriver) -{ - static unsigned short data; - const USBConfigurationDescriptor *pConfiguration; - - data = 0; - // Use different configuration depending on device speed - if (USBD_IsHighSpeed()) { - - pConfiguration = pDriver->pDescriptors->pHsConfiguration; - } - else { - - pConfiguration = pDriver->pDescriptors->pFsConfiguration; - } - - // Check current configuration for power mode (if device is configured) - if (pDriver->cfgnum != 0) { - - if (USBConfigurationDescriptor_IsSelfPowered(pConfiguration)) { - - data |= 1; - } - } - - // Check if remote wake-up is enabled - if (pDriver->isRemoteWakeUpEnabled) { - - data |= 2; - } - - // Send the device status - USBD_Write(0, &data, 2, 0, 0); -} - -//------------------------------------------------------------------------------ -/// Sends the current status of an endpoints to the USB host. -/// \param bEndpoint Endpoint number. -//------------------------------------------------------------------------------ -static void GetEndpointStatus(unsigned char bEndpoint) -{ - static unsigned short data; - - data = 0; - // Check if the endpoint exists - if (bEndpoint > CHIP_USB_NUMENDPOINTS) { - - USBD_Stall(0); - } - else { - - // Check if the endpoint if currently halted - if (USBD_IsHalted(bEndpoint)) { - - data = 1; - } - - // Send the endpoint status - USBD_Write(0, &data, 2, 0, 0); - } -} - -//------------------------------------------------------------------------------ -/// Sends the requested USB descriptor to the host if available, or STALLs the -/// request. -/// \param pDriver Pointer to a USBDDriver instance. -/// \param type Type of the requested descriptor -/// \param index Index of the requested descriptor. -/// \param length Maximum number of bytes to return. -//------------------------------------------------------------------------------ -static void GetDescriptor( - const USBDDriver *pDriver, - unsigned char type, - unsigned char indexRDesc, - unsigned int length) -{ - const USBDeviceDescriptor *pDevice; - const USBConfigurationDescriptor *pConfiguration; - const USBDeviceQualifierDescriptor *pQualifier; - const USBConfigurationDescriptor *pOtherSpeed; - const USBGenericDescriptor **pStrings = - (const USBGenericDescriptor **) pDriver->pDescriptors->pStrings; - const USBGenericDescriptor *pString; - unsigned char numStrings = pDriver->pDescriptors->numStrings; - unsigned char terminateWithNull = 0; - - // Use different set of descriptors depending on device speed - if (USBD_IsHighSpeed()) { - - TRACE_DEBUG("HS "); - pDevice = pDriver->pDescriptors->pHsDevice; - pConfiguration = pDriver->pDescriptors->pHsConfiguration; - pQualifier = pDriver->pDescriptors->pHsQualifier; - pOtherSpeed = pDriver->pDescriptors->pHsOtherSpeed; - } - else { - - TRACE_DEBUG("FS "); - pDevice = pDriver->pDescriptors->pFsDevice; - pConfiguration = pDriver->pDescriptors->pFsConfiguration; - pQualifier = pDriver->pDescriptors->pFsQualifier; - pOtherSpeed = pDriver->pDescriptors->pFsOtherSpeed; - } - - // Check the descriptor type - switch (type) { - - case USBGenericDescriptor_DEVICE: - TRACE_INFO_WP("Dev "); - - // Adjust length and send descriptor - if (length > USBGenericDescriptor_GetLength((USBGenericDescriptor *) pDevice)) { - - length = USBGenericDescriptor_GetLength((USBGenericDescriptor *) pDevice); - } - USBD_Write(0, pDevice, length, 0, 0); - break; - - case USBGenericDescriptor_CONFIGURATION: - TRACE_INFO_WP("Cfg "); - - // Adjust length and send descriptor - if (length > USBConfigurationDescriptor_GetTotalLength(pConfiguration)) { - - length = USBConfigurationDescriptor_GetTotalLength(pConfiguration); - terminateWithNull = ((length % pDevice->bMaxPacketSize0) == 0); - } - USBD_Write(0, - pConfiguration, - length, - terminateWithNull ? TerminateCtrlInWithNull : 0, - 0); - break; - - case USBGenericDescriptor_DEVICEQUALIFIER: - TRACE_INFO_WP("Qua "); - - // Check if descriptor exists - if (!pQualifier) { - - USBD_Stall(0); - } - else { - - // Adjust length and send descriptor - if (length > USBGenericDescriptor_GetLength((USBGenericDescriptor *) pQualifier)) { - - length = USBGenericDescriptor_GetLength((USBGenericDescriptor *) pQualifier); - } - USBD_Write(0, pQualifier, length, 0, 0); - } - break; - - case USBGenericDescriptor_OTHERSPEEDCONFIGURATION: - TRACE_INFO_WP("OSC "); - - // Check if descriptor exists - if (!pOtherSpeed) { - - USBD_Stall(0); - } - else { - - // Adjust length and send descriptor - if (length > USBConfigurationDescriptor_GetTotalLength(pOtherSpeed)) { - - length = USBConfigurationDescriptor_GetTotalLength(pOtherSpeed); - terminateWithNull = ((length % pDevice->bMaxPacketSize0) == 0); - } - USBD_Write(0, - pOtherSpeed, - length, - terminateWithNull ? TerminateCtrlInWithNull : 0, - 0); - } - break; - - case USBGenericDescriptor_STRING: - TRACE_INFO_WP("Str%d ", indexRDesc); - - // Check if descriptor exists - if (indexRDesc > numStrings) { - - USBD_Stall(0); - } - else { - - pString = pStrings[indexRDesc]; - - // Adjust length and send descriptor - if (length > USBGenericDescriptor_GetLength(pString)) { - - length = USBGenericDescriptor_GetLength(pString); - terminateWithNull = ((length % pDevice->bMaxPacketSize0) == 0); - } - USBD_Write(0, - pString, - length, - terminateWithNull ? TerminateCtrlInWithNull : 0, - 0); - } - break; - - default: - TRACE_WARNING( - "USBDDriver_GetDescriptor: Unknown descriptor type (%d)\n\r", - type); - USBD_Stall(0); - } -} - -//------------------------------------------------------------------------------ -/// Sets the active setting of the given interface if the configuration supports -/// it; otherwise, the control pipe is STALLed. If the setting of an interface -/// changes. -/// \parma pDriver Pointer to a USBDDriver instance. -/// \parma infnum Interface number. -/// \parma setting New active setting for the interface. -//------------------------------------------------------------------------------ -static void SetInterface( - USBDDriver *pDriver, - unsigned char infnum, - unsigned char setting) -{ - // Make sure alternate settings are supported - if (!pDriver->pInterfaces) { - - USBD_Stall(0); - } - else { - - // Change the current setting of the interface and trigger the callback - // if necessary - if (pDriver->pInterfaces[infnum] != setting) { - - pDriver->pInterfaces[infnum] = setting; - // USBDDriverCallbacks_InterfaceSettingChanged(infnum, setting); - } - - // Acknowledge the request - USBD_Write(0, 0, 0, 0, 0); - } -} - -//------------------------------------------------------------------------------ -/// Sends the currently active setting of the given interface to the USB -/// host. If alternate settings are not supported, this function STALLs the -/// control pipe. -/// \param pDriver Pointer to a USBDDriver instance. -/// \param infnum Interface number. -//------------------------------------------------------------------------------ -static void GetInterface( - const USBDDriver *pDriver, - unsigned char infnum) -{ - // Make sure alternate settings are supported, or STALL the control pipe - if (!pDriver->pInterfaces) { - - USBD_Stall(0); - } - else { - - // Sends the current interface setting to the host - USBD_Write(0, &(pDriver->pInterfaces[infnum]), 1, 0, 0); - } -} - -#if defined(CHIP_USB_UDPHS) || defined(CHIP_USB_OTGHS) -//------------------------------------------------------------------------------ -// Performs the selected test on the USB device (high-speed only). -// \param test Test selector value. -//------------------------------------------------------------------------------ -static void USBDDriver_Test(unsigned char test) -{ - TRACE_DEBUG("UDPHS_Test\n\r"); - - // the lower byte of wIndex must be zero - // the most significant byte of wIndex is used to specify the specific test mode - switch (test) { - case USBFeatureRequest_TESTPACKET: - //Test mode Test_Packet: - //Upon command, a port must repetitively transmit the following test packet until - //the exit action is taken. This enables the testing of rise and fall times, eye - //patterns, jitter, and any other dynamic waveform specifications. - //The test packet is made up by concatenating the following strings. - //(Note: For J/K NRZI data, and for NRZ data, the bit on the left is the first one - //transmitted. �S� indicates that a bit stuff occurs, which inserts an �extra� NRZI data bit. - //�* N� is used to indicate N occurrences of a string of bits or symbols.) - //A port in Test_Packet mode must send this packet repetitively. The inter-packet timing - //must be no less than the minimum allowable inter-packet gap as defined in Section 7.1.18 and - //no greater than 125 us. - // Send ZLP - USBD_Test(USBFeatureRequest_TESTSENDZLP); - // Tst PACKET - USBD_Test(USBFeatureRequest_TESTPACKET); - while (1); - //break; not reached - - case USBFeatureRequest_TESTJ: - //Test mode Test_J: - //Upon command, a port�s transceiver must enter the high-speed J state and remain in that - //state until the exit action is taken. This enables the testing of the high output drive - //level on the D+ line. - // Send ZLP - USBD_Test(USBFeatureRequest_TESTSENDZLP); - // Tst J - USBD_Test(USBFeatureRequest_TESTJ); - while (1); - //break; not reached - - case USBFeatureRequest_TESTK: - //Test mode Test_K: - //Upon command, a port�s transceiver must enter the high-speed K state and remain in - //that state until the exit action is taken. This enables the testing of the high output drive - //level on the D- line. - // Send a ZLP - USBD_Test(USBFeatureRequest_TESTSENDZLP); - USBD_Test(USBFeatureRequest_TESTK); - while (1); - //break; not reached - - case USBFeatureRequest_TESTSE0NAK: - //Test mode Test_SE0_NAK: - //Upon command, a port�s transceiver must enter the high-speed receive mode - //and remain in that mode until the exit action is taken. This enables the testing - //of output impedance, low level output voltage, and loading characteristics. - //In addition, while in this mode, upstream facing ports (and only upstream facing ports) - //must respond to any IN token packet with a NAK handshake (only if the packet CRC is - //determined to be correct) within the normal allowed device response time. This enables testing of - //the device squelch level circuitry and, additionally, provides a general purpose stimulus/response - //test for basic functional testing. - // Send a ZLP - USBD_Test(USBFeatureRequest_TESTSENDZLP); - // Test SE0_NAK - USBD_Test(USBFeatureRequest_TESTSE0NAK); - while (1); - //break; not reached - - default: - USBD_Stall(0); - break; - - } - // The exit action is to power cycle the device. - // The device must be disconnected from the host -} -#endif - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Initializes a USBDDriver instance with a list of descriptors. If -/// interfaces can have multiple alternate settings, an array to store the -/// current setting for each interface must be provided. -/// \param pDriver Pointer to a USBDDriver instance. -/// \param pDescriptors Pointer to a USBDDriverDescriptors instance. -/// \param pInterfaces Pointer to an array for storing the current alternate -/// setting of each interface (optional). -//------------------------------------------------------------------------------ -void USBDDriver_Initialize( - USBDDriver *pDriver, - const USBDDriverDescriptors *pDescriptors, - unsigned char *pInterfaces) -{ - - pDriver->cfgnum = 0; -#if (BOARD_USB_BMATTRIBUTES == USBConfigurationDescriptor_SELFPOWERED_RWAKEUP) \ - || (BOARD_USB_BMATTRIBUTES == USBConfigurationDescriptor_BUSPOWERED_RWAKEUP) - pDriver->isRemoteWakeUpEnabled = 1; -#else - pDriver->isRemoteWakeUpEnabled = 0; -#endif - - pDriver->pDescriptors = pDescriptors; - pDriver->pInterfaces = pInterfaces; - -#if 0 - // Initialize interfaces array if not null - if (pInterfaces != 0) { - memset(pInterfaces, sizeof(*pInterfaces), 0); // Really wrong, but never happens :) - } -#endif -} - -//------------------------------------------------------------------------------ -/// Handles the given request if it is standard, otherwise STALLs it. -/// \param pDriver Pointer to a USBDDriver instance. -/// \param pRequest Pointer to a USBGenericRequest instance. -//------------------------------------------------------------------------------ -void USBDDriver_RequestHandler( - USBDDriver *pDriver, - const USBGenericRequest *pRequest) -{ - unsigned char cfgnum; - unsigned char infnum; - unsigned char eptnum; - unsigned char setting; - unsigned char type; - unsigned char indexDesc; - unsigned int length; - unsigned int address; - - TRACE_INFO_WP("Std "); - - // Check request code - switch (USBGenericRequest_GetRequest(pRequest)) { - - case USBGenericRequest_GETDESCRIPTOR: - TRACE_INFO_WP("gDesc "); - - // Send the requested descriptor - type = USBGetDescriptorRequest_GetDescriptorType(pRequest); - indexDesc = USBGetDescriptorRequest_GetDescriptorIndex(pRequest); - length = USBGenericRequest_GetLength(pRequest); - GetDescriptor(pDriver, type, indexDesc, length); - break; - - case USBGenericRequest_SETADDRESS: - TRACE_INFO_WP("sAddr "); - - // Sends a zero-length packet and then set the device address - address = USBSetAddressRequest_GetAddress(pRequest); - USBD_Write(0, 0, 0, (TransferCallback) USBD_SetAddress, (void *) address); - break; - - case USBGenericRequest_SETCONFIGURATION: - TRACE_INFO_WP("sCfg "); - - // Set the requested configuration - cfgnum = USBSetConfigurationRequest_GetConfiguration(pRequest); - SetConfiguration(pDriver, cfgnum); - break; - - case USBGenericRequest_GETCONFIGURATION: - TRACE_INFO_WP("gCfg "); - - // Send the current configuration number - GetConfiguration(pDriver); - break; - - case USBGenericRequest_GETSTATUS: - TRACE_INFO_WP("gSta "); - - // Check who is the recipient - switch (USBGenericRequest_GetRecipient(pRequest)) { - - case USBGenericRequest_DEVICE: - TRACE_INFO_WP("Dev "); - - // Send the device status - GetDeviceStatus(pDriver); - break; - - case USBGenericRequest_ENDPOINT: - TRACE_INFO_WP("Ept "); - - // Send the endpoint status - eptnum = USBGenericRequest_GetEndpointNumber(pRequest); - GetEndpointStatus(eptnum); - break; - - default: - TRACE_WARNING( - "USBDDriver_RequestHandler: Unknown recipient (%d)\n\r", - USBGenericRequest_GetRecipient(pRequest)); - USBD_Stall(0); - } - break; - - case USBGenericRequest_CLEARFEATURE: - TRACE_INFO_WP("cFeat "); - - // Check which is the requested feature - switch (USBFeatureRequest_GetFeatureSelector(pRequest)) { - - case USBFeatureRequest_ENDPOINTHALT: - TRACE_INFO_WP("Hlt "); - - // Unhalt endpoint and send a zero-length packet - USBD_Unhalt(USBGenericRequest_GetEndpointNumber(pRequest)); - USBD_Write(0, 0, 0, 0, 0); - break; - - case USBFeatureRequest_DEVICEREMOTEWAKEUP: - TRACE_INFO_WP("RmWU "); - - // Disable remote wake-up and send a zero-length packet - pDriver->isRemoteWakeUpEnabled = 0; - USBD_Write(0, 0, 0, 0, 0); - break; - - default: - TRACE_WARNING( - "USBDDriver_RequestHandler: Unknown feature selector (%d)\n\r", - USBFeatureRequest_GetFeatureSelector(pRequest)); - USBD_Stall(0); - } - break; - - case USBGenericRequest_SETFEATURE: - TRACE_INFO_WP("sFeat "); - - // Check which is the selected feature - switch (USBFeatureRequest_GetFeatureSelector(pRequest)) { - - case USBFeatureRequest_DEVICEREMOTEWAKEUP: - TRACE_INFO_WP("RmWU "); - - // Enable remote wake-up and send a ZLP - pDriver->isRemoteWakeUpEnabled = 1; - USBD_Write(0, 0, 0, 0, 0); - break; - - case USBFeatureRequest_ENDPOINTHALT: - TRACE_INFO_WP("Halt "); - // Halt endpoint - USBD_Halt(USBGenericRequest_GetEndpointNumber(pRequest)); - USBD_Write(0, 0, 0, 0, 0); - break; - -#if defined(CHIP_USB_UDPHS) || defined(CHIP_USB_OTGHS) - - case USBFeatureRequest_TESTMODE: - // 7.1.20 Test Mode Support - if ((USBGenericRequest_GetType(pRequest) == USBGenericRequest_DEVICE) - && ((USBGenericRequest_GetIndex(pRequest) & 0x000F) == 0)) { - - // Handle test request - USBDDriver_Test(USBFeatureRequest_GetTestSelector(pRequest)); - } - else { - - USBD_Stall(0); - } - break; -#endif -#if defined(CHIP_USB_OTGHS) - case USBFeatureRequest_OTG_B_HNP_ENABLE: - TRACE_INFO_WP("OTG_B_HNP_ENABLE "); - otg_features_supported |= 1<isRemoteWakeUpEnabled; -} - -#if defined(CHIP_USB_OTGHS) -//------------------------------------------------------------------------------ -/// Return OTG features supported -/// \return the OTG features -//------------------------------------------------------------------------------ -unsigned char USBDDriver_returnOTGFeatures(void) -{ - return otg_features_supported; -} - -//------------------------------------------------------------------------------ -/// Clear OTG features supported -/// \return none -//------------------------------------------------------------------------------ -void USBDDriver_clearOTGFeatures(void) -{ - otg_features_supported = 0; -} -#endif - diff --git a/radio/src/targets/sky9x/usb/device/core/USBDDriver.h b/radio/src/targets/sky9x/usb/device/core/USBDDriver.h deleted file mode 100644 index e0c05a573..000000000 --- a/radio/src/targets/sky9x/usb/device/core/USBDDriver.h +++ /dev/null @@ -1,101 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - USB Device Driver class definition. - - !!!Usage - - -# Instanciate a USBDDriver object and initialize it using - USBDDriver_Initialize. - -# When a USB SETUP request is received, forward it to the standard - driver using USBDDriver_RequestHandler. - -# Check the Remote Wakeup setting via USBDDriver_IsRemoteWakeUpEnabled. -*/ - -#ifndef USBDDRIVER_H -#define USBDDRIVER_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBGenericRequest.h" -#include "../../../usb/device/core/USBDDriverDescriptors.h" - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// USB device driver structure, holding a list of descriptors identifying -/// the device as well as the driver current state. -//------------------------------------------------------------------------------ -typedef struct { - - /// List of descriptors used by the device. - const USBDDriverDescriptors *pDescriptors; - /// Current setting for each interface. - unsigned char *pInterfaces; - /// Current configuration number (0 -> device is not configured). - unsigned char cfgnum; - /// Indicates if remote wake up has been enabled by the host. - unsigned char isRemoteWakeUpEnabled; -#if defined(CHIP_USB_OTGHS) - /// Features supported by OTG - unsigned char otg_features_supported; -#endif -} USBDDriver; - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern void USBDDriver_Initialize( - USBDDriver *pDriver, - const USBDDriverDescriptors *pDescriptors, - unsigned char *pInterfaces); - -extern void USBDDriver_RequestHandler( - USBDDriver *pDriver, - const USBGenericRequest *pRequest); - -extern unsigned char USBDDriver_IsRemoteWakeUpEnabled(const USBDDriver *pDriver); - -#if defined(CHIP_USB_OTGHS) -extern unsigned char USBDDriver_returnOTGFeatures(void); -extern void USBDDriver_clearOTGFeatures(void); -#endif - -#endif //#ifndef USBDDRIVER_H - diff --git a/radio/src/targets/sky9x/usb/device/core/USBDDriverDescriptors.h b/radio/src/targets/sky9x/usb/device/core/USBDDriverDescriptors.h deleted file mode 100644 index 0a66c5177..000000000 --- a/radio/src/targets/sky9x/usb/device/core/USBDDriverDescriptors.h +++ /dev/null @@ -1,86 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of a class for declaring USB descriptors required by the - device driver. -*/ - -#ifndef USBDDRIVERDESCRIPTORS_H -#define USBDDRIVERDESCRIPTORS_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/common/core/USBConfigurationDescriptor.h" -#include "../../../usb/common/core/USBDeviceDescriptor.h" -#include "../../../usb/common/core/USBDeviceQualifierDescriptor.h" - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// List of all descriptors used by a USB device driver. Each descriptor can -/// be provided in two versions: full-speed and high-speed. Devices which are -/// not high-speed capable do not need to provided high-speed descriptors and -/// the full-speed qualifier & other speed descriptors. -//------------------------------------------------------------------------------ -typedef struct { - - /// Pointer to the full-speed device descriptor. - const USBDeviceDescriptor *pFsDevice; - /// Pointer to the full-speed configuration descriptor. - const USBConfigurationDescriptor *pFsConfiguration; - /// Pointer to the full-speed qualifier descriptor. - const USBDeviceQualifierDescriptor *pFsQualifier; - /// Pointer to the full-speed other speed configuration descriptor. - const USBConfigurationDescriptor *pFsOtherSpeed; - /// Pointer to the high-speed device descriptor. - const USBDeviceDescriptor *pHsDevice; - /// Pointer to the high-speed configuration descriptor. - const USBConfigurationDescriptor *pHsConfiguration; - /// Pointer to the high-speed qualifier descriptor. - const USBDeviceQualifierDescriptor *pHsQualifier; - /// Pointer to the high-speed other speed configuration descriptor. - const USBConfigurationDescriptor *pHsOtherSpeed; - /// Pointer to the list of string descriptors. - const unsigned char **pStrings; - /// Number of string descriptors in list. - unsigned char numStrings; - -} USBDDriverDescriptors; - -#endif //#ifndef USBDDRIVERDESCRIPTORS_H - diff --git a/radio/src/targets/sky9x/usb/device/core/USBD_UDP.c b/radio/src/targets/sky9x/usb/device/core/USBD_UDP.c deleted file mode 100644 index 3ea259437..000000000 --- a/radio/src/targets/sky9x/usb/device/core/USBD_UDP.c +++ /dev/null @@ -1,1730 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Implementation of USB device functions on a UDP controller. - - See "USBD API Methods". -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "board_lowlevel.h" -#include "../../../usb/common/core/USBEndpointDescriptor.h" -#include "../../../usb/common/core/USBGenericRequest.h" -#include "../../../usb/device/core/USBD.h" -#include "debug.h" - -//------------------------------------------------------------------------------ -// Local definitions -//------------------------------------------------------------------------------ -#define MASK_STATUS0 0xFFFFFFFC -#define MASK_STATUS1 0xFFFFFFFF - - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Enables the clock of a peripheral. The peripheral ID is used - * to identify which peripheral is targetted. - * \note The ID must NOT be shifted (i.e. 1 << ID_xxx). - * \param id Peripheral ID (ID_xxx). - */ -void PMC_EnablePeripheral(unsigned int id) -{ - // SANITY_CHECK(id < 35); - - if (id < 32) { - if ((PMC->PMC_PCSR0 & (1 << id)) == (1 << id)) { - - TRACE_DEBUG("PMC_EnablePeripheral: clock of peripheral" " %u is already enabled\n\r", id); - } - else { - PMC->PMC_PCER0 = 1 << id; - } - } - else { - id -= 32; - if ((PMC->PMC_PCSR1 & (1 << id)) == (1 << id)) { - - TRACE_DEBUG("PMC_EnablePeripheral: clock of peripheral" " %u is already enabled\n\r", id + 32); - } - else { - PMC->PMC_PCER1 = 1 << id; - } - } -} - -/** - * \brief Disables the clock of a peripheral. The peripheral ID is used - * to identify which peripheral is targetted. - * \note The ID must NOT be shifted (i.e. 1 << ID_xxx). - * \param id Peripheral ID (ID_xxx). - */ -void PMC_DisablePeripheral(unsigned int id) -{ - // SANITY_CHECK(id < 35); - if (id < 32) { - if ((PMC->PMC_PCSR0 & (1 << id)) != (1 << id)) { - TRACE_DEBUG("PMC_DisablePeripheral: clock of peripheral" " %u is not enabled\n\r", id); - } - else { - PMC->PMC_PCDR0 = 1 << id; - } - } - else { - id -= 32; - if ((PMC->PMC_PCSR1 & (1 << id)) != (1 << id)) { - TRACE_DEBUG("PMC_DisablePeripheral: clock of peripheral" " %u is not enabled\n\r", id + 32); - } - else { - PMC->PMC_PCDR1 = 1 << id; - } - } -} - -/** - * \brief Enable all the periph clock via PMC - */ -void PMC_EnableAllPeripherals(void) -{ - PMC->PMC_PCER0 = MASK_STATUS0; - while( (PMC->PMC_PCSR0 & MASK_STATUS0) != MASK_STATUS0); - PMC->PMC_PCER1 = MASK_STATUS1; - while( (PMC->PMC_PCSR1 & MASK_STATUS1) != MASK_STATUS1); - TRACE_DEBUG("Enable all periph clocks\n\r"); -} -/** - * \brief Disable all the periph clock via PMC - */ -void PMC_DisableAllPeripherals(void) -{ - PMC->PMC_PCDR0 = MASK_STATUS0; - while((PMC->PMC_PCSR0 & MASK_STATUS0) != 0); - PMC->PMC_PCDR1 = MASK_STATUS1; - while((PMC->PMC_PCSR1 & MASK_STATUS1) != 0); - TRACE_DEBUG("Disable all periph clocks\n\r"); -} - -/** - * \brief Get Periph Status for the given peripheral ID. - * \param id Peripheral ID (ID_xxx). - */ -unsigned int PMC_IsPeriphEnabled(unsigned int id) -{ - // SANITY_CHECK(id < 35); - - if (id < 32) { - return (PMC->PMC_PCSR0 & (1 << id)); - } - else { - return (PMC->PMC_PCSR1 & (1 << (id - 32))); - } -} - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "UDP register field values" -/// -/// This page lists the initialize values of UDP registers. -/// -/// !Values -/// - UDP_RXDATA - -/// Bit mask for both banks of the UDP_CSR register. -#define UDP_CSR_RXDATA_BK (UDP_CSR_RX_DATA_BK0 | UDP_CSR_RX_DATA_BK1) -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "Endpoint states" -/// -/// This page lists the endpoint states. -/// -/// !States -// - UDP_ENDPOINT_DISABLED -// - UDP_ENDPOINT_HALTED -// - UDP_ENDPOINT_IDLE -// - UDP_ENDPOINT_SENDING -// - UDP_ENDPOINT_RECEIVING -// - UDP_ENDPOINT_SENDINGM -// - UDP_ENDPOINT_RECEIVINGM - -/// Endpoint states: Endpoint is disabled -#define UDP_ENDPOINT_DISABLED 0 -/// Endpoint states: Endpoint is halted (i.e. STALLs every request) -#define UDP_ENDPOINT_HALTED 1 -/// Endpoint states: Endpoint is idle (i.e. ready for transmission) -#define UDP_ENDPOINT_IDLE 2 -/// Endpoint states: Endpoint is sending data -#define UDP_ENDPOINT_SENDING 3 -/// Endpoint states: Endpoint is receiving data -#define UDP_ENDPOINT_RECEIVING 4 -/// Endpoint states: Endpoint is sending MBL -#define UDP_ENDPOINT_SENDINGM 5 -/// Endpoint states: Endpoint is receiving MBL -#define UDP_ENDPOINT_RECEIVINGM 6 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "UDP_CSR register access" -/// -/// This page lists the macroes to access UDP CSR register. -/// -/// !Macros -/// - CLEAR_CSR -/// - SET_CSR - -/// Bitmap for all status bits in CSR. -#define REG_NO_EFFECT_1_ALL UDP_CSR_RX_DATA_BK0 | UDP_CSR_RX_DATA_BK1 \ - |UDP_CSR_STALLSENTISOERROR | UDP_CSR_RXSETUP \ - |UDP_CSR_TXCOMP - -/// Clears the specified bit(s) in the UDP_CSR register. -/// \param endpoint The endpoint number of the CSR to process. -/// \param flags The bitmap to set to 1. -#define SET_CSR(endpoint, flags) \ - { \ - volatile unsigned int reg; \ - int timeOut = 200; \ - reg = UDP->UDP_CSR[endpoint] ; \ - reg |= REG_NO_EFFECT_1_ALL; \ - reg |= (flags); \ - UDP->UDP_CSR[endpoint] = reg; \ - while ( (UDP->UDP_CSR[endpoint] & (flags)) != (flags)) \ - { \ - if (-- timeOut <= 0) break; \ - } \ - } - -/// Sets the specified bit(s) in the UDP_CSR register. -/// \param endpoint The endpoint number of the CSR to process. -/// \param flags The bitmap to clear to 0. -#define CLEAR_CSR(endpoint, flags) \ - { \ - volatile unsigned int reg; \ - reg = UDP->UDP_CSR[endpoint]; \ - reg |= REG_NO_EFFECT_1_ALL; \ - reg &= ~(flags); \ - UDP->UDP_CSR[endpoint] = reg; \ - while ( (UDP->UDP_CSR[endpoint] & (flags)) == (flags)); \ - } -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -/// Describes an ongoing transfer on a UDP endpoint. -typedef struct { - - /// Pointer to a data buffer used for emission/reception. - char *pData; - /// Number of bytes which have been written into the UDP internal FIFO - /// buffers. - volatile int buffered; - /// Number of bytes which have been sent/received. - volatile int transferred; - /// Number of bytes which have not been buffered/transferred yet. - volatile int remaining; - /// Optional callback to invoke when the transfer completes. - volatile TransferCallback fCallback; - /// Optional argument to the callback function. - void *pArgument; -} Transfer; - -/// Describes Multi Buffer List transfer on a UDP endpoint. -typedef struct { - /// Pointer to frame list - USBDTransferBuffer *pMbl; - /// Pointer to last loaded buffer - USBDTransferBuffer *pLastLoaded; - /// List size - unsigned short listSize; - /// Current processing frame - unsigned short currBuffer; - /// First freed frame to re-use - unsigned short freedBuffer; - /// Frame setting, circle frame list - unsigned char circList; - /// All buffer listed is used - unsigned char allUsed; - /// Optional callback to invoke when the transfer completes. - MblTransferCallback fCallback; - /// Optional argument to the callback function. - void *pArgument; -} MblTransfer; - -//------------------------------------------------------------------------------ -/// Describes the state of an endpoint of the UDP controller. -//------------------------------------------------------------------------------ -typedef struct { - - /// Current endpoint state. - volatile unsigned char state; - /// Current reception bank (0 or 1). - volatile unsigned char bank; - /// Maximum packet size for the endpoint. - volatile unsigned short size; - /// Describes an ongoing transfer (if current state is either - /// or ) - union { - Transfer singleTransfer; - MblTransfer mblTransfer; - } transfer; -} Endpoint; - -//------------------------------------------------------------------------------ -// Internal variables -//------------------------------------------------------------------------------ - -/// Holds the internal state for each endpoint of the UDP. -static Endpoint endpoints[CHIP_USB_NUMENDPOINTS]; - -/// Device current state. -static unsigned char deviceState; -/// Indicates the previous device state -static unsigned char previousDeviceState; - -//------------------------------------------------------------------------------ -// Internal Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Enables the clock of the UDP peripheral. -/// \return 1 if peripheral status changed. -//------------------------------------------------------------------------------ -static unsigned char UDP_EnablePeripheralClock(void) -{ - if (!PMC_IsPeriphEnabled(ID_UDP)) { - PMC_EnablePeripheral(ID_UDP); - return 1; - } - return 0; -} - -//------------------------------------------------------------------------------ -/// Disables the UDP peripheral clock. -//------------------------------------------------------------------------------ -static inline void UDP_DisablePeripheralClock(void) -{ - PMC_DisablePeripheral(ID_UDP); -} - -//------------------------------------------------------------------------------ -/// Enables the 48MHz USB clock. -//------------------------------------------------------------------------------ -static inline void UDP_EnableUsbClock(void) -{ - REG_PMC_SCER = PMC_SCER_UDP; -} - -//------------------------------------------------------------------------------ -/// Disables the 48MHz USB clock. -//------------------------------------------------------------------------------ -static inline void UDP_DisableUsbClock(void) -{ - REG_PMC_SCDR = PMC_SCER_UDP; -} - -//------------------------------------------------------------------------------ -/// Enables the UDP transceiver. -//------------------------------------------------------------------------------ -static inline void UDP_EnableTransceiver(void) -{ - UDP->UDP_TXVC &= ~UDP_TXVC_TXVDIS; -} - -//------------------------------------------------------------------------------ -/// Disables the UDP transceiver. -//------------------------------------------------------------------------------ -static inline void UDP_DisableTransceiver(void) -{ - UDP->UDP_TXVC |= UDP_TXVC_TXVDIS; -} - -//------------------------------------------------------------------------------ -/// Handles a completed transfer on the given endpoint, invoking the -/// configured callback if any. -/// \param bEndpoint Number of the endpoint for which the transfer has completed. -/// \param bStatus Status code returned by the transfer operation -//------------------------------------------------------------------------------ -static void UDP_EndOfTransfer(unsigned char bEndpoint, char bStatus) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - - // Check that endpoint was sending or receiving data - if( (pEndpoint->state == UDP_ENDPOINT_RECEIVING) - || (pEndpoint->state == UDP_ENDPOINT_SENDING)) { - - Transfer *pTransfer = (Transfer *)&(pEndpoint->transfer); - - TRACE_DEBUG_WP("EoT "); - - // Endpoint returns in Idle state - pEndpoint->state = UDP_ENDPOINT_IDLE; - - // Invoke callback is present - if (pTransfer->fCallback != 0) { - - ((TransferCallback) pTransfer->fCallback) - (pTransfer->pArgument, - bStatus, - pTransfer->transferred, - pTransfer->remaining + pTransfer->buffered); - } - else { - TRACE_DEBUG_WP("NoCB "); - } - } - else if ( (pEndpoint->state == UDP_ENDPOINT_RECEIVINGM) - || (pEndpoint->state == UDP_ENDPOINT_SENDINGM) ) { - - MblTransfer *pTransfer = (MblTransfer*)&(pEndpoint->transfer); - - TRACE_DEBUG_WP("EoMT "); - - // Endpoint returns in Idle state - pEndpoint->state = UDP_ENDPOINT_IDLE; - // Invoke callback - if (pTransfer->fCallback != 0) { - - ((MblTransferCallback) pTransfer->fCallback) - (pTransfer->pArgument, - bStatus, - 0); - } - else { - TRACE_DEBUG_WP("NoCB "); - } - } -} - -//------------------------------------------------------------------------------ -/// Clears the correct reception flag (bank 0 or bank 1) of an endpoint -/// \param bEndpoint Index of endpoint -//------------------------------------------------------------------------------ -static void UDP_ClearRxFlag(unsigned char bEndpoint) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - - // Clear flag and change banks - if (pEndpoint->bank == 0) { - - CLEAR_CSR(bEndpoint, UDP_CSR_RX_DATA_BK0); - // Swap bank if in dual-fifo mode - if (CHIP_USB_ENDPOINTS_BANKS(bEndpoint) > 1) { - - pEndpoint->bank = 1; - } - } - else { - - CLEAR_CSR(bEndpoint, UDP_CSR_RX_DATA_BK1); - pEndpoint->bank = 0; - } -} - -//------------------------------------------------------------------------------ -/// Update multi-buffer-transfer descriptors. -/// \param pTransfer Pointer to instance MblTransfer. -/// \param size Size of bytes that processed. -/// \param forceEnd Force the buffer END. -/// \return 1 if current buffer ended. -//------------------------------------------------------------------------------ -static char UDP_MblUpdate(MblTransfer *pTransfer, - USBDTransferBuffer * pBi, - unsigned short size, - unsigned char forceEnd) -{ - // Update transfer descriptor - pBi->remaining -= size; - // Check if current buffer ended - if (pBi->remaining == 0 || forceEnd) { - - // Process to next buffer - if ((++ pTransfer->currBuffer) == pTransfer->listSize) { - if (pTransfer->circList) { - pTransfer->currBuffer = 0; - } - else { - pTransfer->allUsed = 1; - } - } - // All buffer in the list is processed - if (pTransfer->currBuffer == pTransfer->freedBuffer) { - pTransfer->allUsed = 1; - } - // Continue transfer, prepare for next operation - if (pTransfer->allUsed == 0) { - pBi = &pTransfer->pMbl[pTransfer->currBuffer]; - pBi->buffered = 0; - pBi->transferred = 0; - pBi->remaining = pBi->size; - } - return 1; - } - return 0; -} - -//------------------------------------------------------------------------------ -/// Transfers a data payload from the current tranfer buffer to the endpoint -/// FIFO -/// \param bEndpoint Number of the endpoint which is sending data. -//------------------------------------------------------------------------------ -static char UDP_MblWriteFifo(unsigned char bEndpoint) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - MblTransfer *pTransfer = (MblTransfer*)&(pEndpoint->transfer); - USBDTransferBuffer *pBi = &(pTransfer->pMbl[pTransfer->currBuffer]); - signed int size; - - volatile unsigned char * pBytes; - volatile char bufferEnd = 1; - - // Get the number of bytes to send - size = pEndpoint->size; - if (size > pBi->remaining) { - - size = pBi->remaining; - } - - TRACE_DEBUG_WP("w%d.%d ", pTransfer->currBuffer, size); - if (size == 0) { - - return 1; - } - - pTransfer->pLastLoaded = pBi; - pBytes = &(pBi->pBuffer[pBi->transferred + pBi->buffered]); - pBi->buffered += size; - bufferEnd = UDP_MblUpdate(pTransfer, pBi, size, 0); - - // Write packet in the FIFO buffer - if (size) { - signed int c8 = size >> 3; - signed int c1 = size & 0x7; - //printf("%d[%x] ", pBi->transferred, pBytes); - for (; c8; c8 --) { - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - } - for (; c1; c1 --) { - UDP->UDP_FDR[bEndpoint] = *(pBytes ++); - } - } - return bufferEnd; -} -/* -//------------------------------------------------------------------------------ -/// Transfers a data payload from an endpoint FIFO to the current transfer -/// buffer, if NULL packet received, the current buffer is ENDed. -/// \param bEndpoint Endpoint number. -/// \param wPacketSize Size of received data packet -/// \return 1 if the buffer ENDed. -//------------------------------------------------------------------------------ -static char UDP_MblReadFifo(unsigned char bEndpoint, unsigned short wPacketSize) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - MblTransfer *pTransfer = (MblTransfer*)&(pEndpoint->transfer); - USBDTransferBuffer *pBi = &(pTransfer->pMbl[pTransfer->currBuffer]); - char bufferEnd; - - // Check that the requested size is not bigger than the remaining transfer - if (wPacketSize > pTransfer->remaining) { - - pTransfer->buffered += wPacketSize - pTransfer->remaining; - wPacketSize = pTransfer->remaining; - } - - // Update transfer descriptor information - pBi->transferred += wPacketSize; - bufferEnd = UDP_MblUpdate(pTransfer, - wPacketSize, - (wPacketSize < pEndpoint->size)); - - // Retrieve packet - if (wPacketSize) { - unsigned char * pBytes = &pBi->pBuffer[pBi->transferred]; - signed int c8 = wPacketSize >> 3; - signed int c1 = wPacketSize & 0x7; - for (; c8; c8 --) { - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - } - for (; c1; c1 --) { - *(pBytes ++) = UDP->UDP_FDR[bEndpoint]; - } - } - return bufferEnd; -} -*/ -//------------------------------------------------------------------------------ -/// Transfers a data payload from the current tranfer buffer to the endpoint -/// FIFO -/// \param bEndpoint Number of the endpoint which is sending data. -//------------------------------------------------------------------------------ -static void UDP_WritePayload(unsigned char bEndpoint) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); - signed int size; - - // Get the number of bytes to send - size = pEndpoint->size; - if (size > pTransfer->remaining) { - - size = pTransfer->remaining; - } - - // Update transfer descriptor information - pTransfer->buffered += size; - pTransfer->remaining -= size; - - // Write packet in the FIFO buffer - while (size > 0) { - - UDP->UDP_FDR[bEndpoint] = *(pTransfer->pData); - pTransfer->pData++; - size--; - } -} - - -//------------------------------------------------------------------------------ -/// Transfers a data payload from an endpoint FIFO to the current transfer buffer -/// \param bEndpoint Endpoint number. -/// \param wPacketSize Size of received data packet -//------------------------------------------------------------------------------ -static void UDP_ReadPayload(unsigned char bEndpoint, int wPacketSize) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); - - // Check that the requested size is not bigger than the remaining transfer - if (wPacketSize > pTransfer->remaining) { - - pTransfer->buffered += wPacketSize - pTransfer->remaining; - wPacketSize = pTransfer->remaining; - } - - // Update transfer descriptor information - pTransfer->remaining -= wPacketSize; - pTransfer->transferred += wPacketSize; - - // Retrieve packet - while (wPacketSize > 0) { - - *(pTransfer->pData) = (char) UDP->UDP_FDR[bEndpoint]; - pTransfer->pData++; - wPacketSize--; - } -} - -//------------------------------------------------------------------------------ -/// Received SETUP packet from endpoint 0 FIFO -/// \param pRequest Generic USB SETUP request sent over Control endpoints -//------------------------------------------------------------------------------ -static void UDP_ReadRequest(USBGenericRequest *pRequest) -{ - unsigned char *pData = (unsigned char *)pRequest; - unsigned int i; - - // Copy packet - for (i = 0; i < 8; i++) { - - *pData = (unsigned char) UDP->UDP_FDR[0]; - pData++; - } -} - -//------------------------------------------------------------------------------ -/// Reset all endpoint transfer descriptors -//------------------------------------------------------------------------------ -static void UDP_ResetEndpoints( void ) -{ - Endpoint *pEndpoint; - Transfer *pTransfer; - unsigned char bEndpoint; - - // Reset the transfer descriptor of every endpoint - for (bEndpoint = 0; bEndpoint < CHIP_USB_NUMENDPOINTS; bEndpoint++) { - - pEndpoint = &(endpoints[bEndpoint]); - pTransfer = (Transfer*)&(pEndpoint->transfer); - - // Reset endpoint transfer descriptor - pTransfer->pData = 0; - pTransfer->transferred = -1; - pTransfer->buffered = -1; - pTransfer->remaining = -1; - pTransfer->fCallback = 0; - pTransfer->pArgument = 0; - - // Reset endpoint state - pEndpoint->bank = 0; - pEndpoint->state = UDP_ENDPOINT_DISABLED; - } -} - -//------------------------------------------------------------------------------ -/// Disable all endpoints (except control endpoint 0), aborting current -/// transfers if necessary -//------------------------------------------------------------------------------ -static void UDP_DisableEndpoints( void ) - -{ - unsigned char bEndpoint; - - // Disable each endpoint, terminating any pending transfer - // Control endpoint 0 is not disabled - for (bEndpoint = 1; bEndpoint < CHIP_USB_NUMENDPOINTS; bEndpoint++) { - - UDP_EndOfTransfer(bEndpoint, USBD_STATUS_ABORTED); - endpoints[bEndpoint].state = UDP_ENDPOINT_DISABLED; - } -} - -//------------------------------------------------------------------------------ -/// Checks if an ongoing transfer on an endpoint has been completed. -/// \param bEndpoint Endpoint number. -/// \return 1 if the current transfer on the given endpoint is complete; -/// otherwise 0. -//------------------------------------------------------------------------------ -static unsigned char UDP_IsTransferFinished(unsigned char bEndpoint) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); - - // Check if it is a Control endpoint - // -> Control endpoint must always finish their transfer with a zero-length - // packet - if ((UDP->UDP_CSR[bEndpoint] & UDP_CSR_EPTYPE_Msk) - == UDP_CSR_EPTYPE_CTRL) { - - return (pTransfer->buffered < pEndpoint->size); - } - // Other endpoints only need to transfer all the data - else { - - return (pTransfer->buffered <= pEndpoint->size) - && (pTransfer->remaining == 0); - } -} - -//------------------------------------------------------------------------------ -/// Endpoint interrupt handler. -/// Handle IN/OUT transfers, received SETUP packets and STALLing -/// \param bEndpoint Index of endpoint -//------------------------------------------------------------------------------ -static void UDP_EndpointHandler(unsigned char bEndpoint) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); - MblTransfer *pMblt = (MblTransfer*)&(pEndpoint->transfer); - unsigned int status = UDP->UDP_CSR[bEndpoint]; - unsigned short wPacketSize; - USBGenericRequest request; - - TRACE_DEBUG_WP("E%d ", bEndpoint); - TRACE_DEBUG_WP("st:0x%X ", status); - - // Handle interrupts - // IN packet sent - if ((status & UDP_CSR_TXCOMP) != 0) { - - TRACE_DEBUG_WP("Wr "); - - // Check that endpoint was in MBL Sending state - if (pEndpoint->state == UDP_ENDPOINT_SENDINGM) { - - USBDTransferBuffer * pMbli = pMblt->pLastLoaded; - unsigned char bufferEnd = 0; - - TRACE_DEBUG_WP("TxM%d.%d ", pMblt->allUsed, pMbli->buffered); - - // End of transfer ? - if (pMblt->allUsed && pMbli->buffered == 0) { - - pMbli->transferred += pMbli->buffered; - pMbli->buffered = 0; - - // Disable interrupt - UDP->UDP_IDR = 1 << bEndpoint; - UDP_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); - CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); - } - else { - - // Transfer remaining data - TRACE_DEBUG_WP("%d ", pEndpoint->size); - - if (pMbli->buffered > pEndpoint->size) { - pMbli->transferred += pEndpoint->size; - pMbli->buffered -= pEndpoint->size; - } - else { - pMbli->transferred += pMbli->buffered; - pMbli->buffered = 0; - } - - // Send next packet - if (CHIP_USB_ENDPOINTS_BANKS(bEndpoint) == 1) { - - // No double buffering - bufferEnd = UDP_MblWriteFifo(bEndpoint); - SET_CSR(bEndpoint, UDP_CSR_TXPKTRDY); - CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); - } - else { - // Double buffering - SET_CSR(bEndpoint, UDP_CSR_TXPKTRDY); - CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); - bufferEnd = UDP_MblWriteFifo(bEndpoint); - } - - if (bufferEnd && pMblt->fCallback) { - ((MblTransferCallback) pTransfer->fCallback) - (pTransfer->pArgument, - USBD_STATUS_PARTIAL_DONE, - 1); - } - } - } - // Check that endpoint was in Sending state - else if (pEndpoint->state == UDP_ENDPOINT_SENDING) { - - // End of transfer ? - if (UDP_IsTransferFinished(bEndpoint)) { - - pTransfer->transferred += pTransfer->buffered; - pTransfer->buffered = 0; - - // Disable interrupt if this is not a control endpoint - if ((status & UDP_CSR_EPTYPE_Msk) != UDP_CSR_EPTYPE_CTRL) { - - UDP->UDP_IDR = 1 << bEndpoint; - } - - UDP_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); - CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); - } - else { - - // Transfer remaining data - TRACE_DEBUG_WP(" %d ", pEndpoint->size); - - pTransfer->transferred += pEndpoint->size; - pTransfer->buffered -= pEndpoint->size; - - // Send next packet - if (CHIP_USB_ENDPOINTS_BANKS(bEndpoint) == 1) { - - // No double buffering - UDP_WritePayload(bEndpoint); - SET_CSR(bEndpoint, UDP_CSR_TXPKTRDY); - CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); - } - else { - // Double buffering - SET_CSR(bEndpoint, UDP_CSR_TXPKTRDY); - CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); - UDP_WritePayload(bEndpoint); - } - } - } - else { - // Acknowledge interrupt - TRACE_ERROR("Error Wr"); - CLEAR_CSR(bEndpoint, UDP_CSR_TXCOMP); - } - } - - // OUT packet received - if ((status & UDP_CSR_RXDATA_BK) != 0) { - - TRACE_DEBUG_WP("Rd "); - - // Check that the endpoint is in Receiving state - if (pEndpoint->state != UDP_ENDPOINT_RECEIVING) { - - // Check if an ACK has been received on a Control endpoint - if (((status & UDP_CSR_EPTYPE_Msk) == UDP_CSR_EPTYPE_CTRL) - && ((status & UDP_CSR_RXBYTECNT_Msk) == 0)) { - - // Acknowledge the data and finish the current transfer - UDP_ClearRxFlag(bEndpoint); - UDP_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); - } - // Check if the data has been STALLed - else if ((status & UDP_CSR_FORCESTALL) != 0) { - - // Discard STALLed data - TRACE_DEBUG_WP("Discard "); - UDP_ClearRxFlag(bEndpoint); - } - // NAK the data - else { - - TRACE_DEBUG_WP("Nak "); - UDP->UDP_IDR = 1 << bEndpoint; - } - } - // Endpoint is in Read state - else { - - // Retrieve data and store it into the current transfer buffer - wPacketSize = (unsigned short) (status >> 16); - TRACE_DEBUG_WP("%d ", wPacketSize); - UDP_ReadPayload(bEndpoint, wPacketSize); - UDP_ClearRxFlag(bEndpoint); - - // Check if the transfer is finished - if ((pTransfer->remaining == 0) || (wPacketSize < pEndpoint->size)) { - - // Disable interrupt if this is not a control endpoint - if ((status & UDP_CSR_EPTYPE_Msk) != UDP_CSR_EPTYPE_CTRL) { - - UDP->UDP_IDR = 1 << bEndpoint; - } - UDP_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); - } - } - } - - // STALL sent - if ((status & UDP_CSR_STALLSENTISOERROR) != 0) { - - TRACE_WARNING( "Sta 0x%X [%d] ", status, bEndpoint); - - // If the endpoint is not halted, clear the STALL condition - CLEAR_CSR(bEndpoint, UDP_CSR_STALLSENTISOERROR); - if (pEndpoint->state != UDP_ENDPOINT_HALTED) { - - TRACE_WARNING( "_ " ); - CLEAR_CSR(bEndpoint, UDP_CSR_FORCESTALL); - } - } - - // SETUP packet received - if ((status & UDP_CSR_RXSETUP) != 0) { - - TRACE_DEBUG_WP("Stp "); - - // If a transfer was pending, complete it - // Handles the case where during the status phase of a control write - // transfer, the host receives the device ZLP and ack it, but the ack - // is not received by the device - if ((pEndpoint->state == UDP_ENDPOINT_RECEIVING) - || (pEndpoint->state == UDP_ENDPOINT_SENDING)) { - - UDP_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); - } - // Copy the setup packet - UDP_ReadRequest(&request); - - // Set the DIR bit before clearing RXSETUP in Control IN sequence - if (USBGenericRequest_GetDirection(&request) == USBGenericRequest_IN) { - - SET_CSR(bEndpoint, UDP_CSR_DIR); - } - // Acknowledge setup packet - CLEAR_CSR(bEndpoint, UDP_CSR_RXSETUP); - - // Forward the request to the upper layer - USBDCallbacks_RequestReceived(&request); - } - -} - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -/// USB device interrupt handler -/// Manages device resume, suspend, end of bus reset. -/// Forwards endpoint interrupts to the appropriate handler. -//------------------------------------------------------------------------------ -void USBD_IrqHandler(void) -{ - unsigned int status; - int eptnum = 0; - - // Get interrupt status - // Some interrupts may get masked depending on the device state - status = UDP->UDP_ISR; - status &= UDP->UDP_IMR; - - if (deviceState < USBD_STATE_POWERED) { - - status &= UDP_ICR_WAKEUP | UDP_ICR_RXRSM; - UDP->UDP_ICR = ~status; - } - - // Return immediately if there is no interrupt to service - if (status == 0) { - - TRACE_DEBUG_WP(".\n\r"); - return; - } - - // Toggle USB LED if the device is active - if (deviceState >= USBD_STATE_POWERED) { - - // LED_Set(USBD_LEDUSB); - } - - // Service interrupts - - //// Start Of Frame (SOF) - //if (ISSET(dStatus, UDP_ISR_SOFINT)) { - // - // TRACE_DEBUG("SOF"); - // - // // Invoke the SOF callback - // USB_StartOfFrameCallback(pUsb); - // - // // Acknowledge interrupt - // UDP->UDP_ICR = UDP_ICR_SOFINT; - // dStatus &= ~UDP_ISR_SOFINT; - //} - - // Suspend - // This interrupt is always treated last (hence the '==') - if (status == UDP_ISR_RXSUSP) { - - TRACE_INFO_WP("Susp "); - - // Don't do anything if the device is already suspended - if (deviceState != USBD_STATE_SUSPENDED) { - - // The device enters the Suspended state - // Enable wakeup - UDP->UDP_IER = UDP_IER_WAKEUP | UDP_IER_RXRSM; - - // Acknowledge interrupt - UDP->UDP_ICR = UDP_ICR_RXSUSP; - - // Switch to the Suspended state - previousDeviceState = deviceState; - deviceState = USBD_STATE_SUSPENDED; - // Invoke the Suspended callback - USBDCallbacks_Suspended(); - UDP_DisableTransceiver(); - UDP_DisablePeripheralClock(); - UDP_DisableUsbClock(); - } - } - // Resume - else if ((status & (UDP_ISR_WAKEUP | UDP_ISR_RXRSM)) != 0) { - - TRACE_INFO_WP("Res "); - - // Don't do anything if the device was not suspended - if (deviceState == USBD_STATE_SUSPENDED) { - - // The device enters its previous state - UDP_EnablePeripheralClock(); - UDP_EnableUsbClock(); - - // Enable the transceiver if the device was past the Default - // state - deviceState = previousDeviceState; - if (deviceState >= USBD_STATE_DEFAULT) { - - UDP_EnableTransceiver(); - - // Invoke the Resume callback - USBDCallbacks_Resumed(); - } - } - - // Clear and disable resume interrupts - UDP->UDP_ICR = UDP_ICR_WAKEUP | UDP_ICR_RXRSM | UDP_ICR_RXSUSP; - UDP->UDP_IDR = UDP_IDR_WAKEUP | UDP_IDR_RXRSM; - } - // End of bus reset - else if ((status & UDP_ISR_ENDBUSRES) != 0) { - - TRACE_INFO_WP("EoBRes "); - - // The device enters the Default state - deviceState = USBD_STATE_DEFAULT; - UDP_EnableTransceiver(); - UDP_ResetEndpoints(); - UDP_DisableEndpoints(); - USBD_ConfigureEndpoint(0); - - // Flush and enable the Suspend interrupt - UDP->UDP_ICR = UDP_ICR_WAKEUP | UDP_ICR_RXRSM | UDP_ICR_RXSUSP; - UDP->UDP_IER = UDP_IER_RXSUSP; - - //// Enable the Start Of Frame (SOF) interrupt if needed - //if (pUsb->pCallbacks->startOfFrame != 0) { - // - // UDP->UDP_IER = UDP_IER_SOFINT; - //} - - // Invoke the Reset callback - USBDCallbacks_Reset(); - - // Acknowledge end of bus reset interrupt - UDP->UDP_ICR = UDP_ICR_ENDBUSRES; - } - // Endpoint interrupts - else { - - while (status != 0) { - - // Check if endpoint has a pending interrupt - if ((status & (1 << eptnum)) != 0) { - - UDP_EndpointHandler(eptnum); - status &= ~(1 << eptnum); - - if (status != 0) { - - TRACE_INFO_WP("\n\r - "); - } - } - eptnum++; - } - } - - // Toggle LED back to its previous state - TRACE_DEBUG_WP("!"); - TRACE_INFO_WP("\n\r"); - if (deviceState >= USBD_STATE_POWERED) { - - // LED_Clear(USBD_LEDUSB); - } -} - -//------------------------------------------------------------------------------ -/// Configures an endpoint according to its Endpoint Descriptor. -/// \param pDescriptor Pointer to an Endpoint descriptor. -//------------------------------------------------------------------------------ -void USBD_ConfigureEndpoint(const USBEndpointDescriptor *pDescriptor) -{ - Endpoint *pEndpoint; - unsigned char bEndpoint; - unsigned char bType; - unsigned char bEndpointDir; - - // NULL descriptor -> Control endpoint 0 - if (pDescriptor == 0) { - - bEndpoint = 0; - pEndpoint = &(endpoints[bEndpoint]); - bType= USBEndpointDescriptor_CONTROL; - bEndpointDir = 0; - pEndpoint->size = CHIP_USB_ENDPOINTS_MAXPACKETSIZE(0); - } - else { - - bEndpoint = USBEndpointDescriptor_GetNumber(pDescriptor); - pEndpoint = &(endpoints[bEndpoint]); - bType = USBEndpointDescriptor_GetType(pDescriptor); - bEndpointDir = USBEndpointDescriptor_GetDirection(pDescriptor); - pEndpoint->size = USBEndpointDescriptor_GetMaxPacketSize(pDescriptor); - } - - // Abort the current transfer is the endpoint was configured and in - // Write or Read state - if ((pEndpoint->state == UDP_ENDPOINT_RECEIVING) - || (pEndpoint->state == UDP_ENDPOINT_SENDING) - || (pEndpoint->state == UDP_ENDPOINT_RECEIVINGM) - || (pEndpoint->state == UDP_ENDPOINT_SENDINGM)) { - - UDP_EndOfTransfer(bEndpoint, USBD_STATUS_RESET); - } - pEndpoint->state = UDP_ENDPOINT_IDLE; - - // Reset Endpoint Fifos - UDP->UDP_RST_EP |= (1 << bEndpoint); - UDP->UDP_RST_EP &= ~(1 << bEndpoint); - - // Configure endpoint - SET_CSR(bEndpoint, (unsigned int)UDP_CSR_EPEDS - | (bType << 8) | (bEndpointDir << 10)); - if (bType != USBEndpointDescriptor_CONTROL) { - - } - else { - - UDP->UDP_IER = (1 << bEndpoint); - } - - TRACE_INFO_WP("CfgEpt%d ", bEndpoint); -} - -//------------------------------------------------------------------------------ -/// Sends data through a USB endpoint. Sets up the transfer descriptor, -/// writes one or two data payloads (depending on the number of FIFO bank -/// for the endpoint) and then starts the actual transfer. The operation is -/// complete when all the data has been sent. -/// -/// *If the size of the buffer is greater than the size of the endpoint -/// (or twice the size if the endpoint has two FIFO banks), then the buffer -/// must be kept allocated until the transfer is finished*. This means that -/// it is not possible to declare it on the stack (i.e. as a local variable -/// of a function which returns after starting a transfer). -/// -/// \param bEndpoint Endpoint number. -/// \param pData Pointer to a buffer with the data to send. -/// \param dLength Size of the data buffer. -/// \param fCallback Optional callback function to invoke when the transfer is -/// complete. -/// \param pArgument Optional argument to the callback function. -/// \return USBD_STATUS_SUCCESS if the transfer has been started; -/// otherwise, the corresponding error status code. -//------------------------------------------------------------------------------ -char USBD_Write( unsigned char bEndpoint, - const void *pData, - unsigned int dLength, - TransferCallback fCallback, - void *pArgument ) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); - - // Check that the endpoint is in Idle state - if (pEndpoint->state != UDP_ENDPOINT_IDLE) { - - return USBD_STATUS_LOCKED; - } - TRACE_DEBUG_WP("Write%d(%d) ", bEndpoint, dLength); - - // Setup the transfer descriptor - pTransfer->pData = (void *) pData; - pTransfer->remaining = dLength; - pTransfer->buffered = 0; - pTransfer->transferred = 0; - pTransfer->fCallback = fCallback; - pTransfer->pArgument = pArgument; - - // Send the first packet - pEndpoint->state = UDP_ENDPOINT_SENDING; - while((UDP->UDP_CSR[bEndpoint]&UDP_CSR_TXPKTRDY)==UDP_CSR_TXPKTRDY); - UDP_WritePayload(bEndpoint); - SET_CSR(bEndpoint, UDP_CSR_TXPKTRDY); - - // If double buffering is enabled and there is data remaining, - // prepare another packet - if ((CHIP_USB_ENDPOINTS_BANKS(bEndpoint) > 1) && (pTransfer->remaining > 0)) { - - UDP_WritePayload(bEndpoint); - } - - // Enable interrupt on endpoint - UDP->UDP_IER = 1 << bEndpoint; - - return USBD_STATUS_SUCCESS; -} - -//------------------------------------------------------------------------------ -/// Sends data frames through a USB endpoint. Sets up the transfer descriptor -/// list, writes one or two data payloads (depending on the number of FIFO bank -/// for the endpoint) and then starts the actual transfer. The operation is -/// complete when all the data has been sent. -/// -/// *If the size of the frame is greater than the size of the endpoint -/// (or twice the size if the endpoint has two FIFO banks), then the buffer -/// must be kept allocated until the frame is finished*. This means that -/// it is not possible to declare it on the stack (i.e. as a local variable -/// of a function which returns after starting a transfer). -/// -/// \param bEndpoint Endpoint number. -/// \param pMbl Pointer to a frame (USBDTransferBuffer) list that describes -/// the buffer list to send. -/// \param wListSize Size of the frame list. -/// \param bCircList Circle the list. -/// \param wStartNdx For circled list only, the first buffer index to transfer. -/// \param fCallback Optional callback function to invoke when the transfer is -/// complete. -/// \param pArgument Optional argument to the callback function. -/// \return USBD_STATUS_SUCCESS if the transfer has been started; -/// otherwise, the corresponding error status code. -/// \see USBDTransferBuffer, MblTransferCallback, USBD_MblReuse -//------------------------------------------------------------------------------ -char USBD_MblWrite( unsigned char bEndpoint, - void *pMbl, - unsigned short wListSize, - unsigned char bCircList, - unsigned short wStartNdx, - MblTransferCallback fCallback, - void *pArgument ) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - MblTransfer *pTransfer = (MblTransfer*)&(pEndpoint->transfer); - unsigned short i; - - // EP0 is not suitable for Mbl - if (bEndpoint == 0) { - - return USBD_STATUS_INVALID_PARAMETER; - } - - // Check that the endpoint is in Idle state - if (pEndpoint->state != UDP_ENDPOINT_IDLE) { - - return USBD_STATUS_LOCKED; - } - pEndpoint->state = UDP_ENDPOINT_SENDINGM; - - TRACE_DEBUG_WP("WriteM%d(0x%x,%d) ", bEndpoint, pMbl, wListSize); - - // Start from first if not circled list - if (!bCircList) wStartNdx = 0; - - // Setup the transfer descriptor - pTransfer->pMbl = (USBDTransferBuffer*)pMbl; - pTransfer->listSize = wListSize; - pTransfer->fCallback = fCallback; - pTransfer->pArgument = pArgument; - pTransfer->currBuffer = wStartNdx; - pTransfer->freedBuffer = 0; - pTransfer->pLastLoaded = &(((USBDTransferBuffer*)pMbl)[wStartNdx]); - pTransfer->circList = bCircList; - pTransfer->allUsed = 0; - - // Clear all buffer - for (i = 0; i < wListSize; i ++) { - - pTransfer->pMbl[i].transferred = 0; - pTransfer->pMbl[i].buffered = 0; - pTransfer->pMbl[i].remaining = pTransfer->pMbl[i].size; - } - - // Send the first packet - while((UDP->UDP_CSR[bEndpoint]&UDP_CSR_TXPKTRDY)==UDP_CSR_TXPKTRDY); - UDP_MblWriteFifo(bEndpoint); - SET_CSR(bEndpoint, UDP_CSR_TXPKTRDY); - - // If double buffering is enabled and there is data remaining, - // prepare another packet - if ((CHIP_USB_ENDPOINTS_BANKS(bEndpoint) > 1) - && (pTransfer->pMbl[pTransfer->currBuffer].remaining > 0)) { - - UDP_MblWriteFifo(bEndpoint); - } - - // Enable interrupt on endpoint - UDP->UDP_IER = 1 << bEndpoint; - - return USBD_STATUS_SUCCESS; -} - -//------------------------------------------------------------------------------ -/// Reads incoming data on an USB endpoint This methods sets the transfer -/// descriptor and activate the endpoint interrupt. The actual transfer is -/// then carried out by the endpoint interrupt handler. The Read operation -/// finishes either when the buffer is full, or a short packet (inferior to -/// endpoint maximum size) is received. -/// -/// *The buffer must be kept allocated until the transfer is finished*. -/// \param bEndpoint Endpoint number. -/// \param pData Pointer to a data buffer. -/// \param dLength Size of the data buffer in bytes. -/// \param fCallback Optional end-of-transfer callback function. -/// \param pArgument Optional argument to the callback function. -/// \return USBD_STATUS_SUCCESS if the read operation has been started; -/// otherwise, the corresponding error code. -//------------------------------------------------------------------------------ -char USBD_Read(unsigned char bEndpoint, - void *pData, - unsigned int dLength, - TransferCallback fCallback, - void *pArgument) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); - - // Return if the endpoint is not in IDLE state - if (pEndpoint->state != UDP_ENDPOINT_IDLE) { - - return USBD_STATUS_LOCKED; - } - - // Endpoint enters Receiving state - pEndpoint->state = UDP_ENDPOINT_RECEIVING; - TRACE_DEBUG_WP("Read%d(%d) ", bEndpoint, dLength); - - // Set the transfer descriptor - pTransfer->pData = pData; - pTransfer->remaining = dLength; - pTransfer->buffered = 0; - pTransfer->transferred = 0; - pTransfer->fCallback = fCallback; - pTransfer->pArgument = pArgument; - - // Enable interrupt on endpoint - UDP->UDP_IER = 1 << bEndpoint; - - return USBD_STATUS_SUCCESS; -} - -//------------------------------------------------------------------------------ -/// Reuse first used/released buffer with new buffer address and size to be used -/// in transfer again. Only valid when frame list is ringed. Can be used for -/// both read & write. -/// \param bEndpoint Endpoint number. -/// \param pNewBuffer Pointer to new buffer with data to send (0 to keep last). -/// \param wNewSize Size of the data buffer -//------------------------------------------------------------------------------ -char USBD_MblReuse( unsigned char bEndpoint, - unsigned char *pNewBuffer, - unsigned short wNewSize ) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - MblTransfer *pTransfer = (MblTransfer*)&(pEndpoint->transfer); - USBDTransferBuffer *pBi = &(pTransfer->pMbl[pTransfer->freedBuffer]); - - TRACE_DEBUG_WP("MblReuse(%d), st%x, circ%d\n\r", - bEndpoint, pEndpoint->state, pTransfer->circList); - - // Only for Multi-buffer-circle list - if (bEndpoint != 0 - && (pEndpoint->state == UDP_ENDPOINT_RECEIVINGM - || pEndpoint->state == UDP_ENDPOINT_SENDINGM) - && pTransfer->circList) { - } - else { - - return USBD_STATUS_WRONG_STATE; - } - - // Check if there is freed buffer - if (pTransfer->freedBuffer == pTransfer->currBuffer - && !pTransfer->allUsed) { - - return USBD_STATUS_LOCKED; - } - - // Update transfer information - if ((++ pTransfer->freedBuffer) == pTransfer->listSize) - pTransfer->freedBuffer = 0; - if (pNewBuffer) { - pBi->pBuffer = pNewBuffer; - pBi->size = wNewSize; - } - pBi->buffered = 0; - pBi->transferred = 0; - pBi->remaining = pBi->size; - - // At least one buffer is not processed - pTransfer->allUsed = 0; - return USBD_STATUS_SUCCESS; -} - -//------------------------------------------------------------------------------ -/// Sets the HALT feature on the given endpoint (if not already in this state). -/// \param bEndpoint Endpoint number. -//------------------------------------------------------------------------------ -void USBD_Halt(unsigned char bEndpoint) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - - // Check that endpoint is enabled and not already in Halt state - if ((pEndpoint->state != UDP_ENDPOINT_DISABLED) - && (pEndpoint->state != UDP_ENDPOINT_HALTED)) { - - TRACE_DEBUG_WP("Halt%d ", bEndpoint); - - // Abort the current transfer if necessary - UDP_EndOfTransfer(bEndpoint, USBD_STATUS_ABORTED); - - // Put endpoint into Halt state - SET_CSR(bEndpoint, UDP_CSR_FORCESTALL); - pEndpoint->state = UDP_ENDPOINT_HALTED; - - // Enable the endpoint interrupt - UDP->UDP_IER = 1 << bEndpoint; - } -} - -//------------------------------------------------------------------------------ -/// Clears the Halt feature on the given endpoint. -/// \param bEndpoint Index of endpoint -//------------------------------------------------------------------------------ -void USBD_Unhalt(unsigned char bEndpoint) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - - // Check if the endpoint is enabled - if (pEndpoint->state != UDP_ENDPOINT_DISABLED) { - - TRACE_DEBUG_WP("Unhalt%d ", bEndpoint); - - // Return endpoint to Idle state - pEndpoint->state = UDP_ENDPOINT_IDLE; - - // Clear FORCESTALL flag - CLEAR_CSR(bEndpoint, UDP_CSR_FORCESTALL); - - // Reset Endpoint Fifos, beware this is a 2 steps operation - UDP->UDP_RST_EP |= 1 << bEndpoint; - UDP->UDP_RST_EP &= ~(1 << bEndpoint); - } -} - -//------------------------------------------------------------------------------ -/// Returns the current Halt status of an endpoint. -/// \param bEndpoint Index of endpoint -/// \return 1 if the endpoint is currently halted; otherwise 0 -//------------------------------------------------------------------------------ -unsigned char USBD_IsHalted(unsigned char bEndpoint) -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - unsigned char status = 0; - - if (pEndpoint->state == UDP_ENDPOINT_HALTED) { - - status = 1; - } - return( status ); -} - -//------------------------------------------------------------------------------ -/// Indicates if the device is running in high or full-speed. Always returns 0 -/// since UDP does not support high-speed mode. -//------------------------------------------------------------------------------ -unsigned char USBD_IsHighSpeed(void) -{ - return 0; -} - -//------------------------------------------------------------------------------ -/// Causes the given endpoint to acknowledge the next packet it receives -/// with a STALL handshake. -/// \param bEndpoint Endpoint number. -/// \return USBD_STATUS_SUCCESS or USBD_STATUS_LOCKED. -//------------------------------------------------------------------------------ -unsigned char USBD_Stall(unsigned char bEndpoint) - -{ - Endpoint *pEndpoint = &(endpoints[bEndpoint]); - - // Check that endpoint is in Idle state - if (pEndpoint->state != UDP_ENDPOINT_IDLE) { - - TRACE_WARNING("UDP_Stall: Endpoint%d locked\n\r", bEndpoint); - return USBD_STATUS_LOCKED; - } - - TRACE_DEBUG_WP("Stall%d ", bEndpoint); - SET_CSR(bEndpoint, UDP_CSR_FORCESTALL); - - return USBD_STATUS_SUCCESS; -} - -//------------------------------------------------------------------------------ -/// Starts a remote wake-up procedure. -//------------------------------------------------------------------------------ -void USBD_RemoteWakeUp(void) -{ - // Device is NOT suspended - if (deviceState != USBD_STATE_SUSPENDED) { - - TRACE_WARNING("USBD_RemoteWakeUp: Device is not suspended\n\r"); - return; - } - - - UDP_EnablePeripheralClock(); - UDP_EnableUsbClock(); - UDP_EnableTransceiver(); - - TRACE_INFO_WP("RWUp "); - - // Activates a remote wakeup (edge on ESR), then clear ESR - UDP->UDP_GLB_STAT |= UDP_GLB_STAT_ESR; - UDP->UDP_GLB_STAT &= ~UDP_GLB_STAT_ESR; -} - -//------------------------------------------------------------------------------ -/// Sets the device address to the given value. -/// \param address New device address. -//------------------------------------------------------------------------------ -void USBD_SetAddress(unsigned char address) -{ - TRACE_INFO_WP("SetAddr(%d) ", address); - - // Set address - UDP->UDP_FADDR = UDP_FADDR_FEN | (address & UDP_FADDR_FADD_Msk); - - // If the address is 0, the device returns to the Default state - if (address == 0) { - - UDP->UDP_GLB_STAT = 0; - deviceState = USBD_STATE_DEFAULT; - } - // If the address is non-zero, the device enters the Address state - else { - - UDP->UDP_GLB_STAT = UDP_GLB_STAT_FADDEN; - deviceState = USBD_STATE_ADDRESS; - } -} - -//------------------------------------------------------------------------------ -/// Sets the current device configuration. -/// \param cfgnum - Configuration number to set. -//------------------------------------------------------------------------------ -void USBD_SetConfiguration(unsigned char cfgnum) -{ - TRACE_INFO_WP("SetCfg(%d) ", cfgnum); - - // If the configuration number if non-zero, the device enters the - // Configured state - if (cfgnum != 0) { - - // Enter Configured state - deviceState = USBD_STATE_CONFIGURED; - UDP->UDP_GLB_STAT |= UDP_GLB_STAT_CONFG; - } - // If the configuration number is zero, the device goes back to the Address - // state - else { - - deviceState = USBD_STATE_ADDRESS; - UDP->UDP_GLB_STAT = UDP_FADDR_FEN; - - // Abort all transfers - UDP_DisableEndpoints(); - } -} - -//------------------------------------------------------------------------------ -/// Connects the pull-up on the D+ line of the USB. -//------------------------------------------------------------------------------ -void USBD_Connect(void) -{ - unsigned char dis = UDP_EnablePeripheralClock(); - - TRACE_DEBUG("Conn "); - UDP->UDP_TXVC |= UDP_TXVC_PUON; - - if (dis) UDP_DisablePeripheralClock(); -} - -//------------------------------------------------------------------------------ -/// Disconnects the pull-up from the D+ line of the USB. -//------------------------------------------------------------------------------ -void USBD_Disconnect(void) -{ - unsigned char dis = UDP_EnablePeripheralClock(); - - TRACE_DEBUG("Disc "); - UDP->UDP_TXVC &= ~UDP_TXVC_PUON; - - if (dis) UDP_DisablePeripheralClock(); - - // Device returns to the Powered state - if (deviceState > USBD_STATE_POWERED) { - - deviceState = USBD_STATE_POWERED; - } - - if (previousDeviceState > USBD_STATE_POWERED) { - - previousDeviceState = USBD_STATE_POWERED; - } -} - -//------------------------------------------------------------------------------ -/// Initializes the USB driver. -//------------------------------------------------------------------------------ -void USBD_Init(void) -{ - TRACE_INFO_WP("USBD_Init\n\r"); - - // Reset endpoint structures - UDP_ResetEndpoints(); - - // Must before TXVC access! - UDP_EnablePeripheralClock(); - - // Configure the pull-up on D+ and disconnect it - UDP->UDP_TXVC &= ~UDP_TXVC_PUON; - - // Device is in the Attached state - deviceState = USBD_STATE_SUSPENDED; - previousDeviceState = USBD_STATE_POWERED; - UDP_EnableUsbClock(); - - UDP->UDP_IDR = 0xFE; - - UDP->UDP_IER = UDP_IER_WAKEUP; - - // Configure interrupts - NVIC_EnableIRQ(UDP_IRQn); -} - -//------------------------------------------------------------------------------ -/// Configure USB Speed, should be invoked before USB attachment. -/// \param forceFS Force to use FS mode. -//------------------------------------------------------------------------------ -void USBD_ConfigureSpeed(unsigned char forceFS) -{ -} - -//------------------------------------------------------------------------------ -/// Returns the current state of the USB device. -/// \return Device current state. -//------------------------------------------------------------------------------ -unsigned char USBD_GetState(void) -{ - return deviceState; -} - diff --git a/radio/src/targets/sky9x/usb/device/hid-joystick/HIDDJoystickDriver.c b/radio/src/targets/sky9x/usb/device/hid-joystick/HIDDJoystickDriver.c deleted file mode 100644 index 48d2fecd2..000000000 --- a/radio/src/targets/sky9x/usb/device/hid-joystick/HIDDJoystickDriver.c +++ /dev/null @@ -1,356 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "HIDDJoystickDriver.h" -#include "HIDDJoystickDriverDescriptors.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define TRACE_INFO(...) { } -#define TRACE_WARNING(...) { } - -//------------------------------------------------------------------------------ -/// Driver structure for an HID device implementing joystick functionalities. -//------------------------------------------------------------------------------ -typedef struct { - - /// Standard USB device driver instance. - USBDDriver usbdDriver; - /// Idle rate (in milliseconds) of the input report. - unsigned char inputReportIdleRate; - /// - unsigned char inputProtocol; - /// Input report instance. - HIDDJoystickInputReport inputReport; - -} HIDDJoystickDriver; - -//------------------------------------------------------------------------------ -// Internal variables -//------------------------------------------------------------------------------ - -/// Static instance of the HID joystick device driver. -static HIDDJoystickDriver hiddJoystickDriver; - -//------------------------------------------------------------------------------ -// Internal functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Returns the descriptor requested by the host. -/// \param type Descriptor type. -/// \param length Maximum number of bytes to send. -/// \return 1 if the request has been handled by this function, otherwise 0. -//------------------------------------------------------------------------------ -static unsigned char HIDDJoystickDriver_GetDescriptor(unsigned char type, - unsigned char length) -{ - extern int hiddReportDescriptorSize; - - const USBConfigurationDescriptor *pConfiguration; - HIDDescriptor *hidDescriptor; - - switch (type) { - - case HIDGenericDescriptor_REPORT: - TRACE_INFO("Report "); - - // Adjust length and send report descriptor - if (length > hiddReportDescriptorSize) { - - length = hiddReportDescriptorSize; - } - USBD_Write(0, &hiddReportDescriptor, length, 0, 0); - break; - - case HIDGenericDescriptor_HID: - TRACE_INFO("HID "); - - // Configuration descriptor is different depending on configuration - if (USBD_IsHighSpeed()) { - - pConfiguration = - hiddJoystickDriver.usbdDriver.pDescriptors->pHsConfiguration; - } - else { - - pConfiguration = - hiddJoystickDriver.usbdDriver.pDescriptors->pFsConfiguration; - } - - // Parse the device configuration to get the HID descriptor - USBConfigurationDescriptor_Parse(pConfiguration, 0, 0, - (USBGenericDescriptor **) &hidDescriptor); - - // Adjust length and send HID descriptor - if (length > sizeof(HIDDescriptor)) { - - length = sizeof(HIDDescriptor); - } - USBD_Write(0, hidDescriptor, length, 0, 0); - break; - - default: - return 0; - } - - return 1; -} - -//------------------------------------------------------------------------------ -/// Sends the current Idle rate of the input report to the host. -//------------------------------------------------------------------------------ -static void HIDDJoystickDriver_GetIdle() -{ - TRACE_INFO("gIdle "); - - USBD_Write(0, &(hiddJoystickDriver.inputReportIdleRate), 1, 0, 0); -} - -//------------------------------------------------------------------------------ -/// Retrieves the new idle rate of the input report from the USB host. -/// \param idleRate New input report idle rate. -//------------------------------------------------------------------------------ -static void HIDDJoystickDriver_SetIdle(unsigned char idleRate) -{ - TRACE_INFO("sIdle(%d) ", idleRate); - - hiddJoystickDriver.inputReportIdleRate = idleRate; - USBD_Write(0, 0, 0, 0, 0); -} - -//------------------------------------------------------------------------------ -/// Sends the requested report to the host. -/// \param type Report type. -/// \param length Maximum number of bytes to send. -//------------------------------------------------------------------------------ -static void HIDDJoystickDriver_GetReport(unsigned char type, - unsigned short length) -{ - TRACE_INFO("gReport "); - - // Check report type - switch (type) { - - case HIDReportRequest_INPUT: - TRACE_INFO("In "); - - // Adjust size and send report - if (length > sizeof(HIDDJoystickInputReport)) { - - length = sizeof(HIDDJoystickInputReport); - } - USBD_Write(0, // Endpoint #0 - &(hiddJoystickDriver.inputReport), - length, - 0, // No callback - 0); - break; - - default: - USBD_Stall(0); - } -} - -//------------------------------------------------------------------------------ -/// Retrieves the new value of a report from the host and saves it. -/// \param type Report type. -/// \param length Report length. -//------------------------------------------------------------------------------ -static void HIDDJoystickDriver_SetReport(unsigned char type, - unsigned short length) -{ - TRACE_INFO("sReport "); - - // Check report type - switch (type) { - - case HIDReportRequest_INPUT: - // SET_REPORT requests on input reports are ignored - USBD_Stall(0); - break; - - default: - USBD_Stall(0); - } -} - -//------------------------------------------------------------------------------ -// Optional RequestReceived() callback re-implementation -//------------------------------------------------------------------------------ -#if !defined(NOAUTOCALLBACK) - -//------------------------------------------------------------------------------ -/// Callback function when new request receivce from host -/// \param request Pointer to the USBGenericRequest instance -//------------------------------------------------------------------------------ -//void USBDCallbacks_RequestReceived(const USBGenericRequest *request) -//{ -// HIDDJoystickDriver_RequestHandler(request); -//} - -#endif - -//------------------------------------------------------------------------------ -// ConfigurationChanged() callback re-implementation -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Callback function when configureation changed -/// \param cfgnum New configuration number -//------------------------------------------------------------------------------ -//void USBDDriverCallbacks_ConfigurationChanged(unsigned char cfgnum) -//{ -// (void)cfgnum; -//} - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Initializes the HID Joystick %device driver. -//------------------------------------------------------------------------------ -void HIDDJoystickDriver_Initialize() -{ - hiddJoystickDriver.inputReportIdleRate = 0; - HIDDJoystickInputReport_Initialize(&(hiddJoystickDriver.inputReport)); - USBDDriver_Initialize(&(hiddJoystickDriver.usbdDriver), - &hiddJoystickDriverDescriptors, - 0); // Multiple interface settings not supported - USBD_Init(); -} - -//------------------------------------------------------------------------------ -/// Handles HID-specific SETUP request sent by the host. -/// \param request Pointer to a USBGenericRequest instance -//------------------------------------------------------------------------------ -void HIDDJoystickDriver_RequestHandler(const USBGenericRequest *request) -{ - TRACE_INFO("NewReq "); - - // Check if this is a standard request - if (USBGenericRequest_GetType(request) == USBGenericRequest_STANDARD) { - - // This is a standard request - switch (USBGenericRequest_GetRequest(request)) { - - case USBGenericRequest_GETDESCRIPTOR: - // Check if this is a HID descriptor, otherwise forward it to - // the standard driver - if (!HIDDJoystickDriver_GetDescriptor( - USBGetDescriptorRequest_GetDescriptorType(request), - USBGenericRequest_GetLength(request))) { - - USBDDriver_RequestHandler(&(hiddJoystickDriver.usbdDriver), - request); - } - break; - - default: - USBDDriver_RequestHandler(&(hiddJoystickDriver.usbdDriver), - request); - } - } - // Check if this is a class request - else if (USBGenericRequest_GetType(request) == USBGenericRequest_CLASS) { - - // This is a class-specific request - switch (USBGenericRequest_GetRequest(request)) { - - case HIDGenericRequest_GETIDLE: - HIDDJoystickDriver_GetIdle(); - break; - - case HIDGenericRequest_SETIDLE: - HIDDJoystickDriver_SetIdle(HIDIdleRequest_GetIdleRate(request)); - break; - - case HIDGenericRequest_GETREPORT: - HIDDJoystickDriver_GetReport( - HIDReportRequest_GetReportType(request), - USBGenericRequest_GetLength(request)); - break; - - case HIDGenericRequest_SETREPORT: - HIDDJoystickDriver_SetReport( - HIDReportRequest_GetReportType(request), - USBGenericRequest_GetLength(request)); - break; - - case HIDGenericRequest_GETPROTOCOL: - USBD_Write(0, &hiddJoystickDriver.inputProtocol, 1, 0, 0); - break; - - case HIDGenericRequest_SETPROTOCOL: - hiddJoystickDriver.inputProtocol = request->wValue; - USBD_Write(0, 0, 0, 0, 0); - break; - - default: - TRACE_WARNING( - "HIDDJoystickDriver_RequestHandler: Unknown request 0x%02X\n\r", - USBGenericRequest_GetRequest(request)); - USBD_Stall(0); - } - } - else { - - // Vendor request ? - USBD_Stall(0); - } -} - -//------------------------------------------------------------------------------ -/// Update the Joystick state via input report -/// to host -/// \param report Pointer to a HIDDJoystickInputReport instance -//------------------------------------------------------------------------------ -unsigned char HIDDJoystickDriver_ChangeJoystickState(const HIDDJoystickInputReport *report) -{ - memcpy(&(hiddJoystickDriver.inputReport), report, sizeof(HIDDJoystickInputReport)); - - // Send input report through the interrupt IN endpoint - return USBD_Write(HIDDJoystickDriverDescriptors_INTERRUPTIN, - &(hiddJoystickDriver.inputReport), - sizeof(HIDDJoystickInputReport), - 0, - 0); -} diff --git a/radio/src/targets/sky9x/usb/device/hid-joystick/HIDDJoystickDriver.h b/radio/src/targets/sky9x/usb/device/hid-joystick/HIDDJoystickDriver.h deleted file mode 100644 index a4ed3bff2..000000000 --- a/radio/src/targets/sky9x/usb/device/hid-joystick/HIDDJoystickDriver.h +++ /dev/null @@ -1,83 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definition of methods for using a HID joystick device driver. - - !!!Usage - - -# Re-implement the USBDCallbacks_RequestReceived callback to forward - requests to HIDDJoystickDriver_RequestHandler. This is done - automatically unless the NOAUTOCALLBACK symbol is defined during - compilation. - -# Initialize the driver using HIDDJoystickDriver_Initialize. The - USB driver is automatically initialized by this method. - -# Call the HIDDJoystickDriver_ChangePoints method when one or more - keys are pressed/released. -*/ - -#ifndef HIDDJOYSTICKDRIVER_H -#define HIDDJOYSTICKDRIVER_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include -#include "HIDDJoystickInputReport.h" - -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -/* - Function: HIDDJoystickDriver_Initialize - Initializes the HID joystick device driver. -*/ -extern void HIDDJoystickDriver_Initialize(); - -/* - Function: HIDDJoystickDriver_RequestHandler - Handles HID-specific SETUP request sent by the host. - - Parameters: - request - Pointer to a USBGenericRequest instance. -*/ -extern void HIDDJoystickDriver_RequestHandler(const USBGenericRequest *request); - -extern unsigned char HIDDJoystickDriver_ChangeJoystickState(const HIDDJoystickInputReport *report); - -#endif //#ifndef HIDDJOYSTICKDRIVER_H - diff --git a/radio/src/targets/sky9x/usb/device/hid-joystick/HIDDJoystickDriverDescriptors.c b/radio/src/targets/sky9x/usb/device/hid-joystick/HIDDJoystickDriverDescriptors.c deleted file mode 100644 index 5de76b7e2..000000000 --- a/radio/src/targets/sky9x/usb/device/hid-joystick/HIDDJoystickDriverDescriptors.c +++ /dev/null @@ -1,297 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: HIDDJoystickDriverDescriptors - - About: Purpose - Declaration of the descriptors used by the HID device joystick driver. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "HIDDJoystickDriverDescriptors.h" -#include "HIDDJoystickInputReport.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "HID Joystick Device Descriptor IDs" -/// ... -/// -/// !IDs -/// - HIDDJoystickDriverDescriptors_PRODUCTID -/// - HIDDJoystickDriverDescriptors_VENDORID -/// - HIDDJoystickDriverDescriptors_RELEASE - -/// Device product ID. -#define HIDDJoystickDriverDescriptors_PRODUCTID 0x6200 -/// Device vendor ID. -#define HIDDJoystickDriverDescriptors_VENDORID 0x03EB -/// Device release number. -#define HIDDJoystickDriverDescriptors_RELEASE 0x0100 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Internal types -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// List of descriptors that make up the configuration descriptors of a -/// %device using the HID Joystick driver. -//------------------------------------------------------------------------------ -typedef struct { - - /// Configuration descriptor. - USBConfigurationDescriptor configuration; - /// Interface descriptor. - USBInterfaceDescriptor interface; - /// HID descriptor. - HIDDescriptor hid; - /// Interrupt IN endpoint descriptor. - USBEndpointDescriptor interruptIn; - -} __attribute__ ((packed)) HIDDJoystickDriverConfigurationDescriptors; - -//------------------------------------------------------------------------------ -// Internal variables -//------------------------------------------------------------------------------ - -#define BOARD_USB_ENDPOINTS_MAXPACKETSIZE(i) (((i == 0)||(i == 3)||(i == 4)) ? 64 :\ - (((i == 1) || (i == 2)) ? 512 : 1024)) - -/// Device descriptor. -static const USBDeviceDescriptor deviceDescriptor = { - - sizeof(USBDeviceDescriptor), - USBGenericDescriptor_DEVICE, - USBDeviceDescriptor_USB2_00, - HIDDeviceDescriptor_CLASS, - HIDDeviceDescriptor_SUBCLASS, - HIDDeviceDescriptor_PROTOCOL, - BOARD_USB_ENDPOINTS_MAXPACKETSIZE(0), - HIDDJoystickDriverDescriptors_VENDORID, - HIDDJoystickDriverDescriptors_PRODUCTID, - HIDDJoystickDriverDescriptors_RELEASE, - 1, // Index of manufacturer description - 2, // Index of product description - 3, // Index of serial number description - 1 // One possible configuration -}; - -/// Report descriptor used by the driver. -const unsigned char hiddReportDescriptor[] = { - - HIDReport_GLOBAL_USAGEPAGE + 1, HIDGenericDesktop_PAGEID, // USAGE_PAGE (Generic Desktop) - HIDReport_LOCAL_USAGE + 1, HIDGenericDesktop_GAMEPAD, // USAGE (Game Pad) - HIDReport_COLLECTION + 1, HIDReport_COLLECTION_APPLICATION, // COLLECTION (Application) - HIDReport_COLLECTION + 1, HIDReport_COLLECTION_PHYSICAL, // COLLECTION (Physical) - HIDReport_GLOBAL_USAGEPAGE + 1, HIDButton_PAGEID, // USAGE_PAGE (Button) - HIDReport_LOCAL_USAGEMINIMUM + 1, 1, // USAGE_MINIMUM (Button 1) - HIDReport_LOCAL_USAGEMAXIMUM + 1, 24, // USAGE_MAXIMUM (Button 24) - HIDReport_GLOBAL_LOGICALMINIMUM + 1, 0, // LOGICAL_MINIMUM (0) - HIDReport_GLOBAL_LOGICALMAXIMUM + 1, 1, // LOGICAL_MAXIMUM (1) - HIDReport_GLOBAL_REPORTCOUNT + 1, 24, // REPORT_COUNT (24) - HIDReport_GLOBAL_REPORTSIZE + 1, 1, // REPORT_SIZE (1) - HIDReport_INPUT + 1, HIDReport_VARIABLE, // INPUT (Data,Var,Abs) - HIDReport_GLOBAL_USAGEPAGE + 1, HIDGenericDesktop_PAGEID, // USAGE_PAGE (Generic Desktop) - HIDReport_LOCAL_USAGE + 1, HIDGenericDesktop_X_AXIS, // USAGE (X) - HIDReport_LOCAL_USAGE + 1, HIDGenericDesktop_Y_AXIS, // USAGE (Y) - HIDReport_LOCAL_USAGE + 1, HIDGenericDesktop_Z_AXIS, // USAGE (Z) - HIDReport_LOCAL_USAGE + 1, HIDGenericDesktop_X_ROTATION, // USAGE (Rx) - HIDReport_LOCAL_USAGE + 1, HIDGenericDesktop_Y_ROTATION, // USAGE (Ry) - HIDReport_LOCAL_USAGE + 1, HIDGenericDesktop_Z_ROTATION, // USAGE (Rz) - HIDReport_LOCAL_USAGE + 1, HIDGenericDesktop_SLIDER, // USAGE (Slider) - HIDReport_LOCAL_USAGE + 1, HIDGenericDesktop_SLIDER, // USAGE (Slider) - HIDReport_GLOBAL_LOGICALMINIMUM + 1, (unsigned char) -127, // LOGICAL_MINIMUM (-127) - HIDReport_GLOBAL_LOGICALMAXIMUM + 1, 127, // LOGICAL_MAXIMUM (127) - HIDReport_GLOBAL_REPORTSIZE + 1, 8, // REPORT_SIZE (8) - HIDReport_GLOBAL_REPORTCOUNT + 1, 8, // REPORT_COUNT (8) - HIDReport_INPUT + 1, HIDReport_VARIABLE, // INPUT (Data,Var,Abs) - HIDReport_ENDCOLLECTION, // END_COLLECTION - HIDReport_ENDCOLLECTION // END_COLLECTION -}; -int hiddReportDescriptorSize = sizeof(hiddReportDescriptor); - -/// Configuration descriptor. -static const HIDDJoystickDriverConfigurationDescriptors configurationDescriptors = { - - // Configuration descriptor - { - sizeof(USBConfigurationDescriptor), - USBGenericDescriptor_CONFIGURATION, - sizeof(HIDDJoystickDriverConfigurationDescriptors), - 1, // One interface in this configuration - 1, // This is configuration #1 - 0, // No associated string descriptor - BOARD_USB_BMATTRIBUTES, - USBConfigurationDescriptor_POWER(100) - }, - // Interface descriptor - { - sizeof(USBInterfaceDescriptor), - USBGenericDescriptor_INTERFACE, - 0, // This is interface #0 - 0, // This is alternate setting #0 - 1, // One endpoints used - HIDInterfaceDescriptor_CLASS, - HIDInterfaceDescriptor_SUBCLASS_NONE, - HIDInterfaceDescriptor_PROTOCOL_NONE, - 0 // No associated string descriptor - }, - // HID descriptor - { - sizeof(HIDDescriptor), - HIDGenericDescriptor_HID, - HIDDescriptor_HID1_11, - 0, // Device is not localized, no country code - 1, // One HID-specific descriptor (apart from this one) - HIDGenericDescriptor_REPORT, - sizeof(hiddReportDescriptor), - }, - // Interrupt IN endpoint descriptor - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, // 5 - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_IN, - HIDDJoystickDriverDescriptors_INTERRUPTIN), - USBEndpointDescriptor_INTERRUPT, - sizeof(HIDDJoystickInputReport), - HIDDJoystickDriverDescriptors_INTERRUPTIN_POLLING - } -}; - -/* - Variables: String descriptors - languageIdDescriptor - Language ID string descriptor. - manufacturerDescriptor - Manufacturer name. - productDescriptor - Product name. - serialNumberDescriptor - Product serial number. - stringDescriptors - Array of pointers to string descriptors. -*/ -static const unsigned char languageIdDescriptor[] = { - - USBStringDescriptor_LENGTH(1), - USBGenericDescriptor_STRING, - USBStringDescriptor_ENGLISH_US -}; - -static const unsigned char manufacturerDescriptor[] = { - - USBStringDescriptor_LENGTH(5), - USBGenericDescriptor_STRING, - USBStringDescriptor_UNICODE('A'), - USBStringDescriptor_UNICODE('T'), - USBStringDescriptor_UNICODE('M'), - USBStringDescriptor_UNICODE('E'), - USBStringDescriptor_UNICODE('L') -}; - -static const unsigned char productDescriptor[] = { - - USBStringDescriptor_LENGTH(14), - USBGenericDescriptor_STRING, - USBStringDescriptor_UNICODE('S'), - USBStringDescriptor_UNICODE('K'), - USBStringDescriptor_UNICODE('Y'), - USBStringDescriptor_UNICODE('9'), - USBStringDescriptor_UNICODE('X'), - USBStringDescriptor_UNICODE(' '), - USBStringDescriptor_UNICODE('J'), - USBStringDescriptor_UNICODE('o'), - USBStringDescriptor_UNICODE('y'), - USBStringDescriptor_UNICODE('s'), - USBStringDescriptor_UNICODE('t'), - USBStringDescriptor_UNICODE('i'), - USBStringDescriptor_UNICODE('c'), - USBStringDescriptor_UNICODE('k'), -}; - -static const unsigned char serialNumberDescriptor[] = { - - USBStringDescriptor_LENGTH(12), - USBGenericDescriptor_STRING, - USBStringDescriptor_UNICODE('0'), - USBStringDescriptor_UNICODE('1'), - USBStringDescriptor_UNICODE('2'), - USBStringDescriptor_UNICODE('3'), - USBStringDescriptor_UNICODE('4'), - USBStringDescriptor_UNICODE('5'), - USBStringDescriptor_UNICODE('6'), - USBStringDescriptor_UNICODE('7'), - USBStringDescriptor_UNICODE('8'), - USBStringDescriptor_UNICODE('9'), - USBStringDescriptor_UNICODE('A'), - USBStringDescriptor_UNICODE('F') -}; - -static const unsigned char *stringDescriptors[] = { - - languageIdDescriptor, - manufacturerDescriptor, - productDescriptor, - serialNumberDescriptor -}; - -//------------------------------------------------------------------------------ -// Exported variables -//------------------------------------------------------------------------------ - -/// List of descriptors used by the HID joystick driver. -USBDDriverDescriptors hiddJoystickDriverDescriptors = { - - &deviceDescriptor, - (USBConfigurationDescriptor *) &configurationDescriptors, - 0, // No full-speed device qualifier descriptor - 0, // No full-speed other speed configuration - 0, // No high-speed device descriptor - 0, // No high-speed configuration descriptor - 0, // No high-speed device qualifier descriptor - 0, // No high-speed other speed configuration descriptor - stringDescriptors, - 4 // Four string descriptors in list -}; diff --git a/radio/src/targets/sky9x/usb/device/hid-joystick/HIDDJoystickDriverDescriptors.h b/radio/src/targets/sky9x/usb/device/hid-joystick/HIDDJoystickDriverDescriptors.h deleted file mode 100644 index b9c774016..000000000 --- a/radio/src/targets/sky9x/usb/device/hid-joystick/HIDDJoystickDriverDescriptors.h +++ /dev/null @@ -1,79 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Definitions of the descriptors required by the HID device joystick - driver. - - !!!Usage - -# Use the hiddJoystickDriverDescriptors variable to initialize a - USBDDriver instance. - -# Send hiddReportDescriptor to the host when a GET_DESCRIPTOR request - for the report descriptor is received. -*/ - -#ifndef HIDDJOYSTICKDRIVERDESCRIPTORS_H -#define HIDDJOYSTICKDRIVERDESCRIPTORS_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ -/* - Constants: Endpoints - HIDDJoystickDriverDescriptors_INTERRUPTIN - Interrupt IN endpoint number. - HIDDJoystickDriverDescriptors_INTERRUPTIN_POLLING - Interrupt IN endpoint - polling rate (in milliseconds). -*/ -#define HIDDJoystickDriverDescriptors_INTERRUPTIN 1 -#define HIDDJoystickDriverDescriptors_INTERRUPTIN_POLLING 10 - -//------------------------------------------------------------------------------ -// Exported variables -//------------------------------------------------------------------------------ -/* - Variables: HID joystick driver descriptors - hiddJoystickDriverDescriptors - List of descriptors used by the HID - joystick driver. - hiddReportDescriptor - Report descriptor used by the driver. -*/ -extern USBDDriverDescriptors hiddJoystickDriverDescriptors; -extern const unsigned char hiddReportDescriptor[]; - -#endif //#ifndef HIDDJOYSTICKDRIVERDESCRIPTORS_H - diff --git a/radio/src/targets/sky9x/usb/device/hid-joystick/HIDDJoystickInputReport.c b/radio/src/targets/sky9x/usb/device/hid-joystick/HIDDJoystickInputReport.c deleted file mode 100644 index 3fafe5cca..000000000 --- a/radio/src/targets/sky9x/usb/device/hid-joystick/HIDDJoystickInputReport.c +++ /dev/null @@ -1,64 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: HIDDJoystickInputReport implementation - - About: Purpose - Implementation of the HIDDJoystickInputReport class. -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "HIDDJoystickInputReport.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Initializes a joystick input report instance. -/// \param report Pointer to a HIDDJoystickInputReport instance. -//------------------------------------------------------------------------------ -void HIDDJoystickInputReport_Initialize(HIDDJoystickInputReport *report) -{ - report->buttons1 = 0; - report->buttons2 = 0; - report->buttons3 = 0; - report->X = 0; - report->Y = 0; - report->Z = 0; - report->Rx = 0; - report->Ry = 0; - report->Rz = 0; - report->S1 = 0; - report->S2 = 0; -} diff --git a/radio/src/targets/sky9x/usb/device/hid-joystick/HIDDJoystickInputReport.h b/radio/src/targets/sky9x/usb/device/hid-joystick/HIDDJoystickInputReport.h deleted file mode 100644 index 42af51e3f..000000000 --- a/radio/src/targets/sky9x/usb/device/hid-joystick/HIDDJoystickInputReport.h +++ /dev/null @@ -1,86 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - \unit - - !!!Purpose - - Class for manipulating HID Joystick input reports. - - !!!Usage - - -# Initialize a newly created input report with - HIDDJoystickInputReport_Initialize -*/ - -#ifndef HIDDJOYSTICKINPUTREPORT_H -#define HIDDJOYSTICKINPUTREPORT_H - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// HID input report structure used by the Joystick driver to notify the -/// host of pressed keys. -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char buttons1; // bit 0 - button 1, bit 1 - button 2, ..., mapped to channels 9-16, on if channel > 0 - unsigned char buttons2; // mapped to channels 17-24, on if channel > 0 - unsigned char buttons3; // mapped to channels 25-32, on if channel > 0 - unsigned char X; // analog value, mapped to channel 1 - unsigned char Y; // analog value, mapped to channel 2 - unsigned char Z; // analog value, mapped to channel 3 - unsigned char Rx; // analog value, mapped to channel 4 - unsigned char Ry; // analog value, mapped to channel 5 - unsigned char Rz; // analog value, mapped to channel 6 - unsigned char S1; // analog value, mapped to channel 7 - unsigned char S2; // analog value, mapped to channel 8 - -} __attribute__ ((packed)) HIDDJoystickInputReport; // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern void HIDDJoystickInputReport_Initialize(HIDDJoystickInputReport *report); - -#endif //#ifndef HIDDJOYSTICKINPUTREPORT_H - diff --git a/radio/src/targets/sky9x/usb/device/massstorage/MSD.h b/radio/src/targets/sky9x/usb/device/massstorage/MSD.h deleted file mode 100644 index 23a934d35..000000000 --- a/radio/src/targets/sky9x/usb/device/massstorage/MSD.h +++ /dev/null @@ -1,233 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Mass Storage class definitions. -/// -/// See -/// - -/// USB Mass Storage Class Spec. Overview -/// - -/// USB Mass Storage Class Bulk-Only Transport -/// -/// !Usage -/// -/// -# Uses "MSD Requests" to check incoming requests from USB Host. -/// -# Uses "MSD Subclass Codes" and "MSD Protocol Codes" to fill %device -/// interface descriptors for a MSD %device. -/// -# Handle the incoming Bulk data with "MSD CBW Definitions" and MSCbw -/// structure. -/// -# Prepare the outgoing Bulk data with "MSD CSW Definitions" and MSCsw -/// structure. -//------------------------------------------------------------------------------ - -#ifndef MSD_H -#define MSD_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Requests" -/// This page lists MSD-specific requests ( Actually for Bulk-only protocol ). -/// -/// !Requests -/// - MSD_BULK_ONLY_RESET -/// - MSD_GET_MAX_LUN - -/// Reset the mass storage %device and its associated interface. -#define MSD_BULK_ONLY_RESET 0xFF -/// Return the maximum LUN number supported by the %device. -#define MSD_GET_MAX_LUN 0xFE -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Subclass Codes" -/// This page lists the Subclass Codes for bInterfaceSubClass field. -/// (Table 2.1, USB Mass Storage Class Spec. Overview) -/// -/// !SubClasses -/// - MSD_SUBCLASS_RBC -/// - MSD_SUBCLASS_SFF_MCC -/// - MSD_SUBCLASS_QIC -/// - MSD_SUBCLASS_UFI -/// - MSD_SUBCLASS_SFF -/// - MSD_SUBCLASS_SCSI - -/// Reduced Block Commands (RBC) T10 -#define MSD_SUBCLASS_RBC 0x01 -/// C/DVD devices -#define MSD_SUBCLASS_SFF_MCC 0x02 -/// Tape device -#define MSD_SUBCLASS_QIC 0x03 -/// Floppy disk drive (FDD) device -#define MSD_SUBCLASS_UFI 0x04 -/// Floppy disk drive (FDD) device -#define MSD_SUBCLASS_SFF 0x05 -/// SCSI transparent command set -#define MSD_SUBCLASS_SCSI 0x06 -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -/// \page "MSD Protocol Codes" -/// This page lists the Transport Protocol codes for MSD. -/// (Table 3.1, USB Mass Storage Class Spec. Overview) -/// -/// !Protocols -/// - MSD_PROTOCOL_CBI_COMPLETION -/// - MSD_PROTOCOL_CBI -/// - MSD_PROTOCOL_BULK_ONLY - -/// Control/Bulk/Interrupt (CBI) Transport (with command complete interrupt) -#define MSD_PROTOCOL_CBI_COMPLETION 0x00 -/// Control/Bulk/Interrupt (CBI) Transport (no command complete interrupt) -#define MSD_PROTOCOL_CBI 0x01 -/// Bulk-Only Transport -#define MSD_PROTOCOL_BULK_ONLY 0x50 -//------------------------------------------------------------------------------ - -/// Test unit control: -#define CTRL_NOT_READY 0x00 -#define CTRL_GOOD 0x01 -#define CTRL_BUSY 0x02 - -//------------------------------------------------------------------------------ -/// \page "MSD CBW Definitions" -/// This page lists the Command Block Wrapper (CBW) definitions. -/// -/// !Constants -/// - MSD_CBW_SIZE -/// - MSD_CBW_SIGNATURE -/// -/// !Fields -/// - MSD_CBW_DEVICE_TO_HOST - -/// Command Block Wrapper Size -#define MSD_CBW_SIZE 31 -/// 'USBC' 0x43425355 -#define MSD_CBW_SIGNATURE 0x43425355 - -/// CBW bmCBWFlags field -#define MSD_CBW_DEVICE_TO_HOST (1 << 7) -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD CSW Definitions" -/// This page lists the Command Status Wrapper (CSW) definitions. -/// -/// !Constants -/// - MSD_CSW_SIZE -/// - MSD_CSW_SIGNATURE -/// -/// !Command Block Status Values -/// (Table 5.3 , USB Mass Storage Class Bulk-Only Transport) -/// - MSD_CSW_COMMAND_PASSED -/// - MSD_CSW_COMMAND_FAILED -/// - MSD_CSW_PHASE_ERROR - -/// Command Status Wrapper Size -#define MSD_CSW_SIZE 13 -/// 'USBS' 0x53425355 -#define MSD_CSW_SIGNATURE 0x53425355 - -/// Command Passed (good status) -#define MSD_CSW_COMMAND_PASSED 0 -/// Command Failed -#define MSD_CSW_COMMAND_FAILED 1 -/// Phase Error -#define MSD_CSW_PHASE_ERROR 2 -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// Structures -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Command Block Wrapper (CBW), -/// See Table 5.1, USB Mass Storage Class Bulk-Only Transport. -/// -/// The CBW shall start on a packet boundary and shall end as a -/// short packet with exactly 31 (1Fh) bytes transferred. -//------------------------------------------------------------------------------ -typedef struct { - - /// 'USBC' 0x43425355 (little endian) - unsigned int dCBWSignature; - /// Must be the same as dCSWTag - unsigned int dCBWTag; - /// Number of bytes transfer - unsigned int dCBWDataTransferLength; - /// Indicates the directin of the transfer: - /// 0x80=IN=device-to-host, - /// 0x00=OUT=host-to-device - unsigned char bmCBWFlags; - /// bits 0->3: bCBWLUN - unsigned char bCBWLUN :4, - bReserved1:4; /// reserved - /// bits 0->4: bCBWCBLength - unsigned char bCBWCBLength:5, - bReserved2 :3; /// reserved - /// Command block - unsigned char pCommand[16]; - -} MSCbw; - -//------------------------------------------------------------------------------ -/// Command Status Wrapper (CSW), -/// See Table 5.2, USB Mass Storage Class Bulk-Only Transport. -//------------------------------------------------------------------------------ -typedef struct -{ - /// 'USBS' 0x53425355 (little endian) - unsigned int dCSWSignature; - /// Must be the same as dCBWTag - unsigned int dCSWTag; - /// For Data-Out the device shall report in the dCSWDataResidue the - /// difference between the amount of data expected as stated in the - /// dCBWDataTransferLength, and the actual amount of data processed by - /// the device. For Data-In the device shall report in the dCSWDataResidue - /// the difference between the amount of data expected as stated in the - /// dCBWDataTransferLength and the actual amount of relevant data sent by - /// the device. The dCSWDataResidue shall not exceed the value sent in the - /// dCBWDataTransferLength. - unsigned int dCSWDataResidue; - /// Indicates the success or failure of the command. - unsigned char bCSWStatus; - -} MSCsw; - -#endif //#ifndef MSD_H - diff --git a/radio/src/targets/sky9x/usb/device/massstorage/MSDDStateMachine.c b/radio/src/targets/sky9x/usb/device/massstorage/MSDDStateMachine.c deleted file mode 100644 index ff385949e..000000000 --- a/radio/src/targets/sky9x/usb/device/massstorage/MSDDStateMachine.c +++ /dev/null @@ -1,610 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//----------------------------------------------------------------------------- -// Includes -//----------------------------------------------------------------------------- - -#include "../../../usb/device/massstorage/MSDDStateMachine.h" - -#include "../../../usb/device/massstorage/SBCMethods.h" - -//----------------------------------------------------------------------------- -// Internal functions -//----------------------------------------------------------------------------- -//----------------------------------------------------------------------------- -/// Returns the expected transfer length and direction (IN, OUT or don't care) -/// from the host point-of-view. -/// \param cbw Pointer to the CBW to examinate -/// \param pLength Expected length of command -/// \param pType Expected direction of command -//----------------------------------------------------------------------------- -static void MSDD_GetCommandInformation(MSCbw *cbw, - unsigned int *length, - unsigned char *type) -{ - // Expected host transfer direction and length - (*length) = cbw->dCBWDataTransferLength; - - if (*length == 0) { - - (*type) = MSDD_NO_TRANSFER; - } - else if ((cbw->bmCBWFlags & MSD_CBW_DEVICE_TO_HOST) != 0) { - - (*type) = MSDD_DEVICE_TO_HOST; - } - else { - - (*type) = MSDD_HOST_TO_DEVICE; - } -} - -//----------------------------------------------------------------------------- -/// Pre-processes a command by checking the differences between the host and -/// device expectations in term of transfer type and length. -/// Once one of the thirteen cases is identified, the actions to do during the -/// post-processing phase are stored in the dCase variable of the command -/// state. -/// \param pMsdDriver Pointer to a MSDDriver instance -/// \return 1 if the command is supported, false otherwise -//----------------------------------------------------------------------------- -static unsigned char MSDD_PreProcessCommand(MSDDriver *pMsdDriver) -{ - unsigned int hostLength = 0; - unsigned int deviceLength = 0; - unsigned char hostType; - unsigned char deviceType; - unsigned char isCommandSupported; - MSDCommandState *commandState = &(pMsdDriver->commandState); - MSCsw *csw = &(commandState->csw); - MSCbw *cbw = &(commandState->cbw); - MSDLun *lun = &(pMsdDriver->luns[(unsigned char) cbw->bCBWLUN]); - - // Get information about the command - // Host-side - MSDD_GetCommandInformation(cbw, &hostLength, &hostType); - - // Device-side - isCommandSupported = SBC_GetCommandInformation(cbw->pCommand, - &deviceLength, - &deviceType, - lun); - - // Initialize data residue and result status - csw->dCSWDataResidue = 0; - csw->bCSWStatus = MSD_CSW_COMMAND_PASSED; - - // Check if the command is supported - if (isCommandSupported) { - - // Identify the command case - if(hostType == MSDD_NO_TRANSFER) { - - // Case 1 (Hn = Dn) - if(deviceType == MSDD_NO_TRANSFER) { - - //TRACE_WARNING("Case 1\n\r"); - commandState->postprocess = 0; - commandState->length = 0; - } - else if(deviceType == MSDD_DEVICE_TO_HOST) { - - // Case 2 (Hn < Di) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 2\n\r"); - commandState->postprocess = MSDD_CASE_PHASE_ERROR; - commandState->length = 0; - } - else { //if(deviceType == MSDD_HOST_TO_DEVICE) { - - // Case 3 (Hn < Do) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 3\n\r"); - commandState->postprocess = MSDD_CASE_PHASE_ERROR; - commandState->length = 0; - } - } - - // Case 4 (Hi > Dn) - else if(hostType == MSDD_DEVICE_TO_HOST) { - - if(deviceType == MSDD_NO_TRANSFER) { - - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 4\n\r"); - commandState->postprocess = MSDD_CASE_STALL_IN; - commandState->length = 0; - csw->dCSWDataResidue = hostLength; - } - else if(deviceType == MSDD_DEVICE_TO_HOST) { - - TRACE_ERROR("cmd=0x%0x h=%d d=%d", cbw->pCommand[0], hostLength, deviceLength); - - if(hostLength > deviceLength) { - - // Case 5 (Hi > Di) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 5\n\r"); - commandState->postprocess = MSDD_CASE_STALL_IN; - commandState->length = deviceLength; - csw->dCSWDataResidue = hostLength - deviceLength; - } - else if(hostLength == deviceLength) { - - // Case 6 (Hi = Di) - commandState->postprocess = 0; - commandState->length = deviceLength; - } - else { //if(hostLength < deviceLength) { - - // Case 7 (Hi < Di) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 7\n\r"); - commandState->postprocess = MSDD_CASE_PHASE_ERROR; - commandState->length = hostLength; - } - } - else { //if(deviceType == MSDD_HOST_TO_DEVICE) { - - // Case 8 (Hi <> Do) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 8\n\r"); - commandState->postprocess = - MSDD_CASE_STALL_IN | MSDD_CASE_PHASE_ERROR; - commandState->length = 0; - } - } - else if(hostType == MSDD_HOST_TO_DEVICE) { - - if(deviceType == MSDD_NO_TRANSFER) { - - // Case 9 (Ho > Dn) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 9\n\r"); - commandState->postprocess = MSDD_CASE_STALL_OUT; - commandState->length = 0; - csw->dCSWDataResidue = hostLength; - } - else if(deviceType == MSDD_DEVICE_TO_HOST) { - - // Case 10 (Ho <> Di) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 10\n\r"); - commandState->postprocess = - MSDD_CASE_STALL_OUT | MSDD_CASE_PHASE_ERROR; - commandState->length = 0; - } - else { //if(deviceType == MSDD_HOST_TO_DEVICE) { - - if(hostLength > deviceLength) { - - // Case 11 (Ho > Do) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 11\n\r"); - commandState->postprocess = MSDD_CASE_STALL_OUT; -// commandState->length = deviceLength; -// csw->dCSWDataResidue = hostLength - deviceLength; - commandState->length = 0; - csw->dCSWDataResidue = deviceLength; - } - else if(hostLength == deviceLength) { - - // Case 12 (Ho = Do) - //TRACE_WARNING( - // "MSDD_PreProcessCommand: Case 12\n\r"); - commandState->postprocess = 0; - commandState->length = deviceLength; - } - else { //if(hostLength < deviceLength) { - - // Case 13 (Ho < Do) - TRACE_WARNING( - "MSDD_PreProcessCommand: Case 13\n\r"); - commandState->postprocess = MSDD_CASE_PHASE_ERROR; - commandState->length = hostLength; - } - } - } - } - - return isCommandSupported; -} - -//----------------------------------------------------------------------------- -/// Post-processes a command given the case identified during the -/// pre-processing step. -/// Depending on the case, one of the following actions can be done: -/// - Bulk IN endpoint is stalled -/// - Bulk OUT endpoint is stalled -/// - CSW status set to phase error -/// \param pMsdDriver Pointer to a MSDDriver instance -/// \return If the device is halted -//----------------------------------------------------------------------------- -static unsigned char MSDD_PostProcessCommand(MSDDriver *pMsdDriver) -{ - MSDCommandState *commandState = &(pMsdDriver->commandState); - MSCsw *csw = &(commandState->csw); - unsigned char haltStatus = 0; - - // STALL Bulk IN endpoint ? - if ((commandState->postprocess & MSDD_CASE_STALL_IN) != 0) { - - TRACE_INFO_WP("StallIn "); - MSDD_Halt(MSDD_CASE_STALL_IN); - haltStatus = 1; - } - - // STALL Bulk OUT endpoint ? - if ((commandState->postprocess & MSDD_CASE_STALL_OUT) != 0) { - - TRACE_INFO_WP("StallOut "); - MSDD_Halt(MSDD_CASE_STALL_OUT); - haltStatus = 1; - } - - // Set CSW status code to phase error ? - if ((commandState->postprocess & MSDD_CASE_PHASE_ERROR) != 0) { - - TRACE_INFO_WP("PhaseErr "); - csw->bCSWStatus = MSD_CSW_PHASE_ERROR; - } - - return haltStatus; -} - -//----------------------------------------------------------------------------- -/// Processes the latest command received by the %device. -/// \param pMsdDriver Pointer to a MSDDriver instance -/// \return 1 if the command has been completed, false otherwise. -//----------------------------------------------------------------------------- -static unsigned char MSDD_ProcessCommand(MSDDriver * pMsdDriver) -{ - unsigned char status; - MSDCommandState *commandState = &(pMsdDriver->commandState); - MSCbw *cbw = &(commandState->cbw); - MSCsw *csw = &(commandState->csw); - MSDLun *lun = &(pMsdDriver->luns[(unsigned char) cbw->bCBWLUN]); - unsigned char isCommandComplete = 0; - - // Check if LUN is valid - if (cbw->bCBWLUN > pMsdDriver->maxLun) { - - TRACE_WARNING( - "MSDD_ProcessCommand: LUN %d not exist\n\r", cbw->bCBWLUN); - status = MSDD_STATUS_ERROR; - } - else { - - // Process command - if (pMsdDriver->maxLun > 0) { - - TRACE_INFO_WP("LUN%d ", cbw->bCBWLUN); - } - - status = SBC_ProcessCommand(lun, commandState); - } - - // Check command result code - if (status == MSDD_STATUS_PARAMETER) { - - TRACE_WARNING( - "MSDD_ProcessCommand: Unknown cmd 0x%02X\n\r", - cbw->pCommand[0]); - - // Update sense data - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_ILLEGAL_REQUEST, - SBC_ASC_INVALID_FIELD_IN_CDB, - 0); - - // Result codes - csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; - isCommandComplete = 1; - - // stall the request, IN or OUT - if (((cbw->bmCBWFlags & MSD_CBW_DEVICE_TO_HOST) == 0) - && (cbw->dCBWDataTransferLength > 0)) { - - // Stall the OUT endpoint : host to device - // MSDD_Halt(MSDD_CASE_STALL_OUT); - commandState->postprocess = MSDD_CASE_STALL_OUT; - TRACE_INFO_WP("StaOUT "); - } - else { - - // Stall the IN endpoint : device to host - // MSDD_Halt(MSDD_CASE_STALL_IN); - commandState->postprocess = MSDD_CASE_STALL_IN; - TRACE_INFO_WP("StaIN "); - } - } - else if (status == MSDD_STATUS_ERROR) { - - TRACE_WARNING("MSD_ProcessCommand: Cmd %x fail\n\r", - ((SBCCommand*)commandState->cbw.pCommand)->bOperationCode); - - // Update sense data - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_MEDIUM_ERROR, - SBC_ASC_INVALID_FIELD_IN_CDB, - 0); - - // Result codes - csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; - isCommandComplete = 1; - } - else if (status == MSDD_STATUS_RW) { - - csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; - isCommandComplete = 1; - } - else { - - // Update sense data - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_NO_SENSE, - 0, - 0); - - // Is command complete ? - if (status == MSDD_STATUS_SUCCESS) { - - isCommandComplete = 1; - } - } - - // Check if command has been completed - if (isCommandComplete) { - - TRACE_INFO_WP("Cplt "); - - // Adjust data residue - if (commandState->length != 0) { - - csw->dCSWDataResidue += commandState->length; - - // STALL the endpoint waiting for data - if ((cbw->bmCBWFlags & MSD_CBW_DEVICE_TO_HOST) == 0) { - - // Stall the OUT endpoint : host to device - // MSDD_Halt(MSDD_CASE_STALL_OUT); - commandState->postprocess = MSDD_CASE_STALL_OUT; - TRACE_INFO_WP("StaOUT "); - } - else { - - // Stall the IN endpoint : device to host - // MSDD_Halt(MSDD_CASE_STALL_IN); - commandState->postprocess = MSDD_CASE_STALL_IN; - TRACE_INFO_WP("StaIN "); - } - } - - // Reset command state - commandState->state = 0; - } - - return isCommandComplete; -} - -//----------------------------------------------------------------------------- -/// State machine for the MSD %device driver -/// \param pMsdDriver Pointer to a MSDDriver instance -//----------------------------------------------------------------------------- -void MSDD_StateMachine(MSDDriver * pMsdDriver) -{ - MSDCommandState *commandState = &(pMsdDriver->commandState); - MSCbw *cbw = &(commandState->cbw); - MSCsw *csw = &(commandState->csw); - MSDTransfer *transfer = &(commandState->transfer); - unsigned char status; - - // Identify current driver state - switch (pMsdDriver->state) { - //---------------------- - case MSDD_STATE_READ_CBW: - //---------------------- - // Start the CBW read operation - transfer->semaphore = 0; - status = MSDD_Read(cbw, - MSD_CBW_SIZE, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - - // Check operation result code - if (status == USBD_STATUS_SUCCESS) { - - // If the command was successful, wait for transfer - pMsdDriver->state = MSDD_STATE_WAIT_CBW; - } - break; - - //---------------------- - case MSDD_STATE_WAIT_CBW: - //---------------------- - // Check transfer semaphore - if (transfer->semaphore > 0) { - - // Take semaphore and terminate transfer - transfer->semaphore--; - - // Check if transfer was successful - if (transfer->status == USBD_STATUS_SUCCESS) { - - TRACE_INFO_WP("------------------------------\n\r"); - - // Process received command - pMsdDriver->state = MSDD_STATE_PROCESS_CBW; - } - else if (transfer->status == USBD_STATUS_RESET) { - - TRACE_INFO("MSDD_StateMachine: EP resetted\n\r"); - pMsdDriver->state = MSDD_STATE_READ_CBW; - } - else { - - TRACE_WARNING( - "MSDD_StateMachine: Failed to read CBW\n\r"); - pMsdDriver->state = MSDD_STATE_READ_CBW; - } - } - break; - - //------------------------- - case MSDD_STATE_PROCESS_CBW: - //------------------------- - // Check if this is a new command - if (commandState->state == 0) { - - // Copy the CBW tag - csw->dCSWTag = cbw->dCBWTag; - - // Check that the CBW is 31 bytes long - if ((transfer->transferred != MSD_CBW_SIZE) || - (transfer->remaining != 0)) { - - TRACE_WARNING( - "MSDD_StateMachine: Invalid CBW (len %d)\n\r", - (int)transfer->transferred); - - // Wait for a reset recovery - pMsdDriver->waitResetRecovery = 1; - - // Halt the Bulk-IN and Bulk-OUT pipes - MSDD_Halt(MSDD_CASE_STALL_OUT | MSDD_CASE_STALL_IN); - - csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; - pMsdDriver->state = MSDD_STATE_READ_CBW; - - } - // Check the CBW Signature - else if (cbw->dCBWSignature != MSD_CBW_SIGNATURE) { - - TRACE_WARNING( - "MSD_BOTStateMachine: Invalid CBW (Bad signature)\n\r"); - - // Wait for a reset recovery - pMsdDriver->waitResetRecovery = 1; - - // Halt the Bulk-IN and Bulk-OUT pipes - MSDD_Halt(MSDD_CASE_STALL_OUT | MSDD_CASE_STALL_IN); - - csw->bCSWStatus = MSD_CSW_COMMAND_FAILED; - pMsdDriver->state = MSDD_STATE_READ_CBW; - } - else { - - // Pre-process command - MSDD_PreProcessCommand(pMsdDriver); - } - } - - // Process command - if (csw->bCSWStatus == MSDD_STATUS_SUCCESS) { - - if (MSDD_ProcessCommand(pMsdDriver)) { - - // Post-process command if it is finished - if (MSDD_PostProcessCommand(pMsdDriver)) { - - TRACE_INFO_WP("WaitHALT "); - pMsdDriver->state = MSDD_STATE_WAIT_HALT; - } - else { - - pMsdDriver->state = MSDD_STATE_SEND_CSW; - } - } - TRACE_INFO_WP("\n\r"); - } - - break; - - //---------------------- - case MSDD_STATE_SEND_CSW: - //---------------------- - // Set signature - csw->dCSWSignature = MSD_CSW_SIGNATURE; - - // Start the CSW write operation - status = MSDD_Write(csw, - MSD_CSW_SIZE, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - - // Check operation result code - if (status == USBD_STATUS_SUCCESS) { - - TRACE_INFO_WP("SendCSW "); - - // Wait for end of transfer - pMsdDriver->state = MSDD_STATE_WAIT_CSW; - } - break; - - //---------------------- - case MSDD_STATE_WAIT_CSW: - //---------------------- - // Check transfer semaphore - if (transfer->semaphore > 0) { - - // Take semaphore and terminate transfer - transfer->semaphore--; - - // Check if transfer was successful - if (transfer->status == USBD_STATUS_RESET) { - - TRACE_INFO("MSDD_StateMachine: EP resetted\n\r"); - } - else if (transfer->status == USBD_STATUS_ABORTED) { - - TRACE_WARNING( - "MSDD_StateMachine: Failed to send CSW\n\r"); - } - else { - - TRACE_INFO_WP("ok"); - } - - // Read new CBW - pMsdDriver->state = MSDD_STATE_READ_CBW; - } - break; - - //---------------------- - case MSDD_STATE_WAIT_HALT: - //---------------------- - if (MSDD_IsHalted() == 0) { - - pMsdDriver->state = MSDD_STATE_SEND_CSW; - } - break; - } -} diff --git a/radio/src/targets/sky9x/usb/device/massstorage/MSDDStateMachine.h b/radio/src/targets/sky9x/usb/device/massstorage/MSDDStateMachine.h deleted file mode 100644 index f8961c339..000000000 --- a/radio/src/targets/sky9x/usb/device/massstorage/MSDDStateMachine.h +++ /dev/null @@ -1,264 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//----------------------------------------------------------------------------- -/// \unit -/// !Purpose -/// -/// Definitions, structs, functions required by a Mass Storage device driver -/// state machine.. -/// -/// !Usage -/// -/// - For a USB device: -/// -# MSDD_Write, MSDD_Read, MSDD_Halt should be defined for -/// usage in the state machine procedure. -/// -/// -# MSDD_StateMachine is invoked to run the MSD state machine. -/// -//----------------------------------------------------------------------------- - -#ifndef MSDDSTATEMACHINE_H -#define MSDDSTATEMACHINE_H - -//----------------------------------------------------------------------------- -// Headers -//----------------------------------------------------------------------------- - -#include "../../../usb/device/massstorage/MSD.h" -#include "../../../usb/device/massstorage/MSDLun.h" -#include "debug.h" - -//----------------------------------------------------------------------------- -// Definitions -//----------------------------------------------------------------------------- - -//------------------------------------------------------------------------------ -/// \page "MSD Driver Possible states" -/// ... -/// -/// !States -/// - MSDD_STATE_READ_CBW -/// - MSDD_STATE_WAIT_CBW -/// - MSDD_STATE_PROCESS_CBW -/// - MSDD_STATE_WAIT_HALT -/// - MSDD_STATE_SEND_CSW -/// - MSDD_STATE_WAIT_CSW -/// - MSDD_STATE_WAIT_RESET - -//! \brief Driver is expecting a command block wrapper -#define MSDD_STATE_READ_CBW (1 << 0) - -//! \brief Driver is waiting for the transfer to finish -#define MSDD_STATE_WAIT_CBW (1 << 1) - -//! \brief Driver is processing the received command -#define MSDD_STATE_PROCESS_CBW (1 << 2) - -//! \brief Driver is halted because pipe halt or wait reset -#define MSDD_STATE_WAIT_HALT (1 << 3) - -//! \brief Driver is starting the transmission of a command status wrapper -#define MSDD_STATE_SEND_CSW (1 << 4) - -//! \brief Driver is waiting for the CSW transmission to finish -#define MSDD_STATE_WAIT_CSW (1 << 5) - -//! \brief Driver is waiting for the MassStorageReset -#define MSDD_STATE_WAIT_RESET (1 << 6) -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Driver Result Codes" -/// This page lists result codes for MSD functions. -/// -/// !Codes -/// - MSDD_STATUS_SUCCESS -/// - MSDD_STATUS_ERROR -/// - MSDD_STATUS_INCOMPLETE -/// - MSDD_STATUS_PARAMETER -/// - MSDD_STATUS_RW - -//! \brief Method was successful -#define MSDD_STATUS_SUCCESS 0x00 - -//! \brief There was an error when trying to perform a method -#define MSDD_STATUS_ERROR 0x01 - -//! \brief No error was encountered but the application should call the -//! method again to continue the operation -#define MSDD_STATUS_INCOMPLETE 0x02 - -//! \brief A wrong parameter has been passed to the method -#define MSDD_STATUS_PARAMETER 0x03 - -//! \brief An error when reading/writing disk (protected or not present) -#define MSDD_STATUS_RW 0x04 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Driver Action Cases" -/// This page lists actions to perform during the post-processing phase of a -/// command. -/// -/// !Actions -/// - MSDD_CASE_PHASE_ERROR -/// - MSDD_CASE_STALL_IN -/// - MSDD_CASE_STALL_OUT - -//! \brief Indicates that the CSW should report a phase error -#define MSDD_CASE_PHASE_ERROR (1 << 0) - -//! \brief The driver should halt the Bulk IN pipe after the transfer -#define MSDD_CASE_STALL_IN (1 << 1) - -//! \brief The driver should halt the Bulk OUT pipe after the transfer -#define MSDD_CASE_STALL_OUT (1 << 2) - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Driver Xfr Directions" -/// This page lists possible direction values for a data transfer -/// -/// !Directions -/// - MSDD_DEVICE_TO_HOST -/// - MSDD_HOST_TO_DEVICE -/// - MSDD_NO_TRANSFER - -#define MSDD_DEVICE_TO_HOST 0 -#define MSDD_HOST_TO_DEVICE 1 -#define MSDD_NO_TRANSFER 2 -//------------------------------------------------------------------------------ - -//----------------------------------------------------------------------------- -// Types -//----------------------------------------------------------------------------- - -//------------------------------------------------------------------------------ -//! \brief Structure for holding the result of a USB transfer -//! \see MSDDriver_Callback -//------------------------------------------------------------------------------ -typedef struct { - - volatile unsigned int transferred; /// Number of bytes transferred - volatile unsigned int remaining; /// Number of bytes not transferred - volatile unsigned short semaphore; /// Semaphore to indicate transfer completion - volatile unsigned short status; /// Operation result code - -} MSDTransfer; - -//------------------------------------------------------------------------------ -//! \brief Status of an executing command -//! \see MSDCbw -//! \see MSDCsw -//! \see MSDTransfer -//------------------------------------------------------------------------------ -typedef struct { - - MSDTransfer transfer; /// Current transfer status (USB) - MSDTransfer disktransfer;/// Current transfer status (Disk) - unsigned int length; /// Remaining length of command - MSCbw cbw; /// Received CBW (31 bytes) - unsigned char state; /// Current command state - MSCsw csw; /// CSW to send (13 bytes) - unsigned char postprocess; /// Actions to perform when command is complete - -} MSDCommandState; - -//------------------------------------------------------------------------------ -/// \brief MSD driver state variables -/// \see MSDCommandState -/// \see MSDLun -//------------------------------------------------------------------------------ -typedef struct { - - /// LUN list for the %device. - MSDLun *luns; - /// State of the currently executing command - MSDCommandState commandState; - /// Maximum LUN index - unsigned char maxLun; - /// Current state of the driver - unsigned char state; - /// Indicates if the driver is waiting for a reset recovery - unsigned char waitResetRecovery; - -} MSDDriver; - -//----------------------------------------------------------------------------- -// Inline functions -//----------------------------------------------------------------------------- -//----------------------------------------------------------------------------- -/// This function is to be used as a callback for USB or LUN transfers. -/// \param transfer Pointer to the transfer structure to update -/// \param status Operation result code -/// \param transferred Number of bytes transferred by the command -/// \param remaining Number of bytes not transferred -//----------------------------------------------------------------------------- -static inline void MSDDriver_Callback(MSDTransfer *transfer, - unsigned char status, - unsigned int transferred, - unsigned int remaining) -{ - TRACE_DEBUG("Cbk "); - transfer->semaphore++; - transfer->status = status; - transfer->transferred = transferred; - transfer->remaining = remaining; -} - -//----------------------------------------------------------------------------- -// Driver functions -//----------------------------------------------------------------------------- -//- MSD General support function -extern char MSDD_Read( - void* pData, - unsigned int dLength, - TransferCallback fCallback, - void* pArgument); - -extern char MSDD_Write( - void* pData, - unsigned int dLength, - TransferCallback fCallback, - void* pArgument); - -extern void MSDD_Halt(unsigned int stallCase); - -extern unsigned int MSDD_IsHalted(void); - -//----------------------------------------------------------------------------- -// Exported functions -//----------------------------------------------------------------------------- - -extern void MSDD_StateMachine(MSDDriver * pMsdDriver); - -#endif // #define MSDDSTATEMACHINE_H - diff --git a/radio/src/targets/sky9x/usb/device/massstorage/MSDDriver.c b/radio/src/targets/sky9x/usb/device/massstorage/MSDDriver.c deleted file mode 100644 index c5439a27b..000000000 --- a/radio/src/targets/sky9x/usb/device/massstorage/MSDDriver.c +++ /dev/null @@ -1,342 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include "../../../usb/device/massstorage/MSDDriver.h" - -#include "../../../usb/common/core/USBFeatureRequest.h" -#include "../../../usb/device/core/USBDDriver.h" -#include "../../../usb/device/massstorage/MSDDriverDescriptors.h" -#include "../../../usb/device/massstorage/SBCMethods.h" -#include "../../../Media.h" -#include "../../../usb/common/core/USBGenericRequest.h" -#include "../../../usb/device/core/USBD.h" -#include "debug.h" - -//----------------------------------------------------------------------------- -// Internal variables -//----------------------------------------------------------------------------- - -/// Mass storage device driver instance. -static MSDDriver msdDriver; - -/// Standard device driver instance. -static USBDDriver usbdDriver; - -//----------------------------------------------------------------------------- -// Internal functions -//----------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -/// Resets the state of the MSD driver -//----------------------------------------------------------------------------- -static void MSDDriver_Reset(void) -{ - TRACE_INFO_WP("MSDReset "); - - msdDriver.state = MSDD_STATE_READ_CBW; - msdDriver.waitResetRecovery = 0; - msdDriver.commandState.state = 0; -} - -//----------------------------------------------------------------------------- -// Callback re-implementation -//----------------------------------------------------------------------------- -//----------------------------------------------------------------------------- -/// Invoked when a new SETUP request is received from the host. Forwards the -/// request to the Mass Storage device driver handler function. -/// \param request Pointer to a USBGenericRequest instance. -//----------------------------------------------------------------------------- -//void USBDCallbacks_RequestReceived(const USBGenericRequest *request) -//{ -// MSDDriver_RequestHandler(request); -//} - -//----------------------------------------------------------------------------- -/// Invoked when the configuration of the device changes. Resets the mass -/// storage driver. -/// \param cfgnum New configuration number. -//----------------------------------------------------------------------------- -//void USBDDriverCallbacks_ConfigurationChanged(unsigned char cfgnum) -//{ -// if (cfgnum > 0) { - -// MSDDriver_Reset(); -// } -//} - -//----------------------------------------------------------------------------- -// Driver functions -//----------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -/// Reads from host through MSD defined bulk OUT pipe. Act as USBD_Read but by -/// a fixed OUT endpoint. -/// \param data Pointer to the data buffer that contains data read from host. -/// \param size The number of bytes should be read (buffer size). -/// \param callback Pointer to the function invoked on end of reading. -/// \param argument Pointer to additional argument data struct. -//----------------------------------------------------------------------------- -char MSDD_Read(void *data, - unsigned int size, - TransferCallback callback, - void *argument) - -{ - return USBD_Read(MSDDriverDescriptors_BULKOUT, - data, - size, - callback, - argument); -} - -//----------------------------------------------------------------------------- -/// Writes to host through MSD defined bulk IN pipe. Act as USBD_Write but by -/// a fixed IN endpoint. -/// \param data Pointer to the data that writes to the host. -/// \param size The number of bytes should be write. -/// \param callback Pointer to the function invoked on end of writing. -/// \param argument Pointer to additional argument data struct. -//----------------------------------------------------------------------------- -char MSDD_Write(void *data, - unsigned int size, - TransferCallback callback, - void *argument) -{ - return USBD_Write(MSDDriverDescriptors_BULKIN, - data, - size, - callback, - argument); -} - -//----------------------------------------------------------------------------- -/// HALT Specified USB pipe. -/// \param stallCASE Case of the stall condition (Bulk In/Out/Both). -//----------------------------------------------------------------------------- -void MSDD_Halt(unsigned int stallCASE) -{ - if (stallCASE & MSDD_CASE_STALL_OUT) { - - USBD_Halt(MSDDriverDescriptors_BULKOUT); - } - - if (stallCASE & MSDD_CASE_STALL_IN) { - - USBD_Halt(MSDDriverDescriptors_BULKIN); - } -} - -//----------------------------------------------------------------------------- -/// Return halted status -/// \return stallCASE bitmap, case of the stall condition -/// (bit: MSDD_CASE_STALL_OUT or MSDD_CASE_STALL_IN) -//----------------------------------------------------------------------------- -unsigned int MSDD_IsHalted(void) -{ - unsigned int stallCASE = 0; - if (USBD_IsHalted(MSDDriverDescriptors_BULKOUT)) { - - stallCASE |= MSDD_CASE_STALL_OUT; - } - if (USBD_IsHalted(MSDDriverDescriptors_BULKIN)) { - - stallCASE |= MSDD_CASE_STALL_IN; - } - return stallCASE; -} - -//----------------------------------------------------------------------------- -// Exported functions -//----------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -/// Initializes the MSD driver and the associated USB driver. -/// \param luns Pointer to a list of LUNs -/// \param numLuns Number of LUN in list -/// \see MSDLun -//----------------------------------------------------------------------------- -void MSDDriver_Initialize(MSDLun *defLuns, unsigned char numLuns) -{ - - TRACE_INFO("MSD init\n\r"); - - // Command state initialization - msdDriver.commandState.state = 0; - msdDriver.commandState.postprocess = 0; - msdDriver.commandState.length = 0; - msdDriver.commandState.transfer.semaphore = 0; - - // LUNs - msdDriver.luns = defLuns; - msdDriver.maxLun = (unsigned char) (numLuns - 1); - - // Reset BOT driver - MSDDriver_Reset(); - - // Init the USB driver - USBDDriver_Initialize(&usbdDriver, &msdDriverDescriptors, 0); - USBD_Init(); -} - -//----------------------------------------------------------------------------- -/// Handler for incoming SETUP requests on default Control endpoint 0. -/// -/// Standard requests are forwarded to the USBDDriver_RequestHandler -/// method. -/// \param request Pointer to a USBGenericRequest instance -//----------------------------------------------------------------------------- -void MSDDriver_RequestHandler(const USBGenericRequest *request) -{ - TRACE_INFO_WP("NewReq "); - - // Handle requests - switch (USBGenericRequest_GetRequest(request)) { - //--------------------- - case USBGenericRequest_CLEARFEATURE: - //--------------------- - TRACE_INFO_WP("ClrFeat "); - - switch (USBFeatureRequest_GetFeatureSelector(request)) { - - //--------------------- - case USBFeatureRequest_ENDPOINTHALT: - //--------------------- - TRACE_INFO_WP("Hlt "); - - // Do not clear the endpoint halt status if the device is waiting - // for a reset recovery sequence - if (!msdDriver.waitResetRecovery) { - - // Forward the request to the standard handler - USBDDriver_RequestHandler(&usbdDriver, request); - } - else { - - TRACE_INFO_WP("No "); - } - - USBD_Write(0, 0, 0, 0, 0); - break; - - //------ - default: - //------ - // Forward the request to the standard handler - USBDDriver_RequestHandler(&usbdDriver, request); - } - break; - - //------------------- - case MSD_GET_MAX_LUN: - //------------------- - TRACE_INFO_WP("gMaxLun "); - - // Check request parameters - if ((request->wValue == 0) - && (request->wIndex == 0) - && (request->wLength == 1)) { - - USBD_Write(0, &(msdDriver.maxLun), 1, 0, 0); - - } - else { - - TRACE_WARNING( - "MSDDriver_RequestHandler: GetMaxLUN(%d,%d,%d)\n\r", - request->wValue, request->wIndex, request->wLength); - USBD_Stall(0); - } - break; - - //----------------------- - case MSD_BULK_ONLY_RESET: - //----------------------- - TRACE_INFO_WP("Rst "); - - // Check parameters - if ((request->wValue == 0) - && (request->wIndex == 0) - && (request->wLength == 0)) { - - // Reset the MSD driver - MSDDriver_Reset(); - USBD_Write(0, 0, 0, 0, 0); - } - else { - - TRACE_WARNING( - "MSDDriver_RequestHandler: Reset(%d,%d,%d)\n\r", - request->wValue, request->wIndex, request->wLength); - USBD_Stall(0); - } - break; - - //------ - default: - //------ - // Forward request to standard handler - USBDDriver_RequestHandler(&usbdDriver, request); - - break; - } -} - -//----------------------------------------------------------------------------- -/// State machine for the MSD driver -//----------------------------------------------------------------------------- -void MSDDriver_StateMachine(void) -{ - if (USBD_GetState() < USBD_STATE_CONFIGURED){} - else MSDD_StateMachine(&msdDriver); - -} - -//----------------------------------------------------------------------------- -/// Starts a remote wake-up sequence if the host has explicitely enabled it -/// by sending the appropriate SET_FEATURE request. -//----------------------------------------------------------------------------- -void MSDDriver_RemoteWakeUp(void) -{ - // Remote wake-up has been enabled - if (USBDDriver_IsRemoteWakeUpEnabled(&usbdDriver)) { - - USBD_RemoteWakeUp(); - } - // Remote wake-up NOT enabled - else { - - TRACE_WARNING( - "MSD..RemoteWakeUp: Host has not enabled remote wake-up\n\r"); - } -} - diff --git a/radio/src/targets/sky9x/usb/device/massstorage/MSDDriver.h b/radio/src/targets/sky9x/usb/device/massstorage/MSDDriver.h deleted file mode 100644 index a1ac1e990..000000000 --- a/radio/src/targets/sky9x/usb/device/massstorage/MSDDriver.h +++ /dev/null @@ -1,75 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Mass storage %device driver implementation. -/// -/// !Usage -/// -/// -# Enable and setup USB related pins (see pio & board.h). -/// -# Configure the memory interfaces used for Mass Storage LUNs -/// (see memories, MSDLun.h). -/// -# Configure the USB MSD %driver using MSDDriver_Initialize. -/// -# Invoke MSDDriver_StateMachine in main loop to handle all Mass Storage -/// operations. -//------------------------------------------------------------------------------ - -#ifndef MSDDRIVER_H -#define MSDDRIVER_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/device/massstorage/MSD.h" -#include "../../../usb/device/massstorage/MSDLun.h" -// #include - -//------------------------------------------------------------------------------ -// Global functions -//------------------------------------------------------------------------------ - -extern void MSDDriver_Initialize(MSDLun *luns, unsigned char numLuns); - -extern void MSDDriver_RequestHandler(const USBGenericRequest *request); - -extern void MSDDriver_StateMachine(void); - -extern void MSDDriver_RemoteWakeUp(void); - -extern void MSDDriver_DataCallback(unsigned char isRead, - unsigned int dataLength, - unsigned int nullCnt, - unsigned int fullCnt); - -#endif // #ifndef MSDDRIVER_H - diff --git a/radio/src/targets/sky9x/usb/device/massstorage/MSDDriverDescriptors.c b/radio/src/targets/sky9x/usb/device/massstorage/MSDDriverDescriptors.c deleted file mode 100644 index 47a25d7c6..000000000 --- a/radio/src/targets/sky9x/usb/device/massstorage/MSDDriverDescriptors.c +++ /dev/null @@ -1,469 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/device/massstorage/MSDDriverDescriptors.h" - -#include "../../../usb/common/core/USBStringDescriptor.h" -#include "../../../usb/common/massstorage/MSDeviceDescriptor.h" -#include "../../../usb/common/massstorage/MSInterfaceDescriptor.h" -#include "board_lowlevel.h" -#include "../../../usb/common/core/USBConfigurationDescriptor.h" -#include "../../../usb/common/core/USBDeviceDescriptor.h" -#include "../../../usb/common/core/USBEndpointDescriptor.h" -#include "../../../usb/common/core/USBGenericDescriptor.h" -#include "../../../usb/common/core/USBInterfaceDescriptor.h" - -//------------------------------------------------------------------------------ -// Internal definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Device Descriptor IDs" -/// ... -/// !IDs -/// - MSDDriverDescriptors_VENDORID -/// - MSDDriverDescriptors_PRODUCTID -/// - MSDDriverDescriptors_RELEASE - -/// Vendor ID for the Mass Storage device driver. -#define MSDDriverDescriptors_VENDORID 0x03EB -/// Product ID for the Mass Storage device driver. -#define MSDDriverDescriptors_PRODUCTID 0x6129 -/// Device release number for the Mass Storage device driver. -#define MSDDriverDescriptors_RELEASE 0x0100 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Macros -//------------------------------------------------------------------------------ - -/// Returns the minimum between two values. -#define MIN(a, b) ((a < b) ? a : b) - -//------------------------------------------------------------------------------ -// Internal types -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// List of configuration descriptors used by a Mass Storage device driver. -//------------------------------------------------------------------------------ -typedef struct { - - /// Standard configuration descriptor. - USBConfigurationDescriptor configuration; -#if defined(CHIP_USB_OTGHS) - // OTG descriptor - USBOtgDescriptor otgDescriptor; -#endif - /// Mass storage interface descriptor. - USBInterfaceDescriptor interface; - /// Bulk-out endpoint descriptor. - USBEndpointDescriptor bulkOut; - /// Bulk-in endpoint descriptor. - USBEndpointDescriptor bulkIn; - -} __attribute__ ((packed)) MSDConfigurationDescriptors; - -//------------------------------------------------------------------------------ -// Local variables -//------------------------------------------------------------------------------ - -/// Mass storage driver device descriptor. -static const USBDeviceDescriptor deviceDescriptor = { - - sizeof(USBDeviceDescriptor), - USBGenericDescriptor_DEVICE, - USBDeviceDescriptor_USB2_00, - MSDeviceDescriptor_CLASS, - MSDeviceDescriptor_SUBCLASS, - MSDeviceDescriptor_PROTOCOL, - CHIP_USB_ENDPOINTS_MAXPACKETSIZE(0), - MSDDriverDescriptors_VENDORID, - MSDDriverDescriptors_PRODUCTID, - MSDDriverDescriptors_RELEASE, - 1, // Manufacturer string descriptor index. - 2, // Product string descriptor index. - 3, // Serial number string descriptor index. - 1 // Device has one possible configuration. -}; - -#if defined(CHIP_USB_UDPHS) || defined(CHIP_USB_OTGHS) -/// Device qualifier descriptor. -static const USBDeviceQualifierDescriptor qualifierDescriptor = { - - sizeof(USBDeviceQualifierDescriptor), - USBGenericDescriptor_DEVICEQUALIFIER, - USBDeviceDescriptor_USB2_00, - MSDeviceDescriptor_CLASS, - MSDeviceDescriptor_SUBCLASS, - MSDeviceDescriptor_PROTOCOL, - CHIP_USB_ENDPOINTS_MAXPACKETSIZE(0), - 1, // Device has one possible configuration. - 0x00 -}; -#endif - -/// Full-speed configuration descriptor. -static const MSDConfigurationDescriptors configurationDescriptorsFS = { - - // Standard configuration descriptor. - { - sizeof(USBConfigurationDescriptor), - USBGenericDescriptor_CONFIGURATION, - sizeof(MSDConfigurationDescriptors), - 1, // Configuration has one interface. - 1, // This is configuration #1. - 0, // No string descriptor for configuration. - BOARD_USB_BMATTRIBUTES, - USBConfigurationDescriptor_POWER(100) - }, -#if defined(CHIP_USB_OTGHS) - // OTG descriptor - { - sizeof(USBOtgDescriptor), - USBGenericDescriptor_OTG, - USBOTGDescriptor_HNP_SRP - }, -#endif - // Mass Storage interface descriptor. - { - sizeof(USBInterfaceDescriptor), - USBGenericDescriptor_INTERFACE, - 0, // This is interface #0. - 0, // This is alternate setting #0. - 2, // Interface uses two endpoints. - MSInterfaceDescriptor_CLASS, - MSInterfaceDescriptor_SCSI, - MSInterfaceDescriptor_BULKONLY, - 0 // No string descriptor for interface. - }, - // Bulk-OUT endpoint descriptor - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_OUT, - MSDDriverDescriptors_BULKOUT), - USBEndpointDescriptor_BULK, - MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKOUT), - USBEndpointDescriptor_MAXBULKSIZE_FS), - 0 // Must be 0 for full-speed Bulk endpoints. - }, - // Bulk-IN endpoint descriptor - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_IN, - MSDDriverDescriptors_BULKIN), - USBEndpointDescriptor_BULK, - MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKIN), - USBEndpointDescriptor_MAXBULKSIZE_FS), - 0 // Must be 0 for full-speed Bulk endpoints. - } -}; - -#if defined(CHIP_USB_UDPHS) || defined(CHIP_USB_OTGHS) -/// Full-speed other speed configuration descriptor. -static const MSDConfigurationDescriptors otherSpeedDescriptorsFS = { - - // Standard configuration descriptor. - { - sizeof(USBConfigurationDescriptor), - USBGenericDescriptor_OTHERSPEEDCONFIGURATION, - sizeof(MSDConfigurationDescriptors), - 1, // Configuration has one interface. - 1, // This is configuration #1. - 0, // No string descriptor for configuration. - BOARD_USB_BMATTRIBUTES, - USBConfigurationDescriptor_POWER(100) - }, -#if defined(CHIP_USB_OTGHS) - // OTG descriptor - { - sizeof(USBOtgDescriptor), - USBGenericDescriptor_OTG, - USBOTGDescriptor_HNP_SRP - }, -#endif - // Mass Storage interface descriptor. - { - sizeof(USBInterfaceDescriptor), - USBGenericDescriptor_INTERFACE, - 0, // This is interface #0. - 0, // This is alternate setting #0. - 2, // Interface uses two endpoints. - MSInterfaceDescriptor_CLASS, - MSInterfaceDescriptor_SCSI, - MSInterfaceDescriptor_BULKONLY, - 0 // No string descriptor for interface. - }, - // Bulk-OUT endpoint descriptor - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_OUT, - MSDDriverDescriptors_BULKOUT), - USBEndpointDescriptor_BULK, - MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKOUT), - USBEndpointDescriptor_MAXBULKSIZE_HS), - 0 // No string descriptor for endpoint. - }, - // Bulk-IN endpoint descriptor - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_IN, - MSDDriverDescriptors_BULKIN), - USBEndpointDescriptor_BULK, - MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKIN), - USBEndpointDescriptor_MAXBULKSIZE_HS), - 0 // No string descriptor for endpoint. - } -}; - -/// High-speed configuration descriptor. -static const MSDConfigurationDescriptors configurationDescriptorsHS = { - - // Standard configuration descriptor. - { - sizeof(USBConfigurationDescriptor), - USBGenericDescriptor_CONFIGURATION, - sizeof(MSDConfigurationDescriptors), - 1, // Configuration has one interface. - 1, // This is configuration #1. - 0, // No string descriptor for configuration. - BOARD_USB_BMATTRIBUTES, - USBConfigurationDescriptor_POWER(100) - }, -#if defined(CHIP_USB_OTGHS) - // OTG descriptor - { - sizeof(USBOtgDescriptor), - USBGenericDescriptor_OTG, - USBOTGDescriptor_HNP_SRP - }, -#endif - // Mass Storage interface descriptor. - { - sizeof(USBInterfaceDescriptor), - USBGenericDescriptor_INTERFACE, - 0, // This is interface #0. - 0, // This is alternate setting #0. - 2, // Interface uses two endpoints. - MSInterfaceDescriptor_CLASS, - MSInterfaceDescriptor_SCSI, - MSInterfaceDescriptor_BULKONLY, - 0 // No string descriptor for interface. - }, - // Bulk-OUT endpoint descriptor - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_OUT, - MSDDriverDescriptors_BULKOUT), - USBEndpointDescriptor_BULK, - MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKOUT), - USBEndpointDescriptor_MAXBULKSIZE_HS), - 0 // No string descriptor for endpoint. - }, - // Bulk-IN endpoint descriptor - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_IN, - MSDDriverDescriptors_BULKIN), - USBEndpointDescriptor_BULK, - MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKIN), - USBEndpointDescriptor_MAXBULKSIZE_HS), - 0 // No string descriptor for endpoint. - } -}; - -/// High-speed other speed configuration descriptor. -static const MSDConfigurationDescriptors otherSpeedDescriptorsHS = { - - // Standard configuration descriptor. - { - sizeof(USBConfigurationDescriptor), - USBGenericDescriptor_OTHERSPEEDCONFIGURATION, - sizeof(MSDConfigurationDescriptors), - 1, // Configuration has one interface. - 1, // This is configuration #1. - 0, // No string descriptor for configuration. - BOARD_USB_BMATTRIBUTES, - USBConfigurationDescriptor_POWER(100) - }, -#if defined(CHIP_USB_OTGHS) - // OTG descriptor - { - sizeof(USBOtgDescriptor), - USBGenericDescriptor_OTG, - USBOTGDescriptor_HNP_SRP - }, -#endif - // Mass Storage interface descriptor. - { - sizeof(USBInterfaceDescriptor), - USBGenericDescriptor_INTERFACE, - 0, // This is interface #0. - 0, // This is alternate setting #0. - 2, // Interface uses two endpoints. - MSInterfaceDescriptor_CLASS, - MSInterfaceDescriptor_SCSI, - MSInterfaceDescriptor_BULKONLY, - 0 // No string descriptor for interface. - }, - // Bulk-OUT endpoint descriptor - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_OUT, - MSDDriverDescriptors_BULKOUT), - USBEndpointDescriptor_BULK, - MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKOUT), - USBEndpointDescriptor_MAXBULKSIZE_FS), - 0 // No string descriptor for endpoint. - }, - // Bulk-IN endpoint descriptor - { - sizeof(USBEndpointDescriptor), - USBGenericDescriptor_ENDPOINT, - USBEndpointDescriptor_ADDRESS( - USBEndpointDescriptor_IN, - MSDDriverDescriptors_BULKIN), - USBEndpointDescriptor_BULK, - MIN(CHIP_USB_ENDPOINTS_MAXPACKETSIZE(MSDDriverDescriptors_BULKIN), - USBEndpointDescriptor_MAXBULKSIZE_FS), - 0 // No string descriptor for endpoint. - } -}; -#endif - -/// Language ID string descriptor. -static const unsigned char languageIdDescriptor[] = { - - USBStringDescriptor_LENGTH(1), - USBGenericDescriptor_STRING, - USBStringDescriptor_ENGLISH_US -}; - -/// Manufacturer string descriptor. -static const unsigned char manufacturerDescriptor[] = { - - USBStringDescriptor_LENGTH(7), - USBGenericDescriptor_STRING, - USBStringDescriptor_UNICODE('9'), - USBStringDescriptor_UNICODE('X'), - USBStringDescriptor_UNICODE(' '), - USBStringDescriptor_UNICODE('T'), - USBStringDescriptor_UNICODE('E'), - USBStringDescriptor_UNICODE('A'), - USBStringDescriptor_UNICODE('M'), -}; - -/// Product string descriptor. -static const unsigned char productDescriptor[] = { - - USBStringDescriptor_LENGTH(5), - USBGenericDescriptor_STRING, - USBStringDescriptor_UNICODE('S'), - USBStringDescriptor_UNICODE('K'), - USBStringDescriptor_UNICODE('Y'), - USBStringDescriptor_UNICODE('9'), - USBStringDescriptor_UNICODE('X'), -}; - -/// Serial number string descriptor. The serial number must be at least 12 -/// characters long and made up of only letters & numbers to be compliant with -/// the MSD specification. -static const unsigned char serialNumberDescriptor[] = { - - USBStringDescriptor_LENGTH(12), - USBGenericDescriptor_STRING, - USBStringDescriptor_UNICODE('0'), - USBStringDescriptor_UNICODE('1'), - USBStringDescriptor_UNICODE('2'), - USBStringDescriptor_UNICODE('3'), - USBStringDescriptor_UNICODE('4'), - USBStringDescriptor_UNICODE('5'), - USBStringDescriptor_UNICODE('6'), - USBStringDescriptor_UNICODE('7'), - USBStringDescriptor_UNICODE('8'), - USBStringDescriptor_UNICODE('9'), - USBStringDescriptor_UNICODE('A'), - USBStringDescriptor_UNICODE('B') -}; - -/// List of all string descriptors used. -static const unsigned char *stringDescriptors[] = { - - languageIdDescriptor, - manufacturerDescriptor, - productDescriptor, - serialNumberDescriptor -}; - -//------------------------------------------------------------------------------ -// Global variables -//------------------------------------------------------------------------------ - -/// List of the standard descriptors used by the Mass Storage driver. -const USBDDriverDescriptors msdDriverDescriptors = { - - &deviceDescriptor, - (USBConfigurationDescriptor *) &configurationDescriptorsFS, -#if defined(CHIP_USB_UDPHS) || defined(CHIP_USB_OTGHS) - &qualifierDescriptor, - (USBConfigurationDescriptor *) &otherSpeedDescriptorsFS, - &deviceDescriptor, - (USBConfigurationDescriptor *) &configurationDescriptorsHS, - &qualifierDescriptor, - (USBConfigurationDescriptor *) &otherSpeedDescriptorsHS, -#else - 0, // No full-speed device qualifier descriptor - 0, // No full-speed other speed configuration - 0, // No high-speed device descriptor - 0, // No high-speed configuration descriptor - 0, // No high-speed device qualifier descriptor - 0, // No high-speed other speed configuration descriptor -#endif - stringDescriptors, - 4 // Four string descriptors in array -}; - diff --git a/radio/src/targets/sky9x/usb/device/massstorage/MSDDriverDescriptors.h b/radio/src/targets/sky9x/usb/device/massstorage/MSDDriverDescriptors.h deleted file mode 100644 index 11480a900..000000000 --- a/radio/src/targets/sky9x/usb/device/massstorage/MSDDriverDescriptors.h +++ /dev/null @@ -1,83 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Definitions of the descriptors required by a Mass Storage device driver. -/// -/// !Usage -/// -/// - For a USB %device: -/// -# When initializing a USBDDriver instance, use msdDriverDescriptors as -/// the list of standard descriptors. -//------------------------------------------------------------------------------ - -#ifndef MSDDRIVERDESCRIPTORS_H -#define MSDDRIVERDESCRIPTORS_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/device/core/USBDDriverDescriptors.h" - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD endpoint addresses" -/// This page lists the addresses used by the Mass Storage driver %endpoints. -/// -/// !Addresses -/// -/// - MSDDriverDescriptors_BULKOUT -/// - MSDDriverDescriptors_BULKIN - -/// Address of the Mass Storage bulk-out endpoint. -#define MSDDriverDescriptors_BULKOUT 1 - -/// Address of the Mass Storage bulk-in endpoint. -#if defined(at91sam9m10) - #define MSDDriverDescriptors_BULKIN 6 -#else - #define MSDDriverDescriptors_BULKIN 2 -#endif -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Exported variables -//------------------------------------------------------------------------------ - -extern const USBDDriverDescriptors msdDriverDescriptors; - -#endif //#ifndef MSDDRIVERDESCRIPTORS_H - diff --git a/radio/src/targets/sky9x/usb/device/massstorage/MSDIOFifo.h b/radio/src/targets/sky9x/usb/device/massstorage/MSDIOFifo.h deleted file mode 100644 index 5f7b7fba5..000000000 --- a/radio/src/targets/sky9x/usb/device/massstorage/MSDIOFifo.h +++ /dev/null @@ -1,135 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef _MSDIOFIFO_H -#define _MSDIOFIFO_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -/// Idle state, do nothing -#define MSDIO_IDLE 0 -/// Start, to start IO operation -#define MSDIO_START 1 -/// Wait, waiting for IO operation done -#define MSDIO_WAIT 2 -/// Next, to check if the next block can be performed -#define MSDIO_NEXT 3 -/// Pause, to pause the process for buffer full or null -#define MSDIO_PAUSE 4 -/// Abort, to abort the process -#define MSDIO_ABORT 5 -/// Done, finish without error -#define MSDIO_DONE 6 -/// Error, any error happens -#define MSDIO_ERROR 7 - -/// FIFO offset before USB transmit start -//#define MSDIO_FIFO_OFFSET (4*512) - -/// FIFO trunk size (in each transfer, large amount of data) -#if !defined(MSD_OP_BUFFER) -#define MSDIO_READ10_CHUNK_SIZE (4*512) -#define MSDIO_WRITE10_CHUNK_SIZE (4*512) -#endif - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ - -/// FIFO buffer for READ/WRITE (disk) operation of a mass storage device -typedef struct _MSDIOFifo { - - /// Pointer to the ring buffer allocated for read/write - unsigned char * pBuffer; - /// The size of the buffer allocated - unsigned int bufferSize; -#ifdef MSDIO_FIFO_OFFSET - /// The offset to start USB transfer (READ10) - unsigned int bufferOffset; -#endif - /// The index of input data (loaded to fifo buffer) - unsigned int inputNdx; - /// The total size of the loaded data - unsigned int inputTotal; - /// The index of output data (sent from the fifo buffer) - unsigned int outputNdx; - /// The total size of the output data - unsigned int outputTotal; - - /// The total size of the data - unsigned int dataTotal; - /// The size of the block in bytes - unsigned short blockSize; -#if defined(MSDIO_READ10_CHUNK_SIZE) || defined(MSDIO_WRITE10_CHUNK_SIZE) - /// The size of one chunk - /// (1 block, or several blocks for large amount data R/W) - unsigned int chunkSize; -#endif - /// State of input & output - unsigned char inputState; - unsigned char outputState; - - //- Statistics - /// Times when fifo has no data to send - unsigned short nullCnt; - /// Times when fifo can not load more input data - unsigned short fullCnt; -} MSDIOFifo, *PMSDIOFifo; - -//------------------------------------------------------------------------------ -// MACROS -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Increase the index, by defined block size, in the ring buffer -/// \param ndx The index to be increased -/// \param sectSize The defined block size -/// \param bufSize The ring buffer size -//------------------------------------------------------------------------------ -#define MSDIOFifo_IncNdx(ndx, sectSize, bufSize) \ - if ((ndx) >= (bufSize) - (sectSize)) (ndx) = 0; \ - else (ndx) += (sectSize) - - -//------------------------------------------------------------------------------ -// Exported Functions -//------------------------------------------------------------------------------ - - -extern void MSDIOFifo_Init(MSDIOFifo *pFifo, - void * pBuffer, unsigned short bufferSize); - -#endif // _MSDIOFIFO_H - diff --git a/radio/src/targets/sky9x/usb/device/massstorage/MSDLun.c b/radio/src/targets/sky9x/usb/device/massstorage/MSDLun.c deleted file mode 100644 index d39f9cc3c..000000000 --- a/radio/src/targets/sky9x/usb/device/massstorage/MSDLun.c +++ /dev/null @@ -1,367 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - - -#include "../../../usb/device/massstorage/MSDLun.h" -#include "board_lowlevel.h" -#include "../../../usb/device/core/USBD.h" -#include "debug.h" - -//------------------------------------------------------------------------------ -// Constants -//------------------------------------------------------------------------------ - -/// Default LUN block size in bytes -#define DEFAULT_LUN_BLOCK_SIZE BLOCK_SIZE - -//------------------------------------------------------------------------------ -// Internal variables -//------------------------------------------------------------------------------ - -/// Inquiry data to return to the host for the Lun. -static SBCInquiryData inquiryData = { - - SBC_DIRECT_ACCESS_BLOCK_DEVICE, // Direct-access block device - SBC_PERIPHERAL_DEVICE_CONNECTED,// Peripheral device is connected - 0x00, // Reserved bits - 0x01, // Media is removable - 0x02, // SBC_SPC_VERSION_4, // SPC-4 supported - 0x2, // Response data format, must be 0x2 - 0, // Hierarchical addressing not supported - 0, // ACA not supported - 0x0, // Obsolete bits - sizeof(SBCInquiryData) - 5, // Additional length - 0, // No embedded SCC - 0, // No access control coordinator - SBC_TPGS_NONE, // No target port support group - 0, // Third-party copy not supported - 0x0, // Reserved bits - 0, // Protection information not supported - 0x0, // Obsolete bit - 0, // No embedded enclosure service component - 0x0, // ??? - 0, // Device is not multi-port - 0x0, // Obsolete bits - 0x0, // Unused feature - 0x0, // Unused features - 0, // Task management model not supported - 0x0, // ??? - {'A','T','M','E','L',' ',' ',' '}, - {'M','a','s','s',' ', - 'S','t','o','r','a','g','e',' ', - 'M','S','D'}, - {'0','.','0','1'}, - {'M','a','s','s',' ', - 'S','t','o','r','a','g','e',' ', - 'E','x','a','m','p','l','e'}, - 0x00, // Unused features - 0x00, // Reserved bits - {SBC_VERSION_DESCRIPTOR_SBC_3}, // SBC-3 compliant device - {0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0} // Reserved -}; - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -//! \brief Initializes a LUN instance. Must be invoked at least once even no -//! Media is linked. -//! \param lun Pointer to the MSDLun instance to initialize -//! \param media Media on which the LUN is constructed, set to 0 to -//! disconnect the Media or initialize an ejected LUN. -//! \param ioBuffer Pointer to a buffer used for read/write operation and -//! which must be blockSize bytes long. -//! \param ioBufferSize Size of the allocated IO buffer. -//! \param baseAddress Base address of the LUN in number of media blocks -//! \param size Total size of the LUN in number of media blocks -//! \param blockSize One block of the LUN in number of media blocks -//! \param protected The LUN area is forced to readonly even the media -//! is writable -//! \param dataMonitor Pointer to a Monitor Function to analyze the flow of -//! this LUN. -//------------------------------------------------------------------------------ -void LUN_Init(MSDLun *lun, - Media *media, - unsigned char *ioBuffer, - unsigned int ioBufferSize, - unsigned int baseAddress, - unsigned int size, - unsigned short blockSize, - unsigned char protected, - void (*dataMonitor)(unsigned char flowDirection, - unsigned int dataLength, - unsigned int fifoNullCount, - unsigned int fifoFullCount)) -{ - unsigned int logicalBlockAddress; - TRACE_INFO("LUN init\n\r"); - - // Initialize inquiry data - lun->inquiryData = &inquiryData; - - // Initialize request sense data - lun->requestSenseData.bResponseCode = SBC_SENSE_DATA_FIXED_CURRENT; - lun->requestSenseData.isValid = 1; - lun->requestSenseData.bObsolete1 = 0; - lun->requestSenseData.bSenseKey = SBC_SENSE_KEY_NO_SENSE; - lun->requestSenseData.bReserved1 = 0; - lun->requestSenseData.isILI = 0; - lun->requestSenseData.isEOM = 0; - lun->requestSenseData.isFilemark = 0; - lun->requestSenseData.pInformation[0] = 0; - lun->requestSenseData.pInformation[1] = 0; - lun->requestSenseData.pInformation[2] = 0; - lun->requestSenseData.pInformation[3] = 0; - lun->requestSenseData.bAdditionalSenseLength - = sizeof(SBCRequestSenseData) - 8; - lun->requestSenseData.bAdditionalSenseCode = 0; - lun->requestSenseData.bAdditionalSenseCodeQualifier = 0; - lun->requestSenseData.bFieldReplaceableUnitCode = 0; - lun->requestSenseData.bSenseKeySpecific = 0; - lun->requestSenseData.pSenseKeySpecific[0] = 0; - lun->requestSenseData.pSenseKeySpecific[0] = 0; - lun->requestSenseData.isSKSV = 0; - - STORE_DWORDB(0, lun->readCapacityData.pLogicalBlockAddress); - STORE_DWORDB(0, lun->readCapacityData.pLogicalBlockLength); - - // Initialize LUN - lun->media = media; - if (media == 0) { - lun->status = LUN_NOT_PRESENT; - return; - } - - lun->baseAddress = baseAddress; - - // Customized block size - if (blockSize) { - lun->blockSize = blockSize; - } - else { - if (media->blockSize < DEFAULT_LUN_BLOCK_SIZE) - lun->blockSize = DEFAULT_LUN_BLOCK_SIZE / media->blockSize; - else - lun->blockSize = 1; - } - - if (size) { - lun->size = size; - } - else { - lun->size = media->size; - //if (blockSize) - // lun->size = media->size / blockSize; - //else { - // if (media->blockSize < DEFAULT_LUN_BLOCK_SIZE) - // lun->size = media->size / lun->blockSize; - // else - // lun->size = media->size; - //} - } - - TRACE_INFO("LUN: blkSize %d, size %d\n\r", (int)lun->blockSize, (int)lun->size); - if (protected) lun->protected = 1; - else lun->protected = media->protected; - - lun->ioFifo.pBuffer = ioBuffer; - lun->ioFifo.bufferSize = ioBufferSize; - - lun->dataMonitor = dataMonitor; - - // Initialize read capacity data - logicalBlockAddress = lun->size / lun->blockSize - 1; - STORE_DWORDB(logicalBlockAddress, - lun->readCapacityData.pLogicalBlockAddress); - STORE_DWORDB(lun->blockSize * media->blockSize, - lun->readCapacityData.pLogicalBlockLength); - - // Indicate media change - lun->status = LUN_CHANGED; -} - -//------------------------------------------------------------------------------ -//! \brief Eject the media from a LUN -//! \param lun Pointer to the MSDLun instance to initialize -//! \return Operation result code -//------------------------------------------------------------------------------ -unsigned char LUN_Eject(MSDLun *lun) -{ - if (lun->media) { - - // Avoid any LUN R/W in progress - if (lun->media->state == MED_STATE_BUSY) { - - return USBD_STATUS_LOCKED; - } - - // Remove the link of the media - lun->media = 0; - } - // LUN is removed - lun->status = LUN_NOT_PRESENT; - - return USBD_STATUS_SUCCESS; -} - -//------------------------------------------------------------------------------ -//! \brief Writes data on the a LUN starting at the specified block address. -//! \param lun Pointer to a MSDLun instance -//! \param blockAddress First block address to write -//! \param data Pointer to the data to write -//! \param length Number of blocks to write -//! \param callback Optional callback to invoke when the write finishes -//! \return Operation result code -//------------------------------------------------------------------------------ -unsigned char LUN_Write(MSDLun *lun, - unsigned int blockAddress, - void *data, - unsigned int length, - TransferCallback callback, - void *argument) -{ - unsigned int medBlk, medLen; - unsigned char status; - - TRACE_INFO_WP("LUNWrite(%u) ", blockAddress); - - // Check that the data is not too big - if ((length + blockAddress) * lun->blockSize > lun->size) { - - TRACE_WARNING("LUN_Write: Data too big\n\r"); - status = USBD_STATUS_ABORTED; - } - else if (lun->media == 0 || lun->status != LUN_READY) { - - TRACE_WARNING("LUN_Write: Media not ready\n\r"); - status = USBD_STATUS_ABORTED; - } - else if (lun->protected) { - TRACE_WARNING("LUN_Write: LUN is readonly\n\r"); - status = USBD_STATUS_ABORTED; - } - else { - - // Compute write start address - medBlk = lun->baseAddress + blockAddress * lun->blockSize; - medLen = length * lun->blockSize; - - // Start write operation - status = MED_Write(lun->media, - medBlk, - data, - medLen, - (MediaCallback) callback, - argument); - - // Check operation result code - if (status == MED_STATUS_SUCCESS) { - - status = USBD_STATUS_SUCCESS; - } - else { - - TRACE_WARNING("LUN_Write: Cannot write media\n\r"); - status = USBD_STATUS_ABORTED; - } - } - - return status; -} - -//------------------------------------------------------------------------------ -//! \brief Reads data from a LUN, starting at the specified block address. -//! \param lun Pointer to a MSDLun instance -//! \param blockAddress First block address to read -//! \param data Pointer to a data buffer in which to store the data -//! \param length Number of blocks to read -//! \param callback Optional callback to invoke when the read finishes -//! \return Operation result code -//------------------------------------------------------------------------------ -unsigned char LUN_Read(MSDLun *lun, - unsigned int blockAddress, - void *data, - unsigned int length, - TransferCallback callback, - void *argument) -{ - unsigned int medBlk, medLen; - unsigned char status; - - // Check that the data is not too big - if ((length + blockAddress) * lun->blockSize > lun->size) { - - TRACE_WARNING("LUN_Read: Area: (%d + %d)*%d > %d\n\r", - (int)length, (int)blockAddress, (int)lun->blockSize, (int)lun->size); - status = USBD_STATUS_ABORTED; - } - else if (lun->media == 0 || lun->status != LUN_READY) { - - TRACE_WARNING("LUN_Read: Media not present\n\r"); - status = USBD_STATUS_ABORTED; - } - else { - - TRACE_INFO_WP("LUNRead(%u) ", blockAddress); - - // Compute read start address - medBlk = lun->baseAddress + (blockAddress * lun->blockSize); - medLen = length * lun->blockSize; - - // Start write operation - status = MED_Read(lun->media, - medBlk, - data, - medLen, - (MediaCallback) callback, - argument); - - // Check result code - if (status == MED_STATUS_SUCCESS) { - - status = USBD_STATUS_SUCCESS; - } - else { - - TRACE_WARNING("LUN_Read: Cannot read media\n\r"); - status = USBD_STATUS_ABORTED; - } - } - - return status; -} diff --git a/radio/src/targets/sky9x/usb/device/massstorage/MSDLun.h b/radio/src/targets/sky9x/usb/device/massstorage/MSDLun.h deleted file mode 100644 index 92c9120cc..000000000 --- a/radio/src/targets/sky9x/usb/device/massstorage/MSDLun.h +++ /dev/null @@ -1,161 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Logical Unit Number (LUN) used by the Mass Storage driver and the SCSI -/// protocol. Represents a logical hard-drive. -/// -/// !Usage -/// -# Initialize Memory related pins (see pio & board.h). -/// -# Initialize a Media instance for the LUN (see memories). -/// -# Initlalize the LUN with LUN_Init, and link to the initialized Media. -/// -# To read data from the LUN linked media, uses LUN_Read. -/// -# To write data to the LUN linked media, uses LUN_Write. -/// -# To unlink the media, uses LUN_Eject. -//------------------------------------------------------------------------------ - -#ifndef MSDLUN_H -#define MSDLUN_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../Media.h" -#include "../../../usb/device/core/USBD.h" -#include "../../../usb/device/massstorage/MSDIOFifo.h" -#include "../../../usb/device/massstorage/SBC.h" - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -/// LUN RC: success -#define LUN_STATUS_SUCCESS 0x00 -/// LUN RC: error -#define LUN_STATUS_ERROR 0x02 - -/// Media of LUN is removed -#define LUN_NOT_PRESENT 0x00 -/// LUN is ejected by host -#define LUN_EJECTED 0x01 -/// Media of LUN is changed -#define LUN_CHANGED 0x10 -/// LUN Not Ready to Ready transition -#define LUN_TRANS_READY LUN_CHANGED -/// Media of LUN is ready -#define LUN_READY 0x11 - -//------------------------------------------------------------------------------ -// Structures -//------------------------------------------------------------------------------ - -/// LUN structure -typedef struct { - - /// Pointer to a SBCInquiryData instance. - SBCInquiryData *inquiryData; - /// Fifo for USB transfer, must be assigned. - MSDIOFifo ioFifo; - /// Pointer to Media instance for the LUN. - Media *media; - /// Pointer to a Monitor Function to analyze the flow of LUN. - /// \param flowDirection 1 - device to host (READ10) - /// 0 - host to device (WRITE10) - /// \param dataLength Length of data transferred in bytes. - /// \param fifoNullCount Times that FIFO is NULL to wait - /// \param fifoFullCount Times that FIFO is filled to wait - void (*dataMonitor)(unsigned char flowDirection, - unsigned int dataLength, - unsigned int fifoNullCount, - unsigned int fifoFullCount); - /// The start position of the media (blocks) allocated to the LUN. - unsigned int baseAddress; - /// The size of the media (blocks) allocated to the LUN. - unsigned int size; - /// Sector size of the media in number of media blocks - unsigned short blockSize; - /// The LUN can be readonly even the media is writable -#ifdef __cplusplus - unsigned char protectd; -#else - unsigned char protected; -#endif - - /// The LUN status (Ejected/Changed/) - unsigned char status; - - /// Data for the RequestSense command. - SBCRequestSenseData requestSenseData; - /// Data for the ReadCapacity command. - SBCReadCapacity10Data readCapacityData; - -} MSDLun; - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -extern void LUN_Init(MSDLun *lun, - Media *media, - unsigned char *ioBuffer, - unsigned int ioBufferSize, - unsigned int baseAddress, - unsigned int size, - unsigned short blockSize, -#ifdef __cplusplus - unsigned char protectd, -#else - unsigned char protected, -#endif - void (*dataMonitor)(unsigned char flowDirection, - unsigned int dataLength, - unsigned int fifoNullCount, - unsigned int fifoFullCount)); - -extern unsigned char LUN_Eject(MSDLun *lun); - -extern unsigned char LUN_Write(MSDLun *lun, - unsigned int blockAddress, - void *data, - unsigned int length, - TransferCallback callback, - void *argument); - -extern unsigned char LUN_Read(MSDLun *lun, - unsigned int blockAddress, - void *data, - unsigned int length, - TransferCallback callback, - void *argument); - -#endif //#ifndef MSDLUN_H - diff --git a/radio/src/targets/sky9x/usb/device/massstorage/SBC.h b/radio/src/targets/sky9x/usb/device/massstorage/SBC.h deleted file mode 100644 index a8b39820e..000000000 --- a/radio/src/targets/sky9x/usb/device/massstorage/SBC.h +++ /dev/null @@ -1,671 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// SCSI definitions. -/// -/// !Usage -/// -/// -# After command block received, Access and decode the SCSI command block -/// with SBCCommand structure. -//------------------------------------------------------------------------------ - -#ifndef SBC_H -#define SBC_H - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Operation Codes" -/// This page lists operation codes of commands described in the SBC-3 -/// standard. -/// -/// \note That most commands are actually defined in other standards, -/// like SPC-4. Optional commands are not included here. -/// -/// \see sbc3r07.pdf - Section 5.1 - Table 12 -/// \see spc4r06.pdf -/// \see SBCCommand -/// -/// !Codes -/// - SBC_INQUIRY -/// - SBC_READ_10 -/// - SBC_READ_CAPACITY_10 -/// - SBC_REQUEST_SENSE -/// - SBC_TEST_UNIT_READY -/// - SBC_WRITE_10 -/// -/// !Optional Codes but required by Windows -/// - SBC_PREVENT_ALLOW_MEDIUM_REMOVAL -/// - SBC_MODE_SENSE_6 -/// - SBC_VERIFY_10 -/// - SBC_READ_FORMAT_CAPACITIES - -/// Request information regarding parameters of the target and Logical Unit. -#define SBC_INQUIRY 0x12 -/// Request the transfer data to the host. -#define SBC_READ_10 0x28 -/// Request capacities of the currently installed medium. -#define SBC_READ_CAPACITY_10 0x25 -/// Request that the device server transfer sense data. -#define SBC_REQUEST_SENSE 0x03 -/// Check if the LUN is ready -#define SBC_TEST_UNIT_READY 0x00 -/// Request that the device write the data transferred by the host. -#define SBC_WRITE_10 0x2A - -/// Request that the target enable or disable the removal of the medium in -/// the Logical Unit. -#define SBC_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E -/// Report parameters. -#define SBC_MODE_SENSE_6 0x1A -/// Request that the %device verify the data on the medium. -#define SBC_VERIFY_10 0x2F -/// Request a list of the possible capacities that can be formatted on medium -#define SBC_READ_FORMAT_CAPACITIES 0x23 - -#define SBC_START_STOP 0x19 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Periph. Qualifiers" -/// This page lists the peripheral qualifier values specified in the INQUIRY -/// data -/// \see spc4r06.pdf - Section 6.4.2 - Table 83 -/// \see SBCInquiryData -/// -/// !Qualifiers -/// - SBC_PERIPHERAL_DEVICE_CONNECTED -/// - SBC_PERIPHERAL_DEVICE_NOT_CONNECTED -/// - SBC_PERIPHERAL_DEVICE_NOT_SUPPORTED - -#define SBC_PERIPHERAL_DEVICE_CONNECTED 0x00 -#define SBC_PERIPHERAL_DEVICE_NOT_CONNECTED 0x01 -#define SBC_PERIPHERAL_DEVICE_NOT_SUPPORTED 0x03 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Periph. Types" -/// This page lists peripheral device types specified in the INQUIRY data -/// \see spc4r06.pdf - Section 6.4.2 - Table 84 -/// \see SBCInquiryData -/// -/// !Types -/// - SBC_DIRECT_ACCESS_BLOCK_DEVICE -/// - SBC_SEQUENTIAL_ACCESS_DEVICE -/// - SBC_PRINTER_DEVICE -/// - SBC_PROCESSOR_DEVICE -/// - SBC_WRITE_ONCE_DEVICE -/// - SBC_CD_DVD_DEVICE -/// - SBC_SCANNER_DEVICE -/// - SBC_OPTICAL_MEMORY_DEVICE -/// - SBC_MEDIA_CHANGER_DEVICE -/// - SBC_COMMUNICATION_DEVICE -/// - SBC_STORAGE_ARRAY_CONTROLLER_DEVICE -/// - SBC_ENCLOSURE_SERVICES_DEVICE -/// - SBC_SIMPLIFIED_DIRECT_ACCESS_DEVICE -/// - SBC_OPTICAL_CARD_READER_WRITER_DEVICE -/// - SBC_BRIDGE_CONTROLLER_COMMANDS -/// - SBC_OBJECT_BASED_STORAGE_DEVICE - -#define SBC_DIRECT_ACCESS_BLOCK_DEVICE 0x00 -#define SBC_SEQUENTIAL_ACCESS_DEVICE 0x01 -#define SBC_PRINTER_DEVICE 0x02 -#define SBC_PROCESSOR_DEVICE 0x03 -#define SBC_WRITE_ONCE_DEVICE 0x04 -#define SBC_CD_DVD_DEVICE 0x05 -#define SBC_SCANNER_DEVICE 0x06 -#define SBC_OPTICAL_MEMORY_DEVICE 0x07 -#define SBC_MEDIA_CHANGER_DEVICE 0x08 -#define SBC_COMMUNICATION_DEVICE 0x09 -#define SBC_STORAGE_ARRAY_CONTROLLER_DEVICE 0x0C -#define SBC_ENCLOSURE_SERVICES_DEVICE 0x0D -#define SBC_SIMPLIFIED_DIRECT_ACCESS_DEVICE 0x0E -#define SBC_OPTICAL_CARD_READER_WRITER_DEVICE 0x0F -#define SBC_BRIDGE_CONTROLLER_COMMANDS 0x10 -#define SBC_OBJECT_BASED_STORAGE_DEVICE 0x11 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief Version value for the SBC-3 specification -/// \see spc4r06.pdf - Section 6.4.2 - Table 85 -#define SBC_SPC_VERSION_4 0x06 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief Values for the TPGS field returned in INQUIRY data -/// \see spc4r06.pdf - Section 6.4.2 - Table 86 -#define SBC_TPGS_NONE 0x0 -#define SBC_TPGS_ASYMMETRIC 0x1 -#define SBC_TPGS_SYMMETRIC 0x2 -#define SBC_TPGS_BOTH 0x3 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief Version descriptor value for the SBC-3 specification -/// \see spc4r06.pdf - Section 6.4.2 - Table 87 -#define SBC_VERSION_DESCRIPTOR_SBC_3 0x04C0 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Sense Response Codes" -/// This page lists sense data response codes returned in REQUEST SENSE data -/// \see spc4r06.pdf - Section 4.5.1 - Table 12 -/// -/// !Codes -/// - SBC_SENSE_DATA_FIXED_CURRENT -/// - SBC_SENSE_DATA_FIXED_DEFERRED -/// - SBC_SENSE_DATA_DESCRIPTOR_CURRENT -/// - SBC_SENSE_DATA_DESCRIPTOR_DEFERRED - -#define SBC_SENSE_DATA_FIXED_CURRENT 0x70 -#define SBC_SENSE_DATA_FIXED_DEFERRED 0x71 -#define SBC_SENSE_DATA_DESCRIPTOR_CURRENT 0x72 -#define SBC_SENSE_DATA_DESCRIPTOR_DEFERRED 0x73 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Sense Keys" -/// This page lists sense key values returned in the REQUEST SENSE data -/// \see spc4r06.pdf - Section 4.5.6 - Table 27 -/// -/// !Keys -/// - SBC_SENSE_KEY_NO_SENSE -/// - SBC_SENSE_KEY_RECOVERED_ERROR -/// - SBC_SENSE_KEY_NOT_READY -/// - SBC_SENSE_KEY_MEDIUM_ERROR -/// - SBC_SENSE_KEY_HARDWARE_ERROR -/// - SBC_SENSE_KEY_ILLEGAL_REQUEST -/// - SBC_SENSE_KEY_UNIT_ATTENTION -/// - SBC_SENSE_KEY_DATA_PROTECT -/// - SBC_SENSE_KEY_BLANK_CHECK -/// - SBC_SENSE_KEY_VENDOR_SPECIFIC -/// - SBC_SENSE_KEY_COPY_ABORTED -/// - SBC_SENSE_KEY_ABORTED_COMMAND -/// - SBC_SENSE_KEY_VOLUME_OVERFLOW -/// - SBC_SENSE_KEY_MISCOMPARE - -/// No specific sense key. Successful command. -#define SBC_SENSE_KEY_NO_SENSE 0x00 -/// Command completed succesfully with some recovery action by the %device. -#define SBC_SENSE_KEY_RECOVERED_ERROR 0x01 -/// The device can not be accessed. -#define SBC_SENSE_KEY_NOT_READY 0x02 -/// Command terminated with a error condition that was probably caused by a -/// flaw in the medium or an error in the recorded data. -#define SBC_SENSE_KEY_MEDIUM_ERROR 0x03 -/// Hardware failure while performing the command or during a self test. -#define SBC_SENSE_KEY_HARDWARE_ERROR 0x04 -/// Illegal parameter found in the command or additional parameters. -#define SBC_SENSE_KEY_ILLEGAL_REQUEST 0x05 -/// Removable medium may have been changed or the %device has been reset. -#define SBC_SENSE_KEY_UNIT_ATTENTION 0x06 -/// Write on a block that is protected. -#define SBC_SENSE_KEY_DATA_PROTECT 0x07 -/// Indicates that a write-once device or a sequential-access device -/// encountered blank medium or format-defined end-of-data indication while -/// reading or a write-once device encountered a non-blank medium while writing. -#define SBC_SENSE_KEY_BLANK_CHECK 0x08 -/// Reporting vendor specific conditions. -#define SBC_SENSE_KEY_VENDOR_SPECIFIC 0x09 -/// EXTENDED COPY command was aborted. -#define SBC_SENSE_KEY_COPY_ABORTED 0x0A -/// Device aborted the command. -#define SBC_SENSE_KEY_ABORTED_COMMAND 0x0B -/// A buffered peripheral device is overflow. -#define SBC_SENSE_KEY_VOLUME_OVERFLOW 0x0D -/// The source data did not match the data read from the medium. -#define SBC_SENSE_KEY_MISCOMPARE 0x0E -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Sense Additionals" -/// This page lists additional sense code values returned in REQUEST SENSE data -/// \see spc4r06.pdf - Section 4.5.6 - Table 28 -/// -/// !Additional Codes -/// - SBC_ASC_LOGICAL_UNIT_NOT_READY -/// - SBC_ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE -/// - SBC_ASC_INVALID_FIELD_IN_CDB -/// - SBC_ASC_WRITE_PROTECTED -/// - SBC_ASC_FORMAT_CORRUPTED -/// - SBC_ASC_INVALID_COMMAND_OPERATION_CODE -/// - SBC_ASC_TOO_MUCH_WRITE_DATA -/// - SBC_ASC_NOT_READY_TO_READY_CHANGE -/// - SBC_ASC_MEDIUM_NOT_PRESENT - -#define SBC_ASC_LOGICAL_UNIT_NOT_READY 0x04 -#define SBC_ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x21 -#define SBC_ASC_INVALID_FIELD_IN_CDB 0x24 -#define SBC_ASC_WRITE_PROTECTED 0x27 -#define SBC_ASC_FORMAT_CORRUPTED 0x31 -#define SBC_ASC_INVALID_COMMAND_OPERATION_CODE 0x20 -#define SBC_ASC_TOO_MUCH_WRITE_DATA 0x26 -#define SBC_ASC_NOT_READY_TO_READY_CHANGE 0x28 -#define SBC_ASC_MEDIUM_NOT_PRESENT 0x3A -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief MEDIUM TYPE field value for direct-access block devices -/// \see sbc3r06.pdf - Section 6.3.1 -#define SBC_MEDIUM_TYPE_DIRECT_ACCESS_BLOCK_DEVICE 0x00 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief MRIE field values -/// \see sbc3r06.pdf - Section 7.4.11 - Table 286 -#define SBC_MRIE_NO_REPORTING 0x00 -#define SBC_MRIE_ASYNCHRONOUS 0x01 -#define SBC_MRIE_GENERATE_UNIT_ATTENTION 0x02 -#define SBC_MRIE_COND_GENERATE_RECOVERED_ERROR 0x03 -#define SBC_MRIE_UNCOND_GENERATE_RECOVERED_ERROR 0x04 -#define SBC_MRIE_GENERATE_NO_SENSE 0x05 -#define SBC_MRIE_ON_REQUEST 0x06 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \brief Supported mode pages -/// \see sbc3r06.pdf - Section 6.3.1 - Table 115 -#define SBC_PAGE_READ_WRITE_ERROR_RECOVERY 0x01 -#define SBC_PAGE_INFORMATIONAL_EXCEPTIONS_CONTROL 0x1C -#define SBC_PAGE_RETURN_ALL 0x3F -#define SBC_PAGE_VENDOR_SPECIFIC 0x00 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "MSD Endian Macros" -/// This page lists the macros for endianness conversion. -/// -/// !Macros -/// - WORDB -/// - DWORDB -/// - STORE_DWORDB -/// - STORE_WORDB -/// \brief Converts a byte array to a word value using the big endian format -#define WORDB(bytes) ((unsigned short) ((bytes[0] << 8) | bytes[1])) - -/// \brief Converts a byte array to a dword value using the big endian format -#define DWORDB(bytes) ((unsigned int) ((bytes[0] << 24) | (bytes[1] << 16) \ - | (bytes[2] << 8) | bytes[3])) - -/// \brief Stores a dword value in a byte array, in big endian format -#define STORE_DWORDB(dword, bytes) \ - bytes[0] = (unsigned char) (((dword) >> 24) & 0xFF); \ - bytes[1] = (unsigned char) (((dword) >> 16) & 0xFF); \ - bytes[2] = (unsigned char) (((dword) >> 8) & 0xFF); \ - bytes[3] = (unsigned char) ((dword) & 0xFF); - -/// \brief Stores a word value in a byte array, in big endian format -#define STORE_WORDB(word, bytes) \ - bytes[0] = (unsigned char) (((word) >> 8) & 0xFF); \ - bytes[1] = (unsigned char) ((word) & 0xFF); -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Structures -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -/// \brief Structure for the INQUIRY command -/// \see spc4r06.pdf - Section 6.4.1 - Table 81 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x12 : SBC_INQUIRY - unsigned char isEVPD:1, //!< Type of requested data - bReserved1:7; //!< Reserved bits - unsigned char bPageCode; //!< Specifies the VPD to return - unsigned char pAllocationLength[2]; //!< Size of host buffer - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCInquiry; // GCC - -//------------------------------------------------------------------------------ -/// \brief Standard INQUIRY data format returned by the device -/// \see spc4r06.pdf - Section 6.4.2 - Table 82 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bPeripheralDeviceType:5, //!< Peripheral device type - bPeripheralQualifier :3; //!< Peripheral qualifier - unsigned char bReserved1:7, //!< Reserved bits - isRMB :1; //!< Is media removable ? - unsigned char bVersion; //!< SPC version used - unsigned char bResponseDataFormat:4, //!< Must be 0x2 - isHIGHSUP :1, //!< Hierarchical addressing used ? - isNORMACA :1, //!< ACA attribute supported ? - bObsolete1 :2; //!< Obsolete bits - unsigned char bAdditionalLength; //!< Length of remaining INQUIRY data - unsigned char isSCCS :1, //!< Embedded SCC ? - isACC :1, //!< Access control coordinator ? - bTPGS :2, //!< Target port support group - is3PC :1, //!< Third-party copy supported ? - bReserved2:2, //!< Reserved bits - isProtect :1; //!< Protection info supported ? - unsigned char bObsolete2:1, //!< Obsolete bit - isEncServ :1, //!< Embedded enclosure service comp? - isVS :1, //!< ??? - isMultiP :1, //!< Multi-port device ? - bObsolete3:3, //!< Obsolete bits - bUnused1 :1; //!< Unused feature - unsigned char bUnused2:6, //!< Unused features - isCmdQue:1, //!< Task management model supported ? - isVS2 :1; //!< ??? - unsigned char pVendorID[8]; //!< T10 vendor identification - unsigned char pProductID[16]; //!< Vendor-defined product ID - unsigned char pProductRevisionLevel[4];//!< Vendor-defined product revision - unsigned char pVendorSpecific[20]; //!< Vendor-specific data - unsigned char bUnused3; //!< Unused features - unsigned char bReserved3; //!< Reserved bits - unsigned short pVersionDescriptors[8]; //!< Standards the device complies to - unsigned char pReserved4[22]; //!< Reserved bytes - -} __attribute__ ((packed)) SBCInquiryData; // GCC - -//------------------------------------------------------------------------------ -/// \brief Data structure for the READ (10) command -/// \see sbc3r07.pdf - Section 5.7 - Table 34 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x28 : SBC_READ_10 - unsigned char bObsolete1:1, //!< Obsolete bit - isFUA_NV:1, //!< Cache control bit - bReserved1:1, //!< Reserved bit - isFUA:1, //!< Cache control bit - isDPO:1, //!< Cache control bit - bRdProtect:3; //!< Protection information to send - unsigned char pLogicalBlockAddress[4]; //!< Index of first block to read - unsigned char bGroupNumber:5, //!< Information grouping - bReserved2:3; //!< Reserved bits - unsigned char pTransferLength[2]; //!< Number of blocks to transmit - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCRead10; // GCC - -//------------------------------------------------------------------------------ -/// \brief Structure for the READ CAPACITY (10) command -/// \see sbc3r07.pdf - Section 5.11.1 - Table 40 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x25 : RBC_READ_CAPACITY - unsigned char bObsolete1:1, //!< Obsolete bit - bReserved1:7; //!< Reserved bits - unsigned char pLogicalBlockAddress[4]; //!< Block to evaluate if PMI is set - unsigned char pReserved2[2]; //!< Reserved bytes - unsigned char isPMI:1, //!< Partial medium indicator bit - bReserved3:7; //!< Reserved bits - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCReadCapacity10; - -//------------------------------------------------------------------------------ -/// \brief Data returned by the device after a READ CAPACITY (10) command -/// \see sbc3r07.pdf - Section 5.11.2 - Table 41 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char pLogicalBlockAddress[4]; //!< Address of last logical block - unsigned char pLogicalBlockLength[4]; //!< Length of each logical block - -} __attribute__ ((packed)) SBCReadCapacity10Data; - -//------------------------------------------------------------------------------ -/// \brief Structure for the REQUEST SENSE command -/// \see spc4r06.pdf - Section 6.26 - Table 170 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x03 : SBC_REQUEST_SENSE - unsigned char isDesc :1, //!< Type of information expected - bReserved1:7; //!< Reserved bits - unsigned char pReserved2[2]; //!< Reserved bytes - unsigned char bAllocationLength; //!< Size of host buffer - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCRequestSense; - -//------------------------------------------------------------------------------ -/// \brief Fixed format sense data returned after a REQUEST SENSE command has -/// been received with a DESC bit cleared. -/// \see spc4r06.pdf - Section 4.5.3 - Table 26 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bResponseCode:7, //!< Sense data format - isValid :1; //!< Information field is standard - unsigned char bObsolete1; //!< Obsolete byte - unsigned char bSenseKey :4, //!< Generic error information - bReserved1:1, //!< Reserved bit - isILI :1, //!< SSC - isEOM :1, //!< SSC - isFilemark:1; //!< SSC - unsigned char pInformation[4]; //!< Command-specific - unsigned char bAdditionalSenseLength; //!< sizeof(SBCRequestSense_data)-8 - unsigned char pCommandSpecificInformation[4]; //!< Command-specific - unsigned char bAdditionalSenseCode; //!< Additional error information - unsigned char bAdditionalSenseCodeQualifier; //!< Further error information - unsigned char bFieldReplaceableUnitCode; //!< Specific component code - unsigned char bSenseKeySpecific:7, //!< Additional exception info - isSKSV :1; //!< Is sense key specific valid? - unsigned char pSenseKeySpecific[2]; //!< Additional exception info - -} __attribute__ ((packed)) SBCRequestSenseData; - -//------------------------------------------------------------------------------ -/// \brief Data structure for the TEST UNIT READY command -/// \see spc4r06.pdf - Section 6.34 - Table 192 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x00 : SBC_TEST_UNIT_READY - unsigned char pReserved1[4]; //!< Reserved bits - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCTestUnitReady; // GCC - -//------------------------------------------------------------------------------ -/// \brief Structure for the WRITE (10) command -/// \see sbc3r07.pdf - Section 5.26 - Table 70 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x2A : SBC_WRITE_10 - unsigned char bObsolete1:1, //!< Obsolete bit - isFUA_NV:1, //!< Cache control bit - bReserved1:1, //!< Reserved bit - isFUA:1, //!< Cache control bit - isDPO:1, //!< Cache control bit - bWrProtect:3; //!< Protection information to send - unsigned char pLogicalBlockAddress[4]; //!< First block to write - unsigned char bGroupNumber:5, //!< Information grouping - bReserved2:3; //!< Reserved bits - unsigned char pTransferLength[2]; //!< Number of blocks to write - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCWrite10; - -//------------------------------------------------------------------------------ -/// \brief Structure for the PREVENT/ALLOW MEDIUM REMOVAL command -/// \see sbc3r07.pdf - Section 5.5 - Table 30 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x1E : SBC_PREVENT_ALLOW_MEDIUM_REMOVAL - unsigned char pReserved1[3]; //!< Reserved bytes - unsigned char bPrevent:2, //!< Accept/prohibit removal - bReserved2:6; //!< Reserved bits - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCMediumRemoval; // GCC - -//------------------------------------------------------------------------------ -/// \brief Structure for the MODE SENSE (6) command -/// \see spc4r06 - Section 6.9.1 - Table 98 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bOperationCode; //!< 0x1A : SBC_MODE_SENSE_6 - unsigned char bReserved1:3, //!< Reserved bits - isDBD:1, //!< Disable block descriptors bit - bReserved2:4; //!< Reserved bits - unsigned char bPageCode:6, //!< Mode page to return - bPC:2; //!< Type of parameter values to return - unsigned char bSubpageCode; //!< Mode subpage to return - unsigned char bAllocationLength; //!< Host buffer allocated size - unsigned char bControl; //!< 0x00 - -} __attribute__ ((packed)) SBCModeSense6; // GCC - -//------------------------------------------------------------------------------ -/// \brief Header for the data returned after a MODE SENSE (6) command -/// \see spc4r06.pdf - Section 7.4.3 - Table 268 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bModeDataLength; //!< Length of mode data to follow - unsigned char bMediumType; //!< Type of medium (SBC_MEDIUM_TYPE_DIRECT_ACCESS_BLOCK_DEVICE) - unsigned char bReserved1:4, //!< Reserved bits - isDPOFUA:1, //!< DPO/FUA bits supported ? - bReserved2:2, //!< Reserved bits - isWP:1; //!< Is medium write-protected ? - unsigned char bBlockDescriptorLength; //!< Length of all block descriptors - -} __attribute__ ((packed)) SBCModeParameterHeader6; // GCC - -//------------------------------------------------------------------------------ -/// \brief Informational exceptions control mode page -/// \see spc4r06.pdf - Section 7.4.11 - Table 285 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bPageCode:6, //!< 0x1C : SBC_PAGE_INFORMATIONAL_EXCEPTIONS_CONTROL - isSPF:1, //!< Page or subpage data format - isPS:1; //!< Parameters saveable ? - unsigned char bPageLength; //!< Length of page data (0x0A) - unsigned char isLogErr:1, //!< Should informational exceptions be logged ? - isEBackErr:1, //!< Enable background error bit - isTest:1, //!< Create a device test failure ? - isDExcpt:1, //!< Disable exception control bit - isEWasc:1, //!< Report warnings ? - isEBF:1, //!< Enable background function bit - bReserved1:1, //!< Reserved bit - isPerf:1; //!< Delay acceptable when treating exceptions ? - unsigned char bMRIE:4, //!< Method of reporting informational exceptions - bReserved2:4; //!< Reserved bits - unsigned char pIntervalTimer[4]; //!< Error reporting period - unsigned char pReportCount[4]; //!< Maximum number of time a report can be issued - -} __attribute__ ((packed)) SBCInformationalExceptionsControl; // GCC - -//------------------------------------------------------------------------------ -/// \brief Read/write error recovery mode page -/// \see sbc3r07.pdf - Section 6.3.5 - Table 122 -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bPageCode:6, //!< 0x01 : SBC_PAGE_READ_WRITE_ERROR_RECOVERY - isSPF:1, //!< Page or subpage data format - isPS:1; //!< Parameters saveable ? - unsigned char bPageLength; //!< Length of page data (0x0A) - unsigned char isDCR:1, //!< Disable correction bit - isDTE:1, //!< Data terminate on error bit - isPER:1, //!< Post error bit - isEER:1, //!< Enable early recovery bit - isRC:1, //!< Read continuous bit - isTB:1, //!< Transfer block bit - isARRE:1, //!< Automatic read reallocation enabled bit - isAWRE:1; //!< Automatic write reallocation enabled bit - unsigned char bReadRetryCount; //!< Number of retries when reading - unsigned char pObsolete1[3]; //!< Obsolete bytes - unsigned char bReserved1; //!< Reserved byte - unsigned char bWriteRetryCount; //!< Number of retries when writing - unsigned char bReserved2; //!< Reserved byte - unsigned char pRecoveryTimeLimit[2]; //!< Maximum time duration for error recovery - -} __attribute__ ((packed)) SBCReadWriteErrorRecovery; // GCC - -//------------------------------------------------------------------------------ -/// \brief start/stop command -/// \see -//------------------------------------------------------------------------------ -typedef struct { - - unsigned char bModeDataLength; //!< Length of mode data to follow - unsigned char bImmediate:1, //!< - bReserved1:7; //!< Reserved bits - unsigned char pReserved[2]; //!< Reserved bytes - unsigned char startStop:1, //!< DPO/FUA bits supported ? - eject:1, //!< Reserved bits - bReserved2:6; //!< Is medium write-protected ? -} __attribute__ ((packed)) SBCStartStop; // GCC - -//------------------------------------------------------------------------------ -/// \brief Generic structure for holding information about SBC commands -/// \see SBCInquiry -/// \see SBCRead10 -/// \see SBCReadCapacity10 -/// \see SBCRequestSense -/// \see SBCTestUnitReady -/// \see SBCWrite10 -/// \see SBCMediumRemoval -/// \see SBCModeSense6 -//------------------------------------------------------------------------------ -typedef union { - - unsigned char bOperationCode; //!< Operation code of the command - SBCInquiry inquiry; //!< INQUIRY command - SBCRead10 read10; //!< READ (10) command - SBCReadCapacity10 readCapacity10; //!< READ CAPACITY (10) command - SBCRequestSense requestSense; //!< REQUEST SENSE command - SBCTestUnitReady testUnitReady; //!< TEST UNIT READY command - SBCWrite10 write10; //!< WRITE (10) command - SBCMediumRemoval mediumRemoval; //!< PREVENT/ALLOW MEDIUM REMOVAL command - SBCModeSense6 modeSense6; //!< MODE SENSE (6) command - SBCStartStop startStopCmd; //!< START-STOP command - -} SBCCommand; - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -#endif //#ifndef SBC_H - diff --git a/radio/src/targets/sky9x/usb/device/massstorage/SBCMethods.c b/radio/src/targets/sky9x/usb/device/massstorage/SBCMethods.c deleted file mode 100644 index f06454e1b..000000000 --- a/radio/src/targets/sky9x/usb/device/massstorage/SBCMethods.c +++ /dev/null @@ -1,1635 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/device/massstorage/SBCMethods.h" - -#include "../../../usb/device/core/USBD.h" -#include "../../../usb/device/massstorage/MSDDStateMachine.h" -#include "../../../usb/device/massstorage/MSDIOFifo.h" - -//------------------------------------------------------------------------------ -// Global variables -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Macros -//------------------------------------------------------------------------------ - -#ifdef MSDIO_READ10_CHUNK_SIZE -/// READ10 - Read data from specific LUN to FIFO -#define SBC_READ_CHUNK(pLun, lba, pFifo, pCb, pArg) \ - LUN_Read((pLun), (lba), \ - &(pFifo)->pBuffer[(pFifo)->inputNdx], \ - ((pFifo)->chunkSize/(pFifo)->blockSize), \ - (TransferCallback)(pCb), (void*)pArg) -/// READ10 - Transfer data from FIFO to USB -#define SBC_TX_CHUNK(pFifo, pCb, pArg) \ - MSDD_Write(&(pFifo)->pBuffer[(pFifo)->outputNdx], \ - (pFifo)->chunkSize, \ - (TransferCallback)(pCb), (void*)(pArg)) -#endif - -#ifdef MSDIO_WRITE10_CHUNK_SIZE -/// WRITE10 - Read data from USB to FIFO -#define SBC_RX_CHUNK(pFifo,pCb,pArg) \ - MSDD_Read(&(pFifo)->pBuffer[(pFifo)->inputNdx], \ - (pFifo)->chunkSize, \ - (TransferCallback)(pCb), (void*)(pArg)) -/// WRITE10 - Write data from FIFO to LUN -#define SBC_WRITE_CHUNK(pLun, lba, pFifo, pCb, pArg) \ - LUN_Write((pLun), (lba), \ - &(pFifo)->pBuffer[(pFifo)->outputNdx], \ - ((pFifo)->chunkSize/(pFifo)->blockSize), \ - (TransferCallback)(pCb), (void*)(pArg)) -#endif - - -//------------------------------------------------------------------------------ -//! \brief Header for the mode pages data -//! \see SBCModeParameterHeader6 -//------------------------------------------------------------------------------ -static const SBCModeParameterHeader6 modeParameterHeader6 = { - - sizeof(SBCModeParameterHeader6) - 1, //! Length is 0x03 - SBC_MEDIUM_TYPE_DIRECT_ACCESS_BLOCK_DEVICE, //! Direct-access block device - 0, //! Reserved bits - 0, //! DPO/FUA not supported - 0, //! Reserved bits - 0, //! not write-protected - 0 //! No block descriptor -}; - -//------------------------------------------------------------------------------ -// Internal functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -//! \brief Check if the LUN is ready. -//! \param lun Pointer to the LUN affected by the command -//! \return 1 if the LUN is ready to be written -//! \see MSDLun -//------------------------------------------------------------------------------ -static unsigned char SBCLunIsReady(MSDLun *lun) -{ - unsigned char lunIsReady = 0; - Media *media = lun->media; - - if (media == 0 || lun->status < LUN_CHANGED) { - TRACE_INFO("SBCLunIsReady: Not Present!\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_NOT_READY, - SBC_ASC_MEDIUM_NOT_PRESENT, - 0); - - } - else if (lun->status < LUN_READY) { - TRACE_INFO("SBCLunIsReady: Changing!\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_UNIT_ATTENTION, - SBC_ASC_NOT_READY_TO_READY_CHANGE, - 0); - lun->status = LUN_READY; - } - else { - - lunIsReady = 1; - } - - return lunIsReady; -} -//------------------------------------------------------------------------------ -//! \brief Check if the LUN can write. -//! \param lun Pointer to the LUN affected by the command -//! \return 1 if the LUN is ready to be written -//! \see MSDLun -//------------------------------------------------------------------------------ -static unsigned char SBCLunCanBeWritten(MSDLun *lun) -{ - unsigned char canBeWritten = 0; - - if (!SBCLunIsReady(lun)) { - - TRACE_WARNING("SBCLunCanBeWritten: Not Ready!\n\r"); - } - else if (lun->protected) { - - TRACE_WARNING("SBCLunCanBeWritten: Protected!\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_DATA_PROTECT, - SBC_ASC_WRITE_PROTECTED, - 0); - } - else { - - canBeWritten = 1; - } - - return canBeWritten; -} - -//------------------------------------------------------------------------------ -//! \brief Performs a WRITE (10) command on the specified LUN. -//! -//! The data to write is first received from the USB host and then -//! actually written on the media. -//! This function operates asynchronously and must be called multiple -//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE -//! indicates that at least another call of the method is necessary. -//! \param lun Pointer to the LUN affected by the command -//! \param commandState Current state of the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//! \see MSDCommandState -//------------------------------------------------------------------------------ -static unsigned char SBC_Write10(MSDLun *lun, - MSDCommandState *commandState) -{ - unsigned char status; - unsigned char result = MSDD_STATUS_INCOMPLETE; - SBCRead10 *command = (SBCRead10 *) commandState->cbw.pCommand; - MSDTransfer *transfer = &(commandState->transfer); - MSDTransfer *disktransfer = &(commandState->disktransfer); - MSDIOFifo *fifo = &lun->ioFifo; - Media *media = lun->media; - - // Init command state - if (commandState->state == 0) { - - commandState->state = SBC_STATE_WRITE; - - // The command should not be proceeded if READONLY - if (!SBCLunCanBeWritten(lun)) { - - return MSDD_STATUS_RW; - } - else { - - - // Initialize FIFO - fifo->dataTotal = commandState->length; - fifo->blockSize = lun->blockSize * media->blockSize; - #ifdef MSDIO_WRITE10_CHUNK_SIZE - if ( fifo->dataTotal >= 64 * 1024 - && fifo->blockSize < MSDIO_WRITE10_CHUNK_SIZE) - fifo->chunkSize = MSDIO_WRITE10_CHUNK_SIZE; - else - fifo->chunkSize = fifo->blockSize; - #endif - fifo->fullCnt = 0; - fifo->nullCnt = 0; - - // Initialize FIFO output (Disk) - fifo->outputNdx = 0; - fifo->outputTotal = 0; - fifo->outputState = MSDIO_IDLE; - transfer->semaphore = 0; - - // Initialize FIFO input (USB) - fifo->inputNdx = 0; - fifo->inputTotal = 0; - fifo->inputState = MSDIO_START; - disktransfer->semaphore = 0; - } - - } - - if (commandState->length == 0) { - - // Perform the callback! - if (lun->dataMonitor) { - - lun->dataMonitor(0, fifo->dataTotal, fifo->nullCnt, fifo->fullCnt); - } - return MSDD_STATUS_SUCCESS; - } - - // USB receive task - switch(fifo->inputState) { - - //------------------ - case MSDIO_IDLE: - //------------------ - if (fifo->inputTotal < fifo->dataTotal && - fifo->inputTotal - fifo->outputTotal < fifo->bufferSize) { - - fifo->inputState = MSDIO_START; - } - break; - - //------------------ - case MSDIO_START: - //------------------ - // Should not start if there is any disk error - if (fifo->outputState == MSDIO_ERROR) { - - TRACE_INFO_WP("udErr "); - fifo->inputState = MSDIO_ERROR; - break; - } - - // Read one block of data sent by the host - if (media->mappedWR) { - - // Directly read to memory - status = MSDD_Read((void*) - ((media->baseAddress - + (lun->baseAddress - + DWORDB(command->pLogicalBlockAddress) - * lun->blockSize - ) - ) * media->blockSize - ), - fifo->dataTotal, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - } - else { - #ifdef MSDIO_WRITE10_CHUNK_SIZE - status = SBC_RX_CHUNK(fifo, MSDDriver_Callback, transfer); - #else - // Read block to buffer - status = MSDD_Read((void*)&fifo->pBuffer[fifo->inputNdx], - fifo->blockSize, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - #endif - } - - // Check operation result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Write10: Failed to start receiving\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_HARDWARE_ERROR, - 0, - 0); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("uRx "); - - // Prepare next device state - fifo->inputState = MSDIO_WAIT; - } - break; // MSDIO_START - - //------------------ - case MSDIO_WAIT: - //------------------ - TRACE_INFO_WP("uWait "); - - // Check semaphore - if (transfer->semaphore > 0) { - - transfer->semaphore--; - fifo->inputState = MSDIO_NEXT; - } - break; - - //------------------ - case MSDIO_NEXT: - //------------------ - // Check the result code of the read operation - if (transfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Write10: Failed to received\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_HARDWARE_ERROR, - 0, - 0); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("uNxt "); - - // Mapped read, all data done - if (media->mappedWR) { - - fifo->inputTotal = fifo->dataTotal; - fifo->inputState = MSDIO_IDLE; - } - else { - - // Update input index - #ifdef MSDIO_WRITE10_CHUNK_SIZE - MSDIOFifo_IncNdx(fifo->inputNdx, - fifo->chunkSize, - fifo->bufferSize); - fifo->inputTotal += fifo->chunkSize; - #else - MSDIOFifo_IncNdx(fifo->inputNdx, - fifo->blockSize, - fifo->bufferSize); - fifo->inputTotal += fifo->blockSize; - #endif - - // Start Next block - // - All Data done? - if (fifo->inputTotal >= fifo->dataTotal) { - - fifo->inputState = MSDIO_IDLE; - } - // - Buffer full? - else if (fifo->inputNdx == fifo->outputNdx) { - fifo->inputState = MSDIO_IDLE; - fifo->fullCnt ++; - - TRACE_DEBUG_WP("ufFull%d ", fifo->inputNdx); - } - // - More data to transfer? - else if (fifo->inputTotal < fifo->dataTotal) { - fifo->inputState = MSDIO_START; - - TRACE_INFO_WP("uStart "); - } - // never executed ! - //else { - // fifo->inputState = MSDIO_IDLE; - // TRACE_INFO_WP("uDone "); - //} - } - - } - break; // MSDIO_NEXT - - //------------------ - case MSDIO_ERROR: - //------------------ - - TRACE_WARNING_WP("uErr "); - commandState->length -= fifo->inputTotal; - return MSDD_STATUS_RW; - - } - - // Disk write task - switch(fifo->outputState) { - - //------------------ - case MSDIO_IDLE: - //------------------ - if (fifo->outputTotal < fifo->inputTotal) { - - fifo->outputState = MSDIO_START; - } - break; - - //------------------ - case MSDIO_START: - //------------------ - - // Write the block to the media - if (media->mappedWR) { - - MSDDriver_Callback(disktransfer, MED_STATUS_SUCCESS, 0, 0); - status = LUN_STATUS_SUCCESS; - } - else { - #ifdef MSDIO_WRITE10_CHUNK_SIZE - status = SBC_WRITE_CHUNK(lun, DWORDB(command->pLogicalBlockAddress), - fifo, MSDDriver_Callback, disktransfer); - #else - status = LUN_Write(lun, - DWORDB(command->pLogicalBlockAddress), - &fifo->pBuffer[fifo->outputNdx], - 1, - (TransferCallback) MSDDriver_Callback, - (void *) disktransfer); - #endif - } - - // Check operation result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Write10: Failed to start write - "); - - if (!SBCLunCanBeWritten(lun)) { - - TRACE_WARNING("?\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_NOT_READY, - 0, - 0); - } - - fifo->outputState = MSDIO_ERROR; - } - else { - - // Prepare next state - fifo->outputState = MSDIO_WAIT; - } - break; // MSDIO_START - - //------------------ - case MSDIO_WAIT: - //------------------ - TRACE_INFO_WP("dWait "); - - // Check semaphore value - if (disktransfer->semaphore > 0) { - - // Take semaphore and move to next state - disktransfer->semaphore--; - fifo->outputState = MSDIO_NEXT; - } - break; - - //------------------ - case MSDIO_NEXT: - //------------------ - // Check operation result code - if (transfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Write10: Failed to write\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_RECOVERED_ERROR, - SBC_ASC_TOO_MUCH_WRITE_DATA, - 0); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("dNxt "); - - // Update transfer length and block address - - // Mapped memory, done - if (media->mappedWR) { - - commandState->length = 0; - fifo->outputState = MSDIO_IDLE; - } - else { - - // Update output index - #ifdef MSDIO_WRITE10_CHUNK_SIZE - STORE_DWORDB(DWORDB(command->pLogicalBlockAddress) - + fifo->chunkSize/fifo->blockSize, - command->pLogicalBlockAddress); - MSDIOFifo_IncNdx(fifo->outputNdx, - fifo->chunkSize, - fifo->bufferSize); - fifo->outputTotal += fifo->chunkSize; - #else - STORE_DWORDB(DWORDB(command->pLogicalBlockAddress) + 1, - command->pLogicalBlockAddress); - MSDIOFifo_IncNdx(fifo->outputNdx, - fifo->blockSize, - fifo->bufferSize); - fifo->outputTotal += fifo->blockSize; - #endif - - // Start Next block - // - All data done? - if (fifo->outputTotal >= fifo->dataTotal) { - - fifo->outputState = MSDIO_IDLE; - commandState->length = 0; - TRACE_INFO_WP("dDone "); - } - // - Send next? - else if (fifo->outputTotal < fifo->inputTotal) { - - fifo->outputState = MSDIO_START; - TRACE_INFO_WP("dStart "); - } - // - Buffer Null? - else { - fifo->outputState = MSDIO_IDLE; - fifo->nullCnt ++; - - TRACE_DEBUG_WP("dfNull%d ", fifo->outputNdx); - } - } - } - break; // MSDIO_NEXT - - //------------------ - case MSDIO_ERROR: - //------------------ - break; - } - - return result; -} - -//------------------------------------------------------------------------------ -//! \brief Performs a READ (10) command on specified LUN. -//! -//! The data is first read from the media and then sent to the USB host. -//! This function operates asynchronously and must be called multiple -//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE -//! indicates that at least another call of the method is necessary. -//! \param lun Pointer to the LUN affected by the command -//! \param commandState Current state of the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//! \see MSDCommandState -//------------------------------------------------------------------------------ -static unsigned char SBC_Read10(MSDLun *lun, - MSDCommandState *commandState) -{ - unsigned char status; - unsigned char result = MSDD_STATUS_INCOMPLETE; - SBCRead10 *command = (SBCRead10 *) commandState->cbw.pCommand; - MSDTransfer *transfer = &(commandState->transfer); - MSDTransfer *disktransfer = &(commandState->disktransfer); - MSDIOFifo *fifo = &lun->ioFifo; - Media *media = lun->media; - - // Init command state - if (commandState->state == 0) { - - commandState->state = SBC_STATE_READ; - - if (!SBCLunIsReady(lun)) { - - return MSDD_STATUS_RW; - } - else { - - // Initialize FIFO - fifo->dataTotal = commandState->length; - fifo->blockSize = lun->blockSize * media->blockSize; - #ifdef MSDIO_READ10_CHUNK_SIZE - if ( fifo->dataTotal >= 64*1024 - && fifo->blockSize < MSDIO_READ10_CHUNK_SIZE) - fifo->chunkSize = MSDIO_READ10_CHUNK_SIZE; - else - fifo->chunkSize = fifo->blockSize; - #endif - fifo->fullCnt = 0; - fifo->nullCnt = 0; - - #ifdef MSDIO_FIFO_OFFSET - // Enable offset if total size >= 2*bufferSize - if (fifo->dataTotal / fifo->bufferSize >= 2) - fifo->bufferOffset = MSDIO_FIFO_OFFSET; - else - fifo->bufferOffset = 0; - #endif - - // Initialize FIFO output (USB) - fifo->outputNdx = 0; - fifo->outputTotal = 0; - fifo->outputState = MSDIO_IDLE; - transfer->semaphore = 0; - - // Initialize FIFO input (Disk) - fifo->inputNdx = 0; - fifo->inputTotal = 0; - fifo->inputState = MSDIO_START; - disktransfer->semaphore = 0; - } - } - - // Check length - if (commandState->length == 0) { - - // Perform the callback! - if (lun->dataMonitor) { - - lun->dataMonitor(1, fifo->dataTotal, fifo->nullCnt, fifo->fullCnt); - } - return MSDD_STATUS_SUCCESS; - } - - // Disk reading task - switch(fifo->inputState) { - - //------------------ - case MSDIO_IDLE: - //------------------ - if (fifo->inputTotal < fifo->dataTotal && - fifo->inputTotal - fifo->outputTotal < fifo->bufferSize) { - - fifo->inputState = MSDIO_START; - } - break; - - //------------------ - case MSDIO_START: - //------------------ - // Read one block of data from the media - if (media->mappedRD) { - - // Directly write, no read needed - MSDDriver_Callback(disktransfer, MED_STATUS_SUCCESS, 0, 0); - status = LUN_STATUS_SUCCESS; - } - else { - #ifdef MSDIO_READ10_CHUNK_SIZE - status = SBC_READ_CHUNK(lun, DWORDB(command->pLogicalBlockAddress), - fifo, MSDDriver_Callback, disktransfer); - #else - status = LUN_Read(lun, - DWORDB(command->pLogicalBlockAddress), - &fifo->pBuffer[fifo->inputNdx], - 1, - (TransferCallback) MSDDriver_Callback, - (void *)disktransfer); - #endif - } - - // Check operation result code - if (status != LUN_STATUS_SUCCESS) { - - TRACE_WARNING("RBC_Read10: Failed to start reading\n\r"); - - if (SBCLunIsReady(lun)) { - - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_NOT_READY, - SBC_ASC_LOGICAL_UNIT_NOT_READY, - 0); - } - - fifo->inputState = MSDIO_ERROR; - } - else { - - TRACE_INFO_WP("dRd "); - - // Move to next command state - fifo->inputState = MSDIO_WAIT; - } - break; // MSDIO_START - - //------------------ - case MSDIO_WAIT: - //------------------ - // Check semaphore value - if (disktransfer->semaphore > 0) { - - TRACE_INFO_WP("dOk "); - - // Take semaphore and move to next state - disktransfer->semaphore--; - fifo->inputState = MSDIO_NEXT; - } - break; - - //------------------ - case MSDIO_NEXT: - //------------------ - // Check the operation result code - if (disktransfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Read10: Failed to read media\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_RECOVERED_ERROR, - SBC_ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE, - 0); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("dNxt "); - - if (media->mappedRD) { - - // All data is ready - fifo->inputState = MSDIO_IDLE; - fifo->inputTotal = fifo->dataTotal; - } - else { - - // Update block address - #ifdef MSDIO_READ10_CHUNK_SIZE - STORE_DWORDB(DWORDB(command->pLogicalBlockAddress) - + fifo->chunkSize/fifo->blockSize, - command->pLogicalBlockAddress); - - // Update input index - MSDIOFifo_IncNdx(fifo->inputNdx, - fifo->chunkSize, - fifo->bufferSize); - fifo->inputTotal += fifo->chunkSize; - #else - // Update block address - STORE_DWORDB(DWORDB(command->pLogicalBlockAddress) + 1, - command->pLogicalBlockAddress); - - // Update input index - MSDIOFifo_IncNdx(fifo->inputNdx, - fifo->blockSize, - fifo->bufferSize); - fifo->inputTotal += fifo->blockSize; - #endif - - // Start Next block - // - All Data done? - if (fifo->inputTotal >= fifo->dataTotal) { - - TRACE_INFO_WP("dDone "); - fifo->inputState = MSDIO_IDLE; - } - // - Buffer full? - else if (fifo->inputNdx == fifo->outputNdx) { - - TRACE_INFO_WP("dfFull%d ", (int)fifo->inputNdx); - fifo->inputState = MSDIO_IDLE; - fifo->fullCnt ++; - } - // - More data to transfer? - else if (fifo->inputTotal < fifo->dataTotal) { - - TRACE_DEBUG_WP("dStart "); - fifo->inputState = MSDIO_START; - } - } - - } - - break; - - //------------------ - case MSDIO_ERROR: - //------------------ - break; - } - - // USB sending task - switch(fifo->outputState) { - - //------------------ - case MSDIO_IDLE: - //------------------ - if (fifo->outputTotal < fifo->inputTotal) { - - #ifdef MSDIO_FIFO_OFFSET - // Offset buffer the input data - if (fifo->bufferOffset) { - if (fifo->inputTotal < fifo->bufferOffset) { - break; - } - fifo->bufferOffset = 0; - } - #endif - fifo->outputState = MSDIO_START; - } - break; - - //------------------ - case MSDIO_START: - //------------------ - // Should not start if there is any disk error - if (fifo->outputState == MSDIO_ERROR) { - - fifo->inputState = MSDIO_ERROR; - break; - } - - // Send the block to the host - if (media->mappedRD) { - - status = MSDD_Write((void*) - ((media->baseAddress - + (lun->baseAddress - + DWORDB(command->pLogicalBlockAddress) - * lun->blockSize - ) - ) * media->blockSize - ), - commandState->length, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - } - else { - #ifdef MSDIO_READ10_CHUNK_SIZE - status = SBC_TX_CHUNK(fifo, MSDDriver_Callback, transfer); - #else - status = MSDD_Write(&fifo->pBuffer[fifo->outputNdx], - fifo->blockSize, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - #endif - } - // Check operation result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Read10: Failed to start to send\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_HARDWARE_ERROR, - 0, - 0); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("uTx "); - - // Move to next command state - fifo->outputState = MSDIO_WAIT; - } - break; // MSDIO_START - - //------------------ - case MSDIO_WAIT: - //------------------ - // Check semaphore value - if (transfer->semaphore > 0) { - - TRACE_INFO_WP("uOk "); - - // Take semaphore and move to next state - transfer->semaphore--; - fifo->outputState = MSDIO_NEXT; - } - break; - - //------------------ - case MSDIO_NEXT: - //------------------ - // Check operation result code - if (transfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_Read10: Failed to send data\n\r"); - SBC_UpdateSenseData(&(lun->requestSenseData), - SBC_SENSE_KEY_HARDWARE_ERROR, - 0, - 0); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("uNxt "); - - if (media->mappedRD) { - - commandState->length = 0; - } - else { - - // Update output index - #ifdef MSDIO_READ10_CHUNK_SIZE - MSDIOFifo_IncNdx(fifo->outputNdx, - fifo->chunkSize, - fifo->bufferSize); - fifo->outputTotal += fifo->chunkSize; - #else - MSDIOFifo_IncNdx(fifo->outputNdx, - fifo->blockSize, - fifo->bufferSize); - fifo->outputTotal += fifo->blockSize; - #endif - - // Start Next block - // - All data done? - if (fifo->outputTotal >= fifo->dataTotal) { - - fifo->outputState = MSDIO_IDLE; - commandState->length = 0; - TRACE_INFO_WP("uDone "); - } - // - Buffer Null? - else if (fifo->inputNdx == fifo->outputNdx) { - - TRACE_INFO_WP("ufNull%d ", (int)fifo->outputNdx); - fifo->outputState = MSDIO_IDLE; - fifo->nullCnt ++; - } - // - Send next? - else if (fifo->outputTotal < fifo->inputTotal) { - - TRACE_DEBUG_WP("uStart "); - fifo->outputState = MSDIO_START; - } - } - - } - break; - - //------------------ - case MSDIO_ERROR: - //------------------ - break; - } - - return result; -} - -//------------------------------------------------------------------------------ -//! \brief Performs a READ CAPACITY (10) command. -//! -//! This function operates asynchronously and must be called multiple -//! times to complete. A result code of MSDD_STATUS_INCOMPLETE -//! indicates that at least another call of the method is necessary. -//! \param lun Pointer to the LUN affected by the command -//! \param commandState Current state of the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//! \see MSDCommandState -//------------------------------------------------------------------------------ -static unsigned char SBC_ReadCapacity10(MSDLun *lun, - MSDCommandState *commandState) -{ - unsigned char result = MSDD_STATUS_INCOMPLETE; - unsigned char status; - MSDTransfer *transfer = &(commandState->transfer); - - if (!SBCLunIsReady(lun)) { - - TRACE_INFO("SBC_ReadCapacity10: Not Ready!\n\r"); - return MSDD_STATUS_RW; - } - - // Initialize command state if needed - if (commandState->state == 0) { - - commandState->state = SBC_STATE_WRITE; - } - - // Identify current command state - switch (commandState->state) { - //------------------- - case SBC_STATE_WRITE: - //------------------- - // Start the write operation - status = MSDD_Write(&(lun->readCapacityData), - commandState->length, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - - // Check operation result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_ReadCapacity: Cannot start sending data\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - // Proceed to next command state - TRACE_INFO_WP("Sending "); - commandState->state = SBC_STATE_WAIT_WRITE; - } - break; - - //------------------------ - case SBC_STATE_WAIT_WRITE: - //------------------------ - // Check semaphore value - if (transfer->semaphore > 0) { - - // Take semaphore and terminate command - transfer->semaphore--; - - if (transfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING("RBC_ReadCapacity: Cannot send data\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("Sent "); - result = MSDD_STATUS_SUCCESS; - } - commandState->length -= transfer->transferred; - } - break; - } - - return result; -} - -//------------------------------------------------------------------------------ -//! \brief Handles an INQUIRY command. -//! -//! This function operates asynchronously and must be called multiple -//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE -//! indicates that at least another call of the method is necessary. -//! \param lun Pointer to the LUN affected by the command -//! \param commandState Current state of the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//! \see MSDCommandState -//------------------------------------------------------------------------------ -static unsigned char SBC_Inquiry(MSDLun *lun, - MSDCommandState *commandState) -{ - unsigned char result = MSDD_STATUS_INCOMPLETE; - unsigned char status; - MSDTransfer *transfer = &(commandState->transfer); - - // Check if required length is 0 - if (commandState->length == 0) { - - // Nothing to do - result = MSDD_STATUS_SUCCESS; - } - // Initialize command state if needed - else if (commandState->state == 0) { - - commandState->state = SBC_STATE_WRITE; - - // Change additional length field of inquiry data - lun->inquiryData->bAdditionalLength - = (unsigned char) (commandState->length - 5); - } - - // Identify current command state - switch (commandState->state) { - //------------------- - case SBC_STATE_WRITE: - //------------------- - // Start write operation - status = MSDD_Write((void *) lun->inquiryData, - commandState->length, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - - // Check operation result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "SPC_Inquiry: Cannot start sending data\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - // Proceed to next state - TRACE_INFO_WP("Sending "); - commandState->state = SBC_STATE_WAIT_WRITE; - } - break; - - //------------------------ - case SBC_STATE_WAIT_WRITE: - //------------------------ - // Check the semaphore value - if (transfer->semaphore > 0) { - - // Take semaphore and terminate command - transfer->semaphore--; - - if (transfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "SPC_Inquiry: Data transfer failed\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - TRACE_INFO_WP("Sent "); - result = MSDD_STATUS_SUCCESS; - } - - // Update length field - commandState->length -= transfer->transferred; - } - break; - } - - return result; -} - -//------------------------------------------------------------------------------ -//! \brief Performs a REQUEST SENSE command. -//! -//! This function operates asynchronously and must be called multiple -//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE -//! indicates that at least another call of the method is necessary. -//! \param lun Pointer to the LUN affected by the command -//! \param commandState Current state of the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//! \see MSDCommandState -//------------------------------------------------------------------------------ -static unsigned char SBC_RequestSense(MSDLun *lun, - MSDCommandState *commandState) -{ - unsigned char result = MSDD_STATUS_INCOMPLETE; - unsigned char status; - MSDTransfer *transfer = &(commandState->transfer); - - // Check if requested length is zero - if (commandState->length == 0) { - - // Nothing to do - result = MSDD_STATUS_SUCCESS; - } - // Initialize command state if needed - else if (commandState->state == 0) { - - commandState->state = SBC_STATE_WRITE; - } - - // Identify current command state - switch (commandState->state) { - //------------------- - case SBC_STATE_WRITE: - //------------------- - // Start transfer - status = MSDD_Write(&(lun->requestSenseData), - commandState->length, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - - // Check result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "RBC_RequestSense: Cannot start sending data\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - // Change state - commandState->state = SBC_STATE_WAIT_WRITE; - } - break; - - //------------------------ - case SBC_STATE_WAIT_WRITE: - //------------------------ - // Check the transfer semaphore - if (transfer->semaphore > 0) { - - // Take semaphore and finish command - transfer->semaphore--; - - if (transfer->status != USBD_STATUS_SUCCESS) { - - result = MSDD_STATUS_ERROR; - } - else { - - result = MSDD_STATUS_SUCCESS; - } - - // Update length - commandState->length -= transfer->transferred; - } - break; - } - - return result; -} - -//------------------------------------------------------------------------------ -//! \brief Performs a MODE SENSE (6) command. -//! -//! This function operates asynchronously and must be called multiple -//! times to complete. A result code of MSDDriver_STATUS_INCOMPLETE -//! indicates that at least another call of the method is necessary. -//! \param lun Pointer to the LUN affected by the command -//! \param commandState Current state of the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//! \see MSDCommandState -//------------------------------------------------------------------------------ -static unsigned char SBC_ModeSense6(MSDLun *lun, MSDCommandState *commandState) -{ - unsigned char result = MSDD_STATUS_INCOMPLETE; - unsigned char status; - MSDTransfer *transfer = &(commandState->transfer); - - if (!SBCLunIsReady(lun)) { - - TRACE_INFO("SBC_ModeSense6: Not Ready!\n\r"); - return MSDD_STATUS_RW; - } - - // Check if mode page is supported - if (((SBCCommand *) commandState->cbw.pCommand)->modeSense6.bPageCode - != SBC_PAGE_RETURN_ALL) { - - return MSDD_STATUS_PARAMETER; - } - - // Initialize command state if needed - if (commandState->state == 0) { - - commandState->state = SBC_STATE_WRITE; - } - - // Check current command state - switch (commandState->state) { - //------------------- - case SBC_STATE_WRITE: - //------------------- - // Start transfer - status = MSDD_Write((void *) &modeParameterHeader6, - commandState->length, - (TransferCallback) MSDDriver_Callback, - (void *) transfer); - - // Check operation result code - if (status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "SPC_ModeSense6: Cannot start data transfer\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - // Proceed to next state - commandState->state = SBC_STATE_WAIT_WRITE; - } - break; - - //------------------------ - case SBC_STATE_WAIT_WRITE: - //------------------------ - TRACE_INFO_WP("Wait "); - - // Check semaphore value - if (transfer->semaphore > 0) { - - // Take semaphore and terminate command - transfer->semaphore--; - - if (transfer->status != USBD_STATUS_SUCCESS) { - - TRACE_WARNING( - "SPC_ModeSense6: Data transfer failed\n\r"); - result = MSDD_STATUS_ERROR; - } - else { - - result = MSDD_STATUS_SUCCESS; - } - - // Update length field - commandState->length -= transfer->transferred; - - } - break; - } - - return result; -} - -//------------------------------------------------------------------------------ -//! \brief Performs a TEST UNIT READY COMMAND command. -//! \param lun Pointer to the LUN affected by the command -//! \return Operation result code (SUCCESS, ERROR, INCOMPLETE or PARAMETER) -//! \see MSDLun -//------------------------------------------------------------------------------ -static unsigned char SBC_TestUnitReady(MSDLun *lun) -{ - unsigned char result = MSDD_STATUS_RW; - unsigned char senseKey = SBC_SENSE_KEY_NO_SENSE, - addSenseCode = 0, - addSenseCodeQual = 0; - Media *media = lun->media; - - // Check current media state - if (lun->status < LUN_CHANGED) { - - TRACE_INFO_WP("Ejc "); - senseKey = SBC_SENSE_KEY_NOT_READY; - addSenseCode = SBC_ASC_MEDIUM_NOT_PRESENT; - } - else if (lun->status == LUN_CHANGED) { - - TRACE_INFO_WP("Chg "); - senseKey = SBC_SENSE_KEY_UNIT_ATTENTION; - addSenseCode = SBC_ASC_NOT_READY_TO_READY_CHANGE; - lun->status = LUN_READY; - } - else { - - switch(media->state) { - //------------------- - case MED_STATE_READY: - //------------------- - // Nothing to do - TRACE_INFO_WP("Rdy "); - result = MSDD_STATUS_SUCCESS; - break; - - //------------------ - case MED_STATE_BUSY: - //------------------ - TRACE_INFO_WP("Bsy "); - senseKey = SBC_SENSE_KEY_NOT_READY; - break; - - //------ - default: - //------ - TRACE_INFO_WP("? "); - senseKey = SBC_SENSE_KEY_NOT_READY; - addSenseCode = SBC_ASC_MEDIUM_NOT_PRESENT; - break; - } - } - SBC_UpdateSenseData(&(lun->requestSenseData), - senseKey, - addSenseCode, - addSenseCodeQual); - - return result; -} - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -//! \brief Updates the sense data of a LUN with the given key and codes -//! \param requestSenseData Pointer to the sense data to update -//! \param senseKey Sense key -//! \param additionalSenseCode Additional sense code -//! \param additionalSenseCodeQualifier Additional sense code qualifier -//------------------------------------------------------------------------------ -void SBC_UpdateSenseData(SBCRequestSenseData *requestSenseData, - unsigned char senseKey, - unsigned char additionalSenseCode, - unsigned char additionalSenseCodeQualifier) -{ - requestSenseData->bSenseKey = senseKey; - requestSenseData->bAdditionalSenseCode = additionalSenseCode; - requestSenseData->bAdditionalSenseCodeQualifier - = additionalSenseCodeQualifier; -} - -//------------------------------------------------------------------------------ -//! \brief Return information about the transfer length and direction expected -//! by the device for a particular command. -//! \param command Pointer to a buffer holding the command to evaluate -//! \param length Expected length of the data transfer -//! \param type Expected direction of data transfer -//! \param lun Pointer to the LUN affected by the command -//------------------------------------------------------------------------------ -unsigned char SBC_GetCommandInformation(void *command, - unsigned int *length, - unsigned char *type, - MSDLun *lun) -{ - SBCCommand *sbcCommand = (SBCCommand *) command; - unsigned char isCommandSupported = 1; - Media *media = lun->media; - - // Identify command - switch (sbcCommand->bOperationCode) { - //--------------- - case SBC_INQUIRY: - //--------------- - (*type) = MSDD_DEVICE_TO_HOST; - - // Allocation length is stored in big-endian format - (*length) = WORDB(sbcCommand->inquiry.pAllocationLength); - break; - - //-------------------- - case SBC_MODE_SENSE_6: - //-------------------- - (*type) = MSDD_DEVICE_TO_HOST; - if (sbcCommand->modeSense6.bAllocationLength > - sizeof(SBCModeParameterHeader6)) { - - *length = sizeof(SBCModeParameterHeader6); - } - else { - - *length = sbcCommand->modeSense6.bAllocationLength; - } - break; - - //------------------------------------ - case SBC_PREVENT_ALLOW_MEDIUM_REMOVAL: - case SBC_START_STOP: - //------------------------------------ - (*type) = MSDD_NO_TRANSFER; - break; - - //--------------------- - case SBC_REQUEST_SENSE: - //--------------------- - (*type) = MSDD_DEVICE_TO_HOST; - (*length) = sbcCommand->requestSense.bAllocationLength; - break; - - //----------------------- - case SBC_TEST_UNIT_READY: - //----------------------- - (*type) = MSDD_NO_TRANSFER; - break; - - //--------------------- - case SBC_READ_CAPACITY_10: - //--------------------- - (*type) = MSDD_DEVICE_TO_HOST; - (*length) = sizeof(SBCReadCapacity10Data); - break; - - //--------------- - case SBC_READ_10: - //--------------- - (*type) = MSDD_DEVICE_TO_HOST; - (*length) = WORDB(sbcCommand->read10.pTransferLength) - * lun->blockSize * media->blockSize; - break; - - //---------------- - case SBC_WRITE_10: - //---------------- - (*type) = MSDD_HOST_TO_DEVICE; - (*length) = WORDB(sbcCommand->write10.pTransferLength) - * lun->blockSize * media->blockSize; - break; - - //----------------- - case SBC_VERIFY_10: - //----------------- - (*type) = MSDD_NO_TRANSFER; - break; - #if 0 - //--------------------- - case SBC_READ_FORMAT_CAPACITIES: - //--------------------- - (*type) = MSDD_DEVICE_TO_HOST; - (*length) = 1; - break; - #endif - //------ - default: - //------ - isCommandSupported = 0; - } - - // If length is 0, no transfer is expected - if ((*length) == 0) { - - (*type) = MSDD_NO_TRANSFER; - } - - return isCommandSupported; -} - -//------------------------------------------------------------------------------ -//! \brief Processes a SBC command by dispatching it to a subfunction. -//! \param lun Pointer to the affected LUN -//! \param commandState Pointer to the current command state -//! \return Operation result code -//------------------------------------------------------------------------------ -unsigned char SBC_ProcessCommand(MSDLun *lun, - MSDCommandState *commandState) -{ - unsigned char result = MSDD_STATUS_INCOMPLETE; - SBCCommand *command = (SBCCommand *) commandState->cbw.pCommand; - Media *media = lun->media; - - // Identify command - switch (command->bOperationCode) { - //--------------- - case SBC_READ_10: - //--------------- - TRACE_DEBUG_WP("Read(10) "); - - // Perform the Read10 command - result = SBC_Read10(lun, commandState); - break; - - //---------------- - case SBC_WRITE_10: - //---------------- - TRACE_DEBUG_WP("Write(10) "); - - // Perform the Write10 command - result = SBC_Write10(lun, commandState); - break; - - //--------------------- - case SBC_READ_CAPACITY_10: - //--------------------- - TRACE_INFO_WP("RdCapacity(10) "); - - // Perform the ReadCapacity command - result = SBC_ReadCapacity10(lun, commandState); - break; - - //--------------------- - case SBC_VERIFY_10: - //--------------------- - TRACE_INFO_WP("Verify(10) "); - - // Flush media - MED_Flush(media); - result = MSDD_STATUS_SUCCESS; - break; - - //--------------- - case SBC_INQUIRY: - //--------------- - TRACE_INFO_WP("Inquiry "); - - // Process Inquiry command - result = SBC_Inquiry(lun, commandState); - break; - - //-------------------- - case SBC_MODE_SENSE_6: - //-------------------- - TRACE_INFO_WP("ModeSense(6) "); - - // Process ModeSense6 command - result = SBC_ModeSense6(lun, commandState); - break; - - //----------------------- - case SBC_TEST_UNIT_READY: - //----------------------- - TRACE_INFO_WP("TstUnitRdy "); - - // Process TestUnitReady command - //MED_Flush(media); - result = SBC_TestUnitReady(lun); - break; - - //--------------------- - case SBC_REQUEST_SENSE: - //--------------------- - TRACE_INFO_WP("ReqSense "); - - // Perform the RequestSense command - result = SBC_RequestSense(lun, commandState); - break; - - //------------------------------------ - case SBC_PREVENT_ALLOW_MEDIUM_REMOVAL: - //------------------------------------ - TRACE_INFO_WP("PrevAllowRem "); - - // Check parameter - result = command->mediumRemoval.bPrevent ? - MSDD_STATUS_PARAMETER : MSDD_STATUS_SUCCESS; - result = MSDD_STATUS_SUCCESS; - break; - - case SBC_START_STOP: - TRACE_INFO_WP("StartStop "); - - result = command->startStopCmd.startStop ; - if (result == 0) { - lun->status = LUN_EJECTED ; - } - else { - lun->status = LUN_CHANGED ; - } - result = MSDD_STATUS_SUCCESS; - break; - - #if 0 - //------------------------------------ - case SBC_READ_FORMAT_CAPACITIES: - //------------------------------------ - TRACE_INFO_WP("RdFmtCap "); - result = MSDD_STATUS_RW; - break; - /* TODO BSS Added if (!SBCLunIsReady(lun)) { - - result = MSDD_STATUS_RW; - break; - } */ - #endif - //------ - default: - //------ - result = MSDD_STATUS_PARAMETER; - } - - return result; -} diff --git a/radio/src/targets/sky9x/usb/device/massstorage/SBCMethods.h b/radio/src/targets/sky9x/usb/device/massstorage/SBCMethods.h deleted file mode 100644 index 09d049ec6..000000000 --- a/radio/src/targets/sky9x/usb/device/massstorage/SBCMethods.h +++ /dev/null @@ -1,110 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// SCSI commands implementation. -/// -/// !Usage -/// -/// -# After a CBW is received from host, use SBC_GetCommandInformation to check -/// if the command is supported, and get the command length and type -/// information before processing it. -/// -# Then SBC_ProcessCommand can be used to handle a valid command, to -/// perform the command operations. -/// -# SBC_UpdateSenseData is used to update the sense data that will be sent -/// to host. -//------------------------------------------------------------------------------ - -#ifndef SBCMETHODS_H -#define SBCMETHODS_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "../../../usb/device/massstorage/MSDDStateMachine.h" -#include "../../../usb/device/massstorage/SBC.h" - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "SBC Command States" -/// This page lists the possible states of a SBC command. -/// -/// !States -/// - SBC_STATE_READ -/// - SBC_STATE_WAIT_READ -/// - SBC_STATE_WRITE -/// - SBC_STATE_WAIT_WRITE -/// - SBC_STATE_NEXT_BLOCK - -/// Start of reading bulk data -#define SBC_STATE_READ 0x01 -/// Waiting for the bulk data reading complete -#define SBC_STATE_WAIT_READ 0x02 -/// Read error state -#define SBC_STATE_READ_ERROR 0x03 -/// Start next read block -#define SBC_STATE_NEXT_READ 0x04 -/// Start writing bulk data to host -#define SBC_STATE_WRITE 0x05 -/// Waiting for the bulk data sending complete -#define SBC_STATE_WAIT_WRITE 0x06 -/// Write error state -#define SBC_STATE_WRITE_ERROR 0x07 -/// Start next write block -#define SBC_STATE_NEXT_WRITE 0x08 -/// Start next command block -#define SBC_STATE_NEXT_BLOCK 0x09 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -void SBC_UpdateSenseData(SBCRequestSenseData *requestSenseData, - unsigned char senseKey, - unsigned char additionalSenseCode, - unsigned char additionalSenseCodeQualifier); - -unsigned char SBC_GetCommandInformation(void *command, - unsigned int *length, - unsigned char *type, - MSDLun *lun); - -unsigned char SBC_ProcessCommand(MSDLun *lun, - MSDCommandState *commandState); - -#endif //#ifndef SBCMETHODS_H - diff --git a/radio/src/targets/sky9x/usb_driver.cpp b/radio/src/targets/sky9x/usb_driver.cpp deleted file mode 100644 index 8435def7d..000000000 --- a/radio/src/targets/sky9x/usb_driver.cpp +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// TODO: enable masstorage & implement choice between masstorage and joystick - -extern "C" { -#include "usb/device/hid-joystick/HIDDJoystickDriver.h" -#include "usb/device/massstorage/MSDDriver.h" -} - -extern "C" void USBDDriverCallbacks_ConfigurationChanged(unsigned char cfgnum) -{ -// if (selectedUsbMode == USB_JOYSTICK_MODE) { - (void)cfgnum; -// } else if (selectedUsbMode == USB_MASS_STORAGE_MODE){ -// MSDDriver_Reset(); -// } -} - -extern "C" void USBDCallbacks_RequestReceived(const USBGenericRequest *request) -{ -// if (selectedUsbMode == USB_JOYSTICK_MODE) { - HIDDJoystickDriver_RequestHandler(request); -// } else if (selectedUsbMode == USB_MASS_STORAGE_MODE){ -// MSDDriver_RequestHandler(request); -// } -} diff --git a/radio/src/targets/sky9x/vectors_sam3s.c b/radio/src/targets/sky9x/vectors_sam3s.c deleted file mode 100644 index b03d8cdca..000000000 --- a/radio/src/targets/sky9x/vectors_sam3s.c +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __VECTORS_SAM3S_C__ - -#include "debug.h" - -/*=========================================================================*/ -/* DEFINE: All extern Data */ -/*=========================================================================*/ -extern unsigned long _estack; - -/*=========================================================================*/ -/* DEFINE: Prototypes */ -/*=========================================================================*/ -void ResetHandler(void); - -void NMI_Handler (void) __attribute__((weak)); -void HardFault_Handler (void) __attribute__((weak)); -void MemManage_Handler (void) __attribute__((weak)); -void BusFault_Handler (void) __attribute__((weak)); -void UsageFault_Handler (void) __attribute__((weak)); -void SVC_Handler (void) __attribute__((weak)); -void DebugMon_Handler (void) __attribute__((weak)); -void PendSV_Handler(void) __attribute__((weak)); -void SysTick_Handler (void) __attribute__((weak)); -void SUPC_IRQHandler (void) __attribute__((weak)); -void RSTC_IRQHandler (void) __attribute__((weak)); -void RTC_IRQHandler (void) __attribute__((weak)); -void RTT_IRQHandler (void) __attribute__((weak)); -void WDT_IRQHandler (void) __attribute__((weak)); -void PMC_IRQHandler (void) __attribute__((weak)); -void EEFC_IRQHandler (void) __attribute__((weak)); -void UART0_IRQHandler (void) __attribute__((weak)); -void UART1_IRQHandler (void) __attribute__((weak)); -void SMC_IRQHandler (void) __attribute__((weak)); -void PIOA_IRQHandler (void) __attribute__((weak)); -void PIOB_IRQHandler (void) __attribute__((weak)); -void PIOC_IRQHandler (void) __attribute__((weak)); -void USART0_IRQHandler (void) __attribute__((weak)); -void USART1_IRQHandler (void) __attribute__((weak)); -void MCI_IRQHandler (void) __attribute__((weak)); -void TWI0_IRQHandler (void) __attribute__((weak)); -void TWI1_IRQHandler (void) __attribute__((weak)); -void SPI_IRQHandler (void) __attribute__((weak)); -void SSC_IRQHandler (void) __attribute__((weak)); -void TC0_IRQHandler (void) __attribute__((weak)); -void TC1_IRQHandler (void) __attribute__((weak)); -void TC2_IRQHandler (void) __attribute__((weak)); -void TC3_IRQHandler (void) __attribute__((weak)); -void TC4_IRQHandler (void) __attribute__((weak)); -void TC5_IRQHandler (void) __attribute__((weak)); -void ADC_IRQHandler (void) __attribute__((weak)); -void DAC_IRQHandler (void) __attribute__((weak)); -void PWM_IRQHandler (void) __attribute__((weak)); -void CRCCU_IRQHandler (void) __attribute__((weak)); -void ACC_IRQHandler (void) __attribute__((weak)); -void USBD_IrqHandler (void) __attribute__((weak)); - -/*=========================================================================*/ -/* DEFINE: All code exported */ -/*=========================================================================*/ -/* - * This is our vector table. - */ -__attribute__ ((section(".vectors"), used)) -void (* const gVectors[])(void) = -{ - (void (*)(void))((unsigned long)&_estack), - ResetHandler, - NMI_Handler, - HardFault_Handler, - MemManage_Handler, - BusFault_Handler, - UsageFault_Handler, - 0, 0, 0, 0, - SVC_Handler, - DebugMon_Handler, - 0, - PendSV_Handler, - SysTick_Handler, - - SUPC_IRQHandler, /* 0 SUPPLY CONTROLLER */ - RSTC_IRQHandler, /* 1 RESET CONTROLLER */ - RTC_IRQHandler, /* 2 REAL TIME CLOCK */ - RTT_IRQHandler, /* 3 REAL TIME TIMER */ - WDT_IRQHandler, /* 4 WATCHDOG TIMER */ - PMC_IRQHandler, /* 5 PMC */ - EEFC_IRQHandler, /* 6 EEFC */ - 0, /* 7 Reserved */ - UART0_IRQHandler, /* 8 UART0 */ - UART1_IRQHandler, /* 9 UART1 */ - SMC_IRQHandler, /* 10 SMC */ - PIOA_IRQHandler, /* 11 Parallel IO Controller A */ - PIOB_IRQHandler, /* 12 Parallel IO Controller B */ - PIOC_IRQHandler, /* 13 Parallel IO Controller C */ - USART0_IRQHandler, /* 14 USART 0 */ - USART1_IRQHandler, /* 15 USART 1 */ - 0, /* 16 Reserved */ - 0, /* 17 Reserved */ - MCI_IRQHandler, /* 18 MCI */ - TWI0_IRQHandler, /* 19 TWI 0 */ - TWI1_IRQHandler, /* 20 TWI 1 */ - SPI_IRQHandler, /* 21 SPI */ - SSC_IRQHandler, /* 22 SSC */ - TC0_IRQHandler, /* 23 Timer Counter 0 */ - TC1_IRQHandler, /* 24 Timer Counter 1 */ - TC2_IRQHandler, /* 25 Timer Counter 2 */ - TC3_IRQHandler, /* 26 Timer Counter 3 */ - TC4_IRQHandler, /* 27 Timer Counter 4 */ - TC5_IRQHandler, /* 28 Timer Counter 5 */ - ADC_IRQHandler, /* 29 ADC controller */ - DAC_IRQHandler, /* 30 DAC controller */ - PWM_IRQHandler, /* 31 PWM */ - CRCCU_IRQHandler, /* 32 CRC Calculation Unit */ - ACC_IRQHandler, /* 33 Analog Comparator */ - USBD_IrqHandler, /* 34 USB Device Port */ - 0 /* 35 not used */ -}; /* gVectors */ - -/* - * And here are the weak interrupt handlers. - */ -void NMI_Handler (void) { while(1); } -void HardFault_Handler (void) { while(1); } -void MemManage_Handler (void) { while(1); } -void BusFault_Handler (void) { while(1); } -void UsageFault_Handler (void) { while(1); } -void SVC_Handler (void) { while(1); } -void DebugMon_Handler (void) { while(1); } -void SUPC_IRQHandler (void) { while(1); } -void RSTC_IRQHandler (void) { while(1); } -void RTC_IRQHandler (void) { while(1); } -void RTT_IRQHandler (void) { while(1); } -void WDT_IRQHandler (void) { while(1); } -void PMC_IRQHandler (void) { while(1); } -void EEFC_IRQHandler (void) { while(1); } -void UART1_IRQHandler (void) { while(1); } -void SMC_IRQHandler (void) { while(1); } -void PIOA_IRQHandler (void) { while(1); } -void PIOB_IRQHandler (void) { while(1); } -void PIOC_IRQHandler (void) { while(1); } -void USART0_IRQHandler (void) { while(1); } -void USART1_IRQHandler (void) { while(1); } -void MCI_IRQHandler (void) { while(1); } -void TWI1_IRQHandler (void) { while(1); } -void SSC_IRQHandler (void) { while(1); } -void TC0_IRQHandler (void) { while(1); } -void TC1_IRQHandler (void) { while(1); } -void TC4_IRQHandler (void) { while(1); } -void TC5_IRQHandler (void) { while(1); } -void ADC_IRQHandler (void) { while(1); } -void CRCCU_IRQHandler (void) { while(1); } -void ACC_IRQHandler (void) { while(1); } - -/*** EOF ***/ diff --git a/radio/src/telemetry/frsky.cpp b/radio/src/telemetry/frsky.cpp index 592441463..85b72e75e 100644 --- a/radio/src/telemetry/frsky.cpp +++ b/radio/src/telemetry/frsky.cpp @@ -23,10 +23,6 @@ void processFrskyTelemetryData(uint8_t data) { -#if defined(PCBSKY9X) && defined(BLUETOOTH) - // TODO if (g_model.bt_telemetry) - btPushByte(data); -#endif #if defined(AUX_SERIAL) if (g_eeGeneral.auxSerialMode == UART_MODE_TELEMETRY_MIRROR) { diff --git a/radio/src/telemetry/telemetry.cpp b/radio/src/telemetry/telemetry.cpp index 6748b3c59..6adad1acc 100644 --- a/radio/src/telemetry/telemetry.cpp +++ b/radio/src/telemetry/telemetry.cpp @@ -420,7 +420,7 @@ void telemetryInit(uint8_t protocol) } #endif -#if defined(AUX_SERIAL) || defined(PCBSKY9X) +#if defined(AUX_SERIAL) else if (protocol == PROTOCOL_TELEMETRY_FRSKY_D_SECONDARY) { telemetryPortInit(0, TELEMETRY_SERIAL_DEFAULT); auxSerialTelemetryInit(PROTOCOL_TELEMETRY_FRSKY_D_SECONDARY); @@ -448,14 +448,6 @@ void telemetryInit(uint8_t protocol) #endif } -#if defined(REVX) && !defined(SIMU) - if (serialInversion) { - setMFP(); - } - else { - clearMFP(); - } -#endif } diff --git a/radio/src/telemetry/telemetry_sensors.cpp b/radio/src/telemetry/telemetry_sensors.cpp index 68db4066a..0a8f3dbbf 100644 --- a/radio/src/telemetry/telemetry_sensors.cpp +++ b/radio/src/telemetry/telemetry_sensors.cpp @@ -372,20 +372,11 @@ void TelemetryItem::eval(const TelemetrySensor & sensor) } } uint32_t angle = abs(gpsItem.gps.latitude - gpsItem.pilotLatitude); -#if defined(STM32) uint32_t dist = uint64_t(EARTH_RADIUS * M_PI / 180) * angle / 1000000; -#else - // TODO search later why it breaks Sky9x - uint32_t dist = EARTH_RADIUS * angle / 1000000; -#endif uint32_t result = dist * dist; angle = abs(gpsItem.gps.longitude - gpsItem.pilotLongitude); -#if defined(STM32) dist = uint64_t(gpsItem.distFromEarthAxis) * angle / 1000000; -#else - dist = gpsItem.distFromEarthAxis * angle / 1000000; -#endif result += dist * dist; // Length on ground (ignoring curvature of the earth) diff --git a/radio/src/tests/mixer.cpp b/radio/src/tests/mixer.cpp index b8f8bc845..1dce97657 100644 --- a/radio/src/tests/mixer.cpp +++ b/radio/src/tests/mixer.cpp @@ -576,14 +576,9 @@ TEST_F(MixerTest, SlowOnSwitchSource) { g_model.mixData[0].destCh = 0; g_model.mixData[0].mltpx = MLTPX_ADD; -#if defined(PCBSKY9X) - g_model.mixData[0].srcRaw = MIXSRC_THR; - int switchIndex = 1; -#else g_eeGeneral.switchConfig = 0x03; g_model.mixData[0].srcRaw = MIXSRC_SA; int switchIndex = 0; -#endif g_model.mixData[0].weight = 100; g_model.mixData[0].speedUp = 50; g_model.mixData[0].speedDown = 50; diff --git a/radio/src/trainer.cpp b/radio/src/trainer.cpp index 3daed00c4..fd8d88504 100644 --- a/radio/src/trainer.cpp +++ b/radio/src/trainer.cpp @@ -48,25 +48,6 @@ void checkTrainerSignalWarning() } } -#if defined(PCBSKY9X) -void stopTrainer() -{ - stop_trainer_capture(); -} - -void checkTrainerSettings() -{ - uint8_t requiredTrainerMode = SLAVE_MODE(); - - if (requiredTrainerMode != currentTrainerMode) { - currentTrainerMode = requiredTrainerMode; - if (requiredTrainerMode) - stopTrainer(); - else - init_trainer_capture(); - } -} -#else void stopTrainer() { switch (currentTrainerMode) { @@ -174,4 +155,3 @@ void checkTrainerSettings() #endif } } -#endif diff --git a/radio/src/translations.cpp b/radio/src/translations.cpp index 50ee1c31e..9388945a3 100644 --- a/radio/src/translations.cpp +++ b/radio/src/translations.cpp @@ -97,9 +97,6 @@ ISTR(SPORT_MODES); ISTR(FSGROUPS); ISTR(ADCFILTERVALUES); -#if defined(PCBSKY9X) && defined(REVX) -ISTR(VOUTPUT_TYPE); -#endif #if defined(HELI) ISTR(VSWASHTYPE); @@ -787,9 +784,6 @@ const char STR_MENUWHENDONE[] = TR_MENUWHENDONE; const char STR_NO_TELEMETRY_SCREENS[] = TR_NO_TELEMETRY_SCREENS; #endif -#if defined(PCBSKY9X) && defined(REVX) -const char STR_OUTPUT_TYPE[] = TR_OUTPUT_TYPE; -#endif #if defined(HELI) const char STR_MENUHELISETUP[] = TR_MENUHELISETUP; diff --git a/radio/src/translations.h b/radio/src/translations.h index 0dcb4abcb..a6565953b 100644 --- a/radio/src/translations.h +++ b/radio/src/translations.h @@ -115,9 +115,6 @@ extern const char STR_VTRIMINC[]; extern const char STR_VDISPLAYTRIMS[]; extern const char STR_RETA123[]; -#if defined(PCBSKY9X) && defined(REVX) -extern const char STR_VOUTPUT_TYPE[]; -#endif extern const char STR_VBLMODE[]; extern const char STR_VCURVEFUNC[]; @@ -241,9 +238,6 @@ extern const char STR_TTRIM_SW[]; extern const char STR_BEEPCTR[]; extern const char STR_USE_GLOBAL_FUNCS[]; -#if defined(PCBSKY9X) && defined(REVX) - extern const char STR_OUTPUT_TYPE[]; -#endif extern const char STR_PPMFRAME[]; extern const char STR_REFRESHRATE[]; diff --git a/radio/src/translations/cn.h.txt b/radio/src/translations/cn.h.txt index ff429ccc6..1ed96b80c 100644 --- a/radio/src/translations/cn.h.txt +++ b/radio/src/translations/cn.h.txt @@ -121,10 +121,8 @@ #define TR_RETA123 "RETA13245LR" #elif defined(PCBX9E) #define TR_RETA123 "RETA1234LRLR" -#elif defined(PCBTARANIS) || defined(REVX) +#elif defined(PCBTARANIS) #define TR_RETA123 "RETA123LR" -#elif defined(PCBSKY9X) - #define TR_RETA123 "RETA123a" #else #define TR_RETA123 "RETA123" #endif diff --git a/radio/src/translations/cz.h.txt b/radio/src/translations/cz.h.txt index 82f75befd..0e6ccda9d 100644 --- a/radio/src/translations/cz.h.txt +++ b/radio/src/translations/cz.h.txt @@ -125,18 +125,12 @@ #define TR_RETA123 "SVPK13245LR" #elif defined(PCBX9E) #define TR_RETA123 "SVPK1234LRLR" -#elif defined(PCBTARANIS) || defined(REVX) +#elif defined(PCBTARANIS) #define TR_RETA123 "SVPK123LR" -#elif defined(PCBSKY9X) - #define TR_RETA123 "SVPK123a" #else #define TR_RETA123 "SVPK123" #endif -#if defined(PCBSKY9X) && defined(REVX) - #define LEN_VOUTPUT_TYPE "\011" - #define TR_VOUTPUT_TYPE "OpenDrain""PushPull\0" -#endif #define LEN_VCURVEFUNC "\003" #define TR_VCURVEFUNC "---""x>0""x<0""|x|""f>0""f<0""|f|" @@ -193,11 +187,7 @@ #endif #if defined(VOICE) - #if defined(PCBSKY9X) - #define TR_PLAY_TRACK "\221\222Zvuk\0 " - #else #define TR_PLAY_TRACK TR3("\221\222Stopa\0 ", "\221\222Stopa\0 ", "Přehrát wav") - #endif #define TR_PLAY_BOTH "\221\222Pár stop\0" #define TR_PLAY_VALUE TR3("\221\222Hlásit\0 ", "\221\222Hlásit\0 ", "Hlásit stav") #else @@ -312,13 +302,8 @@ #define TR_TRIMS_SWITCHES TR("tSl""tSp""tVd""tVn""tPd""tPn""tKl""tKp", STR_CHAR_TRIM "Sl" STR_CHAR_TRIM "Sp" STR_CHAR_TRIM "Vd" STR_CHAR_TRIM "Vn" STR_CHAR_TRIM "Pd" STR_CHAR_TRIM "Pn" STR_CHAR_TRIM "Kl" STR_CHAR_TRIM "Kp") #endif -#if defined(PCBSKY9X) - #define TR_ROTARY_ENCODERS "REa\0" - #define TR_ROTENC_SWITCHES "REa" -#else #define TR_ROTARY_ENCODERS #define TR_ROTENC_SWITCHES -#endif #define TR_ON_ONE_SWITCHES "ZAP""One" @@ -437,9 +422,6 @@ #define TR_TTRIM_SW TR("T-Trim-Sw", INDENT "Trim switch") #define TR_BEEPCTR TR3("Středy \221\222", "Pípat středy \221\222", "Pípat středy") #define TR_USE_GLOBAL_FUNCS TR("Glob.Funkce", "Použít Glob.Funkce") -#if defined(PCBSKY9X) && defined(REVX) - #define TR_OUTPUT_TYPE INDENT "Výstup" -#endif #define TR_PROTOCOL "Protokol" #define TR_PPMFRAME INDENT "PPM modulace" #define TR_REFRESHRATE TR(INDENT "Obnovit", INDENT "Obn. frekv.") diff --git a/radio/src/translations/de.h.txt b/radio/src/translations/de.h.txt index a69c920a0..bddaea9f0 100644 --- a/radio/src/translations/de.h.txt +++ b/radio/src/translations/de.h.txt @@ -126,18 +126,12 @@ #define TR_RETA123 "SHGQ13245LR" #elif defined(PCBX9E) #define TR_RETA123 "SHGQ1234LRLR" -#elif defined(PCBTARANIS) || defined(REVX) +#elif defined(PCBTARANIS) #define TR_RETA123 "SHGQ123LR" -#elif defined(PCBSKY9X) - #define TR_RETA123 "SHGQ123a" #else #define TR_RETA123 "SHGQ123" #endif -#if defined(PCBSKY9X) && defined(REVX) - #define LEN_VOUTPUT_TYPE "\011" - #define TR_VOUTPUT_TYPE "OpenDrain""PushPull\0" -#endif #define LEN_VCURVEFUNC "\003" #define TR_VCURVEFUNC "---""x>0""x<0""|x|""f>0""f<0""|f|" @@ -194,11 +188,7 @@ #endif #if defined(VOICE) - #if defined(PCBSKY9X) - #define TR_PLAY_TRACK "Spiel\0 " - #else #define TR_PLAY_TRACK "Sag Text\0 " - #endif #define TR_PLAY_BOTH "Sag Beide " #define TR_PLAY_VALUE TR("Sag Wert\0 ", "Sag Wert ") #else @@ -315,13 +305,8 @@ #define TR_TRIMS_SWITCHES TR("tRl""tRr""tEd""tEu""tTd""tTu""tAl""tAr", STR_CHAR_TRIM "Rl" STR_CHAR_TRIM "Rr" STR_CHAR_TRIM "Ed" STR_CHAR_TRIM "Eu" STR_CHAR_TRIM "Td" STR_CHAR_TRIM "Tu" STR_CHAR_TRIM "Al" STR_CHAR_TRIM "Ar") #endif -#if defined(PCBSKY9X) - #define TR_ROTARY_ENCODERS "DGa\0" - #define TR_ROTENC_SWITCHES "DGa" -#else #define TR_ROTARY_ENCODERS #define TR_ROTENC_SWITCHES -#endif #define TR_ON_ONE_SWITCHES "ON\0""One" @@ -439,9 +424,6 @@ #define TR_TTRIM_SW TR("T-Trim-Sw", INDENT "Trim switch") #define TR_BEEPCTR TR("MittePieps", "Mittelstell. -Pieps") #define TR_USE_GLOBAL_FUNCS TR("Glob. Funkt.", "Globale Funkt verw.") -#if defined(PCBSKY9X) && defined(REVX) - #define TR_OUTPUT_TYPE INDENT "Output" -#endif #define TR_PROTOCOL TR("Protok.", "Protokoll") #define TR_PPMFRAME INDENT "PPM-Frame" #define TR_REFRESHRATE TR(INDENT "Refresh", INDENT "Refresh rate") diff --git a/radio/src/translations/en.h.txt b/radio/src/translations/en.h.txt index 7a8587e8b..d8e054196 100644 --- a/radio/src/translations/en.h.txt +++ b/radio/src/translations/en.h.txt @@ -126,18 +126,12 @@ #define TR_RETA123 "RETA13245LR" #elif defined(PCBX9E) #define TR_RETA123 "RETA1234LRLR" -#elif defined(PCBTARANIS) || defined(REVX) +#elif defined(PCBTARANIS) #define TR_RETA123 "RETA123LR" -#elif defined(PCBSKY9X) - #define TR_RETA123 "RETA123a" #else #define TR_RETA123 "RETA123" #endif -#if defined(PCBSKY9X) && defined(REVX) - #define LEN_VOUTPUT_TYPE "\011" - #define TR_VOUTPUT_TYPE "OpenDrain""PushPull\0" -#endif #define LEN_VCURVEFUNC "\003" #define TR_VCURVEFUNC "---""x>0""x<0""|x|""f>0""f<0""|f|" @@ -194,11 +188,7 @@ #endif #if defined(VOICE) - #if defined(PCBSKY9X) - #define TR_PLAY_TRACK "Play\0 " - #else #define TR_PLAY_TRACK "Play Track" - #endif #define TR_PLAY_BOTH "Play Both\0" #define TR_PLAY_VALUE TR("Play Val\0 ", "Play Value") #else @@ -315,13 +305,8 @@ #define TR_TRIMS_SWITCHES TR("tRl""tRr""tEd""tEu""tTd""tTu""tAl""tAr", STR_CHAR_TRIM "Rl" STR_CHAR_TRIM "Rr" STR_CHAR_TRIM "Ed" STR_CHAR_TRIM "Eu" STR_CHAR_TRIM "Td" STR_CHAR_TRIM "Tu" STR_CHAR_TRIM "Al" STR_CHAR_TRIM "Ar") #endif -#if defined(PCBSKY9X) - #define TR_ROTARY_ENCODERS "REa\0" - #define TR_ROTENC_SWITCHES "REa" -#else #define TR_ROTARY_ENCODERS #define TR_ROTENC_SWITCHES -#endif #define TR_ON_ONE_SWITCHES "ON\0""One" @@ -438,9 +423,6 @@ #define TR_TTRIM_SW TR("T-Trim-Sw", INDENT "Trim switch") #define TR_BEEPCTR TR("Ctr Beep", "Center Beep") #define TR_USE_GLOBAL_FUNCS TR("Glob.Funcs", "Use global funcs") -#if defined(PCBSKY9X) && defined(REVX) - #define TR_OUTPUT_TYPE INDENT "Output" -#endif #define TR_PROTOCOL TR("Proto", "Protocol") #define TR_PPMFRAME INDENT "PPM frame" #define TR_REFRESHRATE TR(INDENT "Refresh", INDENT "Refresh rate") diff --git a/radio/src/translations/es.h.txt b/radio/src/translations/es.h.txt index 47c5119fc..955c58a2b 100644 --- a/radio/src/translations/es.h.txt +++ b/radio/src/translations/es.h.txt @@ -126,18 +126,12 @@ #define TR_RETA123 "RETA13245LR" #elif defined(PCBX9E) #define TR_RETA123 "RETA1234LRLR" -#elif defined(PCBTARANIS) || defined(REVX) +#elif defined(PCBTARANIS) #define TR_RETA123 "RETA123LR" -#elif defined(PCBSKY9X) - #define TR_RETA123 "RETA123a" #else #define TR_RETA123 "RETA123" #endif -#if defined(PCBSKY9X) && defined(REVX) - #define LEN_VOUTPUT_TYPE "\011" - #define TR_VOUTPUT_TYPE "OpenDrain""PushPull\0" -#endif #define LEN_VCURVEFUNC "\003" #define TR_VCURVEFUNC "---""x>0""x<0""|x|""f>0""f<0""|f|" @@ -194,11 +188,7 @@ #endif #if defined(VOICE) - #if defined(PCBSKY9X) - #define TR_PLAY_TRACK "Oir\0 " - #else #define TR_PLAY_TRACK "Oir pista\0" - #endif #define TR_PLAY_BOTH "Oir Ambos\0" #define TR_PLAY_VALUE "Oir valor\0" #else @@ -312,13 +302,8 @@ #define TR_TRIMS_SWITCHES TR("tRl""tRr""tEd""tEu""tTd""tTu""tAl""tAr", STR_CHAR_TRIM "Rl" STR_CHAR_TRIM "Rr" STR_CHAR_TRIM "Ed" STR_CHAR_TRIM "Eu" STR_CHAR_TRIM "Td" STR_CHAR_TRIM "Tu" STR_CHAR_TRIM "Al" STR_CHAR_TRIM "Ar") #endif -#if defined(PCBSKY9X) - #define TR_ROTARY_ENCODERS "REa\0" - #define TR_ROTENC_SWITCHES "REa" -#else #define TR_ROTARY_ENCODERS #define TR_ROTENC_SWITCHES -#endif #define TR_ON_ONE_SWITCHES "ON\0""One" @@ -437,9 +422,6 @@ #define TR_TTRIM_SW TR("T-Trim-Sw", INDENT "Trim switch") #define TR_BEEPCTR TR("Beep ctr", "Beep centro") #define TR_USE_GLOBAL_FUNCS TR("Funcs. glob.", "Usar func. globales") -#if defined(PCBSKY9X) && defined(REVX) - #define TR_OUTPUT_TYPE INDENT "Output" -#endif #define TR_PROTOCOL TR("Proto", "Protocolo") #define TR_PPMFRAME INDENT "Trama PPM" #define TR_REFRESHRATE TR(INDENT "Refresco", INDENT "Velocidad refresco") diff --git a/radio/src/translations/fi.h.txt b/radio/src/translations/fi.h.txt index 0ca7e020c..0ddf5d669 100644 --- a/radio/src/translations/fi.h.txt +++ b/radio/src/translations/fi.h.txt @@ -126,18 +126,12 @@ #define TR_RETA123 "RETA13245LR" #elif defined(PCBX9E) #define TR_RETA123 "RETA1234LRLR" -#elif defined(PCBTARANIS) || defined(REVX) +#elif defined(PCBTARANIS) #define TR_RETA123 "RETA123LR" -#elif defined(PCBSKY9X) - #define TR_RETA123 "RETA123a" #else #define TR_RETA123 "RETA123" #endif -#if defined(PCBSKY9X) && defined(REVX) - #define LEN_VOUTPUT_TYPE "\011" - #define TR_VOUTPUT_TYPE "OpenDrain""PushPull\0" -#endif #define LEN_VCURVEFUNC "\003" #define TR_VCURVEFUNC "---""x>0""x<0""|x|""f>0""f<0""|f|" @@ -197,11 +191,7 @@ #endif #if defined(VOICE) - #if defined(PCBSKY9X) - #define TR_PLAY_TRACK "Play\0 " - #else #define TR_PLAY_TRACK "Play Track" - #endif #define TR_PLAY_BOTH "Play Both\0" #define TR_PLAY_VALUE TR("Play Val\0 ", "Play Value") #else @@ -333,13 +323,8 @@ #define TR_TRIMS_SWITCHES TR("tRl""tRr""tEd""tEu""tTd""tTu""tAl""tAr", STR_CHAR_TRIM "Rl" STR_CHAR_TRIM "Rr" STR_CHAR_TRIM "Ed" STR_CHAR_TRIM "Eu" STR_CHAR_TRIM "Td" STR_CHAR_TRIM "Tu" STR_CHAR_TRIM "Al" STR_CHAR_TRIM "Ar") #endif -#if defined(PCBSKY9X) - #define TR_ROTARY_ENCODERS "REa\0" - #define TR_ROTENC_SWITCHES "REa" -#else #define TR_ROTARY_ENCODERS #define TR_ROTENC_SWITCHES -#endif #define TR_ON_ONE_SWITCHES "ON\0""One" @@ -451,9 +436,6 @@ #define TR_TTRIM_SW TR("T-Trim-Sw", INDENT "Trim switch") #define TR_BEEPCTR TR("Ctr Beep", "Center Beep") #define TR_USE_GLOBAL_FUNCS "Use Global Funcs" -#if defined(PCBSKY9X) && defined(REVX) - #define TR_OUTPUT_TYPE INDENT "Output" -#endif #define TR_PROTOCOL TR("Proto", "Protocol") #define TR_PPMFRAME TR("PPM frame", INDENT "PPM frame") #define TR_REFRESHRATE TR(INDENT "Refresh", INDENT "Refresh rate") diff --git a/radio/src/translations/fr.h.txt b/radio/src/translations/fr.h.txt index f99a913b6..7d163b4e9 100644 --- a/radio/src/translations/fr.h.txt +++ b/radio/src/translations/fr.h.txt @@ -126,18 +126,12 @@ #define TR_RETA123 "DPGA13245LR" #elif defined(PCBX9E) #define TR_RETA123 "DPGA1234LRLR" -#elif defined(PCBTARANIS) || defined(REVX) +#elif defined(PCBTARANIS) #define TR_RETA123 "DPGA123LR" -#elif defined(PCBSKY9X) - #define TR_RETA123 "DPGA123a" #else #define TR_RETA123 "DPGA123" #endif -#if defined(PCBSKY9X) && defined(REVX) - #define LEN_VOUTPUT_TYPE "\011" - #define TR_VOUTPUT_TYPE "OpenDrain""PushPull\0" -#endif #define LEN_VCURVEFUNC "\003" #define TR_VCURVEFUNC "---""x>0""x<0""|x|""f>0""f<0""|f|" @@ -197,11 +191,7 @@ #endif #if defined(VOICE) - #if defined(PCBSKY9X) - #define TR_PLAY_TRACK "Jouer\0 " - #else #define TR_PLAY_TRACK "Jouer fich\0 " - #endif #define TR_PLAY_BOTH "Jouer les 2\0 " #define TR_PLAY_VALUE "Lire valeur\0 " #else @@ -335,13 +325,8 @@ #define TR_TRIMS_SWITCHES TR("tDg""tDd""tPb""tPh""tGb""tGh""tAg""tAd", STR_CHAR_TRIM "Dg" STR_CHAR_TRIM "Dd" STR_CHAR_TRIM "Pb" STR_CHAR_TRIM "Ph" STR_CHAR_TRIM "Gb" STR_CHAR_TRIM "Gh" STR_CHAR_TRIM "Ag" STR_CHAR_TRIM "Ad") #endif -#if defined(PCBSKY9X) - #define TR_ROTARY_ENCODERS "REa\0" - #define TR_ROTENC_SWITCHES "REa" -#else #define TR_ROTARY_ENCODERS #define TR_ROTENC_SWITCHES -#endif #define TR_ON_ONE_SWITCHES "ON\0""Un" @@ -457,9 +442,6 @@ #define TR_TTRIM_SW TR("T-Trim-Sw", INDENT "Trim switch") #define TR_BEEPCTR TR("Bips centr", "Bips centrage") #define TR_USE_GLOBAL_FUNCS TR("Fonc. glob.", "Fonctions globales") -#if defined(PCBSKY9X) && defined(REVX) - #define TR_OUTPUT_TYPE INDENT "Sortie" -#endif #define TR_PROTOCOL TR("Proto.", "Protocole") #define TR_PPMFRAME INDENT "Trame PPM" #define TR_REFRESHRATE INDENT "Période" diff --git a/radio/src/translations/it.h.txt b/radio/src/translations/it.h.txt index 504acc1ff..3b5ee9f28 100644 --- a/radio/src/translations/it.h.txt +++ b/radio/src/translations/it.h.txt @@ -130,18 +130,12 @@ #define TR_RETA123 "DEMA13245LR" #elif defined(PCBX9E) #define TR_RETA123 "DEMA123SDSD" -#elif defined(PCBTARANIS) || defined(REVX) +#elif defined(PCBTARANIS) #define TR_RETA123 "DEMA123SD" -#elif defined(PCBSKY9X) - #define TR_RETA123 "DEMA123a" #else #define TR_RETA123 "DEMA123" #endif -#if defined(PCBSKY9X) && defined(REVX) - #define LEN_VOUTPUT_TYPE "\011" - #define TR_VOUTPUT_TYPE "OpenDrain""PushPull\0" -#endif #define LEN_VCURVEFUNC "\003" #define TR_VCURVEFUNC "---""x>0""x<0""|x|""f>0""f<0""|f|" @@ -201,11 +195,7 @@ #endif #if defined(VOICE) - #if defined(PCBSKY9X) - #define TR_PLAY_TRACK "Suona\0 " - #else #define TR_PLAY_TRACK "SuonaTraccia\0" - #endif #define TR_PLAY_BOTH "Play Both\0 " #define TR_PLAY_VALUE TR("LeggiVal\0 ", "LeggiValore\0 ") #else @@ -339,13 +329,8 @@ #define TR_TRIMS_SWITCHES TR("tRl""tRr""tEd""tEu""tTd""tTu""tAl""tAr", STR_CHAR_TRIM "Rl" STR_CHAR_TRIM "Rr" STR_CHAR_TRIM "Ed" STR_CHAR_TRIM "Eu" STR_CHAR_TRIM "Td" STR_CHAR_TRIM "Tu" STR_CHAR_TRIM "Al" STR_CHAR_TRIM "Ar") #endif -#if defined(PCBSKY9X) - #define TR_ROTARY_ENCODERS "REa\0" - #define TR_ROTENC_SWITCHES "REa" -#else #define TR_ROTARY_ENCODERS #define TR_ROTENC_SWITCHES -#endif #define TR_ON_ONE_SWITCHES "ON\0""One" @@ -462,9 +447,6 @@ #define TR_TTRIM_SW TR("T-Trim-Sw", INDENT "Trim switch") #define TR_BEEPCTR TR("Beep al c.", "Beep al centro") #define TR_USE_GLOBAL_FUNCS TR("Funz. Glob.", "Usa Funz. Globali") -#if defined(PCBSKY9X) && defined(REVX) - #define TR_OUTPUT_TYPE INDENT "Uscita" -#endif #define TR_PROTOCOL TR("Protoc.", "Protocollo") #define TR_PPMFRAME INDENT "Frame PPM" #define TR_REFRESHRATE TR(INDENT "Refresh", INDENT "Refresh rate") diff --git a/radio/src/translations/nl.h.txt b/radio/src/translations/nl.h.txt index f4b3cb797..8bffd0916 100644 --- a/radio/src/translations/nl.h.txt +++ b/radio/src/translations/nl.h.txt @@ -127,18 +127,12 @@ #define TR_RETA123 "RETA13245LR" #elif defined(PCBX9E) #define TR_RETA123 "RETA1234LRLR" -#elif defined(PCBTARANIS) || defined(REVX) +#elif defined(PCBTARANIS) #define TR_RETA123 "RETA123LR" -#elif defined(PCBSKY9X) - #define TR_RETA123 "RETA123a" #else #define TR_RETA123 "RETA123" #endif -#if defined(PCBSKY9X) && defined(REVX) - #define LEN_VOUTPUT_TYPE "\011" - #define TR_VOUTPUT_TYPE "OpenDrain""PushPull\0" -#endif #define LEN_VCURVEFUNC "\003" #define TR_VCURVEFUNC "---""x>0""x<0""|x|""f>0""f<0""|f|" @@ -195,11 +189,7 @@ #endif #if defined(VOICE) - #if defined(PCBSKY9X) - #define TR_PLAY_TRACK "Play\0 " - #else #define TR_PLAY_TRACK "Play Track" - #endif #define TR_PLAY_BOTH "Play Both\0" #define TR_PLAY_VALUE TR("Play Val\0 ", "Play Value") #else @@ -316,13 +306,8 @@ #define TR_TRIMS_SWITCHES TR("tRl""tRr""tEd""tEu""tTd""tTu""tAl""tAr", STR_CHAR_TRIM "Rl" STR_CHAR_TRIM "Rr" STR_CHAR_TRIM "Ed" STR_CHAR_TRIM "Eu" STR_CHAR_TRIM "Td" STR_CHAR_TRIM "Tu" STR_CHAR_TRIM "Al" STR_CHAR_TRIM "Ar") #endif -#if defined(PCBSKY9X) - #define TR_ROTARY_ENCODERS "REa\0" - #define TR_ROTENC_SWITCHES "REa" -#else #define TR_ROTARY_ENCODERS #define TR_ROTENC_SWITCHES -#endif #define TR_ON_ONE_SWITCHES "ON\0""One" @@ -441,9 +426,6 @@ #define TR_TTRIM_SW TR("T-Trim-Sw", INDENT "Trim switch") #define TR_BEEPCTR TR("Ctr Beep", "Center Beep") #define TR_USE_GLOBAL_FUNCS TR("Glob.Funcs", "Globale Functies") -#if defined(PCBSKY9X) && defined(REVX) - #define TR_OUTPUT_TYPE INDENT "Output" -#endif #define TR_PROTOCOL TR("Proto", "Protocol") #define TR_PPMFRAME INDENT "PPM frame" #define TR_REFRESHRATE TR(INDENT "Refresh", INDENT "Refresh rate") diff --git a/radio/src/translations/pl.h.txt b/radio/src/translations/pl.h.txt index f730bf437..95e5dcbd2 100644 --- a/radio/src/translations/pl.h.txt +++ b/radio/src/translations/pl.h.txt @@ -127,18 +127,12 @@ #define TR_RETA123 "KWGL13245LR" #elif defined(PCBX9E) #define TR_RETA123 "KWGL1234LRLR" -#elif defined(PCBTARANIS) || defined(REVX) +#elif defined(PCBTARANIS) #define TR_RETA123 "KWGL123LR" -#elif defined(PCBSKY9X) - #define TR_RETA123 "KWGL123a" #else #define TR_RETA123 "KWGL123" #endif -#if defined(PCBSKY9X) && defined(REVX) - #define LEN_VOUTPUT_TYPE "\011" - #define TR_VOUTPUT_TYPE "OpenDrain""PushPull\0" -#endif #define LEN_VCURVEFUNC "\003" #define TR_VCURVEFUNC "---""x>0""x<0""|x|""f>0""f<0""|f|" @@ -195,11 +189,7 @@ #endif #if defined(VOICE) - #if defined(PCBSKY9X) - #define TR_PLAY_TRACK "Ścieżka\0 " - #else #define TR_PLAY_TRACK "GrajŚcieżk" - #endif #define TR_PLAY_BOTH "Graj Oba\0 " #define TR_PLAY_VALUE TR("Graj Wart\0","GrajWartoś") #else @@ -333,13 +323,8 @@ #define TR_TRIMS_SWITCHES TR("tRl""tRr""tEd""tEu""tTd""tTu""tAl""tAr", STR_CHAR_TRIM "Rl" STR_CHAR_TRIM "Rr" STR_CHAR_TRIM "Ed" STR_CHAR_TRIM "Eu" STR_CHAR_TRIM "Td" STR_CHAR_TRIM "Tu" STR_CHAR_TRIM "Al" STR_CHAR_TRIM "Ar") #endif -#if defined(PCBSKY9X) - #define TR_ROTARY_ENCODERS "REa\0" - #define TR_ROTENC_SWITCHES "REa" -#else #define TR_ROTARY_ENCODERS #define TR_ROTENC_SWITCHES -#endif #define TR_ON_ONE_SWITCHES "ON\0""One" @@ -458,9 +443,6 @@ #define TR_TTRIM_SW TR("T-Trim-Sw", INDENT "Trim switch") #define TR_BEEPCTR TR("ŚrodBeep", "Pikn.Środka") #define TR_USE_GLOBAL_FUNCS TR("Funk.Glb.","Użyj Funkcji Glb") -#if defined(PCBSKY9X) && defined(REVX) - #define TR_OUTPUT_TYPE INDENT "Wyjście" -#endif #define TR_PROTOCOL TR("Proto", "Protokół") #define TR_PPMFRAME INDENT "Ramka PPM" #define TR_REFRESHRATE TR(INDENT "Refresh", INDENT "Refresh rate") diff --git a/radio/src/translations/pt.h.txt b/radio/src/translations/pt.h.txt index 3f6c8f73f..540e423a4 100644 --- a/radio/src/translations/pt.h.txt +++ b/radio/src/translations/pt.h.txt @@ -129,18 +129,12 @@ #define TR_RETA123 "LPMA3245LR" #elif defined(PCBX9E) #define TR_RETA123 "RETA1234LRLR" -#elif defined(PCBTARANIS) || defined(REVX) +#elif defined(PCBTARANIS) #define TR_RETA123 "LPMA123LR" -#elif defined(PCBSKY9X) - #define TR_RETA123 "LPMA123a" #else #define TR_RETA123 "LPMA123" #endif -#if defined(PCBSKY9X) && defined(REVX) - #define LEN_VOUTPUT_TYPE "\011" - #define TR_VOUTPUT_TYPE "OpenDrain""PushPull\0" -#endif #define LEN_VCURVEFUNC "\003" #define TR_VCURVEFUNC "---""x>0""x<0""|x|""f>0""f<0""|f|" @@ -197,11 +191,7 @@ #endif #if defined(VOICE) - #if defined(PCBSKY9X) - #define TR_PLAY_TRACK "Tocar Pista\0 " - #else #define TR_PLAY_TRACK "Tocar\0 " - #endif #define TR_PLAY_BOTH "Play Both\0 " #define TR_PLAY_VALUE "Ouvir Valor\0 " #else @@ -333,13 +323,8 @@ #define TR_TRIMS_SWITCHES TR("tRl""tRr""tEd""tEu""tTd""tTu""tAl""tAr", STR_CHAR_TRIM "Rl" STR_CHAR_TRIM "Rr" STR_CHAR_TRIM "Ed" STR_CHAR_TRIM "Eu" STR_CHAR_TRIM "Eu" STR_CHAR_TRIM "Td" STR_CHAR_TRIM "Tu" STR_CHAR_TRIM "Al" STR_CHAR_TRIM "Ar") #endif -#if defined(PCBSKY9X) - #define TR_ROTARY_ENCODERS "REa\0" - #define TR_ROTENC_SWITCHES "REa" -#else #define TR_ROTARY_ENCODERS #define TR_ROTENC_SWITCHES -#endif #define TR_ON_ONE_SWITCHES "ON\0""One" @@ -462,9 +447,6 @@ #define TR_TTRIM_SW TR("T-Trim-Sw", INDENT "Trim switch") #define TR_BEEPCTR "Ctr Beep" #define TR_USE_GLOBAL_FUNCS "Use Global Funcs" -#if defined(PCBSKY9X) && defined(REVX) - #define TR_OUTPUT_TYPE INDENT "Output" -#endif #define TR_PROTOCOL "Proto" #define TR_PPMFRAME "PPM frame" #define TR_REFRESHRATE TR(INDENT "Refresh", INDENT "Refresh rate") diff --git a/radio/src/translations/se.h.txt b/radio/src/translations/se.h.txt index b03623e67..14efd3499 100644 --- a/radio/src/translations/se.h.txt +++ b/radio/src/translations/se.h.txt @@ -129,18 +129,12 @@ #define TR_RETA123 "RHGS13245LR" #elif defined(PCBX9E) #define TR_RETA123 "RHGS1234HVHV" -#elif defined(PCBTARANIS) || defined(REVX) +#elif defined(PCBTARANIS) #define TR_RETA123 "RHGS123HV" -#elif defined(PCBSKY9X) - #define TR_RETA123 "RHGS123a" #else #define TR_RETA123 "RHGS123" #endif -#if defined(PCBSKY9X) && defined(REVX) - #define LEN_VOUTPUT_TYPE "\011" - #define TR_VOUTPUT_TYPE "OpenDrain""PushPull\0" -#endif #define LEN_VCURVEFUNC "\003" #define TR_VCURVEFUNC "---""x>0""x<0""|x|""f>0""f<0""|f|" @@ -197,11 +191,7 @@ #endif #if defined(VOICE) - #if defined(PCBSKY9X) - #define TR_PLAY_TRACK "Spela Spår" - #else #define TR_PLAY_TRACK "Spela upp\0" - #endif #define TR_PLAY_BOTH "Spela Båda" #define TR_PLAY_VALUE TR("Säg värdet", "Säg värdet") #else @@ -336,13 +326,8 @@ #define TR_TRIMS_SWITCHES TR("tRv""tRh""tHn""tHu""tGn""tGu""tSv""tSh", STR_CHAR_TRIM "Rv" STR_CHAR_TRIM "Rh" STR_CHAR_TRIM "Hn" STR_CHAR_TRIM "Hu" STR_CHAR_TRIM "Gn" STR_CHAR_TRIM "Gu" STR_CHAR_TRIM "Sv" STR_CHAR_TRIM "Sh") #endif -#if defined(PCBSKY9X) - #define TR_ROTARY_ENCODERS "REa\0" - #define TR_ROTENC_SWITCHES "REa" -#else #define TR_ROTARY_ENCODERS #define TR_ROTENC_SWITCHES -#endif #define TR_ON_ONE_SWITCHES "På\0""Ett" @@ -465,9 +450,6 @@ #define TR_TTRIM_SW TR("T-Trim-Sw", INDENT "Trim switch") #define TR_BEEPCTR TR("Cent.pip", "Centerpip") #define TR_USE_GLOBAL_FUNCS TR("Glob.Funkt", "Använd Global Funk.") -#if defined(PCBSKY9X) && defined(REVX) - #define TR_OUTPUT_TYPE INDENT "Output" -#endif #define TR_PROTOCOL TR("Proto", "Protokoll") #define TR_PPMFRAME INDENT "PPM-paket" #define TR_REFRESHRATE TR(INDENT "Refresh", INDENT "Refresh rate") diff --git a/radio/src/translations/tw.h.txt b/radio/src/translations/tw.h.txt index 6e2172311..67cf8a64d 100644 --- a/radio/src/translations/tw.h.txt +++ b/radio/src/translations/tw.h.txt @@ -121,10 +121,8 @@ #define TR_RETA123 "RETA13245LR" #elif defined(PCBX9E) #define TR_RETA123 "RETA1234LRLR" -#elif defined(PCBTARANIS) || defined(REVX) +#elif defined(PCBTARANIS) #define TR_RETA123 "RETA123LR" -#elif defined(PCBSKY9X) - #define TR_RETA123 "RETA123a" #else #define TR_RETA123 "RETA123" #endif diff --git a/radio/src/translations/untranslated.h b/radio/src/translations/untranslated.h index a9b963bff..5031592e4 100644 --- a/radio/src/translations/untranslated.h +++ b/radio/src/translations/untranslated.h @@ -72,9 +72,6 @@ #elif defined(PCBTARANIS) #define TR_POTS_VSRCRAW STR_CHAR_POT"S1\0" STR_CHAR_POT"S2\0" STR_CHAR_POT"S3\0" STR_CHAR_SLIDER"LS\0" STR_CHAR_SLIDER"RS\0" #define TR_SW_VSRCRAW STR_CHAR_SWITCH"SA\0" STR_CHAR_SWITCH"SB\0" STR_CHAR_SWITCH"SC\0" STR_CHAR_SWITCH"SD\0" STR_CHAR_SWITCH"SE\0" STR_CHAR_SWITCH"SF\0" STR_CHAR_SWITCH"SG\0" STR_CHAR_SWITCH"SH\0" STR_CHAR_SWITCH"SI\0" -#elif defined(PCBSKY9X) - #define TR_POTS_VSRCRAW "P1\0 ""P2\0 ""P3\0 " - #define TR_SW_VSRCRAW "3POS" "THR\0""RUD\0""ELE\0""AIL\0""GEA\0""TRN\0" #elif defined(PCBNV14) #define TR_POTS_VSRCRAW STR_CHAR_POT"S1\0" STR_CHAR_POT"S2\0" #define TR_SW_VSRCRAW STR_CHAR_SWITCH"SA\0" STR_CHAR_SWITCH"SB\0" STR_CHAR_SWITCH"SC\0" STR_CHAR_SWITCH"SD\0" STR_CHAR_SWITCH"SE\0" STR_CHAR_SWITCH"SF\0" STR_CHAR_SWITCH"SG\0" STR_CHAR_SWITCH"SH\0" @@ -83,8 +80,6 @@ #if defined(PCBFRSKY) || defined(PCBFLYSKY) // only special switches here #define TR_VSWITCHES "---" TR_TRIMS_SWITCHES TR_ON_ONE_SWITCHES -#elif defined(PCBSKY9X) - #define TR_VSWITCHES "---" "ID0""ID1""ID2" "THR""RUD""ELE""AIL""GEA""TRN" TR_TRIMS_SWITCHES TR_ROTENC_SWITCHES TR_ON_ONE_SWITCHES #endif #if defined(PCBNV14)