From 1615fd75932f14739a1897cee9362fa2d2759eda Mon Sep 17 00:00:00 2001 From: Andre Bernet Date: Sun, 5 Jan 2014 15:52:30 +0100 Subject: [PATCH] Switch CPU speed to 120MHz. Rest should not be affected. --- .../Source/Templates/system_stm32f2xx.c | 28 +++++++++---------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/radio/src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c b/radio/src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c index e1d39a223..654bb5fcf 100644 --- a/radio/src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c +++ b/radio/src/targets/taranis/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c @@ -3,7 +3,7 @@ * @file system_stm32f2xx.c * @author MCD Application Team * @version V1.1.0 - * @date 09-January-2013 + * @date 05-January-2014 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. * This file contains the system clock configuration for STM32F2xx devices, * and is generated by the clock configuration tool @@ -46,15 +46,15 @@ *----------------------------------------------------------------------------- * System Clock source | PLL (HSE) *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 60000000 + * SYSCLK(Hz) | 120000000 *----------------------------------------------------------------------------- - * HCLK(Hz) | 60000000 + * HCLK(Hz) | 120000000 *----------------------------------------------------------------------------- * AHB Prescaler | 1 *----------------------------------------------------------------------------- - * APB1 Prescaler | 2 + * APB1 Prescaler | 4 *----------------------------------------------------------------------------- - * APB2 Prescaler | 1 + * APB2 Prescaler | 2 *----------------------------------------------------------------------------- * HSE Frequency(Hz) | 12000000 *----------------------------------------------------------------------------- @@ -62,7 +62,7 @@ *----------------------------------------------------------------------------- * PLL_N | 240 *----------------------------------------------------------------------------- - * PLL_P | 4 + * PLL_P | 2 *----------------------------------------------------------------------------- * PLL_Q | 5 *----------------------------------------------------------------------------- @@ -74,7 +74,7 @@ *----------------------------------------------------------------------------- * VDD(V) | 3.3 *----------------------------------------------------------------------------- - * Flash Latency(WS) | 2 + * Flash Latency(WS) | 3 *----------------------------------------------------------------------------- * Prefetch Buffer | ON *----------------------------------------------------------------------------- @@ -146,7 +146,7 @@ #define PLL_N 240 /* SYSCLK = PLL_VCO / PLL_P */ -#define PLL_P 4 +#define PLL_P 2 /* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ #define PLL_Q 5 @@ -167,7 +167,7 @@ * @{ */ - uint32_t SystemCoreClock = 60000000; + uint32_t SystemCoreClock = 120000000; __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; @@ -359,11 +359,11 @@ static void SetSysClock(void) /* HCLK = SYSCLK / 1*/ RCC->CFGR |= RCC_CFGR_HPRE_DIV1; - /* PCLK2 = HCLK / 1*/ - RCC->CFGR |= RCC_CFGR_PPRE2_DIV1; + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; - /* PCLK1 = HCLK / 2*/ - RCC->CFGR |= RCC_CFGR_PPRE1_DIV2; + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; /* Configure the main PLL */ RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | @@ -378,7 +378,7 @@ static void SetSysClock(void) } /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ - FLASH->ACR = FLASH_ACR_PRFTEN |FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS; + FLASH->ACR = FLASH_ACR_PRFTEN |FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_3WS; /* Select the main PLL as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));