From 2a39ece5afea00d0a41a1de21ad1d39f8f1fbb32 Mon Sep 17 00:00:00 2001 From: bsongis Date: Sun, 10 Feb 2013 19:40:17 +0000 Subject: [PATCH] ACT Tx is stopped. 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b/src/Makefile @@ -50,7 +50,7 @@ DELAY = 5 #----------- BUILD OPTIONS --------------------------- # PCB version -# Values: 9X, 9X128, 9XR, 9XR128, GRUVIN9X, SKY9X, X9D, ACT +# Values: 9X, 9X128, 9XR, 9XR128, GRUVIN9X, SKY9X, X9D # Old values STD and STD128 are mapped to 9X and 9X128 for compatibility PCB = 9X @@ -278,14 +278,6 @@ ifeq ($(PCB), X9D) SDCARD = YES endif -ifeq ($(PCB), ACT) - ARCH = ARM - LDSCRIPT = x9d/stm32_flash.ld - TRGT = arm-none-eabi- - MCU = cortex-m3 - SDCARD = NO -endif - CC = $(TRGT)gcc AS = $(TRGT)as OBJCOPY = $(TRGT)objcopy @@ -481,22 +473,6 @@ endif RUN_FROM_FLASH = 1 -ifeq ($(PCB), ACT) - # ACT radio - OPT = 2 - CPPDEFS += -DPCBACT -DCPUARM -DEEPROM_VARIANT=0 -DAUDIO -DPXX -DDSM2 -DDSM2_PPM -DSTM32F10X_HD - EXTRAINCDIRS += sky9x CoOS/kernel CoOS/portable - EXTRAINCDIRS += act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x - BOARDSRC = act/board_act.cpp - EXTRABOARDSRC += x9d/lcd_driver.cpp - SRC += CoOS/kernel/core.c CoOS/kernel/hook.c CoOS/kernel/task.c CoOS/kernel/event.c CoOS/kernel/time.c CoOS/kernel/timer.c CoOS/kernel/flag.c CoOS/kernel/mutex.c CoOS/kernel/serviceReq.c CoOS/portable/GCC/port.c CoOS/portable/arch.c - EEPROMSRC = eeprom_avr.cpp # TODO later eeprom_conversions.cpp - CPPSRC += x9d/pulses_driver.cpp act/keys_driver.cpp act/audio_driver.cpp - CPPSRC += audio_arm.cpp - PULSESSRC = pulses_arm.cpp - CPPSRC += monitors_views.cpp -endif - ifeq ($(PCB), X9D) # X9D radio OPT = 2 @@ -855,7 +831,7 @@ eep: $(TARGET).eep lss: $(TARGET).lss sym: $(TARGET).sym -lbm: font.lbm font_tiny.lbm font_small.lbm font_midsize.lbm font_dblsize.lbm sticks.lbm splash_9x.lbm splash_X9D.lbm splash_ACT.lbm asterisk.lbm +lbm: font.lbm font_tiny.lbm font_small.lbm font_midsize.lbm font_dblsize.lbm sticks.lbm splash_9x.lbm splash_X9D.lbm asterisk.lbm # Build stamp-file stamp_header: @@ -944,11 +920,6 @@ splash_X9D.lbm: splash_X9D.bmp @echo "Convert X9D splash from xbm to lbm:" $(IMG2LBM) $< $@ bmp -splash_ACT.lbm: splash_ACT.xbm - @echo - @echo "Convert ACT splash from xbm to lbm:" - $(IMG2LBM) $< $@ largimg - asterisk.lbm: asterisk.xbm @echo @echo "Convert asterisk from xbm to lbm:" diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c deleted file mode 100644 index 56fddc52b..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c +++ /dev/null @@ -1,784 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.c - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File - * @version V1.30 - * @date 30. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#include - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -__ASM uint32_t __get_PSP(void) -{ - mrs r0, psp - bx lr -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -__ASM void __set_PSP(uint32_t topOfProcStack) -{ - msr psp, r0 - bx lr -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -__ASM uint32_t __get_MSP(void) -{ - mrs r0, msp - bx lr -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -__ASM void __set_MSP(uint32_t mainStackPointer) -{ - msr msp, r0 - bx lr -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -__ASM uint32_t __REV16(uint16_t value) -{ - rev16 r0, r0 - bx lr -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -__ASM int32_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -__ASM void __CLREX(void) -{ - clrex -} - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -__ASM uint32_t __get_BASEPRI(void) -{ - mrs r0, basepri - bx lr -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -__ASM void __set_BASEPRI(uint32_t basePri) -{ - msr basepri, r0 - bx lr -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -__ASM uint32_t __get_PRIMASK(void) -{ - mrs r0, primask - bx lr -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -__ASM void __set_PRIMASK(uint32_t priMask) -{ - msr primask, r0 - bx lr -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -__ASM uint32_t __get_FAULTMASK(void) -{ - mrs r0, faultmask - bx lr -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -__ASM void __set_FAULTMASK(uint32_t faultMask) -{ - msr faultmask, r0 - bx lr -} - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -__ASM uint32_t __get_CONTROL(void) -{ - mrs r0, control - bx lr -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -__ASM void __set_CONTROL(uint32_t control) -{ - msr control, r0 - bx lr -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#pragma diag_suppress=Pe940 - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) -{ - __ASM("mrs r0, psp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM("msr psp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) -{ - __ASM("mrs r0, msp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM("msr msp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - __ASM("rev16 r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - __ASM("rbit r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit values) - */ -uint8_t __LDREXB(uint8_t *addr) -{ - __ASM("ldrexb r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -uint16_t __LDREXH(uint16_t *addr) -{ - __ASM("ldrexh r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -uint32_t __LDREXW(uint32_t *addr) -{ - __ASM("ldrex r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - __ASM("strexb r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - __ASM("strexh r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - __ASM("strex r0, r0, [r1]"); - __ASM("bx lr"); -} - -#pragma diag_default=Pe940 - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) __attribute__( ( naked ) ); -uint32_t __get_PSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, psp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n\t" - "BX lr \n\t" : : "r" (topOfProcStack) ); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) __attribute__( ( naked ) ); -uint32_t __get_MSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, msp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n\t" - "BX lr \n\t" : : "r" (topOfMainStack) ); -} - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -uint32_t __get_BASEPRI(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -uint32_t __get_PRIMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -uint32_t __get_FAULTMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -uint32_t __get_CONTROL(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** - * @brief Reverse byte order in integer value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -uint32_t __REV(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -int32_t __REVSH(int16_t value) -{ - uint32_t result=0; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -uint8_t __LDREXB(uint8_t *addr) -{ - uint8_t result=0; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -uint16_t __LDREXH(uint16_t *addr) -{ - uint16_t result=0; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -uint32_t __LDREXW(uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/CoreSupport/core_cm3.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/CoreSupport/core_cm3.h deleted file mode 100644 index 2b6b51a7d..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/CoreSupport/core_cm3.h +++ /dev/null @@ -1,1818 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V1.30 - * @date 30. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CM3_CORE_H__ -#define __CM3_CORE_H__ - -/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration - * - * List of Lint messages which will be suppressed and not shown: - * - Error 10: \n - * register uint32_t __regBasePri __asm("basepri"); \n - * Error 10: Expecting ';' - * . - * - Error 530: \n - * return(__regBasePri); \n - * Warning 530: Symbol '__regBasePri' (line 264) not initialized - * . - * - Error 550: \n - * __regBasePri = (basePri & 0x1ff); \n - * Warning 550: Symbol '__regBasePri' (line 271) not accessed - * . - * - Error 754: \n - * uint32_t RESERVED0[24]; \n - * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced - * . - * - Error 750: \n - * #define __CM3_CORE_H__ \n - * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced - * . - * - Error 528: \n - * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n - * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced - * . - * - Error 751: \n - * } InterruptType_Type; \n - * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced - * . - * Note: To re-enable a Message, insert a space before 'lint' * - * - */ - -/*lint -save */ -/*lint -e10 */ -/*lint -e530 */ -/*lint -e550 */ -/*lint -e754 */ -/*lint -e750 */ -/*lint -e528 */ -/*lint -e751 */ - - -/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core registers and bitfields - - Cortex-M core peripheral base address - @{ - */ - -#ifdef __cplusplus - extern "C" { -#endif - -#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - -#include /* Include standard types */ - -#if defined (__ICCARM__) - #include /* IAR Intrinsics */ -#endif - - -#ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ -#endif - - - - -/** - * IO definitions - * - * define access restrictions to peripheral registers - */ - -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register - @{ -*/ - - -/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC - memory mapped structure for Nested Vectored Interrupt Controller (NVIC) - @{ - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ -} NVIC_Type; -/*@}*/ /* end of group CMSIS_CM3_NVIC */ - - -/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB - memory mapped structure for System Control Block (SCB) - @{ - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ -/*@}*/ /* end of group CMSIS_CM3_SCB */ - - -/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick - memory mapped structure for SysTick - @{ - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ -/*@}*/ /* end of group CMSIS_CM3_SysTick */ - - -/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM - memory mapped structure for Instrumentation Trace Macrocell (ITM) - @{ - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ - __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ - __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ -/*@}*/ /* end of group CMSIS_CM3_ITM */ - - -/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type - memory mapped structure for Interrupt Type - @{ - */ -typedef struct -{ - uint32_t RESERVED0; - __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ -#else - uint32_t RESERVED1; -#endif -} InterruptType_Type; - -/* Interrupt Controller Type Register Definitions */ -#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ -#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ -#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ - -#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ -#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ - -#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ -#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ -/*@}*/ /* end of group CMSIS_CM3_InterruptType */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) -/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU - memory mapped structure for Memory Protection Unit (MPU) - @{ - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ -#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ -#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ -#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ -#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ -#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ -#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@}*/ /* end of group CMSIS_CM3_MPU */ -#endif - - -/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug - memory mapped structure for Core Debug Register - @{ - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ -/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ - - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ - -#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ -#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_register */ - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#define __enable_fault_irq __enable_fiq -#define __disable_fault_irq __disable_fiq - -#define __NOP __nop -#define __WFI __wfi -#define __WFE __wfe -#define __SEV __sev -#define __ISB() __isb(0) -#define __DSB() __dsb(0) -#define __DMB() __dmb(0) -#define __REV __rev -#define __RBIT __rbit -#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) -#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) -#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) -#define __STREXB(value, ptr) __strex(value, ptr) -#define __STREXH(value, ptr) __strex(value, ptr) -#define __STREXW(value, ptr) __strex(value, ptr) - - -/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ -/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -extern void __CLREX(void); - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -#else /* (__ARMCC_VERSION >= 400000) */ - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -#define __CLREX __clrex - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -static __INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & 1); -} - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -static __INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ -#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ - -static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } -static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } - -#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ -static __INLINE void __WFI() { __ASM ("wfi"); } -static __INLINE void __WFE() { __ASM ("wfe"); } -static __INLINE void __SEV() { __ASM ("sev"); } -static __INLINE void __CLREX() { __ASM ("clrex"); } - -/* intrinsic void __ISB(void) */ -/* intrinsic void __DSB(void) */ -/* intrinsic void __DMB(void) */ -/* intrinsic void __set_PRIMASK(); */ -/* intrinsic void __get_PRIMASK(); */ -/* intrinsic void __set_FAULTMASK(); */ -/* intrinsic void __get_FAULTMASK(); */ -/* intrinsic uint32_t __REV(uint32_t value); */ -/* intrinsic uint32_t __REVSH(uint32_t value); */ -/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ -/* intrinsic unsigned long __LDREX(unsigned long *); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit values) - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } -static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } - -static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } -static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } - -static __INLINE void __NOP() { __ASM volatile ("nop"); } -static __INLINE void __WFI() { __ASM volatile ("wfi"); } -static __INLINE void __WFE() { __ASM volatile ("wfe"); } -static __INLINE void __SEV() { __ASM volatile ("sev"); } -static __INLINE void __ISB() { __ASM volatile ("isb"); } -static __INLINE void __DSB() { __ASM volatile ("dsb"); } -static __INLINE void __DMB() { __ASM volatile ("dmb"); } -static __INLINE void __CLREX() { __ASM volatile ("clrex"); } - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -/** - * @brief Reverse byte order in integer value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -extern uint32_t __REV(uint32_t value); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - - -/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface - Core Function Interface containing: - - Core NVIC Functions - - Core SysTick Functions - - Core Reset Functions -*/ -/*@{*/ - -/* ########################## NVIC functions #################################### */ - -/** - * @brief Set the Priority Grouping in NVIC Interrupt Controller - * - * @param PriorityGroup is priority grouping field - * - * Set the priority grouping field using the required unlock sequence. - * The parameter priority_grouping is assigned to the field - * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - (0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - -/** - * @brief Get the Priority Grouping from NVIC Interrupt Controller - * - * @return priority grouping field - * - * Get the priority grouping from NVIC Interrupt Controller. - * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - -/** - * @brief Enable Interrupt in NVIC Interrupt Controller - * - * @param IRQn The positive number of the external interrupt to enable - * - * Enable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - -/** - * @brief Disable the interrupt line for external interrupt specified - * - * @param IRQn The positive number of the external interrupt to disable - * - * Disable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - -/** - * @brief Read the interrupt pending bit for a device specific interrupt source - * - * @param IRQn The number of the device specifc interrupt - * @return 1 = interrupt pending, 0 = interrupt not pending - * - * Read the pending register in NVIC and return 1 if its status is pending, - * otherwise it returns 0 - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - -/** - * @brief Set the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for set pending - * - * Set the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - -/** - * @brief Clear the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for clear pending - * - * Clear the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - -/** - * @brief Read the active bit for an external interrupt - * - * @param IRQn The number of the interrupt for read active bit - * @return 1 = interrupt active, 0 = interrupt not active - * - * Read the active register in NVIC and returns 1 if its status is active, - * otherwise it returns 0. - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - -/** - * @brief Set the priority for an interrupt - * - * @param IRQn The number of the interrupt for set priority - * @param priority The priority to set - * - * Set the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - -/** - * @brief Read the priority for an interrupt - * - * @param IRQn The number of the interrupt for get priority - * @return The priority for the interrupt - * - * Read the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * The returned priority value is automatically aligned to the implemented - * priority bits of the microcontroller. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** - * @brief Encode the priority for an interrupt - * - * @param PriorityGroup The used priority group - * @param PreemptPriority The preemptive priority value (starting from 0) - * @param SubPriority The sub priority value (starting from 0) - * @return The encoded priority for the interrupt - * - * Encode the priority for an interrupt with the given priority group, - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The returned priority value can be used for NVIC_SetPriority(...) function - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** - * @brief Decode the priority of an interrupt - * - * @param Priority The priority for the interrupt - * @param PriorityGroup The used priority group - * @param pPreemptPriority The preemptive priority value (starting from 0) - * @param pSubPriority The sub priority value (starting from 0) - * - * Decode an interrupt priority value with the given priority group to - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The priority value can be retrieved with NVIC_GetPriority(...) function - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - - -/* ################################## SysTick function ############################################ */ - -#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) - -/** - * @brief Initialize and start the SysTick counter and its interrupt. - * - * @param ticks number of ticks between two interrupts - * @return 1 = failed, 0 = successful - * - * Initialise the system tick timer and its interrupt and start the - * system tick timer / counter in free running mode to generate - * periodical interrupts. - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - - - - -/* ################################## Reset function ############################################ */ - -/** - * @brief Initiate a system reset request. - * - * Initiate a system reset request to reset the MCU - */ -static __INLINE void NVIC_SystemReset(void) -{ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ - - - -/* ##################################### Debug In/Output function ########################################### */ - -/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface - Core Debug Interface containing: - - Core Debug Receive / Transmit Functions - - Core Debug Defines - - Core Debug Variables -*/ -/*@{*/ - -extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** - * @brief Outputs a character via the ITM channel 0 - * - * @param ch character to output - * @return character to output - * - * The function outputs a character via the ITM channel 0. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** - * @brief Inputs a character via variable ITM_RxBuffer - * - * @return received character, -1 = no character received - * - * The function inputs a character via variable ITM_RxBuffer. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE int ITM_ReceiveChar (void) { - int ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - * @brief Check if a character via variable ITM_RxBuffer is available - * - * @return 1 = character available, 0 = no character available - * - * The function checks variable ITM_RxBuffer whether a character is available or not. - * The function returns '1' if a character is available and '0' if no character is available. - */ -static __INLINE int ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_definitions */ - -#endif /* __CM3_CORE_H__ */ - -/*lint -restore */ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/Release_Notes.html b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/Release_Notes.html deleted file mode 100644 index b80f38df1..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/Release_Notes.html +++ /dev/null @@ -1,284 +0,0 @@ - - - - - - - - - - - - -Release Notes for STM32F10x CMSIS - - - - - -
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Release -Notes for STM32F10x CMSIS

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Copyright 2011 STMicroelectronics

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Contents

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  1. STM32F10x CMSIS -update History
    2. -
  2. License
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STM32F10x CMSIS -update History


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V3.5.0 / 11-March-2011

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Main -Changes

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  • stm32f10x.h -and startup_stm32f10x_hd_vl.s files: remove the FSMC interrupt -definition for STM32F10x High-density Value line devices.
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  • system_stm32f10x.c file provided within the CMSIS folder.
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3.4.0 -- 10/15/2010

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  1. General
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  • Add support -for STM32F10x High-density Value line devices.
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  1. STM32F10x CMSIS Device Peripheral Access Layer
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  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
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    • Update to support High-density Value line devices
      • Add new define STM32F10X_HD_VL
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      • RCC, AFIO, FSMC bits definition updated
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    • - - All -STM32 devices definitions are commented by default. User has to select the -appropriate device before starting else an error will be signaled on compile -time.
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    • Add new IRQs definitons inside the IRQn_Type enumeration for STM23 High-density Value line devices.
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    • "bool" type removed.
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  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
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    • "system_stm32f10x.c" moved to to "STM32F10x_StdPeriph_Template" directory. This file is also moved to each example directory under "STM32F10x_StdPeriph_Examples".
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    • SystemInit_ExtMemCtl() function: update to support High-density Value line devices.
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    • Add "VECT_TAB_SRAM" inside "system_stm32f10x.c" -to select if the user want to place the Vector Table in internal SRAM. -An additional define is also to specify the Vector Table offset "VECT_TAB_OFFSET".
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  • STM32F10x CMSIS startup files:startup_stm32f10x_xx.s
    • Add three -startup files for STM32 High-density Value line devices: - startup_stm32f10x_hd_vl.s
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3.3.0 -- 04/16/2010

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  1. General
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  • Add support -for STM32F10x XL-density devices.
  • Add startup files for TrueSTUDIO toolchain
  1. STM32F10x CMSIS Device Peripheral Access Layer
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  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
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    • Update to support XL-density devices
      • Add new define STM32F10X_XL
      • Add new IRQs for TIM9..14
      • Update FLASH_TypeDef structure
      • Add new IP instances TIM9..14
      • RCC, AFIO, DBGMCU bits definition updated
    • Correct IRQs definition for MD-, LD-, MD_VL- and LD_VL-density devices (remove comma "," at the end of enum list)
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
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    • SystemInit_ExtMemCtl() function: update to support XL-density devices
    • SystemInit() function: swap the order of SetSysClock() and SystemInit_ExtMemCtl() functions. 
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  • STM32F10x CMSIS startup files:
    • add three -startup files for STM32 XL-density devices: - startup_stm32f10x_xl.s
    • startup_stm32f10x_md_vl.s for RIDE7: add USART3 IRQ Handler (was missing in previous version)
    • Add startup files for TrueSTUDIO toolchain
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3.2.0 -- 03/01/2010

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  1. General
    2. -
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    - -
  • STM32F10x CMSIS files updated to CMSIS V1.30 release
    • -
  • Directory structure updated to be aligned with CMSIS V1.30
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    • -
  • Add support -for STM32 Low-density Value line (STM32F100x4/6) and -Medium-density Value line (STM32F100x8/B) devices. 
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  1. CMSIS Core Peripheral Access Layer
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  1. STM32F10x CMSIS Device Peripheral Access Layer
    2. - -
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    - -
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
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    • -
      -
    • Update -the stm32f10x.h file to support new Value line devices features: CEC -peripheral, new General purpose timers TIM15, TIM16 and TIM17.
      • -
    • Peripherals Bits definitions updated to be in line with Value line devices available features.
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      • -
    • HSE_Value, -HSI_Value and HSEStartup_TimeOut changed to upper case: HSE_VALUE, -HSI_VALUE and HSE_STARTUP_TIMEOUT. Old names are kept for legacy -purposes.
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  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
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    • -
      -
    • SystemFrequency variable name changed to SystemCoreClock
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      • -
    • Default - SystemCoreClock is changed to 24MHz when Value line devices are selected and to 72MHz on other devices.
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      • -
    • All while(1) loop were removed from all clock setting functions. User has to handle the HSE startup failure.
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      • -
    • Additional function void SystemCoreClockUpdate (void) is provided.
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  • STM32F10x CMSIS Startup files: startup_stm32f10x_xx.s
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      -
    • Add new -startup files for STM32 Low-density Value line devices: - startup_stm32f10x_ld_vl.s
      • -
    • Add new startup -files for STM32 Medium-density Value line devices: - startup_stm32f10x_md_vl.s
      • -
    • SystemInit() function is called from startup file (startup_stm32f10x_xx.s) before to branch to application main.
      -To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file
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      • -
    • GNU startup file for Low density devices (startup_stm32f10x_ld.s) is updated to fix compilation errors.
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      • -
    - -
- -
    -
-

License

-

The -enclosed firmware and all the related documentation are not covered by -a License Agreement, if you need such License you can contact your -local STMicroelectronics office.

-

THE -PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO -SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR -ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY -CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY -CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH -THEIR PRODUCTS.

-

 

-
-
-

For -complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers -visit www.st.com/STM32

-
-

-
-
-

 

-
- \ No newline at end of file diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_cl.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_cl.s deleted file mode 100644 index e34a52067..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_cl.s +++ /dev/null @@ -1,473 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f10x_cl.s - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief STM32F10x Connectivity line Devices vector table for Atollic - * toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR - * address. - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF1E0F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss - -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler - -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_IRQHandler - .word RTC_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_2_IRQHandler - .word CAN1_TX_IRQHandler - .word CAN1_RX0_IRQHandler - .word CAN1_RX1_IRQHandler - .word CAN1_SCE_IRQHandler - .word EXTI9_5_IRQHandler - .word TIM1_BRK_IRQHandler - .word TIM1_UP_IRQHandler - .word TIM1_TRG_COM_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTCAlarm_IRQHandler - .word OTG_FS_WKUP_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word TIM5_IRQHandler - .word SPI3_IRQHandler - .word UART4_IRQHandler - .word UART5_IRQHandler - .word TIM6_IRQHandler - .word TIM7_IRQHandler - .word DMA2_Channel1_IRQHandler - .word DMA2_Channel2_IRQHandler - .word DMA2_Channel3_IRQHandler - .word DMA2_Channel4_IRQHandler - .word DMA2_Channel5_IRQHandler - .word ETH_IRQHandler - .word ETH_WKUP_IRQHandler - .word CAN2_TX_IRQHandler - .word CAN2_RX0_IRQHandler - .word CAN2_RX1_IRQHandler - .word CAN2_SCE_IRQHandler - .word OTG_FS_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x1E0. This is for boot in RAM mode for - STM32F10x Connectivity line Devices. */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_IRQHandler - .thumb_set TAMPER_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_2_IRQHandler - .thumb_set ADC1_2_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_IRQHandler - .thumb_set TIM1_BRK_IRQHandler,Default_Handler - - .weak TIM1_UP_IRQHandler - .thumb_set TIM1_UP_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_IRQHandler - .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTCAlarm_IRQHandler - .thumb_set RTCAlarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_IRQHandler - .thumb_set TIM6_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Channel1_IRQHandler - .thumb_set DMA2_Channel1_IRQHandler,Default_Handler - - .weak DMA2_Channel2_IRQHandler - .thumb_set DMA2_Channel2_IRQHandler,Default_Handler - - .weak DMA2_Channel3_IRQHandler - .thumb_set DMA2_Channel3_IRQHandler,Default_Handler - - .weak DMA2_Channel4_IRQHandler - .thumb_set DMA2_Channel4_IRQHandler,Default_Handler - - .weak DMA2_Channel5_IRQHandler - .thumb_set DMA2_Channel5_IRQHandler,Default_Handler - - .weak ETH_IRQHandler - .thumb_set ETH_IRQHandler,Default_Handler - - .weak ETH_WKUP_IRQHandler - .thumb_set ETH_WKUP_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler ,Default_Handler - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd.s deleted file mode 100644 index 0aa91884f..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd.s +++ /dev/null @@ -1,469 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f10x_hd.s - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief STM32F10x High Density Devices vector table for Atollic toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address, - * - Configure the clock system - * - Configure external SRAM mounted on STM3210E-EVAL board - * to be used as data memory (optional, to be enabled by user) - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF1E0F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_IRQHandler - .word RTC_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_2_IRQHandler - .word USB_HP_CAN1_TX_IRQHandler - .word USB_LP_CAN1_RX0_IRQHandler - .word CAN1_RX1_IRQHandler - .word CAN1_SCE_IRQHandler - .word EXTI9_5_IRQHandler - .word TIM1_BRK_IRQHandler - .word TIM1_UP_IRQHandler - .word TIM1_TRG_COM_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTCAlarm_IRQHandler - .word USBWakeUp_IRQHandler - .word TIM8_BRK_IRQHandler - .word TIM8_UP_IRQHandler - .word TIM8_TRG_COM_IRQHandler - .word TIM8_CC_IRQHandler - .word ADC3_IRQHandler - .word FSMC_IRQHandler - .word SDIO_IRQHandler - .word TIM5_IRQHandler - .word SPI3_IRQHandler - .word UART4_IRQHandler - .word UART5_IRQHandler - .word TIM6_IRQHandler - .word TIM7_IRQHandler - .word DMA2_Channel1_IRQHandler - .word DMA2_Channel2_IRQHandler - .word DMA2_Channel3_IRQHandler - .word DMA2_Channel4_5_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x1E0. This is for boot in RAM mode for - STM32F10x High Density devices. */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_IRQHandler - .thumb_set TAMPER_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_2_IRQHandler - .thumb_set ADC1_2_IRQHandler,Default_Handler - - .weak USB_HP_CAN1_TX_IRQHandler - .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler - - .weak USB_LP_CAN1_RX0_IRQHandler - .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_IRQHandler - .thumb_set TIM1_BRK_IRQHandler,Default_Handler - - .weak TIM1_UP_IRQHandler - .thumb_set TIM1_UP_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_IRQHandler - .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTCAlarm_IRQHandler - .thumb_set RTCAlarm_IRQHandler,Default_Handler - - .weak USBWakeUp_IRQHandler - .thumb_set USBWakeUp_IRQHandler,Default_Handler - - .weak TIM8_BRK_IRQHandler - .thumb_set TIM8_BRK_IRQHandler,Default_Handler - - .weak TIM8_UP_IRQHandler - .thumb_set TIM8_UP_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_IRQHandler - .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak ADC3_IRQHandler - .thumb_set ADC3_IRQHandler,Default_Handler - - .weak FSMC_IRQHandler - .thumb_set FSMC_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_IRQHandler - .thumb_set TIM6_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Channel1_IRQHandler - .thumb_set DMA2_Channel1_IRQHandler,Default_Handler - - .weak DMA2_Channel2_IRQHandler - .thumb_set DMA2_Channel2_IRQHandler,Default_Handler - - .weak DMA2_Channel3_IRQHandler - .thumb_set DMA2_Channel3_IRQHandler,Default_Handler - - .weak DMA2_Channel4_5_IRQHandler - .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd_vl.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd_vl.s deleted file mode 100644 index 55aa39861..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd_vl.s +++ /dev/null @@ -1,451 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f10x_hd_vl.s - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief STM32F10x High Density Value Line Devices vector table for Atollic - * toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Configure external SRAM mounted on STM32100E-EVAL board - * to be used as data memory (optional, to be enabled by user) - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF108F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_IRQHandler - .word RTC_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word EXTI9_5_IRQHandler - .word TIM1_BRK_TIM15_IRQHandler - .word TIM1_UP_TIM16_IRQHandler - .word TIM1_TRG_COM_TIM17_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTCAlarm_IRQHandler - .word CEC_IRQHandler - .word TIM12_IRQHandler - .word TIM13_IRQHandler - .word TIM14_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word TIM5_IRQHandler - .word SPI3_IRQHandler - .word UART4_IRQHandler - .word UART5_IRQHandler - .word TIM6_DAC_IRQHandler - .word TIM7_IRQHandler - .word DMA2_Channel1_IRQHandler - .word DMA2_Channel2_IRQHandler - .word DMA2_Channel3_IRQHandler - .word DMA2_Channel4_5_IRQHandler - .word DMA2_Channel5_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x1E0. This is for boot in RAM mode for - STM32F10x High Density Value line devices. */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_IRQHandler - .thumb_set TAMPER_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM15_IRQHandler - .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM16_IRQHandler - .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM17_IRQHandler - .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTCAlarm_IRQHandler - .thumb_set RTCAlarm_IRQHandler,Default_Handler - - .weak CEC_IRQHandler - .thumb_set CEC_IRQHandler,Default_Handler - - .weak TIM12_IRQHandler - .thumb_set TIM12_IRQHandler,Default_Handler - - .weak TIM13_IRQHandler - .thumb_set TIM13_IRQHandler,Default_Handler - - .weak TIM14_IRQHandler - .thumb_set TIM14_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Channel1_IRQHandler - .thumb_set DMA2_Channel1_IRQHandler,Default_Handler - - .weak DMA2_Channel2_IRQHandler - .thumb_set DMA2_Channel2_IRQHandler,Default_Handler - - .weak DMA2_Channel3_IRQHandler - .thumb_set DMA2_Channel3_IRQHandler,Default_Handler - - .weak DMA2_Channel4_5_IRQHandler - .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler - - .weak DMA2_Channel5_IRQHandler - .thumb_set DMA2_Channel5_IRQHandler,Default_Handler - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld.s deleted file mode 100644 index 2c5aaa06b..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld.s +++ /dev/null @@ -1,347 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f10x_ld.s - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief STM32F10x Low Density Devices vector table for Atollic toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address. - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF108F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_IRQHandler - .word RTC_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_2_IRQHandler - .word USB_HP_CAN1_TX_IRQHandler - .word USB_LP_CAN1_RX0_IRQHandler - .word CAN1_RX1_IRQHandler - .word CAN1_SCE_IRQHandler - .word EXTI9_5_IRQHandler - .word TIM1_BRK_IRQHandler - .word TIM1_UP_IRQHandler - .word TIM1_TRG_COM_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word 0 - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word 0 - .word 0 - .word SPI1_IRQHandler - .word 0 - .word USART1_IRQHandler - .word USART2_IRQHandler - .word 0 - .word EXTI15_10_IRQHandler - .word RTCAlarm_IRQHandler - .word USBWakeUp_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x108. This is for boot in RAM mode for - STM32F10x Low Density devices.*/ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_IRQHandler - .thumb_set TAMPER_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_2_IRQHandler - .thumb_set ADC1_2_IRQHandler,Default_Handler - - .weak USB_HP_CAN1_TX_IRQHandler - .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler - - .weak USB_LP_CAN1_RX0_IRQHandler - .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_IRQHandler - .thumb_set TIM1_BRK_IRQHandler,Default_Handler - - .weak TIM1_UP_IRQHandler - .thumb_set TIM1_UP_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_IRQHandler - .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTCAlarm_IRQHandler - .thumb_set RTCAlarm_IRQHandler,Default_Handler - - .weak USBWakeUp_IRQHandler - .thumb_set USBWakeUp_IRQHandler,Default_Handler - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld_vl.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld_vl.s deleted file mode 100644 index 9af6e8ba0..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld_vl.s +++ /dev/null @@ -1,392 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f10x_ld_vl.s - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief STM32F10x Low Density Value Line Devices vector table for Atollic toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF108F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_IRQHandler - .word RTC_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word EXTI9_5_IRQHandler - .word TIM1_BRK_TIM15_IRQHandler - .word TIM1_UP_TIM16_IRQHandler - .word TIM1_TRG_COM_TIM17_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word 0 - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word 0 - .word 0 - .word SPI1_IRQHandler - .word 0 - .word USART1_IRQHandler - .word USART2_IRQHandler - .word 0 - .word EXTI15_10_IRQHandler - .word RTCAlarm_IRQHandler - .word CEC_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word TIM6_DAC_IRQHandler - .word TIM7_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x01CC. This is for boot in RAM mode for - STM32F10x Medium Value Line Density devices. */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_IRQHandler - .thumb_set TAMPER_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM15_IRQHandler - .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM16_IRQHandler - .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM17_IRQHandler - .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTCAlarm_IRQHandler - .thumb_set RTCAlarm_IRQHandler,Default_Handler - - .weak CEC_IRQHandler - .thumb_set CEC_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md.s deleted file mode 100644 index c14ba2104..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md.s +++ /dev/null @@ -1,363 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f10x_md.s - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief STM32F10x Medium Density Devices vector table for Atollic toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF108F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_IRQHandler - .word RTC_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_2_IRQHandler - .word USB_HP_CAN1_TX_IRQHandler - .word USB_LP_CAN1_RX0_IRQHandler - .word CAN1_RX1_IRQHandler - .word CAN1_SCE_IRQHandler - .word EXTI9_5_IRQHandler - .word TIM1_BRK_IRQHandler - .word TIM1_UP_IRQHandler - .word TIM1_TRG_COM_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTCAlarm_IRQHandler - .word USBWakeUp_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x108. This is for boot in RAM mode for - STM32F10x Medium Density devices. */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_IRQHandler - .thumb_set TAMPER_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_2_IRQHandler - .thumb_set ADC1_2_IRQHandler,Default_Handler - - .weak USB_HP_CAN1_TX_IRQHandler - .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler - - .weak USB_LP_CAN1_RX0_IRQHandler - .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_IRQHandler - .thumb_set TIM1_BRK_IRQHandler,Default_Handler - - .weak TIM1_UP_IRQHandler - .thumb_set TIM1_UP_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_IRQHandler - .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTCAlarm_IRQHandler - .thumb_set RTCAlarm_IRQHandler,Default_Handler - - .weak USBWakeUp_IRQHandler - .thumb_set USBWakeUp_IRQHandler,Default_Handler - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md_vl.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md_vl.s deleted file mode 100644 index 4ac1230db..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md_vl.s +++ /dev/null @@ -1,408 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f10x_md_vl.s - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief STM32F10x Medium Density Value Line Devices vector table for Atollic - * toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF108F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_IRQHandler - .word RTC_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word EXTI9_5_IRQHandler - .word TIM1_BRK_TIM15_IRQHandler - .word TIM1_UP_TIM16_IRQHandler - .word TIM1_TRG_COM_TIM17_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTCAlarm_IRQHandler - .word CEC_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word TIM6_DAC_IRQHandler - .word TIM7_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x01CC. This is for boot in RAM mode for - STM32F10x Medium Value Line Density devices. */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_IRQHandler - .thumb_set TAMPER_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM15_IRQHandler - .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM16_IRQHandler - .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM17_IRQHandler - .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTCAlarm_IRQHandler - .thumb_set RTCAlarm_IRQHandler,Default_Handler - - .weak CEC_IRQHandler - .thumb_set CEC_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s deleted file mode 100644 index 19bdf5a8c..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s +++ /dev/null @@ -1,467 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f10x_xl.s - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief STM32F10x XL-Density Devices vector table for TrueSTUDIO toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system and the external SRAM mounted on - * STM3210E-EVAL board to be used as data memory (optional, - * to be enabled by user) - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF1E0F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_IRQHandler - .word RTC_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_2_IRQHandler - .word USB_HP_CAN1_TX_IRQHandler - .word USB_LP_CAN1_RX0_IRQHandler - .word CAN1_RX1_IRQHandler - .word CAN1_SCE_IRQHandler - .word EXTI9_5_IRQHandler - .word TIM1_BRK_TIM9_IRQHandler - .word TIM1_UP_TIM10_IRQHandler - .word TIM1_TRG_COM_TIM11_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTCAlarm_IRQHandler - .word USBWakeUp_IRQHandler - .word TIM8_BRK_TIM12_IRQHandler - .word TIM8_UP_TIM13_IRQHandler - .word TIM8_TRG_COM_TIM14_IRQHandler - .word TIM8_CC_IRQHandler - .word ADC3_IRQHandler - .word FSMC_IRQHandler - .word SDIO_IRQHandler - .word TIM5_IRQHandler - .word SPI3_IRQHandler - .word UART4_IRQHandler - .word UART5_IRQHandler - .word TIM6_IRQHandler - .word TIM7_IRQHandler - .word DMA2_Channel1_IRQHandler - .word DMA2_Channel2_IRQHandler - .word DMA2_Channel3_IRQHandler - .word DMA2_Channel4_5_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x1E0. This is for boot in RAM mode for - STM32F10x XL-Density devices. */ -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_IRQHandler - .thumb_set TAMPER_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_2_IRQHandler - .thumb_set ADC1_2_IRQHandler,Default_Handler - - .weak USB_HP_CAN1_TX_IRQHandler - .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler - - .weak USB_LP_CAN1_RX0_IRQHandler - .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTCAlarm_IRQHandler - .thumb_set RTCAlarm_IRQHandler,Default_Handler - - .weak USBWakeUp_IRQHandler - .thumb_set USBWakeUp_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak ADC3_IRQHandler - .thumb_set ADC3_IRQHandler,Default_Handler - - .weak FSMC_IRQHandler - .thumb_set FSMC_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_IRQHandler - .thumb_set TIM6_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Channel1_IRQHandler - .thumb_set DMA2_Channel1_IRQHandler,Default_Handler - - .weak DMA2_Channel2_IRQHandler - .thumb_set DMA2_Channel2_IRQHandler,Default_Handler - - .weak DMA2_Channel3_IRQHandler - .thumb_set DMA2_Channel3_IRQHandler,Default_Handler - - .weak DMA2_Channel4_5_IRQHandler - .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s deleted file mode 100644 index 8196e697f..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s +++ /dev/null @@ -1,368 +0,0 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** -;* File Name : startup_stm32f10x_cl.s -;* Author : MCD Application Team -;* Version : V3.5.0 -;* Date : 11-March-2011 -;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM -;* toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Configure the clock system -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Tamper - DCD RTC_IRQHandler ; RTC - DCD FLASH_IRQHandler ; Flash - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_2_IRQHandler ; ADC1 and ADC2 - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD TIM1_BRK_IRQHandler ; TIM1 Break - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C1 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_IRQHandler ; TIM6 - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 - DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 - DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 - DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4 - DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMPER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_2_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_IRQHandler [WEAK] - EXPORT TIM1_UP_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTCAlarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Channel1_IRQHandler [WEAK] - EXPORT DMA2_Channel2_IRQHandler [WEAK] - EXPORT DMA2_Channel3_IRQHandler [WEAK] - EXPORT DMA2_Channel4_IRQHandler [WEAK] - EXPORT DMA2_Channel5_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMPER_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -DMA1_Channel5_IRQHandler -DMA1_Channel6_IRQHandler -DMA1_Channel7_IRQHandler -ADC1_2_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_IRQHandler -TIM1_UP_IRQHandler -TIM1_TRG_COM_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTCAlarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_IRQHandler -TIM7_IRQHandler -DMA2_Channel1_IRQHandler -DMA2_Channel2_IRQHandler -DMA2_Channel3_IRQHandler -DMA2_Channel4_IRQHandler -DMA2_Channel5_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler - - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s deleted file mode 100644 index adc9b94a9..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s +++ /dev/null @@ -1,358 +0,0 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** -;* File Name : startup_stm32f10x_hd.s -;* Author : MCD Application Team -;* Version : V3.5.0 -;* Date : 11-March-2011 -;* Description : STM32F10x High Density Devices vector table for MDK-ARM -;* toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Configure the clock system and also configure the external -;* SRAM mounted on STM3210E-EVAL board to be used as data -;* memory (optional, to be enabled by user) -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Tamper - DCD RTC_IRQHandler ; RTC - DCD FLASH_IRQHandler ; Flash - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_2_IRQHandler ; ADC1 & ADC2 - DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX - DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD TIM1_BRK_IRQHandler ; TIM1 Break - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line - DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend - DCD TIM8_BRK_IRQHandler ; TIM8 Break - DCD TIM8_UP_IRQHandler ; TIM8 Update - DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD ADC3_IRQHandler ; ADC3 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_IRQHandler ; TIM6 - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 - DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 - DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 - DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMPER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_2_IRQHandler [WEAK] - EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] - EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_IRQHandler [WEAK] - EXPORT TIM1_UP_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTCAlarm_IRQHandler [WEAK] - EXPORT USBWakeUp_IRQHandler [WEAK] - EXPORT TIM8_BRK_IRQHandler [WEAK] - EXPORT TIM8_UP_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT ADC3_IRQHandler [WEAK] - EXPORT FSMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Channel1_IRQHandler [WEAK] - EXPORT DMA2_Channel2_IRQHandler [WEAK] - EXPORT DMA2_Channel3_IRQHandler [WEAK] - EXPORT DMA2_Channel4_5_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMPER_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -DMA1_Channel5_IRQHandler -DMA1_Channel6_IRQHandler -DMA1_Channel7_IRQHandler -ADC1_2_IRQHandler -USB_HP_CAN1_TX_IRQHandler -USB_LP_CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_IRQHandler -TIM1_UP_IRQHandler -TIM1_TRG_COM_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTCAlarm_IRQHandler -USBWakeUp_IRQHandler -TIM8_BRK_IRQHandler -TIM8_UP_IRQHandler -TIM8_TRG_COM_IRQHandler -TIM8_CC_IRQHandler -ADC3_IRQHandler -FSMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_IRQHandler -TIM7_IRQHandler -DMA2_Channel1_IRQHandler -DMA2_Channel2_IRQHandler -DMA2_Channel3_IRQHandler -DMA2_Channel4_5_IRQHandler - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd_vl.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd_vl.s deleted file mode 100644 index d6082b096..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd_vl.s +++ /dev/null @@ -1,346 +0,0 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** -;* File Name : startup_stm32f10x_hd_vl.s -;* Author : MCD Application Team -;* Version : V3.5.0 -;* Date : 11-March-2011 -;* Description : STM32F10x High Density Value Line Devices vector table -;* for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Configure the clock system and also configure the external -;* SRAM mounted on STM32100E-EVAL board to be used as data -;* memory (optional, to be enabled by user) -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Tamper - DCD RTC_IRQHandler ; RTC - DCD FLASH_IRQHandler ; Flash - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_IRQHandler ; ADC1 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 - DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 - DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line - DCD CEC_IRQHandler ; HDMI-CEC - DCD TIM12_IRQHandler ; TIM12 - DCD TIM13_IRQHandler ; TIM13 - DCD TIM14_IRQHandler ; TIM14 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 - DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 - DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 - DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 - DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMPER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTCAlarm_IRQHandler [WEAK] - EXPORT CEC_IRQHandler [WEAK] - EXPORT TIM12_IRQHandler [WEAK] - EXPORT TIM13_IRQHandler [WEAK] - EXPORT TIM14_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Channel1_IRQHandler [WEAK] - EXPORT DMA2_Channel2_IRQHandler [WEAK] - EXPORT DMA2_Channel3_IRQHandler [WEAK] - EXPORT DMA2_Channel4_5_IRQHandler [WEAK] - EXPORT DMA2_Channel5_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMPER_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -DMA1_Channel5_IRQHandler -DMA1_Channel6_IRQHandler -DMA1_Channel7_IRQHandler -ADC1_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM15_IRQHandler -TIM1_UP_TIM16_IRQHandler -TIM1_TRG_COM_TIM17_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTCAlarm_IRQHandler -CEC_IRQHandler -TIM12_IRQHandler -TIM13_IRQHandler -TIM14_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Channel1_IRQHandler -DMA2_Channel2_IRQHandler -DMA2_Channel3_IRQHandler -DMA2_Channel4_5_IRQHandler -DMA2_Channel5_IRQHandler - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s deleted file mode 100644 index 3f3ac2ffd..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s +++ /dev/null @@ -1,297 +0,0 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** -;* File Name : startup_stm32f10x_ld.s -;* Author : MCD Application Team -;* Version : V3.5.0 -;* Date : 11-March-2011 -;* Description : STM32F10x Low Density Devices vector table for MDK-ARM -;* toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Configure the clock system -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Tamper - DCD RTC_IRQHandler ; RTC - DCD FLASH_IRQHandler ; Flash - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_2_IRQHandler ; ADC1_2 - DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX - DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD TIM1_BRK_IRQHandler ; TIM1 Break - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD 0 ; Reserved - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SPI1_IRQHandler ; SPI1 - DCD 0 ; Reserved - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD 0 ; Reserved - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line - DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMPER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_2_IRQHandler [WEAK] - EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] - EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_IRQHandler [WEAK] - EXPORT TIM1_UP_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTCAlarm_IRQHandler [WEAK] - EXPORT USBWakeUp_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMPER_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -DMA1_Channel5_IRQHandler -DMA1_Channel6_IRQHandler -DMA1_Channel7_IRQHandler -ADC1_2_IRQHandler -USB_HP_CAN1_TX_IRQHandler -USB_LP_CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_IRQHandler -TIM1_UP_IRQHandler -TIM1_TRG_COM_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -SPI1_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -EXTI15_10_IRQHandler -RTCAlarm_IRQHandler -USBWakeUp_IRQHandler - - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s deleted file mode 100644 index fe22fc011..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s +++ /dev/null @@ -1,304 +0,0 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** -;* File Name : startup_stm32f10x_ld_vl.s -;* Author : MCD Application Team -;* Version : V3.5.0 -;* Date : 11-March-2011 -;* Description : STM32F10x Low Density Value Line Devices vector table -;* for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Configure the clock system -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Tamper - DCD RTC_IRQHandler ; RTC - DCD FLASH_IRQHandler ; Flash - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_IRQHandler ; ADC1 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 - DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 - DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD 0 ; Reserved - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SPI1_IRQHandler ; SPI1 - DCD 0 ; Reserved - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD 0 ; Reserved - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line - DCD CEC_IRQHandler ; HDMI-CEC - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun - DCD TIM7_IRQHandler ; TIM7 -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMPER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTCAlarm_IRQHandler [WEAK] - EXPORT CEC_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] -WWDG_IRQHandler -PVD_IRQHandler -TAMPER_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -DMA1_Channel5_IRQHandler -DMA1_Channel6_IRQHandler -DMA1_Channel7_IRQHandler -ADC1_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM15_IRQHandler -TIM1_UP_TIM16_IRQHandler -TIM1_TRG_COM_TIM17_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -SPI1_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -EXTI15_10_IRQHandler -RTCAlarm_IRQHandler -CEC_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md.s deleted file mode 100644 index 3223fc95b..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md.s +++ /dev/null @@ -1,307 +0,0 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** -;* File Name : startup_stm32f10x_md.s -;* Author : MCD Application Team -;* Version : V3.5.0 -;* Date : 11-March-2011 -;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM -;* toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Configure the clock system -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Tamper - DCD RTC_IRQHandler ; RTC - DCD FLASH_IRQHandler ; Flash - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_2_IRQHandler ; ADC1_2 - DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX - DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD TIM1_BRK_IRQHandler ; TIM1 Break - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line - DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMPER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_2_IRQHandler [WEAK] - EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] - EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_IRQHandler [WEAK] - EXPORT TIM1_UP_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTCAlarm_IRQHandler [WEAK] - EXPORT USBWakeUp_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMPER_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -DMA1_Channel5_IRQHandler -DMA1_Channel6_IRQHandler -DMA1_Channel7_IRQHandler -ADC1_2_IRQHandler -USB_HP_CAN1_TX_IRQHandler -USB_LP_CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_IRQHandler -TIM1_UP_IRQHandler -TIM1_TRG_COM_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTCAlarm_IRQHandler -USBWakeUp_IRQHandler - - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s deleted file mode 100644 index d3b8aa6c1..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s +++ /dev/null @@ -1,315 +0,0 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** -;* File Name : startup_stm32f10x_md_vl.s -;* Author : MCD Application Team -;* Version : V3.5.0 -;* Date : 11-March-2011 -;* Description : STM32F10x Medium Density Value Line Devices vector table -;* for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Configure the clock system -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Tamper - DCD RTC_IRQHandler ; RTC - DCD FLASH_IRQHandler ; Flash - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_IRQHandler ; ADC1 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 - DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 - DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line - DCD CEC_IRQHandler ; HDMI-CEC - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun - DCD TIM7_IRQHandler ; TIM7 -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMPER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTCAlarm_IRQHandler [WEAK] - EXPORT CEC_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMPER_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -DMA1_Channel5_IRQHandler -DMA1_Channel6_IRQHandler -DMA1_Channel7_IRQHandler -ADC1_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM15_IRQHandler -TIM1_UP_TIM16_IRQHandler -TIM1_TRG_COM_TIM17_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTCAlarm_IRQHandler -CEC_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_xl.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_xl.s deleted file mode 100644 index 7970052d7..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_xl.s +++ /dev/null @@ -1,358 +0,0 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** -;* File Name : startup_stm32f10x_xl.s -;* Author : MCD Application Team -;* Version : V3.5.0 -;* Date : 11-March-2011 -;* Description : STM32F10x XL-Density Devices vector table for MDK-ARM -;* toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Configure the clock system and also configure the external -;* SRAM mounted on STM3210E-EVAL board to be used as data -;* memory (optional, to be enabled by user) -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Tamper - DCD RTC_IRQHandler ; RTC - DCD FLASH_IRQHandler ; Flash - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_2_IRQHandler ; ADC1 & ADC2 - DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX - DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line - DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD ADC3_IRQHandler ; ADC3 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_IRQHandler ; TIM6 - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 - DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 - DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 - DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMPER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_2_IRQHandler [WEAK] - EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] - EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTCAlarm_IRQHandler [WEAK] - EXPORT USBWakeUp_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT ADC3_IRQHandler [WEAK] - EXPORT FSMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Channel1_IRQHandler [WEAK] - EXPORT DMA2_Channel2_IRQHandler [WEAK] - EXPORT DMA2_Channel3_IRQHandler [WEAK] - EXPORT DMA2_Channel4_5_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMPER_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -DMA1_Channel5_IRQHandler -DMA1_Channel6_IRQHandler -DMA1_Channel7_IRQHandler -ADC1_2_IRQHandler -USB_HP_CAN1_TX_IRQHandler -USB_LP_CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTCAlarm_IRQHandler -USBWakeUp_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -ADC3_IRQHandler -FSMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_IRQHandler -TIM7_IRQHandler -DMA2_Channel1_IRQHandler -DMA2_Channel2_IRQHandler -DMA2_Channel3_IRQHandler -DMA2_Channel4_5_IRQHandler - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s deleted file mode 100644 index 039ec06ca..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s +++ /dev/null @@ -1,468 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f10x_cl.s - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief STM32F10x Connectivity line Devices vector table for RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR - * address. - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF1E0F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss - -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler - -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_IRQHandler - .word RTC_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_2_IRQHandler - .word CAN1_TX_IRQHandler - .word CAN1_RX0_IRQHandler - .word CAN1_RX1_IRQHandler - .word CAN1_SCE_IRQHandler - .word EXTI9_5_IRQHandler - .word TIM1_BRK_IRQHandler - .word TIM1_UP_IRQHandler - .word TIM1_TRG_COM_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTCAlarm_IRQHandler - .word OTG_FS_WKUP_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word TIM5_IRQHandler - .word SPI3_IRQHandler - .word UART4_IRQHandler - .word UART5_IRQHandler - .word TIM6_IRQHandler - .word TIM7_IRQHandler - .word DMA2_Channel1_IRQHandler - .word DMA2_Channel2_IRQHandler - .word DMA2_Channel3_IRQHandler - .word DMA2_Channel4_IRQHandler - .word DMA2_Channel5_IRQHandler - .word ETH_IRQHandler - .word ETH_WKUP_IRQHandler - .word CAN2_TX_IRQHandler - .word CAN2_RX0_IRQHandler - .word CAN2_RX1_IRQHandler - .word CAN2_SCE_IRQHandler - .word OTG_FS_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x1E0. This is for boot in RAM mode for - STM32F10x Connectivity line Devices. */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_IRQHandler - .thumb_set TAMPER_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_2_IRQHandler - .thumb_set ADC1_2_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_IRQHandler - .thumb_set TIM1_BRK_IRQHandler,Default_Handler - - .weak TIM1_UP_IRQHandler - .thumb_set TIM1_UP_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_IRQHandler - .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTCAlarm_IRQHandler - .thumb_set RTCAlarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_IRQHandler - .thumb_set TIM6_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Channel1_IRQHandler - .thumb_set DMA2_Channel1_IRQHandler,Default_Handler - - .weak DMA2_Channel2_IRQHandler - .thumb_set DMA2_Channel2_IRQHandler,Default_Handler - - .weak DMA2_Channel3_IRQHandler - .thumb_set DMA2_Channel3_IRQHandler,Default_Handler - - .weak DMA2_Channel4_IRQHandler - .thumb_set DMA2_Channel4_IRQHandler,Default_Handler - - .weak DMA2_Channel5_IRQHandler - .thumb_set DMA2_Channel5_IRQHandler,Default_Handler - - .weak ETH_IRQHandler - .thumb_set ETH_IRQHandler,Default_Handler - - .weak ETH_WKUP_IRQHandler - .thumb_set ETH_WKUP_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler ,Default_Handler - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s deleted file mode 100644 index e4ba08c41..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s +++ /dev/null @@ -1,465 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f10x_hd.s - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief STM32F10x High Density Devices vector table for RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system and the external SRAM mounted on - * STM3210E-EVAL board to be used as data memory (optional, - * to be enabled by user) - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -.equ BootRAM, 0xF1E0F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_IRQHandler - .word RTC_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_2_IRQHandler - .word USB_HP_CAN1_TX_IRQHandler - .word USB_LP_CAN1_RX0_IRQHandler - .word CAN1_RX1_IRQHandler - .word CAN1_SCE_IRQHandler - .word EXTI9_5_IRQHandler - .word TIM1_BRK_IRQHandler - .word TIM1_UP_IRQHandler - .word TIM1_TRG_COM_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTCAlarm_IRQHandler - .word USBWakeUp_IRQHandler - .word TIM8_BRK_IRQHandler - .word TIM8_UP_IRQHandler - .word TIM8_TRG_COM_IRQHandler - .word TIM8_CC_IRQHandler - .word ADC3_IRQHandler - .word FSMC_IRQHandler - .word SDIO_IRQHandler - .word TIM5_IRQHandler - .word SPI3_IRQHandler - .word UART4_IRQHandler - .word UART5_IRQHandler - .word TIM6_IRQHandler - .word TIM7_IRQHandler - .word DMA2_Channel1_IRQHandler - .word DMA2_Channel2_IRQHandler - .word DMA2_Channel3_IRQHandler - .word DMA2_Channel4_5_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x1E0. This is for boot in RAM mode for - STM32F10x High Density devices. */ -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_IRQHandler - .thumb_set TAMPER_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_2_IRQHandler - .thumb_set ADC1_2_IRQHandler,Default_Handler - - .weak USB_HP_CAN1_TX_IRQHandler - .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler - - .weak USB_LP_CAN1_RX0_IRQHandler - .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_IRQHandler - .thumb_set TIM1_BRK_IRQHandler,Default_Handler - - .weak TIM1_UP_IRQHandler - .thumb_set TIM1_UP_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_IRQHandler - .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTCAlarm_IRQHandler - .thumb_set RTCAlarm_IRQHandler,Default_Handler - - .weak USBWakeUp_IRQHandler - .thumb_set USBWakeUp_IRQHandler,Default_Handler - - .weak TIM8_BRK_IRQHandler - .thumb_set TIM8_BRK_IRQHandler,Default_Handler - - .weak TIM8_UP_IRQHandler - .thumb_set TIM8_UP_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_IRQHandler - .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak ADC3_IRQHandler - .thumb_set ADC3_IRQHandler,Default_Handler - - .weak FSMC_IRQHandler - .thumb_set FSMC_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_IRQHandler - .thumb_set TIM6_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Channel1_IRQHandler - .thumb_set DMA2_Channel1_IRQHandler,Default_Handler - - .weak DMA2_Channel2_IRQHandler - .thumb_set DMA2_Channel2_IRQHandler,Default_Handler - - .weak DMA2_Channel3_IRQHandler - .thumb_set DMA2_Channel3_IRQHandler,Default_Handler - - .weak DMA2_Channel4_5_IRQHandler - .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd_vl.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd_vl.s deleted file mode 100644 index daad5cc34..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd_vl.s +++ /dev/null @@ -1,442 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f10x_hd_vl.s - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief STM32F10x High Density Value Line Devices vector table for RIDE7 - * toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system and the external SRAM mounted on - * STM32100E-EVAL board to be used as data memory (optional, - * to be enabled by user) - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF108F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_IRQHandler - .word RTC_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word EXTI9_5_IRQHandler - .word TIM1_BRK_TIM15_IRQHandler - .word TIM1_UP_TIM16_IRQHandler - .word TIM1_TRG_COM_TIM17_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTCAlarm_IRQHandler - .word CEC_IRQHandler - .word TIM12_IRQHandler - .word TIM13_IRQHandler - .word TIM14_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word TIM5_IRQHandler - .word SPI3_IRQHandler - .word UART4_IRQHandler - .word UART5_IRQHandler - .word TIM6_DAC_IRQHandler - .word TIM7_IRQHandler - .word DMA2_Channel1_IRQHandler - .word DMA2_Channel2_IRQHandler - .word DMA2_Channel3_IRQHandler - .word DMA2_Channel4_5_IRQHandler - .word DMA2_Channel5_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x1E0. This is for boot in RAM mode for - STM32F10x High Density Value line devices. */ - -/******************************************************************************* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_IRQHandler - .thumb_set TAMPER_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM15_IRQHandler - .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM16_IRQHandler - .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM17_IRQHandler - .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTCAlarm_IRQHandler - .thumb_set RTCAlarm_IRQHandler,Default_Handler - - .weak CEC_IRQHandler - .thumb_set CEC_IRQHandler,Default_Handler - - .weak TIM12_IRQHandler - .thumb_set TIM12_IRQHandler,Default_Handler - - .weak TIM13_IRQHandler - .thumb_set TIM13_IRQHandler,Default_Handler - - .weak TIM14_IRQHandler - .thumb_set TIM14_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Channel1_IRQHandler - .thumb_set DMA2_Channel1_IRQHandler,Default_Handler - - .weak DMA2_Channel2_IRQHandler - .thumb_set DMA2_Channel2_IRQHandler,Default_Handler - - .weak DMA2_Channel3_IRQHandler - .thumb_set DMA2_Channel3_IRQHandler,Default_Handler - - .weak DMA2_Channel4_5_IRQHandler - .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler - - .weak DMA2_Channel5_IRQHandler - .thumb_set DMA2_Channel5_IRQHandler,Default_Handler - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s deleted file mode 100644 index aaa09ecd4..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s +++ /dev/null @@ -1,343 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f10x_ld.s - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief STM32F10x Low Density Devices vector table for RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF108F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_IRQHandler - .word RTC_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_2_IRQHandler - .word USB_HP_CAN1_TX_IRQHandler - .word USB_LP_CAN1_RX0_IRQHandler - .word CAN1_RX1_IRQHandler - .word CAN1_SCE_IRQHandler - .word EXTI9_5_IRQHandler - .word TIM1_BRK_IRQHandler - .word TIM1_UP_IRQHandler - .word TIM1_TRG_COM_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word 0 - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word 0 - .word 0 - .word SPI1_IRQHandler - .word 0 - .word USART1_IRQHandler - .word USART2_IRQHandler - .word 0 - .word EXTI15_10_IRQHandler - .word RTCAlarm_IRQHandler - .word USBWakeUp_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x108. This is for boot in RAM mode for - STM32F10x Low Density devices.*/ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_IRQHandler - .thumb_set TAMPER_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_2_IRQHandler - .thumb_set ADC1_2_IRQHandler,Default_Handler - - .weak USB_HP_CAN1_TX_IRQHandler - .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler - - .weak USB_LP_CAN1_RX0_IRQHandler - .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_IRQHandler - .thumb_set TIM1_BRK_IRQHandler,Default_Handler - - .weak TIM1_UP_IRQHandler - .thumb_set TIM1_UP_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_IRQHandler - .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTCAlarm_IRQHandler - .thumb_set RTCAlarm_IRQHandler,Default_Handler - - .weak USBWakeUp_IRQHandler - .thumb_set USBWakeUp_IRQHandler,Default_Handler - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld_vl.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld_vl.s deleted file mode 100644 index d4401be2f..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld_vl.s +++ /dev/null @@ -1,383 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f10x_ld_vl.s - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief STM32F10x Low Density Value Line Devices vector table for RIDE7 - * toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF108F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_IRQHandler - .word RTC_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word EXTI9_5_IRQHandler - .word TIM1_BRK_TIM15_IRQHandler - .word TIM1_UP_TIM16_IRQHandler - .word TIM1_TRG_COM_TIM17_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word 0 - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word 0 - .word 0 - .word SPI1_IRQHandler - .word 0 - .word USART1_IRQHandler - .word USART2_IRQHandler - .word 0 - .word EXTI15_10_IRQHandler - .word RTCAlarm_IRQHandler - .word CEC_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word TIM6_DAC_IRQHandler - .word TIM7_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x01CC. This is for boot in RAM mode for - STM32F10x Low Density Value Line devices. */ - -/******************************************************************************* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_IRQHandler - .thumb_set TAMPER_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM15_IRQHandler - .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM16_IRQHandler - .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM17_IRQHandler - .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTCAlarm_IRQHandler - .thumb_set RTCAlarm_IRQHandler,Default_Handler - - .weak CEC_IRQHandler - .thumb_set CEC_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s deleted file mode 100644 index 4b4a0502b..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s +++ /dev/null @@ -1,358 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f10x_md.s - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF108F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_IRQHandler - .word RTC_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_2_IRQHandler - .word USB_HP_CAN1_TX_IRQHandler - .word USB_LP_CAN1_RX0_IRQHandler - .word CAN1_RX1_IRQHandler - .word CAN1_SCE_IRQHandler - .word EXTI9_5_IRQHandler - .word TIM1_BRK_IRQHandler - .word TIM1_UP_IRQHandler - .word TIM1_TRG_COM_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTCAlarm_IRQHandler - .word USBWakeUp_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x108. This is for boot in RAM mode for - STM32F10x Medium Density devices. */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_IRQHandler - .thumb_set TAMPER_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_2_IRQHandler - .thumb_set ADC1_2_IRQHandler,Default_Handler - - .weak USB_HP_CAN1_TX_IRQHandler - .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler - - .weak USB_LP_CAN1_RX0_IRQHandler - .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_IRQHandler - .thumb_set TIM1_BRK_IRQHandler,Default_Handler - - .weak TIM1_UP_IRQHandler - .thumb_set TIM1_UP_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_IRQHandler - .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTCAlarm_IRQHandler - .thumb_set RTCAlarm_IRQHandler,Default_Handler - - .weak USBWakeUp_IRQHandler - .thumb_set USBWakeUp_IRQHandler,Default_Handler - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md_vl.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md_vl.s deleted file mode 100644 index 8bce9979b..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md_vl.s +++ /dev/null @@ -1,399 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f10x_md_vl.s - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief STM32F10x Medium Density Value Line Devices vector table for RIDE7 - * toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF108F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_IRQHandler - .word RTC_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word EXTI9_5_IRQHandler - .word TIM1_BRK_TIM15_IRQHandler - .word TIM1_UP_TIM16_IRQHandler - .word TIM1_TRG_COM_TIM17_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTCAlarm_IRQHandler - .word CEC_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word TIM6_DAC_IRQHandler - .word TIM7_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x01CC. This is for boot in RAM mode for - STM32F10x Medium Value Line Density devices. */ - -/******************************************************************************* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_IRQHandler - .thumb_set TAMPER_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM15_IRQHandler - .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM16_IRQHandler - .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM17_IRQHandler - .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTCAlarm_IRQHandler - .thumb_set RTCAlarm_IRQHandler,Default_Handler - - .weak CEC_IRQHandler - .thumb_set CEC_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_xl.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_xl.s deleted file mode 100644 index 3d727a0d5..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_xl.s +++ /dev/null @@ -1,465 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f10x_xl.s - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief STM32F10x XL-Density Devices vector table for RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system and the external SRAM mounted on - * STM3210E-EVAL board to be used as data memory (optional, - * to be enabled by user) - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -.equ BootRAM, 0xF1E0F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_IRQHandler - .word RTC_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_2_IRQHandler - .word USB_HP_CAN1_TX_IRQHandler - .word USB_LP_CAN1_RX0_IRQHandler - .word CAN1_RX1_IRQHandler - .word CAN1_SCE_IRQHandler - .word EXTI9_5_IRQHandler - .word TIM1_BRK_TIM9_IRQHandler - .word TIM1_UP_TIM10_IRQHandler - .word TIM1_TRG_COM_TIM11_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTCAlarm_IRQHandler - .word USBWakeUp_IRQHandler - .word TIM8_BRK_TIM12_IRQHandler - .word TIM8_UP_TIM13_IRQHandler - .word TIM8_TRG_COM_TIM14_IRQHandler - .word TIM8_CC_IRQHandler - .word ADC3_IRQHandler - .word FSMC_IRQHandler - .word SDIO_IRQHandler - .word TIM5_IRQHandler - .word SPI3_IRQHandler - .word UART4_IRQHandler - .word UART5_IRQHandler - .word TIM6_IRQHandler - .word TIM7_IRQHandler - .word DMA2_Channel1_IRQHandler - .word DMA2_Channel2_IRQHandler - .word DMA2_Channel3_IRQHandler - .word DMA2_Channel4_5_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x1E0. This is for boot in RAM mode for - STM32F10x XL Density devices. */ -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_IRQHandler - .thumb_set TAMPER_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_2_IRQHandler - .thumb_set ADC1_2_IRQHandler,Default_Handler - - .weak USB_HP_CAN1_TX_IRQHandler - .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler - - .weak USB_LP_CAN1_RX0_IRQHandler - .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTCAlarm_IRQHandler - .thumb_set RTCAlarm_IRQHandler,Default_Handler - - .weak USBWakeUp_IRQHandler - .thumb_set USBWakeUp_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak ADC3_IRQHandler - .thumb_set ADC3_IRQHandler,Default_Handler - - .weak FSMC_IRQHandler - .thumb_set FSMC_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_IRQHandler - .thumb_set TIM6_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Channel1_IRQHandler - .thumb_set DMA2_Channel1_IRQHandler,Default_Handler - - .weak DMA2_Channel2_IRQHandler - .thumb_set DMA2_Channel2_IRQHandler,Default_Handler - - .weak DMA2_Channel3_IRQHandler - .thumb_set DMA2_Channel3_IRQHandler,Default_Handler - - .weak DMA2_Channel4_5_IRQHandler - .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s deleted file mode 100644 index 55a79320b..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s +++ /dev/null @@ -1,507 +0,0 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************* -;* File Name : startup_stm32f10x_cl.s -;* Author : MCD Application Team -;* Version : V3.5.0 -;* Date : 11-March-2011 -;* Description : STM32F10x Connectivity line devices vector table for -;* EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Configure the clock system -;* - Set the initial PC == __iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address. -;* After Reset the Cortex-M3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Tamper - DCD RTC_IRQHandler ; RTC - DCD FLASH_IRQHandler ; Flash - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_2_IRQHandler ; ADC1 and ADC2 - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD TIM1_BRK_IRQHandler ; TIM1 Break - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C1 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_IRQHandler ; TIM6 - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 - DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 - DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 - DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4 - DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:REORDER(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:REORDER(1) -PVD_IRQHandler - B PVD_IRQHandler - - PUBWEAK TAMPER_IRQHandler - SECTION .text:CODE:REORDER(1) -TAMPER_IRQHandler - B TAMPER_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:REORDER(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:REORDER(1) -RCC_IRQHandler - B RCC_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel2_IRQHandler - B DMA1_Channel2_IRQHandler - - PUBWEAK DMA1_Channel3_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel3_IRQHandler - B DMA1_Channel3_IRQHandler - - PUBWEAK DMA1_Channel4_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel4_IRQHandler - B DMA1_Channel4_IRQHandler - - PUBWEAK DMA1_Channel5_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel5_IRQHandler - B DMA1_Channel5_IRQHandler - - PUBWEAK DMA1_Channel6_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel6_IRQHandler - B DMA1_Channel6_IRQHandler - - PUBWEAK DMA1_Channel7_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel7_IRQHandler - B DMA1_Channel7_IRQHandler - - PUBWEAK ADC1_2_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC1_2_IRQHandler - B ADC1_2_IRQHandler - - PUBWEAK CAN1_TX_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN1_TX_IRQHandler - B CAN1_TX_IRQHandler - - PUBWEAK CAN1_RX0_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN1_RX0_IRQHandler - B CAN1_RX0_IRQHandler - - PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN1_RX1_IRQHandler - B CAN1_RX1_IRQHandler - - PUBWEAK CAN1_SCE_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN1_SCE_IRQHandler - B CAN1_SCE_IRQHandler - - PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI9_5_IRQHandler - B EXTI9_5_IRQHandler - - PUBWEAK TIM1_BRK_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_BRK_IRQHandler - B TIM1_BRK_IRQHandler - - PUBWEAK TIM1_UP_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_UP_IRQHandler - B TIM1_UP_IRQHandler - - PUBWEAK TIM1_TRG_COM_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_TRG_COM_IRQHandler - B TIM1_TRG_COM_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - PUBWEAK TIM4_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM4_IRQHandler - B TIM4_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C2_EV_IRQHandler - B I2C2_EV_IRQHandler - - PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C2_ER_IRQHandler - B I2C2_ER_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:REORDER(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK USART3_IRQHandler - SECTION .text:CODE:REORDER(1) -USART3_IRQHandler - B USART3_IRQHandler - - PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI15_10_IRQHandler - B EXTI15_10_IRQHandler - - PUBWEAK RTCAlarm_IRQHandler - SECTION .text:CODE:REORDER(1) -RTCAlarm_IRQHandler - B RTCAlarm_IRQHandler - - PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:REORDER(1) -OTG_FS_WKUP_IRQHandler - B OTG_FS_WKUP_IRQHandler - - PUBWEAK TIM5_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM5_IRQHandler - B TIM5_IRQHandler - - PUBWEAK SPI3_IRQHandler - SECTION .text:CODE:REORDER(1) -SPI3_IRQHandler - B SPI3_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:REORDER(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK UART5_IRQHandler - SECTION .text:CODE:REORDER(1) -UART5_IRQHandler - B UART5_IRQHandler - - PUBWEAK TIM6_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM6_IRQHandler - B TIM6_IRQHandler - - PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM7_IRQHandler - B TIM7_IRQHandler - - PUBWEAK DMA2_Channel1_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA2_Channel1_IRQHandler - B DMA2_Channel1_IRQHandler - - PUBWEAK DMA2_Channel2_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA2_Channel2_IRQHandler - B DMA2_Channel2_IRQHandler - - PUBWEAK DMA2_Channel3_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA2_Channel3_IRQHandler - B DMA2_Channel3_IRQHandler - - PUBWEAK DMA2_Channel4_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA2_Channel4_IRQHandler - B DMA2_Channel4_IRQHandler - - PUBWEAK DMA2_Channel5_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA2_Channel5_IRQHandler - B DMA2_Channel5_IRQHandler - - PUBWEAK ETH_IRQHandler - SECTION .text:CODE:REORDER(1) -ETH_IRQHandler - B ETH_IRQHandler - - PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:REORDER(1) -ETH_WKUP_IRQHandler - B ETH_WKUP_IRQHandler - - PUBWEAK CAN2_TX_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN2_TX_IRQHandler - B CAN2_TX_IRQHandler - - PUBWEAK CAN2_RX0_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN2_RX0_IRQHandler - B CAN2_RX0_IRQHandler - - PUBWEAK CAN2_RX1_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN2_RX1_IRQHandler - B CAN2_RX1_IRQHandler - - PUBWEAK CAN2_SCE_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN2_SCE_IRQHandler - B CAN2_SCE_IRQHandler - - PUBWEAK OTG_FS_IRQHandler - SECTION .text:CODE:REORDER(1) -OTG_FS_IRQHandler - B OTG_FS_IRQHandler - - END -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s deleted file mode 100644 index 37ee7a203..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s +++ /dev/null @@ -1,496 +0,0 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** -;* File Name : startup_stm32f10x_hd.s -;* Author : MCD Application Team -;* Version : V3.5.0 -;* Date : 11-March-2011 -;* Description : STM32F10x High Density Devices vector table for EWARM -;* toolchain. -;* This module performs: -;* - Set the initial SP -;* - Configure the clock system and the external SRAM -;* mounted on STM3210E-EVAL board to be used as data -;* memory (optional, to be enabled by user) -;* - Set the initial PC == __iar_program_start, -;* - Set the vector table entries with the exceptions ISR address, -;* After Reset the Cortex-M3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Tamper - DCD RTC_IRQHandler ; RTC - DCD FLASH_IRQHandler ; Flash - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_2_IRQHandler ; ADC1 & ADC2 - DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX - DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD TIM1_BRK_IRQHandler ; TIM1 Break - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line - DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend - DCD TIM8_BRK_IRQHandler ; TIM8 Break - DCD TIM8_UP_IRQHandler ; TIM8 Update - DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD ADC3_IRQHandler ; ADC3 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_IRQHandler ; TIM6 - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 - DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 - DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 - DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:REORDER(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:REORDER(1) -PVD_IRQHandler - B PVD_IRQHandler - - PUBWEAK TAMPER_IRQHandler - SECTION .text:CODE:REORDER(1) -TAMPER_IRQHandler - B TAMPER_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:REORDER(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:REORDER(1) -RCC_IRQHandler - B RCC_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel2_IRQHandler - B DMA1_Channel2_IRQHandler - - PUBWEAK DMA1_Channel3_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel3_IRQHandler - B DMA1_Channel3_IRQHandler - - PUBWEAK DMA1_Channel4_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel4_IRQHandler - B DMA1_Channel4_IRQHandler - - PUBWEAK DMA1_Channel5_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel5_IRQHandler - B DMA1_Channel5_IRQHandler - - PUBWEAK DMA1_Channel6_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel6_IRQHandler - B DMA1_Channel6_IRQHandler - - PUBWEAK DMA1_Channel7_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel7_IRQHandler - B DMA1_Channel7_IRQHandler - - PUBWEAK ADC1_2_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC1_2_IRQHandler - B ADC1_2_IRQHandler - - PUBWEAK USB_HP_CAN1_TX_IRQHandler - SECTION .text:CODE:REORDER(1) -USB_HP_CAN1_TX_IRQHandler - B USB_HP_CAN1_TX_IRQHandler - - PUBWEAK USB_LP_CAN1_RX0_IRQHandler - SECTION .text:CODE:REORDER(1) -USB_LP_CAN1_RX0_IRQHandler - B USB_LP_CAN1_RX0_IRQHandler - - PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN1_RX1_IRQHandler - B CAN1_RX1_IRQHandler - - PUBWEAK CAN1_SCE_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN1_SCE_IRQHandler - B CAN1_SCE_IRQHandler - - PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI9_5_IRQHandler - B EXTI9_5_IRQHandler - - PUBWEAK TIM1_BRK_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_BRK_IRQHandler - B TIM1_BRK_IRQHandler - - PUBWEAK TIM1_UP_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_UP_IRQHandler - B TIM1_UP_IRQHandler - - PUBWEAK TIM1_TRG_COM_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_TRG_COM_IRQHandler - B TIM1_TRG_COM_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - PUBWEAK TIM4_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM4_IRQHandler - B TIM4_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C2_EV_IRQHandler - B I2C2_EV_IRQHandler - - PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C2_ER_IRQHandler - B I2C2_ER_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:REORDER(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK USART3_IRQHandler - SECTION .text:CODE:REORDER(1) -USART3_IRQHandler - B USART3_IRQHandler - - PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI15_10_IRQHandler - B EXTI15_10_IRQHandler - - PUBWEAK RTCAlarm_IRQHandler - SECTION .text:CODE:REORDER(1) -RTCAlarm_IRQHandler - B RTCAlarm_IRQHandler - - PUBWEAK USBWakeUp_IRQHandler - SECTION .text:CODE:REORDER(1) -USBWakeUp_IRQHandler - B USBWakeUp_IRQHandler - - PUBWEAK TIM8_BRK_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM8_BRK_IRQHandler - B TIM8_BRK_IRQHandler - - PUBWEAK TIM8_UP_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM8_UP_IRQHandler - B TIM8_UP_IRQHandler - - PUBWEAK TIM8_TRG_COM_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM8_TRG_COM_IRQHandler - B TIM8_TRG_COM_IRQHandler - - PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM8_CC_IRQHandler - B TIM8_CC_IRQHandler - - PUBWEAK ADC3_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC3_IRQHandler - B ADC3_IRQHandler - - PUBWEAK FSMC_IRQHandler - SECTION .text:CODE:REORDER(1) -FSMC_IRQHandler - B FSMC_IRQHandler - - PUBWEAK SDIO_IRQHandler - SECTION .text:CODE:REORDER(1) -SDIO_IRQHandler - B SDIO_IRQHandler - - PUBWEAK TIM5_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM5_IRQHandler - B TIM5_IRQHandler - - PUBWEAK SPI3_IRQHandler - SECTION .text:CODE:REORDER(1) -SPI3_IRQHandler - B SPI3_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:REORDER(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK UART5_IRQHandler - SECTION .text:CODE:REORDER(1) -UART5_IRQHandler - B UART5_IRQHandler - - PUBWEAK TIM6_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM6_IRQHandler - B TIM6_IRQHandler - - PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM7_IRQHandler - B TIM7_IRQHandler - - PUBWEAK DMA2_Channel1_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA2_Channel1_IRQHandler - B DMA2_Channel1_IRQHandler - - PUBWEAK DMA2_Channel2_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA2_Channel2_IRQHandler - B DMA2_Channel2_IRQHandler - - PUBWEAK DMA2_Channel3_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA2_Channel3_IRQHandler - B DMA2_Channel3_IRQHandler - - PUBWEAK DMA2_Channel4_5_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA2_Channel4_5_IRQHandler - B DMA2_Channel4_5_IRQHandler - - - END - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd_vl.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd_vl.s deleted file mode 100644 index 33f592f1a..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd_vl.s +++ /dev/null @@ -1,461 +0,0 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** -;* File Name : startup_stm32f10x_hd_vl.s -;* Author : MCD Application Team -;* Version : V3.5.0 -;* Date : 11-March-2011 -;* Description : STM32F10x High Density Value Line Devices vector table -;* for EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Configure the clock system and the external SRAM -;* mounted on STM32100E-EVAL board to be used as data -;* memory (optional, to be enabled by user) -;* - Set the initial PC == __iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address. -;* After Reset the Cortex-M3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Tamper - DCD RTC_IRQHandler ; RTC - DCD FLASH_IRQHandler ; Flash - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_IRQHandler ; ADC1 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 - DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 - DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line - DCD CEC_IRQHandler ; HDMI-CEC - DCD TIM12_IRQHandler ; TIM12 - DCD TIM13_IRQHandler ; TIM13 - DCD TIM14_IRQHandler ; TIM14 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 - DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 - DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 - DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 - DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:REORDER(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:REORDER(1) -PVD_IRQHandler - B PVD_IRQHandler - - PUBWEAK TAMPER_IRQHandler - SECTION .text:CODE:REORDER(1) -TAMPER_IRQHandler - B TAMPER_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:REORDER(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:REORDER(1) -RCC_IRQHandler - B RCC_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel2_IRQHandler - B DMA1_Channel2_IRQHandler - - PUBWEAK DMA1_Channel3_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel3_IRQHandler - B DMA1_Channel3_IRQHandler - - PUBWEAK DMA1_Channel4_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel4_IRQHandler - B DMA1_Channel4_IRQHandler - - PUBWEAK DMA1_Channel5_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel5_IRQHandler - B DMA1_Channel5_IRQHandler - - PUBWEAK DMA1_Channel6_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel6_IRQHandler - B DMA1_Channel6_IRQHandler - - PUBWEAK DMA1_Channel7_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel7_IRQHandler - B DMA1_Channel7_IRQHandler - - PUBWEAK ADC1_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC1_IRQHandler - B ADC1_IRQHandler - - PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI9_5_IRQHandler - B EXTI9_5_IRQHandler - - PUBWEAK TIM1_BRK_TIM15_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_BRK_TIM15_IRQHandler - B TIM1_BRK_TIM15_IRQHandler - - PUBWEAK TIM1_UP_TIM16_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_UP_TIM16_IRQHandler - B TIM1_UP_TIM16_IRQHandler - - PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_TRG_COM_TIM17_IRQHandler - B TIM1_TRG_COM_TIM17_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - PUBWEAK TIM4_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM4_IRQHandler - B TIM4_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C2_EV_IRQHandler - B I2C2_EV_IRQHandler - - PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C2_ER_IRQHandler - B I2C2_ER_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:REORDER(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK USART3_IRQHandler - SECTION .text:CODE:REORDER(1) -USART3_IRQHandler - B USART3_IRQHandler - - PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI15_10_IRQHandler - B EXTI15_10_IRQHandler - - PUBWEAK RTCAlarm_IRQHandler - SECTION .text:CODE:REORDER(1) -RTCAlarm_IRQHandler - B RTCAlarm_IRQHandler - - PUBWEAK CEC_IRQHandler - SECTION .text:CODE:REORDER(1) -CEC_IRQHandler - B CEC_IRQHandler - - PUBWEAK TIM12_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM12_IRQHandler - B TIM12_IRQHandler - - PUBWEAK TIM13_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM13_IRQHandler - B TIM13_IRQHandler - - PUBWEAK TIM14_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM14_IRQHandler - B TIM14_IRQHandler - - PUBWEAK TIM5_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM5_IRQHandler - B TIM5_IRQHandler - - PUBWEAK SPI3_IRQHandler - SECTION .text:CODE:REORDER(1) -SPI3_IRQHandler - B SPI3_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:REORDER(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK UART5_IRQHandler - SECTION .text:CODE:REORDER(1) -UART5_IRQHandler - B UART5_IRQHandler - - PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM6_DAC_IRQHandler - B TIM6_DAC_IRQHandler - - PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM7_IRQHandler - B TIM7_IRQHandler - - PUBWEAK DMA2_Channel1_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA2_Channel1_IRQHandler - B DMA2_Channel1_IRQHandler - - PUBWEAK DMA2_Channel2_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA2_Channel2_IRQHandler - B DMA2_Channel2_IRQHandler - - PUBWEAK DMA2_Channel3_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA2_Channel3_IRQHandler - B DMA2_Channel3_IRQHandler - - PUBWEAK DMA2_Channel4_5_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA2_Channel4_5_IRQHandler - B DMA2_Channel4_5_IRQHandler - - PUBWEAK DMA2_Channel5_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA2_Channel5_IRQHandler - B DMA2_Channel5_IRQHandler - - END -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s deleted file mode 100644 index e2b2b4df0..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s +++ /dev/null @@ -1,366 +0,0 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** -;* File Name : startup_stm32f10x_ld.s -;* Author : MCD Application Team -;* Version : V3.5.0 -;* Date : 11-March-2011 -;* Description : STM32F10x Low Density Devices vector table for EWARM -;* toolchain. -;* This module performs: -;* - Set the initial SP -;* - Configure the clock system -;* - Set the initial PC == __iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address. -;* After Reset the Cortex-M3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Tamper - DCD RTC_IRQHandler ; RTC - DCD FLASH_IRQHandler ; Flash - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_2_IRQHandler ; ADC1 & ADC2 - DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX - DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD TIM1_BRK_IRQHandler ; TIM1 Break - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD 0 ; Reserved - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SPI1_IRQHandler ; SPI1 - DCD 0 ; Reserved - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD 0 ; Reserved - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line - DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:REORDER(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:REORDER(1) -PVD_IRQHandler - B PVD_IRQHandler - - PUBWEAK TAMPER_IRQHandler - SECTION .text:CODE:REORDER(1) -TAMPER_IRQHandler - B TAMPER_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:REORDER(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:REORDER(1) -RCC_IRQHandler - B RCC_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel2_IRQHandler - B DMA1_Channel2_IRQHandler - - PUBWEAK DMA1_Channel3_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel3_IRQHandler - B DMA1_Channel3_IRQHandler - - PUBWEAK DMA1_Channel4_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel4_IRQHandler - B DMA1_Channel4_IRQHandler - - PUBWEAK DMA1_Channel5_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel5_IRQHandler - B DMA1_Channel5_IRQHandler - - PUBWEAK DMA1_Channel6_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel6_IRQHandler - B DMA1_Channel6_IRQHandler - - PUBWEAK DMA1_Channel7_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel7_IRQHandler - B DMA1_Channel7_IRQHandler - - PUBWEAK ADC1_2_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC1_2_IRQHandler - B ADC1_2_IRQHandler - - PUBWEAK USB_HP_CAN1_TX_IRQHandler - SECTION .text:CODE:REORDER(1) -USB_HP_CAN1_TX_IRQHandler - B USB_HP_CAN1_TX_IRQHandler - - PUBWEAK USB_LP_CAN1_RX0_IRQHandler - SECTION .text:CODE:REORDER(1) -USB_LP_CAN1_RX0_IRQHandler - B USB_LP_CAN1_RX0_IRQHandler - - PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN1_RX1_IRQHandler - B CAN1_RX1_IRQHandler - - PUBWEAK CAN1_SCE_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN1_SCE_IRQHandler - B CAN1_SCE_IRQHandler - - PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI9_5_IRQHandler - B EXTI9_5_IRQHandler - - PUBWEAK TIM1_BRK_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_BRK_IRQHandler - B TIM1_BRK_IRQHandler - - PUBWEAK TIM1_UP_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_UP_IRQHandler - B TIM1_UP_IRQHandler - - PUBWEAK TIM1_TRG_COM_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_TRG_COM_IRQHandler - B TIM1_TRG_COM_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI15_10_IRQHandler - B EXTI15_10_IRQHandler - - PUBWEAK RTCAlarm_IRQHandler - SECTION .text:CODE:REORDER(1) -RTCAlarm_IRQHandler - B RTCAlarm_IRQHandler - - PUBWEAK USBWakeUp_IRQHandler - SECTION .text:CODE:REORDER(1) -USBWakeUp_IRQHandler - B USBWakeUp_IRQHandler - - END -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s deleted file mode 100644 index a4a49331c..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s +++ /dev/null @@ -1,369 +0,0 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** -;* File Name : startup_stm32f10x_ld_vl.s -;* Author : MCD Application Team -;* Version : V3.5.0 -;* Date : 11-March-2011 -;* Description : STM32F10x Low Density Value Line Devices vector table -;* for EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Configure the clock system -;* - Set the initial PC == __iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address. -;* After Reset the Cortex-M3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Tamper - DCD RTC_IRQHandler ; RTC - DCD FLASH_IRQHandler ; Flash - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_IRQHandler ; ADC1 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 - DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 - DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD 0 ; Reserved - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SPI1_IRQHandler ; SPI1 - DCD 0 ; Reserved - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD 0 ; Reserved - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line - DCD CEC_IRQHandler ; HDMI-CEC - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun - DCD TIM7_IRQHandler ; TIM7 - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:REORDER(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:REORDER(1) -PVD_IRQHandler - B PVD_IRQHandler - - PUBWEAK TAMPER_IRQHandler - SECTION .text:CODE:REORDER(1) -TAMPER_IRQHandler - B TAMPER_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:REORDER(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:REORDER(1) -RCC_IRQHandler - B RCC_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel2_IRQHandler - B DMA1_Channel2_IRQHandler - - PUBWEAK DMA1_Channel3_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel3_IRQHandler - B DMA1_Channel3_IRQHandler - - PUBWEAK DMA1_Channel4_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel4_IRQHandler - B DMA1_Channel4_IRQHandler - - PUBWEAK DMA1_Channel5_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel5_IRQHandler - B DMA1_Channel5_IRQHandler - - PUBWEAK DMA1_Channel6_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel6_IRQHandler - B DMA1_Channel6_IRQHandler - - PUBWEAK DMA1_Channel7_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel7_IRQHandler - B DMA1_Channel7_IRQHandler - - PUBWEAK ADC1_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC1_IRQHandler - B ADC1_IRQHandler - - PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI9_5_IRQHandler - B EXTI9_5_IRQHandler - - PUBWEAK TIM1_BRK_TIM15_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_BRK_TIM15_IRQHandler - B TIM1_BRK_TIM15_IRQHandler - - PUBWEAK TIM1_UP_TIM16_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_UP_TIM16_IRQHandler - B TIM1_UP_TIM16_IRQHandler - - PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_TRG_COM_TIM17_IRQHandler - B TIM1_TRG_COM_TIM17_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI15_10_IRQHandler - B EXTI15_10_IRQHandler - - PUBWEAK RTCAlarm_IRQHandler - SECTION .text:CODE:REORDER(1) -RTCAlarm_IRQHandler - B RTCAlarm_IRQHandler - - PUBWEAK CEC_IRQHandler - SECTION .text:CODE:REORDER(1) -CEC_IRQHandler - B CEC_IRQHandler - - PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM6_DAC_IRQHandler - B TIM6_DAC_IRQHandler - - PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM7_IRQHandler - B TIM7_IRQHandler - - END -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md.s deleted file mode 100644 index 5863eb90f..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md.s +++ /dev/null @@ -1,391 +0,0 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** -;* File Name : startup_stm32f10x_md.s -;* Author : MCD Application Team -;* Version : V3.5.0 -;* Date : 11-March-2011 -;* Description : STM32F10x Medium Density Devices vector table for -;* EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Configure the clock system -;* - Set the initial PC == __iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address. -;* After Reset the Cortex-M3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Tamper - DCD RTC_IRQHandler ; RTC - DCD FLASH_IRQHandler ; Flash - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_2_IRQHandler ; ADC1 & ADC2 - DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX - DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD TIM1_BRK_IRQHandler ; TIM1 Break - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line - DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:REORDER(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:REORDER(1) -PVD_IRQHandler - B PVD_IRQHandler - - PUBWEAK TAMPER_IRQHandler - SECTION .text:CODE:REORDER(1) -TAMPER_IRQHandler - B TAMPER_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:REORDER(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:REORDER(1) -RCC_IRQHandler - B RCC_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel2_IRQHandler - B DMA1_Channel2_IRQHandler - - PUBWEAK DMA1_Channel3_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel3_IRQHandler - B DMA1_Channel3_IRQHandler - - PUBWEAK DMA1_Channel4_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel4_IRQHandler - B DMA1_Channel4_IRQHandler - - PUBWEAK DMA1_Channel5_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel5_IRQHandler - B DMA1_Channel5_IRQHandler - - PUBWEAK DMA1_Channel6_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel6_IRQHandler - B DMA1_Channel6_IRQHandler - - PUBWEAK DMA1_Channel7_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel7_IRQHandler - B DMA1_Channel7_IRQHandler - - PUBWEAK ADC1_2_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC1_2_IRQHandler - B ADC1_2_IRQHandler - - PUBWEAK USB_HP_CAN1_TX_IRQHandler - SECTION .text:CODE:REORDER(1) -USB_HP_CAN1_TX_IRQHandler - B USB_HP_CAN1_TX_IRQHandler - - PUBWEAK USB_LP_CAN1_RX0_IRQHandler - SECTION .text:CODE:REORDER(1) -USB_LP_CAN1_RX0_IRQHandler - B USB_LP_CAN1_RX0_IRQHandler - - PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN1_RX1_IRQHandler - B CAN1_RX1_IRQHandler - - PUBWEAK CAN1_SCE_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN1_SCE_IRQHandler - B CAN1_SCE_IRQHandler - - PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI9_5_IRQHandler - B EXTI9_5_IRQHandler - - PUBWEAK TIM1_BRK_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_BRK_IRQHandler - B TIM1_BRK_IRQHandler - - PUBWEAK TIM1_UP_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_UP_IRQHandler - B TIM1_UP_IRQHandler - - PUBWEAK TIM1_TRG_COM_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_TRG_COM_IRQHandler - B TIM1_TRG_COM_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - PUBWEAK TIM4_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM4_IRQHandler - B TIM4_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C2_EV_IRQHandler - B I2C2_EV_IRQHandler - - PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C2_ER_IRQHandler - B I2C2_ER_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:REORDER(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK USART3_IRQHandler - SECTION .text:CODE:REORDER(1) -USART3_IRQHandler - B USART3_IRQHandler - - PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI15_10_IRQHandler - B EXTI15_10_IRQHandler - - PUBWEAK RTCAlarm_IRQHandler - SECTION .text:CODE:REORDER(1) -RTCAlarm_IRQHandler - B RTCAlarm_IRQHandler - - PUBWEAK USBWakeUp_IRQHandler - SECTION .text:CODE:REORDER(1) -USBWakeUp_IRQHandler - B USBWakeUp_IRQHandler - - END -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s deleted file mode 100644 index add509da6..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s +++ /dev/null @@ -1,394 +0,0 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** -;* File Name : startup_stm32f10x_md_vl.s -;* Author : MCD Application Team -;* Version : V3.5.0 -;* Date : 11-March-2011 -;* Description : STM32F10x Medium Density Value Line Devices vector table -;* for EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Configure the clock system -;* - Set the initial PC == __iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address. -;* After Reset the Cortex-M3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Tamper - DCD RTC_IRQHandler ; RTC - DCD FLASH_IRQHandler ; Flash - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_IRQHandler ; ADC1 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 - DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 - DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line - DCD CEC_IRQHandler ; HDMI-CEC - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun - DCD TIM7_IRQHandler ; TIM7 - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:REORDER(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:REORDER(1) -PVD_IRQHandler - B PVD_IRQHandler - - PUBWEAK TAMPER_IRQHandler - SECTION .text:CODE:REORDER(1) -TAMPER_IRQHandler - B TAMPER_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:REORDER(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:REORDER(1) -RCC_IRQHandler - B RCC_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel2_IRQHandler - B DMA1_Channel2_IRQHandler - - PUBWEAK DMA1_Channel3_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel3_IRQHandler - B DMA1_Channel3_IRQHandler - - PUBWEAK DMA1_Channel4_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel4_IRQHandler - B DMA1_Channel4_IRQHandler - - PUBWEAK DMA1_Channel5_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel5_IRQHandler - B DMA1_Channel5_IRQHandler - - PUBWEAK DMA1_Channel6_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel6_IRQHandler - B DMA1_Channel6_IRQHandler - - PUBWEAK DMA1_Channel7_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel7_IRQHandler - B DMA1_Channel7_IRQHandler - - PUBWEAK ADC1_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC1_IRQHandler - B ADC1_IRQHandler - - PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI9_5_IRQHandler - B EXTI9_5_IRQHandler - - PUBWEAK TIM1_BRK_TIM15_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_BRK_TIM15_IRQHandler - B TIM1_BRK_TIM15_IRQHandler - - PUBWEAK TIM1_UP_TIM16_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_UP_TIM16_IRQHandler - B TIM1_UP_TIM16_IRQHandler - - PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_TRG_COM_TIM17_IRQHandler - B TIM1_TRG_COM_TIM17_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - PUBWEAK TIM4_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM4_IRQHandler - B TIM4_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C2_EV_IRQHandler - B I2C2_EV_IRQHandler - - PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C2_ER_IRQHandler - B I2C2_ER_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:REORDER(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK USART3_IRQHandler - SECTION .text:CODE:REORDER(1) -USART3_IRQHandler - B USART3_IRQHandler - - PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI15_10_IRQHandler - B EXTI15_10_IRQHandler - - PUBWEAK RTCAlarm_IRQHandler - SECTION .text:CODE:REORDER(1) -RTCAlarm_IRQHandler - B RTCAlarm_IRQHandler - - PUBWEAK CEC_IRQHandler - SECTION .text:CODE:REORDER(1) -CEC_IRQHandler - B CEC_IRQHandler - - PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM6_DAC_IRQHandler - B TIM6_DAC_IRQHandler - - PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM7_IRQHandler - B TIM7_IRQHandler - - END -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_xl.s b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_xl.s deleted file mode 100644 index a7f49c56d..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_xl.s +++ /dev/null @@ -1,496 +0,0 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** -;* File Name : startup_stm32f10x_xl.s -;* Author : MCD Application Team -;* Version : V3.5.0 -;* Date : 11-March-2011 -;* Description : STM32F10x XL-Density Devices vector table for EWARM -;* toolchain. -;* This module performs: -;* - Set the initial SP -;* - Configure the clock system and the external SRAM -;* mounted on STM3210E-EVAL board to be used as data -;* memory (optional, to be enabled by user) -;* - Set the initial PC == __iar_program_start, -;* - Set the vector table entries with the exceptions ISR address, -;* After Reset the Cortex-M3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Tamper - DCD RTC_IRQHandler ; RTC - DCD FLASH_IRQHandler ; Flash - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_2_IRQHandler ; ADC1 & ADC2 - DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX - DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line - DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD ADC3_IRQHandler ; ADC3 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_IRQHandler ; TIM6 - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 - DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 - DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 - DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:REORDER(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:REORDER(1) -PVD_IRQHandler - B PVD_IRQHandler - - PUBWEAK TAMPER_IRQHandler - SECTION .text:CODE:REORDER(1) -TAMPER_IRQHandler - B TAMPER_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:REORDER(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:REORDER(1) -RCC_IRQHandler - B RCC_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel2_IRQHandler - B DMA1_Channel2_IRQHandler - - PUBWEAK DMA1_Channel3_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel3_IRQHandler - B DMA1_Channel3_IRQHandler - - PUBWEAK DMA1_Channel4_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel4_IRQHandler - B DMA1_Channel4_IRQHandler - - PUBWEAK DMA1_Channel5_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel5_IRQHandler - B DMA1_Channel5_IRQHandler - - PUBWEAK DMA1_Channel6_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel6_IRQHandler - B DMA1_Channel6_IRQHandler - - PUBWEAK DMA1_Channel7_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA1_Channel7_IRQHandler - B DMA1_Channel7_IRQHandler - - PUBWEAK ADC1_2_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC1_2_IRQHandler - B ADC1_2_IRQHandler - - PUBWEAK USB_HP_CAN1_TX_IRQHandler - SECTION .text:CODE:REORDER(1) -USB_HP_CAN1_TX_IRQHandler - B USB_HP_CAN1_TX_IRQHandler - - PUBWEAK USB_LP_CAN1_RX0_IRQHandler - SECTION .text:CODE:REORDER(1) -USB_LP_CAN1_RX0_IRQHandler - B USB_LP_CAN1_RX0_IRQHandler - - PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN1_RX1_IRQHandler - B CAN1_RX1_IRQHandler - - PUBWEAK CAN1_SCE_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN1_SCE_IRQHandler - B CAN1_SCE_IRQHandler - - PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI9_5_IRQHandler - B EXTI9_5_IRQHandler - - PUBWEAK TIM1_BRK_TIM9_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_BRK_TIM9_IRQHandler - B TIM1_BRK_TIM9_IRQHandler - - PUBWEAK TIM1_UP_TIM10_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_UP_TIM10_IRQHandler - B TIM1_UP_TIM10_IRQHandler - - PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_TRG_COM_TIM11_IRQHandler - B TIM1_TRG_COM_TIM11_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - PUBWEAK TIM4_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM4_IRQHandler - B TIM4_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C2_EV_IRQHandler - B I2C2_EV_IRQHandler - - PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:REORDER(1) -I2C2_ER_IRQHandler - B I2C2_ER_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:REORDER(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK USART3_IRQHandler - SECTION .text:CODE:REORDER(1) -USART3_IRQHandler - B USART3_IRQHandler - - PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTI15_10_IRQHandler - B EXTI15_10_IRQHandler - - PUBWEAK RTCAlarm_IRQHandler - SECTION .text:CODE:REORDER(1) -RTCAlarm_IRQHandler - B RTCAlarm_IRQHandler - - PUBWEAK USBWakeUp_IRQHandler - SECTION .text:CODE:REORDER(1) -USBWakeUp_IRQHandler - B USBWakeUp_IRQHandler - - PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM8_BRK_TIM12_IRQHandler - B TIM8_BRK_TIM12_IRQHandler - - PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM8_UP_TIM13_IRQHandler - B TIM8_UP_TIM13_IRQHandler - - PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM8_TRG_COM_TIM14_IRQHandler - B TIM8_TRG_COM_TIM14_IRQHandler - - PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM8_CC_IRQHandler - B TIM8_CC_IRQHandler - - PUBWEAK ADC3_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC3_IRQHandler - B ADC3_IRQHandler - - PUBWEAK FSMC_IRQHandler - SECTION .text:CODE:REORDER(1) -FSMC_IRQHandler - B FSMC_IRQHandler - - PUBWEAK SDIO_IRQHandler - SECTION .text:CODE:REORDER(1) -SDIO_IRQHandler - B SDIO_IRQHandler - - PUBWEAK TIM5_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM5_IRQHandler - B TIM5_IRQHandler - - PUBWEAK SPI3_IRQHandler - SECTION .text:CODE:REORDER(1) -SPI3_IRQHandler - B SPI3_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:REORDER(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK UART5_IRQHandler - SECTION .text:CODE:REORDER(1) -UART5_IRQHandler - B UART5_IRQHandler - - PUBWEAK TIM6_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM6_IRQHandler - B TIM6_IRQHandler - - PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM7_IRQHandler - B TIM7_IRQHandler - - PUBWEAK DMA2_Channel1_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA2_Channel1_IRQHandler - B DMA2_Channel1_IRQHandler - - PUBWEAK DMA2_Channel2_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA2_Channel2_IRQHandler - B DMA2_Channel2_IRQHandler - - PUBWEAK DMA2_Channel3_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA2_Channel3_IRQHandler - B DMA2_Channel3_IRQHandler - - PUBWEAK DMA2_Channel4_5_IRQHandler - SECTION .text:CODE:REORDER(1) -DMA2_Channel4_5_IRQHandler - B DMA2_Channel4_5_IRQHandler - - - END - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h deleted file mode 100644 index af0c7c9af..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h +++ /dev/null @@ -1,8336 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F10x Connectivity line, - * High density, High density value line, Medium density, - * Medium density Value line, Low density, Low density Value line - * and XL-density devices. - * - * The file is the unique include file that the application programmer - * is using in the C source code, usually in main.c. This file contains: - * - Configuration section that allows to select: - * - The device used in the target application - * - To use or not the peripheral’s drivers in application code(i.e. - * code will be based on direct access to peripheral’s registers - * rather than drivers API), this option is controlled by - * "#define USE_STDPERIPH_DRIVER" - * - To change few application-specific parameters such as the HSE - * crystal frequency - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f10x - * @{ - */ - -#ifndef __STM32F10x_H -#define __STM32F10x_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup Library_configuration_section - * @{ - */ - -/* Uncomment the line below according to the target STM32 device used in your - application - */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) - /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ - /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ - /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */ - /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ - /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */ - /* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */ - /* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */ - /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */ -#endif -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - - - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers - where the Flash memory density ranges between 16 and 32 Kbytes. - - Low-density value line devices are STM32F100xx microcontrollers where the Flash - memory density ranges between 16 and 32 Kbytes. - - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers - where the Flash memory density ranges between 64 and 128 Kbytes. - - Medium-density value line devices are STM32F100xx microcontrollers where the - Flash memory density ranges between 64 and 128 Kbytes. - - High-density devices are STM32F101xx and STM32F103xx microcontrollers where - the Flash memory density ranges between 256 and 512 Kbytes. - - High-density value line devices are STM32F100xx microcontrollers where the - Flash memory density ranges between 256 and 512 Kbytes. - - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where - the Flash memory density ranges between 512 and 1024 Kbytes. - - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. - */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) - #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)" -#endif - -#if !defined USE_STDPERIPH_DRIVER -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_STDPERIPH_DRIVER*/ -#endif - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ -#if !defined HSE_VALUE - #ifdef STM32F10X_CL - #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ - #else - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ - #endif /* STM32F10X_CL */ -#endif /* HSE_VALUE */ - - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value - */ -#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ - -#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ - -/** - * @brief STM32F10x Standard Peripheral Library version number - */ -#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */ -#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */ -#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\ - |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\ - |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\ - |(__STM32F10X_STDPERIPH_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#ifdef STM32F10X_XL - #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */ -#else - #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ -#endif /* STM32F10X_XL */ -#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @brief STM32F10x Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** STM32 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_IRQn = 2, /*!< Tamper Interrupt */ - RTC_IRQn = 3, /*!< RTC global Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - -#ifdef STM32F10X_LD - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ -#endif /* STM32F10X_LD */ - -#ifdef STM32F10X_LD_VL - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ - TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ - TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ - TIM7_IRQn = 55 /*!< TIM7 Interrupt */ -#endif /* STM32F10X_LD_VL */ - -#ifdef STM32F10X_MD - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ -#endif /* STM32F10X_MD */ - -#ifdef STM32F10X_MD_VL - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ - TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ - TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ - TIM7_IRQn = 55 /*!< TIM7 Interrupt */ -#endif /* STM32F10X_MD_VL */ - -#ifdef STM32F10X_HD - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ - TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ - TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ - TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ -#endif /* STM32F10X_HD */ - -#ifdef STM32F10X_HD_VL - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ - TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ - TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ - TIM12_IRQn = 43, /*!< TIM12 global Interrupt */ - TIM13_IRQn = 44, /*!< TIM13 global Interrupt */ - TIM14_IRQn = 45, /*!< TIM14 global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ - DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is - mapped at position 60 only if the MISC_REMAP bit in - the AFIO_MAPR2 register is set) */ -#endif /* STM32F10X_HD_VL */ - -#ifdef STM32F10X_XL - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ -#endif /* STM32F10X_XL */ - -#ifdef STM32F10X_CL - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ - DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ -#endif /* STM32F10X_CL */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm3.h" -#include "system_stm32f10x.h" -#include - -/** @addtogroup Exported_types - * @{ - */ - -/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef const int32_t sc32; /*!< Read Only */ -typedef const int16_t sc16; /*!< Read Only */ -typedef const int8_t sc8; /*!< Read Only */ - -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef __I int32_t vsc32; /*!< Read Only */ -typedef __I int16_t vsc16; /*!< Read Only */ -typedef __I int8_t vsc8; /*!< Read Only */ - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef const uint32_t uc32; /*!< Read Only */ -typedef const uint16_t uc16; /*!< Read Only */ -typedef const uint8_t uc8; /*!< Read Only */ - -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef __I uint32_t vuc32; /*!< Read Only */ -typedef __I uint16_t vuc16; /*!< Read Only */ -typedef __I uint8_t vuc8; /*!< Read Only */ - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */ -#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT -#define HSE_Value HSE_VALUE -#define HSI_Value HSI_VALUE -/** - * @} - */ - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; - __IO uint32_t CR1; - __IO uint32_t CR2; - __IO uint32_t SMPR1; - __IO uint32_t SMPR2; - __IO uint32_t JOFR1; - __IO uint32_t JOFR2; - __IO uint32_t JOFR3; - __IO uint32_t JOFR4; - __IO uint32_t HTR; - __IO uint32_t LTR; - __IO uint32_t SQR1; - __IO uint32_t SQR2; - __IO uint32_t SQR3; - __IO uint32_t JSQR; - __IO uint32_t JDR1; - __IO uint32_t JDR2; - __IO uint32_t JDR3; - __IO uint32_t JDR4; - __IO uint32_t DR; -} ADC_TypeDef; - -/** - * @brief Backup Registers - */ - -typedef struct -{ - uint32_t RESERVED0; - __IO uint16_t DR1; - uint16_t RESERVED1; - __IO uint16_t DR2; - uint16_t RESERVED2; - __IO uint16_t DR3; - uint16_t RESERVED3; - __IO uint16_t DR4; - uint16_t RESERVED4; - __IO uint16_t DR5; - uint16_t RESERVED5; - __IO uint16_t DR6; - uint16_t RESERVED6; - __IO uint16_t DR7; - uint16_t RESERVED7; - __IO uint16_t DR8; - uint16_t RESERVED8; - __IO uint16_t DR9; - uint16_t RESERVED9; - __IO uint16_t DR10; - uint16_t RESERVED10; - __IO uint16_t RTCCR; - uint16_t RESERVED11; - __IO uint16_t CR; - uint16_t RESERVED12; - __IO uint16_t CSR; - uint16_t RESERVED13[5]; - __IO uint16_t DR11; - uint16_t RESERVED14; - __IO uint16_t DR12; - uint16_t RESERVED15; - __IO uint16_t DR13; - uint16_t RESERVED16; - __IO uint16_t DR14; - uint16_t RESERVED17; - __IO uint16_t DR15; - uint16_t RESERVED18; - __IO uint16_t DR16; - uint16_t RESERVED19; - __IO uint16_t DR17; - uint16_t RESERVED20; - __IO uint16_t DR18; - uint16_t RESERVED21; - __IO uint16_t DR19; - uint16_t RESERVED22; - __IO uint16_t DR20; - uint16_t RESERVED23; - __IO uint16_t DR21; - uint16_t RESERVED24; - __IO uint16_t DR22; - uint16_t RESERVED25; - __IO uint16_t DR23; - uint16_t RESERVED26; - __IO uint16_t DR24; - uint16_t RESERVED27; - __IO uint16_t DR25; - uint16_t RESERVED28; - __IO uint16_t DR26; - uint16_t RESERVED29; - __IO uint16_t DR27; - uint16_t RESERVED30; - __IO uint16_t DR28; - uint16_t RESERVED31; - __IO uint16_t DR29; - uint16_t RESERVED32; - __IO uint16_t DR30; - uint16_t RESERVED33; - __IO uint16_t DR31; - uint16_t RESERVED34; - __IO uint16_t DR32; - uint16_t RESERVED35; - __IO uint16_t DR33; - uint16_t RESERVED36; - __IO uint16_t DR34; - uint16_t RESERVED37; - __IO uint16_t DR35; - uint16_t RESERVED38; - __IO uint16_t DR36; - uint16_t RESERVED39; - __IO uint16_t DR37; - uint16_t RESERVED40; - __IO uint16_t DR38; - uint16_t RESERVED41; - __IO uint16_t DR39; - uint16_t RESERVED42; - __IO uint16_t DR40; - uint16_t RESERVED43; - __IO uint16_t DR41; - uint16_t RESERVED44; - __IO uint16_t DR42; - uint16_t RESERVED45; -} BKP_TypeDef; - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; - __IO uint32_t TDTR; - __IO uint32_t TDLR; - __IO uint32_t TDHR; -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; - __IO uint32_t RDTR; - __IO uint32_t RDLR; - __IO uint32_t RDHR; -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; - __IO uint32_t FR2; -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; - __IO uint32_t MSR; - __IO uint32_t TSR; - __IO uint32_t RF0R; - __IO uint32_t RF1R; - __IO uint32_t IER; - __IO uint32_t ESR; - __IO uint32_t BTR; - uint32_t RESERVED0[88]; - CAN_TxMailBox_TypeDef sTxMailBox[3]; - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; - uint32_t RESERVED1[12]; - __IO uint32_t FMR; - __IO uint32_t FM1R; - uint32_t RESERVED2; - __IO uint32_t FS1R; - uint32_t RESERVED3; - __IO uint32_t FFA1R; - uint32_t RESERVED4; - __IO uint32_t FA1R; - uint32_t RESERVED5[8]; -#ifndef STM32F10X_CL - CAN_FilterRegister_TypeDef sFilterRegister[14]; -#else - CAN_FilterRegister_TypeDef sFilterRegister[28]; -#endif /* STM32F10X_CL */ -} CAN_TypeDef; - -/** - * @brief Consumer Electronics Control (CEC) - */ -typedef struct -{ - __IO uint32_t CFGR; - __IO uint32_t OAR; - __IO uint32_t PRES; - __IO uint32_t ESR; - __IO uint32_t CSR; - __IO uint32_t TXD; - __IO uint32_t RXD; -} CEC_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; - __IO uint8_t IDR; - uint8_t RESERVED0; - uint16_t RESERVED1; - __IO uint32_t CR; -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t SWTRIGR; - __IO uint32_t DHR12R1; - __IO uint32_t DHR12L1; - __IO uint32_t DHR8R1; - __IO uint32_t DHR12R2; - __IO uint32_t DHR12L2; - __IO uint32_t DHR8R2; - __IO uint32_t DHR12RD; - __IO uint32_t DHR12LD; - __IO uint32_t DHR8RD; - __IO uint32_t DOR1; - __IO uint32_t DOR2; -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - __IO uint32_t SR; -#endif -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; - __IO uint32_t CR; -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; - __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; - __IO uint32_t IFCR; -} DMA_TypeDef; - -/** - * @brief Ethernet MAC - */ - -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; /* 8 */ - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; /* 11 */ - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; - __IO uint32_t MACSR; /* 15 */ - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; /* 24 */ - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; /* 65 */ - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; /* 69 */ - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; /* 84 */ - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - uint32_t RESERVED8[567]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - uint32_t RESERVED9[9]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; - __IO uint32_t EMR; - __IO uint32_t RTSR; - __IO uint32_t FTSR; - __IO uint32_t SWIER; - __IO uint32_t PR; -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; - __IO uint32_t KEYR; - __IO uint32_t OPTKEYR; - __IO uint32_t SR; - __IO uint32_t CR; - __IO uint32_t AR; - __IO uint32_t RESERVED; - __IO uint32_t OBR; - __IO uint32_t WRPR; -#ifdef STM32F10X_XL - uint32_t RESERVED1[8]; - __IO uint32_t KEYR2; - uint32_t RESERVED2; - __IO uint32_t SR2; - __IO uint32_t CR2; - __IO uint32_t AR2; -#endif /* STM32F10X_XL */ -} FLASH_TypeDef; - -/** - * @brief Option Bytes Registers - */ - -typedef struct -{ - __IO uint16_t RDP; - __IO uint16_t USER; - __IO uint16_t Data0; - __IO uint16_t Data1; - __IO uint16_t WRP0; - __IO uint16_t WRP1; - __IO uint16_t WRP2; - __IO uint16_t WRP3; -} OB_TypeDef; - -/** - * @brief Flexible Static Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; -} FSMC_Bank1_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; -} FSMC_Bank1E_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; - __IO uint32_t SR2; - __IO uint32_t PMEM2; - __IO uint32_t PATT2; - uint32_t RESERVED0; - __IO uint32_t ECCR2; -} FSMC_Bank2_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR3; - __IO uint32_t SR3; - __IO uint32_t PMEM3; - __IO uint32_t PATT3; - uint32_t RESERVED0; - __IO uint32_t ECCR3; -} FSMC_Bank3_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; - __IO uint32_t SR4; - __IO uint32_t PMEM4; - __IO uint32_t PATT4; - __IO uint32_t PIO4; -} FSMC_Bank4_TypeDef; - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t CRL; - __IO uint32_t CRH; - __IO uint32_t IDR; - __IO uint32_t ODR; - __IO uint32_t BSRR; - __IO uint32_t BRR; - __IO uint32_t LCKR; -} GPIO_TypeDef; - -/** - * @brief Alternate Function I/O - */ - -typedef struct -{ - __IO uint32_t EVCR; - __IO uint32_t MAPR; - __IO uint32_t EXTICR[4]; - uint32_t RESERVED0; - __IO uint32_t MAPR2; -} AFIO_TypeDef; -/** - * @brief Inter Integrated Circuit Interface - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t OAR1; - uint16_t RESERVED2; - __IO uint16_t OAR2; - uint16_t RESERVED3; - __IO uint16_t DR; - uint16_t RESERVED4; - __IO uint16_t SR1; - uint16_t RESERVED5; - __IO uint16_t SR2; - uint16_t RESERVED6; - __IO uint16_t CCR; - uint16_t RESERVED7; - __IO uint16_t TRISE; - uint16_t RESERVED8; -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; - __IO uint32_t PR; - __IO uint32_t RLR; - __IO uint32_t SR; -} IWDG_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CSR; -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CFGR; - __IO uint32_t CIR; - __IO uint32_t APB2RSTR; - __IO uint32_t APB1RSTR; - __IO uint32_t AHBENR; - __IO uint32_t APB2ENR; - __IO uint32_t APB1ENR; - __IO uint32_t BDCR; - __IO uint32_t CSR; - -#ifdef STM32F10X_CL - __IO uint32_t AHBRSTR; - __IO uint32_t CFGR2; -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - uint32_t RESERVED0; - __IO uint32_t CFGR2; -#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint16_t CRH; - uint16_t RESERVED0; - __IO uint16_t CRL; - uint16_t RESERVED1; - __IO uint16_t PRLH; - uint16_t RESERVED2; - __IO uint16_t PRLL; - uint16_t RESERVED3; - __IO uint16_t DIVH; - uint16_t RESERVED4; - __IO uint16_t DIVL; - uint16_t RESERVED5; - __IO uint16_t CNTH; - uint16_t RESERVED6; - __IO uint16_t CNTL; - uint16_t RESERVED7; - __IO uint16_t ALRH; - uint16_t RESERVED8; - __IO uint16_t ALRL; - uint16_t RESERVED9; -} RTC_TypeDef; - -/** - * @brief SD host Interface - */ - -typedef struct -{ - __IO uint32_t POWER; - __IO uint32_t CLKCR; - __IO uint32_t ARG; - __IO uint32_t CMD; - __I uint32_t RESPCMD; - __I uint32_t RESP1; - __I uint32_t RESP2; - __I uint32_t RESP3; - __I uint32_t RESP4; - __IO uint32_t DTIMER; - __IO uint32_t DLEN; - __IO uint32_t DCTRL; - __I uint32_t DCOUNT; - __I uint32_t STA; - __IO uint32_t ICR; - __IO uint32_t MASK; - uint32_t RESERVED0[2]; - __I uint32_t FIFOCNT; - uint32_t RESERVED1[13]; - __IO uint32_t FIFO; -} SDIO_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t SR; - uint16_t RESERVED2; - __IO uint16_t DR; - uint16_t RESERVED3; - __IO uint16_t CRCPR; - uint16_t RESERVED4; - __IO uint16_t RXCRCR; - uint16_t RESERVED5; - __IO uint16_t TXCRCR; - uint16_t RESERVED6; - __IO uint16_t I2SCFGR; - uint16_t RESERVED7; - __IO uint16_t I2SPR; - uint16_t RESERVED8; -} SPI_TypeDef; - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t SMCR; - uint16_t RESERVED2; - __IO uint16_t DIER; - uint16_t RESERVED3; - __IO uint16_t SR; - uint16_t RESERVED4; - __IO uint16_t EGR; - uint16_t RESERVED5; - __IO uint16_t CCMR1; - uint16_t RESERVED6; - __IO uint16_t CCMR2; - uint16_t RESERVED7; - __IO uint16_t CCER; - uint16_t RESERVED8; - __IO uint16_t CNT; - uint16_t RESERVED9; - __IO uint16_t PSC; - uint16_t RESERVED10; - __IO uint16_t ARR; - uint16_t RESERVED11; - __IO uint16_t RCR; - uint16_t RESERVED12; - __IO uint16_t CCR1; - uint16_t RESERVED13; - __IO uint16_t CCR2; - uint16_t RESERVED14; - __IO uint16_t CCR3; - uint16_t RESERVED15; - __IO uint16_t CCR4; - uint16_t RESERVED16; - __IO uint16_t BDTR; - uint16_t RESERVED17; - __IO uint16_t DCR; - uint16_t RESERVED18; - __IO uint16_t DMAR; - uint16_t RESERVED19; -} TIM_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint16_t SR; - uint16_t RESERVED0; - __IO uint16_t DR; - uint16_t RESERVED1; - __IO uint16_t BRR; - uint16_t RESERVED2; - __IO uint16_t CR1; - uint16_t RESERVED3; - __IO uint16_t CR2; - uint16_t RESERVED4; - __IO uint16_t CR3; - uint16_t RESERVED5; - __IO uint16_t GTPR; - uint16_t RESERVED6; -} USART_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CFR; - __IO uint32_t SR; -} WWDG_TypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ - - -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ - -#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ - -#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) - -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) -#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) -#define CEC_BASE (APB1PERIPH_BASE + 0x7800) - -#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) -#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) -#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) -#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) -#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) -#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) -#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) -#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800) -#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) -#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) -#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) -#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) -#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) -#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) - -#define SDIO_BASE (PERIPH_BASE + 0x18000) - -#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) -#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) -#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) -#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) -#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) -#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) -#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) -#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) -#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) -#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) -#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) -#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) -#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) -#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) -#define RCC_BASE (AHBPERIPH_BASE + 0x1000) -#define CRC_BASE (AHBPERIPH_BASE + 0x3000) - -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ -#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ - -#define ETH_BASE (AHBPERIPH_BASE + 0x8000) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100) -#define ETH_PTP_BASE (ETH_BASE + 0x0700) -#define ETH_DMA_BASE (ETH_BASE + 0x1000) - -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ -#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */ -#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */ -#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ - -#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ - -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define TIM12 ((TIM_TypeDef *) TIM12_BASE) -#define TIM13 ((TIM_TypeDef *) TIM13_BASE) -#define TIM14 ((TIM_TypeDef *) TIM14_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#define BKP ((BKP_TypeDef *) BKP_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define CEC ((CEC_TypeDef *) CEC_BASE) -#define AFIO ((AFIO_TypeDef *) AFIO_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define TIM15 ((TIM_TypeDef *) TIM15_BASE) -#define TIM16 ((TIM_TypeDef *) TIM16_BASE) -#define TIM17 ((TIM_TypeDef *) TIM17_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) -#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) -#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) -#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) -#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) -#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define OB ((OB_TypeDef *) OB_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) -#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) -#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) -#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) -#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) -#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* CRC calculation unit */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ - - -/******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ - - -/******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ - -/******************************************************************************/ -/* */ -/* Power Control */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for PWR_CR register ********************/ -#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ -#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ -#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ -#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ -#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ - -#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ -#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ -#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ - -/*!< PVD level configuration */ -#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ -#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ -#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ -#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ -#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ -#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ -#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ -#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ - -#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ - - -/******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ -#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ -#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ -#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ - -/******************************************************************************/ -/* */ -/* Backup registers */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for BKP_DR1 register ********************/ -#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR2 register ********************/ -#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR3 register ********************/ -#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR4 register ********************/ -#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR5 register ********************/ -#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR6 register ********************/ -#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR7 register ********************/ -#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR8 register ********************/ -#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR9 register ********************/ -#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR10 register *******************/ -#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR11 register *******************/ -#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR12 register *******************/ -#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR13 register *******************/ -#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR14 register *******************/ -#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR15 register *******************/ -#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR16 register *******************/ -#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR17 register *******************/ -#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/****************** Bit definition for BKP_DR18 register ********************/ -#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR19 register *******************/ -#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR20 register *******************/ -#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR21 register *******************/ -#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR22 register *******************/ -#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR23 register *******************/ -#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR24 register *******************/ -#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR25 register *******************/ -#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR26 register *******************/ -#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR27 register *******************/ -#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR28 register *******************/ -#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR29 register *******************/ -#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR30 register *******************/ -#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR31 register *******************/ -#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR32 register *******************/ -#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR33 register *******************/ -#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR34 register *******************/ -#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR35 register *******************/ -#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR36 register *******************/ -#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR37 register *******************/ -#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR38 register *******************/ -#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR39 register *******************/ -#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR40 register *******************/ -#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR41 register *******************/ -#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR42 register *******************/ -#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/****************** Bit definition for BKP_RTCCR register *******************/ -#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ -#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ -#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ -#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ - -/******************** Bit definition for BKP_CR register ********************/ -#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ -#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ - -/******************* Bit definition for BKP_CSR register ********************/ -#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ -#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ -#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ -#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ -#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ - -/******************************************************************************/ -/* */ -/* Reset and Clock Control */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for RCC_CR register ********************/ -#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ -#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ -#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ -#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ -#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ -#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ -#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ -#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ -#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ -#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ - -#ifdef STM32F10X_CL - #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */ - #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ - #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */ - #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ -#endif /* STM32F10X_CL */ - -/******************* Bit definition for RCC_CFGR register *******************/ -/*!< SW configuration */ -#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ -#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ -#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ -#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ - -/*!< SWS configuration */ -#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ -#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ - -/*!< HPRE configuration */ -#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ -#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ -#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ -#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ -#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ -#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ -#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ -#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ -#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ - -/*!< PPRE1 configuration */ -#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - -#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ - -/*!< PPRE2 configuration */ -#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ -#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ -#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ - -#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ - -/*!< ADCPPRE configuration */ -#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ -#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ -#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ -#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ -#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ - -#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ - -#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ - -/*!< PLLMUL configuration */ -#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ -#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ - -#ifdef STM32F10X_CL - #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ - #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ - - #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ - #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ - - #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */ - #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */ - #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */ - #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */ - #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */ - #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */ - #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */ - - #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */ - -/*!< MCO configuration */ - #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ - #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ - #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - - #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ - #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ - #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ - #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ - #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ - #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/ - #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ - #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ - #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */ -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ - #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ - - #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ - #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ - - #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ - #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ - #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ - #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ - #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ - #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ - #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ - #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ - #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ - #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ - #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ - #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ - #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ - #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ - #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ - -/*!< MCO configuration */ - #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ - #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ - #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - - #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ - #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ - #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ - #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ - #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ -#else - #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ - #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ - - #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ - #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ - - #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ - #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ - #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ - #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ - #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ - #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ - #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ - #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ - #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ - #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ - #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ - #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ - #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ - #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ - #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ - #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ - -/*!< MCO configuration */ - #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ - #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ - #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - - #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ - #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ - #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ - #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ - #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ -#endif /* STM32F10X_CL */ - -/*!<****************** Bit definition for RCC_CIR register ********************/ -#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ -#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ -#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ -#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ -#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ -#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ -#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ -#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ -#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ -#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ -#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ -#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ -#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ -#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ -#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ -#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ -#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ - -#ifdef STM32F10X_CL - #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ - #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ - #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ - #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ - #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ - #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ -#endif /* STM32F10X_CL */ - -/***************** Bit definition for RCC_APB2RSTR register *****************/ -#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ -#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ -#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ -#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ -#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ -#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) -#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ -#endif - -#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ -#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ -#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */ -#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */ -#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */ -#endif - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_XL) - #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ - #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ - #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ - #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */ -#endif - -#if defined (STM32F10X_HD_VL) - #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ - #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ -#endif - -#ifdef STM32F10X_XL - #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */ - #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */ - #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */ -#endif /* STM32F10X_XL */ - -/***************** Bit definition for RCC_APB1RSTR register *****************/ -#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ -#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ -#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ -#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ -#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) -#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ -#endif - -#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ -#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ - #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ - #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ - #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL) - #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ -#endif - -#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL) - #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ - #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ - #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ - #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ - #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ - #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ - #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ -#endif - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ - #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ - #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ - #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ -#endif - -#if defined (STM32F10X_HD_VL) - #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ - #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ - #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ - #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ - #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ - #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ - #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ -#endif - -#ifdef STM32F10X_CL - #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */ -#endif /* STM32F10X_CL */ - -#ifdef STM32F10X_XL - #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ - #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ - #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ -#endif /* STM32F10X_XL */ - -/****************** Bit definition for RCC_AHBENR register ******************/ -#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */ -#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ -#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ -#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL) - #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */ -#endif - -#if defined (STM32F10X_HD) || defined (STM32F10X_XL) - #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ - #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */ -#endif - -#if defined (STM32F10X_HD_VL) - #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ -#endif - -#ifdef STM32F10X_CL - #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */ - #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */ - #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */ - #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */ -#endif /* STM32F10X_CL */ - -/****************** Bit definition for RCC_APB2ENR register *****************/ -#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ -#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ -#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ -#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ -#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ -#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) -#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ -#endif - -#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ -#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ -#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */ -#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */ -#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */ -#endif - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_XL) - #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ - #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ - #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ - #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */ -#endif - -#if defined (STM32F10X_HD_VL) - #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ - #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ -#endif - -#ifdef STM32F10X_XL - #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */ - #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */ - #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */ -#endif - -/***************** Bit definition for RCC_APB1ENR register ******************/ -#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ -#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ -#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ -#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ -#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) -#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ -#endif - -#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ -#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ - #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ - #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ - #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) - #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ -#endif - -#if defined (STM32F10X_HD) || defined (STM32F10X_CL) - #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ - #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ - #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ - #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ - #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ - #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ - #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ -#endif - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ - #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ - #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ - #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ -#endif - -#ifdef STM32F10X_HD_VL - #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ - #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ - #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ - #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ - #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ - #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ - #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ -#endif /* STM32F10X_HD_VL */ - -#ifdef STM32F10X_CL - #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */ -#endif /* STM32F10X_CL */ - -#ifdef STM32F10X_XL - #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ - #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ - #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ -#endif /* STM32F10X_XL */ - -/******************* Bit definition for RCC_BDCR register *******************/ -#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ -#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ -#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ - -#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ -#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -/*!< RTC congiguration */ -#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ -#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ - -#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ -#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ - -/******************* Bit definition for RCC_CSR register ********************/ -#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ -#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ -#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ -#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ -#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ -#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ -#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ -#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ -#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ - -#ifdef STM32F10X_CL -/******************* Bit definition for RCC_AHBRSTR register ****************/ - #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */ - #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */ - -/******************* Bit definition for RCC_CFGR2 register ******************/ -/*!< PREDIV1 configuration */ - #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ - #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ - #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - - #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ - #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ - #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ - #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ - #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ - #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ - #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ - #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ - #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ - #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ - #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ - #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ - #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ - #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ - #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ - #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ - -/*!< PREDIV2 configuration */ - #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ - #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ - #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ - #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - - #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */ - #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */ - #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */ - #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */ - #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */ - #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */ - #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */ - #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */ - #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */ - #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */ - #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */ - #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */ - #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */ - #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */ - #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */ - #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */ - -/*!< PLL2MUL configuration */ - #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */ - #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ - #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - - #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */ - #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */ - #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */ - #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */ - #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */ - #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */ - #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */ - #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */ - #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */ - -/*!< PLL3MUL configuration */ - #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */ - #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ - #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */ - - #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */ - #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */ - #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */ - #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */ - #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */ - #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */ - #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */ - #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */ - #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */ - - #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */ - #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */ - #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */ - #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */ - #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/******************* Bit definition for RCC_CFGR2 register ******************/ -/*!< PREDIV1 configuration */ - #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ - #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ - #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - - #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ - #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ - #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ - #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ - #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ - #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ - #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ - #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ - #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ - #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ - #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ - #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ - #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ - #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ - #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ - #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ -#endif - -/******************************************************************************/ -/* */ -/* General Purpose and Alternate Function I/O */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for GPIO_CRL register *******************/ -#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ - -#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ -#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ -#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ -#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ -#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ -#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ -#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ -#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ -#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ - -#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ -#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ -#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ -#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ -#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ -#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ -#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ -#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ -#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ -#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ - -/******************* Bit definition for GPIO_CRH register *******************/ -#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ - -#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ -#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ -#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ -#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ -#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ -#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ -#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ -#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ -#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ - -#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ -#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ -#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ -#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ -#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ -#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ -#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ -#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ -#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ -#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ - -/*!<****************** Bit definition for GPIO_IDR register *******************/ -#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ -#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ -#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ -#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ -#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ -#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ -#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ -#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ -#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ -#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ -#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ -#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ -#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ -#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ -#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ -#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ - -/******************* Bit definition for GPIO_ODR register *******************/ -#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ -#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ -#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ -#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ -#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ -#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ -#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ -#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ -#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ -#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ -#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ -#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ -#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ -#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ -#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ -#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ - -/****************** Bit definition for GPIO_BSRR register *******************/ -#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ -#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ -#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ -#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ -#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ -#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ -#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ -#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ -#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ -#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ -#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ -#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ -#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ -#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ -#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ -#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ - -#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ -#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ -#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ -#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ -#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ -#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ -#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ -#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ -#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ -#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ -#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ -#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ -#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ -#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ -#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ -#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ - -/******************* Bit definition for GPIO_BRR register *******************/ -#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ -#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ -#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ -#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ -#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ -#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ -#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ -#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ -#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ -#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ -#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ -#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ -#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ -#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ -#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ -#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ - -/****************** Bit definition for GPIO_LCKR register *******************/ -#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ -#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ -#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ -#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ -#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ -#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ -#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ -#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ -#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ -#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ -#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ -#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ -#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ -#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ -#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ -#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ -#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ - -/*----------------------------------------------------------------------------*/ - -/****************** Bit definition for AFIO_EVCR register *******************/ -#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ -#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ -#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ - -/*!< PIN configuration */ -#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ -#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ -#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ -#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ -#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ -#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ -#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ -#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ -#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ -#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ -#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ -#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ -#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ -#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ -#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ -#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ - -#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ -#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ -#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ -#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ - -/*!< PORT configuration */ -#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ -#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ -#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ -#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ -#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ - -#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */ - -/****************** Bit definition for AFIO_MAPR register *******************/ -#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ -#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ -#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ -#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ - -#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ -#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -/* USART3_REMAP configuration */ -#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ - -#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ -#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -/*!< TIM1_REMAP configuration */ -#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ -#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ -#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ - -#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ -#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -/*!< TIM2_REMAP configuration */ -#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ -#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ - -#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ -#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -/*!< TIM3_REMAP configuration */ -#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ - -#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ - -#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ -#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ - -/*!< CAN_REMAP configuration */ -#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ -#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ -#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ - -#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ -#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ -#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ -#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ -#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ - -/*!< SWJ_CFG configuration */ -#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ -#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ -#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ -#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ -#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ - -#ifdef STM32F10X_CL -/*!< ETH_REMAP configuration */ - #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ - -/*!< CAN2_REMAP configuration */ - #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ - -/*!< MII_RMII_SEL configuration */ - #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ - -/*!< SPI3_REMAP configuration */ - #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */ - -/*!< TIM2ITR1_IREMAP configuration */ - #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ - -/*!< PTP_PPS_REMAP configuration */ - #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ -#endif - -/***************** Bit definition for AFIO_EXTICR1 register *****************/ -#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ -#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ -#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ -#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ - -/*!< EXTI0 configuration */ -#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ -#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ -#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ -#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ -#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ -#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ -#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ - -/*!< EXTI1 configuration */ -#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ -#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ -#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ -#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ -#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ -#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ -#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ - -/*!< EXTI2 configuration */ -#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ -#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ -#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ -#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ -#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ -#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ -#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ - -/*!< EXTI3 configuration */ -#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ -#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ -#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ -#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ -#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ -#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ -#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ - -/***************** Bit definition for AFIO_EXTICR2 register *****************/ -#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ -#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ -#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ -#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ - -/*!< EXTI4 configuration */ -#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ -#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ -#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ -#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ -#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ -#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ -#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ - -/* EXTI5 configuration */ -#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ -#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ -#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ -#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ -#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ -#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ -#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ - -/*!< EXTI6 configuration */ -#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ -#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ -#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ -#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ -#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ -#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ -#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ - -/*!< EXTI7 configuration */ -#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ -#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ -#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ -#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ -#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ -#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ -#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ - -/***************** Bit definition for AFIO_EXTICR3 register *****************/ -#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ -#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ -#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ -#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ - -/*!< EXTI8 configuration */ -#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ -#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ -#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ -#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ -#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ -#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ -#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ - -/*!< EXTI9 configuration */ -#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ -#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ -#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ -#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ -#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ -#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ -#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ - -/*!< EXTI10 configuration */ -#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ -#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ -#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ -#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ -#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ -#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ -#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ - -/*!< EXTI11 configuration */ -#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ -#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ -#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ -#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ -#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ -#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ -#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ - -/***************** Bit definition for AFIO_EXTICR4 register *****************/ -#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ -#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ -#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ -#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ - -/* EXTI12 configuration */ -#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ -#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ -#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ -#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ -#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ -#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ -#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ - -/* EXTI13 configuration */ -#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ -#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ -#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ -#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ -#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ -#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ -#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ - -/*!< EXTI14 configuration */ -#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ -#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ -#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ -#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ -#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ -#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ -#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ - -/*!< EXTI15 configuration */ -#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ -#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ -#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ -#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ -#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ -#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ -#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/****************** Bit definition for AFIO_MAPR2 register ******************/ -#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */ -#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */ -#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */ -#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */ -#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */ -#endif - -#ifdef STM32F10X_HD_VL -#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ -#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ -#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ -#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */ -#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */ -#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */ -#endif - -#ifdef STM32F10X_XL -/****************** Bit definition for AFIO_MAPR2 register ******************/ -#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */ -#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */ -#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */ -#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ -#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ -#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ -#endif - -/******************************************************************************/ -/* */ -/* SystemTick */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ -#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ -#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ -#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ -#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */ -#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ -#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ -#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ - -/******************************************************************************/ -/* */ -/* External Interrupt/Event Controller */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for EXTI_IMR register *******************/ -#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ -#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ -#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ -#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ -#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ -#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ -#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ -#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ -#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ -#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ -#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ -#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ -#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ -#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ -#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ -#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ -#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ -#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ -#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ - -/******************* Bit definition for EXTI_EMR register *******************/ -#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ -#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ -#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ -#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ -#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ -#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ -#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ -#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ -#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ -#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ -#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ -#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ -#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ -#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ -#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ -#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ -#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ -#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ -#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ -#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ - -/****************** Bit definition for EXTI_RTSR register *******************/ -#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ -#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ -#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ -#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ -#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ -#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ -#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ -#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ -#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ -#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ -#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ -#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ -#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ -#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ -#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ -#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ -#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ -#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ -#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ - -/****************** Bit definition for EXTI_FTSR register *******************/ -#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ -#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ -#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ -#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ -#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ -#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ -#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ -#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ -#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ -#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ -#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ -#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ -#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ -#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ -#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ -#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ -#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ -#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ -#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ - -/****************** Bit definition for EXTI_SWIER register ******************/ -#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ -#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ -#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ -#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ -#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ -#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ -#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ -#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ -#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ -#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ -#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ -#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ -#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ -#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ -#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ -#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ -#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ -#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ -#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ - -/******************* Bit definition for EXTI_PR register ********************/ -#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ -#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ -#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ -#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ -#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ -#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ -#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ -#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ -#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ -#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ -#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ -#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ -#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ -#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ -#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ -#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ -#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ -#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ -#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ -#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ - -/******************************************************************************/ -/* */ -/* DMA Controller */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for DMA_ISR register ********************/ -#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ -#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ -#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ -#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ -#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ -#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ -#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ -#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ -#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ -#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ -#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ -#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ -#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ -#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ -#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ -#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ -#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ -#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ -#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ -#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ -#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ -#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ -#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ -#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ -#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ -#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ -#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ -#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ - -/******************* Bit definition for DMA_IFCR register *******************/ -#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ -#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ -#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ -#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ -#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ -#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ -#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ -#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ -#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ -#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ -#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ -#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ -#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ -#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ -#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ -#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ -#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ -#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ -#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ -#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ -#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ -#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ -#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ -#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ -#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ -#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ -#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ -#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ - -/******************* Bit definition for DMA_CCR1 register *******************/ -#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ -#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ -#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/******************* Bit definition for DMA_CCR2 register *******************/ -#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/******************* Bit definition for DMA_CCR3 register *******************/ -#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/*!<****************** Bit definition for DMA_CCR4 register *******************/ -#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/****************** Bit definition for DMA_CCR5 register *******************/ -#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ - -/******************* Bit definition for DMA_CCR6 register *******************/ -#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/******************* Bit definition for DMA_CCR7 register *******************/ -#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ - -/****************** Bit definition for DMA_CNDTR1 register ******************/ -#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR2 register ******************/ -#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR3 register ******************/ -#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR4 register ******************/ -#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR5 register ******************/ -#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR6 register ******************/ -#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CNDTR7 register ******************/ -#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CPAR1 register *******************/ -#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CPAR2 register *******************/ -#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CPAR3 register *******************/ -#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - - -/****************** Bit definition for DMA_CPAR4 register *******************/ -#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CPAR5 register *******************/ -#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CPAR6 register *******************/ -#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - - -/****************** Bit definition for DMA_CPAR7 register *******************/ -#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CMAR1 register *******************/ -#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/****************** Bit definition for DMA_CMAR2 register *******************/ -#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/****************** Bit definition for DMA_CMAR3 register *******************/ -#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - - -/****************** Bit definition for DMA_CMAR4 register *******************/ -#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/****************** Bit definition for DMA_CMAR5 register *******************/ -#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/****************** Bit definition for DMA_CMAR6 register *******************/ -#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/****************** Bit definition for DMA_CMAR7 register *******************/ -#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint8_t)0x01) /*!< Analog watchdog flag */ -#define ADC_SR_EOC ((uint8_t)0x02) /*!< End of conversion */ -#define ADC_SR_JEOC ((uint8_t)0x04) /*!< Injected channel end of conversion */ -#define ADC_SR_JSTRT ((uint8_t)0x08) /*!< Injected channel Start flag */ -#define ADC_SR_STRT ((uint8_t)0x10) /*!< Regular channel Start flag */ - -/******************* Bit definition for ADC_CR1 register ********************/ -#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ -#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ -#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ -#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ -#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ -#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ -#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ -#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ - -#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ -#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ - -#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!< DUALMOD[3:0] bits (Dual mode selection) */ -#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ -#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ - - -/******************* Bit definition for ADC_CR2 register ********************/ -#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ -#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ -#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */ -#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */ -#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ -#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ - -#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */ -#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */ - -#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ -#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */ -#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */ -#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */ - -#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */ -#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */ -#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */ -#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ - -/****************** Bit definition for ADC_SMPR1 register *******************/ -#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ -#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ -#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ -#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ -#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ -#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */ -#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ -#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ -#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -/****************** Bit definition for ADC_SMPR2 register *******************/ -#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ -#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ -#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ -#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ -#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ -#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ -#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ -#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ -#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ -#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ - -/****************** Bit definition for ADC_JOFR1 register *******************/ -#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */ - -/****************** Bit definition for ADC_JOFR2 register *******************/ -#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */ - -/****************** Bit definition for ADC_JOFR3 register *******************/ -#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */ - -/****************** Bit definition for ADC_JOFR4 register *******************/ -#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */ - -/******************* Bit definition for ADC_HTR register ********************/ -#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */ - -/******************* Bit definition for ADC_LTR register ********************/ -#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */ - -/******************* Bit definition for ADC_SQR1 register *******************/ -#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ -#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ -#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ -#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ -#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ -#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -/******************* Bit definition for ADC_SQR2 register *******************/ -#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ -#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ -#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ -#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ -#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ -#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ -#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ - -/******************* Bit definition for ADC_SQR3 register *******************/ -#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ -#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ -#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ -#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ -#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ -#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ -#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ - -/******************* Bit definition for ADC_JSQR register *******************/ -#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ -#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ -#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ -#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ -#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ -#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -/******************* Bit definition for ADC_JDR1 register *******************/ -#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_JDR2 register *******************/ -#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_JDR3 register *******************/ -#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_JDR4 register *******************/ -#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ - -/******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ -#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!< ADC2 data */ - -/******************************************************************************/ -/* */ -/* Digital to Analog Converter */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */ -#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */ -#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */ - -#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ -#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ -#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */ -#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */ -#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */ -#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */ - -#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ -#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */ -#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */ -#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */ - -#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ -#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */ - -/***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */ -#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */ - -/***************** Bit definition for DAC_DHR12R1 register ******************/ -#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12L1 register ******************/ -#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8R1 register ******************/ -#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12R2 register ******************/ -#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12L2 register ******************/ -#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8R2 register ******************/ -#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12RD register ******************/ -#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ -#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12LD register ******************/ -#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ -#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8RD register ******************/ -#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */ -#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */ - -/******************* Bit definition for DAC_DOR1 register *******************/ -#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */ - -/******************* Bit definition for DAC_DOR2 register *******************/ -#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */ - -/******************** Bit definition for DAC_SR register ********************/ -#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */ -#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */ - -/******************************************************************************/ -/* */ -/* CEC */ -/* */ -/******************************************************************************/ -/******************** Bit definition for CEC_CFGR register ******************/ -#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ -#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */ -#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */ -#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */ - -/******************** Bit definition for CEC_OAR register ******************/ -#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */ -#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */ - -/******************** Bit definition for CEC_PRES register ******************/ -#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */ - -/******************** Bit definition for CEC_ESR register ******************/ -#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */ -#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */ -#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */ -#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */ -#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */ -#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */ -#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finished Error */ - -/******************** Bit definition for CEC_CSR register ******************/ -#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */ -#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */ -#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */ -#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */ -#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */ -#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */ -#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */ -#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */ - -/******************** Bit definition for CEC_TXD register ******************/ -#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */ - -/******************** Bit definition for CEC_RXD register ******************/ -#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */ - -/******************************************************************************/ -/* */ -/* TIM */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for TIM_CR1 register ********************/ -#define TIM_CR1_CEN ((uint16_t)0x0001) /*!< Counter enable */ -#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!< Update disable */ -#define TIM_CR1_URS ((uint16_t)0x0004) /*!< Update request source */ -#define TIM_CR1_OPM ((uint16_t)0x0008) /*!< One pulse mode */ -#define TIM_CR1_DIR ((uint16_t)0x0010) /*!< Direction */ - -#define TIM_CR1_CMS ((uint16_t)0x0060) /*!< CMS[1:0] bits (Center-aligned mode selection) */ -#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!< Bit 0 */ -#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!< Bit 1 */ - -#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!< Auto-reload preload enable */ - -#define TIM_CR1_CKD ((uint16_t)0x0300) /*!< CKD[1:0] bits (clock division) */ -#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -/******************* Bit definition for TIM_CR2 register ********************/ -#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!< Capture/Compare Preloaded Control */ -#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!< Capture/Compare Control Update Selection */ -#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!< Capture/Compare DMA Selection */ - -#define TIM_CR2_MMS ((uint16_t)0x0070) /*!< MMS[2:0] bits (Master Mode Selection) */ -#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!< Bit 2 */ - -#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!< TI1 Selection */ -#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!< Output Idle state 1 (OC1 output) */ -#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!< Output Idle state 1 (OC1N output) */ -#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!< Output Idle state 2 (OC2 output) */ -#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!< Output Idle state 2 (OC2N output) */ -#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!< Output Idle state 3 (OC3 output) */ -#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!< Output Idle state 3 (OC3N output) */ -#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!< Output Idle state 4 (OC4 output) */ - -/******************* Bit definition for TIM_SMCR register *******************/ -#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */ -#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!< Bit 2 */ - -#define TIM_SMCR_TS ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */ -#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!< Bit 2 */ - -#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!< Master/slave mode */ - -#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */ -#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!< Bit 1 */ -#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!< Bit 2 */ -#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!< Bit 3 */ - -#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */ -#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!< External clock enable */ -#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!< External trigger polarity */ - -/******************* Bit definition for TIM_DIER register *******************/ -#define TIM_DIER_UIE ((uint16_t)0x0001) /*!< Update interrupt enable */ -#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */ -#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */ -#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */ -#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */ -#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!< COM interrupt enable */ -#define TIM_DIER_TIE ((uint16_t)0x0040) /*!< Trigger interrupt enable */ -#define TIM_DIER_BIE ((uint16_t)0x0080) /*!< Break interrupt enable */ -#define TIM_DIER_UDE ((uint16_t)0x0100) /*!< Update DMA request enable */ -#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */ -#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */ -#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */ -#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */ -#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!< COM DMA request enable */ -#define TIM_DIER_TDE ((uint16_t)0x4000) /*!< Trigger DMA request enable */ - -/******************** Bit definition for TIM_SR register ********************/ -#define TIM_SR_UIF ((uint16_t)0x0001) /*!< Update interrupt Flag */ -#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt Flag */ -#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt Flag */ -#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt Flag */ -#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt Flag */ -#define TIM_SR_COMIF ((uint16_t)0x0020) /*!< COM interrupt Flag */ -#define TIM_SR_TIF ((uint16_t)0x0040) /*!< Trigger interrupt Flag */ -#define TIM_SR_BIF ((uint16_t)0x0080) /*!< Break interrupt Flag */ -#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!< Capture/Compare 1 Overcapture Flag */ -#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!< Capture/Compare 2 Overcapture Flag */ -#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!< Capture/Compare 3 Overcapture Flag */ -#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!< Capture/Compare 4 Overcapture Flag */ - -/******************* Bit definition for TIM_EGR register ********************/ -#define TIM_EGR_UG ((uint8_t)0x01) /*!< Update Generation */ -#define TIM_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */ -#define TIM_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */ -#define TIM_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */ -#define TIM_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */ -#define TIM_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */ -#define TIM_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation */ -#define TIM_EGR_BG ((uint8_t)0x80) /*!< Break Generation */ - -/****************** Bit definition for TIM_CCMR1 register *******************/ -#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */ -#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!< Bit 1 */ - -#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */ -#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */ - -#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */ -#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */ - -#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */ - -#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */ -#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */ -#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */ - -#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */ -#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */ -#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */ - -#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */ - -/*----------------------------------------------------------------------------*/ - -#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ -#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ -#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ - -#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */ -#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */ -#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */ - -#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ -#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */ -#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */ -#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */ -#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */ - -/****************** Bit definition for TIM_CCMR2 register *******************/ -#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */ -#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!< Bit 1 */ - -#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */ -#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */ - -#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */ -#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!< Bit 2 */ - -#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */ - -#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */ -#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */ -#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */ - -#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */ -#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!< Bit 1 */ -#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!< Bit 2 */ - -#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */ - -/*----------------------------------------------------------------------------*/ - -#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ -#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ -#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ - -#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */ -#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */ -#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */ - -#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ -#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */ -#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */ -#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */ -#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */ - -/******************* Bit definition for TIM_CCER register *******************/ -#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!< Capture/Compare 1 output enable */ -#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!< Capture/Compare 1 output Polarity */ -#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!< Capture/Compare 1 Complementary output enable */ -#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!< Capture/Compare 1 Complementary output Polarity */ -#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!< Capture/Compare 2 output enable */ -#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!< Capture/Compare 2 output Polarity */ -#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!< Capture/Compare 2 Complementary output enable */ -#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!< Capture/Compare 2 Complementary output Polarity */ -#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!< Capture/Compare 3 output enable */ -#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!< Capture/Compare 3 output Polarity */ -#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!< Capture/Compare 3 Complementary output enable */ -#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!< Capture/Compare 3 Complementary output Polarity */ -#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!< Capture/Compare 4 output enable */ -#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!< Capture/Compare 4 output Polarity */ -#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!< Capture/Compare 4 Complementary output Polarity */ - -/******************* Bit definition for TIM_CNT register ********************/ -#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */ - -/******************* Bit definition for TIM_PSC register ********************/ -#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */ - -/******************* Bit definition for TIM_ARR register ********************/ -#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */ - -/******************* Bit definition for TIM_RCR register ********************/ -#define TIM_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value */ - -/******************* Bit definition for TIM_CCR1 register *******************/ -#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */ - -/******************* Bit definition for TIM_CCR2 register *******************/ -#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */ - -/******************* Bit definition for TIM_CCR3 register *******************/ -#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */ - -/******************* Bit definition for TIM_CCR4 register *******************/ -#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */ - -/******************* Bit definition for TIM_BDTR register *******************/ -#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */ -#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!< Bit 5 */ -#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!< Bit 6 */ -#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!< Bit 7 */ - -#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */ -#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */ -#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */ -#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!< Break enable */ -#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!< Break Polarity */ -#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!< Automatic Output enable */ -#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!< Main Output enable */ - -/******************* Bit definition for TIM_DCR register ********************/ -#define TIM_DCR_DBA ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */ -#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!< Bit 4 */ - -#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */ -#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!< Bit 1 */ -#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!< Bit 2 */ -#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!< Bit 3 */ -#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!< Bit 4 */ - -/******************* Bit definition for TIM_DMAR register *******************/ -#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */ - -/******************************************************************************/ -/* */ -/* Real-Time Clock */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for RTC_CRH register ********************/ -#define RTC_CRH_SECIE ((uint8_t)0x01) /*!< Second Interrupt Enable */ -#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!< Alarm Interrupt Enable */ -#define RTC_CRH_OWIE ((uint8_t)0x04) /*!< OverfloW Interrupt Enable */ - -/******************* Bit definition for RTC_CRL register ********************/ -#define RTC_CRL_SECF ((uint8_t)0x01) /*!< Second Flag */ -#define RTC_CRL_ALRF ((uint8_t)0x02) /*!< Alarm Flag */ -#define RTC_CRL_OWF ((uint8_t)0x04) /*!< OverfloW Flag */ -#define RTC_CRL_RSF ((uint8_t)0x08) /*!< Registers Synchronized Flag */ -#define RTC_CRL_CNF ((uint8_t)0x10) /*!< Configuration Flag */ -#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!< RTC operation OFF */ - -/******************* Bit definition for RTC_PRLH register *******************/ -#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!< RTC Prescaler Reload Value High */ - -/******************* Bit definition for RTC_PRLL register *******************/ -#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!< RTC Prescaler Reload Value Low */ - -/******************* Bit definition for RTC_DIVH register *******************/ -#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!< RTC Clock Divider High */ - -/******************* Bit definition for RTC_DIVL register *******************/ -#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!< RTC Clock Divider Low */ - -/******************* Bit definition for RTC_CNTH register *******************/ -#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter High */ - -/******************* Bit definition for RTC_CNTL register *******************/ -#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter Low */ - -/******************* Bit definition for RTC_ALRH register *******************/ -#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm High */ - -/******************* Bit definition for RTC_ALRL register *******************/ -#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm Low */ - -/******************************************************************************/ -/* */ -/* Independent WATCHDOG */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for IWDG_KR register ********************/ -#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */ - -/******************* Bit definition for IWDG_PR register ********************/ -#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */ -#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */ - -/******************* Bit definition for IWDG_RLR register *******************/ -#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */ - -/******************* Bit definition for IWDG_SR register ********************/ -#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */ -#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */ - -/******************************************************************************/ -/* */ -/* Window WATCHDOG */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for WWDG_CR register ********************/ -#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ -#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */ -#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */ -#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */ -#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */ -#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */ -#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */ -#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */ - -#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */ - -/******************* Bit definition for WWDG_CFR register *******************/ -#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */ -#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */ -#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */ - -#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */ -#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */ -#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */ - -#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */ - -/******************* Bit definition for WWDG_SR register ********************/ -#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */ - -/******************************************************************************/ -/* */ -/* Flexible Static Memory Controller */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for FSMC_BCR1 register *******************/ -#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ -#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ - -#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ -#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ -#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ -#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ -#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ -#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ -#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ -#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ -#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ -#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ - -/****************** Bit definition for FSMC_BCR2 register *******************/ -#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ -#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ - -#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ -#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ -#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ -#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ -#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ -#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ -#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ -#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ -#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ -#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ - -/****************** Bit definition for FSMC_BCR3 register *******************/ -#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ -#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ - -#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ -#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ -#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit. */ -#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ -#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ -#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ -#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ -#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ -#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ -#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ - -/****************** Bit definition for FSMC_BCR4 register *******************/ -#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ -#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ - -#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ -#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ -#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ -#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ -#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ -#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ -#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ -#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ -#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ -#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ - -/****************** Bit definition for FSMC_BTR1 register ******************/ -#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BTR2 register *******************/ -#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/******************* Bit definition for FSMC_BTR3 register *******************/ -#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BTR4 register *******************/ -#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BWTR1 register ******************/ -#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BWTR2 register ******************/ -#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/ -#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BWTR3 register ******************/ -#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_BWTR4 register ******************/ -#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for FSMC_PCR2 register *******************/ -#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ -#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!< Memory type */ - -#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ -#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ - -#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ -#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ -#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ - -#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ -#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ -#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ - -#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */ -#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ -#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ -#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ - -/****************** Bit definition for FSMC_PCR3 register *******************/ -#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ -#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!< Memory type */ - -#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ -#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ - -#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ -#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ -#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ - -#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ -#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ -#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ - -#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ -#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ -#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ -#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ - -/****************** Bit definition for FSMC_PCR4 register *******************/ -#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ -#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!< Memory type */ - -#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ -#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ - -#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ -#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ -#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ - -#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ -#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ -#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ - -#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ -#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ -#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ -#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ - -/******************* Bit definition for FSMC_SR2 register *******************/ -#define FSMC_SR2_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ -#define FSMC_SR2_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ -#define FSMC_SR2_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ -#define FSMC_SR2_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ -#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ -#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ -#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ - -/******************* Bit definition for FSMC_SR3 register *******************/ -#define FSMC_SR3_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ -#define FSMC_SR3_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ -#define FSMC_SR3_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ -#define FSMC_SR3_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ -#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ -#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ -#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ - -/******************* Bit definition for FSMC_SR4 register *******************/ -#define FSMC_SR4_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ -#define FSMC_SR4_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ -#define FSMC_SR4_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ -#define FSMC_SR4_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ -#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ -#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ -#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ - -/****************** Bit definition for FSMC_PMEM2 register ******************/ -#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */ -#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */ -#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */ -#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ -#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PMEM3 register ******************/ -#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */ -#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */ -#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */ -#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ -#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PMEM4 register ******************/ -#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */ -#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */ -#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */ -#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ -#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PATT2 register ******************/ -#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */ -#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ -#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ -#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ -#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PATT3 register ******************/ -#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */ -#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ -#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ -#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ -#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PATT4 register ******************/ -#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */ -#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ -#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ -#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ -#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_PIO4 register *******************/ -#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!< IOSET4[7:0] bits (I/O 4 setup time) */ -#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */ -#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */ -#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ -#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for FSMC_ECCR2 register ******************/ -#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ - -/****************** Bit definition for FSMC_ECCR3 register ******************/ -#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ - -/******************************************************************************/ -/* */ -/* SD host Interface */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for SDIO_POWER register ******************/ -#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */ -#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!< Bit 1 */ - -/****************** Bit definition for SDIO_CLKCR register ******************/ -#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!< Clock divide factor */ -#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!< Clock enable bit */ -#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!< Power saving configuration bit */ -#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!< Clock divider bypass enable bit */ - -#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */ -#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!< Bit 0 */ -#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!< Bit 1 */ - -#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!< SDIO_CK dephasing selection bit */ -#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!< HW Flow Control enable */ - -/******************* Bit definition for SDIO_ARG register *******************/ -#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */ - -/******************* Bit definition for SDIO_CMD register *******************/ -#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!< Command Index */ - -#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */ -#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */ -#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */ - -#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!< CPSM Waits for Interrupt Request */ -#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */ -#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */ -#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!< SD I/O suspend command */ -#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!< Enable CMD completion */ -#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!< Not Interrupt Enable */ -#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!< CE-ATA command */ - -/***************** Bit definition for SDIO_RESPCMD register *****************/ -#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!< Response command index */ - -/****************** Bit definition for SDIO_RESP0 register ******************/ -#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ - -/****************** Bit definition for SDIO_RESP1 register ******************/ -#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ - -/****************** Bit definition for SDIO_RESP2 register ******************/ -#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ - -/****************** Bit definition for SDIO_RESP3 register ******************/ -#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ - -/****************** Bit definition for SDIO_RESP4 register ******************/ -#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ - -/****************** Bit definition for SDIO_DTIMER register *****************/ -#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */ - -/****************** Bit definition for SDIO_DLEN register *******************/ -#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */ - -/****************** Bit definition for SDIO_DCTRL register ******************/ -#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!< Data transfer enabled bit */ -#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!< Data transfer direction selection */ -#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!< Data transfer mode selection */ -#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!< DMA enabled bit */ - -#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */ -#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!< Bit 2 */ -#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!< Bit 3 */ - -#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!< Read wait start */ -#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!< Read wait stop */ -#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!< Read wait mode */ -#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!< SD I/O enable functions */ - -/****************** Bit definition for SDIO_DCOUNT register *****************/ -#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */ - -/****************** Bit definition for SDIO_STA register ********************/ -#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */ -#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */ -#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */ -#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */ -#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */ -#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */ -#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */ -#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */ -#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */ -#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */ -#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */ -#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */ -#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */ -#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */ -#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ -#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */ -#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */ -#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */ -#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */ -#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */ -#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */ -#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */ -#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */ -#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */ - -/******************* Bit definition for SDIO_ICR register *******************/ -#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */ -#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */ -#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */ -#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */ -#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */ -#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */ -#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */ -#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */ -#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */ -#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */ -#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */ -#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */ -#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */ - -/****************** Bit definition for SDIO_MASK register *******************/ -#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */ -#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */ -#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */ -#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */ -#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */ -#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */ -#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */ -#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */ -#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */ -#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */ -#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */ -#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */ -#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */ -#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */ -#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */ -#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */ -#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */ -#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */ -#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */ -#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */ -#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */ -#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */ -#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */ -#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */ - -/***************** Bit definition for SDIO_FIFOCNT register *****************/ -#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */ - -/****************** Bit definition for SDIO_FIFO register *******************/ -#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */ - -/******************************************************************************/ -/* */ -/* USB Device FS */ -/* */ -/******************************************************************************/ - -/*!< Endpoint-specific registers */ -/******************* Bit definition for USB_EP0R register *******************/ -#define USB_EP0R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP1R register *******************/ -#define USB_EP1R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP2R register *******************/ -#define USB_EP2R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP3R register *******************/ -#define USB_EP3R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP4R register *******************/ -#define USB_EP4R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP5R register *******************/ -#define USB_EP5R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP6R register *******************/ -#define USB_EP6R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/******************* Bit definition for USB_EP7R register *******************/ -#define USB_EP7R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ - -#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ -#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ -#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ - -#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ - -#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ - -#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ -#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ - -/*!< Common registers */ -/******************* Bit definition for USB_CNTR register *******************/ -#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB Reset */ -#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power down */ -#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */ -#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force suspend */ -#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< Resume request */ -#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */ -#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */ -#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Interrupt Mask */ -#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */ -#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */ -#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< Error Interrupt Mask */ -#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */ -#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */ - -/******************* Bit definition for USB_ISTR register *******************/ -#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */ -#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< Direction of transaction */ -#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame */ -#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame */ -#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< USB RESET request */ -#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< Suspend mode request */ -#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< Wake up */ -#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< Error */ -#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */ -#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct Transfer */ - -/******************* Bit definition for USB_FNR register ********************/ -#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */ -#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */ -#define USB_FNR_LCK ((uint16_t)0x2000) /*!< Locked */ -#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< Receive Data - Line Status */ -#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< Receive Data + Line Status */ - -/****************** Bit definition for USB_DADDR register *******************/ -#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */ -#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!< Bit 0 */ -#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!< Bit 1 */ -#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!< Bit 2 */ -#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!< Bit 3 */ -#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!< Bit 4 */ -#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!< Bit 5 */ -#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!< Bit 6 */ - -#define USB_DADDR_EF ((uint8_t)0x80) /*!< Enable Function */ - -/****************** Bit definition for USB_BTABLE register ******************/ -#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!< Buffer Table */ - -/*!< Buffer descriptor table */ -/***************** Bit definition for USB_ADDR0_TX register *****************/ -#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */ - -/***************** Bit definition for USB_ADDR1_TX register *****************/ -#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */ - -/***************** Bit definition for USB_ADDR2_TX register *****************/ -#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */ - -/***************** Bit definition for USB_ADDR3_TX register *****************/ -#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */ - -/***************** Bit definition for USB_ADDR4_TX register *****************/ -#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */ - -/***************** Bit definition for USB_ADDR5_TX register *****************/ -#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */ - -/***************** Bit definition for USB_ADDR6_TX register *****************/ -#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */ - -/***************** Bit definition for USB_ADDR7_TX register *****************/ -#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */ - -/*----------------------------------------------------------------------------*/ - -/***************** Bit definition for USB_COUNT0_TX register ****************/ -#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */ - -/***************** Bit definition for USB_COUNT1_TX register ****************/ -#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */ - -/***************** Bit definition for USB_COUNT2_TX register ****************/ -#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */ - -/***************** Bit definition for USB_COUNT3_TX register ****************/ -#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */ - -/***************** Bit definition for USB_COUNT4_TX register ****************/ -#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */ - -/***************** Bit definition for USB_COUNT5_TX register ****************/ -#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */ - -/***************** Bit definition for USB_COUNT6_TX register ****************/ -#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */ - -/***************** Bit definition for USB_COUNT7_TX register ****************/ -#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */ - -/*----------------------------------------------------------------------------*/ - -/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ -#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */ - -/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ -#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */ - -/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ -#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */ - -/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ -#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */ - -/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ -#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */ - -/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ -#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */ - -/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ -#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */ - -/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ -#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */ - -/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ -#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */ - -/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ -#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */ - -/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ -#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */ - -/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ -#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */ - -/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ -#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */ - -/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ -#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */ - -/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ -#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */ - -/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ -#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */ - -/*----------------------------------------------------------------------------*/ - -/***************** Bit definition for USB_ADDR0_RX register *****************/ -#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */ - -/***************** Bit definition for USB_ADDR1_RX register *****************/ -#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */ - -/***************** Bit definition for USB_ADDR2_RX register *****************/ -#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */ - -/***************** Bit definition for USB_ADDR3_RX register *****************/ -#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */ - -/***************** Bit definition for USB_ADDR4_RX register *****************/ -#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */ - -/***************** Bit definition for USB_ADDR5_RX register *****************/ -#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */ - -/***************** Bit definition for USB_ADDR6_RX register *****************/ -#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */ - -/***************** Bit definition for USB_ADDR7_RX register *****************/ -#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */ - -/*----------------------------------------------------------------------------*/ - -/***************** Bit definition for USB_COUNT0_RX register ****************/ -#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT1_RX register ****************/ -#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT2_RX register ****************/ -#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT3_RX register ****************/ -#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT4_RX register ****************/ -#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT5_RX register ****************/ -#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT6_RX register ****************/ -#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/***************** Bit definition for USB_COUNT7_RX register ****************/ -#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ - -#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ -#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ -#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ -#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ - -#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ - -/*----------------------------------------------------------------------------*/ - -/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ -#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ -#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ -#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ -#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ -#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ -#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ -#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ -#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ -#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ -#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ -#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ -#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ -#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ -#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ -#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ - -#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ - -/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ -#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ - -#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ - -#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ - -/******************************************************************************/ -/* */ -/* Controller Area Network */ -/* */ -/******************************************************************************/ - -/*!< CAN control and status registers */ -/******************* Bit definition for CAN_MCR register ********************/ -#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!< Initialization Request */ -#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!< Sleep Mode Request */ -#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!< Transmit FIFO Priority */ -#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!< Receive FIFO Locked Mode */ -#define CAN_MCR_NART ((uint16_t)0x0010) /*!< No Automatic Retransmission */ -#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */ -#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */ -#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */ -#define CAN_MCR_RESET ((uint16_t)0x8000) /*!< CAN software master reset */ - -/******************* Bit definition for CAN_MSR register ********************/ -#define CAN_MSR_INAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */ -#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!< Sleep Acknowledge */ -#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!< Error Interrupt */ -#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!< Wakeup Interrupt */ -#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */ -#define CAN_MSR_TXM ((uint16_t)0x0100) /*!< Transmit Mode */ -#define CAN_MSR_RXM ((uint16_t)0x0200) /*!< Receive Mode */ -#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!< Last Sample Point */ -#define CAN_MSR_RX ((uint16_t)0x0800) /*!< CAN Rx Signal */ - -/******************* Bit definition for CAN_TSR register ********************/ -#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */ -#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */ -#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */ -#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */ -#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */ -#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */ -#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */ -#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */ -#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */ -#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */ -#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */ -#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */ -#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */ -#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */ -#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */ -#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */ - -#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!< TME[2:0] bits */ -#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */ -#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */ -#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */ - -#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */ -#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */ -#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */ -#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */ - -/******************* Bit definition for CAN_RF0R register *******************/ -#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!< FIFO 0 Message Pending */ -#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!< FIFO 0 Full */ -#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!< FIFO 0 Overrun */ -#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!< Release FIFO 0 Output Mailbox */ - -/******************* Bit definition for CAN_RF1R register *******************/ -#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!< FIFO 1 Message Pending */ -#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!< FIFO 1 Full */ -#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!< FIFO 1 Overrun */ -#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!< Release FIFO 1 Output Mailbox */ - -/******************** Bit definition for CAN_IER register *******************/ -#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */ -#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!< FIFO Message Pending Interrupt Enable */ -#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!< FIFO Full Interrupt Enable */ -#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!< FIFO Overrun Interrupt Enable */ -#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!< FIFO Message Pending Interrupt Enable */ -#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!< FIFO Full Interrupt Enable */ -#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!< FIFO Overrun Interrupt Enable */ -#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */ -#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */ -#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */ -#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */ -#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */ -#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */ -#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */ - -/******************** Bit definition for CAN_ESR register *******************/ -#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!< Error Warning Flag */ -#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!< Error Passive Flag */ -#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!< Bus-Off Flag */ - -#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */ -#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */ - -#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */ -#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!< Receive Error Counter */ - -/******************* Bit definition for CAN_BTR register ********************/ -#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */ -#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */ -#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */ -#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */ -#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */ -#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!< Silent Mode */ - -/*!< Mailbox registers */ -/****************** Bit definition for CAN_TI0R register ********************/ -#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ -#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ -#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ -#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ -#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ - -/****************** Bit definition for CAN_TDT0R register *******************/ -#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ -#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ -#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ - -/****************** Bit definition for CAN_TDL0R register *******************/ -#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/****************** Bit definition for CAN_TDH0R register *******************/ -#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/******************* Bit definition for CAN_TI1R register *******************/ -#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ -#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ -#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ -#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ -#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_TDT1R register ******************/ -#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ -#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ -#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ - -/******************* Bit definition for CAN_TDL1R register ******************/ -#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/******************* Bit definition for CAN_TDH1R register ******************/ -#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/******************* Bit definition for CAN_TI2R register *******************/ -#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ -#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ -#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ -#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ -#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_TDT2R register ******************/ -#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ -#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ -#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ - -/******************* Bit definition for CAN_TDL2R register ******************/ -#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/******************* Bit definition for CAN_TDH2R register ******************/ -#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/******************* Bit definition for CAN_RI0R register *******************/ -#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ -#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ -#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ -#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_RDT0R register ******************/ -#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ -#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ -#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ - -/******************* Bit definition for CAN_RDL0R register ******************/ -#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/******************* Bit definition for CAN_RDH0R register ******************/ -#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/******************* Bit definition for CAN_RI1R register *******************/ -#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ -#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ -#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ -#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_RDT1R register ******************/ -#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ -#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ -#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ - -/******************* Bit definition for CAN_RDL1R register ******************/ -#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/******************* Bit definition for CAN_RDH1R register ******************/ -#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/*!< CAN filter registers */ -/******************* Bit definition for CAN_FMR register ********************/ -#define CAN_FMR_FINIT ((uint8_t)0x01) /*!< Filter Init Mode */ - -/******************* Bit definition for CAN_FM1R register *******************/ -#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!< Filter Mode */ -#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */ -#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */ -#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */ -#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */ -#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */ -#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */ -#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */ -#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */ -#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */ -#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */ -#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */ -#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */ -#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */ -#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */ - -/******************* Bit definition for CAN_FS1R register *******************/ -#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */ -#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */ -#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */ -#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */ -#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */ -#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */ -#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */ -#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */ -#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */ -#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */ -#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */ -#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */ -#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */ -#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */ -#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */ - -/****************** Bit definition for CAN_FFA1R register *******************/ -#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!< Filter FIFO Assignment */ -#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!< Filter FIFO Assignment for Filter 0 */ -#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!< Filter FIFO Assignment for Filter 1 */ -#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!< Filter FIFO Assignment for Filter 2 */ -#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!< Filter FIFO Assignment for Filter 3 */ -#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!< Filter FIFO Assignment for Filter 4 */ -#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!< Filter FIFO Assignment for Filter 5 */ -#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!< Filter FIFO Assignment for Filter 6 */ -#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!< Filter FIFO Assignment for Filter 7 */ -#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!< Filter FIFO Assignment for Filter 8 */ -#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!< Filter FIFO Assignment for Filter 9 */ -#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!< Filter FIFO Assignment for Filter 10 */ -#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!< Filter FIFO Assignment for Filter 11 */ -#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!< Filter FIFO Assignment for Filter 12 */ -#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!< Filter FIFO Assignment for Filter 13 */ - -/******************* Bit definition for CAN_FA1R register *******************/ -#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!< Filter Active */ -#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!< Filter 0 Active */ -#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!< Filter 1 Active */ -#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!< Filter 2 Active */ -#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!< Filter 3 Active */ -#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!< Filter 4 Active */ -#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!< Filter 5 Active */ -#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!< Filter 6 Active */ -#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!< Filter 7 Active */ -#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!< Filter 8 Active */ -#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!< Filter 9 Active */ -#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!< Filter 10 Active */ -#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!< Filter 11 Active */ -#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!< Filter 12 Active */ -#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!< Filter 13 Active */ - -/******************* Bit definition for CAN_F0R1 register *******************/ -#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F1R1 register *******************/ -#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F2R1 register *******************/ -#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F3R1 register *******************/ -#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F4R1 register *******************/ -#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F5R1 register *******************/ -#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F6R1 register *******************/ -#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F7R1 register *******************/ -#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F8R1 register *******************/ -#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F9R1 register *******************/ -#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F10R1 register ******************/ -#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F11R1 register ******************/ -#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F12R1 register ******************/ -#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F13R1 register ******************/ -#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F0R2 register *******************/ -#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F1R2 register *******************/ -#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F2R2 register *******************/ -#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F3R2 register *******************/ -#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F4R2 register *******************/ -#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F5R2 register *******************/ -#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F6R2 register *******************/ -#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F7R2 register *******************/ -#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F8R2 register *******************/ -#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F9R2 register *******************/ -#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F10R2 register ******************/ -#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F11R2 register ******************/ -#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F12R2 register ******************/ -#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F13R2 register ******************/ -#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************************************************************************/ -/* */ -/* Serial Peripheral Interface */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for SPI_CR1 register ********************/ -#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */ -#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */ -#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */ - -#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */ -#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */ -#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */ -#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */ - -#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */ -#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */ -#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */ -#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */ -#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */ -#define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */ -#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */ -#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */ -#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */ -#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */ - -/******************* Bit definition for SPI_CR2 register ********************/ -#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */ -#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */ -#define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */ -#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */ -#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */ -#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */ - -/******************** Bit definition for SPI_SR register ********************/ -#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */ -#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */ -#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!< Channel side */ -#define SPI_SR_UDR ((uint8_t)0x08) /*!< Underrun flag */ -#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */ -#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */ -#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */ -#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */ - -/******************** Bit definition for SPI_DR register ********************/ -#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */ - -/******************* Bit definition for SPI_CRCPR register ******************/ -#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */ - -/****************** Bit definition for SPI_RXCRCR register ******************/ -#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */ - -/****************** Bit definition for SPI_TXCRCR register ******************/ -#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */ - -/****************** Bit definition for SPI_I2SCFGR register *****************/ -#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */ - -#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!< DATLEN[1:0] bits (Data length to be transferred) */ -#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!< Bit 0 */ -#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!< Bit 1 */ - -#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */ - -#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!< I2SSTD[1:0] bits (I2S standard selection) */ -#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */ - -#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!< I2SCFG[1:0] bits (I2S configuration mode) */ -#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!< I2S Enable */ -#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!< I2S mode selection */ - -/****************** Bit definition for SPI_I2SPR register *******************/ -#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */ -#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!< Odd factor for the prescaler */ -#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!< Master Clock Output Enable */ - -/******************************************************************************/ -/* */ -/* Inter-integrated Circuit Interface */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for I2C_CR1 register ********************/ -#define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ -#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */ -#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */ -#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */ -#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */ -#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */ -#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */ -#define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */ -#define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */ -#define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */ -#define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */ -#define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */ -#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */ -#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */ - -/******************* Bit definition for I2C_CR2 register ********************/ -#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ -#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */ - -#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */ -#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */ -#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */ -#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */ -#define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */ - -/******************* Bit definition for I2C_OAR1 register *******************/ -#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */ -#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */ - -#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */ -#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */ -#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */ -#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */ -#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */ - -#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */ - -/******************* Bit definition for I2C_OAR2 register *******************/ -#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */ -#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */ - -/******************** Bit definition for I2C_DR register ********************/ -#define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */ - -/******************* Bit definition for I2C_SR1 register ********************/ -#define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */ -#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */ -#define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */ -#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */ -#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */ -#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */ -#define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */ -#define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */ -#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */ -#define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */ -#define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */ -#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */ -#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */ -#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */ - -/******************* Bit definition for I2C_SR2 register ********************/ -#define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */ -#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */ -#define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */ -#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */ -#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */ -#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */ -#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */ -#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */ - -/******************* Bit definition for I2C_CCR register ********************/ -#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */ -#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */ -#define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */ - -/****************** Bit definition for I2C_TRISE register *******************/ -#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ - -/******************************************************************************/ -/* */ -/* Universal Synchronous Asynchronous Receiver Transmitter */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for USART_SR register *******************/ -#define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */ -#define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */ -#define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */ -#define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */ -#define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */ -#define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */ -#define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */ -#define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */ -#define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */ -#define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */ - -/******************* Bit definition for USART_DR register *******************/ -#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */ - -/****************** Bit definition for USART_BRR register *******************/ -#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!< Fraction of USARTDIV */ -#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */ - -/****************** Bit definition for USART_CR1 register *******************/ -#define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */ -#define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */ -#define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */ -#define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */ -#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */ -#define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */ -#define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */ -#define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */ -#define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */ -#define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */ -#define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */ -#define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */ -#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< USART Oversmapling 8-bits */ - -/****************** Bit definition for USART_CR2 register *******************/ -#define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */ -#define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */ -#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */ -#define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */ -#define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */ -#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */ - -#define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */ -#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */ - -/****************** Bit definition for USART_CR3 register *******************/ -#define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */ -#define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */ -#define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */ -#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */ -#define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */ -#define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */ -#define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */ -#define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */ -#define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */ -#define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */ -#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */ -#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One Bit method */ - -/****************** Bit definition for USART_GTPR register ******************/ -#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */ -#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */ -#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */ -#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */ - -#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */ - -/******************************************************************************/ -/* */ -/* Debug MCU */ -/* */ -/******************************************************************************/ - -/**************** Bit definition for DBGMCU_IDCODE register *****************/ -#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */ - -#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */ -#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */ -#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */ -#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */ -#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */ -#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */ -#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */ -#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */ -#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */ -#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */ - -/****************** Bit definition for DBGMCU_CR register *******************/ -#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */ -#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */ -#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */ -#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */ - -#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ -#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */ -#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!< Debug CAN1 stopped when Core is halted */ -#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */ -#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!< Debug CAN2 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!< Debug TIM15 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!< Debug TIM16 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!< Debug TIM17 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!< Debug TIM12 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!< Debug TIM13 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!< Debug TIM14 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!< Debug TIM9 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!< Debug TIM10 stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!< Debug TIM11 stopped when Core is halted */ - -/******************************************************************************/ -/* */ -/* FLASH and Option Bytes Registers */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for FLASH_ACR register ******************/ -#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!< LATENCY[2:0] bits (Latency) */ -#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!< Bit 0 */ -#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!< Bit 0 */ -#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!< Bit 1 */ - -#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!< Flash Half Cycle Access Enable */ -#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!< Prefetch Buffer Enable */ -#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!< Prefetch Buffer Status */ - -/****************** Bit definition for FLASH_KEYR register ******************/ -#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */ - -/***************** Bit definition for FLASH_OPTKEYR register ****************/ -#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ - -/****************** Bit definition for FLASH_SR register *******************/ -#define FLASH_SR_BSY ((uint8_t)0x01) /*!< Busy */ -#define FLASH_SR_PGERR ((uint8_t)0x04) /*!< Programming Error */ -#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!< Write Protection Error */ -#define FLASH_SR_EOP ((uint8_t)0x20) /*!< End of operation */ - -/******************* Bit definition for FLASH_CR register *******************/ -#define FLASH_CR_PG ((uint16_t)0x0001) /*!< Programming */ -#define FLASH_CR_PER ((uint16_t)0x0002) /*!< Page Erase */ -#define FLASH_CR_MER ((uint16_t)0x0004) /*!< Mass Erase */ -#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!< Option Byte Programming */ -#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!< Option Byte Erase */ -#define FLASH_CR_STRT ((uint16_t)0x0040) /*!< Start */ -#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!< Lock */ -#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!< Option Bytes Write Enable */ -#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!< Error Interrupt Enable */ -#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!< End of operation interrupt enable */ - -/******************* Bit definition for FLASH_AR register *******************/ -#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ - -/****************** Bit definition for FLASH_OBR register *******************/ -#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!< Option Byte Error */ -#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!< Read protection */ - -#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!< User Option Bytes */ -#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!< WDG_SW */ -#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!< nRST_STOP */ -#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */ -#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!< BFB2 */ - -/****************** Bit definition for FLASH_WRPR register ******************/ -#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ - -/*----------------------------------------------------------------------------*/ - -/****************** Bit definition for FLASH_RDP register *******************/ -#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */ -#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ - -/****************** Bit definition for FLASH_USER register ******************/ -#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ -#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ - -/****************** Bit definition for FLASH_Data0 register *****************/ -#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!< User data storage option byte */ -#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */ - -/****************** Bit definition for FLASH_Data1 register *****************/ -#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */ -#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */ - -/****************** Bit definition for FLASH_WRP0 register ******************/ -#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ -#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRP1 register ******************/ -#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ -#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRP2 register ******************/ -#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ -#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRP3 register ******************/ -#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ -#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ - -#ifdef STM32F10X_CL -/******************************************************************************/ -/* Ethernet MAC Registers bits definitions */ -/******************************************************************************/ -/* Bit definition for Ethernet MAC Control Register register */ -#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ -#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ -#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ - #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ - #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ - #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ - #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ - #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ - #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ - #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ - #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ -#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ -#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ -#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ -#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ -#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ -#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ -#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ -#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ -#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling - a transmission attempt during retries after a collision: 0 =< r <2^k */ - #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ - #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ - #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ - #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ -#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ -#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ -#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ - -/* Bit definition for Ethernet MAC Frame Filter Register */ -#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ -#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ -#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ -#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ -#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ - #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ - #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ - #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ -#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ -#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ -#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ -#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ -#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ -#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ - -/* Bit definition for Ethernet MAC Hash Table High Register */ -#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ - -/* Bit definition for Ethernet MAC Hash Table Low Register */ -#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ - -/* Bit definition for Ethernet MAC MII Address Register */ -#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ -#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ -#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ - #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */ - #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ - #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ -#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ -#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ - -/* Bit definition for Ethernet MAC MII Data Register */ -#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ - -/* Bit definition for Ethernet MAC Flow Control Register */ -#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ -#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ -#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ - #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ - #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ - #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ - #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ -#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ -#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ -#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ -#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ - -/* Bit definition for Ethernet MAC VLAN Tag Register */ -#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ -#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ - -/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ -#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ -/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. - Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ -/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask - Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask - Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask - Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask - Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - - RSVD - Filter1 Command - RSVD - Filter0 Command - Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset - Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 - Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ - -/* Bit definition for Ethernet MAC PMT Control and Status Register */ -#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ -#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ -#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ -#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ -#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ -#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ -#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ - -/* Bit definition for Ethernet MAC Status Register */ -#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ -#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ -#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ -#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ -#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ - -/* Bit definition for Ethernet MAC Interrupt Mask Register */ -#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ -#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ - -/* Bit definition for Ethernet MAC Address0 High Register */ -#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ - -/* Bit definition for Ethernet MAC Address0 Low Register */ -#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ - -/* Bit definition for Ethernet MAC Address1 High Register */ -#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ -#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ -#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ - #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ - #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ - #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ - #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ - #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ - #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ -#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ - -/* Bit definition for Ethernet MAC Address1 Low Register */ -#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ - -/* Bit definition for Ethernet MAC Address2 High Register */ -#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ -#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ -#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ - #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ - #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ - #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ - #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ - #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ - #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ -#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ - -/* Bit definition for Ethernet MAC Address2 Low Register */ -#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ - -/* Bit definition for Ethernet MAC Address3 High Register */ -#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ -#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ -#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ - #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ - #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ - #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ - #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ - #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ - #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ -#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ - -/* Bit definition for Ethernet MAC Address3 Low Register */ -#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ - -/******************************************************************************/ -/* Ethernet MMC Registers bits definition */ -/******************************************************************************/ - -/* Bit definition for Ethernet MMC Contol Register */ -#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ -#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ -#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ -#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ - -/* Bit definition for Ethernet MMC Receive Interrupt Register */ -#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ -#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ -#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Transmit Interrupt Register */ -#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ -#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ -#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ -#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ -#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ -#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ -#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ -#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ -#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ -#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ - -/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ -#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ - -/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ -#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ - -/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ -#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ - -/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ -#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ - -/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ -#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ - -/******************************************************************************/ -/* Ethernet PTP Registers bits definition */ -/******************************************************************************/ - -/* Bit definition for Ethernet PTP Time Stamp Contol Register */ -#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ -#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ -#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ -#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ -#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ -#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ - -/* Bit definition for Ethernet PTP Sub-Second Increment Register */ -#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ - -/* Bit definition for Ethernet PTP Time Stamp High Register */ -#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ - -/* Bit definition for Ethernet PTP Time Stamp Low Register */ -#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ -#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ - -/* Bit definition for Ethernet PTP Time Stamp High Update Register */ -#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ - -/* Bit definition for Ethernet PTP Time Stamp Low Update Register */ -#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ -#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ - -/* Bit definition for Ethernet PTP Time Stamp Addend Register */ -#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ - -/* Bit definition for Ethernet PTP Target Time High Register */ -#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ - -/* Bit definition for Ethernet PTP Target Time Low Register */ -#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ - -/******************************************************************************/ -/* Ethernet DMA Registers bits definition */ -/******************************************************************************/ - -/* Bit definition for Ethernet DMA Bus Mode Register */ -#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ -#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ -#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ -#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ - #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ - #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ - #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ - #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ - #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ - #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ - #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ - #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ - #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ - #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ - #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ - #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ -#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ -#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ -#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ - #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ - #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ - #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ - #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ - #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ - #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ - #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ - #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ - #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ - #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ - #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ - #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ -#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ -#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ -#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ - -/* Bit definition for Ethernet DMA Transmit Poll Demand Register */ -#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ - -/* Bit definition for Ethernet DMA Receive Poll Demand Register */ -#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ - -/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ -#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ - -/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ -#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ - -/* Bit definition for Ethernet DMA Status Register */ -#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ -#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ -#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ -#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ - /* combination with EBS[2:0] for GetFlagStatus function */ - #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ - #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ - #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ -#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ - #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ - #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ - #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ - #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ - #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ - #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ -#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ - #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ - #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ - #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ - #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ - #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ - #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ -#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ -#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ -#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ -#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ -#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ -#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ -#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ -#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ -#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ -#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ -#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ -#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ -#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ -#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ -#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ - -/* Bit definition for Ethernet DMA Operation Mode Register */ -#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ -#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ -#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ -#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ -#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ -#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ - #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ - #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ - #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ - #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ - #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ - #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ - #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ - #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ -#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ -#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ -#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ -#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ - #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ - #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ - #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ - #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ -#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ -#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ - -/* Bit definition for Ethernet DMA Interrupt Enable Register */ -#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ -#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ -#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ -#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ -#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ -#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ -#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ -#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ -#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ -#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ -#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ -#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ -#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ -#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ -#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ - -/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ -#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ -#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ -#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ -#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ - -/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ -#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ - -/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ -#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ - -/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ -#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ - -/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ -#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ -#endif /* STM32F10X_CL */ - -/** - * @} - */ - - /** - * @} - */ - -#ifdef USE_STDPERIPH_DRIVER - #include "stm32f10x_conf.h" -#endif - -/** @addtogroup Exported_macro - * @{ - */ - -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_H */ - -/** - * @} - */ - - /** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c deleted file mode 100644 index 6fb4579ec..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c +++ /dev/null @@ -1,1094 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f10x.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier - * factors, AHB/APBx prescalers and Flash settings). - * This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f10x_xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the HSI (8 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to - * configure the system clock before to branch to main program. - * - * 3. If the system clock source selected by user fails to startup, the SystemInit() - * function will do nothing and HSI still used as system clock source. User can - * add some code to deal with this issue inside the SetSysClock() function. - * - * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on - * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. - * When HSE is used as system clock source, directly or through PLL, and you - * are using different crystal you have to adapt the HSE value to your own - * configuration. - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f10x_system - * @{ - */ - -/** @addtogroup STM32F10x_System_Private_Includes - * @{ - */ - -#include "stm32f10x.h" - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_Defines - * @{ - */ - -/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) - frequency (after reset the HSI is used as SYSCLK source) - - IMPORTANT NOTE: - ============== - 1. After each device reset the HSI is used as System clock source. - - 2. Please make sure that the selected System clock doesn't exceed your device's - maximum frequency. - - 3. If none of the define below is enabled, the HSI is used as System clock - source. - - 4. The System clock configuration functions provided within this file assume that: - - For Low, Medium and High density Value line devices an external 8MHz - crystal is used to drive the System clock. - - For Low, Medium and High density devices an external 8MHz crystal is - used to drive the System clock. - - For Connectivity line devices an external 25MHz crystal is used to drive - the System clock. - If you are using different crystal you have to adapt those functions accordingly. - */ - -#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) -/* #define SYSCLK_FREQ_HSE HSE_VALUE */ - #define SYSCLK_FREQ_24MHz 24000000 -#else -/* #define SYSCLK_FREQ_HSE HSE_VALUE */ -/* #define SYSCLK_FREQ_24MHz 24000000 */ -/* #define SYSCLK_FREQ_36MHz 36000000 */ -/* #define SYSCLK_FREQ_48MHz 48000000 */ -/* #define SYSCLK_FREQ_56MHz 56000000 */ -#define SYSCLK_FREQ_72MHz 72000000 -#endif - -/*!< Uncomment the following line if you need to use external SRAM mounted - on STM3210E-EVAL board (STM32 High density and XL-density devices) or on - STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ -#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) -/* #define DATA_IN_ExtSRAM */ -#endif - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_Variables - * @{ - */ - -/******************************************************************************* -* Clock Definitions -*******************************************************************************/ -#ifdef SYSCLK_FREQ_HSE - uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_24MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_36MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_48MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_56MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_72MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ -#else /*!< HSI Selected as System Clock source */ - uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ -#endif - -__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); - -#ifdef SYSCLK_FREQ_HSE - static void SetSysClockToHSE(void); -#elif defined SYSCLK_FREQ_24MHz - static void SetSysClockTo24(void); -#elif defined SYSCLK_FREQ_36MHz - static void SetSysClockTo36(void); -#elif defined SYSCLK_FREQ_48MHz - static void SetSysClockTo48(void); -#elif defined SYSCLK_FREQ_56MHz - static void SetSysClockTo56(void); -#elif defined SYSCLK_FREQ_72MHz - static void SetSysClockTo72(void); -#endif - -#ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemCoreClock variable. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -void SystemInit (void) -{ - /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ -#ifndef STM32F10X_CL - RCC->CFGR &= (uint32_t)0xF8FF0000; -#else - RCC->CFGR &= (uint32_t)0xF0FF0000; -#endif /* STM32F10X_CL */ - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ - RCC->CFGR &= (uint32_t)0xFF80FFFF; - -#ifdef STM32F10X_CL - /* Reset PLL2ON and PLL3ON bits */ - RCC->CR &= (uint32_t)0xEBFFFFFF; - - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x00FF0000; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; -#else - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) - #ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); - #endif /* DATA_IN_ExtSRAM */ -#endif - - /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ - /* Configure the Flash Latency cycles and enable prefetch buffer */ - SetSysClock(); - -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value - * 8 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value - * 8 MHz or 25 MHz, depedning on the product used), user has to ensure - * that HSE_VALUE is same as the real frequency of the crystal used. - * Otherwise, this function may have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * @param None - * @retval None - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0; - -#ifdef STM32F10X_CL - uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) - uint32_t prediv1factor = 0; -#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock */ - - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - -#ifndef STM32F10X_CL - pllmull = ( pllmull >> 18) + 2; - - if (pllsource == 0x00) - { - /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; - } - else - { - #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; - /* HSE oscillator clock selected as PREDIV1 clock entry */ - SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; - #else - /* HSE selected as PLL clock entry */ - if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) - {/* HSE oscillator clock divided by 2 */ - SystemCoreClock = (HSE_VALUE >> 1) * pllmull; - } - else - { - SystemCoreClock = HSE_VALUE * pllmull; - } - #endif - } -#else - pllmull = pllmull >> 18; - - if (pllmull != 0x0D) - { - pllmull += 2; - } - else - { /* PLL multiplication factor = PLL input clock * 6.5 */ - pllmull = 13 / 2; - } - - if (pllsource == 0x00) - { - /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; - } - else - {/* PREDIV1 selected as PLL clock entry */ - - /* Get PREDIV1 clock source and division factor */ - prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; - - if (prediv1source == 0) - { - /* HSE oscillator clock selected as PREDIV1 clock entry */ - SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; - } - else - {/* PLL2 clock selected as PREDIV1 clock entry */ - - /* Get PREDIV2 division factor and PLL2 multiplication factor */ - prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; - pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; - SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; - } - } -#endif /* STM32F10X_CL */ - break; - - default: - SystemCoreClock = HSI_VALUE; - break; - } - - /* Compute HCLK clock frequency ----------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. - * @param None - * @retval None - */ -static void SetSysClock(void) -{ -#ifdef SYSCLK_FREQ_HSE - SetSysClockToHSE(); -#elif defined SYSCLK_FREQ_24MHz - SetSysClockTo24(); -#elif defined SYSCLK_FREQ_36MHz - SetSysClockTo36(); -#elif defined SYSCLK_FREQ_48MHz - SetSysClockTo48(); -#elif defined SYSCLK_FREQ_56MHz - SetSysClockTo56(); -#elif defined SYSCLK_FREQ_72MHz - SetSysClockTo72(); -#endif - - /* If none of the define above is enabled, the HSI is used as System clock - source (default after reset) */ -} - -/** - * @brief Setup the external memory controller. Called in startup_stm32f10x.s - * before jump to __main - * @param None - * @retval None - */ -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f10x_xx.s/.c before jump to main. - * This function configures the external SRAM mounted on STM3210E-EVAL - * board (STM32 High density devices). This SRAM will be used as program - * data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ -/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is - required, then adjust the Register Addresses */ - - /* Enable FSMC clock */ - RCC->AHBENR = 0x00000114; - - /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ - RCC->APB2ENR = 0x000001E0; - -/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ -/*---------------- SRAM Address lines configuration -------------------------*/ -/*---------------- NOE and NWE configuration --------------------------------*/ -/*---------------- NE3 configuration ----------------------------------------*/ -/*---------------- NBL0, NBL1 configuration ---------------------------------*/ - - GPIOD->CRL = 0x44BB44BB; - GPIOD->CRH = 0xBBBBBBBB; - - GPIOE->CRL = 0xB44444BB; - GPIOE->CRH = 0xBBBBBBBB; - - GPIOF->CRL = 0x44BBBBBB; - GPIOF->CRH = 0xBBBB4444; - - GPIOG->CRL = 0x44BBBBBB; - GPIOG->CRH = 0x44444B44; - -/*---------------- FSMC Configuration ---------------------------------------*/ -/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ - - FSMC_Bank1->BTCR[4] = 0x00001011; - FSMC_Bank1->BTCR[5] = 0x00000200; -} -#endif /* DATA_IN_ExtSRAM */ - -#ifdef SYSCLK_FREQ_HSE -/** - * @brief Selects HSE as System clock source and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockToHSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - -#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 0 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - -#ifndef STM32F10X_CL - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; -#else - if (HSE_VALUE <= 24000000) - { - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; - } - else - { - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; - } -#endif /* STM32F10X_CL */ -#endif - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - - /* Select HSE as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; - - /* Wait till HSE is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_24MHz -/** - * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo24(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 0 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; -#endif - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | - RCC_CFGR_PLLMULL6); - - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); -#else - /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); -#endif /* STM32F10X_CL */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_36MHz -/** - * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo36(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - - /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | - RCC_CFGR_PLLMULL9); - - /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ - - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } - -#else - /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); -#endif /* STM32F10X_CL */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_48MHz -/** - * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo48(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ - - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } - - - /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | - RCC_CFGR_PLLMULL6); -#else - /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); -#endif /* STM32F10X_CL */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_56MHz -/** - * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo56(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 2 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ - - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } - - - /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | - RCC_CFGR_PLLMULL7); -#else - /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); - -#endif /* STM32F10X_CL */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_72MHz -/** - * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo72(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 2 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; - - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ - - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } - - - /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | - RCC_CFGR_PLLMULL9); -#else - /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | - RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); -#endif /* STM32F10X_CL */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#endif - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h deleted file mode 100644 index 739f33283..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f10x.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f10x_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32F10X_H -#define __SYSTEM_STM32F10X_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32F10x_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32F10x_System_Exported_types - * @{ - */ - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32F10X_H */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CMSIS debug support.htm b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CMSIS debug support.htm deleted file mode 100644 index efda685be..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CMSIS debug support.htm +++ /dev/null @@ -1,243 +0,0 @@ - - - -CMSIS Debug Support - - - - - - - - -

CMSIS Debug Support

- -
- -

Cortex-M3 ITM Debug Access

-

- The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with - the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has - 32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM - communication channels are used by CMSIS to output the following information: -

-
    -
  • ITM Channel 0: used for printf-style output via the debug interface.
    • -
  • ITM Channel 31: is reserved for RTOS kernel awareness debugging.
    • -
- -

Debug IN / OUT functions

-

CMSIS provides following debug functions:

-
    -
  • ITM_SendChar (uses ITM channel 0)
    • -
  • ITM_ReceiveChar (uses global variable)
    • -
  • ITM_CheckChar (uses global variable)
    • -
- -

ITM_SendChar

-

- ITM_SendChar is used to transmit a character over ITM channel 0 from - the microcontroller system to the debug system.
- Only a 8 bit value is transmitted. -

-
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  /* check if debugger connected and ITM channel enabled for tracing */
-  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA)  &&
-      (ITM->TCR & ITM_TCR_ITMENA)                  &&
-      (ITM->TER & (1UL << 0))  ) 
-  {
-    while (ITM->PORT[0].u32 == 0);
-    ITM->PORT[0].u8 = (uint8_t)ch;
-  }  
-  return (ch);
-}
- -

ITM_ReceiveChar

-

- ITM communication channel is only capable for OUT direction. For IN direction - a globel variable is used. A simple mechansim detects if a character is received. - The project to test need to be build with debug information. -

- -

- The globale variable ITM_RxBuffer is used to transmit a 8 bit value from debug system - to microcontroller system. ITM_RxBuffer is 32 bit wide to enshure a proper handshake. -

-
-extern volatile int ITM_RxBuffer;                    /* variable to receive characters                             */
-
-

- A dedicated bit pattern is used to determin if ITM_RxBuffer is empty - or contains a valid value. -

-
-#define             ITM_RXBUFFER_EMPTY    0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
-
-

- ITM_ReceiveChar is used to receive a 8 bit value from the debug system. The function is nonblocking. - It returns the received character or '-1' if no character was available. -

-
-static __INLINE int ITM_ReceiveChar (void) {
-  int ch = -1;                               /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-  
-  return (ch); 
-}
-
- -

ITM_CheckChar

-

- ITM_CheckChar is used to check if a character is received. -

-
-static __INLINE int ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}
- - -

ITM Debug Support in uVision

-

- uVision uses in a debug session the Debug (printf) Viewer window to - display the debug data. -

-

Direction microcontroller system -> uVision:

-
    -
  • - Characters received via ITM communication channel 0 are written in a printf style - to Debug (printf) Viewer window. -
    • -
- -

Direction uVision -> microcontroller system:

-
    -
  • Check if ITM_RxBuffer variable is available (only performed once).
    • -
  • Read character from Debug (printf) Viewer window.
    • -
  • If ITM_RxBuffer empty write character to ITM_RxBuffer.
    • -
- -

Note

-
    -

  • Current solution does not use a buffer machanism for trasmitting the characters.

    -
    • -
- -

RTX Kernel awareness in uVision

-

- uVision / RTX are using a simple and efficient solution for RTX Kernel awareness. - No format overhead is necessary.
- uVsion debugger decodes the RTX events via the 32 / 16 / 8 bit ITM write access - to ITM communication channel 31. -

- -

Following RTX events are traced:

-
    -
  • Task Create / Delete event -
      -
    1. 32 bit access. Task start address is transmitted
      2. -
    2. 16 bit access. Task ID and Create/Delete flag are transmitted
      - High byte holds Create/Delete flag, Low byte holds TASK ID. -
      3. -
    -
    • -
  • Task switch event -
      -
    1. 8 bit access. Task ID of current task is transmitted
      2. -
    -
    • -
- -

Note

-
    -

  • Other RTOS information could be retrieved via memory read access in a polling mode manner.

    -
    • -
- - -

 

- -
- -

Copyright © KEIL - An ARM Company.
-All rights reserved.
-Visit our web site at www.keil.com. -

- - - - \ No newline at end of file diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CMSIS_changes.htm b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CMSIS_changes.htm deleted file mode 100644 index 162ffcc9d..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CMSIS_changes.htm +++ /dev/null @@ -1,320 +0,0 @@ - - - -CMSIS Changes - - - - - - - - -

Changes to CMSIS version V1.20

- -
- -

1. Removed CMSIS Middelware packages

-

- CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found. -

- -

2. SystemFrequency renamed to SystemCoreClock

-

- The variable name SystemCoreClock is more precise than SystemFrequency - because the variable holds the clock value at which the core is running. -

- -

3. Changed startup concept

-

- The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit - from main) has the weakness that it does not work for controllers which need a already - configuerd clock system to configure the external memory controller. -

- -

Changed startup concept

-
    -
  • - SystemInit() is called from startup file before premain. -
    • -
  • - SystemInit() configures the clock system and also configures - an existing external memory controller. -
    • -
  • - SystemInit() must not use global variables. -
    • -
  • - SystemCoreClock is initialized with a correct predefined value. -
    • -
  • - Additional function void SystemCoreClockUpdate (void) is provided.
    - SystemCoreClockUpdate() updates the variable SystemCoreClock - and must be called whenever the core clock is changed.
    - SystemCoreClockUpdate() evaluates the clock register settings and calculates - the current core clock. -
    • -
- - -

4. Advanced Debug Functions

-

- ITM communication channel is only capable for OUT direction. To allow also communication for - IN direction a simple concept is provided. -

-
    -
  • - Global variable volatile int ITM_RxBuffer used for IN data. -
    • -
  • - Function int ITM_CheckChar (void) checks if a new character is available. -
    • -
  • - Function int ITM_ReceiveChar (void) retrieves the new character. -
    • -
- -

- For detailed explanation see file CMSIS debug support.htm. -

- - -

5. Core Register Bit Definitions

-

- Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the - defines correspond with the Cortex-M Technical Reference Manual. -

-

- e.g. SysTick structure with bit definitions -

-
-/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
-  memory mapped structure for SysTick
-  @{
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                         /*!< Offset: 0x00  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                         /*!< Offset: 0x04  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                          /*!< Offset: 0x08  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                        /*!< Offset: 0x0C  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1ul << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1ul << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1ul << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1ul << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1ul << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1ul << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-/*@}*/ /* end of group CMSIS_CM3_SysTick */
- -

7. DoxyGen Tags

-

- DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation - using DoxyGen. -

- -

8. Folder Structure

-

- The folder structure is changed to differentiate the single support packages. -

- -
    -
  • CM0
    • -
  • CM3 -
      -
    • CoreSupport
      • -
    • DeviceSupport
      • -
        -
      • Vendor -
          -
        • Device -
            -
          • Startup -
              -
            • Toolchain
              • -
            • Toolchain
              • -
            • ...
              • -
            -
            • -
          -
          • -
        • Device
          • -
        • ...
          • -
        -
        • -
      • Vendor
        • -
      • ...
        • -
      - -
    • Example -
        -
      • Toolchain -
          -
        • Device
          • -
        • Device
          • -
        • ...
          • -
        -
        • -
      • Toolchain
        • -
      • ...
        • -
      -
      • -
    -
    • - -
  • Documentation
    • -
- -

9. Open Points

-

- Following points need to be clarified and solved: -

-
    -
  • -

    - Equivalent C and Assembler startup files. -

    -

    - Is there a need for having C startup files although assembler startup files are - very efficient and do not need to be changed? -

    -

    • -
  • -

    - Placing of HEAP in external RAM. -

    -

    - It must be possible to place HEAP in external RAM if the device supports an - external memory controller. -

    -
    • -
  • -

    - Placing of STACK /HEAP. -

    -

    - STACK should always be placed at the end of internal RAM. -

    -

    - If HEAP is placed in internal RAM than it should be placed after RW ZI section. -

    -
    • -
  • -

    - Removing core_cm3.c and core_cm0.c. -

    -

    - On a long term the functions in core_cm3.c and core_cm0.c must be replaced with - appropriate compiler intrinsics. -

    -
    • -
- - -

10. Limitations

-

- The following limitations are not covered with the current CMSIS version: -

-
    -
  • - No C startup files for ARM toolchain are provided. -
    • -
  • - No C startup files for GNU toolchain are provided. -
    • -
  • - No C startup files for IAR toolchain are provided. -
    • -
  • - No Tasking projects are provided yet. -
    • -
diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/Documentation/CMSIS_Core.htm b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/Documentation/CMSIS_Core.htm deleted file mode 100644 index 6fd131e12..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/Documentation/CMSIS_Core.htm +++ /dev/null @@ -1,1337 +0,0 @@ - - - - CMSIS: Cortex Microcontroller Software Interface Standard - - - -

Cortex Microcontroller Software Interface Standard

- -

This file describes the Cortex Microcontroller Software Interface Standard (CMSIS).

-

Version: 1.30 - 30. October 2009

- -

Information in this file, the accompany manuals, and software is
- Copyright © ARM Ltd.
All rights reserved. -

- -
- -

Revision History

-
    -
  • Version 1.00: initial release.
    • -
  • Version 1.01: added __LDREXx, __STREXx, and __CLREX.
    • -
  • Version 1.02: added Cortex-M0.
    • -
  • Version 1.10: second review.
    • -
  • Version 1.20: third review.
    • -
  • Version 1.30 PRE-RELEASE: reworked Startup Concept, additional Debug Functionality.
    • -
  • Version 1.30 2nd PRE-RELEASE: changed folder structure, added doxyGen comments, added Bit definitions.
    • -
  • Version 1.30: updated Device Support Packages.
    • -
- -
- -

Contents

- -
    -
  1. About
    2. -
  2. Coding Rules and Conventions
    3. -
  3. CMSIS Files
    4. -
  4. Core Peripheral Access Layer
    5. -
  5. CMSIS Example
    6. -
- -

About

- -

- The Cortex Microcontroller Software Interface Standard (CMSIS) answers the challenges - that are faced when software components are deployed to physical microcontroller devices based on a - Cortex-M0 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M - processor cores (the term Cortex-M is used to indicate that). The CMSIS is defined in close co-operation - with various silicon and software vendors and provides a common approach to interface to peripherals, - real-time operating systems, and middleware components. -

- -

ARM provides as part of the CMSIS the following software layers that are -available for various compiler implementations:

-
    -
  • Core Peripheral Access Layer: contains name definitions, - address definitions and helper functions to - access core registers and peripherals. It defines also a device - independent interface for RTOS Kernels that includes debug channel - definitions.
    • -
- -

These software layers are expanded by Silicon partners with:

-
    -
  • Device Peripheral Access Layer: provides definitions - for all device peripherals
    • -
  • Access Functions for Peripherals (optional): provides - additional helper functions for peripherals
    • -
- -

CMSIS defines for a Cortex-M Microcontroller System:

-
    -
  • A common way to access peripheral registers - and a common way to define exception vectors.
    • -
  • The register names of the Core - Peripherals and the names of the Core - Exception Vectors.
    • -
  • An device independent interface for RTOS Kernels including a debug - channel.
    • -
- -

- By using CMSIS compliant software components, the user can easier re-use template code. - CMSIS is intended to enable the combination of software components from multiple middleware vendors. -

- -

Coding Rules and Conventions

- -

- The following section describes the coding rules and conventions used in the CMSIS - implementation. It contains also information about data types and version number information. -

- -

Essentials

-
    -
  • The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations, - there are disable and enable sequences for PC-LINT inserted.
    • -
  • ANSI standard data types defined in the ANSI C header file - <stdint.h> are used.
    • -
  • #define constants that include expressions must be enclosed by - parenthesis.
    • -
  • Variables and parameters have a complete data type.
    • -
  • All functions in the Core Peripheral Access Layer are - re-entrant.
    • -
  • The Core Peripheral Access Layer has no blocking code - (which means that wait/query loops are done at other software layers).
    • -
  • For each exception/interrupt there is definition for: -
      -
    • an exception/interrupt handler with the postfix _Handler - (for exceptions) or _IRQHandler (for interrupts).
      • -
    • a default exception/interrupt handler (weak definition) that contains an endless loop.
      • -
    • a #define of the interrupt number with the postfix _IRQn.
      • -
    • -
- -

Recommendations

- -

The CMSIS recommends the following conventions for identifiers.

-
    -
  • CAPITAL names to identify Core Registers, Peripheral Registers, and CPU Instructions.
    • -
  • CamelCase names to identify peripherals access functions and interrupts.
    • -
  • PERIPHERAL_ prefix to identify functions that belong to specify peripherals.
    • -
  • Doxygen comments for all functions are included as described under Function Comments below.
    • -
- -Comments - -
    -
  • Comments use the ANSI C90 style (/* comment */) or C++ style - (// comment). It is assumed that the programming tools support today - consistently the C++ comment style.
    • -
  • Function Comments provide for each function the following information: -
      -
    • one-line brief function overview.
      • -
    • detailed parameter explanation.
      • -
    • detailed information about return values.
      • -
    • detailed description of the actual function.
      • -
    -

    Doxygen Example:

    - 
    -/** 
- * @brief  Enable Interrupt in NVIC Interrupt Controller
- * @param  IRQn  interrupt number that specifies the interrupt
- * @return none.
- * Enable the specified interrupt in the NVIC Interrupt Controller.
- * Other settings of the interrupt such as priority are not affected.
- */
    -
    • -
- -

Data Types and IO Type Qualifiers

- -

- The Cortex-M HAL uses the standard types from the standard ANSI C header file - <stdint.h>. IO Type Qualifiers are used to specify the access - to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of - debug information of peripheral registers. -

- - - - - - - - - - - - - - - - - - - - - - - - -
IO Type Qualifier#defineDescription
__Ivolatile constRead access only
__OvolatileWrite access only
__IOvolatileRead and write access
- -

CMSIS Version Number

-

- File core_cm3.h contains the version number of the CMSIS with the following define: -

- -
-#define __CM3_CMSIS_VERSION_MAIN  (0x01)      /* [31:16] main version       */
-#define __CM3_CMSIS_VERSION_SUB   (0x30)      /* [15:0]  sub version        */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB)
- -

- File core_cm0.h contains the version number of the CMSIS with the following define: -

- -
-#define __CM0_CMSIS_VERSION_MAIN  (0x01)      /* [31:16] main version       */
-#define __CM0_CMSIS_VERSION_SUB   (0x30)      /* [15:0]  sub version        */
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB)
- - -

CMSIS Cortex Core

-

- File core_cm3.h contains the type of the CMSIS Cortex-M with the following define: -

- -
-#define __CORTEX_M                (0x03)
- -

- File core_cm0.h contains the type of the CMSIS Cortex-M with the following define: -

- -
-#define __CORTEX_M                (0x00)
- - -

CMSIS Files

-

- This section describes the Files provided in context with the CMSIS to access the Cortex-M - hardware and peripherals. -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
FileProviderDescription
device.hDevice specific (provided by silicon partner)Defines the peripherals for the actual device. The file may use - several other include files to define the peripherals of the actual device.
core_cm0.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the core peripherals for the Cortex-M0 CPU and core peripherals.
core_cm3.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the core peripherals for the Cortex-M3 CPU and core peripherals.
core_cm0.cARM (for RealView ARMCC, IAR, and GNU GCC)Provides helper functions that access core registers.
core_cm3.cARM (for RealView ARMCC, IAR, and GNU GCC)Provides helper functions that access core registers.
startup_deviceARM (adapted by compiler partner / silicon partner)Provides the Cortex-M startup code and the complete (device specific) Interrupt Vector Table
system_deviceARM (adapted by silicon partner)Provides a device specific configuration file for the device. It configures the device initializes - typically the oscillator (PLL) that is part of the microcontroller device
- -

device.h

- -

- The file device.h is provided by the silicon vendor and is the - central include file that the application programmer is using in - the C source code. This file contains: -

-
    -
  • -

    Interrupt Number Definition: provides interrupt numbers - (IRQn) for all core and device specific exceptions and interrupts.

    -
    • -
  • -

    Configuration for core_cm0.h / core_cm3.h: reflects the - actual configuration of the Cortex-M processor that is part of the actual - device. As such the file core_cm0.h / core_cm3.h is included that - implements access to processor registers and core peripherals.

    -
    • -
  • -

    Device Peripheral Access Layer: provides definitions - for all device peripherals. It contains all data structures and the address - mapping for the device specific peripherals.

    -
    • -
  • Access Functions for Peripherals (optional): provides - additional helper functions for peripherals that are useful for programming - of these peripherals. Access Functions may be provided as inline functions - or can be extern references to a device specific library provided by the - silicon vendor.
    • -
- - -

Interrupt Number Definition

- -

To access the device specific interrupts the device.h file defines IRQn -numbers for the complete device using a enum typedef as shown below:

-
-typedef enum IRQn
-{
-/******  Cortex-M3 Processor Exceptions/Interrupt Numbers ************************************************/
-  NonMaskableInt_IRQn             = -14,      /*!< 2 Non Maskable Interrupt                              */
-  HardFault_IRQn                  = -13,      /*!< 3 Cortex-M3 Hard Fault Interrupt                      */
-  MemoryManagement_IRQn           = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt               */
-  BusFault_IRQn                   = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                       */
-  UsageFault_IRQn                 = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                     */
-  SVCall_IRQn                     = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                        */
-  DebugMonitor_IRQn               = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt                  */
-  PendSV_IRQn                     = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                        */
-  SysTick_IRQn                    = -1,       /*!< 15 Cortex-M3 System Tick Interrupt                    */
-/******  STM32 specific Interrupt Numbers ****************************************************************/
-  WWDG_STM_IRQn                   = 0,        /*!< Window WatchDog Interrupt                             */
-  PVD_STM_IRQn                    = 1,        /*!< PVD through EXTI Line detection Interrupt             */
-  :
-  :
-  } IRQn_Type;
- - -

Configuration for core_cm0.h / core_cm3.h

-

- The Cortex-M core configuration options which are defined for each device implementation. Some - configuration options are reflected in the CMSIS layer using the #define settings described below. -

-

- To access core peripherals file device.h includes file core_cm0.h / core_cm3.h. - Several features in core_cm0.h / core_cm3.h are configured by the following defines that must be - defined before #include <core_cm0.h> / #include <core_cm3.h> - preprocessor command. -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#defineFileValueDescription
__NVIC_PRIO_BITScore_cm0.h(2)Number of priority bits implemented in the NVIC (device specific)
__NVIC_PRIO_BITScore_cm3.h(2 ... 8)Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENTcore_cm0.h, core_cm3.h(0, 1)Defines if an MPU is present or not
__Vendor_SysTickConfigcore_cm0.h, core_cm3.h(1)When this define is setup to 1, the SysTickConfig function - in core_cm3.h is excluded. In this case the device.h - file must contain a vendor specific implementation of this function.
- - -

Device Peripheral Access Layer

-

- Each peripheral uses a prefix which consists of <device abbreviation>_ - and <peripheral name>_ to identify peripheral registers that access this - specific peripheral. The intention of this is to avoid name collisions caused - due to short names. If more than one peripheral of the same type exists, - identifiers have a postfix (digit or letter). For example: -

-
    -
  • <device abbreviation>_UART_Type: defines the generic register layout for all UART channels in a device. - 
    -typedef struct
-{
-  union {
-  __I  uint8_t  RBR;                     /*!< Offset: 0x000   Receiver Buffer Register    */
-  __O  uint8_t  THR;                     /*!< Offset: 0x000   Transmit Holding Register   */
-  __IO uint8_t  DLL;                     /*!< Offset: 0x000   Divisor Latch LSB           */
-       uint32_t RESERVED0;
-  };
-  union {
-  __IO uint8_t  DLM;                     /*!< Offset: 0x004   Divisor Latch MSB           */
-  __IO uint32_t IER;                     /*!< Offset: 0x004   Interrupt Enable Register   */
-  };
-  union {
-  __I  uint32_t IIR;                     /*!< Offset: 0x008   Interrupt ID Register       */
-  __O  uint8_t  FCR;                     /*!< Offset: 0x008   FIFO Control Register       */
-  };
-  __IO uint8_t  LCR;                     /*!< Offset: 0x00C   Line Control Register       */
-       uint8_t  RESERVED1[7];
-  __I  uint8_t  LSR;                     /*!< Offset: 0x014   Line Status Register        */
-       uint8_t  RESERVED2[7];
-  __IO uint8_t  SCR;                     /*!< Offset: 0x01C   Scratch Pad Register        */
-       uint8_t  RESERVED3[3];
-  __IO uint32_t ACR;                     /*!< Offset: 0x020   Autobaud Control Register   */
-  __IO uint8_t  ICR;                     /*!< Offset: 0x024   IrDA Control Register       */
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  FDR;                     /*!< Offset: 0x028   Fractional Divider Register */
-       uint8_t  RESERVED5[7];
-  __IO uint8_t  TER;                     /*!< Offset: 0x030   Transmit Enable Register    */
-       uint8_t  RESERVED6[39];
-  __I  uint8_t  FIFOLVL;                 /*!< Offset: 0x058   FIFO Level Register         */
-} LPC_UART_TypeDef;
    -
    • -
  • <device abbreviation>_UART1: is a pointer to a register structure that refers to a specific UART. - For example UART1->DR is the data register of UART1. - 
    -#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
-#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )
    -
    • -
- -
Minimal Requiements
-

- To access the peripheral registers and related function in a device the files device.h - and core_cm0.h / core_cm3.h defines as a minimum: -

-
    -
  • The Register Layout Typedef for each peripheral that defines all register names. - Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of - the peripheral registers. For example: - 
    -typedef struct {
-  __IO uint32_t CTRL;      /* SysTick Control and Status Register */
-  __IO uint32_t LOAD;      /* SysTick Reload Value Register       */
-  __IO uint32_t VAL;       /* SysTick Current Value Register      */
-  __I  uint32_t CALIB;     /* SysTick Calibration Register        */
-  } SysTick_Type;
    -
    • - -
  • - Base Address for each peripheral (in case of multiple peripherals - that use the same register layout typedef multiple base addresses are defined). For example: - 
    -#define SysTick_BASE (SCS_BASE + 0x0010)            /* SysTick Base Address */
    -
    • - -
  • - Access Definition for each peripheral (in case of multiple peripherals that use - the same register layout typedef multiple access definitions exist, i.e. LPC_UART0, - LPC_UART2). For Example: - 
    -#define SysTick ((SysTick_Type *) SysTick_BASE)     /* SysTick access definition */
    -
    • -
- -

- These definitions allow to access the peripheral registers from user code with simple assignments like: -

-
SysTick->CTRL = 0;
- -
Optional Features
-

In addition the device.h file may define:

-
    -
  • - #define constants that simplify access to the peripheral registers. - These constant define bit-positions or other specific patterns are that required for the - programming of the peripheral registers. The identifiers used start with - <device abbreviation>_ and <peripheral name>_. - It is recommended to use CAPITAL letters for such #define constants. -
    • -
  • - Functions that perform more complex functions with the peripheral (i.e. status query before - a sending register is accessed). Again these function start with - <device abbreviation>_ and <peripheral name>_. -
    • -
- -

core_cm0.h and core_cm0.c

-

- File core_cm0.h describes the data structures for the Cortex-M0 core peripherals and does - the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers - and core peripherals with efficient functions (defined as static inline). -

-

- File core_cm0.c defines several helper functions that access processor registers. -

-

Together these files implement the Core Peripheral Access Layer for a Cortex-M0.

- -

core_cm3.h and core_cm3.c

-

- File core_cm3.h describes the data structures for the Cortex-M3 core peripherals and does - the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers - and core peripherals with efficient functions (defined as static inline). -

-

- File core_cm3.c defines several helper functions that access processor registers. -

-

Together these files implement the Core Peripheral Access Layer for a Cortex-M3.

- -

startup_device

-

- A template file for startup_device is provided by ARM for each supported - compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific - interrupt handlers. Each interrupt handler is defined as weak function - to an dummy handler. Therefore the interrupt handler can be directly used in application software - without any requirements to adapt the startup_device file. -

-

- The following exception names are fixed and define the start of the vector table for a Cortex-M0: -

-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
- -

- The following exception names are fixed and define the start of the vector table for a Cortex-M3: -

-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
- -

- In the following examples for device specific interrupts are shown: -

-
-; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler         ; Tamper
- -

- Device specific interrupts must have a dummy function that can be overwritten in user code. - Below is an example for this dummy function. -

-
-Default_Handler PROC
-                EXPORT WWDG_IRQHandler   [WEAK]
-                EXPORT PVD_IRQHandler    [WEAK]
-                EXPORT TAMPER_IRQHandler [WEAK]
-                :
-                :
-                WWDG_IRQHandler
-                PVD_IRQHandler
-                TAMPER_IRQHandler
-                :
-                :
-                B .
-                ENDP
- -

- The user application may simply define an interrupt handler function by using the handler name - as shown below. -

-
-void WWDG_IRQHandler(void)
-{
-  :
-  :
-}
- - -

system_device.c

-

- A template file for system_device.c is provided by ARM but adapted by - the silicon vendor to match their actual device. As a minimum requirement - this file must provide a device specific system configuration function and a global variable - that contains the system frequency. It configures the device and initializes typically the - oscillator (PLL) that is part of the microcontroller device. -

-

- The file system_device.c must provide - as a minimum requirement the SystemInit function as shown below. -

- - - - - - - - - - - - - - - - -
Function DefinitionDescription
void SystemInit (void)Setup the microcontroller system. Typically this function configures the - oscillator (PLL) that is part of the microcontroller device. For systems - with variable clock speed it also updates the variable SystemCoreClock.
- SystemInit is called from startup_device file.
void SystemCoreClockUpdate (void)Updates the variable SystemCoreClock and must be called whenever the - core clock is changed during program execution. SystemCoreClockUpdate() - evaluates the clock register settings and calculates the current core clock. -
- -

- Also part of the file system_device.c - is the variable SystemCoreClock which contains the current CPU clock speed shown below. -

- - - - - - - - - - - - -
Variable DefinitionDescription
uint32_t SystemCoreClockContains the system core clock (which is the system clock frequency supplied - to the SysTick timer and the processor core clock). This variable can be - used by the user application to setup the SysTick timer or configure other - parameters. It may also be used by debugger to query the frequency of the - debug timer or configure the trace clock speed.
- SystemCoreClock is initialized with a correct predefined value.

- The compiler must be configured to avoid the removal of this variable in - case that the application program is not using it. It is important for - debug systems that the variable is physically present in memory so that - it can be examined to configure the debugger.
- -

Note

-
    -

  • The above definitions are the minimum requirements for the file - system_device.c. This - file may export more functions or variables that provide a more flexible - configuration of the microcontroller system.

    -
    • -
- - -

Core Peripheral Access Layer

- -

Cortex-M Core Register Access

-

- The following functions are defined in core_cm0.h / core_cm3.h - and provide access to Cortex-M core registers. -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Function DefinitionCoreCore RegisterDescription
void __enable_irq (void)M0, M3PRIMASK = 0Global Interrupt enable (using the instruction CPSIE - i)
void __disable_irq (void)M0, M3PRIMASK = 1Global Interrupt disable (using the instruction - CPSID i)
void __set_PRIMASK (uint32_t value)M0, M3PRIMASK = valueAssign value to Priority Mask Register (using the instruction - MSR)
uint32_t __get_PRIMASK (void)M0, M3return PRIMASKReturn Priority Mask Register (using the instruction - MRS)
void __enable_fault_irq (void)M3FAULTMASK = 0Global Fault exception and Interrupt enable (using the - instruction CPSIE - f)
void __disable_fault_irq (void)M3FAULTMASK = 1Global Fault exception and Interrupt disable (using the - instruction CPSID f)
void __set_FAULTMASK (uint32_t value)M3FAULTMASK = valueAssign value to Fault Mask Register (using the instruction - MSR)
uint32_t __get_FAULTMASK (void)M3return FAULTMASKReturn Fault Mask Register (using the instruction MRS)
void __set_BASEPRI (uint32_t value)M3BASEPRI = valueSet Base Priority (using the instruction MSR)
uiuint32_t __get_BASEPRI (void)M3return BASEPRIReturn Base Priority (using the instruction MRS)
void __set_CONTROL (uint32_t value)M0, M3CONTROL = valueSet CONTROL register value (using the instruction MSR)
uint32_t __get_CONTROL (void)M0, M3return CONTROLReturn Control Register Value (using the instruction - MRS)
void __set_PSP (uint32_t TopOfProcStack)M0, M3PSP = TopOfProcStackSet Process Stack Pointer value (using the instruction - MSR)
uint32_t __get_PSP (void)M0, M3return PSPReturn Process Stack Pointer (using the instruction MRS)
void __set_MSP (uint32_t TopOfMainStack)M0, M3MSP = TopOfMainStackSet Main Stack Pointer (using the instruction MSR)
uint32_t __get_MSP (void)M0, M3return MSPReturn Main Stack Pointer (using the instruction MRS)
- -

Cortex-M Instruction Access

-

- The following functions are defined in core_cm0.h / core_cm3.hand - generate specific Cortex-M instructions. The functions are implemented in the file - core_cm0.c / core_cm3.c. -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameCoreGenerated CPU InstructionDescription
void __NOP (void)M0, M3NOPNo Operation
void __WFI (void)M0, M3WFIWait for Interrupt
void __WFE (void)M0, M3WFEWait for Event
void __SEV (void)M0, M3SEVSet Event
void __ISB (void)M0, M3ISBInstruction Synchronization Barrier
void __DSB (void)M0, M3DSBData Synchronization Barrier
void __DMB (void)M0, M3DMBData Memory Barrier
uint32_t __REV (uint32_t value)M0, M3REVReverse byte order in integer value.
uint32_t __REV16 (uint16_t value)M0, M3REV16Reverse byte order in unsigned short value.
sint32_t __REVSH (sint16_t value)M0, M3REVSHReverse byte order in signed short value with sign extension to integer.
uint32_t __RBIT (uint32_t value)M3RBITReverse bit order of value
uint8_t __LDREXB (uint8_t *addr)M3LDREXBLoad exclusive byte
uint16_t __LDREXH (uint16_t *addr)M3LDREXHLoad exclusive half-word
uint32_t __LDREXW (uint32_t *addr)M3LDREXWLoad exclusive word
uint32_t __STREXB (uint8_t value, uint8_t *addr)M3STREXBStore exclusive byte
uint32_t __STREXB (uint16_t value, uint16_t *addr)M3STREXHStore exclusive half-word
uint32_t __STREXB (uint32_t value, uint32_t *addr)M3STREXWStore exclusive word
void __CLREX (void)M3CLREXRemove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW
- - -

NVIC Access Functions

-

- The CMSIS provides access to the NVIC via the register interface structure and several helper - functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to - identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative - IRQn values are used for processor core exceptions. -

-

- For the IRQn values of core exceptions the file device.h provides - the following enum names. -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Core Exception enum ValueCoreIRQnDescription
NonMaskableInt_IRQnM0, M3-14Cortex-M Non Maskable Interrupt
HardFault_IRQnM0, M3-13Cortex-M Hard Fault Interrupt
MemoryManagement_IRQnM3-12Cortex-M Memory Management Interrupt
BusFault_IRQnM3-11Cortex-M Bus Fault Interrupt
UsageFault_IRQnM3-10Cortex-M Usage Fault Interrupt
SVCall_IRQnM0, M3-5Cortex-M SV Call Interrupt
DebugMonitor_IRQnM3-4Cortex-M Debug Monitor Interrupt
PendSV_IRQnM0, M3-2Cortex-M Pend SV Interrupt
SysTick_IRQnM0, M3-1Cortex-M System Tick Interrupt
- -

The following functions simplify the setup of the NVIC. -The functions are defined as static inline.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NameCoreParameterDescription
void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)M3Priority Grouping ValueSet the Priority Grouping (Groups . Subgroups)
uint32_t NVIC_GetPriorityGrouping (void)M3(void)Get the Priority Grouping (Groups . Subgroups)
void NVIC_EnableIRQ (IRQn_Type IRQn)M0, M3IRQ NumberEnable IRQn
void NVIC_DisableIRQ (IRQn_Type IRQn)M0, M3IRQ NumberDisable IRQn
uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)M0, M3IRQ NumberReturn 1 if IRQn is pending else 0
void NVIC_SetPendingIRQ (IRQn_Type IRQn)M0, M3IRQ NumberSet IRQn Pending
void NVIC_ClearPendingIRQ (IRQn_Type IRQn)M0, M3IRQ NumberClear IRQn Pending Status
uint32_t NVIC_GetActive (IRQn_Type IRQn)M3IRQ NumberReturn 1 if IRQn is active else 0
void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)M0, M3IRQ Number, PrioritySet Priority for IRQn
- (not threadsafe for Cortex-M0)
uint32_t NVIC_GetPriority (IRQn_Type IRQn)M0, M3IRQ NumberGet Priority for IRQn
uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)M3IRQ Number, Priority Group, Preemptive Priority, Sub PriorityEncode priority for given group, preemptive and sub priority
NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)M3IRQ Number, Priority, pointer to Priority Group, pointer to Preemptive Priority, pointer to Sub PriorityDeccode given priority to group, preemptive and sub priority
void NVIC_SystemReset (void)M0, M3(void)Resets the System
-

Note

-
    -

  • The processor exceptions have negative enum values. Device specific interrupts - have positive enum values and start with 0. The values are defined in - device.h file. -

    -
    • -

  • The values for PreemptPriority and SubPriority - used in functions NVIC_EncodePriority and NVIC_DecodePriority - depend on the available __NVIC_PRIO_BITS implemented in the NVIC. -

    -
    • -
- - -

SysTick Configuration Function

- -

The following function is used to configure the SysTick timer and start the -SysTick interrupt.

- - - - - - - - - - - - - - -
NameParameterDescription
uint32_t SysTickConfig - (uint32_t ticks)ticks is SysTick counter reload valueSetup the SysTick timer and enable the SysTick interrupt. After this - call the SysTick timer creates interrupts with the specified time - interval.
-
- Return: 0 when successful, 1 on failure.
-
- - -

Cortex-M3 ITM Debug Access

- -

The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that -provides together with the Serial Viewer Output trace capabilities for the -microcontroller system. The ITM has 32 communication channels; two ITM -communication channels are used by CMSIS to output the following information:

-
    -
  • ITM Channel 0: implements the ITM_SendChar function - which can be used for printf-style output via the debug interface.
    • -
  • ITM Channel 31: is reserved for the RTOS kernel and can be used for - kernel awareness debugging.
    • -
-

Note

-
    -

  • The ITM channel 31 is selected for the RTOS kernel since some kernels - may use the Privileged level for program execution. ITM - channels have 4 groups with 8 channels each, whereby each group can be - configured for access rights in the Unprivileged level. The ITM channel 0 - may be therefore enabled for the user task whereas ITM channel 31 may be - accessible only in Privileged level from the RTOS kernel itself.

    -
    • -
- -

The prototype of the ITM_SendChar routine is shown in the -table below.

- - - - - - - - - - - - - - -
NameParameterDescription
void uint32_t ITM_SendChar(uint32_t chr)character to outputThe function outputs a character via the ITM channel 0. The - function returns when no debugger is connected that has booked the - output. It is blocking when a debugger is connected, but the - previous character send is not transmitted.

- Return: the input character 'chr'.
- -

- Example for the usage of the ITM Channel 31 for RTOS Kernels: -

-
-  // check if debugger connected and ITM channel enabled for tracing
-  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
-  (ITM->TCR & ITM_TCR_ITMENA) &&
-  (ITM->TER & (1UL << 31))) {
-    // transmit trace data
-    while (ITM->PORT31_U32 == 0);
-    ITM->PORT[31].u8 = task_id;      // id of next task
-    while (ITM->PORT[31].u32 == 0);
-    ITM->PORT[31].u32 = task_status; // status information
-  }
- - -

Cortex-M3 additional Debug Access

- -

CMSIS provides additional debug functions to enlarge the Cortex-M3 Debug Access. -Data can be transmitted via a certain global buffer variable towards the target system.

- -

The buffer variable and the prototypes of the additional functions are shown in the -table below.

- - - - - - - - - - - - - - - - - - - - - - - - -
NameParameterDescription
extern volatile int ITM_RxBuffer Buffer to transmit data towards debug system.

- Value 0x5AA55AA5 indicates that buffer is empty.
int ITM_ReceiveChar (void)noneThe nonblocking functions returns the character stored in - ITM_RxBuffer.

- Return: -1 indicates that no character was received.
int ITM_CheckChar (void)noneThe function checks if a character is available in ITM_RxBuffer.

- Return: 1 indicates that a character is available, 0 indicates that - no character is available.
- - -

CMSIS Example

-

- The following section shows a typical example for using the CMSIS layer in user applications. - The example is based on a STM32F10x Device. -

-
-#include "stm32f10x.h"
-
-volatile uint32_t msTicks;                       /* timeTicks counter */
-
-void SysTick_Handler(void) {
-  msTicks++;                                     /* increment timeTicks counter */
-}
-
-__INLINE static void Delay (uint32_t dlyTicks) {
-  uint32_t curTicks = msTicks;
-
-  while ((msTicks - curTicks) < dlyTicks);
-}
-
-__INLINE static void LED_Config(void) {
-  ;                                              /* Configure the LEDs */
-}
-
-__INLINE static void LED_On (uint32_t led) {
-  ;                                              /* Turn On  LED */
-}
-
-__INLINE static void LED_Off (uint32_t led) {
-  ;                                              /* Turn Off LED */
-}
-
-int main (void) {
-  if (SysTick_Config (SystemCoreClock / 1000)) { /* Setup SysTick for 1 msec interrupts */
-    ;                                            /* Handle Error */
-    while (1);
-  }
-  
-  LED_Config();                                  /* configure the LEDs */                            
- 
-  while(1) {
-    LED_On (0x100);                              /* Turn  on the LED   */
-    Delay (100);                                 /* delay  100 Msec    */
-    LED_Off (0x100);                             /* Turn off the LED   */
-    Delay (100);                                 /* delay  100 Msec    */
-  }
-}
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Release -Notes for STM32F10x Standard Peripherals Library Drivers -(StdPeriph_Driver)

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Copyright 2011 STMicroelectronics

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Contents

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  1. STM32F10x Standard Peripherals Library -Drivers update History
    2. -
  2. License
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STM32F10x Standard -Peripherals Library Drivers  update History


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V3.5.0 / 11-March-2011

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Main -Changes

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  • stm32f10x_can.h/.c files:
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    • Add 5 new functions
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      • 3 -new functions controlling the counter errors: CAN_GetLastErrorCode(), -CAN_GetReceiveErrorCounter() and CAN_GetLSBTransmitErrorCounter().
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      • 1 new function to select the CAN operating mode: CAN_OperatingModeRequest().
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      • 1 new function to support CAN TT mode: CAN_TTComModeCmd().
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    • CAN_TransmitStatus() function updated to support all CAN transmit intermediate states
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  • stm32f10x_i2c.h/.c files:
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    • Add 1 new function:
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      • I2C_NACKPositionConfig(): -This function configures the same bit (POS) as I2C_PECPositionConfig() -but is intended to be used in I2C mode while I2C_PECPositionConfig() is -intended to used in SMBUS mode.
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  • stm32f10x_tim.h/.c files:
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    • Change the TIM_DMABurstLength_xBytes definitions to TIM_DMABurstLength_xTansfers
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3.4.0 -- 10/15/2010

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  1. General
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  • Add support for STM32F10x High-density value line devices.
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  1. STM32F10x_StdPeriph_Driver
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  • stm32f10x_bkp.h/.c
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    • Delete BKP registers definition from stm32f10x_bkp.c and use defines within stm32f10x.h file.
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  • stm32f10x_can.h/.c
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    • Delete CAN registers definition from stm32f10x_can.c and use defines within stm32f10x.h file.
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    • Update the wording of some defines and Asserts macro.
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    • CAN_GetFlagStatus() -and CAN_ClearFlag() functions: updated to support new flags (were not -supported in previous version). These flags are:  CAN_FLAG_RQCP0, -CAN_FLAG_RQCP1, CAN_FLAG_RQCP2, CAN_FLAG_FMP1, CAN_FLAG_FF1, -CAN_FLAG_FOV1, CAN_FLAG_FMP0, CAN_FLAG_FF0,   CAN_FLAG_FOV0, -CAN_FLAG_WKU, CAN_FLAG_SLAK and CAN_FLAG_LEC.
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    • CAN_GetITStatus() -function: add a check of the interrupt enable bit before getting the -status of corresponding interrupt pending bit.
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    • CAN_ClearITPendingBit() function: correct the procedure to clear the interrupt pending bit.
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  • stm32f10x_crc.h/.c
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    • Delete CRC registers definition from stm32f10x_crc.c and use defines within stm32f10x.h file.
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  • stm32f10x_dac.h/.c
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    • Delete DAC registers definition from stm32f10x_dac.c and use defines within stm32f10x.h file.
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  • stm32f10x_dbgmcu.h/.c
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    • Delete DBGMCU registers definition from stm32f10x_dbgmcu.c and use defines within stm32f10x.h file.
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  • stm32f10x_dma.h/.c
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    • Delete DMA registers definition from stm32f10x_dma.c and use defines within stm32f10x.h file.
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    • Add new function "void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);"
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  • stm32f10x_flash.h/.c
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    • FLASH functions (Erase and Program) updated to always clear the "PG", "MER" and "PER" bits even in case of TimeOut Error.
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  • stm32f10x_fsmc.h/.c
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    • Add new member "FSMC_AsynchronousWait" in "FSMC_NORSRAMInitTypeDef" structure.
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  • stm32f10x_gpio.h/.c
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    • GPIO_PinRemapConfig() function: add new values for GPIO_Remap parameter, to support new remap for TIM6, TIM7 and DAC DMA requests, TIM12 and DAC Triggers / DMA2_Channel5 Interrupt mapping.
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  • stm32f10x_pwr.h/.c
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    • Delete PWR registers definition from stm32f10x_pwr.c and use defines within stm32f10x.h and core_cm3.h files.
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  • stm32f10x_rtc.h/.c
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      -
    • Delete RTC registers definition from stm32f10x_rtc.c and use defines within stm32f10x.h file.
      • -
    -
  • stm32f10x_spi.h/.c
    • -
      -
    • Add new definition for I2S Audio Clock frequencies "I2S_AudioFreq_192k".
      • -
    -
  • stm32f10x_tim.h/.c
    • -
    • Add new definition for TIM Input Capture Polarity "TIM_ICPolarity_BothEdge".
    - -
- -

3.3.0 -- 04/16/2010

- -
  1. General
-
  • Add support for STM32F10x XL-density devices.
  • I2C driver: events description and management enhancement.
-
  1. STM32F10x_StdPeriph_Driver
-
  • stm32f10x_dbgmcu.h/.c
    • DBGMCU_Config() function: add new values DBGMCU_TIMx_STOP (x: 9..14) for DBGMCU_Periph parameter.
  • stm32f10x_flash.h/.c: -updated to support Bank2 of XL-density devices (up to 1MByte of Flash -memory). For more details, refer to the description provided within -stm32f10x_flash.c file.
  • stm32f10x_gpio.h/.c
    • GPIO_PinRemapConfig() function: add new values for GPIO_Remap parameter, to support new remap for FSMC_NADV pin and TIM9..11,13,14.
  • stm32f10x_i2c.h/.c: I2C events description and management enhancement.
    • I2C_CheckEvent() -function: updated to check whether the last event contains the -I2C_EVENT  (instead of check whether the last event is equal to -I2C_EVENT)
    • Add -detailed description of I2C events and how to manage them using the -functions provided by this driver. For more information, refer to -stm32f10x_i2c.h and stm32f10x_i2c.c files.
  • stm32f10x_rcc.h/.c: updated to support TIM9..TIM14 APB clock and reset configuration
  • stm32f10x_tim.h/.c: updated to support new Timers TIM9..TIM14.
  • stm32f10x_sdio.h: 
    • SDIO_SetSDIOReadWaitMode() function: correct values of SDIO_ReadWaitMode parameter
      change
        -#define -SDIO_ReadWaitMode_CLK               -  ((uint32_t)0x00000000)
        #define -SDIO_ReadWaitMode_DATA2             -((uint32_t)0x00000001)
      by
        #define -SDIO_ReadWaitMode_CLK               -  ((uint32_t)0x00000001)
        #define -SDIO_ReadWaitMode_DATA2             -((uint32_t)0x00000000)
-

3.2.0 -- 03/01/2010

-
    -
  1. General
    2. -
-
    - -
  • Add support -for STM32 Low-density Value line (STM32F100x4/6) and -Medium-density Value line (STM32F100x8/B) devices.
    • -
  • Almost -peripherals drivers were updated to support Value -line devices features
    • -
  • Drivers limitations fix and enhancements.
    • - -
-
    -
  1. STM32F10x_StdPeriph_Driver
    2. -
-
    -
  • Add new -firmware driver for CEC peripheral: stm32f10x_cec.h and stm32f10x_cec.c
    • -
  • Timers drivers stm32f10x_tim.h/.c: add support for new General Purpose Timers: TIM15, TIM16 and TIM17.
    • -
  • RCC driver: add support for new Value peripherals: HDMI-CEC, TIM15, TIM16 and TIM17.
    • -
  • GPIO driver: add new remap parameters for TIM1, TIM15, TIM16, TIM17 and HDMI-CEC: GPIO_Remap_TIM1_DMA, GPIO_Remap_TIM15, GPIO_Remap_TIM16, GPIO_Remap_TIM17, GPIO_Remap_CEC.
    • -
  • USART -driver: add support for Oversampling by 8 mode and onebit method. 2 -functions has been added: USART_OverSampling8Cmd() and -USART_OneBitMethodCmd().
    -
    • -
  • DAC -driver: add new functions handling the DAC under run feature: -DAC_ITConfig(), DAC_GetFlagStatus(), DAC_ClearFlag(), DAC_GetITStatus() -and DAC_ClearITPendingBit().
    • -
  • DBGMCU driver: add new parameters for TIM15, TIM16 and TIM17: DBGMCU_TIM15_STOP, DBGMCU_TIM16_STOP, DBGMCU_TIM17_STOP.
    -
    • -
  • FLASH -driver: the FLASH_EraseOptionBytes() function updated. This is now just -erasing the option bytes without modifying the RDP status either -enabled or disabled.
    • -
  • PWR -driver: the PWR_EnterSTOPMode() function updated. When woken up from -STOP mode, this function resets again the SLEEPDEEP bit in the -Cortex-M3 System Control register to allow Sleep mode entering.
    • - - -
-

License

-

The -enclosed firmware and all the related documentation are not covered by -a License Agreement, if you need such License you can contact your -local STMicroelectronics office.

-

THE -PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO -SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR -ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY -CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY -CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH -THEIR PRODUCTS.

-

 

-
-
-

For -complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers -visit www.st.com/STM32

-
-

-
-
-

 

-
- \ No newline at end of file diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h deleted file mode 100644 index 7d401ca9b..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h +++ /dev/null @@ -1,220 +0,0 @@ -/** - ****************************************************************************** - * @file misc.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the miscellaneous - * firmware library functions (add-on to CMSIS functions). - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MISC_H -#define __MISC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup MISC - * @{ - */ - -/** @defgroup MISC_Exported_Types - * @{ - */ - -/** - * @brief NVIC Init Structure definition - */ - -typedef struct -{ - uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. - This parameter can be a value of @ref IRQn_Type - (For the complete STM32 Devices IRQ Channels list, please - refer to stm32f10x.h file) */ - - uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel - specified in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref NVIC_Priority_Table */ - - uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified - in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref NVIC_Priority_Table */ - - FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel - will be enabled or disabled. - This parameter can be set either to ENABLE or DISABLE */ -} NVIC_InitTypeDef; - -/** - * @} - */ - -/** @defgroup NVIC_Priority_Table - * @{ - */ - -/** -@code - The table below gives the allowed values of the pre-emption priority and subpriority according - to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function - ============================================================================================================================ - NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - ============================================================================================================================ - NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority - | | | 4 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority - | | | 3 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - | | | 2 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - | | | 1 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority - | | | 0 bits for subpriority - ============================================================================================================================ -@endcode -*/ - -/** - * @} - */ - -/** @defgroup MISC_Exported_Constants - * @{ - */ - -/** @defgroup Vector_Table_Base - * @{ - */ - -#define NVIC_VectTab_RAM ((uint32_t)0x20000000) -#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) -#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ - ((VECTTAB) == NVIC_VectTab_FLASH)) -/** - * @} - */ - -/** @defgroup System_Low_Power - * @{ - */ - -#define NVIC_LP_SEVONPEND ((uint8_t)0x10) -#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) -#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) -#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ - ((LP) == NVIC_LP_SLEEPDEEP) || \ - ((LP) == NVIC_LP_SLEEPONEXIT)) -/** - * @} - */ - -/** @defgroup Preemption_Priority_Group - * @{ - */ - -#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ - -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ - ((GROUP) == NVIC_PriorityGroup_1) || \ - ((GROUP) == NVIC_PriorityGroup_2) || \ - ((GROUP) == NVIC_PriorityGroup_3) || \ - ((GROUP) == NVIC_PriorityGroup_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) - -/** - * @} - */ - -/** @defgroup SysTick_clock_source - * @{ - */ - -#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) -#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ - ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup MISC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup MISC_Exported_Functions - * @{ - */ - -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); - -#ifdef __cplusplus -} -#endif - -#endif /* __MISC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h deleted file mode 100644 index d1b2653a6..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h +++ /dev/null @@ -1,483 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_adc.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the ADC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_ADC_H -#define __STM32F10x_ADC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/** @defgroup ADC_Exported_Types - * @{ - */ - -/** - * @brief ADC Init structure definition - */ - -typedef struct -{ - uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or - dual mode. - This parameter can be a value of @ref ADC_mode */ - - FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in - Scan (multichannels) or Single (one channel) mode. - This parameter can be set to ENABLE or DISABLE */ - - FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in - Continuous or Single mode. - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog - to digital conversion of regular channels. This parameter - can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ - - uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. - This parameter can be a value of @ref ADC_data_align */ - - uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted - using the sequencer for regular channel group. - This parameter must range from 1 to 16. */ -}ADC_InitTypeDef; -/** - * @} - */ - -/** @defgroup ADC_Exported_Constants - * @{ - */ - -#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ - ((PERIPH) == ADC2) || \ - ((PERIPH) == ADC3)) - -#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ - ((PERIPH) == ADC3)) - -/** @defgroup ADC_mode - * @{ - */ - -#define ADC_Mode_Independent ((uint32_t)0x00000000) -#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) -#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) -#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) -#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) -#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) -#define ADC_Mode_RegSimult ((uint32_t)0x00060000) -#define ADC_Mode_FastInterl ((uint32_t)0x00070000) -#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) -#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) - -#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ - ((MODE) == ADC_Mode_RegInjecSimult) || \ - ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \ - ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \ - ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \ - ((MODE) == ADC_Mode_InjecSimult) || \ - ((MODE) == ADC_Mode_RegSimult) || \ - ((MODE) == ADC_Mode_FastInterl) || \ - ((MODE) == ADC_Mode_SlowInterl) || \ - ((MODE) == ADC_Mode_AlterTrig)) -/** - * @} - */ - -/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion - * @{ - */ - -#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */ - -#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */ -#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */ - -#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */ - -#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ - ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_None) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3)) -/** - * @} - */ - -/** @defgroup ADC_data_align - * @{ - */ - -#define ADC_DataAlign_Right ((uint32_t)0x00000000) -#define ADC_DataAlign_Left ((uint32_t)0x00000800) -#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ - ((ALIGN) == ADC_DataAlign_Left)) -/** - * @} - */ - -/** @defgroup ADC_channels - * @{ - */ - -#define ADC_Channel_0 ((uint8_t)0x00) -#define ADC_Channel_1 ((uint8_t)0x01) -#define ADC_Channel_2 ((uint8_t)0x02) -#define ADC_Channel_3 ((uint8_t)0x03) -#define ADC_Channel_4 ((uint8_t)0x04) -#define ADC_Channel_5 ((uint8_t)0x05) -#define ADC_Channel_6 ((uint8_t)0x06) -#define ADC_Channel_7 ((uint8_t)0x07) -#define ADC_Channel_8 ((uint8_t)0x08) -#define ADC_Channel_9 ((uint8_t)0x09) -#define ADC_Channel_10 ((uint8_t)0x0A) -#define ADC_Channel_11 ((uint8_t)0x0B) -#define ADC_Channel_12 ((uint8_t)0x0C) -#define ADC_Channel_13 ((uint8_t)0x0D) -#define ADC_Channel_14 ((uint8_t)0x0E) -#define ADC_Channel_15 ((uint8_t)0x0F) -#define ADC_Channel_16 ((uint8_t)0x10) -#define ADC_Channel_17 ((uint8_t)0x11) - -#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) -#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) - -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ - ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \ - ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \ - ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \ - ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \ - ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \ - ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \ - ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \ - ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17)) -/** - * @} - */ - -/** @defgroup ADC_sampling_time - * @{ - */ - -#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) -#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) -#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) -#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) -#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) -#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) -#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) -#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) -#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \ - ((TIME) == ADC_SampleTime_7Cycles5) || \ - ((TIME) == ADC_SampleTime_13Cycles5) || \ - ((TIME) == ADC_SampleTime_28Cycles5) || \ - ((TIME) == ADC_SampleTime_41Cycles5) || \ - ((TIME) == ADC_SampleTime_55Cycles5) || \ - ((TIME) == ADC_SampleTime_71Cycles5) || \ - ((TIME) == ADC_SampleTime_239Cycles5)) -/** - * @} - */ - -/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion - * @{ - */ - -#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */ - -#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */ -#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */ -#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */ - -#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */ -#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */ -#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */ -#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */ -#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */ - -#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4)) -/** - * @} - */ - -/** @defgroup ADC_injected_channel_selection - * @{ - */ - -#define ADC_InjectedChannel_1 ((uint8_t)0x14) -#define ADC_InjectedChannel_2 ((uint8_t)0x18) -#define ADC_InjectedChannel_3 ((uint8_t)0x1C) -#define ADC_InjectedChannel_4 ((uint8_t)0x20) -#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ - ((CHANNEL) == ADC_InjectedChannel_2) || \ - ((CHANNEL) == ADC_InjectedChannel_3) || \ - ((CHANNEL) == ADC_InjectedChannel_4)) -/** - * @} - */ - -/** @defgroup ADC_analog_watchdog_selection - * @{ - */ - -#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) -#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) -#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) -#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) -#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) -#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) -#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) - -#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_None)) -/** - * @} - */ - -/** @defgroup ADC_interrupts_definition - * @{ - */ - -#define ADC_IT_EOC ((uint16_t)0x0220) -#define ADC_IT_AWD ((uint16_t)0x0140) -#define ADC_IT_JEOC ((uint16_t)0x0480) - -#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00)) - -#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ - ((IT) == ADC_IT_JEOC)) -/** - * @} - */ - -/** @defgroup ADC_flags_definition - * @{ - */ - -#define ADC_FLAG_AWD ((uint8_t)0x01) -#define ADC_FLAG_EOC ((uint8_t)0x02) -#define ADC_FLAG_JEOC ((uint8_t)0x04) -#define ADC_FLAG_JSTRT ((uint8_t)0x08) -#define ADC_FLAG_STRT ((uint8_t)0x10) -#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00)) -#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \ - ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \ - ((FLAG) == ADC_FLAG_STRT)) -/** - * @} - */ - -/** @defgroup ADC_thresholds - * @{ - */ - -#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) - -/** - * @} - */ - -/** @defgroup ADC_injected_offset - * @{ - */ - -#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) - -/** - * @} - */ - -/** @defgroup ADC_injected_length - * @{ - */ - -#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) - -/** - * @} - */ - -/** @defgroup ADC_injected_rank - * @{ - */ - -#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) - -/** - * @} - */ - - -/** @defgroup ADC_regular_length - * @{ - */ - -#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) -/** - * @} - */ - -/** @defgroup ADC_regular_rank - * @{ - */ - -#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) - -/** - * @} - */ - -/** @defgroup ADC_regular_discontinuous_mode_number - * @{ - */ - -#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup ADC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Exported_Functions - * @{ - */ - -void ADC_DeInit(ADC_TypeDef* ADCx); -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); -void ADC_ResetCalibration(ADC_TypeDef* ADCx); -FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); -void ADC_StartCalibration(ADC_TypeDef* ADCx); -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); -void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); -uint32_t ADC_GetDualModeConversionValue(void); -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); -void ADC_TempSensorVrefintCmd(FunctionalState NewState); -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_ADC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h deleted file mode 100644 index b620753ef..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h +++ /dev/null @@ -1,195 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_bkp.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the BKP firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_BKP_H -#define __STM32F10x_BKP_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup BKP - * @{ - */ - -/** @defgroup BKP_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Exported_Constants - * @{ - */ - -/** @defgroup Tamper_Pin_active_level - * @{ - */ - -#define BKP_TamperPinLevel_High ((uint16_t)0x0000) -#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) -#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \ - ((LEVEL) == BKP_TamperPinLevel_Low)) -/** - * @} - */ - -/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin - * @{ - */ - -#define BKP_RTCOutputSource_None ((uint16_t)0x0000) -#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) -#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) -#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) -#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \ - ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \ - ((SOURCE) == BKP_RTCOutputSource_Alarm) || \ - ((SOURCE) == BKP_RTCOutputSource_Second)) -/** - * @} - */ - -/** @defgroup Data_Backup_Register - * @{ - */ - -#define BKP_DR1 ((uint16_t)0x0004) -#define BKP_DR2 ((uint16_t)0x0008) -#define BKP_DR3 ((uint16_t)0x000C) -#define BKP_DR4 ((uint16_t)0x0010) -#define BKP_DR5 ((uint16_t)0x0014) -#define BKP_DR6 ((uint16_t)0x0018) -#define BKP_DR7 ((uint16_t)0x001C) -#define BKP_DR8 ((uint16_t)0x0020) -#define BKP_DR9 ((uint16_t)0x0024) -#define BKP_DR10 ((uint16_t)0x0028) -#define BKP_DR11 ((uint16_t)0x0040) -#define BKP_DR12 ((uint16_t)0x0044) -#define BKP_DR13 ((uint16_t)0x0048) -#define BKP_DR14 ((uint16_t)0x004C) -#define BKP_DR15 ((uint16_t)0x0050) -#define BKP_DR16 ((uint16_t)0x0054) -#define BKP_DR17 ((uint16_t)0x0058) -#define BKP_DR18 ((uint16_t)0x005C) -#define BKP_DR19 ((uint16_t)0x0060) -#define BKP_DR20 ((uint16_t)0x0064) -#define BKP_DR21 ((uint16_t)0x0068) -#define BKP_DR22 ((uint16_t)0x006C) -#define BKP_DR23 ((uint16_t)0x0070) -#define BKP_DR24 ((uint16_t)0x0074) -#define BKP_DR25 ((uint16_t)0x0078) -#define BKP_DR26 ((uint16_t)0x007C) -#define BKP_DR27 ((uint16_t)0x0080) -#define BKP_DR28 ((uint16_t)0x0084) -#define BKP_DR29 ((uint16_t)0x0088) -#define BKP_DR30 ((uint16_t)0x008C) -#define BKP_DR31 ((uint16_t)0x0090) -#define BKP_DR32 ((uint16_t)0x0094) -#define BKP_DR33 ((uint16_t)0x0098) -#define BKP_DR34 ((uint16_t)0x009C) -#define BKP_DR35 ((uint16_t)0x00A0) -#define BKP_DR36 ((uint16_t)0x00A4) -#define BKP_DR37 ((uint16_t)0x00A8) -#define BKP_DR38 ((uint16_t)0x00AC) -#define BKP_DR39 ((uint16_t)0x00B0) -#define BKP_DR40 ((uint16_t)0x00B4) -#define BKP_DR41 ((uint16_t)0x00B8) -#define BKP_DR42 ((uint16_t)0x00BC) - -#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \ - ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \ - ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \ - ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \ - ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \ - ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \ - ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \ - ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \ - ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \ - ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \ - ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \ - ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \ - ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \ - ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42)) - -#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup BKP_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Exported_Functions - * @{ - */ - -void BKP_DeInit(void); -void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); -void BKP_TamperPinCmd(FunctionalState NewState); -void BKP_ITConfig(FunctionalState NewState); -void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); -void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); -void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); -uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); -FlagStatus BKP_GetFlagStatus(void); -void BKP_ClearFlag(void); -ITStatus BKP_GetITStatus(void); -void BKP_ClearITPendingBit(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_BKP_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h deleted file mode 100644 index 648f747cd..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h +++ /dev/null @@ -1,697 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_can.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the CAN firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_CAN_H -#define __STM32F10x_CAN_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CAN - * @{ - */ - -/** @defgroup CAN_Exported_Types - * @{ - */ - -#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ - ((PERIPH) == CAN2)) - -/** - * @brief CAN init structure definition - */ - -typedef struct -{ - uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. - It ranges from 1 to 1024. */ - - uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. - This parameter can be a value of - @ref CAN_operating_mode */ - - uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta - the CAN hardware is allowed to lengthen or - shorten a bit to perform resynchronization. - This parameter can be a value of - @ref CAN_synchronisation_jump_width */ - - uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit - Segment 1. This parameter can be a value of - @ref CAN_time_quantum_in_bit_segment_1 */ - - uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit - Segment 2. - This parameter can be a value of - @ref CAN_time_quantum_in_bit_segment_2 */ - - FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered - communication mode. This parameter can be set - either to ENABLE or DISABLE. */ - - FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off - management. This parameter can be set either - to ENABLE or DISABLE. */ - - FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. - This parameter can be set either to ENABLE or - DISABLE. */ - - FunctionalState CAN_NART; /*!< Enable or disable the no-automatic - retransmission mode. This parameter can be - set either to ENABLE or DISABLE. */ - - FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. - This parameter can be set either to ENABLE - or DISABLE. */ - - FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. - This parameter can be set either to ENABLE - or DISABLE. */ -} CAN_InitTypeDef; - -/** - * @brief CAN filter init structure definition - */ - -typedef struct -{ - uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit - configuration, first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit - configuration, second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, - according to the mode (MSBs for a 32-bit configuration, - first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, - according to the mode (LSBs for a 32-bit configuration, - second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. - This parameter can be a value of @ref CAN_filter_FIFO */ - - uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ - - uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. - This parameter can be a value of @ref CAN_filter_mode */ - - uint8_t CAN_FilterScale; /*!< Specifies the filter scale. - This parameter can be a value of @ref CAN_filter_scale */ - - FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. - This parameter can be set either to ENABLE or DISABLE. */ -} CAN_FilterInitTypeDef; - -/** - * @brief CAN Tx message structure definition - */ - -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /*!< Specifies the type of identifier for the message that - will be transmitted. This parameter can be a value - of @ref CAN_identifier_type */ - - uint8_t RTR; /*!< Specifies the type of frame for the message that will - be transmitted. This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /*!< Specifies the length of the frame that will be - transmitted. This parameter can be a value between - 0 to 8 */ - - uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 - to 0xFF. */ -} CanTxMsg; - -/** - * @brief CAN Rx message structure definition - */ - -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /*!< Specifies the type of identifier for the message that - will be received. This parameter can be a value of - @ref CAN_identifier_type */ - - uint8_t RTR; /*!< Specifies the type of frame for the received message. - This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /*!< Specifies the length of the frame that will be received. - This parameter can be a value between 0 to 8 */ - - uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to - 0xFF. */ - - uint8_t FMI; /*!< Specifies the index of the filter the message stored in - the mailbox passes through. This parameter can be a - value between 0 to 0xFF */ -} CanRxMsg; - -/** - * @} - */ - -/** @defgroup CAN_Exported_Constants - * @{ - */ - -/** @defgroup CAN_sleep_constants - * @{ - */ - -#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ -#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */ - -/** - * @} - */ - -/** @defgroup CAN_Mode - * @{ - */ - -#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ -#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ -#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ -#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ - -#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \ - ((MODE) == CAN_Mode_LoopBack)|| \ - ((MODE) == CAN_Mode_Silent) || \ - ((MODE) == CAN_Mode_Silent_LoopBack)) -/** - * @} - */ - - -/** - * @defgroup CAN_Operating_Mode - * @{ - */ -#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */ -#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */ -#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */ - - -#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ - ((MODE) == CAN_OperatingMode_Normal)|| \ - ((MODE) == CAN_OperatingMode_Sleep)) -/** - * @} - */ - -/** - * @defgroup CAN_Mode_Status - * @{ - */ - -#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ -#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */ - - -/** - * @} - */ - -/** @defgroup CAN_synchronisation_jump_width - * @{ - */ - -#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ - -#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ - ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_1 - * @{ - */ - -#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ -#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ -#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ -#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ -#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ -#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ -#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ -#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ -#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ -#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ -#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ -#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ -#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ - -#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_2 - * @{ - */ - -#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ -#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ -#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ -#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ -#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ - -#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) - -/** - * @} - */ - -/** @defgroup CAN_clock_prescaler - * @{ - */ - -#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) - -/** - * @} - */ - -/** @defgroup CAN_filter_number - * @{ - */ -#ifndef STM32F10X_CL - #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13) -#else - #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) -#endif /* STM32F10X_CL */ -/** - * @} - */ - -/** @defgroup CAN_filter_mode - * @{ - */ - -#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */ -#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ - -#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ - ((MODE) == CAN_FilterMode_IdList)) -/** - * @} - */ - -/** @defgroup CAN_filter_scale - * @{ - */ - -#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ -#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ - -#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ - ((SCALE) == CAN_FilterScale_32bit)) - -/** - * @} - */ - -/** @defgroup CAN_filter_FIFO - * @{ - */ - -#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ -#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ - ((FIFO) == CAN_FilterFIFO1)) -/** - * @} - */ - -/** @defgroup Start_bank_filter_for_slave_CAN - * @{ - */ -#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) -/** - * @} - */ - -/** @defgroup CAN_Tx - * @{ - */ - -#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) -#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) -#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) -#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) - -/** - * @} - */ - -/** @defgroup CAN_identifier_type - * @{ - */ - -#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ -#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */ -#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ - ((IDTYPE) == CAN_Id_Extended)) -/** - * @} - */ - -/** @defgroup CAN_remote_transmission_request - * @{ - */ - -#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ -#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */ -#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) - -/** - * @} - */ - -/** @defgroup CAN_transmit_constants - * @{ - */ - -#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */ -#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ -#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ -#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */ - -/** - * @} - */ - -/** @defgroup CAN_receive_FIFO_number_constants - * @{ - */ - -#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ - -#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) - -/** - * @} - */ - -/** @defgroup CAN_sleep_constants - * @{ - */ - -#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ -#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ - -/** - * @} - */ - -/** @defgroup CAN_wake_up_constants - * @{ - */ - -#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ -#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ - -/** - * @} - */ - -/** - * @defgroup CAN_Error_Code_constants - * @{ - */ - -#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ -#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ -#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ -#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ -#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ -#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ -#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ -#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ - - -/** - * @} - */ - -/** @defgroup CAN_flags - * @{ - */ -/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() - and CAN_ClearFlag() functions. */ -/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */ - -/* Transmit Flags */ -#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ -#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ -#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ - -/* Receive Flags */ -#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */ -#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */ -#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */ -#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */ -#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */ -#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */ - -/* Operating Mode Flags */ -#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ -#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ -/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. - In this case the SLAK bit can be polled.*/ - -/* Error Flags */ -#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */ -#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */ -#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ -#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ - -#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \ - ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \ - ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \ - ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \ - ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \ - ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \ - ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \ - ((FLAG) == CAN_FLAG_SLAK )) - -#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \ - ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \ - ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\ - ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \ - ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK)) -/** - * @} - */ - - -/** @defgroup CAN_interrupts - * @{ - */ - - - -#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ - -/* Receive Interrupts */ -#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/ -#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/ -#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/ -#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/ -#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/ -#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/ - -/* Operating Mode Interrupts */ -#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ -#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ - -/* Error Interrupts */ -#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ -#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ -#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ -#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ -#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ - -/* Flags named as Interrupts : kept only for FW compatibility */ -#define CAN_IT_RQCP0 CAN_IT_TME -#define CAN_IT_RQCP1 CAN_IT_TME -#define CAN_IT_RQCP2 CAN_IT_TME - - -#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ - ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ - ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) - -#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ - ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) - -/** - * @} - */ - -/** @defgroup CAN_Legacy - * @{ - */ -#define CANINITFAILED CAN_InitStatus_Failed -#define CANINITOK CAN_InitStatus_Success -#define CAN_FilterFIFO0 CAN_Filter_FIFO0 -#define CAN_FilterFIFO1 CAN_Filter_FIFO1 -#define CAN_ID_STD CAN_Id_Standard -#define CAN_ID_EXT CAN_Id_Extended -#define CAN_RTR_DATA CAN_RTR_Data -#define CAN_RTR_REMOTE CAN_RTR_Remote -#define CANTXFAILE CAN_TxStatus_Failed -#define CANTXOK CAN_TxStatus_Ok -#define CANTXPENDING CAN_TxStatus_Pending -#define CAN_NO_MB CAN_TxStatus_NoMailBox -#define CANSLEEPFAILED CAN_Sleep_Failed -#define CANSLEEPOK CAN_Sleep_Ok -#define CANWAKEUPFAILED CAN_WakeUp_Failed -#define CANWAKEUPOK CAN_WakeUp_Ok - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup CAN_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CAN_Exported_Functions - * @{ - */ -/* Function used to set the CAN configuration to the default reset state *****/ -void CAN_DeInit(CAN_TypeDef* CANx); - -/* Initialization and Configuration functions *********************************/ -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); -void CAN_SlaveStartBank(uint8_t CAN_BankNumber); -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); -void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); - -/* Transmit functions *********************************************************/ -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); - -/* Receive functions **********************************************************/ -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); - - -/* Operation modes functions **************************************************/ -uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); -uint8_t CAN_Sleep(CAN_TypeDef* CANx); -uint8_t CAN_WakeUp(CAN_TypeDef* CANx); - -/* Error management functions *************************************************/ -uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); - -/* Interrupts and flags management functions **********************************/ -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_CAN_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h deleted file mode 100644 index a3f8fc785..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h +++ /dev/null @@ -1,210 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_cec.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the CEC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_CEC_H -#define __STM32F10x_CEC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CEC - * @{ - */ - - -/** @defgroup CEC_Exported_Types - * @{ - */ - -/** - * @brief CEC Init structure definition - */ -typedef struct -{ - uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. - This parameter can be a value of @ref CEC_BitTiming_Mode */ - uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. - This parameter can be a value of @ref CEC_BitPeriod_Mode */ -}CEC_InitTypeDef; - -/** - * @} - */ - -/** @defgroup CEC_Exported_Constants - * @{ - */ - -/** @defgroup CEC_BitTiming_Mode - * @{ - */ -#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */ -#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */ - -#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \ - ((MODE) == CEC_BitTimingErrFreeMode)) -/** - * @} - */ - -/** @defgroup CEC_BitPeriod_Mode - * @{ - */ -#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */ -#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */ - -#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \ - ((MODE) == CEC_BitPeriodFlexibleMode)) -/** - * @} - */ - - -/** @defgroup CEC_interrupts_definition - * @{ - */ -#define CEC_IT_TERR CEC_CSR_TERR -#define CEC_IT_TBTRF CEC_CSR_TBTRF -#define CEC_IT_RERR CEC_CSR_RERR -#define CEC_IT_RBTF CEC_CSR_RBTF -#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \ - ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF)) -/** - * @} - */ - - -/** @defgroup CEC_Own_Address - * @{ - */ -#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) -/** - * @} - */ - -/** @defgroup CEC_Prescaler - * @{ - */ -#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF) - -/** - * @} - */ - -/** @defgroup CEC_flags_definition - * @{ - */ - -/** - * @brief ESR register flags - */ -#define CEC_FLAG_BTE ((uint32_t)0x10010000) -#define CEC_FLAG_BPE ((uint32_t)0x10020000) -#define CEC_FLAG_RBTFE ((uint32_t)0x10040000) -#define CEC_FLAG_SBE ((uint32_t)0x10080000) -#define CEC_FLAG_ACKE ((uint32_t)0x10100000) -#define CEC_FLAG_LINE ((uint32_t)0x10200000) -#define CEC_FLAG_TBTFE ((uint32_t)0x10400000) - -/** - * @brief CSR register flags - */ -#define CEC_FLAG_TEOM ((uint32_t)0x00000002) -#define CEC_FLAG_TERR ((uint32_t)0x00000004) -#define CEC_FLAG_TBTRF ((uint32_t)0x00000008) -#define CEC_FLAG_RSOM ((uint32_t)0x00000010) -#define CEC_FLAG_REOM ((uint32_t)0x00000020) -#define CEC_FLAG_RERR ((uint32_t)0x00000040) -#define CEC_FLAG_RBTF ((uint32_t)0x00000080) - -#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00)) - -#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \ - ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \ - ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \ - ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \ - ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \ - ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \ - ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup CEC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CEC_Exported_Functions - * @{ - */ -void CEC_DeInit(void); -void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); -void CEC_Cmd(FunctionalState NewState); -void CEC_ITConfig(FunctionalState NewState); -void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); -void CEC_SetPrescaler(uint16_t CEC_Prescaler); -void CEC_SendDataByte(uint8_t Data); -uint8_t CEC_ReceiveDataByte(void); -void CEC_StartOfMessage(void); -void CEC_EndOfMessageCmd(FunctionalState NewState); -FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG); -void CEC_ClearFlag(uint32_t CEC_FLAG); -ITStatus CEC_GetITStatus(uint8_t CEC_IT); -void CEC_ClearITPendingBit(uint16_t CEC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_CEC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h deleted file mode 100644 index 658a51cef..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h +++ /dev/null @@ -1,94 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_crc.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the CRC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_CRC_H -#define __STM32F10x_CRC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CRC - * @{ - */ - -/** @defgroup CRC_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Exported_Functions - * @{ - */ - -void CRC_ResetDR(void); -uint32_t CRC_CalcCRC(uint32_t Data); -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); -uint32_t CRC_GetCRC(void); -void CRC_SetIDRegister(uint8_t IDValue); -uint8_t CRC_GetIDRegister(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_CRC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h deleted file mode 100644 index 710616412..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h +++ /dev/null @@ -1,317 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dac.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the DAC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_DAC_H -#define __STM32F10x_DAC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DAC - * @{ - */ - -/** @defgroup DAC_Exported_Types - * @{ - */ - -/** - * @brief DAC Init structure definition - */ - -typedef struct -{ - uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. - This parameter can be a value of @ref DAC_trigger_selection */ - - uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves - are generated, or whether no wave is generated. - This parameter can be a value of @ref DAC_wave_generation */ - - uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or - the maximum amplitude triangle generation for the DAC channel. - This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ - - uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. - This parameter can be a value of @ref DAC_output_buffer */ -}DAC_InitTypeDef; - -/** - * @} - */ - -/** @defgroup DAC_Exported_Constants - * @{ - */ - -/** @defgroup DAC_trigger_selection - * @{ - */ - -#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel - only in High-density devices*/ -#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel - only in Connectivity line, Medium-density and Low-density Value Line devices */ -#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel - only in Medium-density and Low-density Value Line devices*/ -#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ - -#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ - ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ - ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ - ((TRIGGER) == DAC_Trigger_Software)) - -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_WaveGeneration_None ((uint32_t)0x00000000) -#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) -#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) -#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ - ((WAVE) == DAC_WaveGeneration_Noise) || \ - ((WAVE) == DAC_WaveGeneration_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_lfsrunmask_triangleamplitude - * @{ - */ - -#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ -#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ -#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ -#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ -#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ -#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ -#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ -#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ -#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ -#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ -#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ -#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ -#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ - -#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ - ((VALUE) == DAC_TriangleAmplitude_1) || \ - ((VALUE) == DAC_TriangleAmplitude_3) || \ - ((VALUE) == DAC_TriangleAmplitude_7) || \ - ((VALUE) == DAC_TriangleAmplitude_15) || \ - ((VALUE) == DAC_TriangleAmplitude_31) || \ - ((VALUE) == DAC_TriangleAmplitude_63) || \ - ((VALUE) == DAC_TriangleAmplitude_127) || \ - ((VALUE) == DAC_TriangleAmplitude_255) || \ - ((VALUE) == DAC_TriangleAmplitude_511) || \ - ((VALUE) == DAC_TriangleAmplitude_1023) || \ - ((VALUE) == DAC_TriangleAmplitude_2047) || \ - ((VALUE) == DAC_TriangleAmplitude_4095)) -/** - * @} - */ - -/** @defgroup DAC_output_buffer - * @{ - */ - -#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) -#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) -#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ - ((STATE) == DAC_OutputBuffer_Disable)) -/** - * @} - */ - -/** @defgroup DAC_Channel_selection - * @{ - */ - -#define DAC_Channel_1 ((uint32_t)0x00000000) -#define DAC_Channel_2 ((uint32_t)0x00000010) -#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ - ((CHANNEL) == DAC_Channel_2)) -/** - * @} - */ - -/** @defgroup DAC_data_alignment - * @{ - */ - -#define DAC_Align_12b_R ((uint32_t)0x00000000) -#define DAC_Align_12b_L ((uint32_t)0x00000004) -#define DAC_Align_8b_R ((uint32_t)0x00000008) -#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ - ((ALIGN) == DAC_Align_12b_L) || \ - ((ALIGN) == DAC_Align_8b_R)) -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_Wave_Noise ((uint32_t)0x00000040) -#define DAC_Wave_Triangle ((uint32_t)0x00000080) -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ - ((WAVE) == DAC_Wave_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_data - * @{ - */ - -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) -/** - * @} - */ -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/** @defgroup DAC_interrupts_definition - * @{ - */ - -#define DAC_IT_DMAUDR ((uint32_t)0x00002000) -#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) - -/** - * @} - */ - -/** @defgroup DAC_flags_definition - * @{ - */ - -#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) -#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) - -/** - * @} - */ -#endif - -/** - * @} - */ - -/** @defgroup DAC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Exported_Functions - * @{ - */ - -void DAC_DeInit(void); -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); -#endif -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); -#endif - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_DAC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h deleted file mode 100644 index 1e6a68acb..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h +++ /dev/null @@ -1,119 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dbgmcu.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the DBGMCU - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_DBGMCU_H -#define __STM32F10x_DBGMCU_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DBGMCU - * @{ - */ - -/** @defgroup DBGMCU_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Exported_Constants - * @{ - */ - -#define DBGMCU_SLEEP ((uint32_t)0x00000001) -#define DBGMCU_STOP ((uint32_t)0x00000002) -#define DBGMCU_STANDBY ((uint32_t)0x00000004) -#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) -#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) -#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400) -#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800) -#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000) -#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000) -#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000) -#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) -#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) -#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000) -#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000) -#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000) -#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000) -#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) -#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000) -#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000) -#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000) -#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000) -#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000) -#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000) -#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000) -#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000) -#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000) - -#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup DBGMCU_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Exported_Functions - * @{ - */ - -uint32_t DBGMCU_GetREVID(void); -uint32_t DBGMCU_GetDEVID(void); -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_DBGMCU_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h deleted file mode 100644 index b5dc6a80a..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h +++ /dev/null @@ -1,439 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dma.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the DMA firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_DMA_H -#define __STM32F10x_DMA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/** @defgroup DMA_Exported_Types - * @{ - */ - -/** - * @brief DMA Init structure definition - */ - -typedef struct -{ - uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ - - uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ - - uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. - This parameter can be a value of @ref DMA_data_transfer_direction */ - - uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. - The data unit is equal to the configuration set in DMA_PeripheralDataSize - or DMA_MemoryDataSize members depending in the transfer direction. */ - - uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. - This parameter can be a value of @ref DMA_peripheral_incremented_mode */ - - uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. - This parameter can be a value of @ref DMA_memory_incremented_mode */ - - uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_peripheral_data_size */ - - uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. - This parameter can be a value of @ref DMA_memory_data_size */ - - uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. - This parameter can be a value of @ref DMA_circular_normal_mode. - @note: The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ - - uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. - This parameter can be a value of @ref DMA_priority_level */ - - uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. - This parameter can be a value of @ref DMA_memory_to_memory */ -}DMA_InitTypeDef; - -/** - * @} - */ - -/** @defgroup DMA_Exported_Constants - * @{ - */ - -#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ - ((PERIPH) == DMA1_Channel2) || \ - ((PERIPH) == DMA1_Channel3) || \ - ((PERIPH) == DMA1_Channel4) || \ - ((PERIPH) == DMA1_Channel5) || \ - ((PERIPH) == DMA1_Channel6) || \ - ((PERIPH) == DMA1_Channel7) || \ - ((PERIPH) == DMA2_Channel1) || \ - ((PERIPH) == DMA2_Channel2) || \ - ((PERIPH) == DMA2_Channel3) || \ - ((PERIPH) == DMA2_Channel4) || \ - ((PERIPH) == DMA2_Channel5)) - -/** @defgroup DMA_data_transfer_direction - * @{ - */ - -#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) -#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) -#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ - ((DIR) == DMA_DIR_PeripheralSRC)) -/** - * @} - */ - -/** @defgroup DMA_peripheral_incremented_mode - * @{ - */ - -#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) -#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ - ((STATE) == DMA_PeripheralInc_Disable)) -/** - * @} - */ - -/** @defgroup DMA_memory_incremented_mode - * @{ - */ - -#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) -#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ - ((STATE) == DMA_MemoryInc_Disable)) -/** - * @} - */ - -/** @defgroup DMA_peripheral_data_size - * @{ - */ - -#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) -#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) -#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ - ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ - ((SIZE) == DMA_PeripheralDataSize_Word)) -/** - * @} - */ - -/** @defgroup DMA_memory_data_size - * @{ - */ - -#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) -#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) -#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ - ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ - ((SIZE) == DMA_MemoryDataSize_Word)) -/** - * @} - */ - -/** @defgroup DMA_circular_normal_mode - * @{ - */ - -#define DMA_Mode_Circular ((uint32_t)0x00000020) -#define DMA_Mode_Normal ((uint32_t)0x00000000) -#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) -/** - * @} - */ - -/** @defgroup DMA_priority_level - * @{ - */ - -#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) -#define DMA_Priority_High ((uint32_t)0x00002000) -#define DMA_Priority_Medium ((uint32_t)0x00001000) -#define DMA_Priority_Low ((uint32_t)0x00000000) -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ - ((PRIORITY) == DMA_Priority_High) || \ - ((PRIORITY) == DMA_Priority_Medium) || \ - ((PRIORITY) == DMA_Priority_Low)) -/** - * @} - */ - -/** @defgroup DMA_memory_to_memory - * @{ - */ - -#define DMA_M2M_Enable ((uint32_t)0x00004000) -#define DMA_M2M_Disable ((uint32_t)0x00000000) -#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) - -/** - * @} - */ - -/** @defgroup DMA_interrupts_definition - * @{ - */ - -#define DMA_IT_TC ((uint32_t)0x00000002) -#define DMA_IT_HT ((uint32_t)0x00000004) -#define DMA_IT_TE ((uint32_t)0x00000008) -#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) - -#define DMA1_IT_GL1 ((uint32_t)0x00000001) -#define DMA1_IT_TC1 ((uint32_t)0x00000002) -#define DMA1_IT_HT1 ((uint32_t)0x00000004) -#define DMA1_IT_TE1 ((uint32_t)0x00000008) -#define DMA1_IT_GL2 ((uint32_t)0x00000010) -#define DMA1_IT_TC2 ((uint32_t)0x00000020) -#define DMA1_IT_HT2 ((uint32_t)0x00000040) -#define DMA1_IT_TE2 ((uint32_t)0x00000080) -#define DMA1_IT_GL3 ((uint32_t)0x00000100) -#define DMA1_IT_TC3 ((uint32_t)0x00000200) -#define DMA1_IT_HT3 ((uint32_t)0x00000400) -#define DMA1_IT_TE3 ((uint32_t)0x00000800) -#define DMA1_IT_GL4 ((uint32_t)0x00001000) -#define DMA1_IT_TC4 ((uint32_t)0x00002000) -#define DMA1_IT_HT4 ((uint32_t)0x00004000) -#define DMA1_IT_TE4 ((uint32_t)0x00008000) -#define DMA1_IT_GL5 ((uint32_t)0x00010000) -#define DMA1_IT_TC5 ((uint32_t)0x00020000) -#define DMA1_IT_HT5 ((uint32_t)0x00040000) -#define DMA1_IT_TE5 ((uint32_t)0x00080000) -#define DMA1_IT_GL6 ((uint32_t)0x00100000) -#define DMA1_IT_TC6 ((uint32_t)0x00200000) -#define DMA1_IT_HT6 ((uint32_t)0x00400000) -#define DMA1_IT_TE6 ((uint32_t)0x00800000) -#define DMA1_IT_GL7 ((uint32_t)0x01000000) -#define DMA1_IT_TC7 ((uint32_t)0x02000000) -#define DMA1_IT_HT7 ((uint32_t)0x04000000) -#define DMA1_IT_TE7 ((uint32_t)0x08000000) - -#define DMA2_IT_GL1 ((uint32_t)0x10000001) -#define DMA2_IT_TC1 ((uint32_t)0x10000002) -#define DMA2_IT_HT1 ((uint32_t)0x10000004) -#define DMA2_IT_TE1 ((uint32_t)0x10000008) -#define DMA2_IT_GL2 ((uint32_t)0x10000010) -#define DMA2_IT_TC2 ((uint32_t)0x10000020) -#define DMA2_IT_HT2 ((uint32_t)0x10000040) -#define DMA2_IT_TE2 ((uint32_t)0x10000080) -#define DMA2_IT_GL3 ((uint32_t)0x10000100) -#define DMA2_IT_TC3 ((uint32_t)0x10000200) -#define DMA2_IT_HT3 ((uint32_t)0x10000400) -#define DMA2_IT_TE3 ((uint32_t)0x10000800) -#define DMA2_IT_GL4 ((uint32_t)0x10001000) -#define DMA2_IT_TC4 ((uint32_t)0x10002000) -#define DMA2_IT_HT4 ((uint32_t)0x10004000) -#define DMA2_IT_TE4 ((uint32_t)0x10008000) -#define DMA2_IT_GL5 ((uint32_t)0x10010000) -#define DMA2_IT_TC5 ((uint32_t)0x10020000) -#define DMA2_IT_HT5 ((uint32_t)0x10040000) -#define DMA2_IT_TE5 ((uint32_t)0x10080000) - -#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) - -#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ - ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ - ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ - ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ - ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ - ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ - ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ - ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ - ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ - ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ - ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ - ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ - ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ - ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ - ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ - ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ - ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ - ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ - ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ - ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ - ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ - ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ - ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ - ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) - -/** - * @} - */ - -/** @defgroup DMA_flags_definition - * @{ - */ -#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) -#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) -#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) -#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) -#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) -#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) -#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) -#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) -#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) -#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) -#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) -#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) -#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) -#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) -#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) -#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) -#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) -#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) -#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) -#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) -#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) -#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) -#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) -#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) -#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) -#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) -#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) -#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) - -#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) -#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) -#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) -#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) -#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) -#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) -#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) -#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) -#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) -#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) -#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) -#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) -#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) -#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) -#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) -#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) -#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) -#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) -#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) -#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) - -#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) - -#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ - ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ - ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ - ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ - ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ - ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ - ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ - ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ - ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ - ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ - ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ - ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ - ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ - ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ - ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ - ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ - ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ - ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ - ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ - ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ - ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ - ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ - ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ - ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) -/** - * @} - */ - -/** @defgroup DMA_Buffer_Size - * @{ - */ - -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup DMA_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DMA_Exported_Functions - * @{ - */ - -void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); -void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); -void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); -void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); -FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); -void DMA_ClearFlag(uint32_t DMAy_FLAG); -ITStatus DMA_GetITStatus(uint32_t DMAy_IT); -void DMA_ClearITPendingBit(uint32_t DMAy_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_DMA_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h deleted file mode 100644 index a1ab7d03e..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h +++ /dev/null @@ -1,184 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_exti.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the EXTI firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_EXTI_H -#define __STM32F10x_EXTI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup EXTI - * @{ - */ - -/** @defgroup EXTI_Exported_Types - * @{ - */ - -/** - * @brief EXTI mode enumeration - */ - -typedef enum -{ - EXTI_Mode_Interrupt = 0x00, - EXTI_Mode_Event = 0x04 -}EXTIMode_TypeDef; - -#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) - -/** - * @brief EXTI Trigger enumeration - */ - -typedef enum -{ - EXTI_Trigger_Rising = 0x08, - EXTI_Trigger_Falling = 0x0C, - EXTI_Trigger_Rising_Falling = 0x10 -}EXTITrigger_TypeDef; - -#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ - ((TRIGGER) == EXTI_Trigger_Falling) || \ - ((TRIGGER) == EXTI_Trigger_Rising_Falling)) -/** - * @brief EXTI Init Structure definition - */ - -typedef struct -{ - uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. - This parameter can be any combination of @ref EXTI_Lines */ - - EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ -}EXTI_InitTypeDef; - -/** - * @} - */ - -/** @defgroup EXTI_Exported_Constants - * @{ - */ - -/** @defgroup EXTI_Lines - * @{ - */ - -#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ -#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ -#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ -#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ -#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ -#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ -#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ -#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ -#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ -#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ -#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ -#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ -#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ -#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ -#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ -#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ -#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ -#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ -#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS - Wakeup from suspend event */ -#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ - -#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00)) -#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ - ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ - ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ - ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ - ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ - ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ - ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ - ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ - ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ - ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19)) - - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup EXTI_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Exported_Functions - * @{ - */ - -void EXTI_DeInit(void); -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); -void EXTI_ClearFlag(uint32_t EXTI_Line); -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); -void EXTI_ClearITPendingBit(uint32_t EXTI_Line); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_EXTI_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h deleted file mode 100644 index f46d4e873..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h +++ /dev/null @@ -1,426 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_flash.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the FLASH - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_FLASH_H -#define __STM32F10x_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/** @defgroup FLASH_Exported_Types - * @{ - */ - -/** - * @brief FLASH Status - */ - -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_PG, - FLASH_ERROR_WRP, - FLASH_COMPLETE, - FLASH_TIMEOUT -}FLASH_Status; - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Constants - * @{ - */ - -/** @defgroup Flash_Latency - * @{ - */ - -#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ -#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */ -#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */ -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ - ((LATENCY) == FLASH_Latency_1) || \ - ((LATENCY) == FLASH_Latency_2)) -/** - * @} - */ - -/** @defgroup Half_Cycle_Enable_Disable - * @{ - */ - -#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */ -#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */ -#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ - ((STATE) == FLASH_HalfCycleAccess_Disable)) -/** - * @} - */ - -/** @defgroup Prefetch_Buffer_Enable_Disable - * @{ - */ - -#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */ -#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */ -#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ - ((STATE) == FLASH_PrefetchBuffer_Disable)) -/** - * @} - */ - -/** @defgroup Option_Bytes_Write_Protection - * @{ - */ - -/* Values to be used with STM32 Low and Medium density devices */ -#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */ -#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */ -#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */ -#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */ -#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */ -#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */ -#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */ -#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */ - -/* Values to be used with STM32 Medium-density devices */ -#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */ -#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */ -#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */ -#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */ -#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */ -#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */ -#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */ -#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */ -#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */ -#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */ -#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */ -#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */ -#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */ -#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */ -#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */ -#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */ -#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */ -#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */ -#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */ -#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */ -#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */ -#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */ -#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */ -#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */ - -/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */ -#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 0 to 1 */ -#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 2 to 3 */ -#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 4 to 5 */ -#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 6 to 7 */ -#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 8 to 9 */ -#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 10 to 11 */ -#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 12 to 13 */ -#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 14 to 15 */ -#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 16 to 17 */ -#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 18 to 19 */ -#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 20 to 21 */ -#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 22 to 23 */ -#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 24 to 25 */ -#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 26 to 27 */ -#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 28 to 29 */ -#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 30 to 31 */ -#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 32 to 33 */ -#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 34 to 35 */ -#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 36 to 37 */ -#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 38 to 39 */ -#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 40 to 41 */ -#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 42 to 43 */ -#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 44 to 45 */ -#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 46 to 47 */ -#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 48 to 49 */ -#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 50 to 51 */ -#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 52 to 53 */ -#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 54 to 55 */ -#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 56 to 57 */ -#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 58 to 59 */ -#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 60 to 61 */ -#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */ -#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */ -#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */ - -#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */ - -#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000)) - -#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) - -#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_IWatchdog - * @{ - */ - -#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */ -#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */ -#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_nRST_STOP - * @{ - */ - -#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */ -#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_nRST_STDBY - * @{ - */ - -#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */ -#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) - -#ifdef STM32F10X_XL -/** - * @} - */ -/** @defgroup FLASH_Boot - * @{ - */ -#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position - and this parameter is selected the device will boot from Bank1(Default) */ -#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position - and this parameter is selected the device will boot from Bank 2 or Bank 1, - depending on the activation of the bank */ -#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2)) -#endif -/** - * @} - */ -/** @defgroup FLASH_Interrupts - * @{ - */ -#ifdef STM32F10X_XL -#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */ -#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */ - -#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ -#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ - -#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */ -#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */ -#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) -#else -#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */ -#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */ -#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ -#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ - -#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) -#endif - -/** - * @} - */ - -/** @defgroup FLASH_Flags - * @{ - */ -#ifdef STM32F10X_XL -#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */ -#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */ -#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */ -#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */ - -#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ -#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ -#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ -#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ - -#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ -#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ -#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ - -#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) -#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ - ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ - ((FLAG) == FLASH_FLAG_OPTERR)|| \ - ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ - ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ - ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \ - ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR)) -#else -#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ -#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ -#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ - -#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ -#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ -#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ -#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ - -#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) -#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ - ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ - ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ - ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ - ((FLAG) == FLASH_FLAG_OPTERR)) -#endif - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions - * @{ - */ - -/*------------ Functions used for all STM32F10x devices -----*/ -void FLASH_SetLatency(uint32_t FLASH_Latency); -void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess); -void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer); -void FLASH_Unlock(void); -void FLASH_Lock(void); -FLASH_Status FLASH_ErasePage(uint32_t Page_Address); -FLASH_Status FLASH_EraseAllPages(void); -FLASH_Status FLASH_EraseOptionBytes(void); -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); -FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); -FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); -FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); -uint32_t FLASH_GetUserOptionByte(void); -uint32_t FLASH_GetWriteProtectionOptionByte(void); -FlagStatus FLASH_GetReadOutProtectionStatus(void); -FlagStatus FLASH_GetPrefetchBufferStatus(void); -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); -void FLASH_ClearFlag(uint32_t FLASH_FLAG); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); - -/*------------ New function used for all STM32F10x devices -----*/ -void FLASH_UnlockBank1(void); -void FLASH_LockBank1(void); -FLASH_Status FLASH_EraseAllBank1Pages(void); -FLASH_Status FLASH_GetBank1Status(void); -FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); - -#ifdef STM32F10X_XL -/*---- New Functions used only with STM32F10x_XL density devices -----*/ -void FLASH_UnlockBank2(void); -void FLASH_LockBank2(void); -FLASH_Status FLASH_EraseAllBank2Pages(void); -FLASH_Status FLASH_GetBank2Status(void); -FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout); -FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT); -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_FLASH_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h deleted file mode 100644 index ee707e743..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h +++ /dev/null @@ -1,733 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_fsmc.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the FSMC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_FSMC_H -#define __STM32F10x_FSMC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FSMC - * @{ - */ - -/** @defgroup FSMC_Exported_Types - * @{ - */ - -/** - * @brief Timing parameters For NOR/SRAM Banks - */ - -typedef struct -{ - uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address setup time. - This parameter can be a value between 0 and 0xF. - @note: It is not used with synchronous NOR Flash memories. */ - - uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address hold time. - This parameter can be a value between 0 and 0xF. - @note: It is not used with synchronous NOR Flash memories.*/ - - uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the data setup time. - This parameter can be a value between 0 and 0xFF. - @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ - - uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure - the duration of the bus turnaround. - This parameter can be a value between 0 and 0xF. - @note: It is only used for multiplexed NOR Flash memories. */ - - uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. - This parameter can be a value between 1 and 0xF. - @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ - - uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue - to the memory before getting the first data. - The value of this parameter depends on the memory type as shown below: - - It must be set to 0 in case of a CRAM - - It is don't care in asynchronous NOR, SRAM or ROM accesses - - It may assume a value between 0 and 0xF in NOR Flash memories - with synchronous burst mode enable */ - - uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FSMC_Access_Mode */ -}FSMC_NORSRAMTimingInitTypeDef; - -/** - * @brief FSMC NOR/SRAM Init structure definition - */ - -typedef struct -{ - uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. - This parameter can be a value of @ref FSMC_NORSRAM_Bank */ - - uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are - multiplexed on the databus or not. - This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ - - uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to - the corresponding memory bank. - This parameter can be a value of @ref FSMC_Memory_Type */ - - uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FSMC_Data_Width */ - - uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, - valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FSMC_Burst_Access_Mode */ - - uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, - valid only with asynchronous Flash memories. - This parameter can be a value of @ref FSMC_AsynchronousWait */ - - uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing - the Flash memory in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ - - uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash - memory, valid only when accessing Flash memories in burst mode. - This parameter can be a value of @ref FSMC_Wrap_Mode */ - - uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one - clock cycle before the wait state or during the wait state, - valid only when accessing memories in burst mode. - This parameter can be a value of @ref FSMC_Wait_Timing */ - - uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. - This parameter can be a value of @ref FSMC_Write_Operation */ - - uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait - signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal */ - - uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FSMC_Extended_Mode */ - - uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FSMC_Write_Burst */ - - FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ - - FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ -}FSMC_NORSRAMInitTypeDef; - -/** - * @brief Timing parameters For FSMC NAND and PCCARD Banks - */ - -typedef struct -{ - uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before - the command assertion for NAND-Flash read or write access - to common/Attribute or I/O memory space (depending on - the memory space timing to be configured). - This parameter can be a value between 0 and 0xFF.*/ - - uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the - command for NAND-Flash read or write access to - common/Attribute or I/O memory space (depending on the - memory space timing to be configured). - This parameter can be a number between 0x00 and 0xFF */ - - uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address - (and data for write access) after the command deassertion - for NAND-Flash read or write access to common/Attribute - or I/O memory space (depending on the memory space timing - to be configured). - This parameter can be a number between 0x00 and 0xFF */ - - uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the - databus is kept in HiZ after the start of a NAND-Flash - write access to common/Attribute or I/O memory space (depending - on the memory space timing to be configured). - This parameter can be a number between 0x00 and 0xFF */ -}FSMC_NAND_PCCARDTimingInitTypeDef; - -/** - * @brief FSMC NAND Init structure definition - */ - -typedef struct -{ - uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. - This parameter can be a value of @ref FSMC_NAND_Bank */ - - uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. - This parameter can be any value of @ref FSMC_Wait_feature */ - - uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be any value of @ref FSMC_Data_Width */ - - uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. - This parameter can be any value of @ref FSMC_ECC */ - - uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. - This parameter can be any value of @ref FSMC_ECC_Page_Size */ - - uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 0xFF. */ - - uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0x0 and 0xFF */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ -}FSMC_NANDInitTypeDef; - -/** - * @brief FSMC PCCARD Init structure definition - */ - -typedef struct -{ - uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. - This parameter can be any value of @ref FSMC_Wait_feature */ - - uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 0xFF. */ - - uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0x0 and 0xFF */ - - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ -}FSMC_PCCARDInitTypeDef; - -/** - * @} - */ - -/** @defgroup FSMC_Exported_Constants - * @{ - */ - -/** @defgroup FSMC_NORSRAM_Bank - * @{ - */ -#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) -#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) -#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) -#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) -/** - * @} - */ - -/** @defgroup FSMC_NAND_Bank - * @{ - */ -#define FSMC_Bank2_NAND ((uint32_t)0x00000010) -#define FSMC_Bank3_NAND ((uint32_t)0x00000100) -/** - * @} - */ - -/** @defgroup FSMC_PCCARD_Bank - * @{ - */ -#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) -/** - * @} - */ - -#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ - ((BANK) == FSMC_Bank1_NORSRAM2) || \ - ((BANK) == FSMC_Bank1_NORSRAM3) || \ - ((BANK) == FSMC_Bank1_NORSRAM4)) - -#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND)) - -#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND) || \ - ((BANK) == FSMC_Bank4_PCCARD)) - -#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND) || \ - ((BANK) == FSMC_Bank4_PCCARD)) - -/** @defgroup NOR_SRAM_Controller - * @{ - */ - -/** @defgroup FSMC_Data_Address_Bus_Multiplexing - * @{ - */ - -#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) -#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) -#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ - ((MUX) == FSMC_DataAddressMux_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_Memory_Type - * @{ - */ - -#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) -#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) -#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) -#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ - ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ - ((MEMORY) == FSMC_MemoryType_NOR)) - -/** - * @} - */ - -/** @defgroup FSMC_Data_Width - * @{ - */ - -#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) -#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) -#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ - ((WIDTH) == FSMC_MemoryDataWidth_16b)) - -/** - * @} - */ - -/** @defgroup FSMC_Burst_Access_Mode - * @{ - */ - -#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) -#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) -#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ - ((STATE) == FSMC_BurstAccessMode_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_AsynchronousWait - * @{ - */ -#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) -#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) -#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ - ((STATE) == FSMC_AsynchronousWait_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_Wait_Signal_Polarity - * @{ - */ - -#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) -#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) -#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ - ((POLARITY) == FSMC_WaitSignalPolarity_High)) - -/** - * @} - */ - -/** @defgroup FSMC_Wrap_Mode - * @{ - */ - -#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) -#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) -#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ - ((MODE) == FSMC_WrapMode_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_Wait_Timing - * @{ - */ - -#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) -#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) -#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ - ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) - -/** - * @} - */ - -/** @defgroup FSMC_Write_Operation - * @{ - */ - -#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) -#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) -#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ - ((OPERATION) == FSMC_WriteOperation_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_Wait_Signal - * @{ - */ - -#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) -#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) -#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ - ((SIGNAL) == FSMC_WaitSignal_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Extended_Mode - * @{ - */ - -#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) -#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) - -#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ - ((MODE) == FSMC_ExtendedMode_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_Write_Burst - * @{ - */ - -#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) -#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) -#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ - ((BURST) == FSMC_WriteBurst_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Address_Setup_Time - * @{ - */ - -#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) - -/** - * @} - */ - -/** @defgroup FSMC_Address_Hold_Time - * @{ - */ - -#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) - -/** - * @} - */ - -/** @defgroup FSMC_Data_Setup_Time - * @{ - */ - -#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) - -/** - * @} - */ - -/** @defgroup FSMC_Bus_Turn_around_Duration - * @{ - */ - -#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) - -/** - * @} - */ - -/** @defgroup FSMC_CLK_Division - * @{ - */ - -#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) - -/** - * @} - */ - -/** @defgroup FSMC_Data_Latency - * @{ - */ - -#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) - -/** - * @} - */ - -/** @defgroup FSMC_Access_Mode - * @{ - */ - -#define FSMC_AccessMode_A ((uint32_t)0x00000000) -#define FSMC_AccessMode_B ((uint32_t)0x10000000) -#define FSMC_AccessMode_C ((uint32_t)0x20000000) -#define FSMC_AccessMode_D ((uint32_t)0x30000000) -#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ - ((MODE) == FSMC_AccessMode_B) || \ - ((MODE) == FSMC_AccessMode_C) || \ - ((MODE) == FSMC_AccessMode_D)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup NAND_PCCARD_Controller - * @{ - */ - -/** @defgroup FSMC_Wait_feature - * @{ - */ - -#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) -#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) -#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ - ((FEATURE) == FSMC_Waitfeature_Enable)) - -/** - * @} - */ - - -/** @defgroup FSMC_ECC - * @{ - */ - -#define FSMC_ECC_Disable ((uint32_t)0x00000000) -#define FSMC_ECC_Enable ((uint32_t)0x00000040) -#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ - ((STATE) == FSMC_ECC_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_ECC_Page_Size - * @{ - */ - -#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) -#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) -#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) -#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) -#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) -#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) -#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_8192Bytes)) - -/** - * @} - */ - -/** @defgroup FSMC_TCLR_Setup_Time - * @{ - */ - -#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_TAR_Setup_Time - * @{ - */ - -#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_Setup_Time - * @{ - */ - -#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_Wait_Setup_Time - * @{ - */ - -#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_Hold_Setup_Time - * @{ - */ - -#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_HiZ_Setup_Time - * @{ - */ - -#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_Interrupt_sources - * @{ - */ - -#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) -#define FSMC_IT_Level ((uint32_t)0x00000010) -#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) -#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) -#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ - ((IT) == FSMC_IT_Level) || \ - ((IT) == FSMC_IT_FallingEdge)) -/** - * @} - */ - -/** @defgroup FSMC_Flags - * @{ - */ - -#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) -#define FSMC_FLAG_Level ((uint32_t)0x00000002) -#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) -#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) -#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ - ((FLAG) == FSMC_FLAG_Level) || \ - ((FLAG) == FSMC_FLAG_FallingEdge) || \ - ((FLAG) == FSMC_FLAG_FEMPT)) - -#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FSMC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup FSMC_Exported_Functions - * @{ - */ - -void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); -void FSMC_NANDDeInit(uint32_t FSMC_Bank); -void FSMC_PCCARDDeInit(void); -void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); -void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); -void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); -void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); -void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); -void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); -void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); -void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); -void FSMC_PCCARDCmd(FunctionalState NewState); -void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); -uint32_t FSMC_GetECC(uint32_t FSMC_Bank); -void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); -FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); -void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); -ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); -void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_FSMC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h deleted file mode 100644 index b8aa49a2a..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h +++ /dev/null @@ -1,385 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_gpio.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the GPIO - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_GPIO_H -#define __STM32F10x_GPIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/** @defgroup GPIO_Exported_Types - * @{ - */ - -#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ - ((PERIPH) == GPIOB) || \ - ((PERIPH) == GPIOC) || \ - ((PERIPH) == GPIOD) || \ - ((PERIPH) == GPIOE) || \ - ((PERIPH) == GPIOF) || \ - ((PERIPH) == GPIOG)) - -/** - * @brief Output Maximum frequency selection - */ - -typedef enum -{ - GPIO_Speed_10MHz = 1, - GPIO_Speed_2MHz, - GPIO_Speed_50MHz -}GPIOSpeed_TypeDef; -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \ - ((SPEED) == GPIO_Speed_50MHz)) - -/** - * @brief Configuration Mode enumeration - */ - -typedef enum -{ GPIO_Mode_AIN = 0x0, - GPIO_Mode_IN_FLOATING = 0x04, - GPIO_Mode_IPD = 0x28, - GPIO_Mode_IPU = 0x48, - GPIO_Mode_Out_OD = 0x14, - GPIO_Mode_Out_PP = 0x10, - GPIO_Mode_AF_OD = 0x1C, - GPIO_Mode_AF_PP = 0x18 -}GPIOMode_TypeDef; - -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \ - ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \ - ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \ - ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) - -/** - * @brief GPIO Init structure definition - */ - -typedef struct -{ - uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIOSpeed_TypeDef */ - - GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIOMode_TypeDef */ -}GPIO_InitTypeDef; - - -/** - * @brief Bit_SET and Bit_RESET enumeration - */ - -typedef enum -{ Bit_RESET = 0, - Bit_SET -}BitAction; - -#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) - -/** - * @} - */ - -/** @defgroup GPIO_Exported_Constants - * @{ - */ - -/** @defgroup GPIO_pins_define - * @{ - */ - -#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ -#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ -#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ -#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ -#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ -#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ -#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ -#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ -#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ -#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ -#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ -#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ -#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ -#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ -#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ -#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ -#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ - -#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) - -#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ - ((PIN) == GPIO_Pin_1) || \ - ((PIN) == GPIO_Pin_2) || \ - ((PIN) == GPIO_Pin_3) || \ - ((PIN) == GPIO_Pin_4) || \ - ((PIN) == GPIO_Pin_5) || \ - ((PIN) == GPIO_Pin_6) || \ - ((PIN) == GPIO_Pin_7) || \ - ((PIN) == GPIO_Pin_8) || \ - ((PIN) == GPIO_Pin_9) || \ - ((PIN) == GPIO_Pin_10) || \ - ((PIN) == GPIO_Pin_11) || \ - ((PIN) == GPIO_Pin_12) || \ - ((PIN) == GPIO_Pin_13) || \ - ((PIN) == GPIO_Pin_14) || \ - ((PIN) == GPIO_Pin_15)) - -/** - * @} - */ - -/** @defgroup GPIO_Remap_define - * @{ - */ - -#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */ -#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */ -#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */ -#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */ -#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */ -#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */ -#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */ -#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */ -#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */ -#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */ -#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */ -#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */ -#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */ -#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */ -#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */ -#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */ -#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */ -#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */ -#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */ -#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */ -#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */ -#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */ -#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ -#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */ -#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */ -#define GPIO_Remap_SPI3 ((uint32_t)0x00201100) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ -#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected - to TIM2 Internal Trigger 1 for calibration - (only for Connectivity line devices) */ -#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ - -#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */ -#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */ -#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */ -#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */ -#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */ - -#define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */ -#define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */ -#define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */ -#define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */ -#define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */ -#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */ - -#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */ -#define GPIO_Remap_TIM12 ((uint32_t)0x80001000) /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */ -#define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, - only for High density Value line devices) */ - -#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \ - ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \ - ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \ - ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \ - ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \ - ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \ - ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \ - ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \ - ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \ - ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \ - ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \ - ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \ - ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \ - ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \ - ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \ - ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \ - ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \ - ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \ - ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \ - ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \ - ((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \ - ((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC)) - -/** - * @} - */ - -/** @defgroup GPIO_Port_Sources - * @{ - */ - -#define GPIO_PortSourceGPIOA ((uint8_t)0x00) -#define GPIO_PortSourceGPIOB ((uint8_t)0x01) -#define GPIO_PortSourceGPIOC ((uint8_t)0x02) -#define GPIO_PortSourceGPIOD ((uint8_t)0x03) -#define GPIO_PortSourceGPIOE ((uint8_t)0x04) -#define GPIO_PortSourceGPIOF ((uint8_t)0x05) -#define GPIO_PortSourceGPIOG ((uint8_t)0x06) -#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOE)) - -#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOG)) - -/** - * @} - */ - -/** @defgroup GPIO_Pin_sources - * @{ - */ - -#define GPIO_PinSource0 ((uint8_t)0x00) -#define GPIO_PinSource1 ((uint8_t)0x01) -#define GPIO_PinSource2 ((uint8_t)0x02) -#define GPIO_PinSource3 ((uint8_t)0x03) -#define GPIO_PinSource4 ((uint8_t)0x04) -#define GPIO_PinSource5 ((uint8_t)0x05) -#define GPIO_PinSource6 ((uint8_t)0x06) -#define GPIO_PinSource7 ((uint8_t)0x07) -#define GPIO_PinSource8 ((uint8_t)0x08) -#define GPIO_PinSource9 ((uint8_t)0x09) -#define GPIO_PinSource10 ((uint8_t)0x0A) -#define GPIO_PinSource11 ((uint8_t)0x0B) -#define GPIO_PinSource12 ((uint8_t)0x0C) -#define GPIO_PinSource13 ((uint8_t)0x0D) -#define GPIO_PinSource14 ((uint8_t)0x0E) -#define GPIO_PinSource15 ((uint8_t)0x0F) - -#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ - ((PINSOURCE) == GPIO_PinSource1) || \ - ((PINSOURCE) == GPIO_PinSource2) || \ - ((PINSOURCE) == GPIO_PinSource3) || \ - ((PINSOURCE) == GPIO_PinSource4) || \ - ((PINSOURCE) == GPIO_PinSource5) || \ - ((PINSOURCE) == GPIO_PinSource6) || \ - ((PINSOURCE) == GPIO_PinSource7) || \ - ((PINSOURCE) == GPIO_PinSource8) || \ - ((PINSOURCE) == GPIO_PinSource9) || \ - ((PINSOURCE) == GPIO_PinSource10) || \ - ((PINSOURCE) == GPIO_PinSource11) || \ - ((PINSOURCE) == GPIO_PinSource12) || \ - ((PINSOURCE) == GPIO_PinSource13) || \ - ((PINSOURCE) == GPIO_PinSource14) || \ - ((PINSOURCE) == GPIO_PinSource15)) - -/** - * @} - */ - -/** @defgroup Ethernet_Media_Interface - * @{ - */ -#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) -#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) - -#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \ - ((INTERFACE) == GPIO_ETH_MediaInterface_RMII)) - -/** - * @} - */ -/** - * @} - */ - -/** @defgroup GPIO_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Exported_Functions - * @{ - */ - -void GPIO_DeInit(GPIO_TypeDef* GPIOx); -void GPIO_AFIODeInit(void); -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); -void GPIO_EventOutputCmd(FunctionalState NewState); -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); -void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_GPIO_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h deleted file mode 100644 index 2d42e5ce3..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h +++ /dev/null @@ -1,684 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_i2c.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the I2C firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_I2C_H -#define __STM32F10x_I2C_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/** @defgroup I2C_Exported_Types - * @{ - */ - -/** - * @brief I2C Init structure definition - */ - -typedef struct -{ - uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. - This parameter must be set to a value lower than 400kHz */ - - uint16_t I2C_Mode; /*!< Specifies the I2C mode. - This parameter can be a value of @ref I2C_mode */ - - uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. - This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ - - uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. - This parameter can be a value of @ref I2C_acknowledgement */ - - uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. - This parameter can be a value of @ref I2C_acknowledged_address */ -}I2C_InitTypeDef; - -/** - * @} - */ - - -/** @defgroup I2C_Exported_Constants - * @{ - */ - -#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ - ((PERIPH) == I2C2)) -/** @defgroup I2C_mode - * @{ - */ - -#define I2C_Mode_I2C ((uint16_t)0x0000) -#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) -#define I2C_Mode_SMBusHost ((uint16_t)0x000A) -#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ - ((MODE) == I2C_Mode_SMBusDevice) || \ - ((MODE) == I2C_Mode_SMBusHost)) -/** - * @} - */ - -/** @defgroup I2C_duty_cycle_in_fast_mode - * @{ - */ - -#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ -#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ -#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ - ((CYCLE) == I2C_DutyCycle_2)) -/** - * @} - */ - -/** @defgroup I2C_acknowledgement - * @{ - */ - -#define I2C_Ack_Enable ((uint16_t)0x0400) -#define I2C_Ack_Disable ((uint16_t)0x0000) -#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ - ((STATE) == I2C_Ack_Disable)) -/** - * @} - */ - -/** @defgroup I2C_transfer_direction - * @{ - */ - -#define I2C_Direction_Transmitter ((uint8_t)0x00) -#define I2C_Direction_Receiver ((uint8_t)0x01) -#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ - ((DIRECTION) == I2C_Direction_Receiver)) -/** - * @} - */ - -/** @defgroup I2C_acknowledged_address - * @{ - */ - -#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) -#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) -#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ - ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) -/** - * @} - */ - -/** @defgroup I2C_registers - * @{ - */ - -#define I2C_Register_CR1 ((uint8_t)0x00) -#define I2C_Register_CR2 ((uint8_t)0x04) -#define I2C_Register_OAR1 ((uint8_t)0x08) -#define I2C_Register_OAR2 ((uint8_t)0x0C) -#define I2C_Register_DR ((uint8_t)0x10) -#define I2C_Register_SR1 ((uint8_t)0x14) -#define I2C_Register_SR2 ((uint8_t)0x18) -#define I2C_Register_CCR ((uint8_t)0x1C) -#define I2C_Register_TRISE ((uint8_t)0x20) -#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ - ((REGISTER) == I2C_Register_CR2) || \ - ((REGISTER) == I2C_Register_OAR1) || \ - ((REGISTER) == I2C_Register_OAR2) || \ - ((REGISTER) == I2C_Register_DR) || \ - ((REGISTER) == I2C_Register_SR1) || \ - ((REGISTER) == I2C_Register_SR2) || \ - ((REGISTER) == I2C_Register_CCR) || \ - ((REGISTER) == I2C_Register_TRISE)) -/** - * @} - */ - -/** @defgroup I2C_SMBus_alert_pin_level - * @{ - */ - -#define I2C_SMBusAlert_Low ((uint16_t)0x2000) -#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) -#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ - ((ALERT) == I2C_SMBusAlert_High)) -/** - * @} - */ - -/** @defgroup I2C_PEC_position - * @{ - */ - -#define I2C_PECPosition_Next ((uint16_t)0x0800) -#define I2C_PECPosition_Current ((uint16_t)0xF7FF) -#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ - ((POSITION) == I2C_PECPosition_Current)) -/** - * @} - */ - -/** @defgroup I2C_NCAK_position - * @{ - */ - -#define I2C_NACKPosition_Next ((uint16_t)0x0800) -#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) -#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \ - ((POSITION) == I2C_NACKPosition_Current)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_BUF ((uint16_t)0x0400) -#define I2C_IT_EVT ((uint16_t)0x0200) -#define I2C_IT_ERR ((uint16_t)0x0100) -#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_SMBALERT ((uint32_t)0x01008000) -#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) -#define I2C_IT_PECERR ((uint32_t)0x01001000) -#define I2C_IT_OVR ((uint32_t)0x01000800) -#define I2C_IT_AF ((uint32_t)0x01000400) -#define I2C_IT_ARLO ((uint32_t)0x01000200) -#define I2C_IT_BERR ((uint32_t)0x01000100) -#define I2C_IT_TXE ((uint32_t)0x06000080) -#define I2C_IT_RXNE ((uint32_t)0x06000040) -#define I2C_IT_STOPF ((uint32_t)0x02000010) -#define I2C_IT_ADD10 ((uint32_t)0x02000008) -#define I2C_IT_BTF ((uint32_t)0x02000004) -#define I2C_IT_ADDR ((uint32_t)0x02000002) -#define I2C_IT_SB ((uint32_t)0x02000001) - -#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) - -#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ - ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ - ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ - ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ - ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ - ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ - ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) -/** - * @} - */ - -/** @defgroup I2C_flags_definition - * @{ - */ - -/** - * @brief SR2 register flags - */ - -#define I2C_FLAG_DUALF ((uint32_t)0x00800000) -#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) -#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) -#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) -#define I2C_FLAG_TRA ((uint32_t)0x00040000) -#define I2C_FLAG_BUSY ((uint32_t)0x00020000) -#define I2C_FLAG_MSL ((uint32_t)0x00010000) - -/** - * @brief SR1 register flags - */ - -#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) -#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) -#define I2C_FLAG_PECERR ((uint32_t)0x10001000) -#define I2C_FLAG_OVR ((uint32_t)0x10000800) -#define I2C_FLAG_AF ((uint32_t)0x10000400) -#define I2C_FLAG_ARLO ((uint32_t)0x10000200) -#define I2C_FLAG_BERR ((uint32_t)0x10000100) -#define I2C_FLAG_TXE ((uint32_t)0x10000080) -#define I2C_FLAG_RXNE ((uint32_t)0x10000040) -#define I2C_FLAG_STOPF ((uint32_t)0x10000010) -#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) -#define I2C_FLAG_BTF ((uint32_t)0x10000004) -#define I2C_FLAG_ADDR ((uint32_t)0x10000002) -#define I2C_FLAG_SB ((uint32_t)0x10000001) - -#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) - -#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ - ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ - ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ - ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ - ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ - ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ - ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ - ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ - ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ - ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ - ((FLAG) == I2C_FLAG_SB)) -/** - * @} - */ - -/** @defgroup I2C_Events - * @{ - */ - -/*======================================== - - I2C Master Events (Events grouped in order of communication) - ==========================================*/ -/** - * @brief Communication start - * - * After sending the START condition (I2C_GenerateSTART() function) the master - * has to wait for this event. It means that the Start condition has been correctly - * released on the I2C bus (the bus is free, no other devices is communicating). - * - */ -/* --EV5 */ -#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ - -/** - * @brief Address Acknowledge - * - * After checking on EV5 (start condition correctly released on the bus), the - * master sends the address of the slave(s) with which it will communicate - * (I2C_Send7bitAddress() function, it also determines the direction of the communication: - * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges - * his address. If an acknowledge is sent on the bus, one of the following events will - * be set: - * - * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - * event is set. - * - * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - * is set - * - * 3) In case of 10-Bit addressing mode, the master (just after generating the START - * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() - * function). Then master should wait on EV9. It means that the 10-bit addressing - * header has been correctly sent on the bus. Then master should send the second part of - * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master - * should wait for event EV6. - * - */ - -/* --EV6 */ -#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ -#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ -/* --EV9 */ -#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ - -/** - * @brief Communication events - * - * If a communication is established (START condition generated and slave address - * acknowledged) then the master has to check on one of the following events for - * communication procedures: - * - * 1) Master Receiver mode: The master has to wait on the event EV7 then to read - * the data received from the slave (I2C_ReceiveData() function). - * - * 2) Master Transmitter mode: The master has to send data (I2C_SendData() - * function) then to wait on event EV8 or EV8_2. - * These two events are similar: - * - EV8 means that the data has been written in the data register and is - * being shifted out. - * - EV8_2 means that the data has been physically shifted out and output - * on the bus. - * In most cases, using EV8 is sufficient for the application. - * Using EV8_2 leads to a slower communication but ensure more reliable test. - * EV8_2 is also more suitable than EV8 for testing on the last data transmission - * (before Stop condition generation). - * - * @note In case the user software does not guarantee that this event EV7 is - * managed before the current byte end of transfer, then user may check on EV7 - * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). - * In this case the communication may be slower. - * - */ - -/* Master RECEIVER mode -----------------------------*/ -/* --EV7 */ -#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ - -/* Master TRANSMITTER mode --------------------------*/ -/* --EV8 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ -/* --EV8_2 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ - - -/*======================================== - - I2C Slave Events (Events grouped in order of communication) - ==========================================*/ - -/** - * @brief Communication start events - * - * Wait on one of these events at the start of the communication. It means that - * the I2C peripheral detected a Start condition on the bus (generated by master - * device) followed by the peripheral address. The peripheral generates an ACK - * condition on the bus (if the acknowledge feature is enabled through function - * I2C_AcknowledgeConfig()) and the events listed above are set : - * - * 1) In normal case (only one address managed by the slave), when the address - * sent by the master matches the own address of the peripheral (configured by - * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set - * (where XXX could be TRANSMITTER or RECEIVER). - * - * 2) In case the address sent by the master matches the second address of the - * peripheral (configured by the function I2C_OwnAddress2Config() and enabled - * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED - * (where XXX could be TRANSMITTER or RECEIVER) are set. - * - * 3) In case the address sent by the master is General Call (address 0x00) and - * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) - * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. - * - */ - -/* --EV1 (all the events below are variants of EV1) */ -/* 1) Case of One Single Address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ - -/* 2) Case of Dual address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ - -/* 3) Case of General Call enabled for the slave */ -#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ - -/** - * @brief Communication events - * - * Wait on one of these events when EV1 has already been checked and: - * - * - Slave RECEIVER mode: - * - EV2: When the application is expecting a data byte to be received. - * - EV4: When the application is expecting the end of the communication: master - * sends a stop condition and data transmission is stopped. - * - * - Slave Transmitter mode: - * - EV3: When a byte has been transmitted by the slave and the application is expecting - * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and - * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be - * used when the user software doesn't guarantee the EV3 is managed before the - * current byte end of transfer. - * - EV3_2: When the master sends a NACK in order to tell slave that data transmission - * shall end (before sending the STOP condition). In this case slave has to stop sending - * data bytes and expect a Stop condition on the bus. - * - * @note In case the user software does not guarantee that the event EV2 is - * managed before the current byte end of transfer, then user may check on EV2 - * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). - * In this case the communication may be slower. - * - */ - -/* Slave RECEIVER mode --------------------------*/ -/* --EV2 */ -#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ -/* --EV4 */ -#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ - -/* Slave TRANSMITTER mode -----------------------*/ -/* --EV3 */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ -/* --EV3_2 */ -#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ - -/*=========================== End of Events Description ==========================================*/ - -#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ - ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ - ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) -/** - * @} - */ - -/** @defgroup I2C_own_address1 - * @{ - */ - -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) -/** - * @} - */ - -/** @defgroup I2C_clock_speed - * @{ - */ - -#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup I2C_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions - * @{ - */ - -void I2C_DeInit(I2C_TypeDef* I2Cx); -void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); - -/** - * @brief - **************************************************************************************** - * - * I2C State Monitoring Functions - * - **************************************************************************************** - * This I2C driver provides three different ways for I2C state monitoring - * depending on the application requirements and constraints: - * - * - * 1) Basic state monitoring: - * Using I2C_CheckEvent() function: - * It compares the status registers (SR1 and SR2) content to a given event - * (can be the combination of one or more flags). - * It returns SUCCESS if the current status includes the given flags - * and returns ERROR if one or more flags are missing in the current status. - * - When to use: - * - This function is suitable for most applications as well as for startup - * activity since the events are fully described in the product reference manual - * (RM0008). - * - It is also suitable for users who need to define their own events. - * - Limitations: - * - If an error occurs (ie. error flags are set besides to the monitored flags), - * the I2C_CheckEvent() function may return SUCCESS despite the communication - * hold or corrupted real state. - * In this case, it is advised to use error interrupts to monitor the error - * events and handle them in the interrupt IRQ handler. - * - * @note - * For error management, it is advised to use the following functions: - * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. - * Where x is the peripheral instance (I2C1, I2C2 ...) - * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() - * in order to determine which error occurred. - * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() - * and/or I2C_GenerateStop() in order to clear the error flag and source, - * and return to correct communication status. - * - * - * 2) Advanced state monitoring: - * Using the function I2C_GetLastEvent() which returns the image of both status - * registers in a single word (uint32_t) (Status Register 2 value is shifted left - * by 16 bits and concatenated to Status Register 1). - * - When to use: - * - This function is suitable for the same applications above but it allows to - * overcome the limitations of I2C_GetFlagStatus() function (see below). - * The returned value could be compared to events already defined in the - * library (stm32f10x_i2c.h) or to custom values defined by user. - * - This function is suitable when multiple flags are monitored at the same time. - * - At the opposite of I2C_CheckEvent() function, this function allows user to - * choose when an event is accepted (when all events flags are set and no - * other flags are set or just when the needed flags are set like - * I2C_CheckEvent() function). - * - Limitations: - * - User may need to define his own events. - * - Same remark concerning the error management is applicable for this - * function if user decides to check only regular communication flags (and - * ignores error flags). - * - * - * 3) Flag-based state monitoring: - * Using the function I2C_GetFlagStatus() which simply returns the status of - * one single flag (ie. I2C_FLAG_RXNE ...). - * - When to use: - * - This function could be used for specific applications or in debug phase. - * - It is suitable when only one flag checking is needed (most I2C events - * are monitored through multiple flags). - * - Limitations: - * - When calling this function, the Status register is accessed. Some flags are - * cleared when the status register is accessed. So checking the status - * of one Flag, may clear other ones. - * - Function may need to be called twice or more in order to monitor one - * single event. - * - */ - -/** - * - * 1) Basic state monitoring - ******************************************************************************* - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); -/** - * - * 2) Advanced state monitoring - ******************************************************************************* - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); -/** - * - * 3) Flag-based state monitoring - ******************************************************************************* - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -/** - * - ******************************************************************************* - */ - -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_I2C_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h deleted file mode 100644 index 7f5ab7642..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h +++ /dev/null @@ -1,140 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_iwdg.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the IWDG - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_IWDG_H -#define __STM32F10x_IWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup IWDG - * @{ - */ - -/** @defgroup IWDG_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Exported_Constants - * @{ - */ - -/** @defgroup IWDG_WriteAccess - * @{ - */ - -#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) -#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) -#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ - ((ACCESS) == IWDG_WriteAccess_Disable)) -/** - * @} - */ - -/** @defgroup IWDG_prescaler - * @{ - */ - -#define IWDG_Prescaler_4 ((uint8_t)0x00) -#define IWDG_Prescaler_8 ((uint8_t)0x01) -#define IWDG_Prescaler_16 ((uint8_t)0x02) -#define IWDG_Prescaler_32 ((uint8_t)0x03) -#define IWDG_Prescaler_64 ((uint8_t)0x04) -#define IWDG_Prescaler_128 ((uint8_t)0x05) -#define IWDG_Prescaler_256 ((uint8_t)0x06) -#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ - ((PRESCALER) == IWDG_Prescaler_8) || \ - ((PRESCALER) == IWDG_Prescaler_16) || \ - ((PRESCALER) == IWDG_Prescaler_32) || \ - ((PRESCALER) == IWDG_Prescaler_64) || \ - ((PRESCALER) == IWDG_Prescaler_128)|| \ - ((PRESCALER) == IWDG_Prescaler_256)) -/** - * @} - */ - -/** @defgroup IWDG_Flag - * @{ - */ - -#define IWDG_FLAG_PVU ((uint16_t)0x0001) -#define IWDG_FLAG_RVU ((uint16_t)0x0002) -#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) -#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup IWDG_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Exported_Functions - * @{ - */ - -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); -void IWDG_SetReload(uint16_t Reload); -void IWDG_ReloadCounter(void); -void IWDG_Enable(void); -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_IWDG_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h deleted file mode 100644 index 76e6ce91f..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h +++ /dev/null @@ -1,156 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_pwr.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the PWR firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_PWR_H -#define __STM32F10x_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup PWR - * @{ - */ - -/** @defgroup PWR_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Exported_Constants - * @{ - */ - -/** @defgroup PVD_detection_level - * @{ - */ - -#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) -#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) -#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) -#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) -#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) -#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) -#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) -#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \ - ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \ - ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \ - ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9)) -/** - * @} - */ - -/** @defgroup Regulator_state_is_STOP_mode - * @{ - */ - -#define PWR_Regulator_ON ((uint32_t)0x00000000) -#define PWR_Regulator_LowPower ((uint32_t)0x00000001) -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ - ((REGULATOR) == PWR_Regulator_LowPower)) -/** - * @} - */ - -/** @defgroup STOP_mode_entry - * @{ - */ - -#define PWR_STOPEntry_WFI ((uint8_t)0x01) -#define PWR_STOPEntry_WFE ((uint8_t)0x02) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) - -/** - * @} - */ - -/** @defgroup PWR_Flag - * @{ - */ - -#define PWR_FLAG_WU ((uint32_t)0x00000001) -#define PWR_FLAG_SB ((uint32_t)0x00000002) -#define PWR_FLAG_PVDO ((uint32_t)0x00000004) -#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ - ((FLAG) == PWR_FLAG_PVDO)) - -#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup PWR_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Exported_Functions - * @{ - */ - -void PWR_DeInit(void); -void PWR_BackupAccessCmd(FunctionalState NewState); -void PWR_PVDCmd(FunctionalState NewState); -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); -void PWR_WakeUpPinCmd(FunctionalState NewState); -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); -void PWR_EnterSTANDBYMode(void); -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); -void PWR_ClearFlag(uint32_t PWR_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_PWR_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h deleted file mode 100644 index b3b7d821d..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h +++ /dev/null @@ -1,727 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_rcc.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the RCC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_RCC_H -#define __STM32F10x_RCC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/** @defgroup RCC_Exported_Types - * @{ - */ - -typedef struct -{ - uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */ - uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */ - uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */ - uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */ - uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */ -}RCC_ClocksTypeDef; - -/** - * @} - */ - -/** @defgroup RCC_Exported_Constants - * @{ - */ - -/** @defgroup HSE_configuration - * @{ - */ - -#define RCC_HSE_OFF ((uint32_t)0x00000000) -#define RCC_HSE_ON ((uint32_t)0x00010000) -#define RCC_HSE_Bypass ((uint32_t)0x00040000) -#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ - ((HSE) == RCC_HSE_Bypass)) - -/** - * @} - */ - -/** @defgroup PLL_entry_clock_source - * @{ - */ - -#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL) - #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) - #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) - #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ - ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ - ((SOURCE) == RCC_PLLSource_HSE_Div2)) -#else - #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) - #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ - ((SOURCE) == RCC_PLLSource_PREDIV1)) -#endif /* STM32F10X_CL */ - -/** - * @} - */ - -/** @defgroup PLL_multiplication_factor - * @{ - */ -#ifndef STM32F10X_CL - #define RCC_PLLMul_2 ((uint32_t)0x00000000) - #define RCC_PLLMul_3 ((uint32_t)0x00040000) - #define RCC_PLLMul_4 ((uint32_t)0x00080000) - #define RCC_PLLMul_5 ((uint32_t)0x000C0000) - #define RCC_PLLMul_6 ((uint32_t)0x00100000) - #define RCC_PLLMul_7 ((uint32_t)0x00140000) - #define RCC_PLLMul_8 ((uint32_t)0x00180000) - #define RCC_PLLMul_9 ((uint32_t)0x001C0000) - #define RCC_PLLMul_10 ((uint32_t)0x00200000) - #define RCC_PLLMul_11 ((uint32_t)0x00240000) - #define RCC_PLLMul_12 ((uint32_t)0x00280000) - #define RCC_PLLMul_13 ((uint32_t)0x002C0000) - #define RCC_PLLMul_14 ((uint32_t)0x00300000) - #define RCC_PLLMul_15 ((uint32_t)0x00340000) - #define RCC_PLLMul_16 ((uint32_t)0x00380000) - #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ - ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ - ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ - ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ - ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ - ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ - ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ - ((MUL) == RCC_PLLMul_16)) - -#else - #define RCC_PLLMul_4 ((uint32_t)0x00080000) - #define RCC_PLLMul_5 ((uint32_t)0x000C0000) - #define RCC_PLLMul_6 ((uint32_t)0x00100000) - #define RCC_PLLMul_7 ((uint32_t)0x00140000) - #define RCC_PLLMul_8 ((uint32_t)0x00180000) - #define RCC_PLLMul_9 ((uint32_t)0x001C0000) - #define RCC_PLLMul_6_5 ((uint32_t)0x00340000) - - #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ - ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ - ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ - ((MUL) == RCC_PLLMul_6_5)) -#endif /* STM32F10X_CL */ -/** - * @} - */ - -/** @defgroup PREDIV1_division_factor - * @{ - */ -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) - #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) - #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) - #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) - #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) - #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) - #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) - #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) - #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) - #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) - #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) - #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) - #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) - #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) - #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) - #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) - #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) - - #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ - ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ - ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ - ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ - ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ - ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ - ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ - ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) -#endif -/** - * @} - */ - - -/** @defgroup PREDIV1_clock_source - * @{ - */ -#ifdef STM32F10X_CL -/* PREDIV1 clock source (for STM32 connectivity line devices) */ - #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) - #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) - - #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \ - ((SOURCE) == RCC_PREDIV1_Source_PLL2)) -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/* PREDIV1 clock source (for STM32 Value line devices) */ - #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) - - #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) -#endif -/** - * @} - */ - -#ifdef STM32F10X_CL -/** @defgroup PREDIV2_division_factor - * @{ - */ - - #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) - #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) - #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) - #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) - #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) - #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) - #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) - #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) - #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) - #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) - #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) - #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) - #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) - #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) - #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) - #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) - - #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \ - ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \ - ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \ - ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \ - ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \ - ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \ - ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \ - ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16)) -/** - * @} - */ - - -/** @defgroup PLL2_multiplication_factor - * @{ - */ - - #define RCC_PLL2Mul_8 ((uint32_t)0x00000600) - #define RCC_PLL2Mul_9 ((uint32_t)0x00000700) - #define RCC_PLL2Mul_10 ((uint32_t)0x00000800) - #define RCC_PLL2Mul_11 ((uint32_t)0x00000900) - #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) - #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) - #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) - #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) - #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) - - #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \ - ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \ - ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \ - ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \ - ((MUL) == RCC_PLL2Mul_20)) -/** - * @} - */ - - -/** @defgroup PLL3_multiplication_factor - * @{ - */ - - #define RCC_PLL3Mul_8 ((uint32_t)0x00006000) - #define RCC_PLL3Mul_9 ((uint32_t)0x00007000) - #define RCC_PLL3Mul_10 ((uint32_t)0x00008000) - #define RCC_PLL3Mul_11 ((uint32_t)0x00009000) - #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) - #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) - #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) - #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) - #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) - - #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \ - ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \ - ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \ - ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \ - ((MUL) == RCC_PLL3Mul_20)) -/** - * @} - */ - -#endif /* STM32F10X_CL */ - - -/** @defgroup System_clock_source - * @{ - */ - -#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) -#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) -#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) -#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ - ((SOURCE) == RCC_SYSCLKSource_HSE) || \ - ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) -/** - * @} - */ - -/** @defgroup AHB_clock_source - * @{ - */ - -#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) -#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) -#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) -#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) -#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) -#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) -#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) -#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) -#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) -#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ - ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ - ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ - ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ - ((HCLK) == RCC_SYSCLK_Div512)) -/** - * @} - */ - -/** @defgroup APB1_APB2_clock_source - * @{ - */ - -#define RCC_HCLK_Div1 ((uint32_t)0x00000000) -#define RCC_HCLK_Div2 ((uint32_t)0x00000400) -#define RCC_HCLK_Div4 ((uint32_t)0x00000500) -#define RCC_HCLK_Div8 ((uint32_t)0x00000600) -#define RCC_HCLK_Div16 ((uint32_t)0x00000700) -#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ - ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ - ((PCLK) == RCC_HCLK_Div16)) -/** - * @} - */ - -/** @defgroup RCC_Interrupt_source - * @{ - */ - -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_LSERDY ((uint8_t)0x02) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_CSS ((uint8_t)0x80) - -#ifndef STM32F10X_CL - #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) - #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) - #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) -#else - #define RCC_IT_PLL2RDY ((uint8_t)0x20) - #define RCC_IT_PLL3RDY ((uint8_t)0x40) - #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) - #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ - ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY)) - #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) -#endif /* STM32F10X_CL */ - - -/** - * @} - */ - -#ifndef STM32F10X_CL -/** @defgroup USB_Device_clock_source - * @{ - */ - - #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) - #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) - - #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ - ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) -/** - * @} - */ -#else -/** @defgroup USB_OTG_FS_clock_source - * @{ - */ - #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00) - #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01) - - #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \ - ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2)) -/** - * @} - */ -#endif /* STM32F10X_CL */ - - -#ifdef STM32F10X_CL -/** @defgroup I2S2_clock_source - * @{ - */ - #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) - #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) - - #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \ - ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO)) -/** - * @} - */ - -/** @defgroup I2S3_clock_source - * @{ - */ - #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) - #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) - - #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \ - ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) -/** - * @} - */ -#endif /* STM32F10X_CL */ - - -/** @defgroup ADC_clock_source - * @{ - */ - -#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) -#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) -#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) -#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) -#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ - ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) -/** - * @} - */ - -/** @defgroup LSE_configuration - * @{ - */ - -#define RCC_LSE_OFF ((uint8_t)0x00) -#define RCC_LSE_ON ((uint8_t)0x01) -#define RCC_LSE_Bypass ((uint8_t)0x04) -#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ - ((LSE) == RCC_LSE_Bypass)) -/** - * @} - */ - -/** @defgroup RTC_clock_source - * @{ - */ - -#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) -#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) -#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) -#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ - ((SOURCE) == RCC_RTCCLKSource_LSI) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) -/** - * @} - */ - -/** @defgroup AHB_peripheral - * @{ - */ - -#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) -#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) -#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) -#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) -#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) - -#ifndef STM32F10X_CL - #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) - #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) - #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) -#else - #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) - #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) - #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) - #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) - - #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00)) - #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00)) -#endif /* STM32F10X_CL */ -/** - * @} - */ - -/** @defgroup APB2_peripheral - * @{ - */ - -#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) -#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) -#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) -#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) -#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) -#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) -#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) -#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) -#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) -#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) -#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) -#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) -#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) -#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) -#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) -#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) -#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) -#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) -#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) -#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) -#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) - -#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup APB1_peripheral - * @{ - */ - -#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) -#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) -#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) -#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) -#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) -#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) -#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) -#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) -#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) -#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) -#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) -#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) -#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) -#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) -#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) -#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) -#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) -#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) -#define RCC_APB1Periph_USB ((uint32_t)0x00800000) -#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) -#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) -#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) -#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) -#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) -#define RCC_APB1Periph_CEC ((uint32_t)0x40000000) - -#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00)) - -/** - * @} - */ - -/** @defgroup Clock_source_to_output_on_MCO_pin - * @{ - */ - -#define RCC_MCO_NoClock ((uint8_t)0x00) -#define RCC_MCO_SYSCLK ((uint8_t)0x04) -#define RCC_MCO_HSI ((uint8_t)0x05) -#define RCC_MCO_HSE ((uint8_t)0x06) -#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) - -#ifndef STM32F10X_CL - #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ - ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ - ((MCO) == RCC_MCO_PLLCLK_Div2)) -#else - #define RCC_MCO_PLL2CLK ((uint8_t)0x08) - #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) - #define RCC_MCO_XT1 ((uint8_t)0x0A) - #define RCC_MCO_PLL3CLK ((uint8_t)0x0B) - - #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ - ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ - ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \ - ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \ - ((MCO) == RCC_MCO_PLL3CLK)) -#endif /* STM32F10X_CL */ - -/** - * @} - */ - -/** @defgroup RCC_Flag - * @{ - */ - -#define RCC_FLAG_HSIRDY ((uint8_t)0x21) -#define RCC_FLAG_HSERDY ((uint8_t)0x31) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39) -#define RCC_FLAG_LSERDY ((uint8_t)0x41) -#define RCC_FLAG_LSIRDY ((uint8_t)0x61) -#define RCC_FLAG_PINRST ((uint8_t)0x7A) -#define RCC_FLAG_PORRST ((uint8_t)0x7B) -#define RCC_FLAG_SFTRST ((uint8_t)0x7C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) - -#ifndef STM32F10X_CL - #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ - ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ - ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ - ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ - ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ - ((FLAG) == RCC_FLAG_LPWRRST)) -#else - #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) - #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) - #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ - ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ - ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \ - ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ - ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ - ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ - ((FLAG) == RCC_FLAG_LPWRRST)) -#endif /* STM32F10X_CL */ - -#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RCC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup RCC_Exported_Functions - * @{ - */ - -void RCC_DeInit(void); -void RCC_HSEConfig(uint32_t RCC_HSE); -ErrorStatus RCC_WaitForHSEStartUp(void); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); -void RCC_PLLCmd(FunctionalState NewState); - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) - void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); -#endif - -#ifdef STM32F10X_CL - void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); - void RCC_PLL2Config(uint32_t RCC_PLL2Mul); - void RCC_PLL2Cmd(FunctionalState NewState); - void RCC_PLL3Config(uint32_t RCC_PLL3Mul); - void RCC_PLL3Cmd(FunctionalState NewState); -#endif /* STM32F10X_CL */ - -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); -uint8_t RCC_GetSYSCLKSource(void); -void RCC_HCLKConfig(uint32_t RCC_SYSCLK); -void RCC_PCLK1Config(uint32_t RCC_HCLK); -void RCC_PCLK2Config(uint32_t RCC_HCLK); -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); - -#ifndef STM32F10X_CL - void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); -#else - void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource); -#endif /* STM32F10X_CL */ - -void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); - -#ifdef STM32F10X_CL - void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); - void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); -#endif /* STM32F10X_CL */ - -void RCC_LSEConfig(uint8_t RCC_LSE); -void RCC_LSICmd(FunctionalState NewState); -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); -void RCC_RTCCLKCmd(FunctionalState NewState); -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); - -#ifdef STM32F10X_CL -void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -#endif /* STM32F10X_CL */ - -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_BackupResetCmd(FunctionalState NewState); -void RCC_ClockSecuritySystemCmd(FunctionalState NewState); -void RCC_MCOConfig(uint8_t RCC_MCO); -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); -void RCC_ClearFlag(void); -ITStatus RCC_GetITStatus(uint8_t RCC_IT); -void RCC_ClearITPendingBit(uint8_t RCC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_RCC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h deleted file mode 100644 index 214a5893a..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h +++ /dev/null @@ -1,135 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_rtc.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the RTC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_RTC_H -#define __STM32F10x_RTC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RTC - * @{ - */ - -/** @defgroup RTC_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Exported_Constants - * @{ - */ - -/** @defgroup RTC_interrupts_define - * @{ - */ - -#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */ -#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */ -#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */ -#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00)) -#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \ - ((IT) == RTC_IT_SEC)) -/** - * @} - */ - -/** @defgroup RTC_interrupts_flags - * @{ - */ - -#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */ -#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */ -#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */ -#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */ -#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */ -#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00)) -#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \ - ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \ - ((FLAG) == RTC_FLAG_SEC)) -#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RTC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions - * @{ - */ - -void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); -void RTC_EnterConfigMode(void); -void RTC_ExitConfigMode(void); -uint32_t RTC_GetCounter(void); -void RTC_SetCounter(uint32_t CounterValue); -void RTC_SetPrescaler(uint32_t PrescalerValue); -void RTC_SetAlarm(uint32_t AlarmValue); -uint32_t RTC_GetDivider(void); -void RTC_WaitForLastTask(void); -void RTC_WaitForSynchro(void); -FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); -void RTC_ClearFlag(uint16_t RTC_FLAG); -ITStatus RTC_GetITStatus(uint16_t RTC_IT); -void RTC_ClearITPendingBit(uint16_t RTC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_RTC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h deleted file mode 100644 index 40cfdedc3..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h +++ /dev/null @@ -1,531 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_sdio.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the SDIO firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_SDIO_H -#define __STM32F10x_SDIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SDIO - * @{ - */ - -/** @defgroup SDIO_Exported_Types - * @{ - */ - -typedef struct -{ - uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref SDIO_Clock_Edge */ - - uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is - enabled or disabled. - This parameter can be a value of @ref SDIO_Clock_Bypass */ - - uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or - disabled when the bus is idle. - This parameter can be a value of @ref SDIO_Clock_Power_Save */ - - uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width. - This parameter can be a value of @ref SDIO_Bus_Wide */ - - uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. - This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ - - uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. - This parameter can be a value between 0x00 and 0xFF. */ - -} SDIO_InitTypeDef; - -typedef struct -{ - uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent - to a card as part of a command message. If a command - contains an argument, it must be loaded into this register - before writing the command to the command register */ - - uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ - - uint32_t SDIO_Response; /*!< Specifies the SDIO response type. - This parameter can be a value of @ref SDIO_Response_Type */ - - uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled. - This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ - - uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) - is enabled or disabled. - This parameter can be a value of @ref SDIO_CPSM_State */ -} SDIO_CmdInitTypeDef; - -typedef struct -{ - uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ - - uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */ - - uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer. - This parameter can be a value of @ref SDIO_Data_Block_Size */ - - uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer - is a read or write. - This parameter can be a value of @ref SDIO_Transfer_Direction */ - - uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode. - This parameter can be a value of @ref SDIO_Transfer_Type */ - - uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) - is enabled or disabled. - This parameter can be a value of @ref SDIO_DPSM_State */ -} SDIO_DataInitTypeDef; - -/** - * @} - */ - -/** @defgroup SDIO_Exported_Constants - * @{ - */ - -/** @defgroup SDIO_Clock_Edge - * @{ - */ - -#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) -#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) -#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ - ((EDGE) == SDIO_ClockEdge_Falling)) -/** - * @} - */ - -/** @defgroup SDIO_Clock_Bypass - * @{ - */ - -#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) -#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) -#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ - ((BYPASS) == SDIO_ClockBypass_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Clock_Power_Save - * @{ - */ - -#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) -#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) -#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ - ((SAVE) == SDIO_ClockPowerSave_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Bus_Wide - * @{ - */ - -#define SDIO_BusWide_1b ((uint32_t)0x00000000) -#define SDIO_BusWide_4b ((uint32_t)0x00000800) -#define SDIO_BusWide_8b ((uint32_t)0x00001000) -#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ - ((WIDE) == SDIO_BusWide_8b)) - -/** - * @} - */ - -/** @defgroup SDIO_Hardware_Flow_Control - * @{ - */ - -#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) -#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) -#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ - ((CONTROL) == SDIO_HardwareFlowControl_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Power_State - * @{ - */ - -#define SDIO_PowerState_OFF ((uint32_t)0x00000000) -#define SDIO_PowerState_ON ((uint32_t)0x00000003) -#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) -/** - * @} - */ - - -/** @defgroup SDIO_Interrupt_sources - * @{ - */ - -#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) -#define SDIO_IT_CMDREND ((uint32_t)0x00000040) -#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) -#define SDIO_IT_DATAEND ((uint32_t)0x00000100) -#define SDIO_IT_STBITERR ((uint32_t)0x00000200) -#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) -#define SDIO_IT_CMDACT ((uint32_t)0x00000800) -#define SDIO_IT_TXACT ((uint32_t)0x00001000) -#define SDIO_IT_RXACT ((uint32_t)0x00002000) -#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) -#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) -#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) -#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) -#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) -/** - * @} - */ - -/** @defgroup SDIO_Command_Index - * @{ - */ - -#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) -/** - * @} - */ - -/** @defgroup SDIO_Response_Type - * @{ - */ - -#define SDIO_Response_No ((uint32_t)0x00000000) -#define SDIO_Response_Short ((uint32_t)0x00000040) -#define SDIO_Response_Long ((uint32_t)0x000000C0) -#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ - ((RESPONSE) == SDIO_Response_Short) || \ - ((RESPONSE) == SDIO_Response_Long)) -/** - * @} - */ - -/** @defgroup SDIO_Wait_Interrupt_State - * @{ - */ - -#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ -#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ -#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ -#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ - ((WAIT) == SDIO_Wait_Pend)) -/** - * @} - */ - -/** @defgroup SDIO_CPSM_State - * @{ - */ - -#define SDIO_CPSM_Disable ((uint32_t)0x00000000) -#define SDIO_CPSM_Enable ((uint32_t)0x00000400) -#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) -/** - * @} - */ - -/** @defgroup SDIO_Response_Registers - * @{ - */ - -#define SDIO_RESP1 ((uint32_t)0x00000000) -#define SDIO_RESP2 ((uint32_t)0x00000004) -#define SDIO_RESP3 ((uint32_t)0x00000008) -#define SDIO_RESP4 ((uint32_t)0x0000000C) -#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ - ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) -/** - * @} - */ - -/** @defgroup SDIO_Data_Length - * @{ - */ - -#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) -/** - * @} - */ - -/** @defgroup SDIO_Data_Block_Size - * @{ - */ - -#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) -#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) -#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) -#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) -#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) -#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) -#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) -#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) -#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) -#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) -#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) -#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) -#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) -#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) -#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) -#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ - ((SIZE) == SDIO_DataBlockSize_2b) || \ - ((SIZE) == SDIO_DataBlockSize_4b) || \ - ((SIZE) == SDIO_DataBlockSize_8b) || \ - ((SIZE) == SDIO_DataBlockSize_16b) || \ - ((SIZE) == SDIO_DataBlockSize_32b) || \ - ((SIZE) == SDIO_DataBlockSize_64b) || \ - ((SIZE) == SDIO_DataBlockSize_128b) || \ - ((SIZE) == SDIO_DataBlockSize_256b) || \ - ((SIZE) == SDIO_DataBlockSize_512b) || \ - ((SIZE) == SDIO_DataBlockSize_1024b) || \ - ((SIZE) == SDIO_DataBlockSize_2048b) || \ - ((SIZE) == SDIO_DataBlockSize_4096b) || \ - ((SIZE) == SDIO_DataBlockSize_8192b) || \ - ((SIZE) == SDIO_DataBlockSize_16384b)) -/** - * @} - */ - -/** @defgroup SDIO_Transfer_Direction - * @{ - */ - -#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) -#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) -#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ - ((DIR) == SDIO_TransferDir_ToSDIO)) -/** - * @} - */ - -/** @defgroup SDIO_Transfer_Type - * @{ - */ - -#define SDIO_TransferMode_Block ((uint32_t)0x00000000) -#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) -#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ - ((MODE) == SDIO_TransferMode_Block)) -/** - * @} - */ - -/** @defgroup SDIO_DPSM_State - * @{ - */ - -#define SDIO_DPSM_Disable ((uint32_t)0x00000000) -#define SDIO_DPSM_Enable ((uint32_t)0x00000001) -#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) -/** - * @} - */ - -/** @defgroup SDIO_Flags - * @{ - */ - -#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) -#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) -#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) -#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) -#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) -#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) -#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) -#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) -#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) -#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) -#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) -#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) -#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) -#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ - ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ - ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ - ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ - ((FLAG) == SDIO_FLAG_TXUNDERR) || \ - ((FLAG) == SDIO_FLAG_RXOVERR) || \ - ((FLAG) == SDIO_FLAG_CMDREND) || \ - ((FLAG) == SDIO_FLAG_CMDSENT) || \ - ((FLAG) == SDIO_FLAG_DATAEND) || \ - ((FLAG) == SDIO_FLAG_STBITERR) || \ - ((FLAG) == SDIO_FLAG_DBCKEND) || \ - ((FLAG) == SDIO_FLAG_CMDACT) || \ - ((FLAG) == SDIO_FLAG_TXACT) || \ - ((FLAG) == SDIO_FLAG_RXACT) || \ - ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ - ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ - ((FLAG) == SDIO_FLAG_TXFIFOF) || \ - ((FLAG) == SDIO_FLAG_RXFIFOF) || \ - ((FLAG) == SDIO_FLAG_TXFIFOE) || \ - ((FLAG) == SDIO_FLAG_RXFIFOE) || \ - ((FLAG) == SDIO_FLAG_TXDAVL) || \ - ((FLAG) == SDIO_FLAG_RXDAVL) || \ - ((FLAG) == SDIO_FLAG_SDIOIT) || \ - ((FLAG) == SDIO_FLAG_CEATAEND)) - -#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) - -#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ - ((IT) == SDIO_IT_DCRCFAIL) || \ - ((IT) == SDIO_IT_CTIMEOUT) || \ - ((IT) == SDIO_IT_DTIMEOUT) || \ - ((IT) == SDIO_IT_TXUNDERR) || \ - ((IT) == SDIO_IT_RXOVERR) || \ - ((IT) == SDIO_IT_CMDREND) || \ - ((IT) == SDIO_IT_CMDSENT) || \ - ((IT) == SDIO_IT_DATAEND) || \ - ((IT) == SDIO_IT_STBITERR) || \ - ((IT) == SDIO_IT_DBCKEND) || \ - ((IT) == SDIO_IT_CMDACT) || \ - ((IT) == SDIO_IT_TXACT) || \ - ((IT) == SDIO_IT_RXACT) || \ - ((IT) == SDIO_IT_TXFIFOHE) || \ - ((IT) == SDIO_IT_RXFIFOHF) || \ - ((IT) == SDIO_IT_TXFIFOF) || \ - ((IT) == SDIO_IT_RXFIFOF) || \ - ((IT) == SDIO_IT_TXFIFOE) || \ - ((IT) == SDIO_IT_RXFIFOE) || \ - ((IT) == SDIO_IT_TXDAVL) || \ - ((IT) == SDIO_IT_RXDAVL) || \ - ((IT) == SDIO_IT_SDIOIT) || \ - ((IT) == SDIO_IT_CEATAEND)) - -#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) - -/** - * @} - */ - -/** @defgroup SDIO_Read_Wait_Mode - * @{ - */ - -#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) -#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) -#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ - ((MODE) == SDIO_ReadWaitMode_DATA2)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup SDIO_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Exported_Functions - * @{ - */ - -void SDIO_DeInit(void); -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_ClockCmd(FunctionalState NewState); -void SDIO_SetPowerState(uint32_t SDIO_PowerState); -uint32_t SDIO_GetPowerState(void); -void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); -void SDIO_DMACmd(FunctionalState NewState); -void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); -uint8_t SDIO_GetCommandResponse(void); -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); -void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); -void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); -uint32_t SDIO_GetDataCounter(void); -uint32_t SDIO_ReadData(void); -void SDIO_WriteData(uint32_t Data); -uint32_t SDIO_GetFIFOCount(void); -void SDIO_StartSDIOReadWait(FunctionalState NewState); -void SDIO_StopSDIOReadWait(FunctionalState NewState); -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); -void SDIO_SetSDIOOperation(FunctionalState NewState); -void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); -void SDIO_CommandCompletionCmd(FunctionalState NewState); -void SDIO_CEATAITCmd(FunctionalState NewState); -void SDIO_SendCEATACmd(FunctionalState NewState); -FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); -void SDIO_ClearFlag(uint32_t SDIO_FLAG); -ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); -void SDIO_ClearITPendingBit(uint32_t SDIO_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_SDIO_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h deleted file mode 100644 index 6056c4c6b..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h +++ /dev/null @@ -1,487 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_spi.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the SPI firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_SPI_H -#define __STM32F10x_SPI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/** @defgroup SPI_Exported_Types - * @{ - */ - -/** - * @brief SPI Init structure definition - */ - -typedef struct -{ - uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref SPI_data_direction */ - - uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. - This parameter can be a value of @ref SPI_mode */ - - uint16_t SPI_DataSize; /*!< Specifies the SPI data size. - This parameter can be a value of @ref SPI_data_size */ - - uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_management */ - - uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_BaudRate_Prescaler. - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_MSB_LSB_transmission */ - - uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ -}SPI_InitTypeDef; - -/** - * @brief I2S Init structure definition - */ - -typedef struct -{ - - uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. - This parameter can be a value of @ref I2S_Mode */ - - uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. - This parameter can be a value of @ref I2S_Standard */ - - uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. - This parameter can be a value of @ref I2S_Data_Format */ - - uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. - This parameter can be a value of @ref I2S_MCLK_Output */ - - uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. - This parameter can be a value of @ref I2S_Audio_Frequency */ - - uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. - This parameter can be a value of @ref I2S_Clock_Polarity */ -}I2S_InitTypeDef; - -/** - * @} - */ - -/** @defgroup SPI_Exported_Constants - * @{ - */ - -#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ - ((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -/** @defgroup SPI_data_direction - * @{ - */ - -#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) -#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) -#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) -#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) -#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ - ((MODE) == SPI_Direction_2Lines_RxOnly) || \ - ((MODE) == SPI_Direction_1Line_Rx) || \ - ((MODE) == SPI_Direction_1Line_Tx)) -/** - * @} - */ - -/** @defgroup SPI_mode - * @{ - */ - -#define SPI_Mode_Master ((uint16_t)0x0104) -#define SPI_Mode_Slave ((uint16_t)0x0000) -#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ - ((MODE) == SPI_Mode_Slave)) -/** - * @} - */ - -/** @defgroup SPI_data_size - * @{ - */ - -#define SPI_DataSize_16b ((uint16_t)0x0800) -#define SPI_DataSize_8b ((uint16_t)0x0000) -#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ - ((DATASIZE) == SPI_DataSize_8b)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Polarity - * @{ - */ - -#define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High ((uint16_t)0x0002) -#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ - ((CPOL) == SPI_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Phase - * @{ - */ - -#define SPI_CPHA_1Edge ((uint16_t)0x0000) -#define SPI_CPHA_2Edge ((uint16_t)0x0001) -#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ - ((CPHA) == SPI_CPHA_2Edge)) -/** - * @} - */ - -/** @defgroup SPI_Slave_Select_management - * @{ - */ - -#define SPI_NSS_Soft ((uint16_t)0x0200) -#define SPI_NSS_Hard ((uint16_t)0x0000) -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ - ((NSS) == SPI_NSS_Hard)) -/** - * @} - */ - -/** @defgroup SPI_BaudRate_Prescaler - * @{ - */ - -#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) -#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) -#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) -#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) -#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) -#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) -#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) -#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_256)) -/** - * @} - */ - -/** @defgroup SPI_MSB_LSB_transmission - * @{ - */ - -#define SPI_FirstBit_MSB ((uint16_t)0x0000) -#define SPI_FirstBit_LSB ((uint16_t)0x0080) -#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ - ((BIT) == SPI_FirstBit_LSB)) -/** - * @} - */ - -/** @defgroup I2S_Mode - * @{ - */ - -#define I2S_Mode_SlaveTx ((uint16_t)0x0000) -#define I2S_Mode_SlaveRx ((uint16_t)0x0100) -#define I2S_Mode_MasterTx ((uint16_t)0x0200) -#define I2S_Mode_MasterRx ((uint16_t)0x0300) -#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ - ((MODE) == I2S_Mode_SlaveRx) || \ - ((MODE) == I2S_Mode_MasterTx) || \ - ((MODE) == I2S_Mode_MasterRx) ) -/** - * @} - */ - -/** @defgroup I2S_Standard - * @{ - */ - -#define I2S_Standard_Phillips ((uint16_t)0x0000) -#define I2S_Standard_MSB ((uint16_t)0x0010) -#define I2S_Standard_LSB ((uint16_t)0x0020) -#define I2S_Standard_PCMShort ((uint16_t)0x0030) -#define I2S_Standard_PCMLong ((uint16_t)0x00B0) -#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ - ((STANDARD) == I2S_Standard_MSB) || \ - ((STANDARD) == I2S_Standard_LSB) || \ - ((STANDARD) == I2S_Standard_PCMShort) || \ - ((STANDARD) == I2S_Standard_PCMLong)) -/** - * @} - */ - -/** @defgroup I2S_Data_Format - * @{ - */ - -#define I2S_DataFormat_16b ((uint16_t)0x0000) -#define I2S_DataFormat_16bextended ((uint16_t)0x0001) -#define I2S_DataFormat_24b ((uint16_t)0x0003) -#define I2S_DataFormat_32b ((uint16_t)0x0005) -#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ - ((FORMAT) == I2S_DataFormat_16bextended) || \ - ((FORMAT) == I2S_DataFormat_24b) || \ - ((FORMAT) == I2S_DataFormat_32b)) -/** - * @} - */ - -/** @defgroup I2S_MCLK_Output - * @{ - */ - -#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) -#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) -#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ - ((OUTPUT) == I2S_MCLKOutput_Disable)) -/** - * @} - */ - -/** @defgroup I2S_Audio_Frequency - * @{ - */ - -#define I2S_AudioFreq_192k ((uint32_t)192000) -#define I2S_AudioFreq_96k ((uint32_t)96000) -#define I2S_AudioFreq_48k ((uint32_t)48000) -#define I2S_AudioFreq_44k ((uint32_t)44100) -#define I2S_AudioFreq_32k ((uint32_t)32000) -#define I2S_AudioFreq_22k ((uint32_t)22050) -#define I2S_AudioFreq_16k ((uint32_t)16000) -#define I2S_AudioFreq_11k ((uint32_t)11025) -#define I2S_AudioFreq_8k ((uint32_t)8000) -#define I2S_AudioFreq_Default ((uint32_t)2) - -#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ - ((FREQ) <= I2S_AudioFreq_192k)) || \ - ((FREQ) == I2S_AudioFreq_Default)) -/** - * @} - */ - -/** @defgroup I2S_Clock_Polarity - * @{ - */ - -#define I2S_CPOL_Low ((uint16_t)0x0000) -#define I2S_CPOL_High ((uint16_t)0x0008) -#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ - ((CPOL) == I2S_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_I2S_DMA_transfer_requests - * @{ - */ - -#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) -#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) -#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) -/** - * @} - */ - -/** @defgroup SPI_NSS_internal_software_management - * @{ - */ - -#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) -#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) -#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ - ((INTERNAL) == SPI_NSSInternalSoft_Reset)) -/** - * @} - */ - -/** @defgroup SPI_CRC_Transmit_Receive - * @{ - */ - -#define SPI_CRC_Tx ((uint8_t)0x00) -#define SPI_CRC_Rx ((uint8_t)0x01) -#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) -/** - * @} - */ - -/** @defgroup SPI_direction_transmit_receive - * @{ - */ - -#define SPI_Direction_Rx ((uint16_t)0xBFFF) -#define SPI_Direction_Tx ((uint16_t)0x4000) -#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ - ((DIRECTION) == SPI_Direction_Tx)) -/** - * @} - */ - -/** @defgroup SPI_I2S_interrupts_definition - * @{ - */ - -#define SPI_I2S_IT_TXE ((uint8_t)0x71) -#define SPI_I2S_IT_RXNE ((uint8_t)0x60) -#define SPI_I2S_IT_ERR ((uint8_t)0x50) -#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_I2S_IT_RXNE) || \ - ((IT) == SPI_I2S_IT_ERR)) -#define SPI_I2S_IT_OVR ((uint8_t)0x56) -#define SPI_IT_MODF ((uint8_t)0x55) -#define SPI_IT_CRCERR ((uint8_t)0x54) -#define I2S_IT_UDR ((uint8_t)0x53) -#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) -#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \ - ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR)) -/** - * @} - */ - -/** @defgroup SPI_I2S_flags_definition - * @{ - */ - -#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) -#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) -#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) -#define I2S_FLAG_UDR ((uint16_t)0x0008) -#define SPI_FLAG_CRCERR ((uint16_t)0x0010) -#define SPI_FLAG_MODF ((uint16_t)0x0020) -#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) -#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) -#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) -#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ - ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ - ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ - ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)) -/** - * @} - */ - -/** @defgroup SPI_CRC_polynomial - * @{ - */ - -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup SPI_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup SPI_Exported_Functions - * @{ - */ - -void SPI_I2S_DeInit(SPI_TypeDef* SPIx); -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); -void SPI_TransmitCRC(SPI_TypeDef* SPIx); -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_SPI_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h deleted file mode 100644 index cd7ac3e9c..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h +++ /dev/null @@ -1,1164 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_tim.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the TIM firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_TIM_H -#define __STM32F10x_TIM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup TIM - * @{ - */ - -/** @defgroup TIM_Exported_Types - * @{ - */ - -/** - * @brief TIM Time Base Init structure definition - * @note This structure is used with all TIMx except for TIM6 and TIM7. - */ - -typedef struct -{ - uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter must be a number between 0x0000 and 0xFFFF. */ - - uint16_t TIM_ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_Clock_Division_CKD */ - - uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_TimeBaseInitTypeDef; - -/** - * @brief TIM Output Compare Init structure definition - */ - -typedef struct -{ - uint16_t TIM_OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_state */ - - uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_N_state - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_OCInitTypeDef; - -/** - * @brief TIM Input Capture Init structure definition - */ - -typedef struct -{ - - uint16_t TIM_Channel; /*!< Specifies the TIM channel. - This parameter can be a value of @ref TIM_Channel */ - - uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint16_t TIM_ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between 0x0 and 0xF */ -} TIM_ICInitTypeDef; - -/** - * @brief BDTR structure definition - * @note This structure is used only with TIM1 and TIM8. - */ - -typedef struct -{ - - uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. - This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ - - uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. - This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ - - uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. - This parameter can be a value of @ref Lock_level */ - - uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the - switching-on of the outputs. - This parameter can be a number between 0x00 and 0xFF */ - - uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. - This parameter can be a value of @ref Break_Input_enable_disable */ - - uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. - This parameter can be a value of @ref Break_Polarity */ - - uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ -} TIM_BDTRInitTypeDef; - -/** @defgroup TIM_Exported_constants - * @{ - */ - -#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM10)|| \ - ((PERIPH) == TIM11)|| \ - ((PERIPH) == TIM12)|| \ - ((PERIPH) == TIM13)|| \ - ((PERIPH) == TIM14)|| \ - ((PERIPH) == TIM15)|| \ - ((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM17)) - -/* LIST1: TIM 1 and 8 */ -#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM8)) - -/* LIST2: TIM 1, 8, 15 16 and 17 */ -#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM15)|| \ - ((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM17)) - -/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */ -#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8)) - -/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */ -#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM15)|| \ - ((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM17)) - -/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */ -#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM15)) - -/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */ -#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM12)|| \ - ((PERIPH) == TIM15)) - -/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */ -#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM12)|| \ - ((PERIPH) == TIM15)) - -/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */ -#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM10)|| \ - ((PERIPH) == TIM11)|| \ - ((PERIPH) == TIM12)|| \ - ((PERIPH) == TIM13)|| \ - ((PERIPH) == TIM14)|| \ - ((PERIPH) == TIM15)|| \ - ((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM17)) - -/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */ -#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM15)|| \ - ((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM17)) - -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_and_PWM_modes - * @{ - */ - -#define TIM_OCMode_Timing ((uint16_t)0x0000) -#define TIM_OCMode_Active ((uint16_t)0x0010) -#define TIM_OCMode_Inactive ((uint16_t)0x0020) -#define TIM_OCMode_Toggle ((uint16_t)0x0030) -#define TIM_OCMode_PWM1 ((uint16_t)0x0060) -#define TIM_OCMode_PWM2 ((uint16_t)0x0070) -#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2)) -#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2) || \ - ((MODE) == TIM_ForcedAction_Active) || \ - ((MODE) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode - * @{ - */ - -#define TIM_OPMode_Single ((uint16_t)0x0008) -#define TIM_OPMode_Repetitive ((uint16_t)0x0000) -#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ - ((MODE) == TIM_OPMode_Repetitive)) -/** - * @} - */ - -/** @defgroup TIM_Channel - * @{ - */ - -#define TIM_Channel_1 ((uint16_t)0x0000) -#define TIM_Channel_2 ((uint16_t)0x0004) -#define TIM_Channel_3 ((uint16_t)0x0008) -#define TIM_Channel_4 ((uint16_t)0x000C) -#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3) || \ - ((CHANNEL) == TIM_Channel_4)) -#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2)) -#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3)) -/** - * @} - */ - -/** @defgroup TIM_Clock_Division_CKD - * @{ - */ - -#define TIM_CKD_DIV1 ((uint16_t)0x0000) -#define TIM_CKD_DIV2 ((uint16_t)0x0100) -#define TIM_CKD_DIV4 ((uint16_t)0x0200) -#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ - ((DIV) == TIM_CKD_DIV2) || \ - ((DIV) == TIM_CKD_DIV4)) -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode - * @{ - */ - -#define TIM_CounterMode_Up ((uint16_t)0x0000) -#define TIM_CounterMode_Down ((uint16_t)0x0010) -#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) -#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) -#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) -#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ - ((MODE) == TIM_CounterMode_Down) || \ - ((MODE) == TIM_CounterMode_CenterAligned1) || \ - ((MODE) == TIM_CounterMode_CenterAligned2) || \ - ((MODE) == TIM_CounterMode_CenterAligned3)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity - * @{ - */ - -#define TIM_OCPolarity_High ((uint16_t)0x0000) -#define TIM_OCPolarity_Low ((uint16_t)0x0002) -#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ - ((POLARITY) == TIM_OCPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Polarity - * @{ - */ - -#define TIM_OCNPolarity_High ((uint16_t)0x0000) -#define TIM_OCNPolarity_Low ((uint16_t)0x0008) -#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ - ((POLARITY) == TIM_OCNPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_state - * @{ - */ - -#define TIM_OutputState_Disable ((uint16_t)0x0000) -#define TIM_OutputState_Enable ((uint16_t)0x0001) -#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ - ((STATE) == TIM_OutputState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_state - * @{ - */ - -#define TIM_OutputNState_Disable ((uint16_t)0x0000) -#define TIM_OutputNState_Enable ((uint16_t)0x0004) -#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ - ((STATE) == TIM_OutputNState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_state - * @{ - */ - -#define TIM_CCx_Enable ((uint16_t)0x0001) -#define TIM_CCx_Disable ((uint16_t)0x0000) -#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ - ((CCX) == TIM_CCx_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_N_state - * @{ - */ - -#define TIM_CCxN_Enable ((uint16_t)0x0004) -#define TIM_CCxN_Disable ((uint16_t)0x0000) -#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ - ((CCXN) == TIM_CCxN_Disable)) -/** - * @} - */ - -/** @defgroup Break_Input_enable_disable - * @{ - */ - -#define TIM_Break_Enable ((uint16_t)0x1000) -#define TIM_Break_Disable ((uint16_t)0x0000) -#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ - ((STATE) == TIM_Break_Disable)) -/** - * @} - */ - -/** @defgroup Break_Polarity - * @{ - */ - -#define TIM_BreakPolarity_Low ((uint16_t)0x0000) -#define TIM_BreakPolarity_High ((uint16_t)0x2000) -#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ - ((POLARITY) == TIM_BreakPolarity_High)) -/** - * @} - */ - -/** @defgroup TIM_AOE_Bit_Set_Reset - * @{ - */ - -#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) -#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) -#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ - ((STATE) == TIM_AutomaticOutput_Disable)) -/** - * @} - */ - -/** @defgroup Lock_level - * @{ - */ - -#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) -#define TIM_LOCKLevel_1 ((uint16_t)0x0100) -#define TIM_LOCKLevel_2 ((uint16_t)0x0200) -#define TIM_LOCKLevel_3 ((uint16_t)0x0300) -#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ - ((LEVEL) == TIM_LOCKLevel_1) || \ - ((LEVEL) == TIM_LOCKLevel_2) || \ - ((LEVEL) == TIM_LOCKLevel_3)) -/** - * @} - */ - -/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state - * @{ - */ - -#define TIM_OSSIState_Enable ((uint16_t)0x0400) -#define TIM_OSSIState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ - ((STATE) == TIM_OSSIState_Disable)) -/** - * @} - */ - -/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state - * @{ - */ - -#define TIM_OSSRState_Enable ((uint16_t)0x0800) -#define TIM_OSSRState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ - ((STATE) == TIM_OSSRState_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Idle_State - * @{ - */ - -#define TIM_OCIdleState_Set ((uint16_t)0x0100) -#define TIM_OCIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ - ((STATE) == TIM_OCIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Idle_State - * @{ - */ - -#define TIM_OCNIdleState_Set ((uint16_t)0x0200) -#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ - ((STATE) == TIM_OCNIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Polarity - * @{ - */ - -#define TIM_ICPolarity_Rising ((uint16_t)0x0000) -#define TIM_ICPolarity_Falling ((uint16_t)0x0002) -#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) -#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ - ((POLARITY) == TIM_ICPolarity_Falling)) -#define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ - ((POLARITY) == TIM_ICPolarity_Falling)|| \ - ((POLARITY) == TIM_ICPolarity_BothEdge)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection - * @{ - */ - -#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively. */ -#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ -#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ - ((SELECTION) == TIM_ICSelection_IndirectTI) || \ - ((SELECTION) == TIM_ICSelection_TRC)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler - * @{ - */ - -#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ -#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ -#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ -#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ -#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ - ((PRESCALER) == TIM_ICPSC_DIV2) || \ - ((PRESCALER) == TIM_ICPSC_DIV4) || \ - ((PRESCALER) == TIM_ICPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_interrupt_sources - * @{ - */ - -#define TIM_IT_Update ((uint16_t)0x0001) -#define TIM_IT_CC1 ((uint16_t)0x0002) -#define TIM_IT_CC2 ((uint16_t)0x0004) -#define TIM_IT_CC3 ((uint16_t)0x0008) -#define TIM_IT_CC4 ((uint16_t)0x0010) -#define TIM_IT_COM ((uint16_t)0x0020) -#define TIM_IT_Trigger ((uint16_t)0x0040) -#define TIM_IT_Break ((uint16_t)0x0080) -#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) - -#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ - ((IT) == TIM_IT_CC1) || \ - ((IT) == TIM_IT_CC2) || \ - ((IT) == TIM_IT_CC3) || \ - ((IT) == TIM_IT_CC4) || \ - ((IT) == TIM_IT_COM) || \ - ((IT) == TIM_IT_Trigger) || \ - ((IT) == TIM_IT_Break)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address - * @{ - */ - -#define TIM_DMABase_CR1 ((uint16_t)0x0000) -#define TIM_DMABase_CR2 ((uint16_t)0x0001) -#define TIM_DMABase_SMCR ((uint16_t)0x0002) -#define TIM_DMABase_DIER ((uint16_t)0x0003) -#define TIM_DMABase_SR ((uint16_t)0x0004) -#define TIM_DMABase_EGR ((uint16_t)0x0005) -#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) -#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) -#define TIM_DMABase_CCER ((uint16_t)0x0008) -#define TIM_DMABase_CNT ((uint16_t)0x0009) -#define TIM_DMABase_PSC ((uint16_t)0x000A) -#define TIM_DMABase_ARR ((uint16_t)0x000B) -#define TIM_DMABase_RCR ((uint16_t)0x000C) -#define TIM_DMABase_CCR1 ((uint16_t)0x000D) -#define TIM_DMABase_CCR2 ((uint16_t)0x000E) -#define TIM_DMABase_CCR3 ((uint16_t)0x000F) -#define TIM_DMABase_CCR4 ((uint16_t)0x0010) -#define TIM_DMABase_BDTR ((uint16_t)0x0011) -#define TIM_DMABase_DCR ((uint16_t)0x0012) -#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ - ((BASE) == TIM_DMABase_CR2) || \ - ((BASE) == TIM_DMABase_SMCR) || \ - ((BASE) == TIM_DMABase_DIER) || \ - ((BASE) == TIM_DMABase_SR) || \ - ((BASE) == TIM_DMABase_EGR) || \ - ((BASE) == TIM_DMABase_CCMR1) || \ - ((BASE) == TIM_DMABase_CCMR2) || \ - ((BASE) == TIM_DMABase_CCER) || \ - ((BASE) == TIM_DMABase_CNT) || \ - ((BASE) == TIM_DMABase_PSC) || \ - ((BASE) == TIM_DMABase_ARR) || \ - ((BASE) == TIM_DMABase_RCR) || \ - ((BASE) == TIM_DMABase_CCR1) || \ - ((BASE) == TIM_DMABase_CCR2) || \ - ((BASE) == TIM_DMABase_CCR3) || \ - ((BASE) == TIM_DMABase_CCR4) || \ - ((BASE) == TIM_DMABase_BDTR) || \ - ((BASE) == TIM_DMABase_DCR)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Burst_Length - * @{ - */ - -#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) -#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) -#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) -#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) -#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) -#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) -#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) -#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) -#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) -#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) -#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) -#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) -#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) -#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) -#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) -#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) -#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) -#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) -#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ - ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_18Transfers)) -/** - * @} - */ - -/** @defgroup TIM_DMA_sources - * @{ - */ - -#define TIM_DMA_Update ((uint16_t)0x0100) -#define TIM_DMA_CC1 ((uint16_t)0x0200) -#define TIM_DMA_CC2 ((uint16_t)0x0400) -#define TIM_DMA_CC3 ((uint16_t)0x0800) -#define TIM_DMA_CC4 ((uint16_t)0x1000) -#define TIM_DMA_COM ((uint16_t)0x2000) -#define TIM_DMA_Trigger ((uint16_t)0x4000) -#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Prescaler - * @{ - */ - -#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) -#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) -#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) -#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) -#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_Internal_Trigger_Selection - * @{ - */ - -#define TIM_TS_ITR0 ((uint16_t)0x0000) -#define TIM_TS_ITR1 ((uint16_t)0x0010) -#define TIM_TS_ITR2 ((uint16_t)0x0020) -#define TIM_TS_ITR3 ((uint16_t)0x0030) -#define TIM_TS_TI1F_ED ((uint16_t)0x0040) -#define TIM_TS_TI1FP1 ((uint16_t)0x0050) -#define TIM_TS_TI2FP2 ((uint16_t)0x0060) -#define TIM_TS_ETRF ((uint16_t)0x0070) -#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_TI1F_ED) || \ - ((SELECTION) == TIM_TS_TI1FP1) || \ - ((SELECTION) == TIM_TS_TI2FP2) || \ - ((SELECTION) == TIM_TS_ETRF)) -#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3)) -/** - * @} - */ - -/** @defgroup TIM_TIx_External_Clock_Source - * @{ - */ - -#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) -#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) -#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) -#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \ - ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \ - ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED)) -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Polarity - * @{ - */ -#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) -#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) -#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ - ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) -/** - * @} - */ - -/** @defgroup TIM_Prescaler_Reload_Mode - * @{ - */ - -#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) -#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) -#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ - ((RELOAD) == TIM_PSCReloadMode_Immediate)) -/** - * @} - */ - -/** @defgroup TIM_Forced_Action - * @{ - */ - -#define TIM_ForcedAction_Active ((uint16_t)0x0050) -#define TIM_ForcedAction_InActive ((uint16_t)0x0040) -#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ - ((ACTION) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode - * @{ - */ - -#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) -#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) -#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) -#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ - ((MODE) == TIM_EncoderMode_TI2) || \ - ((MODE) == TIM_EncoderMode_TI12)) -/** - * @} - */ - - -/** @defgroup TIM_Event_Source - * @{ - */ - -#define TIM_EventSource_Update ((uint16_t)0x0001) -#define TIM_EventSource_CC1 ((uint16_t)0x0002) -#define TIM_EventSource_CC2 ((uint16_t)0x0004) -#define TIM_EventSource_CC3 ((uint16_t)0x0008) -#define TIM_EventSource_CC4 ((uint16_t)0x0010) -#define TIM_EventSource_COM ((uint16_t)0x0020) -#define TIM_EventSource_Trigger ((uint16_t)0x0040) -#define TIM_EventSource_Break ((uint16_t)0x0080) -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_Update_Source - * @{ - */ - -#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow - or the setting of UG bit, or an update generation - through the slave mode controller. */ -#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ -#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ - ((SOURCE) == TIM_UpdateSource_Regular)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Preload_State - * @{ - */ - -#define TIM_OCPreload_Enable ((uint16_t)0x0008) -#define TIM_OCPreload_Disable ((uint16_t)0x0000) -#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ - ((STATE) == TIM_OCPreload_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Fast_State - * @{ - */ - -#define TIM_OCFast_Enable ((uint16_t)0x0004) -#define TIM_OCFast_Disable ((uint16_t)0x0000) -#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ - ((STATE) == TIM_OCFast_Disable)) - -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Clear_State - * @{ - */ - -#define TIM_OCClear_Enable ((uint16_t)0x0080) -#define TIM_OCClear_Disable ((uint16_t)0x0000) -#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ - ((STATE) == TIM_OCClear_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Output_Source - * @{ - */ - -#define TIM_TRGOSource_Reset ((uint16_t)0x0000) -#define TIM_TRGOSource_Enable ((uint16_t)0x0010) -#define TIM_TRGOSource_Update ((uint16_t)0x0020) -#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) -#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) -#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) -#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) -#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) -#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ - ((SOURCE) == TIM_TRGOSource_Enable) || \ - ((SOURCE) == TIM_TRGOSource_Update) || \ - ((SOURCE) == TIM_TRGOSource_OC1) || \ - ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC4Ref)) -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode - * @{ - */ - -#define TIM_SlaveMode_Reset ((uint16_t)0x0004) -#define TIM_SlaveMode_Gated ((uint16_t)0x0005) -#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) -#define TIM_SlaveMode_External1 ((uint16_t)0x0007) -#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ - ((MODE) == TIM_SlaveMode_Gated) || \ - ((MODE) == TIM_SlaveMode_Trigger) || \ - ((MODE) == TIM_SlaveMode_External1)) -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode - * @{ - */ - -#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) -#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) -#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ - ((STATE) == TIM_MasterSlaveMode_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Flags - * @{ - */ - -#define TIM_FLAG_Update ((uint16_t)0x0001) -#define TIM_FLAG_CC1 ((uint16_t)0x0002) -#define TIM_FLAG_CC2 ((uint16_t)0x0004) -#define TIM_FLAG_CC3 ((uint16_t)0x0008) -#define TIM_FLAG_CC4 ((uint16_t)0x0010) -#define TIM_FLAG_COM ((uint16_t)0x0020) -#define TIM_FLAG_Trigger ((uint16_t)0x0040) -#define TIM_FLAG_Break ((uint16_t)0x0080) -#define TIM_FLAG_CC1OF ((uint16_t)0x0200) -#define TIM_FLAG_CC2OF ((uint16_t)0x0400) -#define TIM_FLAG_CC3OF ((uint16_t)0x0800) -#define TIM_FLAG_CC4OF ((uint16_t)0x1000) -#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ - ((FLAG) == TIM_FLAG_CC1) || \ - ((FLAG) == TIM_FLAG_CC2) || \ - ((FLAG) == TIM_FLAG_CC3) || \ - ((FLAG) == TIM_FLAG_CC4) || \ - ((FLAG) == TIM_FLAG_COM) || \ - ((FLAG) == TIM_FLAG_Trigger) || \ - ((FLAG) == TIM_FLAG_Break) || \ - ((FLAG) == TIM_FLAG_CC1OF) || \ - ((FLAG) == TIM_FLAG_CC2OF) || \ - ((FLAG) == TIM_FLAG_CC3OF) || \ - ((FLAG) == TIM_FLAG_CC4OF)) - - -#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Filer_Value - * @{ - */ - -#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Filter - * @{ - */ - -#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_Legacy - * @{ - */ - -#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer -#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers -#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers -#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers -#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers -#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers -#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers -#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers -#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers -#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers -#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers -#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers -#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers -#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers -#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers -#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers -#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers -#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup TIM_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions - * @{ - */ - -void TIM_DeInit(TIM_TypeDef* TIMx); -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); -void TIM_InternalClockConfig(TIM_TypeDef* TIMx); -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter); -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); -void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter); -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1); -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2); -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3); -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4); -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); -uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx); -uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx); -uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx); -uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx); -uint16_t TIM_GetCounter(TIM_TypeDef* TIMx); -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_TIM_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h deleted file mode 100644 index 61ae249a4..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h +++ /dev/null @@ -1,412 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_usart.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the USART - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_USART_H -#define __STM32F10x_USART_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup USART - * @{ - */ - -/** @defgroup USART_Exported_Types - * @{ - */ - -/** - * @brief USART Init Structure definition - */ - -typedef struct -{ - uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) - - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ - - uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_Word_Length */ - - uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits */ - - uint16_t USART_Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref USART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode */ - - uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref USART_Hardware_Flow_Control */ -} USART_InitTypeDef; - -/** - * @brief USART Clock Init Structure definition - */ - -typedef struct -{ - - uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_Clock */ - - uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock. - This parameter can be a value of @ref USART_Clock_Polarity */ - - uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_Clock_Phase */ - - uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_Last_Bit */ -} USART_ClockInitTypeDef; - -/** - * @} - */ - -/** @defgroup USART_Exported_Constants - * @{ - */ - -#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == UART4) || \ - ((PERIPH) == UART5)) - -#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3)) - -#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == UART4)) -/** @defgroup USART_Word_Length - * @{ - */ - -#define USART_WordLength_8b ((uint16_t)0x0000) -#define USART_WordLength_9b ((uint16_t)0x1000) - -#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ - ((LENGTH) == USART_WordLength_9b)) -/** - * @} - */ - -/** @defgroup USART_Stop_Bits - * @{ - */ - -#define USART_StopBits_1 ((uint16_t)0x0000) -#define USART_StopBits_0_5 ((uint16_t)0x1000) -#define USART_StopBits_2 ((uint16_t)0x2000) -#define USART_StopBits_1_5 ((uint16_t)0x3000) -#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ - ((STOPBITS) == USART_StopBits_0_5) || \ - ((STOPBITS) == USART_StopBits_2) || \ - ((STOPBITS) == USART_StopBits_1_5)) -/** - * @} - */ - -/** @defgroup USART_Parity - * @{ - */ - -#define USART_Parity_No ((uint16_t)0x0000) -#define USART_Parity_Even ((uint16_t)0x0400) -#define USART_Parity_Odd ((uint16_t)0x0600) -#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ - ((PARITY) == USART_Parity_Even) || \ - ((PARITY) == USART_Parity_Odd)) -/** - * @} - */ - -/** @defgroup USART_Mode - * @{ - */ - -#define USART_Mode_Rx ((uint16_t)0x0004) -#define USART_Mode_Tx ((uint16_t)0x0008) -#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) -/** - * @} - */ - -/** @defgroup USART_Hardware_Flow_Control - * @{ - */ -#define USART_HardwareFlowControl_None ((uint16_t)0x0000) -#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) -#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) -#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) -#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ - (((CONTROL) == USART_HardwareFlowControl_None) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS) || \ - ((CONTROL) == USART_HardwareFlowControl_CTS) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) -/** - * @} - */ - -/** @defgroup USART_Clock - * @{ - */ -#define USART_Clock_Disable ((uint16_t)0x0000) -#define USART_Clock_Enable ((uint16_t)0x0800) -#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ - ((CLOCK) == USART_Clock_Enable)) -/** - * @} - */ - -/** @defgroup USART_Clock_Polarity - * @{ - */ - -#define USART_CPOL_Low ((uint16_t)0x0000) -#define USART_CPOL_High ((uint16_t)0x0400) -#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) - -/** - * @} - */ - -/** @defgroup USART_Clock_Phase - * @{ - */ - -#define USART_CPHA_1Edge ((uint16_t)0x0000) -#define USART_CPHA_2Edge ((uint16_t)0x0200) -#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) - -/** - * @} - */ - -/** @defgroup USART_Last_Bit - * @{ - */ - -#define USART_LastBit_Disable ((uint16_t)0x0000) -#define USART_LastBit_Enable ((uint16_t)0x0100) -#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ - ((LASTBIT) == USART_LastBit_Enable)) -/** - * @} - */ - -/** @defgroup USART_Interrupt_definition - * @{ - */ - -#define USART_IT_PE ((uint16_t)0x0028) -#define USART_IT_TXE ((uint16_t)0x0727) -#define USART_IT_TC ((uint16_t)0x0626) -#define USART_IT_RXNE ((uint16_t)0x0525) -#define USART_IT_IDLE ((uint16_t)0x0424) -#define USART_IT_LBD ((uint16_t)0x0846) -#define USART_IT_CTS ((uint16_t)0x096A) -#define USART_IT_ERR ((uint16_t)0x0060) -#define USART_IT_ORE ((uint16_t)0x0360) -#define USART_IT_NE ((uint16_t)0x0260) -#define USART_IT_FE ((uint16_t)0x0160) -#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) -#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ - ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) -#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) -/** - * @} - */ - -/** @defgroup USART_DMA_Requests - * @{ - */ - -#define USART_DMAReq_Tx ((uint16_t)0x0080) -#define USART_DMAReq_Rx ((uint16_t)0x0040) -#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) - -/** - * @} - */ - -/** @defgroup USART_WakeUp_methods - * @{ - */ - -#define USART_WakeUp_IdleLine ((uint16_t)0x0000) -#define USART_WakeUp_AddressMark ((uint16_t)0x0800) -#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ - ((WAKEUP) == USART_WakeUp_AddressMark)) -/** - * @} - */ - -/** @defgroup USART_LIN_Break_Detection_Length - * @{ - */ - -#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) -#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) -#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ - (((LENGTH) == USART_LINBreakDetectLength_10b) || \ - ((LENGTH) == USART_LINBreakDetectLength_11b)) -/** - * @} - */ - -/** @defgroup USART_IrDA_Low_Power - * @{ - */ - -#define USART_IrDAMode_LowPower ((uint16_t)0x0004) -#define USART_IrDAMode_Normal ((uint16_t)0x0000) -#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ - ((MODE) == USART_IrDAMode_Normal)) -/** - * @} - */ - -/** @defgroup USART_Flags - * @{ - */ - -#define USART_FLAG_CTS ((uint16_t)0x0200) -#define USART_FLAG_LBD ((uint16_t)0x0100) -#define USART_FLAG_TXE ((uint16_t)0x0080) -#define USART_FLAG_TC ((uint16_t)0x0040) -#define USART_FLAG_RXNE ((uint16_t)0x0020) -#define USART_FLAG_IDLE ((uint16_t)0x0010) -#define USART_FLAG_ORE ((uint16_t)0x0008) -#define USART_FLAG_NE ((uint16_t)0x0004) -#define USART_FLAG_FE ((uint16_t)0x0002) -#define USART_FLAG_PE ((uint16_t)0x0001) -#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ - ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ - ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ - ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ - ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) - -#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) -#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\ - ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \ - || ((USART_FLAG) != USART_FLAG_CTS)) -#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21)) -#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) -#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup USART_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Exported_Functions - * @{ - */ - -void USART_DeInit(USART_TypeDef* USARTx); -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); -void USART_StructInit(USART_InitTypeDef* USART_InitStruct); -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); -uint16_t USART_ReceiveData(USART_TypeDef* USARTx); -void USART_SendBreak(USART_TypeDef* USARTx); -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_USART_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h deleted file mode 100644 index cd573da44..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h +++ /dev/null @@ -1,115 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_wwdg.h - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file contains all the functions prototypes for the WWDG firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_WWDG_H -#define __STM32F10x_WWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup WWDG - * @{ - */ - -/** @defgroup WWDG_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup WWDG_Exported_Constants - * @{ - */ - -/** @defgroup WWDG_Prescaler - * @{ - */ - -#define WWDG_Prescaler_1 ((uint32_t)0x00000000) -#define WWDG_Prescaler_2 ((uint32_t)0x00000080) -#define WWDG_Prescaler_4 ((uint32_t)0x00000100) -#define WWDG_Prescaler_8 ((uint32_t)0x00000180) -#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ - ((PRESCALER) == WWDG_Prescaler_2) || \ - ((PRESCALER) == WWDG_Prescaler_4) || \ - ((PRESCALER) == WWDG_Prescaler_8)) -#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) -#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup WWDG_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup WWDG_Exported_Functions - * @{ - */ - -void WWDG_DeInit(void); -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); -void WWDG_SetWindowValue(uint8_t WindowValue); -void WWDG_EnableIT(void); -void WWDG_SetCounter(uint8_t Counter); -void WWDG_Enable(uint8_t Counter); -FlagStatus WWDG_GetFlagStatus(void); -void WWDG_ClearFlag(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_WWDG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c deleted file mode 100644 index ec9165f71..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c +++ /dev/null @@ -1,225 +0,0 @@ -/** - ****************************************************************************** - * @file misc.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the miscellaneous firmware functions (add-on - * to CMSIS functions). - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "misc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup MISC - * @brief MISC driver modules - * @{ - */ - -/** @defgroup MISC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup MISC_Private_Defines - * @{ - */ - -#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) -/** - * @} - */ - -/** @defgroup MISC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup MISC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup MISC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup MISC_Private_Functions - * @{ - */ - -/** - * @brief Configures the priority grouping: pre-emption priority and subpriority. - * @param NVIC_PriorityGroup: specifies the priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority - * 4 bits for subpriority - * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority - * 3 bits for subpriority - * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority - * 2 bits for subpriority - * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority - * 1 bits for subpriority - * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority - * 0 bits for subpriority - * @retval None - */ -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); - - /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ - SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; -} - -/** - * @brief Initializes the NVIC peripheral according to the specified - * parameters in the NVIC_InitStruct. - * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains - * the configuration information for the specified NVIC peripheral. - * @retval None - */ -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) -{ - uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); - assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); - - if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) - { - /* Compute the Corresponding IRQ Priority --------------------------------*/ - tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; - tmppre = (0x4 - tmppriority); - tmpsub = tmpsub >> tmppriority; - - tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; - tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; - tmppriority = tmppriority << 0x04; - - NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; - - /* Enable the Selected IRQ Channels --------------------------------------*/ - NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } - else - { - /* Disable the Selected IRQ Channels -------------------------------------*/ - NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } -} - -/** - * @brief Sets the vector table location and Offset. - * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. - * This parameter can be one of the following values: - * @arg NVIC_VectTab_RAM - * @arg NVIC_VectTab_FLASH - * @param Offset: Vector Table base offset field. This value must be a multiple - * of 0x200. - * @retval None - */ -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) -{ - /* Check the parameters */ - assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); - assert_param(IS_NVIC_OFFSET(Offset)); - - SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); -} - -/** - * @brief Selects the condition for the system to enter low power mode. - * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. - * This parameter can be one of the following values: - * @arg NVIC_LP_SEVONPEND - * @arg NVIC_LP_SLEEPDEEP - * @arg NVIC_LP_SLEEPONEXIT - * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_NVIC_LP(LowPowerMode)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - SCB->SCR |= LowPowerMode; - } - else - { - SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); - } -} - -/** - * @brief Configures the SysTick clock source. - * @param SysTick_CLKSource: specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); - if (SysTick_CLKSource == SysTick_CLKSource_HCLK) - { - SysTick->CTRL |= SysTick_CLKSource_HCLK; - } - else - { - SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c deleted file mode 100644 index 916a096d4..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c +++ /dev/null @@ -1,1307 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_adc.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the ADC firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_adc.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup ADC - * @brief ADC driver modules - * @{ - */ - -/** @defgroup ADC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_Defines - * @{ - */ - -/* ADC DISCNUM mask */ -#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) - -/* ADC DISCEN mask */ -#define CR1_DISCEN_Set ((uint32_t)0x00000800) -#define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) - -/* ADC JAUTO mask */ -#define CR1_JAUTO_Set ((uint32_t)0x00000400) -#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) - -/* ADC JDISCEN mask */ -#define CR1_JDISCEN_Set ((uint32_t)0x00001000) -#define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) - -/* ADC AWDCH mask */ -#define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) - -/* ADC Analog watchdog enable mode mask */ -#define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) - -/* CR1 register Mask */ -#define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) - -/* ADC ADON mask */ -#define CR2_ADON_Set ((uint32_t)0x00000001) -#define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE) - -/* ADC DMA mask */ -#define CR2_DMA_Set ((uint32_t)0x00000100) -#define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF) - -/* ADC RSTCAL mask */ -#define CR2_RSTCAL_Set ((uint32_t)0x00000008) - -/* ADC CAL mask */ -#define CR2_CAL_Set ((uint32_t)0x00000004) - -/* ADC SWSTART mask */ -#define CR2_SWSTART_Set ((uint32_t)0x00400000) - -/* ADC EXTTRIG mask */ -#define CR2_EXTTRIG_Set ((uint32_t)0x00100000) -#define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) - -/* ADC Software start mask */ -#define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) -#define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) - -/* ADC JEXTSEL mask */ -#define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) - -/* ADC JEXTTRIG mask */ -#define CR2_JEXTTRIG_Set ((uint32_t)0x00008000) -#define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) - -/* ADC JSWSTART mask */ -#define CR2_JSWSTART_Set ((uint32_t)0x00200000) - -/* ADC injected software start mask */ -#define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) -#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) - -/* ADC TSPD mask */ -#define CR2_TSVREFE_Set ((uint32_t)0x00800000) -#define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) - -/* CR2 register Mask */ -#define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) - -/* ADC SQx mask */ -#define SQR3_SQ_Set ((uint32_t)0x0000001F) -#define SQR2_SQ_Set ((uint32_t)0x0000001F) -#define SQR1_SQ_Set ((uint32_t)0x0000001F) - -/* SQR1 register Mask */ -#define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) - -/* ADC JSQx mask */ -#define JSQR_JSQ_Set ((uint32_t)0x0000001F) - -/* ADC JL mask */ -#define JSQR_JL_Set ((uint32_t)0x00300000) -#define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF) - -/* ADC SMPx mask */ -#define SMPR1_SMP_Set ((uint32_t)0x00000007) -#define SMPR2_SMP_Set ((uint32_t)0x00000007) - -/* ADC JDRx registers offset */ -#define JDR_Offset ((uint8_t)0x28) - -/* ADC1 DR register base address */ -#define DR_ADDRESS ((uint32_t)0x4001244C) - -/** - * @} - */ - -/** @defgroup ADC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the ADCx peripheral registers to their default reset values. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_DeInit(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - if (ADCx == ADC1) - { - /* Enable ADC1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); - /* Release ADC1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); - } - else if (ADCx == ADC2) - { - /* Enable ADC2 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); - /* Release ADC2 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); - } - else - { - if (ADCx == ADC3) - { - /* Enable ADC3 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE); - /* Release ADC3 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE); - } - } -} - -/** - * @brief Initializes the ADCx peripheral according to the specified parameters - * in the ADC_InitStruct. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains - * the configuration information for the specified ADC peripheral. - * @retval None - */ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) -{ - uint32_t tmpreg1 = 0; - uint8_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); - assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); - assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel)); - - /*---------------------------- ADCx CR1 Configuration -----------------*/ - /* Get the ADCx CR1 value */ - tmpreg1 = ADCx->CR1; - /* Clear DUALMOD and SCAN bits */ - tmpreg1 &= CR1_CLEAR_Mask; - /* Configure ADCx: Dual mode and scan conversion mode */ - /* Set DUALMOD bits according to ADC_Mode value */ - /* Set SCAN bit according to ADC_ScanConvMode value */ - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); - /* Write to ADCx CR1 */ - ADCx->CR1 = tmpreg1; - - /*---------------------------- ADCx CR2 Configuration -----------------*/ - /* Get the ADCx CR2 value */ - tmpreg1 = ADCx->CR2; - /* Clear CONT, ALIGN and EXTSEL bits */ - tmpreg1 &= CR2_CLEAR_Mask; - /* Configure ADCx: external trigger event and continuous conversion mode */ - /* Set ALIGN bit according to ADC_DataAlign value */ - /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ - /* Set CONT bit according to ADC_ContinuousConvMode value */ - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | - ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); - /* Write to ADCx CR2 */ - ADCx->CR2 = tmpreg1; - - /*---------------------------- ADCx SQR1 Configuration -----------------*/ - /* Get the ADCx SQR1 value */ - tmpreg1 = ADCx->SQR1; - /* Clear L bits */ - tmpreg1 &= SQR1_CLEAR_Mask; - /* Configure ADCx: regular channel sequence length */ - /* Set L bits according to ADC_NbrOfChannel value */ - tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); - tmpreg1 |= (uint32_t)tmpreg2 << 20; - /* Write to ADCx SQR1 */ - ADCx->SQR1 = tmpreg1; -} - -/** - * @brief Fills each ADC_InitStruct member with its default value. - * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized. - * @retval None - */ -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) -{ - /* Reset ADC init structure parameters values */ - /* Initialize the ADC_Mode member */ - ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; - /* initialize the ADC_ScanConvMode member */ - ADC_InitStruct->ADC_ScanConvMode = DISABLE; - /* Initialize the ADC_ContinuousConvMode member */ - ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; - /* Initialize the ADC_ExternalTrigConv member */ - ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; - /* Initialize the ADC_DataAlign member */ - ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; - /* Initialize the ADC_NbrOfChannel member */ - ADC_InitStruct->ADC_NbrOfChannel = 1; -} - -/** - * @brief Enables or disables the specified ADC peripheral. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the ADCx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the ADON bit to wake up the ADC from power down mode */ - ADCx->CR2 |= CR2_ADON_Set; - } - else - { - /* Disable the selected ADC peripheral */ - ADCx->CR2 &= CR2_ADON_Reset; - } -} - -/** - * @brief Enables or disables the specified ADC DMA request. - * @param ADCx: where x can be 1 or 3 to select the ADC peripheral. - * Note: ADC2 hasn't a DMA capability. - * @param NewState: new state of the selected ADC DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_DMA_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request */ - ADCx->CR2 |= CR2_DMA_Set; - } - else - { - /* Disable the selected ADC DMA request */ - ADCx->CR2 &= CR2_DMA_Reset; - } -} - -/** - * @brief Enables or disables the specified ADC interrupts. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @param NewState: new state of the specified ADC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) -{ - uint8_t itmask = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_ADC_IT(ADC_IT)); - /* Get the ADC IT index */ - itmask = (uint8_t)ADC_IT; - if (NewState != DISABLE) - { - /* Enable the selected ADC interrupts */ - ADCx->CR1 |= itmask; - } - else - { - /* Disable the selected ADC interrupts */ - ADCx->CR1 &= (~(uint32_t)itmask); - } -} - -/** - * @brief Resets the selected ADC calibration registers. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_ResetCalibration(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Resets the selected ADC calibration registers */ - ADCx->CR2 |= CR2_RSTCAL_Set; -} - -/** - * @brief Gets the selected ADC reset calibration registers status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC reset calibration registers (SET or RESET). - */ -FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of RSTCAL bit */ - if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET) - { - /* RSTCAL bit is set */ - bitstatus = SET; - } - else - { - /* RSTCAL bit is reset */ - bitstatus = RESET; - } - /* Return the RSTCAL bit status */ - return bitstatus; -} - -/** - * @brief Starts the selected ADC calibration process. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_StartCalibration(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Enable the selected ADC calibration process */ - ADCx->CR2 |= CR2_CAL_Set; -} - -/** - * @brief Gets the selected ADC calibration status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC calibration (SET or RESET). - */ -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of CAL bit */ - if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET) - { - /* CAL bit is set: calibration on going */ - bitstatus = SET; - } - else - { - /* CAL bit is reset: end of calibration */ - bitstatus = RESET; - } - /* Return the CAL bit status */ - return bitstatus; -} - -/** - * @brief Enables or disables the selected ADC software start conversion . - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC software start conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC conversion on external event and start the selected - ADC conversion */ - ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set; - } - else - { - /* Disable the selected ADC conversion on external event and stop the selected - ADC conversion */ - ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset; - } -} - -/** - * @brief Gets the selected ADC Software start conversion Status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC software start conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of SWSTART bit */ - if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET) - { - /* SWSTART bit is set */ - bitstatus = SET; - } - else - { - /* SWSTART bit is reset */ - bitstatus = RESET; - } - /* Return the SWSTART bit status */ - return bitstatus; -} - -/** - * @brief Configures the discontinuous mode for the selected ADC regular - * group channel. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param Number: specifies the discontinuous mode regular channel - * count value. This number must be between 1 and 8. - * @retval None - */ -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); - /* Get the old register value */ - tmpreg1 = ADCx->CR1; - /* Clear the old discontinuous mode channel count */ - tmpreg1 &= CR1_DISCNUM_Reset; - /* Set the discontinuous mode channel count */ - tmpreg2 = Number - 1; - tmpreg1 |= tmpreg2 << 13; - /* Store the new register value */ - ADCx->CR1 = tmpreg1; -} - -/** - * @brief Enables or disables the discontinuous mode on regular group - * channel for the specified ADC - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode - * on regular group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC regular discontinuous mode */ - ADCx->CR1 |= CR1_DISCEN_Set; - } - else - { - /* Disable the selected ADC regular discontinuous mode */ - ADCx->CR1 &= CR1_DISCEN_Reset; - } -} - -/** - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16. - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles - * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles - * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles - * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles - * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles - * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles - * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles - * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles - * @retval None - */ -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_REGULAR_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ - if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10)); - /* Clear the old channel sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - /* Set the new channel sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); - /* Clear the old channel sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - /* Set the new channel sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - /* For Rank 1 to 6 */ - if (Rank < 7) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR3; - /* Calculate the mask to clear */ - tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR3 = tmpreg1; - } - /* For Rank 7 to 12 */ - else if (Rank < 13) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR2; - /* Calculate the mask to clear */ - tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR2 = tmpreg1; - } - /* For Rank 13 to 16 */ - else - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR1; - /* Calculate the mask to clear */ - tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR1 = tmpreg1; - } -} - -/** - * @brief Enables or disables the ADCx conversion through external trigger. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC external trigger start of conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC conversion on external event */ - ADCx->CR2 |= CR2_EXTTRIG_Set; - } - else - { - /* Disable the selected ADC conversion on external event */ - ADCx->CR2 &= CR2_EXTTRIG_Reset; - } -} - -/** - * @brief Returns the last ADCx conversion result data for regular channel. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The Data conversion value. - */ -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Return the selected ADC conversion value */ - return (uint16_t) ADCx->DR; -} - -/** - * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode. - * @retval The Data conversion value. - */ -uint32_t ADC_GetDualModeConversionValue(void) -{ - /* Return the dual mode conversion value */ - return (*(__IO uint32_t *) DR_ADDRESS); -} - -/** - * @brief Enables or disables the selected ADC automatic injected group - * conversion after regular one. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC auto injected conversion - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC automatic injected group conversion */ - ADCx->CR1 |= CR1_JAUTO_Set; - } - else - { - /* Disable the selected ADC automatic injected group conversion */ - ADCx->CR1 &= CR1_JAUTO_Reset; - } -} - -/** - * @brief Enables or disables the discontinuous mode for injected group - * channel for the specified ADC - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode - * on injected group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC injected discontinuous mode */ - ADCx->CR1 |= CR1_JDISCEN_Set; - } - else - { - /* Disable the selected ADC injected discontinuous mode */ - ADCx->CR1 &= CR1_JDISCEN_Reset; - } -} - -/** - * @brief Configures the ADCx external trigger for injected channels conversion. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. - * This parameter can be one of the following values: - * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3) - * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3) - * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8 - * capture compare4 event selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not - * by external trigger (for ADC1, ADC2 and ADC3) - * @retval None - */ -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); - /* Get the old register value */ - tmpreg = ADCx->CR2; - /* Clear the old external event selection for injected group */ - tmpreg &= CR2_JEXTSEL_Reset; - /* Set the external event selection for injected group */ - tmpreg |= ADC_ExternalTrigInjecConv; - /* Store the new register value */ - ADCx->CR2 = tmpreg; -} - -/** - * @brief Enables or disables the ADCx injected channels conversion through - * external trigger - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC external trigger start of - * injected conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC external event selection for injected group */ - ADCx->CR2 |= CR2_JEXTTRIG_Set; - } - else - { - /* Disable the selected ADC external event selection for injected group */ - ADCx->CR2 &= CR2_JEXTTRIG_Reset; - } -} - -/** - * @brief Enables or disables the selected ADC start of the injected - * channels conversion. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC software start injected conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC conversion for injected group on external event and start the selected - ADC injected conversion */ - ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set; - } - else - { - /* Disable the selected ADC conversion on external event for injected group and stop the selected - ADC injected conversion */ - ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset; - } -} - -/** - * @brief Gets the selected ADC Software start injected conversion Status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC software start injected conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of JSWSTART bit */ - if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET) - { - /* JSWSTART bit is set */ - bitstatus = SET; - } - else - { - /* JSWSTART bit is reset */ - bitstatus = RESET; - } - /* Return the JSWSTART bit status */ - return bitstatus; -} - -/** - * @brief Configures for the selected ADC injected channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @param Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4. - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles - * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles - * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles - * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles - * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles - * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles - * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles - * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles - * @retval None - */ -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_INJECTED_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ - if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10)); - /* Clear the old channel sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); - /* Set the new channel sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); - /* Clear the old channel sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - /* Set the new channel sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - /* Rank configuration */ - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - /* Get JL value: Number = JL+1 */ - tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20; - /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ - tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Clear the old JSQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Set the JSQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Configures the sequencer length for injected channels - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param Length: The sequencer length. - * This parameter must be a number between 1 to 4. - * @retval None - */ -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_LENGTH(Length)); - - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - /* Clear the old injected sequnence lenght JL bits */ - tmpreg1 &= JSQR_JL_Reset; - /* Set the injected sequnence lenght JL bits */ - tmpreg2 = Length - 1; - tmpreg1 |= tmpreg2 << 20; - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Set the injected channels conversion value offset - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InjectedChannel: the ADC injected channel to set its offset. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @param Offset: the offset value for the selected ADC injected channel - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - assert_param(IS_ADC_OFFSET(Offset)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel; - - /* Set the selected injected channel data offset */ - *(__IO uint32_t *) tmp = (uint32_t)Offset; -} - -/** - * @brief Returns the ADC injected channel conversion result - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InjectedChannel: the converted ADC injected channel. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @retval The Data conversion value. - */ -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel + JDR_Offset; - - /* Returns the selected injected channel conversion data value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} - -/** - * @brief Enables or disables the analog watchdog on single/all regular - * or injected channels - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. - * This parameter can be one of the following values: - * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel - * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel - * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel - * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel - * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel - * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels - * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog - * @retval None - */ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); - /* Get the old register value */ - tmpreg = ADCx->CR1; - /* Clear AWDEN, AWDENJ and AWDSGL bits */ - tmpreg &= CR1_AWDMode_Reset; - /* Set the analog watchdog enable mode */ - tmpreg |= ADC_AnalogWatchdog; - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} - -/** - * @brief Configures the high and low thresholds of the analog watchdog. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param HighThreshold: the ADC analog watchdog High threshold value. - * This parameter must be a 12bit value. - * @param LowThreshold: the ADC analog watchdog Low threshold value. - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_THRESHOLD(HighThreshold)); - assert_param(IS_ADC_THRESHOLD(LowThreshold)); - /* Set the ADCx high threshold */ - ADCx->HTR = HighThreshold; - /* Set the ADCx low threshold */ - ADCx->LTR = LowThreshold; -} - -/** - * @brief Configures the analog watchdog guarded single channel - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure for the analog watchdog. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @retval None - */ -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - /* Get the old register value */ - tmpreg = ADCx->CR1; - /* Clear the Analog watchdog channel select bits */ - tmpreg &= CR1_AWDCH_Reset; - /* Set the Analog watchdog channel */ - tmpreg |= ADC_Channel; - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} - -/** - * @brief Enables or disables the temperature sensor and Vrefint channel. - * @param NewState: new state of the temperature sensor. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_TempSensorVrefintCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the temperature sensor and Vrefint channel*/ - ADC1->CR2 |= CR2_TSVREFE_Set; - } - else - { - /* Disable the temperature sensor and Vrefint channel*/ - ADC1->CR2 &= CR2_TSVREFE_Reset; - } -} - -/** - * @brief Checks whether the specified ADC flag is set or not. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @retval The new state of ADC_FLAG (SET or RESET). - */ -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); - /* Check the status of the specified ADC flag */ - if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) - { - /* ADC_FLAG is set */ - bitstatus = SET; - } - else - { - /* ADC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the ADC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's pending flags. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @retval None - */ -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); - /* Clear the selected ADC flags */ - ADCx->SR = ~(uint32_t)ADC_FLAG; -} - -/** - * @brief Checks whether the specified ADC interrupt has occurred or not. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt source to check. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @retval The new state of ADC_IT (SET or RESET). - */ -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t itmask = 0, enablestatus = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_IT(ADC_IT)); - /* Get the ADC IT index */ - itmask = ADC_IT >> 8; - /* Get the ADC_IT enable bit status */ - enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ; - /* Check the status of the specified ADC interrupt */ - if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) - { - /* ADC_IT is set */ - bitstatus = SET; - } - else - { - /* ADC_IT is reset */ - bitstatus = RESET; - } - /* Return the ADC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's interrupt pending bits. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @retval None - */ -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - uint8_t itmask = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_IT(ADC_IT)); - /* Get the ADC IT index */ - itmask = (uint8_t)(ADC_IT >> 8); - /* Clear the selected ADC interrupt pending bits */ - ADCx->SR = ~(uint32_t)itmask; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c deleted file mode 100644 index 3004b9ef8..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c +++ /dev/null @@ -1,308 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_bkp.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the BKP firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_bkp.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup BKP - * @brief BKP driver modules - * @{ - */ - -/** @defgroup BKP_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Private_Defines - * @{ - */ - -/* ------------ BKP registers bit address in the alias region --------------- */ -#define BKP_OFFSET (BKP_BASE - PERIPH_BASE) - -/* --- CR Register ----*/ - -/* Alias word address of TPAL bit */ -#define CR_OFFSET (BKP_OFFSET + 0x30) -#define TPAL_BitNumber 0x01 -#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4)) - -/* Alias word address of TPE bit */ -#define TPE_BitNumber 0x00 -#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of TPIE bit */ -#define CSR_OFFSET (BKP_OFFSET + 0x34) -#define TPIE_BitNumber 0x02 -#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4)) - -/* Alias word address of TIF bit */ -#define TIF_BitNumber 0x09 -#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4)) - -/* Alias word address of TEF bit */ -#define TEF_BitNumber 0x08 -#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4)) - -/* ---------------------- BKP registers bit mask ------------------------ */ - -/* RTCCR register bit mask */ -#define RTCCR_CAL_MASK ((uint16_t)0xFF80) -#define RTCCR_MASK ((uint16_t)0xFC7F) - -/** - * @} - */ - - -/** @defgroup BKP_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the BKP peripheral registers to their default reset values. - * @param None - * @retval None - */ -void BKP_DeInit(void) -{ - RCC_BackupResetCmd(ENABLE); - RCC_BackupResetCmd(DISABLE); -} - -/** - * @brief Configures the Tamper Pin active level. - * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. - * This parameter can be one of the following values: - * @arg BKP_TamperPinLevel_High: Tamper pin active on high level - * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level - * @retval None - */ -void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) -{ - /* Check the parameters */ - assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel)); - *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel; -} - -/** - * @brief Enables or disables the Tamper Pin activation. - * @param NewState: new state of the Tamper Pin activation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void BKP_TamperPinCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Tamper Pin Interrupt. - * @param NewState: new state of the Tamper Pin Interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void BKP_ITConfig(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState; -} - -/** - * @brief Select the RTC output source to output on the Tamper pin. - * @param BKP_RTCOutputSource: specifies the RTC output source. - * This parameter can be one of the following values: - * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin. - * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency - * divided by 64 on the Tamper pin. - * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on - * the Tamper pin. - * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on - * the Tamper pin. - * @retval None - */ -void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) -{ - uint16_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource)); - tmpreg = BKP->RTCCR; - /* Clear CCO, ASOE and ASOS bits */ - tmpreg &= RTCCR_MASK; - - /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */ - tmpreg |= BKP_RTCOutputSource; - /* Store the new value */ - BKP->RTCCR = tmpreg; -} - -/** - * @brief Sets RTC Clock Calibration value. - * @param CalibrationValue: specifies the RTC Clock Calibration value. - * This parameter must be a number between 0 and 0x7F. - * @retval None - */ -void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) -{ - uint16_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue)); - tmpreg = BKP->RTCCR; - /* Clear CAL[6:0] bits */ - tmpreg &= RTCCR_CAL_MASK; - /* Set CAL[6:0] bits according to CalibrationValue value */ - tmpreg |= CalibrationValue; - /* Store the new value */ - BKP->RTCCR = tmpreg; -} - -/** - * @brief Writes user data to the specified Data Backup Register. - * @param BKP_DR: specifies the Data Backup Register. - * This parameter can be BKP_DRx where x:[1, 42] - * @param Data: data to write - * @retval None - */ -void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_BKP_DR(BKP_DR)); - - tmp = (uint32_t)BKP_BASE; - tmp += BKP_DR; - - *(__IO uint32_t *) tmp = Data; -} - -/** - * @brief Reads data from the specified Data Backup Register. - * @param BKP_DR: specifies the Data Backup Register. - * This parameter can be BKP_DRx where x:[1, 42] - * @retval The content of the specified Data Backup Register - */ -uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_BKP_DR(BKP_DR)); - - tmp = (uint32_t)BKP_BASE; - tmp += BKP_DR; - - return (*(__IO uint16_t *) tmp); -} - -/** - * @brief Checks whether the Tamper Pin Event flag is set or not. - * @param None - * @retval The new state of the Tamper Pin Event flag (SET or RESET). - */ -FlagStatus BKP_GetFlagStatus(void) -{ - return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB); -} - -/** - * @brief Clears Tamper Pin Event pending flag. - * @param None - * @retval None - */ -void BKP_ClearFlag(void) -{ - /* Set CTE bit to clear Tamper Pin Event flag */ - BKP->CSR |= BKP_CSR_CTE; -} - -/** - * @brief Checks whether the Tamper Pin Interrupt has occurred or not. - * @param None - * @retval The new state of the Tamper Pin Interrupt (SET or RESET). - */ -ITStatus BKP_GetITStatus(void) -{ - return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB); -} - -/** - * @brief Clears Tamper Pin Interrupt pending bit. - * @param None - * @retval None - */ -void BKP_ClearITPendingBit(void) -{ - /* Set CTI bit to clear Tamper Pin Interrupt pending bit */ - BKP->CSR |= BKP_CSR_CTI; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c deleted file mode 100644 index 607d6924f..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c +++ /dev/null @@ -1,1415 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_can.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the CAN firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_can.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup CAN - * @brief CAN driver modules - * @{ - */ - -/** @defgroup CAN_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup CAN_Private_Defines - * @{ - */ - -/* CAN Master Control Register bits */ - -#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ - -/* CAN Mailbox Transmit Request */ -#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ - -/* CAN Filter Master Register bits */ -#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ - -/* Time out for INAK bit */ -#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) -/* Time out for SLAK bit */ -#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) - - - -/* Flags in TSR register */ -#define CAN_FLAGS_TSR ((uint32_t)0x08000000) -/* Flags in RF1R register */ -#define CAN_FLAGS_RF1R ((uint32_t)0x04000000) -/* Flags in RF0R register */ -#define CAN_FLAGS_RF0R ((uint32_t)0x02000000) -/* Flags in MSR register */ -#define CAN_FLAGS_MSR ((uint32_t)0x01000000) -/* Flags in ESR register */ -#define CAN_FLAGS_ESR ((uint32_t)0x00F00000) - -/* Mailboxes definition */ -#define CAN_TXMAILBOX_0 ((uint8_t)0x00) -#define CAN_TXMAILBOX_1 ((uint8_t)0x01) -#define CAN_TXMAILBOX_2 ((uint8_t)0x02) - - - -#define CAN_MODE_MASK ((uint32_t) 0x00000003) -/** - * @} - */ - -/** @defgroup CAN_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CAN_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup CAN_Private_FunctionPrototypes - * @{ - */ - -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); - -/** - * @} - */ - -/** @defgroup CAN_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the CAN peripheral registers to their default reset values. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @retval None. - */ -void CAN_DeInit(CAN_TypeDef* CANx) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - if (CANx == CAN1) - { - /* Enable CAN1 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); - /* Release CAN1 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); - } - else - { - /* Enable CAN2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); - /* Release CAN2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); - } -} - -/** - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_InitStruct. - * @param CANx: where x can be 1 or 2 to to select the CAN - * peripheral. - * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that - * contains the configuration information for the - * CAN peripheral. - * @retval Constant indicates initialization succeed which will be - * CAN_InitStatus_Failed or CAN_InitStatus_Success. - */ -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) -{ - uint8_t InitStatus = CAN_InitStatus_Failed; - uint32_t wait_ack = 0x00000000; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); - assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); - assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); - assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); - assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); - assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); - - /* Exit from sleep mode */ - CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP); - - /* Request initialisation */ - CANx->MCR |= CAN_MCR_INRQ ; - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - /* Check acknowledge */ - if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - /* Set the time triggered communication mode */ - if (CAN_InitStruct->CAN_TTCM == ENABLE) - { - CANx->MCR |= CAN_MCR_TTCM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM; - } - - /* Set the automatic bus-off management */ - if (CAN_InitStruct->CAN_ABOM == ENABLE) - { - CANx->MCR |= CAN_MCR_ABOM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM; - } - - /* Set the automatic wake-up mode */ - if (CAN_InitStruct->CAN_AWUM == ENABLE) - { - CANx->MCR |= CAN_MCR_AWUM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM; - } - - /* Set the no automatic retransmission */ - if (CAN_InitStruct->CAN_NART == ENABLE) - { - CANx->MCR |= CAN_MCR_NART; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_NART; - } - - /* Set the receive FIFO locked mode */ - if (CAN_InitStruct->CAN_RFLM == ENABLE) - { - CANx->MCR |= CAN_MCR_RFLM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM; - } - - /* Set the transmit FIFO priority */ - if (CAN_InitStruct->CAN_TXFP == ENABLE) - { - CANx->MCR |= CAN_MCR_TXFP; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP; - } - - /* Set the bit timing register */ - CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ - ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ - ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ - ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ - ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); - - /* Request leave initialisation */ - CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ; - - /* Wait the acknowledge */ - wait_ack = 0; - - while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - /* ...and check acknowledged */ - if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - InitStatus = CAN_InitStatus_Success ; - } - } - - /* At this step, return the status of initialization */ - return InitStatus; -} - -/** - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_FilterInitStruct. - * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef - * structure that contains the configuration - * information. - * @retval None. - */ -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) -{ - uint32_t filter_number_bit_pos = 0; - /* Check the parameters */ - assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); - assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); - assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); - assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); - assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); - - filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; - - /* Initialisation mode for the filter */ - CAN1->FMR |= FMR_FINIT; - - /* Filter Deactivation */ - CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; - - /* Filter Scale */ - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) - { - /* 16-bit scale for the filter */ - CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); - } - - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) - { - /* 32-bit scale for the filter */ - CAN1->FS1R |= filter_number_bit_pos; - /* 32-bit identifier or First 32-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - /* 32-bit mask or Second 32-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); - } - - /* Filter Mode */ - if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) - { - /*Id/Mask mode for the filter*/ - CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; - } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ - { - /*Identifier list mode for the filter*/ - CAN1->FM1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter FIFO assignment */ - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) - { - /* FIFO 0 assignation for the filter */ - CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; - } - - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) - { - /* FIFO 1 assignation for the filter */ - CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter activation */ - if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) - { - CAN1->FA1R |= filter_number_bit_pos; - } - - /* Leave the initialisation mode for the filter */ - CAN1->FMR &= ~FMR_FINIT; -} - -/** - * @brief Fills each CAN_InitStruct member with its default value. - * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which - * will be initialized. - * @retval None. - */ -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) -{ - /* Reset CAN init structure parameters values */ - - /* Initialize the time triggered communication mode */ - CAN_InitStruct->CAN_TTCM = DISABLE; - - /* Initialize the automatic bus-off management */ - CAN_InitStruct->CAN_ABOM = DISABLE; - - /* Initialize the automatic wake-up mode */ - CAN_InitStruct->CAN_AWUM = DISABLE; - - /* Initialize the no automatic retransmission */ - CAN_InitStruct->CAN_NART = DISABLE; - - /* Initialize the receive FIFO locked mode */ - CAN_InitStruct->CAN_RFLM = DISABLE; - - /* Initialize the transmit FIFO priority */ - CAN_InitStruct->CAN_TXFP = DISABLE; - - /* Initialize the CAN_Mode member */ - CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; - - /* Initialize the CAN_SJW member */ - CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; - - /* Initialize the CAN_BS1 member */ - CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; - - /* Initialize the CAN_BS2 member */ - CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; - - /* Initialize the CAN_Prescaler member */ - CAN_InitStruct->CAN_Prescaler = 1; -} - -/** - * @brief Select the start bank filter for slave CAN. - * @note This function applies only to STM32 Connectivity line devices. - * @param CAN_BankNumber: Select the start slave bank filter from 1..27. - * @retval None. - */ -void CAN_SlaveStartBank(uint8_t CAN_BankNumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); - - /* Enter Initialisation mode for the filter */ - CAN1->FMR |= FMR_FINIT; - - /* Select the start slave bank */ - CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; - CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8; - - /* Leave Initialisation mode for the filter */ - CAN1->FMR &= ~FMR_FINIT; -} - -/** - * @brief Enables or disables the DBG Freeze for CAN. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param NewState: new state of the CAN peripheral. This parameter can - * be: ENABLE or DISABLE. - * @retval None. - */ -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Debug Freeze */ - CANx->MCR |= MCR_DBF; - } - else - { - /* Disable Debug Freeze */ - CANx->MCR &= ~MCR_DBF; - } -} - - -/** - * @brief Enables or disabes the CAN Time TriggerOperation communication mode. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param NewState : Mode new state , can be one of @ref FunctionalState. - * @note when enabled, Time stamp (TIME[15:0]) value is sent in the last - * two data bytes of the 8-byte message: TIME[7:0] in data byte 6 - * and TIME[15:8] in data byte 7 - * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be - * sent over the CAN bus. - * @retval None - */ -void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the TTCM mode */ - CANx->MCR |= CAN_MCR_TTCM; - - /* Set TGT bits */ - CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT); - CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT); - CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT); - } - else - { - /* Disable the TTCM mode */ - CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM); - - /* Reset TGT bits */ - CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT); - CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT); - CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT); - } -} -/** - * @brief Initiates the transmission of a message. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param TxMessage: pointer to a structure which contains CAN Id, CAN - * DLC and CAN data. - * @retval The number of the mailbox that is used for transmission - * or CAN_TxStatus_NoMailBox if there is no empty mailbox. - */ -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) -{ - uint8_t transmit_mailbox = 0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); - assert_param(IS_CAN_RTR(TxMessage->RTR)); - assert_param(IS_CAN_DLC(TxMessage->DLC)); - - /* Select one empty transmit mailbox */ - if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmit_mailbox = 0; - } - else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmit_mailbox = 1; - } - else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) - { - transmit_mailbox = 2; - } - else - { - transmit_mailbox = CAN_TxStatus_NoMailBox; - } - - if (transmit_mailbox != CAN_TxStatus_NoMailBox) - { - /* Set up the Id */ - CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; - if (TxMessage->IDE == CAN_Id_Standard) - { - assert_param(IS_CAN_STDID(TxMessage->StdId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \ - TxMessage->RTR); - } - else - { - assert_param(IS_CAN_EXTID(TxMessage->ExtId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \ - TxMessage->IDE | \ - TxMessage->RTR); - } - - /* Set up the DLC */ - TxMessage->DLC &= (uint8_t)0x0000000F; - CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; - CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; - - /* Set up the data field */ - CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | - ((uint32_t)TxMessage->Data[2] << 16) | - ((uint32_t)TxMessage->Data[1] << 8) | - ((uint32_t)TxMessage->Data[0])); - CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | - ((uint32_t)TxMessage->Data[6] << 16) | - ((uint32_t)TxMessage->Data[5] << 8) | - ((uint32_t)TxMessage->Data[4])); - /* Request transmission */ - CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; - } - return transmit_mailbox; -} - -/** - * @brief Checks the transmission of a message. - * @param CANx: where x can be 1 or 2 to to select the - * CAN peripheral. - * @param TransmitMailbox: the number of the mailbox that is used for - * transmission. - * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed - * in an other case. - */ -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) -{ - uint32_t state = 0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); - - switch (TransmitMailbox) - { - case (CAN_TXMAILBOX_0): - state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0); - break; - case (CAN_TXMAILBOX_1): - state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1); - break; - case (CAN_TXMAILBOX_2): - state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2); - break; - default: - state = CAN_TxStatus_Failed; - break; - } - switch (state) - { - /* transmit pending */ - case (0x0): state = CAN_TxStatus_Pending; - break; - /* transmit failed */ - case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed; - break; - case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed; - break; - case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed; - break; - /* transmit succeeded */ - case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok; - break; - case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok; - break; - case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok; - break; - default: state = CAN_TxStatus_Failed; - break; - } - return (uint8_t) state; -} - -/** - * @brief Cancels a transmit request. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param Mailbox: Mailbox number. - * @retval None. - */ -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); - /* abort transmission */ - switch (Mailbox) - { - case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0; - break; - case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1; - break; - case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2; - break; - default: - break; - } -} - - -/** - * @brief Receives a message. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @param RxMessage: pointer to a structure receive message which contains - * CAN Id, CAN DLC, CAN datas and FMI number. - * @retval None. - */ -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Get the Id */ - RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; - if (RxMessage->IDE == CAN_Id_Standard) - { - RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); - } - else - { - RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); - } - - RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FMI */ - RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); - /* Get the data field */ - RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; - RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); - RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); - RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); - RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; - RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); - RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); - RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); - /* Release the FIFO */ - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - CANx->RF0R |= CAN_RF0R_RFOM0; - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - CANx->RF1R |= CAN_RF1R_RFOM1; - } -} - -/** - * @brief Releases the specified FIFO. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. - * @retval None. - */ -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - CANx->RF0R |= CAN_RF0R_RFOM0; - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - CANx->RF1R |= CAN_RF1R_RFOM1; - } -} - -/** - * @brief Returns the number of pending messages. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval NbMessage : which is the number of pending message. - */ -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - uint8_t message_pending=0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - if (FIFONumber == CAN_FIFO0) - { - message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); - } - else if (FIFONumber == CAN_FIFO1) - { - message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); - } - else - { - message_pending = 0; - } - return message_pending; -} - - -/** - * @brief Select the CAN Operation mode. - * @param CAN_OperatingMode : CAN Operating Mode. This parameter can be one - * of @ref CAN_OperatingMode_TypeDef enumeration. - * @retval status of the requested mode which can be - * - CAN_ModeStatus_Failed CAN failed entering the specific mode - * - CAN_ModeStatus_Success CAN Succeed entering the specific mode - - */ -uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) -{ - uint8_t status = CAN_ModeStatus_Failed; - - /* Timeout for INAK or also for SLAK bits*/ - uint32_t timeout = INAK_TIMEOUT; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode)); - - if (CAN_OperatingMode == CAN_OperatingMode_Initialization) - { - /* Request initialisation */ - CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if (CAN_OperatingMode == CAN_OperatingMode_Normal) - { - /* Request leave initialisation and sleep mode and enter Normal mode */ - CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ)); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != 0) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) - { - /* Request Sleep mode */ - CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else - { - status = CAN_ModeStatus_Failed; - } - - return (uint8_t) status; -} - -/** - * @brief Enters the low power mode. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval status: CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an - * other case. - */ -uint8_t CAN_Sleep(CAN_TypeDef* CANx) -{ - uint8_t sleepstatus = CAN_Sleep_Failed; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Request Sleep mode */ - CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Sleep mode status */ - if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) - { - /* Sleep mode not entered */ - sleepstatus = CAN_Sleep_Ok; - } - /* return sleep mode status */ - return (uint8_t)sleepstatus; -} - -/** - * @brief Wakes the CAN up. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval status: CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an - * other case. - */ -uint8_t CAN_WakeUp(CAN_TypeDef* CANx) -{ - uint32_t wait_slak = SLAK_TIMEOUT; - uint8_t wakeupstatus = CAN_WakeUp_Failed; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Wake up request */ - CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP; - - /* Sleep mode status */ - while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) - { - wait_slak--; - } - if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) - { - /* wake up done : Sleep mode exited */ - wakeupstatus = CAN_WakeUp_Ok; - } - /* return wakeup status */ - return (uint8_t)wakeupstatus; -} - - -/** - * @brief Returns the CANx's last error code (LEC). - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval CAN_ErrorCode: specifies the Error code : - * - CAN_ERRORCODE_NoErr No Error - * - CAN_ERRORCODE_StuffErr Stuff Error - * - CAN_ERRORCODE_FormErr Form Error - * - CAN_ERRORCODE_ACKErr Acknowledgment Error - * - CAN_ERRORCODE_BitRecessiveErr Bit Recessive Error - * - CAN_ERRORCODE_BitDominantErr Bit Dominant Error - * - CAN_ERRORCODE_CRCErr CRC Error - * - CAN_ERRORCODE_SoftwareSetErr Software Set Error - */ - -uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) -{ - uint8_t errorcode=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the error code*/ - errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC); - - /* Return the error code*/ - return errorcode; -} -/** - * @brief Returns the CANx Receive Error Counter (REC). - * @note In case of an error during reception, this counter is incremented - * by 1 or by 8 depending on the error condition as defined by the CAN - * standard. After every successful reception, the counter is - * decremented by 1 or reset to 120 if its value was higher than 128. - * When the counter value exceeds 127, the CAN controller enters the - * error passive state. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval CAN Receive Error Counter. - */ -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) -{ - uint8_t counter=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the Receive Error Counter*/ - counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24); - - /* Return the Receive Error Counter*/ - return counter; -} - - -/** - * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval LSB of the 9-bit CAN Transmit Error Counter. - */ -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) -{ - uint8_t counter=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ - counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16); - - /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ - return counter; -} - - -/** - * @brief Enables or disables the specified CANx interrupts. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. - * This parameter can be: - * - CAN_IT_TME, - * - CAN_IT_FMP0, - * - CAN_IT_FF0, - * - CAN_IT_FOV0, - * - CAN_IT_FMP1, - * - CAN_IT_FF1, - * - CAN_IT_FOV1, - * - CAN_IT_EWG, - * - CAN_IT_EPV, - * - CAN_IT_LEC, - * - CAN_IT_ERR, - * - CAN_IT_WKU or - * - CAN_IT_SLK. - * @param NewState: new state of the CAN interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IT(CAN_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected CANx interrupt */ - CANx->IER |= CAN_IT; - } - else - { - /* Disable the selected CANx interrupt */ - CANx->IER &= ~CAN_IT; - } -} -/** - * @brief Checks whether the specified CAN flag is set or not. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_FLAG: specifies the flag to check. - * This parameter can be one of the following flags: - * - CAN_FLAG_EWG - * - CAN_FLAG_EPV - * - CAN_FLAG_BOF - * - CAN_FLAG_RQCP0 - * - CAN_FLAG_RQCP1 - * - CAN_FLAG_RQCP2 - * - CAN_FLAG_FMP1 - * - CAN_FLAG_FF1 - * - CAN_FLAG_FOV1 - * - CAN_FLAG_FMP0 - * - CAN_FLAG_FF0 - * - CAN_FLAG_FOV0 - * - CAN_FLAG_WKU - * - CAN_FLAG_SLAK - * - CAN_FLAG_LEC - * @retval The new state of CAN_FLAG (SET or RESET). - */ -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); - - - if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */ - { - /* Check the status of the specified CAN flag */ - if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - /* Return the CAN_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the CAN's pending flags. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_FLAG: specifies the flag to clear. - * This parameter can be one of the following flags: - * - CAN_FLAG_RQCP0 - * - CAN_FLAG_RQCP1 - * - CAN_FLAG_RQCP2 - * - CAN_FLAG_FF1 - * - CAN_FLAG_FOV1 - * - CAN_FLAG_FF0 - * - CAN_FLAG_FOV0 - * - CAN_FLAG_WKU - * - CAN_FLAG_SLAK - * - CAN_FLAG_LEC - * @retval None. - */ -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - uint32_t flagtmp=0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG)); - - if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */ - { - /* Clear the selected CAN flags */ - CANx->ESR = (uint32_t)RESET; - } - else /* MSR or TSR or RF0R or RF1R */ - { - flagtmp = CAN_FLAG & 0x000FFFFF; - - if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET) - { - /* Receive Flags */ - CANx->RF0R = (uint32_t)(flagtmp); - } - else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET) - { - /* Receive Flags */ - CANx->RF1R = (uint32_t)(flagtmp); - } - else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET) - { - /* Transmit Flags */ - CANx->TSR = (uint32_t)(flagtmp); - } - else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */ - { - /* Operating mode Flags */ - CANx->MSR = (uint32_t)(flagtmp); - } - } -} - -/** - * @brief Checks whether the specified CANx interrupt has occurred or not. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt source to check. - * This parameter can be one of the following flags: - * - CAN_IT_TME - * - CAN_IT_FMP0 - * - CAN_IT_FF0 - * - CAN_IT_FOV0 - * - CAN_IT_FMP1 - * - CAN_IT_FF1 - * - CAN_IT_FOV1 - * - CAN_IT_WKU - * - CAN_IT_SLK - * - CAN_IT_EWG - * - CAN_IT_EPV - * - CAN_IT_BOF - * - CAN_IT_LEC - * - CAN_IT_ERR - * @retval The current state of CAN_IT (SET or RESET). - */ -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - ITStatus itstatus = RESET; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IT(CAN_IT)); - - /* check the enable interrupt bit */ - if((CANx->IER & CAN_IT) != RESET) - { - /* in case the Interrupt is enabled, .... */ - switch (CAN_IT) - { - case CAN_IT_TME: - /* Check CAN_TSR_RQCPx bits */ - itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); - break; - case CAN_IT_FMP0: - /* Check CAN_RF0R_FMP0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); - break; - case CAN_IT_FF0: - /* Check CAN_RF0R_FULL0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); - break; - case CAN_IT_FOV0: - /* Check CAN_RF0R_FOVR0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); - break; - case CAN_IT_FMP1: - /* Check CAN_RF1R_FMP1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); - break; - case CAN_IT_FF1: - /* Check CAN_RF1R_FULL1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); - break; - case CAN_IT_FOV1: - /* Check CAN_RF1R_FOVR1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); - break; - case CAN_IT_WKU: - /* Check CAN_MSR_WKUI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); - break; - case CAN_IT_SLK: - /* Check CAN_MSR_SLAKI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); - break; - case CAN_IT_EWG: - /* Check CAN_ESR_EWGF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); - break; - case CAN_IT_EPV: - /* Check CAN_ESR_EPVF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); - break; - case CAN_IT_BOF: - /* Check CAN_ESR_BOFF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); - break; - case CAN_IT_LEC: - /* Check CAN_ESR_LEC bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); - break; - case CAN_IT_ERR: - /* Check CAN_MSR_ERRI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); - break; - default : - /* in case of error, return RESET */ - itstatus = RESET; - break; - } - } - else - { - /* in case the Interrupt is not enabled, return RESET */ - itstatus = RESET; - } - - /* Return the CAN_IT status */ - return itstatus; -} - -/** - * @brief Clears the CANx's interrupt pending bits. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the interrupt pending bit to clear. - * - CAN_IT_TME - * - CAN_IT_FF0 - * - CAN_IT_FOV0 - * - CAN_IT_FF1 - * - CAN_IT_FOV1 - * - CAN_IT_WKU - * - CAN_IT_SLK - * - CAN_IT_EWG - * - CAN_IT_EPV - * - CAN_IT_BOF - * - CAN_IT_LEC - * - CAN_IT_ERR - * @retval None. - */ -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_CLEAR_IT(CAN_IT)); - - switch (CAN_IT) - { - case CAN_IT_TME: - /* Clear CAN_TSR_RQCPx (rc_w1)*/ - CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2; - break; - case CAN_IT_FF0: - /* Clear CAN_RF0R_FULL0 (rc_w1)*/ - CANx->RF0R = CAN_RF0R_FULL0; - break; - case CAN_IT_FOV0: - /* Clear CAN_RF0R_FOVR0 (rc_w1)*/ - CANx->RF0R = CAN_RF0R_FOVR0; - break; - case CAN_IT_FF1: - /* Clear CAN_RF1R_FULL1 (rc_w1)*/ - CANx->RF1R = CAN_RF1R_FULL1; - break; - case CAN_IT_FOV1: - /* Clear CAN_RF1R_FOVR1 (rc_w1)*/ - CANx->RF1R = CAN_RF1R_FOVR1; - break; - case CAN_IT_WKU: - /* Clear CAN_MSR_WKUI (rc_w1)*/ - CANx->MSR = CAN_MSR_WKUI; - break; - case CAN_IT_SLK: - /* Clear CAN_MSR_SLAKI (rc_w1)*/ - CANx->MSR = CAN_MSR_SLAKI; - break; - case CAN_IT_EWG: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* Note : the corresponding Flag is cleared by hardware depending - of the CAN Bus status*/ - break; - case CAN_IT_EPV: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* Note : the corresponding Flag is cleared by hardware depending - of the CAN Bus status*/ - break; - case CAN_IT_BOF: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* Note : the corresponding Flag is cleared by hardware depending - of the CAN Bus status*/ - break; - case CAN_IT_LEC: - /* Clear LEC bits */ - CANx->ESR = RESET; - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - break; - case CAN_IT_ERR: - /*Clear LEC bits */ - CANx->ESR = RESET; - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending - of the CAN Bus status*/ - break; - default : - break; - } -} - -/** - * @brief Checks whether the CAN interrupt has occurred or not. - * @param CAN_Reg: specifies the CAN interrupt register to check. - * @param It_Bit: specifies the interrupt source bit to check. - * @retval The new state of the CAN Interrupt (SET or RESET). - */ -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) -{ - ITStatus pendingbitstatus = RESET; - - if ((CAN_Reg & It_Bit) != (uint32_t)RESET) - { - /* CAN_IT is set */ - pendingbitstatus = SET; - } - else - { - /* CAN_IT is reset */ - pendingbitstatus = RESET; - } - return pendingbitstatus; -} - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c deleted file mode 100644 index 08b501a0c..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c +++ /dev/null @@ -1,433 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_cec.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the CEC firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_cec.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup CEC - * @brief CEC driver modules - * @{ - */ - -/** @defgroup CEC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - - -/** @defgroup CEC_Private_Defines - * @{ - */ - -/* ------------ CEC registers bit address in the alias region ----------- */ -#define CEC_OFFSET (CEC_BASE - PERIPH_BASE) - -/* --- CFGR Register ---*/ - -/* Alias word address of PE bit */ -#define CFGR_OFFSET (CEC_OFFSET + 0x00) -#define PE_BitNumber 0x00 -#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4)) - -/* Alias word address of IE bit */ -#define IE_BitNumber 0x01 -#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of TSOM bit */ -#define CSR_OFFSET (CEC_OFFSET + 0x10) -#define TSOM_BitNumber 0x00 -#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4)) - -/* Alias word address of TEOM bit */ -#define TEOM_BitNumber 0x01 -#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4)) - -#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */ -#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */ - -/** - * @} - */ - - -/** @defgroup CEC_Private_Macros - * @{ - */ - -/** - * @} - */ - - -/** @defgroup CEC_Private_Variables - * @{ - */ - -/** - * @} - */ - - -/** @defgroup CEC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - - -/** @defgroup CEC_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the CEC peripheral registers to their default reset - * values. - * @param None - * @retval None - */ -void CEC_DeInit(void) -{ - /* Enable CEC reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE); - /* Release CEC from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); -} - - -/** - * @brief Initializes the CEC peripheral according to the specified - * parameters in the CEC_InitStruct. - * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that - * contains the configuration information for the specified - * CEC peripheral. - * @retval None - */ -void CEC_Init(CEC_InitTypeDef* CEC_InitStruct) -{ - uint16_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); - assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode)); - - /*---------------------------- CEC CFGR Configuration -----------------*/ - /* Get the CEC CFGR value */ - tmpreg = CEC->CFGR; - - /* Clear BTEM and BPEM bits */ - tmpreg &= CFGR_CLEAR_Mask; - - /* Configure CEC: Bit Timing Error and Bit Period Error */ - tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode); - - /* Write to CEC CFGR register*/ - CEC->CFGR = tmpreg; - -} - -/** - * @brief Enables or disables the specified CEC peripheral. - * @param NewState: new state of the CEC peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CEC_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState; - - if(NewState == DISABLE) - { - /* Wait until the PE bit is cleared by hardware (Idle Line detected) */ - while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET) - { - } - } -} - -/** - * @brief Enables or disables the CEC interrupt. - * @param NewState: new state of the CEC interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CEC_ITConfig(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState; -} - -/** - * @brief Defines the Own Address of the CEC device. - * @param CEC_OwnAddress: The CEC own address - * @retval None - */ -void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress) -{ - /* Check the parameters */ - assert_param(IS_CEC_ADDRESS(CEC_OwnAddress)); - - /* Set the CEC own address */ - CEC->OAR = CEC_OwnAddress; -} - -/** - * @brief Sets the CEC prescaler value. - * @param CEC_Prescaler: CEC prescaler new value - * @retval None - */ -void CEC_SetPrescaler(uint16_t CEC_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_CEC_PRESCALER(CEC_Prescaler)); - - /* Set the Prescaler value*/ - CEC->PRES = CEC_Prescaler; -} - -/** - * @brief Transmits single data through the CEC peripheral. - * @param Data: the data to transmit. - * @retval None - */ -void CEC_SendDataByte(uint8_t Data) -{ - /* Transmit Data */ - CEC->TXD = Data ; -} - - -/** - * @brief Returns the most recent received data by the CEC peripheral. - * @param None - * @retval The received data. - */ -uint8_t CEC_ReceiveDataByte(void) -{ - /* Receive Data */ - return (uint8_t)(CEC->RXD); -} - -/** - * @brief Starts a new message. - * @param None - * @retval None - */ -void CEC_StartOfMessage(void) -{ - /* Starts of new message */ - *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1; -} - -/** - * @brief Transmits message with or without an EOM bit. - * @param NewState: new state of the CEC Tx End Of Message. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CEC_EndOfMessageCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* The data byte will be transmitted with or without an EOM bit*/ - *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState; -} - -/** - * @brief Gets the CEC flag status - * @param CEC_FLAG: specifies the CEC flag to check. - * This parameter can be one of the following values: - * @arg CEC_FLAG_BTE: Bit Timing Error - * @arg CEC_FLAG_BPE: Bit Period Error - * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error - * @arg CEC_FLAG_SBE: Start Bit Error - * @arg CEC_FLAG_ACKE: Block Acknowledge Error - * @arg CEC_FLAG_LINE: Line Error - * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error - * @arg CEC_FLAG_TEOM: Tx End Of Message - * @arg CEC_FLAG_TERR: Tx Error - * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished - * @arg CEC_FLAG_RSOM: Rx Start Of Message - * @arg CEC_FLAG_REOM: Rx End Of Message - * @arg CEC_FLAG_RERR: Rx Error - * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished - * @retval The new state of CEC_FLAG (SET or RESET) - */ -FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t cecreg = 0, cecbase = 0; - - /* Check the parameters */ - assert_param(IS_CEC_GET_FLAG(CEC_FLAG)); - - /* Get the CEC peripheral base address */ - cecbase = (uint32_t)(CEC_BASE); - - /* Read flag register index */ - cecreg = CEC_FLAG >> 28; - - /* Get bit[23:0] of the flag */ - CEC_FLAG &= FLAG_Mask; - - if(cecreg != 0) - { - /* Flag in CEC ESR Register */ - CEC_FLAG = (uint32_t)(CEC_FLAG >> 16); - - /* Get the CEC ESR register address */ - cecbase += 0xC; - } - else - { - /* Get the CEC CSR register address */ - cecbase += 0x10; - } - - if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET) - { - /* CEC_FLAG is set */ - bitstatus = SET; - } - else - { - /* CEC_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the CEC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the CEC's pending flags. - * @param CEC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg CEC_FLAG_TERR: Tx Error - * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished - * @arg CEC_FLAG_RSOM: Rx Start Of Message - * @arg CEC_FLAG_REOM: Rx End Of Message - * @arg CEC_FLAG_RERR: Rx Error - * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished - * @retval None - */ -void CEC_ClearFlag(uint32_t CEC_FLAG) -{ - uint32_t tmp = 0x0; - - /* Check the parameters */ - assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG)); - - tmp = CEC->CSR & 0x2; - - /* Clear the selected CEC flags */ - CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp); -} - -/** - * @brief Checks whether the specified CEC interrupt has occurred or not. - * @param CEC_IT: specifies the CEC interrupt source to check. - * This parameter can be one of the following values: - * @arg CEC_IT_TERR: Tx Error - * @arg CEC_IT_TBTF: Tx Block Transfer Finished - * @arg CEC_IT_RERR: Rx Error - * @arg CEC_IT_RBTF: Rx Block Transfer Finished - * @retval The new state of CEC_IT (SET or RESET). - */ -ITStatus CEC_GetITStatus(uint8_t CEC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_CEC_GET_IT(CEC_IT)); - - /* Get the CEC IT enable bit status */ - enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ; - - /* Check the status of the specified CEC interrupt */ - if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus) - { - /* CEC_IT is set */ - bitstatus = SET; - } - else - { - /* CEC_IT is reset */ - bitstatus = RESET; - } - /* Return the CEC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the CEC's interrupt pending bits. - * @param CEC_IT: specifies the CEC interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg CEC_IT_TERR: Tx Error - * @arg CEC_IT_TBTF: Tx Block Transfer Finished - * @arg CEC_IT_RERR: Rx Error - * @arg CEC_IT_RBTF: Rx Block Transfer Finished - * @retval None - */ -void CEC_ClearITPendingBit(uint16_t CEC_IT) -{ - uint32_t tmp = 0x0; - - /* Check the parameters */ - assert_param(IS_CEC_GET_IT(CEC_IT)); - - tmp = CEC->CSR & 0x2; - - /* Clear the selected CEC interrupt pending bits */ - CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c deleted file mode 100644 index ef0c047d8..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c +++ /dev/null @@ -1,160 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_crc.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the CRC firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_crc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRC - * @brief CRC driver modules - * @{ - */ - -/** @defgroup CRC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Private_Defines - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Private_Functions - * @{ - */ - -/** - * @brief Resets the CRC Data register (DR). - * @param None - * @retval None - */ -void CRC_ResetDR(void) -{ - /* Reset CRC generator */ - CRC->CR = CRC_CR_RESET; -} - -/** - * @brief Computes the 32-bit CRC of a given data word(32-bit). - * @param Data: data word(32-bit) to compute its CRC - * @retval 32-bit CRC - */ -uint32_t CRC_CalcCRC(uint32_t Data) -{ - CRC->DR = Data; - - return (CRC->DR); -} - -/** - * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). - * @param pBuffer: pointer to the buffer containing the data to be computed - * @param BufferLength: length of the buffer to be computed - * @retval 32-bit CRC - */ -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) -{ - uint32_t index = 0; - - for(index = 0; index < BufferLength; index++) - { - CRC->DR = pBuffer[index]; - } - return (CRC->DR); -} - -/** - * @brief Returns the current CRC value. - * @param None - * @retval 32-bit CRC - */ -uint32_t CRC_GetCRC(void) -{ - return (CRC->DR); -} - -/** - * @brief Stores a 8-bit data in the Independent Data(ID) register. - * @param IDValue: 8-bit value to be stored in the ID register - * @retval None - */ -void CRC_SetIDRegister(uint8_t IDValue) -{ - CRC->IDR = IDValue; -} - -/** - * @brief Returns the 8-bit data stored in the Independent Data(ID) register - * @param None - * @retval 8-bit value of the ID register - */ -uint8_t CRC_GetIDRegister(void) -{ - return (CRC->IDR); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c deleted file mode 100644 index 025b8e283..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c +++ /dev/null @@ -1,571 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dac.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the DAC firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_dac.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup DAC - * @brief DAC driver modules - * @{ - */ - -/** @defgroup DAC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Private_Defines - * @{ - */ - -/* CR register Mask */ -#define CR_CLEAR_MASK ((uint32_t)0x00000FFE) - -/* DAC Dual Channels SWTRIG masks */ -#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) -#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) - -/* DHR registers offsets */ -#define DHR12R1_OFFSET ((uint32_t)0x00000008) -#define DHR12R2_OFFSET ((uint32_t)0x00000014) -#define DHR12RD_OFFSET ((uint32_t)0x00000020) - -/* DOR register offset */ -#define DOR_OFFSET ((uint32_t)0x0000002C) -/** - * @} - */ - -/** @defgroup DAC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the DAC peripheral registers to their default reset values. - * @param None - * @retval None - */ -void DAC_DeInit(void) -{ - /* Enable DAC reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); - /* Release DAC from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); -} - -/** - * @brief Initializes the DAC peripheral according to the specified - * parameters in the DAC_InitStruct. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that - * contains the configuration information for the specified DAC channel. - * @retval None - */ -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - /* Check the DAC parameters */ - assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); - assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); - assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); - assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); -/*---------------------------- DAC CR Configuration --------------------------*/ - /* Get the DAC CR value */ - tmpreg1 = DAC->CR; - /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); - /* Configure for the selected DAC channel: buffer output, trigger, wave generation, - mask/amplitude for wave generation */ - /* Set TSELx and TENx bits according to DAC_Trigger value */ - /* Set WAVEx bits according to DAC_WaveGeneration value */ - /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ - /* Set BOFFx bit according to DAC_OutputBuffer value */ - tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); - /* Calculate CR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << DAC_Channel; - /* Write to DAC CR */ - DAC->CR = tmpreg1; -} - -/** - * @brief Fills each DAC_InitStruct member with its default value. - * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) -{ -/*--------------- Reset DAC init structure parameters values -----------------*/ - /* Initialize the DAC_Trigger member */ - DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; - /* Initialize the DAC_WaveGeneration member */ - DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; - /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; - /* Initialize the DAC_OutputBuffer member */ - DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; -} - -/** - * @brief Enables or disables the specified DAC channel. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the DAC channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected DAC channel */ - DAC->CR |= (DAC_CR_EN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel */ - DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel); - } -} -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/** - * @brief Enables or disables the specified DAC interrupts. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @param NewState: new state of the specified DAC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_DAC_IT(DAC_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC interrupts */ - DAC->CR |= (DAC_IT << DAC_Channel); - } - else - { - /* Disable the selected DAC interrupts */ - DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); - } -} -#endif - -/** - * @brief Enables or disables the specified DAC channel DMA request. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel DMA request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected DAC channel DMA request */ - DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel DMA request */ - DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel); - } -} - -/** - * @brief Enables or disables the selected DAC channel software trigger. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel software trigger. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable software trigger for the selected DAC channel */ - DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); - } - else - { - /* Disable software trigger for the selected DAC channel */ - DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); - } -} - -/** - * @brief Enables or disables simultaneously the two DAC channels software - * triggers. - * @param NewState: new state of the DAC channels software triggers. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable software trigger for both DAC channels */ - DAC->SWTRIGR |= DUAL_SWTRIG_SET ; - } - else - { - /* Disable software trigger for both DAC channels */ - DAC->SWTRIGR &= DUAL_SWTRIG_RESET; - } -} - -/** - * @brief Enables or disables the selected DAC channel wave generation. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_Wave: Specifies the wave type to enable or disable. - * This parameter can be one of the following values: - * @arg DAC_Wave_Noise: noise wave generation - * @arg DAC_Wave_Triangle: triangle wave generation - * @param NewState: new state of the selected DAC channel wave generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_WAVE(DAC_Wave)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected wave generation for the selected DAC channel */ - DAC->CR |= DAC_Wave << DAC_Channel; - } - else - { - /* Disable the selected wave generation for the selected DAC channel */ - DAC->CR &= ~(DAC_Wave << DAC_Channel); - } -} - -/** - * @brief Set the specified data holding register value for DAC channel1. - * @param DAC_Align: Specifies the data alignment for DAC channel1. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data : Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R1_OFFSET + DAC_Align; - - /* Set the DAC channel1 selected data holding register */ - *(__IO uint32_t *) tmp = Data; -} - -/** - * @brief Set the specified data holding register value for DAC channel2. - * @param DAC_Align: Specifies the data alignment for DAC channel2. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data : Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R2_OFFSET + DAC_Align; - - /* Set the DAC channel2 selected data holding register */ - *(__IO uint32_t *)tmp = Data; -} - -/** - * @brief Set the specified data holding register value for dual channel - * DAC. - * @param DAC_Align: Specifies the data alignment for dual channel DAC. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data2: Data for DAC Channel2 to be loaded in the selected data - * holding register. - * @param Data1: Data for DAC Channel1 to be loaded in the selected data - * holding register. - * @retval None - */ -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) -{ - uint32_t data = 0, tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data1)); - assert_param(IS_DAC_DATA(Data2)); - - /* Calculate and set dual DAC data holding register value */ - if (DAC_Align == DAC_Align_8b_R) - { - data = ((uint32_t)Data2 << 8) | Data1; - } - else - { - data = ((uint32_t)Data2 << 16) | Data1; - } - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12RD_OFFSET + DAC_Align; - - /* Set the dual DAC selected data holding register */ - *(__IO uint32_t *)tmp = data; -} - -/** - * @brief Returns the last data output value of the selected DAC channel. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @retval The selected DAC channel data output value. - */ -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - - tmp = (uint32_t) DAC_BASE ; - tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); - - /* Returns the DAC channel data output register value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) -/** - * @brief Checks whether the specified DAC flag is set or not. - * @param DAC_Channel: thee selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to check. - * This parameter can be only of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @retval The new state of DAC_FLAG (SET or RESET). - */ -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Check the status of the specified DAC flag */ - if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) - { - /* DAC_FLAG is set */ - bitstatus = SET; - } - else - { - /* DAC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the DAC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channelx's pending flags. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to clear. - * This parameter can be of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @retval None - */ -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Clear the selected DAC flags */ - DAC->SR = (DAC_FLAG << DAC_Channel); -} - -/** - * @brief Checks whether the specified DAC interrupt has occurred or not. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt source to check. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @retval The new state of DAC_IT (SET or RESET). - */ -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Get the DAC_IT enable bit status */ - enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; - - /* Check the status of the specified DAC interrupt */ - if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) - { - /* DAC_IT is set */ - bitstatus = SET; - } - else - { - /* DAC_IT is reset */ - bitstatus = RESET; - } - /* Return the DAC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channelx's interrupt pending bits. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt pending bit to clear. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @retval None - */ -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Clear the selected DAC interrupt pending bits */ - DAC->SR = (DAC_IT << DAC_Channel); -} -#endif - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c deleted file mode 100644 index d34307b05..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c +++ /dev/null @@ -1,162 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dbgmcu.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the DBGMCU firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_dbgmcu.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup DBGMCU - * @brief DBGMCU driver modules - * @{ - */ - -/** @defgroup DBGMCU_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Private_Defines - * @{ - */ - -#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) -/** - * @} - */ - -/** @defgroup DBGMCU_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Private_Functions - * @{ - */ - -/** - * @brief Returns the device revision identifier. - * @param None - * @retval Device revision identifier - */ -uint32_t DBGMCU_GetREVID(void) -{ - return(DBGMCU->IDCODE >> 16); -} - -/** - * @brief Returns the device identifier. - * @param None - * @retval Device identifier - */ -uint32_t DBGMCU_GetDEVID(void) -{ - return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); -} - -/** - * @brief Configures the specified peripheral and low power mode behavior - * when the MCU under Debug mode. - * @param DBGMCU_Periph: specifies the peripheral and low power mode. - * This parameter can be any combination of the following values: - * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode - * @arg DBGMCU_STOP: Keep debugger connection during STOP mode - * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode - * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted - * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted - * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted - * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted - * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted - * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted - * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted - * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted - * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted - * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted - * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted - * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted - * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted - * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted - * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted - * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted - * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted - * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted - * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted - * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted - * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted - * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted - * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted - * @param NewState: new state of the specified peripheral in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->CR |= DBGMCU_Periph; - } - else - { - DBGMCU->CR &= ~DBGMCU_Periph; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c deleted file mode 100644 index 0c86f9018..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c +++ /dev/null @@ -1,714 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dma.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the DMA firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_dma.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup DMA - * @brief DMA driver modules - * @{ - */ - -/** @defgroup DMA_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - -/** @defgroup DMA_Private_Defines - * @{ - */ - - -/* DMA1 Channelx interrupt pending bit masks */ -#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) -#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) -#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) -#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) -#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) -#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6)) -#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7)) - -/* DMA2 Channelx interrupt pending bit masks */ -#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) -#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) -#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) -#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) -#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) - -/* DMA2 FLAG mask */ -#define FLAG_Mask ((uint32_t)0x10000000) - -/* DMA registers Masks */ -#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F) - -/** - * @} - */ - -/** @defgroup DMA_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DMA_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup DMA_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup DMA_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the DMAy Channelx registers to their default reset - * values. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @retval None - */ -void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - - /* Disable the selected DMAy Channelx */ - DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); - - /* Reset DMAy Channelx control register */ - DMAy_Channelx->CCR = 0; - - /* Reset DMAy Channelx remaining bytes register */ - DMAy_Channelx->CNDTR = 0; - - /* Reset DMAy Channelx peripheral address register */ - DMAy_Channelx->CPAR = 0; - - /* Reset DMAy Channelx memory address register */ - DMAy_Channelx->CMAR = 0; - - if (DMAy_Channelx == DMA1_Channel1) - { - /* Reset interrupt pending bits for DMA1 Channel1 */ - DMA1->IFCR |= DMA1_Channel1_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel2) - { - /* Reset interrupt pending bits for DMA1 Channel2 */ - DMA1->IFCR |= DMA1_Channel2_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel3) - { - /* Reset interrupt pending bits for DMA1 Channel3 */ - DMA1->IFCR |= DMA1_Channel3_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel4) - { - /* Reset interrupt pending bits for DMA1 Channel4 */ - DMA1->IFCR |= DMA1_Channel4_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel5) - { - /* Reset interrupt pending bits for DMA1 Channel5 */ - DMA1->IFCR |= DMA1_Channel5_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel6) - { - /* Reset interrupt pending bits for DMA1 Channel6 */ - DMA1->IFCR |= DMA1_Channel6_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel7) - { - /* Reset interrupt pending bits for DMA1 Channel7 */ - DMA1->IFCR |= DMA1_Channel7_IT_Mask; - } - else if (DMAy_Channelx == DMA2_Channel1) - { - /* Reset interrupt pending bits for DMA2 Channel1 */ - DMA2->IFCR |= DMA2_Channel1_IT_Mask; - } - else if (DMAy_Channelx == DMA2_Channel2) - { - /* Reset interrupt pending bits for DMA2 Channel2 */ - DMA2->IFCR |= DMA2_Channel2_IT_Mask; - } - else if (DMAy_Channelx == DMA2_Channel3) - { - /* Reset interrupt pending bits for DMA2 Channel3 */ - DMA2->IFCR |= DMA2_Channel3_IT_Mask; - } - else if (DMAy_Channelx == DMA2_Channel4) - { - /* Reset interrupt pending bits for DMA2 Channel4 */ - DMA2->IFCR |= DMA2_Channel4_IT_Mask; - } - else - { - if (DMAy_Channelx == DMA2_Channel5) - { - /* Reset interrupt pending bits for DMA2 Channel5 */ - DMA2->IFCR |= DMA2_Channel5_IT_Mask; - } - } -} - -/** - * @brief Initializes the DMAy Channelx according to the specified - * parameters in the DMA_InitStruct. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that - * contains the configuration information for the specified DMA Channel. - * @retval None - */ -void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); - assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); - assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); - assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); - assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); - assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); - assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); - assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); - assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); - -/*--------------------------- DMAy Channelx CCR Configuration -----------------*/ - /* Get the DMAy_Channelx CCR value */ - tmpreg = DMAy_Channelx->CCR; - /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ - tmpreg &= CCR_CLEAR_Mask; - /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ - /* Set DIR bit according to DMA_DIR value */ - /* Set CIRC bit according to DMA_Mode value */ - /* Set PINC bit according to DMA_PeripheralInc value */ - /* Set MINC bit according to DMA_MemoryInc value */ - /* Set PSIZE bits according to DMA_PeripheralDataSize value */ - /* Set MSIZE bits according to DMA_MemoryDataSize value */ - /* Set PL bits according to DMA_Priority value */ - /* Set the MEM2MEM bit according to DMA_M2M value */ - tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | - DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | - DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | - DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; - - /* Write to DMAy Channelx CCR */ - DMAy_Channelx->CCR = tmpreg; - -/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ - /* Write to DMAy Channelx CNDTR */ - DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; - -/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/ - /* Write to DMAy Channelx CPAR */ - DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; - -/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/ - /* Write to DMAy Channelx CMAR */ - DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; -} - -/** - * @brief Fills each DMA_InitStruct member with its default value. - * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) -{ -/*-------------- Reset DMA init structure parameters values ------------------*/ - /* Initialize the DMA_PeripheralBaseAddr member */ - DMA_InitStruct->DMA_PeripheralBaseAddr = 0; - /* Initialize the DMA_MemoryBaseAddr member */ - DMA_InitStruct->DMA_MemoryBaseAddr = 0; - /* Initialize the DMA_DIR member */ - DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; - /* Initialize the DMA_BufferSize member */ - DMA_InitStruct->DMA_BufferSize = 0; - /* Initialize the DMA_PeripheralInc member */ - DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; - /* Initialize the DMA_MemoryInc member */ - DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; - /* Initialize the DMA_PeripheralDataSize member */ - DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - /* Initialize the DMA_MemoryDataSize member */ - DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - /* Initialize the DMA_Mode member */ - DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; - /* Initialize the DMA_Priority member */ - DMA_InitStruct->DMA_Priority = DMA_Priority_Low; - /* Initialize the DMA_M2M member */ - DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; -} - -/** - * @brief Enables or disables the specified DMAy Channelx. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @param NewState: new state of the DMAy Channelx. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DMAy Channelx */ - DMAy_Channelx->CCR |= DMA_CCR1_EN; - } - else - { - /* Disable the selected DMAy Channelx */ - DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); - } -} - -/** - * @brief Enables or disables the specified DMAy Channelx interrupts. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @param DMA_IT: specifies the DMA interrupts sources to be enabled - * or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @param NewState: new state of the specified DMA interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_DMA_CONFIG_IT(DMA_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected DMA interrupts */ - DMAy_Channelx->CCR |= DMA_IT; - } - else - { - /* Disable the selected DMA interrupts */ - DMAy_Channelx->CCR &= ~DMA_IT; - } -} - -/** - * @brief Sets the number of data units in the current DMAy Channelx transfer. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @param DataNumber: The number of data units in the current DMAy Channelx - * transfer. - * @note This function can only be used when the DMAy_Channelx is disabled. - * @retval None. - */ -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - -/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ - /* Write to DMAy Channelx CNDTR */ - DMAy_Channelx->CNDTR = DataNumber; -} - -/** - * @brief Returns the number of remaining data units in the current - * DMAy Channelx transfer. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @retval The number of remaining data units in the current DMAy Channelx - * transfer. - */ -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - /* Return the number of remaining data units for DMAy Channelx */ - return ((uint16_t)(DMAy_Channelx->CNDTR)); -} - -/** - * @brief Checks whether the specified DMAy Channelx flag is set or not. - * @param DMAy_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. - * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. - * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. - * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. - * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. - * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. - * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. - * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. - * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. - * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. - * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. - * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. - * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. - * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. - * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. - * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. - * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. - * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. - * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. - * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. - * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. - * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. - * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. - * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. - * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. - * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. - * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. - * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. - * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. - * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. - * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. - * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. - * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. - * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. - * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. - * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. - * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. - * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. - * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. - * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. - * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. - * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. - * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. - * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. - * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. - * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. - * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. - * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. - * @retval The new state of DMAy_FLAG (SET or RESET). - */ -FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_GET_FLAG(DMAy_FLAG)); - - /* Calculate the used DMAy */ - if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) - { - /* Get DMA2 ISR register value */ - tmpreg = DMA2->ISR ; - } - else - { - /* Get DMA1 ISR register value */ - tmpreg = DMA1->ISR ; - } - - /* Check the status of the specified DMAy flag */ - if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET) - { - /* DMAy_FLAG is set */ - bitstatus = SET; - } - else - { - /* DMAy_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the DMAy_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Channelx's pending flags. - * @param DMAy_FLAG: specifies the flag to clear. - * This parameter can be any combination (for the same DMA) of the following values: - * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. - * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. - * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. - * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. - * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. - * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. - * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. - * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. - * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. - * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. - * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. - * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. - * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. - * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. - * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. - * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. - * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. - * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. - * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. - * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. - * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. - * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. - * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. - * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. - * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. - * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. - * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. - * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. - * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. - * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. - * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. - * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. - * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. - * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. - * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. - * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. - * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. - * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. - * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. - * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. - * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. - * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. - * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. - * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. - * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. - * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. - * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. - * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. - * @retval None - */ -void DMA_ClearFlag(uint32_t DMAy_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG)); - - /* Calculate the used DMAy */ - if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) - { - /* Clear the selected DMAy flags */ - DMA2->IFCR = DMAy_FLAG; - } - else - { - /* Clear the selected DMAy flags */ - DMA1->IFCR = DMAy_FLAG; - } -} - -/** - * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. - * @param DMAy_IT: specifies the DMAy interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. - * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. - * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. - * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. - * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. - * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. - * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. - * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. - * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. - * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. - * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. - * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. - * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. - * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. - * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. - * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. - * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. - * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. - * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. - * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. - * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. - * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. - * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. - * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. - * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. - * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. - * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. - * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. - * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. - * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. - * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. - * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. - * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. - * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. - * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. - * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. - * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. - * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. - * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. - * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. - * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. - * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. - * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. - * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. - * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. - * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. - * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. - * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. - * @retval The new state of DMAy_IT (SET or RESET). - */ -ITStatus DMA_GetITStatus(uint32_t DMAy_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_GET_IT(DMAy_IT)); - - /* Calculate the used DMA */ - if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) - { - /* Get DMA2 ISR register value */ - tmpreg = DMA2->ISR; - } - else - { - /* Get DMA1 ISR register value */ - tmpreg = DMA1->ISR; - } - - /* Check the status of the specified DMAy interrupt */ - if ((tmpreg & DMAy_IT) != (uint32_t)RESET) - { - /* DMAy_IT is set */ - bitstatus = SET; - } - else - { - /* DMAy_IT is reset */ - bitstatus = RESET; - } - /* Return the DMA_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Channelx's interrupt pending bits. - * @param DMAy_IT: specifies the DMAy interrupt pending bit to clear. - * This parameter can be any combination (for the same DMA) of the following values: - * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. - * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. - * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. - * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. - * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. - * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. - * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. - * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. - * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. - * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. - * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. - * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. - * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. - * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. - * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. - * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. - * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. - * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. - * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. - * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. - * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. - * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. - * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. - * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. - * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. - * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. - * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. - * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. - * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. - * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. - * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. - * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. - * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. - * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. - * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. - * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. - * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. - * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. - * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. - * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. - * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. - * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. - * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. - * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. - * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. - * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. - * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. - * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. - * @retval None - */ -void DMA_ClearITPendingBit(uint32_t DMAy_IT) -{ - /* Check the parameters */ - assert_param(IS_DMA_CLEAR_IT(DMAy_IT)); - - /* Calculate the used DMAy */ - if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) - { - /* Clear the selected DMAy interrupt pending bits */ - DMA2->IFCR = DMAy_IT; - } - else - { - /* Clear the selected DMAy interrupt pending bits */ - DMA1->IFCR = DMAy_IT; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c deleted file mode 100644 index ab7346276..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c +++ /dev/null @@ -1,269 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_exti.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the EXTI firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_exti.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup EXTI - * @brief EXTI driver modules - * @{ - */ - -/** @defgroup EXTI_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Private_Defines - * @{ - */ - -#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ - -/** - * @} - */ - -/** @defgroup EXTI_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the EXTI peripheral registers to their default reset values. - * @param None - * @retval None - */ -void EXTI_DeInit(void) -{ - EXTI->IMR = 0x00000000; - EXTI->EMR = 0x00000000; - EXTI->RTSR = 0x00000000; - EXTI->FTSR = 0x00000000; - EXTI->PR = 0x000FFFFF; -} - -/** - * @brief Initializes the EXTI peripheral according to the specified - * parameters in the EXTI_InitStruct. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure - * that contains the configuration information for the EXTI peripheral. - * @retval None - */ -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); - assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); - assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); - assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); - - tmp = (uint32_t)EXTI_BASE; - - if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) - { - /* Clear EXTI line configuration */ - EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; - - tmp += EXTI_InitStruct->EXTI_Mode; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - - /* Clear Rising Falling edge configuration */ - EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; - - /* Select the trigger for the selected external interrupts */ - if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) - { - /* Rising Falling edge */ - EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; - EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; - } - else - { - tmp = (uint32_t)EXTI_BASE; - tmp += EXTI_InitStruct->EXTI_Trigger; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - } - } - else - { - tmp += EXTI_InitStruct->EXTI_Mode; - - /* Disable the selected external lines */ - *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; - } -} - -/** - * @brief Fills each EXTI_InitStruct member with its reset value. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) -{ - EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; - EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStruct->EXTI_LineCmd = DISABLE; -} - -/** - * @brief Generates a Software interrupt. - * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled. - * This parameter can be any combination of EXTI_Linex where x can be (0..19). - * @retval None - */ -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->SWIER |= EXTI_Line; -} - -/** - * @brief Checks whether the specified EXTI line flag is set or not. - * @param EXTI_Line: specifies the EXTI line flag to check. - * This parameter can be: - * @arg EXTI_Linex: External interrupt line x where x(0..19) - * @retval The new state of EXTI_Line (SET or RESET). - */ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTI's line pending flags. - * @param EXTI_Line: specifies the EXTI lines flags to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..19). - * @retval None - */ -void EXTI_ClearFlag(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @brief Checks whether the specified EXTI line is asserted or not. - * @param EXTI_Line: specifies the EXTI line to check. - * This parameter can be: - * @arg EXTI_Linex: External interrupt line x where x(0..19) - * @retval The new state of EXTI_Line (SET or RESET). - */ -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - enablestatus = EXTI->IMR & EXTI_Line; - if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTI's line pending bits. - * @param EXTI_Line: specifies the EXTI lines to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..19). - * @retval None - */ -void EXTI_ClearITPendingBit(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c deleted file mode 100644 index f6c7bf172..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c +++ /dev/null @@ -1,1684 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_flash.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the FLASH firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_flash.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup FLASH - * @brief FLASH driver modules - * @{ - */ - -/** @defgroup FLASH_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Private_Defines - * @{ - */ - -/* Flash Access Control Register bits */ -#define ACR_LATENCY_Mask ((uint32_t)0x00000038) -#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7) -#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF) - -/* Flash Access Control Register bits */ -#define ACR_PRFTBS_Mask ((uint32_t)0x00000020) - -/* Flash Control Register bits */ -#define CR_PG_Set ((uint32_t)0x00000001) -#define CR_PG_Reset ((uint32_t)0x00001FFE) -#define CR_PER_Set ((uint32_t)0x00000002) -#define CR_PER_Reset ((uint32_t)0x00001FFD) -#define CR_MER_Set ((uint32_t)0x00000004) -#define CR_MER_Reset ((uint32_t)0x00001FFB) -#define CR_OPTPG_Set ((uint32_t)0x00000010) -#define CR_OPTPG_Reset ((uint32_t)0x00001FEF) -#define CR_OPTER_Set ((uint32_t)0x00000020) -#define CR_OPTER_Reset ((uint32_t)0x00001FDF) -#define CR_STRT_Set ((uint32_t)0x00000040) -#define CR_LOCK_Set ((uint32_t)0x00000080) - -/* FLASH Mask */ -#define RDPRT_Mask ((uint32_t)0x00000002) -#define WRP0_Mask ((uint32_t)0x000000FF) -#define WRP1_Mask ((uint32_t)0x0000FF00) -#define WRP2_Mask ((uint32_t)0x00FF0000) -#define WRP3_Mask ((uint32_t)0xFF000000) -#define OB_USER_BFB2 ((uint16_t)0x0008) - -/* FLASH Keys */ -#define RDP_Key ((uint16_t)0x00A5) -#define FLASH_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) - -/* FLASH BANK address */ -#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) - -/* Delay definition */ -#define EraseTimeout ((uint32_t)0x000B0000) -#define ProgramTimeout ((uint32_t)0x00002000) -/** - * @} - */ - -/** @defgroup FLASH_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Private_Functions - * @{ - */ - -/** -@code - - This driver provides functions to configure and program the Flash memory of all STM32F10x devices, - including the latest STM32F10x_XL density devices. - - STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability: - - bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each) - - bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each) - While other STM32F10x devices features only one bank with memory up to 512 Kbytes. - - In version V3.3.0, some functions were updated and new ones were added to support - STM32F10x_XL devices. Thus some functions manages all devices, while other are - dedicated for XL devices only. - - The table below presents the list of available functions depending on the used STM32F10x devices. - - *************************************************** - * Legacy functions used for all STM32F10x devices * - *************************************************** - +----------------------------------------------------------------------------------------------------------------------------------+ - | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | - | | devices | devices | | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_SetLatency | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_HalfCycleAccessCmd | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_PrefetchBufferCmd | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_Unlock | Yes | Yes | - For STM32F10X_XL devices: unlock Bank1 and Bank2. | - | | | | - For other devices: unlock Bank1 and it is equivalent | - | | | | to FLASH_UnlockBank1 function. | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_Lock | Yes | Yes | - For STM32F10X_XL devices: lock Bank1 and Bank2. | - | | | | - For other devices: lock Bank1 and it is equivalent | - | | | | to FLASH_LockBank1 function. | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ErasePage | Yes | Yes | - For STM32F10x_XL devices: erase a page in Bank1 and Bank2 | - | | | | - For other devices: erase a page in Bank1 | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_EraseAllPages | Yes | Yes | - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 | - | | | | - For other devices: erase all pages in Bank1 | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_EraseOptionBytes | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ProgramWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ProgramHalfWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ProgramOptionByteData | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_EnableWriteProtection | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ReadOutProtection | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_UserOptionByteConfig | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_GetUserOptionByte | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_GetWriteProtectionOptionByte | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_GetReadOutProtectionStatus | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_GetPrefetchBufferStatus | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ITConfig | Yes | Yes | - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts| - | | | | - For other devices: enable Bank1's interrupts | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_GetFlagStatus | Yes | Yes | - For STM32F10x_XL devices: return Bank1 and Bank2's flag status| - | | | | - For other devices: return Bank1's flag status | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ClearFlag | Yes | Yes | - For STM32F10x_XL devices: clear Bank1 and Bank2's flag | - | | | | - For other devices: clear Bank1's flag | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_GetStatus | Yes | Yes | - Return the status of Bank1 (for all devices) | - | | | | equivalent to FLASH_GetBank1Status function | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_WaitForLastOperation | Yes | Yes | - Wait for Bank1 last operation (for all devices) | - | | | | equivalent to: FLASH_WaitForLastBank1Operation function | - +----------------------------------------------------------------------------------------------------------------------------------+ - - ************************************************************************************************************************ - * New functions used for all STM32F10x devices to manage Bank1: * - * - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 * - * - For other devices, these functions are optional (covered by functions listed above) * - ************************************************************************************************************************ - +----------------------------------------------------------------------------------------------------------------------------------+ - | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | - | | devices | devices | | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_UnlockBank1 | Yes | Yes | - Unlock Bank1 | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_LockBank1 | Yes | Yes | - Lock Bank1 | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_EraseAllBank1Pages | Yes | Yes | - Erase all pages in Bank1 | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_GetBank1Status | Yes | Yes | - Return the status of Bank1 | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_WaitForLastBank1Operation | Yes | Yes | - Wait for Bank1 last operation | - +----------------------------------------------------------------------------------------------------------------------------------+ - - ***************************************************************************** - * New Functions used only with STM32F10x_XL density devices to manage Bank2 * - ***************************************************************************** - +----------------------------------------------------------------------------------------------------------------------------------+ - | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | - | | devices | devices | | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_UnlockBank2 | Yes | No | - Unlock Bank2 | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_LockBank2 | Yes | No | - Lock Bank2 | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_EraseAllBank2Pages | Yes | No | - Erase all pages in Bank2 | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_GetBank2Status | Yes | No | - Return the status of Bank2 | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_WaitForLastBank2Operation | Yes | No | - Wait for Bank2 last operation | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_BootConfig | Yes | No | - Configure to boot from Bank1 or Bank2 | - +----------------------------------------------------------------------------------------------------------------------------------+ -@endcode -*/ - - -/** - * @brief Sets the code latency value. - * @note This function can be used for all STM32F10x devices. - * @param FLASH_Latency: specifies the FLASH Latency value. - * This parameter can be one of the following values: - * @arg FLASH_Latency_0: FLASH Zero Latency cycle - * @arg FLASH_Latency_1: FLASH One Latency cycle - * @arg FLASH_Latency_2: FLASH Two Latency cycles - * @retval None - */ -void FLASH_SetLatency(uint32_t FLASH_Latency) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_LATENCY(FLASH_Latency)); - - /* Read the ACR register */ - tmpreg = FLASH->ACR; - - /* Sets the Latency value */ - tmpreg &= ACR_LATENCY_Mask; - tmpreg |= FLASH_Latency; - - /* Write the ACR register */ - FLASH->ACR = tmpreg; -} - -/** - * @brief Enables or disables the Half cycle flash access. - * @note This function can be used for all STM32F10x devices. - * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode. - * This parameter can be one of the following values: - * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable - * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable - * @retval None - */ -void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess) -{ - /* Check the parameters */ - assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess)); - - /* Enable or disable the Half cycle access */ - FLASH->ACR &= ACR_HLFCYA_Mask; - FLASH->ACR |= FLASH_HalfCycleAccess; -} - -/** - * @brief Enables or disables the Prefetch Buffer. - * @note This function can be used for all STM32F10x devices. - * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status. - * This parameter can be one of the following values: - * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable - * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable - * @retval None - */ -void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer) -{ - /* Check the parameters */ - assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer)); - - /* Enable or disable the Prefetch Buffer */ - FLASH->ACR &= ACR_PRFTBE_Mask; - FLASH->ACR |= FLASH_PrefetchBuffer; -} - -/** - * @brief Unlocks the FLASH Program Erase Controller. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices this function unlocks Bank1 and Bank2. - * - For all other devices it unlocks Bank1 and it is equivalent - * to FLASH_UnlockBank1 function.. - * @param None - * @retval None - */ -void FLASH_Unlock(void) -{ - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - -#ifdef STM32F10X_XL - /* Authorize the FPEC of Bank2 Access */ - FLASH->KEYR2 = FLASH_KEY1; - FLASH->KEYR2 = FLASH_KEY2; -#endif /* STM32F10X_XL */ -} -/** - * @brief Unlocks the FLASH Bank1 Program Erase Controller. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices this function unlocks Bank1. - * - For all other devices it unlocks Bank1 and it is - * equivalent to FLASH_Unlock function. - * @param None - * @retval None - */ -void FLASH_UnlockBank1(void) -{ - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; -} - -#ifdef STM32F10X_XL -/** - * @brief Unlocks the FLASH Bank2 Program Erase Controller. - * @note This function can be used only for STM32F10X_XL density devices. - * @param None - * @retval None - */ -void FLASH_UnlockBank2(void) -{ - /* Authorize the FPEC of Bank2 Access */ - FLASH->KEYR2 = FLASH_KEY1; - FLASH->KEYR2 = FLASH_KEY2; - -} -#endif /* STM32F10X_XL */ - -/** - * @brief Locks the FLASH Program Erase Controller. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices this function Locks Bank1 and Bank2. - * - For all other devices it Locks Bank1 and it is equivalent - * to FLASH_LockBank1 function. - * @param None - * @retval None - */ -void FLASH_Lock(void) -{ - /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */ - FLASH->CR |= CR_LOCK_Set; - -#ifdef STM32F10X_XL - /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */ - FLASH->CR2 |= CR_LOCK_Set; -#endif /* STM32F10X_XL */ -} - -/** - * @brief Locks the FLASH Bank1 Program Erase Controller. - * @note this function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices this function Locks Bank1. - * - For all other devices it Locks Bank1 and it is equivalent - * to FLASH_Lock function. - * @param None - * @retval None - */ -void FLASH_LockBank1(void) -{ - /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */ - FLASH->CR |= CR_LOCK_Set; -} - -#ifdef STM32F10X_XL -/** - * @brief Locks the FLASH Bank2 Program Erase Controller. - * @note This function can be used only for STM32F10X_XL density devices. - * @param None - * @retval None - */ -void FLASH_LockBank2(void) -{ - /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */ - FLASH->CR2 |= CR_LOCK_Set; -} -#endif /* STM32F10X_XL */ - -/** - * @brief Erases a specified FLASH page. - * @note This function can be used for all STM32F10x devices. - * @param Page_Address: The page address to be erased. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ErasePage(uint32_t Page_Address) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Page_Address)); - -#ifdef STM32F10X_XL - if(Page_Address < FLASH_BANK1_END_ADDRESS) - { - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase the page */ - FLASH->CR|= CR_PER_Set; - FLASH->AR = Page_Address; - FLASH->CR|= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - - /* Disable the PER Bit */ - FLASH->CR &= CR_PER_Reset; - } - } - else - { - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase the page */ - FLASH->CR2|= CR_PER_Set; - FLASH->AR2 = Page_Address; - FLASH->CR2|= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(EraseTimeout); - - /* Disable the PER Bit */ - FLASH->CR2 &= CR_PER_Reset; - } - } -#else - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase the page */ - FLASH->CR|= CR_PER_Set; - FLASH->AR = Page_Address; - FLASH->CR|= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - /* Disable the PER Bit */ - FLASH->CR &= CR_PER_Reset; - } -#endif /* STM32F10X_XL */ - - /* Return the Erase Status */ - return status; -} - -/** - * @brief Erases all FLASH pages. - * @note This function can be used for all STM32F10x devices. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllPages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - -#ifdef STM32F10X_XL - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all pages */ - FLASH->CR |= CR_MER_Set; - FLASH->CR |= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - - /* Disable the MER Bit */ - FLASH->CR &= CR_MER_Reset; - } - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all pages */ - FLASH->CR2 |= CR_MER_Set; - FLASH->CR2 |= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(EraseTimeout); - - /* Disable the MER Bit */ - FLASH->CR2 &= CR_MER_Reset; - } -#else - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all pages */ - FLASH->CR |= CR_MER_Set; - FLASH->CR |= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - /* Disable the MER Bit */ - FLASH->CR &= CR_MER_Reset; - } -#endif /* STM32F10X_XL */ - - /* Return the Erase Status */ - return status; -} - -/** - * @brief Erases all Bank1 FLASH pages. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices this function erases all Bank1 pages. - * - For all other devices it erases all Bank1 pages and it is equivalent - * to FLASH_EraseAllPages function. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllBank1Pages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all pages */ - FLASH->CR |= CR_MER_Set; - FLASH->CR |= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - - /* Disable the MER Bit */ - FLASH->CR &= CR_MER_Reset; - } - /* Return the Erase Status */ - return status; -} - -#ifdef STM32F10X_XL -/** - * @brief Erases all Bank2 FLASH pages. - * @note This function can be used only for STM32F10x_XL density devices. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllBank2Pages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all pages */ - FLASH->CR2 |= CR_MER_Set; - FLASH->CR2 |= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(EraseTimeout); - - /* Disable the MER Bit */ - FLASH->CR2 &= CR_MER_Reset; - } - /* Return the Erase Status */ - return status; -} -#endif /* STM32F10X_XL */ - -/** - * @brief Erases the FLASH option bytes. - * @note This functions erases all option bytes except the Read protection (RDP). - * @note This function can be used for all STM32F10x devices. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseOptionBytes(void) -{ - uint16_t rdptmp = RDP_Key; - - FLASH_Status status = FLASH_COMPLETE; - - /* Get the actual read protection Option Byte value */ - if(FLASH_GetReadOutProtectionStatus() != RESET) - { - rdptmp = 0x00; - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* Authorize the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - - /* if the previous operation is completed, proceed to erase the option bytes */ - FLASH->CR |= CR_OPTER_Set; - FLASH->CR |= CR_STRT_Set; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= CR_OPTER_Reset; - - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - /* Restore the last read protection Option Byte value */ - OB->RDP = (uint16_t)rdptmp; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - else - { - if (status != FLASH_TIMEOUT) - { - /* Disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - } - /* Return the erase status */ - return status; -} - -/** - * @brief Programs a word at a specified address. - * @note This function can be used for all STM32F10x devices. - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - -#ifdef STM32F10X_XL - if(Address < FLASH_BANK1_END_ADDRESS - 2) - { - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(ProgramTimeout); - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new first - half word */ - FLASH->CR |= CR_PG_Set; - - *(__IO uint16_t*)Address = (uint16_t)Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new second - half word */ - tmp = Address + 2; - - *(__IO uint16_t*) tmp = Data >> 16; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - else - { - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - } - } - else if(Address == (FLASH_BANK1_END_ADDRESS - 1)) - { - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new first - half word */ - FLASH->CR |= CR_PG_Set; - - *(__IO uint16_t*)Address = (uint16_t)Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - else - { - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new second - half word */ - FLASH->CR2 |= CR_PG_Set; - tmp = Address + 2; - - *(__IO uint16_t*) tmp = Data >> 16; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR2 &= CR_PG_Reset; - } - else - { - /* Disable the PG Bit */ - FLASH->CR2 &= CR_PG_Reset; - } - } - else - { - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new first - half word */ - FLASH->CR2 |= CR_PG_Set; - - *(__IO uint16_t*)Address = (uint16_t)Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new second - half word */ - tmp = Address + 2; - - *(__IO uint16_t*) tmp = Data >> 16; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR2 &= CR_PG_Reset; - } - else - { - /* Disable the PG Bit */ - FLASH->CR2 &= CR_PG_Reset; - } - } - } -#else - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new first - half word */ - FLASH->CR |= CR_PG_Set; - - *(__IO uint16_t*)Address = (uint16_t)Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new second - half word */ - tmp = Address + 2; - - *(__IO uint16_t*) tmp = Data >> 16; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - else - { - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - } -#endif /* STM32F10X_XL */ - - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a half word at a specified address. - * @note This function can be used for all STM32F10x devices. - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - -#ifdef STM32F10X_XL - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(Address < FLASH_BANK1_END_ADDRESS) - { - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR |= CR_PG_Set; - - *(__IO uint16_t*)Address = Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - } - else - { - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR2 |= CR_PG_Set; - - *(__IO uint16_t*)Address = Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR2 &= CR_PG_Reset; - } - } -#else - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR |= CR_PG_Set; - - *(__IO uint16_t*)Address = Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } -#endif /* STM32F10X_XL */ - - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a half word at a specified Option Byte Data address. - * @note This function can be used for all STM32F10x devices. - * @param Address: specifies the address to be programmed. - * This parameter can be 0x1FFFF804 or 0x1FFFF806. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_OB_DATA_ADDRESS(Address)); - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* Authorize the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - /* Enables the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - *(__IO uint16_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - /* Return the Option Byte Data Program Status */ - return status; -} - -/** - * @brief Write protects the desired pages - * @note This function can be used for all STM32F10x devices. - * @param FLASH_Pages: specifies the address of the pages to be write protected. - * This parameter can be: - * @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31 - * @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3 - * and FLASH_WRProt_Pages124to127 - * @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and - * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255 - * @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and - * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127 - * @arg For @b STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and - * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511 - * @arg FLASH_WRProt_AllPages - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) -{ - uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; - - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages)); - - FLASH_Pages = (uint32_t)(~FLASH_Pages); - WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask); - WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8); - WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16); - WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* Authorizes the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - FLASH->CR |= CR_OPTPG_Set; - if(WRP0_Data != 0xFF) - { - OB->WRP0 = WRP0_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) - { - OB->WRP1 = WRP1_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF)) - { - OB->WRP2 = WRP2_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - - if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF)) - { - OB->WRP3 = WRP3_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - /* Return the write protection operation Status */ - return status; -} - -/** - * @brief Enables or disables the read out protection. - * @note If the user has already programmed the other option bytes before calling - * this function, he must re-program them since this function erases all option bytes. - * @note This function can be used for all STM32F10x devices. - * @param Newstate: new state of the ReadOut Protection. - * This parameter can be: ENABLE or DISABLE. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* Authorizes the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - FLASH->CR |= CR_OPTER_Set; - FLASH->CR |= CR_STRT_Set; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* if the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= CR_OPTER_Reset; - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - if(NewState != DISABLE) - { - OB->RDP = 0x00; - } - else - { - OB->RDP = RDP_Key; - } - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - else - { - if(status != FLASH_TIMEOUT) - { - /* Disable the OPTER Bit */ - FLASH->CR &= CR_OPTER_Reset; - } - } - } - /* Return the protection operation Status */ - return status; -} - -/** - * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @note This function can be used for all STM32F10x devices. - * @param OB_IWDG: Selects the IWDG mode - * This parameter can be one of the following values: - * @arg OB_IWDG_SW: Software IWDG selected - * @arg OB_IWDG_HW: Hardware IWDG selected - * @param OB_STOP: Reset event when entering STOP mode. - * This parameter can be one of the following values: - * @arg OB_STOP_NoRST: No reset generated when entering in STOP - * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param OB_STDBY: Reset event when entering Standby mode. - * This parameter can be one of the following values: - * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); - assert_param(IS_OB_STOP_SOURCE(OB_STOP)); - assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); - - /* Authorize the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - - OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - /* Return the Option Byte program Status */ - return status; -} - -#ifdef STM32F10X_XL -/** - * @brief Configures to boot from Bank1 or Bank2. - * @note This function can be used only for STM32F10x_XL density devices. - * @param FLASH_BOOT: select the FLASH Bank to boot from. - * This parameter can be one of the following values: - * @arg FLASH_BOOT_Bank1: At startup, if boot pins are set in boot from user Flash - * position and this parameter is selected the device will boot from Bank1(Default). - * @arg FLASH_BOOT_Bank2: At startup, if boot pins are set in boot from user Flash - * position and this parameter is selected the device will boot from Bank2 or Bank1, - * depending on the activation of the bank. The active banks are checked in - * the following order: Bank2, followed by Bank1. - * The active bank is recognized by the value programmed at the base address - * of the respective bank (corresponding to the initial stack pointer value - * in the interrupt vector table). - * For more information, please refer to AN2606 from www.st.com. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT) -{ - FLASH_Status status = FLASH_COMPLETE; - assert_param(IS_FLASH_BOOT(FLASH_BOOT)); - /* Authorize the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - - if(FLASH_BOOT == FLASH_BOOT_Bank1) - { - OB->USER |= OB_USER_BFB2; - } - else - { - OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2)); - } - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - /* Return the Option Byte program Status */ - return status; -} -#endif /* STM32F10X_XL */ - -/** - * @brief Returns the FLASH User Option Bytes values. - * @note This function can be used for all STM32F10x devices. - * @param None - * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) - * and RST_STDBY(Bit2). - */ -uint32_t FLASH_GetUserOptionByte(void) -{ - /* Return the User Option Byte */ - return (uint32_t)(FLASH->OBR >> 2); -} - -/** - * @brief Returns the FLASH Write Protection Option Bytes Register value. - * @note This function can be used for all STM32F10x devices. - * @param None - * @retval The FLASH Write Protection Option Bytes Register value - */ -uint32_t FLASH_GetWriteProtectionOptionByte(void) -{ - /* Return the Flash write protection Register value */ - return (uint32_t)(FLASH->WRPR); -} - -/** - * @brief Checks whether the FLASH Read Out Protection Status is set or not. - * @note This function can be used for all STM32F10x devices. - * @param None - * @retval FLASH ReadOut Protection Status(SET or RESET) - */ -FlagStatus FLASH_GetReadOutProtectionStatus(void) -{ - FlagStatus readoutstatus = RESET; - if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) - { - readoutstatus = SET; - } - else - { - readoutstatus = RESET; - } - return readoutstatus; -} - -/** - * @brief Checks whether the FLASH Prefetch Buffer status is set or not. - * @note This function can be used for all STM32F10x devices. - * @param None - * @retval FLASH Prefetch Buffer Status (SET or RESET). - */ -FlagStatus FLASH_GetPrefetchBufferStatus(void) -{ - FlagStatus bitstatus = RESET; - - if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */ - return bitstatus; -} - -/** - * @brief Enables or disables the specified FLASH interrupts. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices, enables or disables the specified FLASH interrupts - for Bank1 and Bank2. - * - For other devices it enables or disables the specified FLASH interrupts for Bank1. - * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FLASH_IT_ERROR: FLASH Error Interrupt - * @arg FLASH_IT_EOP: FLASH end of operation Interrupt - * @param NewState: new state of the specified Flash interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) -{ -#ifdef STM32F10X_XL - /* Check the parameters */ - assert_param(IS_FLASH_IT(FLASH_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if((FLASH_IT & 0x80000000) != 0x0) - { - if(NewState != DISABLE) - { - /* Enable the interrupt sources */ - FLASH->CR2 |= (FLASH_IT & 0x7FFFFFFF); - } - else - { - /* Disable the interrupt sources */ - FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF); - } - } - else - { - if(NewState != DISABLE) - { - /* Enable the interrupt sources */ - FLASH->CR |= FLASH_IT; - } - else - { - /* Disable the interrupt sources */ - FLASH->CR &= ~(uint32_t)FLASH_IT; - } - } -#else - /* Check the parameters */ - assert_param(IS_FLASH_IT(FLASH_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - /* Enable the interrupt sources */ - FLASH->CR |= FLASH_IT; - } - else - { - /* Disable the interrupt sources */ - FLASH->CR &= ~(uint32_t)FLASH_IT; - } -#endif /* STM32F10X_XL */ -} - -/** - * @brief Checks whether the specified FLASH flag is set or not. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices, this function checks whether the specified - * Bank1 or Bank2 flag is set or not. - * - For other devices, it checks whether the specified Bank1 flag is - * set or not. - * @param FLASH_FLAG: specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg FLASH_FLAG_BSY: FLASH Busy flag - * @arg FLASH_FLAG_PGERR: FLASH Program error flag - * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag - * @retval The new state of FLASH_FLAG (SET or RESET). - */ -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) -{ - FlagStatus bitstatus = RESET; - -#ifdef STM32F10X_XL - /* Check the parameters */ - assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; - if(FLASH_FLAG == FLASH_FLAG_OPTERR) - { - if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if((FLASH_FLAG & 0x80000000) != 0x0) - { - if((FLASH->SR2 & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - } -#else - /* Check the parameters */ - assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; - if(FLASH_FLAG == FLASH_FLAG_OPTERR) - { - if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } -#endif /* STM32F10X_XL */ - - /* Return the new state of FLASH_FLAG (SET or RESET) */ - return bitstatus; -} - -/** - * @brief Clears the FLASH's pending flags. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices, this function clears Bank1 or Bank2’s pending flags - * - For other devices, it clears Bank1’s pending flags. - * @param FLASH_FLAG: specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_PGERR: FLASH Program error flag - * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @retval None - */ -void FLASH_ClearFlag(uint32_t FLASH_FLAG) -{ -#ifdef STM32F10X_XL - /* Check the parameters */ - assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; - - if((FLASH_FLAG & 0x80000000) != 0x0) - { - /* Clear the flags */ - FLASH->SR2 = FLASH_FLAG; - } - else - { - /* Clear the flags */ - FLASH->SR = FLASH_FLAG; - } - -#else - /* Check the parameters */ - assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; - - /* Clear the flags */ - FLASH->SR = FLASH_FLAG; -#endif /* STM32F10X_XL */ -} - -/** - * @brief Returns the FLASH Status. - * @note This function can be used for all STM32F10x devices, it is equivalent - * to FLASH_GetBank1Status function. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE - */ -FLASH_Status FLASH_GetStatus(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->SR & FLASH_FLAG_PGERR) != 0) - { - flashstatus = FLASH_ERROR_PG; - } - else - { - if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 ) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - } - /* Return the Flash Status */ - return flashstatus; -} - -/** - * @brief Returns the FLASH Bank1 Status. - * @note This function can be used for all STM32F10x devices, it is equivalent - * to FLASH_GetStatus function. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE - */ -FLASH_Status FLASH_GetBank1Status(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->SR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->SR & FLASH_FLAG_BANK1_PGERR) != 0) - { - flashstatus = FLASH_ERROR_PG; - } - else - { - if((FLASH->SR & FLASH_FLAG_BANK1_WRPRTERR) != 0 ) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - } - /* Return the Flash Status */ - return flashstatus; -} - -#ifdef STM32F10X_XL -/** - * @brief Returns the FLASH Bank2 Status. - * @note This function can be used for STM32F10x_XL density devices. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE - */ -FLASH_Status FLASH_GetBank2Status(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0) - { - flashstatus = FLASH_ERROR_PG; - } - else - { - if((FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 ) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - } - /* Return the Flash Status */ - return flashstatus; -} -#endif /* STM32F10X_XL */ -/** - * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. - * @note This function can be used for all STM32F10x devices, - * it is equivalent to FLASH_WaitForLastBank1Operation. - * - For STM32F10X_XL devices this function waits for a Bank1 Flash operation - * to complete or a TIMEOUT to occur. - * - For all other devices it waits for a Flash operation to complete - * or a TIMEOUT to occur. - * @param Timeout: FLASH programming Timeout - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check for the Flash Status */ - status = FLASH_GetBank1Status(); - /* Wait for a Flash operation to complete or a TIMEOUT to occur */ - while((status == FLASH_BUSY) && (Timeout != 0x00)) - { - status = FLASH_GetBank1Status(); - Timeout--; - } - if(Timeout == 0x00 ) - { - status = FLASH_TIMEOUT; - } - /* Return the operation status */ - return status; -} - -/** - * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. - * @note This function can be used for all STM32F10x devices, - * it is equivalent to FLASH_WaitForLastOperation. - * @param Timeout: FLASH programming Timeout - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check for the Flash Status */ - status = FLASH_GetBank1Status(); - /* Wait for a Flash operation to complete or a TIMEOUT to occur */ - while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) - { - status = FLASH_GetBank1Status(); - Timeout--; - } - if(Timeout == 0x00 ) - { - status = FLASH_TIMEOUT; - } - /* Return the operation status */ - return status; -} - -#ifdef STM32F10X_XL -/** - * @brief Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur. - * @note This function can be used only for STM32F10x_XL density devices. - * @param Timeout: FLASH programming Timeout - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check for the Flash Status */ - status = FLASH_GetBank2Status(); - /* Wait for a Flash operation to complete or a TIMEOUT to occur */ - while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00)) - { - status = FLASH_GetBank2Status(); - Timeout--; - } - if(Timeout == 0x00 ) - { - status = FLASH_TIMEOUT; - } - /* Return the operation status */ - return status; -} -#endif /* STM32F10X_XL */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c deleted file mode 100644 index c75137cac..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c +++ /dev/null @@ -1,866 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_fsmc.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the FSMC firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_fsmc.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup FSMC - * @brief FSMC driver modules - * @{ - */ - -/** @defgroup FSMC_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - -/** @defgroup FSMC_Private_Defines - * @{ - */ - -/* --------------------- FSMC registers bit mask ---------------------------- */ - -/* FSMC BCRx Mask */ -#define BCR_MBKEN_Set ((uint32_t)0x00000001) -#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE) -#define BCR_FACCEN_Set ((uint32_t)0x00000040) - -/* FSMC PCRx Mask */ -#define PCR_PBKEN_Set ((uint32_t)0x00000004) -#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB) -#define PCR_ECCEN_Set ((uint32_t)0x00000040) -#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF) -#define PCR_MemoryType_NAND ((uint32_t)0x00000008) -/** - * @} - */ - -/** @defgroup FSMC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup FSMC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup FSMC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup FSMC_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default - * reset values. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 - * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 - * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 - * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 - * @retval None - */ -void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); - - /* FSMC_Bank1_NORSRAM1 */ - if(FSMC_Bank == FSMC_Bank1_NORSRAM1) - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; - } - /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ - else - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; - } - FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; - FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; -} - -/** - * @brief Deinitializes the FSMC NAND Banks registers to their default reset values. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @retval None - */ -void FSMC_NANDDeInit(uint32_t FSMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - /* Set the FSMC_Bank2 registers to their reset values */ - FSMC_Bank2->PCR2 = 0x00000018; - FSMC_Bank2->SR2 = 0x00000040; - FSMC_Bank2->PMEM2 = 0xFCFCFCFC; - FSMC_Bank2->PATT2 = 0xFCFCFCFC; - } - /* FSMC_Bank3_NAND */ - else - { - /* Set the FSMC_Bank3 registers to their reset values */ - FSMC_Bank3->PCR3 = 0x00000018; - FSMC_Bank3->SR3 = 0x00000040; - FSMC_Bank3->PMEM3 = 0xFCFCFCFC; - FSMC_Bank3->PATT3 = 0xFCFCFCFC; - } -} - -/** - * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values. - * @param None - * @retval None - */ -void FSMC_PCCARDDeInit(void) -{ - /* Set the FSMC_Bank4 registers to their reset values */ - FSMC_Bank4->PCR4 = 0x00000018; - FSMC_Bank4->SR4 = 0x00000000; - FSMC_Bank4->PMEM4 = 0xFCFCFCFC; - FSMC_Bank4->PATT4 = 0xFCFCFCFC; - FSMC_Bank4->PIO4 = 0xFCFCFCFC; -} - -/** - * @brief Initializes the FSMC NOR/SRAM Banks according to the specified - * parameters in the FSMC_NORSRAMInitStruct. - * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef - * structure that contains the configuration information for - * the FSMC NOR/SRAM specified Banks. - * @retval None - */ -void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) -{ - /* Check the parameters */ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); - assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); - assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); - assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); - assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); - assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait)); - assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); - assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); - assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); - assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); - assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); - assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); - assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); - assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); - assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); - assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); - assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); - - /* Bank1 NOR/SRAM control register configuration */ - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | - FSMC_NORSRAMInitStruct->FSMC_MemoryType | - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | - FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | - FSMC_NORSRAMInitStruct->FSMC_WrapMode | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | - FSMC_NORSRAMInitStruct->FSMC_WriteOperation | - FSMC_NORSRAMInitStruct->FSMC_WaitSignal | - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | - FSMC_NORSRAMInitStruct->FSMC_WriteBurst; - - if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) - { - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set; - } - - /* Bank1 NOR/SRAM timing register configuration */ - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; - - - /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ - if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) - { - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); - assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); - assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); - assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; - } - else - { - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; - } -} - -/** - * @brief Initializes the FSMC NAND Banks according to the specified - * parameters in the FSMC_NANDInitStruct. - * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef - * structure that contains the configuration information for the FSMC - * NAND specified Banks. - * @retval None - */ -void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) -{ - uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; - - /* Check the parameters */ - assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); - assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); - assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); - assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); - assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); - assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); - assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); - - /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ - tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | - PCR_MemoryType_NAND | - FSMC_NANDInitStruct->FSMC_MemoryDataWidth | - FSMC_NANDInitStruct->FSMC_ECC | - FSMC_NANDInitStruct->FSMC_ECCPageSize | - (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| - (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); - - /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ - tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ - tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) - { - /* FSMC_Bank2_NAND registers configuration */ - FSMC_Bank2->PCR2 = tmppcr; - FSMC_Bank2->PMEM2 = tmppmem; - FSMC_Bank2->PATT2 = tmppatt; - } - else - { - /* FSMC_Bank3_NAND registers configuration */ - FSMC_Bank3->PCR3 = tmppcr; - FSMC_Bank3->PMEM3 = tmppmem; - FSMC_Bank3->PATT3 = tmppatt; - } -} - -/** - * @brief Initializes the FSMC PCCARD Bank according to the specified - * parameters in the FSMC_PCCARDInitStruct. - * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef - * structure that contains the configuration information for the FSMC - * PCCARD Bank. - * @retval None - */ -void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) -{ - /* Check the parameters */ - assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); - assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); - assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); - - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); - - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); - - /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ - FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | - FSMC_MemoryDataWidth_16b | - (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | - (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); - - /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ - FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ - FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ - FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); -} - -/** - * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. - * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef - * structure which will be initialized. - * @retval None - */ -void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) -{ - /* Reset NOR/SRAM Init structure parameters values */ - FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; - FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; - FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; -} - -/** - * @brief Fills each FSMC_NANDInitStruct member with its default value. - * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef - * structure which will be initialized. - * @retval None - */ -void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) -{ - /* Reset NAND Init structure parameters values */ - FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; - FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; - FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; - FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; - FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; -} - -/** - * @brief Fills each FSMC_PCCARDInitStruct member with its default value. - * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef - * structure which will be initialized. - * @retval None - */ -void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) -{ - /* Reset PCCARD Init structure parameters values */ - FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; - FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; - FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; -} - -/** - * @brief Enables or disables the specified NOR/SRAM Memory Bank. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 - * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 - * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 - * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 - * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ - FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set; - } - else - { - /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ - FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset; - } -} - -/** - * @brief Enables or disables the specified NAND Memory Bank. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_PBKEN_Set; - } - else - { - FSMC_Bank3->PCR3 |= PCR_PBKEN_Set; - } - } - else - { - /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset; - } - else - { - FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset; - } - } -} - -/** - * @brief Enables or disables the PCCARD Memory Bank. - * @param NewState: new state of the PCCARD Memory Bank. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_PCCARDCmd(FunctionalState NewState) -{ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ - FSMC_Bank4->PCR4 |= PCR_PBKEN_Set; - } - else - { - /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ - FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset; - } -} - -/** - * @brief Enables or disables the FSMC NAND ECC feature. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @param NewState: new state of the FSMC NAND ECC feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_ECCEN_Set; - } - else - { - FSMC_Bank3->PCR3 |= PCR_ECCEN_Set; - } - } - else - { - /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset; - } - else - { - FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset; - } - } -} - -/** - * @brief Returns the error correction code register value. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @retval The Error Correction Code (ECC) value. - */ -uint32_t FSMC_GetECC(uint32_t FSMC_Bank) -{ - uint32_t eccval = 0x00000000; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - /* Get the ECCR2 register value */ - eccval = FSMC_Bank2->ECCR2; - } - else - { - /* Get the ECCR3 register value */ - eccval = FSMC_Bank3->ECCR3; - } - /* Return the error correction code value */ - return(eccval); -} - -/** - * @brief Enables or disables the specified FSMC interrupts. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @param NewState: new state of the specified FSMC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) -{ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_IT(FSMC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected FSMC_Bank2 interrupts */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 |= FSMC_IT; - } - /* Enable the selected FSMC_Bank3 interrupts */ - else if (FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 |= FSMC_IT; - } - /* Enable the selected FSMC_Bank4 interrupts */ - else - { - FSMC_Bank4->SR4 |= FSMC_IT; - } - } - else - { - /* Disable the selected FSMC_Bank2 interrupts */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - - FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; - } - /* Disable the selected FSMC_Bank3 interrupts */ - else if (FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; - } - /* Disable the selected FSMC_Bank4 interrupts */ - else - { - FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; - } - } -} - -/** - * @brief Checks whether the specified FSMC flag is set or not. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. - * @arg FSMC_FLAG_Level: Level detection Flag. - * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. - * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. - * @retval The new state of FSMC_FLAG (SET or RESET). - */ -FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpsr = 0x00000000; - - /* Check the parameters */ - assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); - assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - tmpsr = FSMC_Bank3->SR3; - } - /* FSMC_Bank4_PCCARD*/ - else - { - tmpsr = FSMC_Bank4->SR4; - } - - /* Get the flag status */ - if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the FSMC's pending flags. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. - * @arg FSMC_FLAG_Level: Level detection Flag. - * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. - * @retval None - */ -void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); - assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~FSMC_FLAG; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= ~FSMC_FLAG; - } - /* FSMC_Bank4_PCCARD*/ - else - { - FSMC_Bank4->SR4 &= ~FSMC_FLAG; - } -} - -/** - * @brief Checks whether the specified FSMC interrupt has occurred or not. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the FSMC interrupt source to check. - * This parameter can be one of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @retval The new state of FSMC_IT (SET or RESET). - */ -ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; - - /* Check the parameters */ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_GET_IT(FSMC_IT)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - tmpsr = FSMC_Bank3->SR3; - } - /* FSMC_Bank4_PCCARD*/ - else - { - tmpsr = FSMC_Bank4->SR4; - } - - itstatus = tmpsr & FSMC_IT; - - itenable = tmpsr & (FSMC_IT >> 3); - if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the FSMC's interrupt pending bits. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @retval None - */ -void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - /* Check the parameters */ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_IT(FSMC_IT)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); - } - /* FSMC_Bank4_PCCARD*/ - else - { - FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c deleted file mode 100644 index 93dbcd7ca..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c +++ /dev/null @@ -1,650 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_gpio.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the GPIO firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_gpio.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup GPIO - * @brief GPIO driver modules - * @{ - */ - -/** @defgroup GPIO_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Private_Defines - * @{ - */ - -/* ------------ RCC registers bit address in the alias region ----------------*/ -#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE) - -/* --- EVENTCR Register -----*/ - -/* Alias word address of EVOE bit */ -#define EVCR_OFFSET (AFIO_OFFSET + 0x00) -#define EVOE_BitNumber ((uint8_t)0x07) -#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4)) - - -/* --- MAPR Register ---*/ -/* Alias word address of MII_RMII_SEL bit */ -#define MAPR_OFFSET (AFIO_OFFSET + 0x04) -#define MII_RMII_SEL_BitNumber ((u8)0x17) -#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) - - -#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) -#define LSB_MASK ((uint16_t)0xFFFF) -#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) -#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) -#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) -#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) -/** - * @} - */ - -/** @defgroup GPIO_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the GPIOx peripheral registers to their default reset values. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @retval None - */ -void GPIO_DeInit(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - if (GPIOx == GPIOA) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); - } - else if (GPIOx == GPIOB) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); - } - else if (GPIOx == GPIOC) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); - } - else if (GPIOx == GPIOD) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); - } - else if (GPIOx == GPIOE) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); - } - else if (GPIOx == GPIOF) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE); - } - else - { - if (GPIOx == GPIOG) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE); - } - } -} - -/** - * @brief Deinitializes the Alternate Functions (remap, event control - * and EXTI configuration) registers to their default reset values. - * @param None - * @retval None - */ -void GPIO_AFIODeInit(void) -{ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); -} - -/** - * @brief Initializes the GPIOx peripheral according to the specified - * parameters in the GPIO_InitStruct. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that - * contains the configuration information for the specified GPIO peripheral. - * @retval None - */ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) -{ - uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; - uint32_t tmpreg = 0x00, pinmask = 0x00; - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); - assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); - -/*---------------------------- GPIO Mode Configuration -----------------------*/ - currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); - if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) - { - /* Check the parameters */ - assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); - /* Output mode */ - currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; - } -/*---------------------------- GPIO CRL Configuration ------------------------*/ - /* Configure the eight low port pins */ - if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) - { - tmpreg = GPIOx->CRL; - for (pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - /* Get the port pins position */ - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - if (currentpin == pos) - { - pos = pinpos << 2; - /* Clear the corresponding low control register bits */ - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - /* Write the mode configuration in the corresponding bits */ - tmpreg |= (currentmode << pos); - /* Reset the corresponding ODR bit */ - if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BRR = (((uint32_t)0x01) << pinpos); - } - else - { - /* Set the corresponding ODR bit */ - if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSRR = (((uint32_t)0x01) << pinpos); - } - } - } - } - GPIOx->CRL = tmpreg; - } -/*---------------------------- GPIO CRH Configuration ------------------------*/ - /* Configure the eight high port pins */ - if (GPIO_InitStruct->GPIO_Pin > 0x00FF) - { - tmpreg = GPIOx->CRH; - for (pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = (((uint32_t)0x01) << (pinpos + 0x08)); - /* Get the port pins position */ - currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); - if (currentpin == pos) - { - pos = pinpos << 2; - /* Clear the corresponding high control register bits */ - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - /* Write the mode configuration in the corresponding bits */ - tmpreg |= (currentmode << pos); - /* Reset the corresponding ODR bit */ - if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - /* Set the corresponding ODR bit */ - if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - } - } - GPIOx->CRH = tmpreg; - } -} - -/** - * @brief Fills each GPIO_InitStruct member with its default value. - * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; -} - -/** - * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The input port pin value. - */ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO input data port. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @retval GPIO input data port value. - */ -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->IDR); -} - -/** - * @brief Reads the specified output data port bit. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The output port pin value. - */ -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO output data port. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @retval GPIO output data port value. - */ -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->ODR); -} - -/** - * @brief Sets the selected data port bits. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BSRR = GPIO_Pin; -} - -/** - * @brief Clears the selected data port bits. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BRR = GPIO_Pin; -} - -/** - * @brief Sets or clears the selected data port bit. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_Pin_x where x can be (0..15). - * @param BitVal: specifies the value to be written to the selected bit. - * This parameter can be one of the BitAction enum values: - * @arg Bit_RESET: to clear the port pin - * @arg Bit_SET: to set the port pin - * @retval None - */ -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_BIT_ACTION(BitVal)); - - if (BitVal != Bit_RESET) - { - GPIOx->BSRR = GPIO_Pin; - } - else - { - GPIOx->BRR = GPIO_Pin; - } -} - -/** - * @brief Writes data to the specified GPIO data port. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param PortVal: specifies the value to be written to the port output data register. - * @retval None - */ -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->ODR = PortVal; -} - -/** - * @brief Locks GPIO Pins configuration registers. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint32_t tmp = 0x00010000; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - tmp |= GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Reset LCKK bit */ - GPIOx->LCKR = GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; -} - -/** - * @brief Selects the GPIO pin used as Event output. - * @param GPIO_PortSource: selects the GPIO port to be used as source - * for Event output. - * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). - * @param GPIO_PinSource: specifies the pin for the Event output. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * @retval None - */ -void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) -{ - uint32_t tmpreg = 0x00; - /* Check the parameters */ - assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource)); - assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); - - tmpreg = AFIO->EVCR; - /* Clear the PORT[6:4] and PIN[3:0] bits */ - tmpreg &= EVCR_PORTPINCONFIG_MASK; - tmpreg |= (uint32_t)GPIO_PortSource << 0x04; - tmpreg |= GPIO_PinSource; - AFIO->EVCR = tmpreg; -} - -/** - * @brief Enables or disables the Event Output. - * @param NewState: new state of the Event output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void GPIO_EventOutputCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState; -} - -/** - * @brief Changes the mapping of the specified pin. - * @param GPIO_Remap: selects the pin to remap. - * This parameter can be one of the following values: - * @arg GPIO_Remap_SPI1 : SPI1 Alternate Function mapping - * @arg GPIO_Remap_I2C1 : I2C1 Alternate Function mapping - * @arg GPIO_Remap_USART1 : USART1 Alternate Function mapping - * @arg GPIO_Remap_USART2 : USART2 Alternate Function mapping - * @arg GPIO_PartialRemap_USART3 : USART3 Partial Alternate Function mapping - * @arg GPIO_FullRemap_USART3 : USART3 Full Alternate Function mapping - * @arg GPIO_PartialRemap_TIM1 : TIM1 Partial Alternate Function mapping - * @arg GPIO_FullRemap_TIM1 : TIM1 Full Alternate Function mapping - * @arg GPIO_PartialRemap1_TIM2 : TIM2 Partial1 Alternate Function mapping - * @arg GPIO_PartialRemap2_TIM2 : TIM2 Partial2 Alternate Function mapping - * @arg GPIO_FullRemap_TIM2 : TIM2 Full Alternate Function mapping - * @arg GPIO_PartialRemap_TIM3 : TIM3 Partial Alternate Function mapping - * @arg GPIO_FullRemap_TIM3 : TIM3 Full Alternate Function mapping - * @arg GPIO_Remap_TIM4 : TIM4 Alternate Function mapping - * @arg GPIO_Remap1_CAN1 : CAN1 Alternate Function mapping - * @arg GPIO_Remap2_CAN1 : CAN1 Alternate Function mapping - * @arg GPIO_Remap_PD01 : PD01 Alternate Function mapping - * @arg GPIO_Remap_TIM5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibration - * @arg GPIO_Remap_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping - * @arg GPIO_Remap_ADC1_ETRGREG : ADC1 External Trigger Regular Conversion remapping - * @arg GPIO_Remap_ADC2_ETRGINJ : ADC2 External Trigger Injected Conversion remapping - * @arg GPIO_Remap_ADC2_ETRGREG : ADC2 External Trigger Regular Conversion remapping - * @arg GPIO_Remap_ETH : Ethernet remapping (only for Connectivity line devices) - * @arg GPIO_Remap_CAN2 : CAN2 remapping (only for Connectivity line devices) - * @arg GPIO_Remap_SWJ_NoJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST - * @arg GPIO_Remap_SWJ_JTAGDisable : JTAG-DP Disabled and SW-DP Enabled - * @arg GPIO_Remap_SWJ_Disable : Full SWJ Disabled (JTAG-DP + SW-DP) - * @arg GPIO_Remap_SPI3 : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) - * When the SPI3/I2S3 is remapped using this function, the SWJ is configured - * to Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST. - * @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected - * to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices) - * If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to - * Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output. - * @arg GPIO_Remap_PTP_PPS : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) - * @arg GPIO_Remap_TIM15 : TIM15 Alternate Function mapping (only for Value line devices) - * @arg GPIO_Remap_TIM16 : TIM16 Alternate Function mapping (only for Value line devices) - * @arg GPIO_Remap_TIM17 : TIM17 Alternate Function mapping (only for Value line devices) - * @arg GPIO_Remap_CEC : CEC Alternate Function mapping (only for Value line devices) - * @arg GPIO_Remap_TIM1_DMA : TIM1 DMA requests mapping (only for Value line devices) - * @arg GPIO_Remap_TIM9 : TIM9 Alternate Function mapping (only for XL-density devices) - * @arg GPIO_Remap_TIM10 : TIM10 Alternate Function mapping (only for XL-density devices) - * @arg GPIO_Remap_TIM11 : TIM11 Alternate Function mapping (only for XL-density devices) - * @arg GPIO_Remap_TIM13 : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) - * @arg GPIO_Remap_TIM14 : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) - * @arg GPIO_Remap_FSMC_NADV : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) - * @arg GPIO_Remap_TIM67_DAC_DMA : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) - * @arg GPIO_Remap_TIM12 : TIM12 Alternate Function mapping (only for High density Value line devices) - * @arg GPIO_Remap_MISC : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, - * only for High density Value line devices) - * @param NewState: new state of the port pin remapping. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) -{ - uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_REMAP(GPIO_Remap)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if((GPIO_Remap & 0x80000000) == 0x80000000) - { - tmpreg = AFIO->MAPR2; - } - else - { - tmpreg = AFIO->MAPR; - } - - tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; - tmp = GPIO_Remap & LSB_MASK; - - if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) - { - tmpreg &= DBGAFR_SWJCFG_MASK; - AFIO->MAPR &= DBGAFR_SWJCFG_MASK; - } - else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) - { - tmp1 = ((uint32_t)0x03) << tmpmask; - tmpreg &= ~tmp1; - tmpreg |= ~DBGAFR_SWJCFG_MASK; - } - else - { - tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10)); - tmpreg |= ~DBGAFR_SWJCFG_MASK; - } - - if (NewState != DISABLE) - { - tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10)); - } - - if((GPIO_Remap & 0x80000000) == 0x80000000) - { - AFIO->MAPR2 = tmpreg; - } - else - { - AFIO->MAPR = tmpreg; - } -} - -/** - * @brief Selects the GPIO pin used as EXTI Line. - * @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines. - * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). - * @param GPIO_PinSource: specifies the EXTI line to be configured. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * @retval None - */ -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) -{ - uint32_t tmp = 0x00; - /* Check the parameters */ - assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource)); - assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); - - tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); - AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; - AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); -} - -/** - * @brief Selects the Ethernet media interface. - * @note This function applies only to STM32 Connectivity line devices. - * @param GPIO_ETH_MediaInterface: specifies the Media Interface mode. - * This parameter can be one of the following values: - * @arg GPIO_ETH_MediaInterface_MII: MII mode - * @arg GPIO_ETH_MediaInterface_RMII: RMII mode - * @retval None - */ -void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) -{ - assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); - - /* Configure MII_RMII selection bit */ - *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c deleted file mode 100644 index 889672683..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c +++ /dev/null @@ -1,1331 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_i2c.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the I2C firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_i2c.h" -#include "stm32f10x_rcc.h" - - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup I2C - * @brief I2C driver modules - * @{ - */ - -/** @defgroup I2C_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Private_Defines - * @{ - */ - -/* I2C SPE mask */ -#define CR1_PE_Set ((uint16_t)0x0001) -#define CR1_PE_Reset ((uint16_t)0xFFFE) - -/* I2C START mask */ -#define CR1_START_Set ((uint16_t)0x0100) -#define CR1_START_Reset ((uint16_t)0xFEFF) - -/* I2C STOP mask */ -#define CR1_STOP_Set ((uint16_t)0x0200) -#define CR1_STOP_Reset ((uint16_t)0xFDFF) - -/* I2C ACK mask */ -#define CR1_ACK_Set ((uint16_t)0x0400) -#define CR1_ACK_Reset ((uint16_t)0xFBFF) - -/* I2C ENGC mask */ -#define CR1_ENGC_Set ((uint16_t)0x0040) -#define CR1_ENGC_Reset ((uint16_t)0xFFBF) - -/* I2C SWRST mask */ -#define CR1_SWRST_Set ((uint16_t)0x8000) -#define CR1_SWRST_Reset ((uint16_t)0x7FFF) - -/* I2C PEC mask */ -#define CR1_PEC_Set ((uint16_t)0x1000) -#define CR1_PEC_Reset ((uint16_t)0xEFFF) - -/* I2C ENPEC mask */ -#define CR1_ENPEC_Set ((uint16_t)0x0020) -#define CR1_ENPEC_Reset ((uint16_t)0xFFDF) - -/* I2C ENARP mask */ -#define CR1_ENARP_Set ((uint16_t)0x0010) -#define CR1_ENARP_Reset ((uint16_t)0xFFEF) - -/* I2C NOSTRETCH mask */ -#define CR1_NOSTRETCH_Set ((uint16_t)0x0080) -#define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) - -/* I2C registers Masks */ -#define CR1_CLEAR_Mask ((uint16_t)0xFBF5) - -/* I2C DMAEN mask */ -#define CR2_DMAEN_Set ((uint16_t)0x0800) -#define CR2_DMAEN_Reset ((uint16_t)0xF7FF) - -/* I2C LAST mask */ -#define CR2_LAST_Set ((uint16_t)0x1000) -#define CR2_LAST_Reset ((uint16_t)0xEFFF) - -/* I2C FREQ mask */ -#define CR2_FREQ_Reset ((uint16_t)0xFFC0) - -/* I2C ADD0 mask */ -#define OAR1_ADD0_Set ((uint16_t)0x0001) -#define OAR1_ADD0_Reset ((uint16_t)0xFFFE) - -/* I2C ENDUAL mask */ -#define OAR2_ENDUAL_Set ((uint16_t)0x0001) -#define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE) - -/* I2C ADD2 mask */ -#define OAR2_ADD2_Reset ((uint16_t)0xFF01) - -/* I2C F/S mask */ -#define CCR_FS_Set ((uint16_t)0x8000) - -/* I2C CCR mask */ -#define CCR_CCR_Set ((uint16_t)0x0FFF) - -/* I2C FLAG mask */ -#define FLAG_Mask ((uint32_t)0x00FFFFFF) - -/* I2C Interrupt Enable mask */ -#define ITEN_Mask ((uint32_t)0x07000000) - -/** - * @} - */ - -/** @defgroup I2C_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the I2Cx peripheral registers to their default reset values. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval None - */ -void I2C_DeInit(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - if (I2Cx == I2C1) - { - /* Enable I2C1 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); - /* Release I2C1 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); - } - else - { - /* Enable I2C2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); - /* Release I2C2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); - } -} - -/** - * @brief Initializes the I2Cx peripheral according to the specified - * parameters in the I2C_InitStruct. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that - * contains the configuration information for the specified I2C peripheral. - * @retval None - */ -void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) -{ - uint16_t tmpreg = 0, freqrange = 0; - uint16_t result = 0x04; - uint32_t pclk1 = 8000000; - RCC_ClocksTypeDef rcc_clocks; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed)); - assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); - assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); - assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); - assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); - assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); - -/*---------------------------- I2Cx CR2 Configuration ------------------------*/ - /* Get the I2Cx CR2 value */ - tmpreg = I2Cx->CR2; - /* Clear frequency FREQ[5:0] bits */ - tmpreg &= CR2_FREQ_Reset; - /* Get pclk1 frequency value */ - RCC_GetClocksFreq(&rcc_clocks); - pclk1 = rcc_clocks.PCLK1_Frequency; - /* Set frequency bits depending on pclk1 value */ - freqrange = (uint16_t)(pclk1 / 1000000); - tmpreg |= freqrange; - /* Write to I2Cx CR2 */ - I2Cx->CR2 = tmpreg; - -/*---------------------------- I2Cx CCR Configuration ------------------------*/ - /* Disable the selected I2C peripheral to configure TRISE */ - I2Cx->CR1 &= CR1_PE_Reset; - /* Reset tmpreg value */ - /* Clear F/S, DUTY and CCR[11:0] bits */ - tmpreg = 0; - - /* Configure speed in standard mode */ - if (I2C_InitStruct->I2C_ClockSpeed <= 100000) - { - /* Standard mode speed calculate */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); - /* Test if CCR value is under 0x4*/ - if (result < 0x04) - { - /* Set minimum allowed value */ - result = 0x04; - } - /* Set speed value for standard mode */ - tmpreg |= result; - /* Set Maximum Rise Time for standard mode */ - I2Cx->TRISE = freqrange + 1; - } - /* Configure speed in fast mode */ - else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ - { - if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) - { - /* Fast mode speed calculate: Tlow/Thigh = 2 */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); - } - else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ - { - /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); - /* Set DUTY bit */ - result |= I2C_DutyCycle_16_9; - } - - /* Test if CCR value is under 0x1*/ - if ((result & CCR_CCR_Set) == 0) - { - /* Set minimum allowed value */ - result |= (uint16_t)0x0001; - } - /* Set speed value and set F/S bit for fast mode */ - tmpreg |= (uint16_t)(result | CCR_FS_Set); - /* Set Maximum Rise Time for fast mode */ - I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); - } - - /* Write to I2Cx CCR */ - I2Cx->CCR = tmpreg; - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= CR1_PE_Set; - -/*---------------------------- I2Cx CR1 Configuration ------------------------*/ - /* Get the I2Cx CR1 value */ - tmpreg = I2Cx->CR1; - /* Clear ACK, SMBTYPE and SMBUS bits */ - tmpreg &= CR1_CLEAR_Mask; - /* Configure I2Cx: mode and acknowledgement */ - /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ - /* Set ACK bit according to I2C_Ack value */ - tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); - /* Write to I2Cx CR1 */ - I2Cx->CR1 = tmpreg; - -/*---------------------------- I2Cx OAR1 Configuration -----------------------*/ - /* Set I2Cx Own Address1 and acknowledged address */ - I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); -} - -/** - * @brief Fills each I2C_InitStruct member with its default value. - * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) -{ -/*---------------- Reset I2C init structure parameters values ----------------*/ - /* initialize the I2C_ClockSpeed member */ - I2C_InitStruct->I2C_ClockSpeed = 5000; - /* Initialize the I2C_Mode member */ - I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; - /* Initialize the I2C_DutyCycle member */ - I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; - /* Initialize the I2C_OwnAddress1 member */ - I2C_InitStruct->I2C_OwnAddress1 = 0; - /* Initialize the I2C_Ack member */ - I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; - /* Initialize the I2C_AcknowledgedAddress member */ - I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; -} - -/** - * @brief Enables or disables the specified I2C peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= CR1_PE_Set; - } - else - { - /* Disable the selected I2C peripheral */ - I2Cx->CR1 &= CR1_PE_Reset; - } -} - -/** - * @brief Enables or disables the specified I2C DMA requests. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C DMA requests */ - I2Cx->CR2 |= CR2_DMAEN_Set; - } - else - { - /* Disable the selected I2C DMA requests */ - I2Cx->CR2 &= CR2_DMAEN_Reset; - } -} - -/** - * @brief Specifies if the next DMA transfer will be the last one. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C DMA last transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Next DMA transfer is the last transfer */ - I2Cx->CR2 |= CR2_LAST_Set; - } - else - { - /* Next DMA transfer is not the last transfer */ - I2Cx->CR2 &= CR2_LAST_Reset; - } -} - -/** - * @brief Generates I2Cx communication START condition. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C START condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Generate a START condition */ - I2Cx->CR1 |= CR1_START_Set; - } - else - { - /* Disable the START condition generation */ - I2Cx->CR1 &= CR1_START_Reset; - } -} - -/** - * @brief Generates I2Cx communication STOP condition. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C STOP condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Generate a STOP condition */ - I2Cx->CR1 |= CR1_STOP_Set; - } - else - { - /* Disable the STOP condition generation */ - I2Cx->CR1 &= CR1_STOP_Reset; - } -} - -/** - * @brief Enables or disables the specified I2C acknowledge feature. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C Acknowledgement. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the acknowledgement */ - I2Cx->CR1 |= CR1_ACK_Set; - } - else - { - /* Disable the acknowledgement */ - I2Cx->CR1 &= CR1_ACK_Reset; - } -} - -/** - * @brief Configures the specified I2C own address2. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Address: specifies the 7bit I2C own address2. - * @retval None. - */ -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) -{ - uint16_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Get the old register value */ - tmpreg = I2Cx->OAR2; - - /* Reset I2Cx Own address2 bit [7:1] */ - tmpreg &= OAR2_ADD2_Reset; - - /* Set I2Cx Own address2 */ - tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); - - /* Store the new register value */ - I2Cx->OAR2 = tmpreg; -} - -/** - * @brief Enables or disables the specified I2C dual addressing mode. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C dual addressing mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable dual addressing mode */ - I2Cx->OAR2 |= OAR2_ENDUAL_Set; - } - else - { - /* Disable dual addressing mode */ - I2Cx->OAR2 &= OAR2_ENDUAL_Reset; - } -} - -/** - * @brief Enables or disables the specified I2C general call feature. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C General call. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable generall call */ - I2Cx->CR1 |= CR1_ENGC_Set; - } - else - { - /* Disable generall call */ - I2Cx->CR1 &= CR1_ENGC_Reset; - } -} - -/** - * @brief Enables or disables the specified I2C interrupts. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg I2C_IT_BUF: Buffer interrupt mask - * @arg I2C_IT_EVT: Event interrupt mask - * @arg I2C_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified I2C interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_I2C_CONFIG_IT(I2C_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected I2C interrupts */ - I2Cx->CR2 |= I2C_IT; - } - else - { - /* Disable the selected I2C interrupts */ - I2Cx->CR2 &= (uint16_t)~I2C_IT; - } -} - -/** - * @brief Sends a data byte through the I2Cx peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Data: Byte to be transmitted.. - * @retval None - */ -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Write in the DR register the data to be sent */ - I2Cx->DR = Data; -} - -/** - * @brief Returns the most recent received data by the I2Cx peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval The value of the received data. - */ -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Return the data in the DR register */ - return (uint8_t)I2Cx->DR; -} - -/** - * @brief Transmits the address byte to select the slave device. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Address: specifies the slave address which will be transmitted - * @param I2C_Direction: specifies whether the I2C device will be a - * Transmitter or a Receiver. This parameter can be one of the following values - * @arg I2C_Direction_Transmitter: Transmitter mode - * @arg I2C_Direction_Receiver: Receiver mode - * @retval None. - */ -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DIRECTION(I2C_Direction)); - /* Test on the direction to set/reset the read/write bit */ - if (I2C_Direction != I2C_Direction_Transmitter) - { - /* Set the address bit0 for read */ - Address |= OAR1_ADD0_Set; - } - else - { - /* Reset the address bit0 for write */ - Address &= OAR1_ADD0_Reset; - } - /* Send the address */ - I2Cx->DR = Address; -} - -/** - * @brief Reads the specified I2C register and returns its value. - * @param I2C_Register: specifies the register to read. - * This parameter can be one of the following values: - * @arg I2C_Register_CR1: CR1 register. - * @arg I2C_Register_CR2: CR2 register. - * @arg I2C_Register_OAR1: OAR1 register. - * @arg I2C_Register_OAR2: OAR2 register. - * @arg I2C_Register_DR: DR register. - * @arg I2C_Register_SR1: SR1 register. - * @arg I2C_Register_SR2: SR2 register. - * @arg I2C_Register_CCR: CCR register. - * @arg I2C_Register_TRISE: TRISE register. - * @retval The value of the read register. - */ -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_REGISTER(I2C_Register)); - - tmp = (uint32_t) I2Cx; - tmp += I2C_Register; - - /* Return the selected register value */ - return (*(__IO uint16_t *) tmp); -} - -/** - * @brief Enables or disables the specified I2C software reset. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C software reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Peripheral under reset */ - I2Cx->CR1 |= CR1_SWRST_Set; - } - else - { - /* Peripheral not under reset */ - I2Cx->CR1 &= CR1_SWRST_Reset; - } -} - -/** - * @brief Selects the specified I2C NACK position in master receiver mode. - * This function is useful in I2C Master Receiver mode when the number - * of data to be received is equal to 2. In this case, this function - * should be called (with parameter I2C_NACKPosition_Next) before data - * reception starts,as described in the 2-byte reception procedure - * recommended in Reference Manual in Section: Master receiver. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_NACKPosition: specifies the NACK position. - * This parameter can be one of the following values: - * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last - * received byte. - * @arg I2C_NACKPosition_Current: indicates that current byte is the last - * received byte. - * - * @note This function configures the same bit (POS) as I2C_PECPositionConfig() - * but is intended to be used in I2C mode while I2C_PECPositionConfig() - * is intended to used in SMBUS mode. - * - * @retval None - */ -void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition)); - - /* Check the input parameter */ - if (I2C_NACKPosition == I2C_NACKPosition_Next) - { - /* Next byte in shift register is the last received byte */ - I2Cx->CR1 |= I2C_NACKPosition_Next; - } - else - { - /* Current byte in shift register is the last received byte */ - I2Cx->CR1 &= I2C_NACKPosition_Current; - } -} - -/** - * @brief Drives the SMBusAlert pin high or low for the specified I2C. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_SMBusAlert: specifies SMBAlert pin level. - * This parameter can be one of the following values: - * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low - * @arg I2C_SMBusAlert_High: SMBAlert pin driven high - * @retval None - */ -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); - if (I2C_SMBusAlert == I2C_SMBusAlert_Low) - { - /* Drive the SMBusAlert pin Low */ - I2Cx->CR1 |= I2C_SMBusAlert_Low; - } - else - { - /* Drive the SMBusAlert pin High */ - I2Cx->CR1 &= I2C_SMBusAlert_High; - } -} - -/** - * @brief Enables or disables the specified I2C PEC transfer. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C PEC transmission. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C PEC transmission */ - I2Cx->CR1 |= CR1_PEC_Set; - } - else - { - /* Disable the selected I2C PEC transmission */ - I2Cx->CR1 &= CR1_PEC_Reset; - } -} - -/** - * @brief Selects the specified I2C PEC position. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_PECPosition: specifies the PEC position. - * This parameter can be one of the following values: - * @arg I2C_PECPosition_Next: indicates that the next byte is PEC - * @arg I2C_PECPosition_Current: indicates that current byte is PEC - * - * @note This function configures the same bit (POS) as I2C_NACKPositionConfig() - * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() - * is intended to used in I2C mode. - * - * @retval None - */ -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); - if (I2C_PECPosition == I2C_PECPosition_Next) - { - /* Next byte in shift register is PEC */ - I2Cx->CR1 |= I2C_PECPosition_Next; - } - else - { - /* Current byte in shift register is PEC */ - I2Cx->CR1 &= I2C_PECPosition_Current; - } -} - -/** - * @brief Enables or disables the PEC value calculation of the transferred bytes. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx PEC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C PEC calculation */ - I2Cx->CR1 |= CR1_ENPEC_Set; - } - else - { - /* Disable the selected I2C PEC calculation */ - I2Cx->CR1 &= CR1_ENPEC_Reset; - } -} - -/** - * @brief Returns the PEC value for the specified I2C. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval The PEC value. - */ -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Return the selected I2C PEC value */ - return ((I2Cx->SR2) >> 8); -} - -/** - * @brief Enables or disables the specified I2C ARP. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx ARP. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C ARP */ - I2Cx->CR1 |= CR1_ENARP_Set; - } - else - { - /* Disable the selected I2C ARP */ - I2Cx->CR1 &= CR1_ENARP_Reset; - } -} - -/** - * @brief Enables or disables the specified I2C Clock stretching. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx Clock stretching. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState == DISABLE) - { - /* Enable the selected I2C Clock stretching */ - I2Cx->CR1 |= CR1_NOSTRETCH_Set; - } - else - { - /* Disable the selected I2C Clock stretching */ - I2Cx->CR1 &= CR1_NOSTRETCH_Reset; - } -} - -/** - * @brief Selects the specified I2C fast mode duty cycle. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_DutyCycle: specifies the fast mode duty cycle. - * This parameter can be one of the following values: - * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 - * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 - * @retval None - */ -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); - if (I2C_DutyCycle != I2C_DutyCycle_16_9) - { - /* I2C fast mode Tlow/Thigh=2 */ - I2Cx->CCR &= I2C_DutyCycle_2; - } - else - { - /* I2C fast mode Tlow/Thigh=16/9 */ - I2Cx->CCR |= I2C_DutyCycle_16_9; - } -} - - - -/** - * @brief - **************************************************************************************** - * - * I2C State Monitoring Functions - * - **************************************************************************************** - * This I2C driver provides three different ways for I2C state monitoring - * depending on the application requirements and constraints: - * - * - * 1) Basic state monitoring: - * Using I2C_CheckEvent() function: - * It compares the status registers (SR1 and SR2) content to a given event - * (can be the combination of one or more flags). - * It returns SUCCESS if the current status includes the given flags - * and returns ERROR if one or more flags are missing in the current status. - * - When to use: - * - This function is suitable for most applications as well as for startup - * activity since the events are fully described in the product reference manual - * (RM0008). - * - It is also suitable for users who need to define their own events. - * - Limitations: - * - If an error occurs (ie. error flags are set besides to the monitored flags), - * the I2C_CheckEvent() function may return SUCCESS despite the communication - * hold or corrupted real state. - * In this case, it is advised to use error interrupts to monitor the error - * events and handle them in the interrupt IRQ handler. - * - * @note - * For error management, it is advised to use the following functions: - * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. - * Where x is the peripheral instance (I2C1, I2C2 ...) - * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() - * in order to determine which error occured. - * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() - * and/or I2C_GenerateStop() in order to clear the error flag and source, - * and return to correct communication status. - * - * - * 2) Advanced state monitoring: - * Using the function I2C_GetLastEvent() which returns the image of both status - * registers in a single word (uint32_t) (Status Register 2 value is shifted left - * by 16 bits and concatenated to Status Register 1). - * - When to use: - * - This function is suitable for the same applications above but it allows to - * overcome the mentioned limitation of I2C_GetFlagStatus() function. - * The returned value could be compared to events already defined in the - * library (stm32f10x_i2c.h) or to custom values defined by user. - * - This function is suitable when multiple flags are monitored at the same time. - * - At the opposite of I2C_CheckEvent() function, this function allows user to - * choose when an event is accepted (when all events flags are set and no - * other flags are set or just when the needed flags are set like - * I2C_CheckEvent() function). - * - Limitations: - * - User may need to define his own events. - * - Same remark concerning the error management is applicable for this - * function if user decides to check only regular communication flags (and - * ignores error flags). - * - * - * 3) Flag-based state monitoring: - * Using the function I2C_GetFlagStatus() which simply returns the status of - * one single flag (ie. I2C_FLAG_RXNE ...). - * - When to use: - * - This function could be used for specific applications or in debug phase. - * - It is suitable when only one flag checking is needed (most I2C events - * are monitored through multiple flags). - * - Limitations: - * - When calling this function, the Status register is accessed. Some flags are - * cleared when the status register is accessed. So checking the status - * of one Flag, may clear other ones. - * - Function may need to be called twice or more in order to monitor one - * single event. - * - * For detailed description of Events, please refer to section I2C_Events in - * stm32f10x_i2c.h file. - * - */ - -/** - * - * 1) Basic state monitoring - ******************************************************************************* - */ - -/** - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_EVENT: specifies the event to be checked. - * This parameter can be one of the following values: - * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2 - * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2 - * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2 - * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3 - * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3 - * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3 - * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2 - * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4 - * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5 - * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6 - * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6 - * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7 - * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8 - * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2 - * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9 - * - * @note: For detailed description of Events, please refer to section - * I2C_Events in stm32f10x_i2c.h file. - * - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Last event is equal to the I2C_EVENT - * - ERROR: Last event is different from the I2C_EVENT - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_EVENT(I2C_EVENT)); - - /* Read the I2Cx status register */ - flag1 = I2Cx->SR1; - flag2 = I2Cx->SR2; - flag2 = flag2 << 16; - - /* Get the last event value from I2C status register */ - lastevent = (flag1 | flag2) & FLAG_Mask; - - /* Check whether the last event contains the I2C_EVENT */ - if ((lastevent & I2C_EVENT) == I2C_EVENT) - { - /* SUCCESS: last event is equal to I2C_EVENT */ - status = SUCCESS; - } - else - { - /* ERROR: last event is different from I2C_EVENT */ - status = ERROR; - } - /* Return status */ - return status; -} - -/** - * - * 2) Advanced state monitoring - ******************************************************************************* - */ - -/** - * @brief Returns the last I2Cx Event. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * - * @note: For detailed description of Events, please refer to section - * I2C_Events in stm32f10x_i2c.h file. - * - * @retval The last event - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Read the I2Cx status register */ - flag1 = I2Cx->SR1; - flag2 = I2Cx->SR2; - flag2 = flag2 << 16; - - /* Get the last event value from I2C status register */ - lastevent = (flag1 | flag2) & FLAG_Mask; - - /* Return status */ - return lastevent; -} - -/** - * - * 3) Flag-based state monitoring - ******************************************************************************* - */ - -/** - * @brief Checks whether the specified I2C flag is set or not. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg I2C_FLAG_DUALF: Dual flag (Slave mode) - * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode) - * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) - * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) - * @arg I2C_FLAG_TRA: Transmitter/Receiver flag - * @arg I2C_FLAG_BUSY: Bus busy flag - * @arg I2C_FLAG_MSL: Master/Slave flag - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter) - * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag - * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode) - * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) - * @arg I2C_FLAG_BTF: Byte transfer finished flag - * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL" - * Address matched flag (Slave mode)"ENDA" - * @arg I2C_FLAG_SB: Start bit flag (Master mode) - * @retval The new state of I2C_FLAG (SET or RESET). - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - FlagStatus bitstatus = RESET; - __IO uint32_t i2creg = 0, i2cxbase = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); - - /* Get the I2Cx peripheral base address */ - i2cxbase = (uint32_t)I2Cx; - - /* Read flag register index */ - i2creg = I2C_FLAG >> 28; - - /* Get bit[23:0] of the flag */ - I2C_FLAG &= FLAG_Mask; - - if(i2creg != 0) - { - /* Get the I2Cx SR1 register address */ - i2cxbase += 0x14; - } - else - { - /* Flag in I2Cx SR2 Register */ - I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); - /* Get the I2Cx SR2 register address */ - i2cxbase += 0x18; - } - - if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) - { - /* I2C_FLAG is set */ - bitstatus = SET; - } - else - { - /* I2C_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the I2C_FLAG status */ - return bitstatus; -} - - - -/** - * @brief Clears the I2Cx's pending flags. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * - * @note - * - STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation - * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * - ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the - * second byte of the address in DR register. - * - BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a - * read/write to I2C_DR register (I2C_SendData()). - * - ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to - * I2C_SR2 register ((void)(I2Cx->SR2)). - * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 - * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR - * register (I2C_SendData()). - * @retval None - */ -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - uint32_t flagpos = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); - /* Get the I2C flag position */ - flagpos = I2C_FLAG & FLAG_Mask; - /* Clear the selected I2C flag */ - I2Cx->SR1 = (uint16_t)~flagpos; -} - -/** - * @brief Checks whether the specified I2C interrupt has occurred or not. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt source to check. - * This parameter can be one of the following values: - * @arg I2C_IT_SMBALERT: SMBus Alert flag - * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_IT_PECERR: PEC error in reception flag - * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_IT_AF: Acknowledge failure flag - * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_IT_BERR: Bus error flag - * @arg I2C_IT_TXE: Data register empty flag (Transmitter) - * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag - * @arg I2C_IT_STOPF: Stop detection flag (Slave mode) - * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode) - * @arg I2C_IT_BTF: Byte transfer finished flag - * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL" - * Address matched flag (Slave mode)"ENDAD" - * @arg I2C_IT_SB: Start bit flag (Master mode) - * @retval The new state of I2C_IT (SET or RESET). - */ -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_IT(I2C_IT)); - - /* Check if the interrupt source is enabled or not */ - enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ; - - /* Get bit[23:0] of the flag */ - I2C_IT &= FLAG_Mask; - - /* Check the status of the specified I2C flag */ - if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) - { - /* I2C_IT is set */ - bitstatus = SET; - } - else - { - /* I2C_IT is reset */ - bitstatus = RESET; - } - /* Return the I2C_IT status */ - return bitstatus; -} - -/** - * @brief Clears the I2Cx’s interrupt pending bits. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg I2C_IT_SMBALERT: SMBus Alert interrupt - * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt - * @arg I2C_IT_PECERR: PEC error in reception interrupt - * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode) - * @arg I2C_IT_AF: Acknowledge failure interrupt - * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode) - * @arg I2C_IT_BERR: Bus error interrupt - * - * @note - * - STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * - ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second - * byte of the address in I2C_DR register. - * - BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a - * read/write to I2C_DR register (I2C_SendData()). - * - ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to - * I2C_SR2 register ((void)(I2Cx->SR2)). - * - SB (Start Bit) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_DR register (I2C_SendData()). - * @retval None - */ -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - uint32_t flagpos = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_IT(I2C_IT)); - /* Get the I2C flag position */ - flagpos = I2C_IT & FLAG_Mask; - /* Clear the selected I2C flag */ - I2Cx->SR1 = (uint16_t)~flagpos; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c deleted file mode 100644 index 9d3b0e855..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c +++ /dev/null @@ -1,190 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_iwdg.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the IWDG firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_iwdg.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup IWDG - * @brief IWDG driver modules - * @{ - */ - -/** @defgroup IWDG_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Private_Defines - * @{ - */ - -/* ---------------------- IWDG registers bit mask ----------------------------*/ - -/* KR register bit mask */ -#define KR_KEY_Reload ((uint16_t)0xAAAA) -#define KR_KEY_Enable ((uint16_t)0xCCCC) - -/** - * @} - */ - -/** @defgroup IWDG_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Private_Functions - * @{ - */ - -/** - * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. - * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. - * This parameter can be one of the following values: - * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers - * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers - * @retval None - */ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) -{ - /* Check the parameters */ - assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); - IWDG->KR = IWDG_WriteAccess; -} - -/** - * @brief Sets IWDG Prescaler value. - * @param IWDG_Prescaler: specifies the IWDG Prescaler value. - * This parameter can be one of the following values: - * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 - * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 - * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 - * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 - * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 - * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 - * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 - * @retval None - */ -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); - IWDG->PR = IWDG_Prescaler; -} - -/** - * @brief Sets IWDG Reload value. - * @param Reload: specifies the IWDG Reload value. - * This parameter must be a number between 0 and 0x0FFF. - * @retval None - */ -void IWDG_SetReload(uint16_t Reload) -{ - /* Check the parameters */ - assert_param(IS_IWDG_RELOAD(Reload)); - IWDG->RLR = Reload; -} - -/** - * @brief Reloads IWDG counter with value defined in the reload register - * (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_ReloadCounter(void) -{ - IWDG->KR = KR_KEY_Reload; -} - -/** - * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_Enable(void) -{ - IWDG->KR = KR_KEY_Enable; -} - -/** - * @brief Checks whether the specified IWDG flag is set or not. - * @param IWDG_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg IWDG_FLAG_PVU: Prescaler Value Update on going - * @arg IWDG_FLAG_RVU: Reload Value Update on going - * @retval The new state of IWDG_FLAG (SET or RESET). - */ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_IWDG_FLAG(IWDG_FLAG)); - if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c deleted file mode 100644 index 147bf0f8d..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c +++ /dev/null @@ -1,307 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_pwr.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the PWR firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_pwr.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup PWR - * @brief PWR driver modules - * @{ - */ - -/** @defgroup PWR_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Private_Defines - * @{ - */ - -/* --------- PWR registers bit address in the alias region ---------- */ -#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) - -/* --- CR Register ---*/ - -/* Alias word address of DBP bit */ -#define CR_OFFSET (PWR_OFFSET + 0x00) -#define DBP_BitNumber 0x08 -#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) - -/* Alias word address of PVDE bit */ -#define PVDE_BitNumber 0x04 -#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of EWUP bit */ -#define CSR_OFFSET (PWR_OFFSET + 0x04) -#define EWUP_BitNumber 0x08 -#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) - -/* ------------------ PWR registers bit mask ------------------------ */ - -/* CR register bit mask */ -#define CR_DS_MASK ((uint32_t)0xFFFFFFFC) -#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) - - -/** - * @} - */ - -/** @defgroup PWR_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the PWR peripheral registers to their default reset values. - * @param None - * @retval None - */ -void PWR_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); -} - -/** - * @brief Enables or disables access to the RTC and backup registers. - * @param NewState: new state of the access to the RTC and backup registers. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_BackupAccessCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Power Voltage Detector(PVD). - * @param NewState: new state of the PVD. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_PVDCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param PWR_PVDLevel: specifies the PVD detection level - * This parameter can be one of the following values: - * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V - * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V - * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V - * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V - * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V - * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V - * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V - * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V - * @retval None - */ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); - tmpreg = PWR->CR; - /* Clear PLS[7:5] bits */ - tmpreg &= CR_PLS_MASK; - /* Set PLS[7:5] bits according to PWR_PVDLevel value */ - tmpreg |= PWR_PVDLevel; - /* Store the new value */ - PWR->CR = tmpreg; -} - -/** - * @brief Enables or disables the WakeUp Pin functionality. - * @param NewState: new state of the WakeUp Pin functionality. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_WakeUpPinCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; -} - -/** - * @brief Enters STOP mode. - * @param PWR_Regulator: specifies the regulator state in STOP mode. - * This parameter can be one of the following values: - * @arg PWR_Regulator_ON: STOP mode with regulator ON - * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode - * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction - * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction - * @retval None - */ -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(PWR_Regulator)); - assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); - - /* Select the regulator state in STOP mode ---------------------------------*/ - tmpreg = PWR->CR; - /* Clear PDDS and LPDS bits */ - tmpreg &= CR_DS_MASK; - /* Set LPDS bit according to PWR_Regulator value */ - tmpreg |= PWR_Regulator; - /* Store the new value */ - PWR->CR = tmpreg; - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP; - - /* Select STOP mode entry --------------------------------------------------*/ - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __WFE(); - } - - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); -} - -/** - * @brief Enters STANDBY mode. - * @param None - * @retval None - */ -void PWR_EnterSTANDBYMode(void) -{ - /* Clear Wake-up flag */ - PWR->CR |= PWR_CR_CWUF; - /* Select STANDBY mode */ - PWR->CR |= PWR_CR_PDDS; - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP; -/* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM ) - __force_stores(); -#endif - /* Request Wait For Interrupt */ - __WFI(); -} - -/** - * @brief Checks whether the specified PWR flag is set or not. - * @param PWR_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - * @arg PWR_FLAG_PVDO: PVD Output - * @retval The new state of PWR_FLAG (SET or RESET). - */ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); - - if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the PWR's pending flags. - * @param PWR_FLAG: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - * @retval None - */ -void PWR_ClearFlag(uint32_t PWR_FLAG) -{ - /* Check the parameters */ - assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); - - PWR->CR |= PWR_FLAG << 2; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c deleted file mode 100644 index 4b2ec1f10..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c +++ /dev/null @@ -1,1470 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_rcc.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the RCC firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup RCC - * @brief RCC driver modules - * @{ - */ - -/** @defgroup RCC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup RCC_Private_Defines - * @{ - */ - -/* ------------ RCC registers bit address in the alias region ----------- */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) - -/* --- CR Register ---*/ - -/* Alias word address of HSION bit */ -#define CR_OFFSET (RCC_OFFSET + 0x00) -#define HSION_BitNumber 0x00 -#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) - -/* Alias word address of PLLON bit */ -#define PLLON_BitNumber 0x18 -#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) - -#ifdef STM32F10X_CL - /* Alias word address of PLL2ON bit */ - #define PLL2ON_BitNumber 0x1A - #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4)) - - /* Alias word address of PLL3ON bit */ - #define PLL3ON_BitNumber 0x1C - #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4)) -#endif /* STM32F10X_CL */ - -/* Alias word address of CSSON bit */ -#define CSSON_BitNumber 0x13 -#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) - -/* --- CFGR Register ---*/ - -/* Alias word address of USBPRE bit */ -#define CFGR_OFFSET (RCC_OFFSET + 0x04) - -#ifndef STM32F10X_CL - #define USBPRE_BitNumber 0x16 - #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) -#else - #define OTGFSPRE_BitNumber 0x16 - #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4)) -#endif /* STM32F10X_CL */ - -/* --- BDCR Register ---*/ - -/* Alias word address of RTCEN bit */ -#define BDCR_OFFSET (RCC_OFFSET + 0x20) -#define RTCEN_BitNumber 0x0F -#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) - -/* Alias word address of BDRST bit */ -#define BDRST_BitNumber 0x10 -#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of LSION bit */ -#define CSR_OFFSET (RCC_OFFSET + 0x24) -#define LSION_BitNumber 0x00 -#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) - -#ifdef STM32F10X_CL -/* --- CFGR2 Register ---*/ - - /* Alias word address of I2S2SRC bit */ - #define CFGR2_OFFSET (RCC_OFFSET + 0x2C) - #define I2S2SRC_BitNumber 0x11 - #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4)) - - /* Alias word address of I2S3SRC bit */ - #define I2S3SRC_BitNumber 0x12 - #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4)) -#endif /* STM32F10X_CL */ - -/* ---------------------- RCC registers bit mask ------------------------ */ - -/* CR register bit mask */ -#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) -#define CR_HSEBYP_Set ((uint32_t)0x00040000) -#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF) -#define CR_HSEON_Set ((uint32_t)0x00010000) -#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) - -/* CFGR register bit mask */ -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) - #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF) -#else - #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) -#endif /* STM32F10X_CL */ - -#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000) -#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000) -#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000) -#define CFGR_SWS_Mask ((uint32_t)0x0000000C) -#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC) -#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) -#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0) -#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) -#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) -#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) -#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) -#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) -#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000) - -/* CSR register bit mask */ -#define CSR_RMVF_Set ((uint32_t)0x01000000) - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) -/* CFGR2 register bit mask */ - #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) - #define CFGR2_PREDIV1 ((uint32_t)0x0000000F) -#endif -#ifdef STM32F10X_CL - #define CFGR2_PREDIV2 ((uint32_t)0x000000F0) - #define CFGR2_PLL2MUL ((uint32_t)0x00000F00) - #define CFGR2_PLL3MUL ((uint32_t)0x0000F000) -#endif /* STM32F10X_CL */ - -/* RCC Flag Mask */ -#define FLAG_Mask ((uint8_t)0x1F) - -/* CIR register byte 2 (Bits[15:8]) base address */ -#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) - -/* CIR register byte 3 (Bits[23:16]) base address */ -#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) - -/* CFGR register byte 4 (Bits[31:24]) base address */ -#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007) - -/* BDCR register base address */ -#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) - -/** - * @} - */ - -/** @defgroup RCC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup RCC_Private_Variables - * @{ - */ - -static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; -static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; - -/** - * @} - */ - -/** @defgroup RCC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup RCC_Private_Functions - * @{ - */ - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @param None - * @retval None - */ -void RCC_DeInit(void) -{ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ -#ifndef STM32F10X_CL - RCC->CFGR &= (uint32_t)0xF8FF0000; -#else - RCC->CFGR &= (uint32_t)0xF0FF0000; -#endif /* STM32F10X_CL */ - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ - RCC->CFGR &= (uint32_t)0xFF80FFFF; - -#ifdef STM32F10X_CL - /* Reset PLL2ON and PLL3ON bits */ - RCC->CR &= (uint32_t)0xEBFFFFFF; - - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x00FF0000; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; -#else - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; -#endif /* STM32F10X_CL */ - -} - -/** - * @brief Configures the External High Speed oscillator (HSE). - * @note HSE can not be stopped if it is used directly or through the PLL as system clock. - * @param RCC_HSE: specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg RCC_HSE_OFF: HSE oscillator OFF - * @arg RCC_HSE_ON: HSE oscillator ON - * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock - * @retval None - */ -void RCC_HSEConfig(uint32_t RCC_HSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_HSE)); - /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ - /* Reset HSEON bit */ - RCC->CR &= CR_HSEON_Reset; - /* Reset HSEBYP bit */ - RCC->CR &= CR_HSEBYP_Reset; - /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */ - switch(RCC_HSE) - { - case RCC_HSE_ON: - /* Set HSEON bit */ - RCC->CR |= CR_HSEON_Set; - break; - - case RCC_HSE_Bypass: - /* Set HSEBYP and HSEON bits */ - RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set; - break; - - default: - break; - } -} - -/** - * @brief Waits for HSE start-up. - * @param None - * @retval An ErrorStatus enumuration value: - * - SUCCESS: HSE oscillator is stable and ready to use - * - ERROR: HSE oscillator not yet ready - */ -ErrorStatus RCC_WaitForHSEStartUp(void) -{ - __IO uint32_t StartUpCounter = 0; - ErrorStatus status = ERROR; - FlagStatus HSEStatus = RESET; - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - StartUpCounter++; - } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); - - if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - return (status); -} - -/** - * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - * @param HSICalibrationValue: specifies the calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * @retval None - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); - tmpreg = RCC->CR; - /* Clear HSITRIM[4:0] bits */ - tmpreg &= CR_HSITRIM_Mask; - /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ - tmpreg |= (uint32_t)HSICalibrationValue << 3; - /* Store the new value */ - RCC->CR = tmpreg; -} - -/** - * @brief Enables or disables the Internal High Speed oscillator (HSI). - * @note HSI can not be stopped if it is used directly or through the PLL as system clock. - * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_HSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the PLL clock source and multiplication factor. - * @note This function must be used only when the PLL is disabled. - * @param RCC_PLLSource: specifies the PLL entry clock source. - * For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices, - * this parameter can be one of the following values: - * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry - * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry - * For @b other_STM32_devices, this parameter can be one of the following values: - * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry - * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry - * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry - * @param RCC_PLLMul: specifies the PLL multiplication factor. - * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5} - * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16] - * @retval None - */ -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); - assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); - - tmpreg = RCC->CFGR; - /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ - tmpreg &= CFGR_PLL_Mask; - /* Set the PLL configuration bits */ - tmpreg |= RCC_PLLSource | RCC_PLLMul; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Enables or disables the PLL. - * @note The PLL can not be disabled if it is used as system clock. - * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; -} - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) -/** - * @brief Configures the PREDIV1 division factor. - * @note - * - This function must be used only when the PLL is disabled. - * - This function applies only to STM32 Connectivity line and Value line - * devices. - * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source. - * This parameter can be one of the following values: - * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock - * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock - * @note - * For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE - * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor. - * This parameter can be RCC_PREDIV1_Divx where x:[1,16] - * @retval None - */ -void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source)); - assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div)); - - tmpreg = RCC->CFGR2; - /* Clear PREDIV1[3:0] and PREDIV1SRC bits */ - tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC); - /* Set the PREDIV1 clock source and division factor */ - tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} -#endif - -#ifdef STM32F10X_CL -/** - * @brief Configures the PREDIV2 division factor. - * @note - * - This function must be used only when both PLL2 and PLL3 are disabled. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor. - * This parameter can be RCC_PREDIV2_Divx where x:[1,16] - * @retval None - */ -void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div)); - - tmpreg = RCC->CFGR2; - /* Clear PREDIV2[3:0] bits */ - tmpreg &= ~CFGR2_PREDIV2; - /* Set the PREDIV2 division factor */ - tmpreg |= RCC_PREDIV2_Div; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} - -/** - * @brief Configures the PLL2 multiplication factor. - * @note - * - This function must be used only when the PLL2 is disabled. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor. - * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20} - * @retval None - */ -void RCC_PLL2Config(uint32_t RCC_PLL2Mul) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul)); - - tmpreg = RCC->CFGR2; - /* Clear PLL2Mul[3:0] bits */ - tmpreg &= ~CFGR2_PLL2MUL; - /* Set the PLL2 configuration bits */ - tmpreg |= RCC_PLL2Mul; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} - - -/** - * @brief Enables or disables the PLL2. - * @note - * - The PLL2 can not be disabled if it is used indirectly as system clock - * (i.e. it is used as PLL clock entry that is used as System clock). - * - This function applies only to STM32 Connectivity line devices. - * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLL2Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState; -} - - -/** - * @brief Configures the PLL3 multiplication factor. - * @note - * - This function must be used only when the PLL3 is disabled. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor. - * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20} - * @retval None - */ -void RCC_PLL3Config(uint32_t RCC_PLL3Mul) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul)); - - tmpreg = RCC->CFGR2; - /* Clear PLL3Mul[3:0] bits */ - tmpreg &= ~CFGR2_PLL3MUL; - /* Set the PLL3 configuration bits */ - tmpreg |= RCC_PLL3Mul; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} - - -/** - * @brief Enables or disables the PLL3. - * @note This function applies only to STM32 Connectivity line devices. - * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLL3Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState; -} -#endif /* STM32F10X_CL */ - -/** - * @brief Configures the system clock (SYSCLK). - * @param RCC_SYSCLKSource: specifies the clock source used as system clock. - * This parameter can be one of the following values: - * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock - * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock - * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock - * @retval None - */ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); - tmpreg = RCC->CFGR; - /* Clear SW[1:0] bits */ - tmpreg &= CFGR_SW_Mask; - /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ - tmpreg |= RCC_SYSCLKSource; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the clock source used as system clock. - * @param None - * @retval The clock source used as system clock. The returned value can - * be one of the following: - * - 0x00: HSI used as system clock - * - 0x04: HSE used as system clock - * - 0x08: PLL used as system clock - */ -uint8_t RCC_GetSYSCLKSource(void) -{ - return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask)); -} - -/** - * @brief Configures the AHB clock (HCLK). - * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from - * the system clock (SYSCLK). - * This parameter can be one of the following values: - * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK - * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 - * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 - * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 - * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 - * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 - * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 - * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 - * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 - * @retval None - */ -void RCC_HCLKConfig(uint32_t RCC_SYSCLK) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_HCLK(RCC_SYSCLK)); - tmpreg = RCC->CFGR; - /* Clear HPRE[3:0] bits */ - tmpreg &= CFGR_HPRE_Reset_Mask; - /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ - tmpreg |= RCC_SYSCLK; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the Low Speed APB clock (PCLK1). - * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB1 clock = HCLK - * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK1Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - tmpreg = RCC->CFGR; - /* Clear PPRE1[2:0] bits */ - tmpreg &= CFGR_PPRE1_Reset_Mask; - /* Set PPRE1[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the High Speed APB clock (PCLK2). - * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB2 clock = HCLK - * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK2Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - tmpreg = RCC->CFGR; - /* Clear PPRE2[2:0] bits */ - tmpreg &= CFGR_PPRE2_Reset_Mask; - /* Set PPRE2[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK << 3; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Enables or disables the specified RCC interrupts. - * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. - * - * For @b STM32_Connectivity_line_devices, this parameter can be any combination - * of the following values - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt - * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt - * - * For @b other_STM32_devices, this parameter can be any combination of the - * following values - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * - * @param NewState: new state of the specified RCC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_IT(RCC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; - } - else - { - /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; - } -} - -#ifndef STM32F10X_CL -/** - * @brief Configures the USB clock (USBCLK). - * @param RCC_USBCLKSource: specifies the USB clock source. This clock is - * derived from the PLL output. - * This parameter can be one of the following values: - * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB - * clock source - * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source - * @retval None - */ -void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource)); - - *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource; -} -#else -/** - * @brief Configures the USB OTG FS clock (OTGFSCLK). - * This function applies only to STM32 Connectivity line devices. - * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source. - * This clock is derived from the PLL output. - * This parameter can be one of the following values: - * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source - * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source - * @retval None - */ -void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource)); - - *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource; -} -#endif /* STM32F10X_CL */ - -/** - * @brief Configures the ADC clock (ADCCLK). - * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from - * the APB2 clock (PCLK2). - * This parameter can be one of the following values: - * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2 - * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4 - * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6 - * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8 - * @retval None - */ -void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_ADCCLK(RCC_PCLK2)); - tmpreg = RCC->CFGR; - /* Clear ADCPRE[1:0] bits */ - tmpreg &= CFGR_ADCPRE_Reset_Mask; - /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */ - tmpreg |= RCC_PCLK2; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -#ifdef STM32F10X_CL -/** - * @brief Configures the I2S2 clock source(I2S2CLK). - * @note - * - This function must be called before enabling I2S2 APB clock. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_I2S2CLKSource: specifies the I2S2 clock source. - * This parameter can be one of the following values: - * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry - * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry - * @retval None - */ -void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource)); - - *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource; -} - -/** - * @brief Configures the I2S3 clock source(I2S2CLK). - * @note - * - This function must be called before enabling I2S3 APB clock. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_I2S3CLKSource: specifies the I2S3 clock source. - * This parameter can be one of the following values: - * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry - * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry - * @retval None - */ -void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource)); - - *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource; -} -#endif /* STM32F10X_CL */ - -/** - * @brief Configures the External Low Speed oscillator (LSE). - * @param RCC_LSE: specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg RCC_LSE_OFF: LSE oscillator OFF - * @arg RCC_LSE_ON: LSE oscillator ON - * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock - * @retval None - */ -void RCC_LSEConfig(uint8_t RCC_LSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_LSE)); - /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ - /* Reset LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - /* Reset LSEBYP bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ - switch(RCC_LSE) - { - case RCC_LSE_ON: - /* Set LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; - break; - - case RCC_LSE_Bypass: - /* Set LSEBYP and LSEON bits */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; - break; - - default: - break; - } -} - -/** - * @brief Enables or disables the Internal Low Speed oscillator (LSI). - * @note LSI can not be disabled if the IWDG is running. - * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_LSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the RTC clock (RTCCLK). - * @note Once the RTC clock is selected it can't be changed unless the Backup domain is reset. - * @param RCC_RTCCLKSource: specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock - * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock - * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock - * @retval None - */ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); - /* Select the RTC clock source */ - RCC->BDCR |= RCC_RTCCLKSource; -} - -/** - * @brief Enables or disables the RTC clock. - * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function. - * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_RTCCLKCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; -} - -/** - * @brief Returns the frequencies of different on chip clocks. - * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold - * the clocks frequencies. - * @note The result of this function could be not correct when using - * fractional value for HSE crystal. - * @retval None - */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; - -#ifdef STM32F10X_CL - uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - uint32_t prediv1factor = 0; -#endif - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & CFGR_SWS_Mask; - - switch (tmp) - { - case 0x00: /* HSI used as system clock */ - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock */ - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock */ - - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & CFGR_PLLMull_Mask; - pllsource = RCC->CFGR & CFGR_PLLSRC_Mask; - -#ifndef STM32F10X_CL - pllmull = ( pllmull >> 18) + 2; - - if (pllsource == 0x00) - {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ - RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; - } - else - { - #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; - /* HSE oscillator clock selected as PREDIV1 clock entry */ - RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; - #else - /* HSE selected as PLL clock entry */ - if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET) - {/* HSE oscillator clock divided by 2 */ - RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; - } - else - { - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; - } - #endif - } -#else - pllmull = pllmull >> 18; - - if (pllmull != 0x0D) - { - pllmull += 2; - } - else - { /* PLL multiplication factor = PLL input clock * 6.5 */ - pllmull = 13 / 2; - } - - if (pllsource == 0x00) - {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ - RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; - } - else - {/* PREDIV1 selected as PLL clock entry */ - - /* Get PREDIV1 clock source and division factor */ - prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC; - prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; - - if (prediv1source == 0) - { /* HSE oscillator clock selected as PREDIV1 clock entry */ - RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; - } - else - {/* PLL2 clock selected as PREDIV1 clock entry */ - - /* Get PREDIV2 division factor and PLL2 multiplication factor */ - prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1; - pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; - RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; - } - } -#endif /* STM32F10X_CL */ - break; - - default: - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - } - - /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ - /* Get HCLK prescaler */ - tmp = RCC->CFGR & CFGR_HPRE_Set_Mask; - tmp = tmp >> 4; - presc = APBAHBPrescTable[tmp]; - /* HCLK clock frequency */ - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; - /* Get PCLK1 prescaler */ - tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask; - tmp = tmp >> 8; - presc = APBAHBPrescTable[tmp]; - /* PCLK1 clock frequency */ - RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - /* Get PCLK2 prescaler */ - tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask; - tmp = tmp >> 11; - presc = APBAHBPrescTable[tmp]; - /* PCLK2 clock frequency */ - RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - /* Get ADCCLK prescaler */ - tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask; - tmp = tmp >> 14; - presc = ADCPrescTable[tmp]; - /* ADCCLK clock frequency */ - RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; -} - -/** - * @brief Enables or disables the AHB peripheral clock. - * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. - * - * For @b STM32_Connectivity_line_devices, this parameter can be any combination - * of the following values: - * @arg RCC_AHBPeriph_DMA1 - * @arg RCC_AHBPeriph_DMA2 - * @arg RCC_AHBPeriph_SRAM - * @arg RCC_AHBPeriph_FLITF - * @arg RCC_AHBPeriph_CRC - * @arg RCC_AHBPeriph_OTG_FS - * @arg RCC_AHBPeriph_ETH_MAC - * @arg RCC_AHBPeriph_ETH_MAC_Tx - * @arg RCC_AHBPeriph_ETH_MAC_Rx - * - * For @b other_STM32_devices, this parameter can be any combination of the - * following values: - * @arg RCC_AHBPeriph_DMA1 - * @arg RCC_AHBPeriph_DMA2 - * @arg RCC_AHBPeriph_SRAM - * @arg RCC_AHBPeriph_FLITF - * @arg RCC_AHBPeriph_CRC - * @arg RCC_AHBPeriph_FSMC - * @arg RCC_AHBPeriph_SDIO - * - * @note SRAM and FLITF clock can be disabled only during sleep mode. - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHBENR |= RCC_AHBPeriph; - } - else - { - RCC->AHBENR &= ~RCC_AHBPeriph; - } -} - -/** - * @brief Enables or disables the High Speed APB (APB2) peripheral clock. - * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, - * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, - * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, - * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, - * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, - * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, - * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2ENR |= RCC_APB2Periph; - } - else - { - RCC->APB2ENR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. - * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, - * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, - * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, - * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, - * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, - * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, - * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, - * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1ENR |= RCC_APB1Periph; - } - else - { - RCC->APB1ENR &= ~RCC_APB1Periph; - } -} - -#ifdef STM32F10X_CL -/** - * @brief Forces or releases AHB peripheral reset. - * @note This function applies only to STM32 Connectivity line devices. - * @param RCC_AHBPeriph: specifies the AHB peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_AHBPeriph_OTG_FS - * @arg RCC_AHBPeriph_ETH_MAC - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHBRSTR |= RCC_AHBPeriph; - } - else - { - RCC->AHBRSTR &= ~RCC_AHBPeriph; - } -} -#endif /* STM32F10X_CL */ - -/** - * @brief Forces or releases High Speed APB (APB2) peripheral reset. - * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, - * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, - * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, - * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, - * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, - * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, - * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2RSTR |= RCC_APB2Periph; - } - else - { - RCC->APB2RSTR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Forces or releases Low Speed APB (APB1) peripheral reset. - * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, - * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, - * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, - * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, - * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, - * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, - * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, - * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1RSTR |= RCC_APB1Periph; - } - else - { - RCC->APB1RSTR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Forces or releases the Backup domain reset. - * @param NewState: new state of the Backup domain reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_BackupResetCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Clock Security System. - * @param NewState: new state of the Clock Security System.. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ClockSecuritySystemCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; -} - -/** - * @brief Selects the clock source to output on MCO pin. - * @param RCC_MCO: specifies the clock source to output. - * - * For @b STM32_Connectivity_line_devices, this parameter can be one of the - * following values: - * @arg RCC_MCO_NoClock: No clock selected - * @arg RCC_MCO_SYSCLK: System clock selected - * @arg RCC_MCO_HSI: HSI oscillator clock selected - * @arg RCC_MCO_HSE: HSE oscillator clock selected - * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected - * @arg RCC_MCO_PLL2CLK: PLL2 clock selected - * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected - * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected - * @arg RCC_MCO_PLL3CLK: PLL3 clock selected - * - * For @b other_STM32_devices, this parameter can be one of the following values: - * @arg RCC_MCO_NoClock: No clock selected - * @arg RCC_MCO_SYSCLK: System clock selected - * @arg RCC_MCO_HSI: HSI oscillator clock selected - * @arg RCC_MCO_HSE: HSE oscillator clock selected - * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected - * - * @retval None - */ -void RCC_MCOConfig(uint8_t RCC_MCO) -{ - /* Check the parameters */ - assert_param(IS_RCC_MCO(RCC_MCO)); - - /* Perform Byte access to MCO bits to select the MCO source */ - *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO; -} - -/** - * @brief Checks whether the specified RCC flag is set or not. - * @param RCC_FLAG: specifies the flag to check. - * - * For @b STM32_Connectivity_line_devices, this parameter can be one of the - * following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready - * @arg RCC_FLAG_PLLRDY: PLL clock ready - * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready - * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready - * @arg RCC_FLAG_PINRST: Pin reset - * @arg RCC_FLAG_PORRST: POR/PDR reset - * @arg RCC_FLAG_SFTRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPWRRST: Low Power reset - * - * For @b other_STM32_devices, this parameter can be one of the following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready - * @arg RCC_FLAG_PLLRDY: PLL clock ready - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready - * @arg RCC_FLAG_PINRST: Pin reset - * @arg RCC_FLAG_PORRST: POR/PDR reset - * @arg RCC_FLAG_SFTRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPWRRST: Low Power reset - * - * @retval The new state of RCC_FLAG (SET or RESET). - */ -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -{ - uint32_t tmp = 0; - uint32_t statusreg = 0; - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RCC_FLAG(RCC_FLAG)); - - /* Get the RCC register index */ - tmp = RCC_FLAG >> 5; - if (tmp == 1) /* The flag to check is in CR register */ - { - statusreg = RCC->CR; - } - else if (tmp == 2) /* The flag to check is in BDCR register */ - { - statusreg = RCC->BDCR; - } - else /* The flag to check is in CSR register */ - { - statusreg = RCC->CSR; - } - - /* Get the flag position */ - tmp = RCC_FLAG & FLAG_Mask; - if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the RCC reset flags. - * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, - * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST - * @param None - * @retval None - */ -void RCC_ClearFlag(void) -{ - /* Set RMVF bit to clear the reset flags */ - RCC->CSR |= CSR_RMVF_Set; -} - -/** - * @brief Checks whether the specified RCC interrupt has occurred or not. - * @param RCC_IT: specifies the RCC interrupt source to check. - * - * For @b STM32_Connectivity_line_devices, this parameter can be one of the - * following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt - * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * - * For @b other_STM32_devices, this parameter can be one of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * - * @retval The new state of RCC_IT (SET or RESET). - */ -ITStatus RCC_GetITStatus(uint8_t RCC_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RCC_GET_IT(RCC_IT)); - - /* Check the status of the specified RCC interrupt */ - if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - /* Return the RCC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the RCC's interrupt pending bits. - * @param RCC_IT: specifies the interrupt pending bit to clear. - * - * For @b STM32_Connectivity_line_devices, this parameter can be any combination - * of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt - * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * - * For @b other_STM32_devices, this parameter can be any combination of the - * following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval None - */ -void RCC_ClearITPendingBit(uint8_t RCC_IT) -{ - /* Check the parameters */ - assert_param(IS_RCC_CLEAR_IT(RCC_IT)); - - /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt - pending bits */ - *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c deleted file mode 100644 index f798d2bd6..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c +++ /dev/null @@ -1,339 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_rtc.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the RTC firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_rtc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup RTC - * @brief RTC driver modules - * @{ - */ - -/** @defgroup RTC_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - -/** @defgroup RTC_Private_Defines - * @{ - */ -#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */ -#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */ - -/** - * @} - */ - -/** @defgroup RTC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Private_Functions - * @{ - */ - -/** - * @brief Enables or disables the specified RTC interrupts. - * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_OW: Overflow interrupt - * @arg RTC_IT_ALR: Alarm interrupt - * @arg RTC_IT_SEC: Second interrupt - * @param NewState: new state of the specified RTC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RTC_IT(RTC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RTC->CRH |= RTC_IT; - } - else - { - RTC->CRH &= (uint16_t)~RTC_IT; - } -} - -/** - * @brief Enters the RTC configuration mode. - * @param None - * @retval None - */ -void RTC_EnterConfigMode(void) -{ - /* Set the CNF flag to enter in the Configuration Mode */ - RTC->CRL |= RTC_CRL_CNF; -} - -/** - * @brief Exits from the RTC configuration mode. - * @param None - * @retval None - */ -void RTC_ExitConfigMode(void) -{ - /* Reset the CNF flag to exit from the Configuration Mode */ - RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF); -} - -/** - * @brief Gets the RTC counter value. - * @param None - * @retval RTC counter value. - */ -uint32_t RTC_GetCounter(void) -{ - uint16_t tmp = 0; - tmp = RTC->CNTL; - return (((uint32_t)RTC->CNTH << 16 ) | tmp) ; -} - -/** - * @brief Sets the RTC counter value. - * @param CounterValue: RTC counter new value. - * @retval None - */ -void RTC_SetCounter(uint32_t CounterValue) -{ - RTC_EnterConfigMode(); - /* Set RTC COUNTER MSB word */ - RTC->CNTH = CounterValue >> 16; - /* Set RTC COUNTER LSB word */ - RTC->CNTL = (CounterValue & RTC_LSB_MASK); - RTC_ExitConfigMode(); -} - -/** - * @brief Sets the RTC prescaler value. - * @param PrescalerValue: RTC prescaler new value. - * @retval None - */ -void RTC_SetPrescaler(uint32_t PrescalerValue) -{ - /* Check the parameters */ - assert_param(IS_RTC_PRESCALER(PrescalerValue)); - - RTC_EnterConfigMode(); - /* Set RTC PRESCALER MSB word */ - RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16; - /* Set RTC PRESCALER LSB word */ - RTC->PRLL = (PrescalerValue & RTC_LSB_MASK); - RTC_ExitConfigMode(); -} - -/** - * @brief Sets the RTC alarm value. - * @param AlarmValue: RTC alarm new value. - * @retval None - */ -void RTC_SetAlarm(uint32_t AlarmValue) -{ - RTC_EnterConfigMode(); - /* Set the ALARM MSB word */ - RTC->ALRH = AlarmValue >> 16; - /* Set the ALARM LSB word */ - RTC->ALRL = (AlarmValue & RTC_LSB_MASK); - RTC_ExitConfigMode(); -} - -/** - * @brief Gets the RTC divider value. - * @param None - * @retval RTC Divider value. - */ -uint32_t RTC_GetDivider(void) -{ - uint32_t tmp = 0x00; - tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; - tmp |= RTC->DIVL; - return tmp; -} - -/** - * @brief Waits until last write operation on RTC registers has finished. - * @note This function must be called before any write to RTC registers. - * @param None - * @retval None - */ -void RTC_WaitForLastTask(void) -{ - /* Loop until RTOFF flag is set */ - while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) - { - } -} - -/** - * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) - * are synchronized with RTC APB clock. - * @note This function must be called before any read operation after an APB reset - * or an APB clock stop. - * @param None - * @retval None - */ -void RTC_WaitForSynchro(void) -{ - /* Clear RSF flag */ - RTC->CRL &= (uint16_t)~RTC_FLAG_RSF; - /* Loop until RSF flag is set */ - while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET) - { - } -} - -/** - * @brief Checks whether the specified RTC flag is set or not. - * @param RTC_FLAG: specifies the flag to check. - * This parameter can be one the following values: - * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @arg RTC_FLAG_OW: Overflow flag - * @arg RTC_FLAG_ALR: Alarm flag - * @arg RTC_FLAG_SEC: Second flag - * @retval The new state of RTC_FLAG (SET or RESET). - */ -FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); - - if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's pending flags. - * @param RTC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after - * an APB reset or an APB Clock stop. - * @arg RTC_FLAG_OW: Overflow flag - * @arg RTC_FLAG_ALR: Alarm flag - * @arg RTC_FLAG_SEC: Second flag - * @retval None - */ -void RTC_ClearFlag(uint16_t RTC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); - - /* Clear the corresponding RTC flag */ - RTC->CRL &= (uint16_t)~RTC_FLAG; -} - -/** - * @brief Checks whether the specified RTC interrupt has occurred or not. - * @param RTC_IT: specifies the RTC interrupts sources to check. - * This parameter can be one of the following values: - * @arg RTC_IT_OW: Overflow interrupt - * @arg RTC_IT_ALR: Alarm interrupt - * @arg RTC_IT_SEC: Second interrupt - * @retval The new state of the RTC_IT (SET or RESET). - */ -ITStatus RTC_GetITStatus(uint16_t RTC_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RTC_GET_IT(RTC_IT)); - - bitstatus = (ITStatus)(RTC->CRL & RTC_IT); - if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's interrupt pending bits. - * @param RTC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RTC_IT_OW: Overflow interrupt - * @arg RTC_IT_ALR: Alarm interrupt - * @arg RTC_IT_SEC: Second interrupt - * @retval None - */ -void RTC_ClearITPendingBit(uint16_t RTC_IT) -{ - /* Check the parameters */ - assert_param(IS_RTC_IT(RTC_IT)); - - /* Clear the corresponding RTC pending bit */ - RTC->CRL &= (uint16_t)~RTC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c deleted file mode 100644 index d1870cef1..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c +++ /dev/null @@ -1,799 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_sdio.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the SDIO firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_sdio.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup SDIO - * @brief SDIO driver modules - * @{ - */ - -/** @defgroup SDIO_Private_TypesDefinitions - * @{ - */ - -/* ------------ SDIO registers bit address in the alias region ----------- */ -#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) - -/* --- CLKCR Register ---*/ - -/* Alias word address of CLKEN bit */ -#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) -#define CLKEN_BitNumber 0x08 -#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) - -/* --- CMD Register ---*/ - -/* Alias word address of SDIOSUSPEND bit */ -#define CMD_OFFSET (SDIO_OFFSET + 0x0C) -#define SDIOSUSPEND_BitNumber 0x0B -#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) - -/* Alias word address of ENCMDCOMPL bit */ -#define ENCMDCOMPL_BitNumber 0x0C -#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) - -/* Alias word address of NIEN bit */ -#define NIEN_BitNumber 0x0D -#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) - -/* Alias word address of ATACMD bit */ -#define ATACMD_BitNumber 0x0E -#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) - -/* --- DCTRL Register ---*/ - -/* Alias word address of DMAEN bit */ -#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) -#define DMAEN_BitNumber 0x03 -#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) - -/* Alias word address of RWSTART bit */ -#define RWSTART_BitNumber 0x08 -#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) - -/* Alias word address of RWSTOP bit */ -#define RWSTOP_BitNumber 0x09 -#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) - -/* Alias word address of RWMOD bit */ -#define RWMOD_BitNumber 0x0A -#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) - -/* Alias word address of SDIOEN bit */ -#define SDIOEN_BitNumber 0x0B -#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) - -/* ---------------------- SDIO registers bit mask ------------------------ */ - -/* --- CLKCR Register ---*/ - -/* CLKCR register clear mask */ -#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) - -/* --- PWRCTRL Register ---*/ - -/* SDIO PWRCTRL Mask */ -#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) - -/* --- DCTRL Register ---*/ - -/* SDIO DCTRL Clear Mask */ -#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) - -/* --- CMD Register ---*/ - -/* CMD Register clear mask */ -#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) - -/* SDIO RESP Registers Address */ -#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) - -/** - * @} - */ - -/** @defgroup SDIO_Private_Defines - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the SDIO peripheral registers to their default reset values. - * @param None - * @retval None - */ -void SDIO_DeInit(void) -{ - SDIO->POWER = 0x00000000; - SDIO->CLKCR = 0x00000000; - SDIO->ARG = 0x00000000; - SDIO->CMD = 0x00000000; - SDIO->DTIMER = 0x00000000; - SDIO->DLEN = 0x00000000; - SDIO->DCTRL = 0x00000000; - SDIO->ICR = 0x00C007FF; - SDIO->MASK = 0x00000000; -} - -/** - * @brief Initializes the SDIO peripheral according to the specified - * parameters in the SDIO_InitStruct. - * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure - * that contains the configuration information for the SDIO peripheral. - * @retval None - */ -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); - assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); - assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); - assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); - assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); - -/*---------------------------- SDIO CLKCR Configuration ------------------------*/ - /* Get the SDIO CLKCR value */ - tmpreg = SDIO->CLKCR; - - /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ - tmpreg &= CLKCR_CLEAR_MASK; - - /* Set CLKDIV bits according to SDIO_ClockDiv value */ - /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ - /* Set BYPASS bit according to SDIO_ClockBypass value */ - /* Set WIDBUS bits according to SDIO_BusWide value */ - /* Set NEGEDGE bits according to SDIO_ClockEdge value */ - /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ - tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | - SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | - SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); - - /* Write to SDIO CLKCR */ - SDIO->CLKCR = tmpreg; -} - -/** - * @brief Fills each SDIO_InitStruct member with its default value. - * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which - * will be initialized. - * @retval None - */ -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) -{ - /* SDIO_InitStruct members default value */ - SDIO_InitStruct->SDIO_ClockDiv = 0x00; - SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; - SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; - SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; - SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; - SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; -} - -/** - * @brief Enables or disables the SDIO Clock. - * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_ClockCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; -} - -/** - * @brief Sets the power status of the controller. - * @param SDIO_PowerState: new state of the Power state. - * This parameter can be one of the following values: - * @arg SDIO_PowerState_OFF - * @arg SDIO_PowerState_ON - * @retval None - */ -void SDIO_SetPowerState(uint32_t SDIO_PowerState) -{ - /* Check the parameters */ - assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); - - SDIO->POWER &= PWR_PWRCTRL_MASK; - SDIO->POWER |= SDIO_PowerState; -} - -/** - * @brief Gets the power status of the controller. - * @param None - * @retval Power status of the controller. The returned value can - * be one of the following: - * - 0x00: Power OFF - * - 0x02: Power UP - * - 0x03: Power ON - */ -uint32_t SDIO_GetPowerState(void) -{ - return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); -} - -/** - * @brief Enables or disables the SDIO interrupts. - * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @param NewState: new state of the specified SDIO interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SDIO_IT(SDIO_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the SDIO interrupts */ - SDIO->MASK |= SDIO_IT; - } - else - { - /* Disable the SDIO interrupts */ - SDIO->MASK &= ~SDIO_IT; - } -} - -/** - * @brief Enables or disables the SDIO DMA request. - * @param NewState: new state of the selected SDIO DMA request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_DMACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; -} - -/** - * @brief Initializes the SDIO Command according to the specified - * parameters in the SDIO_CmdInitStruct and send the command. - * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef - * structure that contains the configuration information for the SDIO command. - * @retval None - */ -void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); - assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); - assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); - assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); - -/*---------------------------- SDIO ARG Configuration ------------------------*/ - /* Set the SDIO Argument value */ - SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; - -/*---------------------------- SDIO CMD Configuration ------------------------*/ - /* Get the SDIO CMD value */ - tmpreg = SDIO->CMD; - /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ - tmpreg &= CMD_CLEAR_MASK; - /* Set CMDINDEX bits according to SDIO_CmdIndex value */ - /* Set WAITRESP bits according to SDIO_Response value */ - /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ - /* Set CPSMEN bits according to SDIO_CPSM value */ - tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response - | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; - - /* Write to SDIO CMD */ - SDIO->CMD = tmpreg; -} - -/** - * @brief Fills each SDIO_CmdInitStruct member with its default value. - * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef - * structure which will be initialized. - * @retval None - */ -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) -{ - /* SDIO_CmdInitStruct members default value */ - SDIO_CmdInitStruct->SDIO_Argument = 0x00; - SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; - SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; - SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; -} - -/** - * @brief Returns command index of last command for which response received. - * @param None - * @retval Returns the command index of the last command response received. - */ -uint8_t SDIO_GetCommandResponse(void) -{ - return (uint8_t)(SDIO->RESPCMD); -} - -/** - * @brief Returns response received from the card for the last command. - * @param SDIO_RESP: Specifies the SDIO response register. - * This parameter can be one of the following values: - * @arg SDIO_RESP1: Response Register 1 - * @arg SDIO_RESP2: Response Register 2 - * @arg SDIO_RESP3: Response Register 3 - * @arg SDIO_RESP4: Response Register 4 - * @retval The Corresponding response register value. - */ -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_RESP(SDIO_RESP)); - - tmp = SDIO_RESP_ADDR + SDIO_RESP; - - return (*(__IO uint32_t *) tmp); -} - -/** - * @brief Initializes the SDIO data path according to the specified - * parameters in the SDIO_DataInitStruct. - * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that - * contains the configuration information for the SDIO command. - * @retval None - */ -void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); - assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); - assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); - assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); - assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); - -/*---------------------------- SDIO DTIMER Configuration ---------------------*/ - /* Set the SDIO Data TimeOut value */ - SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; - -/*---------------------------- SDIO DLEN Configuration -----------------------*/ - /* Set the SDIO DataLength value */ - SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; - -/*---------------------------- SDIO DCTRL Configuration ----------------------*/ - /* Get the SDIO DCTRL value */ - tmpreg = SDIO->DCTRL; - /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ - tmpreg &= DCTRL_CLEAR_MASK; - /* Set DEN bit according to SDIO_DPSM value */ - /* Set DTMODE bit according to SDIO_TransferMode value */ - /* Set DTDIR bit according to SDIO_TransferDir value */ - /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ - tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir - | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; - - /* Write to SDIO DCTRL */ - SDIO->DCTRL = tmpreg; -} - -/** - * @brief Fills each SDIO_DataInitStruct member with its default value. - * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which - * will be initialized. - * @retval None - */ -void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - /* SDIO_DataInitStruct members default value */ - SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; - SDIO_DataInitStruct->SDIO_DataLength = 0x00; - SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; - SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; - SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; -} - -/** - * @brief Returns number of remaining data bytes to be transferred. - * @param None - * @retval Number of remaining data bytes to be transferred - */ -uint32_t SDIO_GetDataCounter(void) -{ - return SDIO->DCOUNT; -} - -/** - * @brief Read one data word from Rx FIFO. - * @param None - * @retval Data received - */ -uint32_t SDIO_ReadData(void) -{ - return SDIO->FIFO; -} - -/** - * @brief Write one data word to Tx FIFO. - * @param Data: 32-bit data word to write. - * @retval None - */ -void SDIO_WriteData(uint32_t Data) -{ - SDIO->FIFO = Data; -} - -/** - * @brief Returns the number of words left to be written to or read from FIFO. - * @param None - * @retval Remaining number of words. - */ -uint32_t SDIO_GetFIFOCount(void) -{ - return SDIO->FIFOCNT; -} - -/** - * @brief Starts the SD I/O Read Wait operation. - * @param NewState: new state of the Start SDIO Read Wait operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StartSDIOReadWait(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; -} - -/** - * @brief Stops the SD I/O Read Wait operation. - * @param NewState: new state of the Stop SDIO Read Wait operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StopSDIOReadWait(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; -} - -/** - * @brief Sets one of the two options of inserting read wait interval. - * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. - * This parameter can be: - * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK - * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 - * @retval None - */ -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) -{ - /* Check the parameters */ - assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); - - *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; -} - -/** - * @brief Enables or disables the SD I/O Mode Operation. - * @param NewState: new state of SDIO specific operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SetSDIOOperation(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the SD I/O Mode suspend command sending. - * @param NewState: new state of the SD I/O Mode suspend command. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the command completion signal. - * @param NewState: new state of command completion signal. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CommandCompletionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the CE-ATA interrupt. - * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CEATAITCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); -} - -/** - * @brief Sends CE-ATA command (CMD61). - * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendCEATACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; -} - -/** - * @brief Checks whether the specified SDIO flag is set or not. - * @param SDIO_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide - * bus mode. - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_CMDACT: Command transfer in progress - * @arg SDIO_FLAG_TXACT: Data transmit in progress - * @arg SDIO_FLAG_RXACT: Data receive in progress - * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty - * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full - * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full - * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full - * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty - * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty - * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO - * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval The new state of SDIO_FLAG (SET or RESET). - */ -FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SDIO_FLAG(SDIO_FLAG)); - - if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SDIO's pending flags. - * @param SDIO_FLAG: specifies the flag to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide - * bus mode - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearFlag(uint32_t SDIO_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); - - SDIO->ICR = SDIO_FLAG; -} - -/** - * @brief Checks whether the specified SDIO interrupt has occurred or not. - * @param SDIO_IT: specifies the SDIO interrupt source to check. - * This parameter can be one of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @retval The new state of SDIO_IT (SET or RESET). - */ -ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SDIO_GET_IT(SDIO_IT)); - if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SDIO's interrupt pending bits. - * @param SDIO_IT: specifies the interrupt pending bit to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearITPendingBit(uint32_t SDIO_IT) -{ - /* Check the parameters */ - assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); - - SDIO->ICR = SDIO_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c deleted file mode 100644 index 51a9cce77..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c +++ /dev/null @@ -1,908 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_spi.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the SPI firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_spi.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup SPI - * @brief SPI driver modules - * @{ - */ - -/** @defgroup SPI_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - - -/** @defgroup SPI_Private_Defines - * @{ - */ - -/* SPI SPE mask */ -#define CR1_SPE_Set ((uint16_t)0x0040) -#define CR1_SPE_Reset ((uint16_t)0xFFBF) - -/* I2S I2SE mask */ -#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) -#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) - -/* SPI CRCNext mask */ -#define CR1_CRCNext_Set ((uint16_t)0x1000) - -/* SPI CRCEN mask */ -#define CR1_CRCEN_Set ((uint16_t)0x2000) -#define CR1_CRCEN_Reset ((uint16_t)0xDFFF) - -/* SPI SSOE mask */ -#define CR2_SSOE_Set ((uint16_t)0x0004) -#define CR2_SSOE_Reset ((uint16_t)0xFFFB) - -/* SPI registers Masks */ -#define CR1_CLEAR_Mask ((uint16_t)0x3040) -#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) - -/* SPI or I2S mode selection masks */ -#define SPI_Mode_Select ((uint16_t)0xF7FF) -#define I2S_Mode_Select ((uint16_t)0x0800) - -/* I2S clock source selection masks */ -#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) -#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) -#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) -#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) - -/** - * @} - */ - -/** @defgroup SPI_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup SPI_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup SPI_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup SPI_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the SPIx peripheral registers to their default - * reset values (Affects also the I2Ss). - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval None - */ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - if (SPIx == SPI1) - { - /* Enable SPI1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); - /* Release SPI1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); - } - else if (SPIx == SPI2) - { - /* Enable SPI2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); - /* Release SPI2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); - } - else - { - if (SPIx == SPI3) - { - /* Enable SPI3 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); - /* Release SPI3 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); - } - } -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral. - * @retval None - */ -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) -{ - uint16_t tmpreg = 0; - - /* check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Check the SPI parameters */ - assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); - assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); - assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); - assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); - assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); - assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); - assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); - assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); - assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); - -/*---------------------------- SPIx CR1 Configuration ------------------------*/ - /* Get the SPIx CR1 value */ - tmpreg = SPIx->CR1; - /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ - tmpreg &= CR1_CLEAR_Mask; - /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler - master/salve mode, CPOL and CPHA */ - /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ - /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ - /* Set LSBFirst bit according to SPI_FirstBit value */ - /* Set BR bits according to SPI_BaudRatePrescaler value */ - /* Set CPOL bit according to SPI_CPOL value */ - /* Set CPHA bit according to SPI_CPHA value */ - tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | - SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | - SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | - SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); - /* Write to SPIx CR1 */ - SPIx->CR1 = tmpreg; - - /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ - SPIx->I2SCFGR &= SPI_Mode_Select; - -/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ - /* Write to SPIx CRCPOLY */ - SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the I2S_InitStruct. - * @param SPIx: where x can be 2 or 3 to select the SPI peripheral - * (configured in I2S mode). - * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral - * configured in I2S mode. - * @note - * The function calculates the optimal prescaler needed to obtain the most - * accurate audio frequency (depending on the I2S clock source, the PLL values - * and the product configuration). But in case the prescaler value is greater - * than 511, the default value (0x02) will be configured instead. * - * @retval None - */ -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) -{ - uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; - uint32_t tmp = 0; - RCC_ClocksTypeDef RCC_Clocks; - uint32_t sourceclock = 0; - - /* Check the I2S parameters */ - assert_param(IS_SPI_23_PERIPH(SPIx)); - assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); - assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); - assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); - assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); - assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); - assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); - -/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; - SPIx->I2SPR = 0x0002; - - /* Get the I2SCFGR register value */ - tmpreg = SPIx->I2SCFGR; - - /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ - if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) - { - i2sodd = (uint16_t)0; - i2sdiv = (uint16_t)2; - } - /* If the requested audio frequency is not the default, compute the prescaler */ - else - { - /* Check the frame length (For the Prescaler computing) */ - if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) - { - /* Packet length is 16 bits */ - packetlength = 1; - } - else - { - /* Packet length is 32 bits */ - packetlength = 2; - } - - /* Get the I2S clock source mask depending on the peripheral number */ - if(((uint32_t)SPIx) == SPI2_BASE) - { - /* The mask is relative to I2S2 */ - tmp = I2S2_CLOCK_SRC; - } - else - { - /* The mask is relative to I2S3 */ - tmp = I2S3_CLOCK_SRC; - } - - /* Check the I2S clock source configuration depending on the Device: - Only Connectivity line devices have the PLL3 VCO clock */ -#ifdef STM32F10X_CL - if((RCC->CFGR2 & tmp) != 0) - { - /* Get the configuration bits of RCC PLL3 multiplier */ - tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12); - - /* Get the value of the PLL3 multiplier */ - if((tmp > 5) && (tmp < 15)) - { - /* Multiplier is between 8 and 14 (value 15 is forbidden) */ - tmp += 2; - } - else - { - if (tmp == 15) - { - /* Multiplier is 20 */ - tmp = 20; - } - } - /* Get the PREDIV2 value */ - sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1); - - /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */ - sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2); - } - else - { - /* I2S Clock source is System clock: Get System Clock frequency */ - RCC_GetClocksFreq(&RCC_Clocks); - - /* Get the source clock value: based on System Clock value */ - sourceclock = RCC_Clocks.SYSCLK_Frequency; - } -#else /* STM32F10X_HD */ - /* I2S Clock source is System clock: Get System Clock frequency */ - RCC_GetClocksFreq(&RCC_Clocks); - - /* Get the source clock value: based on System Clock value */ - sourceclock = RCC_Clocks.SYSCLK_Frequency; -#endif /* STM32F10X_CL */ - - /* Compute the Real divider depending on the MCLK output state with a floating point */ - if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) - { - /* MCLK output is enabled */ - tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - else - { - /* MCLK output is disabled */ - tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - - /* Remove the floating point */ - tmp = tmp / 10; - - /* Check the parity of the divider */ - i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); - - /* Compute the i2sdiv prescaler */ - i2sdiv = (uint16_t)((tmp - i2sodd) / 2); - - /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ - i2sodd = (uint16_t) (i2sodd << 8); - } - - /* Test if the divider is 1 or 0 or greater than 0xFF */ - if ((i2sdiv < 2) || (i2sdiv > 0xFF)) - { - /* Set the default values */ - i2sdiv = 2; - i2sodd = 0; - } - - /* Write to SPIx I2SPR register the computed value */ - SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); - - /* Configure the I2S with the SPI_InitStruct values */ - tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \ - (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ - (uint16_t)I2S_InitStruct->I2S_CPOL)))); - - /* Write to SPIx I2SCFGR */ - SPIx->I2SCFGR = tmpreg; -} - -/** - * @brief Fills each SPI_InitStruct member with its default value. - * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized. - * @retval None - */ -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) -{ -/*--------------- Reset SPI init structure parameters values -----------------*/ - /* Initialize the SPI_Direction member */ - SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; - /* initialize the SPI_Mode member */ - SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; - /* initialize the SPI_DataSize member */ - SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; - /* Initialize the SPI_CPOL member */ - SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; - /* Initialize the SPI_CPHA member */ - SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; - /* Initialize the SPI_NSS member */ - SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; - /* Initialize the SPI_BaudRatePrescaler member */ - SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - /* Initialize the SPI_FirstBit member */ - SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; - /* Initialize the SPI_CRCPolynomial member */ - SPI_InitStruct->SPI_CRCPolynomial = 7; -} - -/** - * @brief Fills each I2S_InitStruct member with its default value. - * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) -{ -/*--------------- Reset I2S init structure parameters values -----------------*/ - /* Initialize the I2S_Mode member */ - I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; - - /* Initialize the I2S_Standard member */ - I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; - - /* Initialize the I2S_DataFormat member */ - I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; - - /* Initialize the I2S_MCLKOutput member */ - I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; - - /* Initialize the I2S_AudioFreq member */ - I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; - - /* Initialize the I2S_CPOL member */ - I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; -} - -/** - * @brief Enables or disables the specified SPI peripheral. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral */ - SPIx->CR1 |= CR1_SPE_Set; - } - else - { - /* Disable the selected SPI peripheral */ - SPIx->CR1 &= CR1_SPE_Reset; - } -} - -/** - * @brief Enables or disables the specified SPI peripheral (in I2S mode). - * @param SPIx: where x can be 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_23_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral (in I2S mode) */ - SPIx->I2SCFGR |= I2SCFGR_I2SE_Set; - } - else - { - /* Disable the selected SPI peripheral (in I2S mode) */ - SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset; - } -} - -/** - * @brief Enables or disables the specified SPI/I2S interrupts. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask - * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask - * @arg SPI_I2S_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified SPI/I2S interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) -{ - uint16_t itpos = 0, itmask = 0 ; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); - - /* Get the SPI/I2S IT index */ - itpos = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = (uint16_t)1 << (uint16_t)itpos; - - if (NewState != DISABLE) - { - /* Enable the selected SPI/I2S interrupt */ - SPIx->CR2 |= itmask; - } - else - { - /* Disable the selected SPI/I2S interrupt */ - SPIx->CR2 &= (uint16_t)~itmask; - } -} - -/** - * @brief Enables or disables the SPIx/I2Sx DMA interface. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request - * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request - * @param NewState: new state of the selected SPI/I2S DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); - if (NewState != DISABLE) - { - /* Enable the selected SPI/I2S DMA requests */ - SPIx->CR2 |= SPI_I2S_DMAReq; - } - else - { - /* Disable the selected SPI/I2S DMA requests */ - SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; - } -} - -/** - * @brief Transmits a Data through the SPIx/I2Sx peripheral. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @param Data : Data to be transmitted. - * @retval None - */ -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Write in the DR register the data to be sent */ - SPIx->DR = Data; -} - -/** - * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @retval The value of the received data. - */ -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Return the data in the DR register */ - return SPIx->DR; -} - -/** - * @brief Configures internally by software the NSS pin for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. - * This parameter can be one of the following values: - * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally - * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally - * @retval None - */ -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); - if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) - { - /* Set NSS pin internally by software */ - SPIx->CR1 |= SPI_NSSInternalSoft_Set; - } - else - { - /* Reset NSS pin internally by software */ - SPIx->CR1 &= SPI_NSSInternalSoft_Reset; - } -} - -/** - * @brief Enables or disables the SS output for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx SS output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI SS output */ - SPIx->CR2 |= CR2_SSOE_Set; - } - else - { - /* Disable the selected SPI SS output */ - SPIx->CR2 &= CR2_SSOE_Reset; - } -} - -/** - * @brief Configures the data size for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_DataSize: specifies the SPI data size. - * This parameter can be one of the following values: - * @arg SPI_DataSize_16b: Set data frame format to 16bit - * @arg SPI_DataSize_8b: Set data frame format to 8bit - * @retval None - */ -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DATASIZE(SPI_DataSize)); - /* Clear DFF bit */ - SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; - /* Set new DFF bit value */ - SPIx->CR1 |= SPI_DataSize; -} - -/** - * @brief Transmit the SPIx CRC value. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval None - */ -void SPI_TransmitCRC(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Enable the selected SPI CRC transmission */ - SPIx->CR1 |= CR1_CRCNext_Set; -} - -/** - * @brief Enables or disables the CRC value calculation of the transferred bytes. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx CRC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI CRC calculation */ - SPIx->CR1 |= CR1_CRCEN_Set; - } - else - { - /* Disable the selected SPI CRC calculation */ - SPIx->CR1 &= CR1_CRCEN_Reset; - } -} - -/** - * @brief Returns the transmit or the receive CRC register value for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_CRC: specifies the CRC register to be read. - * This parameter can be one of the following values: - * @arg SPI_CRC_Tx: Selects Tx CRC register - * @arg SPI_CRC_Rx: Selects Rx CRC register - * @retval The selected CRC register value.. - */ -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) -{ - uint16_t crcreg = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_CRC(SPI_CRC)); - if (SPI_CRC != SPI_CRC_Rx) - { - /* Get the Tx CRC register */ - crcreg = SPIx->TXCRCR; - } - else - { - /* Get the Rx CRC register */ - crcreg = SPIx->RXCRCR; - } - /* Return the selected CRC register */ - return crcreg; -} - -/** - * @brief Returns the CRC Polynomial register value for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval The CRC Polynomial register value. - */ -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Return the CRC polynomial register */ - return SPIx->CRCPR; -} - -/** - * @brief Selects the data transfer direction in bi-directional mode for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_Direction: specifies the data transfer direction in bi-directional mode. - * This parameter can be one of the following values: - * @arg SPI_Direction_Tx: Selects Tx transmission direction - * @arg SPI_Direction_Rx: Selects Rx receive direction - * @retval None - */ -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DIRECTION(SPI_Direction)); - if (SPI_Direction == SPI_Direction_Tx) - { - /* Set the Tx only mode */ - SPIx->CR1 |= SPI_Direction_Tx; - } - else - { - /* Set the Rx only mode */ - SPIx->CR1 &= SPI_Direction_Rx; - } -} - -/** - * @brief Checks whether the specified SPI/I2S flag is set or not. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. - * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. - * @arg SPI_I2S_FLAG_BSY: Busy flag. - * @arg SPI_I2S_FLAG_OVR: Overrun flag. - * @arg SPI_FLAG_MODF: Mode Fault flag. - * @arg SPI_FLAG_CRCERR: CRC Error flag. - * @arg I2S_FLAG_UDR: Underrun Error flag. - * @arg I2S_FLAG_CHSIDE: Channel Side flag. - * @retval The new state of SPI_I2S_FLAG (SET or RESET). - */ -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); - /* Check the status of the specified SPI/I2S flag */ - if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) - { - /* SPI_I2S_FLAG is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_FLAG is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) flag. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * @param SPI_I2S_FLAG: specifies the SPI flag to clear. - * This function clears only CRCERR flag. - * @note - * - OVR (OverRun error) flag is cleared by software sequence: a read - * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). - * - UDR (UnderRun error) flag is cleared by a read operation to - * SPI_SR register (SPI_I2S_GetFlagStatus()). - * - MODF (Mode Fault) flag is cleared by software sequence: a read/write - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a - * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). - * @retval None - */ -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); - - /* Clear the selected SPI CRC Error (CRCERR) flag */ - SPIx->SR = (uint16_t)~SPI_I2S_FLAG; -} - -/** - * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. - * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. - * @arg SPI_I2S_IT_OVR: Overrun interrupt. - * @arg SPI_IT_MODF: Mode Fault interrupt. - * @arg SPI_IT_CRCERR: CRC Error interrupt. - * @arg I2S_IT_UDR: Underrun Error interrupt. - * @retval The new state of SPI_I2S_IT (SET or RESET). - */ -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itpos = 0, itmask = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); - - /* Get the SPI/I2S IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Get the SPI/I2S IT mask */ - itmask = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = 0x01 << itmask; - - /* Get the SPI_I2S_IT enable bit status */ - enablestatus = (SPIx->CR2 & itmask) ; - - /* Check the status of the specified SPI/I2S interrupt */ - if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) - { - /* SPI_I2S_IT is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_IT is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_IT status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. - * This function clears only CRCERR interrupt pending bit. - * @note - * - OVR (OverRun Error) interrupt pending bit is cleared by software - * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) - * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). - * - UDR (UnderRun Error) interrupt pending bit is cleared by a read - * operation to SPI_SR register (SPI_I2S_GetITStatus()). - * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: - * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) - * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable - * the SPI). - * @retval None - */ -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - uint16_t itpos = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); - - /* Get the SPI IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ - SPIx->SR = (uint16_t)~itpos; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c deleted file mode 100644 index 81c8484e3..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c +++ /dev/null @@ -1,2890 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_tim.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the TIM firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_tim.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup TIM - * @brief TIM driver modules - * @{ - */ - -/** @defgroup TIM_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_Defines - * @{ - */ - -/* ---------------------- TIM registers bit mask ------------------------ */ -#define SMCR_ETR_Mask ((uint16_t)0x00FF) -#define CCMR_Offset ((uint16_t)0x0018) -#define CCER_CCE_Set ((uint16_t)0x0001) -#define CCER_CCNE_Set ((uint16_t)0x0004) - -/** - * @} - */ - -/** @defgroup TIM_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_FunctionPrototypes - * @{ - */ - -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -/** - * @} - */ - -/** @defgroup TIM_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the TIMx peripheral registers to their default reset values. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @retval None - */ -void TIM_DeInit(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - if (TIMx == TIM1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); - } - else if (TIMx == TIM2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); - } - else if (TIMx == TIM3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); - } - else if (TIMx == TIM4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); - } - else if (TIMx == TIM5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); - } - else if (TIMx == TIM6) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); - } - else if (TIMx == TIM7) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); - } - else if (TIMx == TIM8) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); - } - else if (TIMx == TIM9) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); - } - else if (TIMx == TIM10) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); - } - else if (TIMx == TIM11) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); - } - else if (TIMx == TIM12) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); - } - else if (TIMx == TIM13) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); - } - else if (TIMx == TIM14) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); - } - else if (TIMx == TIM15) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE); - } - else if (TIMx == TIM16) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE); - } - else - { - if (TIMx == TIM17) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE); - } - } -} - -/** - * @brief Initializes the TIMx Time Base Unit peripheral according to - * the specified parameters in the TIM_TimeBaseInitStruct. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef - * structure that contains the configuration information for the - * specified TIM peripheral. - * @retval None - */ -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - uint16_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); - assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); - - tmpcr1 = TIMx->CR1; - - if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)|| - (TIMx == TIM4) || (TIMx == TIM5)) - { - /* Select the Counter Mode */ - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; - } - - if((TIMx != TIM6) && (TIMx != TIM7)) - { - /* Set the clock division */ - tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD)); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; - } - - TIMx->CR1 = tmpcr1; - - /* Set the Autoreload value */ - TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; - - /* Set the Prescaler value */ - TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; - - if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17)) - { - /* Set the Repetition Counter value */ - TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; - } - - /* Generate an update event to reload the Prescaler and the Repetition counter - values immediately */ - TIMx->EGR = TIM_PSCReloadMode_Immediate; -} - -/** - * @brief Initializes the TIMx Channel1 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E); - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S)); - - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P)); - /* Set the Output Compare Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; - - /* Set the Output State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputState; - - if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| - (TIMx == TIM16)|| (TIMx == TIM17)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP)); - /* Set the Output N Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; - - /* Reset the Output N State */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE)); - /* Set the Output N State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputNState; - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N)); - - /* Set the Output Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; - /* Set the Output N Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel2 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select - * the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E)); - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)); - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P)); - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP)); - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); - - /* Reset the Output N State */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE)); - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N)); - - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel3 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E)); - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S)); - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P)); - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP)); - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); - /* Reset the Output N State */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE)); - - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N)); - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel4 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 2: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E)); - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S)); - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P)); - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - /* Reset the Output Compare IDLE State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4)); - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); - assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); - - if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || - (TIMx == TIM4) ||(TIMx == TIM5)) - { - assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); - } - else - { - assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity)); - } - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) - { - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) - { - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* TI3 Configuration */ - TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* TI4 Configuration */ - TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Configures the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct to measure an external PWM signal. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - uint16_t icoppositepolarity = TIM_ICPolarity_Rising; - uint16_t icoppositeselection = TIM_ICSelection_DirectTI; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* Select the Opposite Input Polarity */ - if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) - { - icoppositepolarity = TIM_ICPolarity_Falling; - } - else - { - icoppositepolarity = TIM_ICPolarity_Rising; - } - /* Select the Opposite Input */ - if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) - { - icoppositeselection = TIM_ICSelection_IndirectTI; - } - else - { - icoppositeselection = TIM_ICSelection_DirectTI; - } - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI2 Configuration */ - TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI1 Configuration */ - TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Configures the: Break feature, dead time, Lock level, the OSSI, - * the OSSR State and the AOE(automatic output enable). - * @param TIMx: where x can be 1 or 8 to select the TIM - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. - * @retval None - */ -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); - assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); - assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); - assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); - assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); - assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); - /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | - TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | - TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | - TIM_BDTRInitStruct->TIM_AutomaticOutput; -} - -/** - * @brief Fills each TIM_TimeBaseInitStruct member with its default value. - * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef - * structure which will be initialized. - * @retval None - */ -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - /* Set the default configuration */ - TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; - TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; - TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; - TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; -} - -/** - * @brief Fills each TIM_OCInitStruct member with its default value. - * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - /* Set the default configuration */ - TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; - TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; - TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; - TIM_OCInitStruct->TIM_Pulse = 0x0000; - TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; - TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; -} - -/** - * @brief Fills each TIM_ICInitStruct member with its default value. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Set the default configuration */ - TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; - TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; - TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; - TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; - TIM_ICInitStruct->TIM_ICFilter = 0x00; -} - -/** - * @brief Fills each TIM_BDTRInitStruct member with its default value. - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which - * will be initialized. - * @retval None - */ -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) -{ - /* Set the default configuration */ - TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; - TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; - TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; - TIM_BDTRInitStruct->TIM_DeadTime = 0x00; - TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; - TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; - TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; -} - -/** - * @brief Enables or disables the specified TIM peripheral. - * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral. - * @param NewState: new state of the TIMx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TIM Counter */ - TIMx->CR1 |= TIM_CR1_CEN; - } - else - { - /* Disable the TIM Counter */ - TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN)); - } -} - -/** - * @brief Enables or disables the TIM peripheral Main Outputs. - * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral. - * @param NewState: new state of the TIM peripheral Main Outputs. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the TIM Main Output */ - TIMx->BDTR |= TIM_BDTR_MOE; - } - else - { - /* Disable the TIM Main Output */ - TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE)); - } -} - -/** - * @brief Enables or disables the specified TIM interrupts. - * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral. - * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * @note - * - TIM6 and TIM7 can only generate an update interrupt. - * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, - * TIM_IT_CC2 or TIM_IT_Trigger. - * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. - * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. - * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. - * @param NewState: new state of the TIM interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IT(TIM_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Interrupt sources */ - TIMx->DIER |= TIM_IT; - } - else - { - /* Disable the Interrupt sources */ - TIMx->DIER &= (uint16_t)~TIM_IT; - } -} - -/** - * @brief Configures the TIMx event to be generate by software. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_EventSource: specifies the event source. - * This parameter can be one or more of the following values: - * @arg TIM_EventSource_Update: Timer update Event source - * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EventSource_COM: Timer COM event source - * @arg TIM_EventSource_Trigger: Timer Trigger Event source - * @arg TIM_EventSource_Break: Timer Break event source - * @note - * - TIM6 and TIM7 can only generate an update event. - * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. - * @retval None - */ -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); - - /* Set the event sources */ - TIMx->EGR = TIM_EventSource; -} - -/** - * @brief Configures the TIMx's DMA interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select - * the TIM peripheral. - * @param TIM_DMABase: DMA Base address. - * This parameter can be one of the following values: - * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR, - * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR, - * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, - * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, - * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2, - * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR, - * TIM_DMABase_DCR. - * @param TIM_DMABurstLength: DMA Burst length. - * This parameter can be one value between: - * TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. - * @retval None - */ -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); - assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); - /* Set the DMA Base and the DMA Burst Length */ - TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; -} - -/** - * @brief Enables or disables the TIMx's DMA Requests. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17 - * to select the TIM peripheral. - * @param TIM_DMASource: specifies the DMA Request sources. - * This parameter can be any combination of the following values: - * @arg TIM_DMA_Update: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_Trigger: TIM Trigger DMA source - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST9_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA sources */ - TIMx->DIER |= TIM_DMASource; - } - else - { - /* Disable the DMA sources */ - TIMx->DIER &= (uint16_t)~TIM_DMASource; - } -} - -/** - * @brief Configures the TIMx internal Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 - * to select the TIM peripheral. - * @retval None - */ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* Disable slave mode to clock the prescaler directly with the internal clock */ - TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); -} - -/** - * @brief Configures the TIMx Internal Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_ITRSource: Trigger source. - * This parameter can be one of the following values: - * @param TIM_TS_ITR0: Internal Trigger 0 - * @param TIM_TS_ITR1: Internal Trigger 1 - * @param TIM_TS_ITR2: Internal Trigger 2 - * @param TIM_TS_ITR3: Internal Trigger 3 - * @retval None - */ -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); - /* Select the Internal Trigger */ - TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the TIMx Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_TIxExternalCLKSource: Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector - * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 - * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 - * @param TIM_ICPolarity: specifies the TIx Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param ICFilter : specifies the filter value. - * This parameter must be a value between 0x0 and 0xF. - * @retval None - */ -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); - assert_param(IS_TIM_IC_FILTER(ICFilter)); - /* Configure the Timer Input Clock Source */ - if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) - { - TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - else - { - TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - /* Select the Trigger source */ - TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the External clock Mode1 - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the SMS Bits */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); - /* Select the External clock mode1 */ - tmpsmcr |= TIM_SlaveMode_External1; - /* Select the Trigger selection : ETRF */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); - tmpsmcr |= TIM_TS_ETRF; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the External clock Mode2 - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - /* Enable the External clock mode2 */ - TIMx->SMCR |= TIM_SMCR_ECE; -} - -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - tmpsmcr = TIMx->SMCR; - /* Reset the ETR Bits */ - tmpsmcr &= SMCR_ETR_Mask; - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the TIMx Prescaler. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param Prescaler: specifies the Prescaler Register value - * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode - * This parameter can be one of the following values: - * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. - * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately. - * @retval None - */ -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); - /* Set the Prescaler value */ - TIMx->PSC = Prescaler; - /* Set or reset the UG Bit */ - TIMx->EGR = TIM_PSCReloadMode; -} - -/** - * @brief Specifies the TIMx Counter Mode to be used. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_CounterMode: specifies the Counter Mode to be used - * This parameter can be one of the following values: - * @arg TIM_CounterMode_Up: TIM Up Counting Mode - * @arg TIM_CounterMode_Down: TIM Down Counting Mode - * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 - * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 - * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 - * @retval None - */ -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) -{ - uint16_t tmpcr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); - tmpcr1 = TIMx->CR1; - /* Reset the CMS and DIR Bits */ - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); - /* Set the Counter Mode */ - tmpcr1 |= TIM_CounterMode; - /* Write to TIMx CR1 register */ - TIMx->CR1 = tmpcr1; -} - -/** - * @brief Selects the Input Trigger source - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_InputTriggerSource: The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input - * @retval None - */ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - uint16_t tmpsmcr = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the TS Bits */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); - /* Set the Input Trigger source */ - tmpsmcr |= TIM_InputTriggerSource; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the TIMx Encoder Interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. - * This parameter can be one of the following values: - * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. - * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. - * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending - * on the level of the other input. - * @param TIM_IC1Polarity: specifies the IC1 Polarity - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @param TIM_IC2Polarity: specifies the IC2 Polarity - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @retval None - */ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) -{ - uint16_t tmpsmcr = 0; - uint16_t tmpccmr1 = 0; - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST5_PERIPH(TIMx)); - assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Set the encoder Mode */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); - tmpsmcr |= TIM_EncoderMode; - - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S))); - tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; - - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P))); - tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Forces the TIMx output 1 waveform to active or inactive level. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC1REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. - * @retval None - */ -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1M Bits */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M); - /* Configure The Forced output Mode */ - tmpccmr1 |= TIM_ForcedAction; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 2 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC2REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. - * @retval None - */ -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2M Bits */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M); - /* Configure The Forced output Mode */ - tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 3 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC3REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. - * @retval None - */ -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC1M Bits */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M); - /* Configure The Forced output Mode */ - tmpccmr2 |= TIM_ForcedAction; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Forces the TIMx output 4 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC4REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. - * @retval None - */ -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC2M Bits */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M); - /* Configure The Forced output Mode */ - tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables TIMx peripheral Preload register on ARR. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param NewState: new state of the TIMx peripheral Preload register - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the ARR Preload Bit */ - TIMx->CR1 |= TIM_CR1_ARPE; - } - else - { - /* Reset the ARR Preload Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE); - } -} - -/** - * @brief Selects the TIM peripheral Commutation event. - * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral - * @param NewState: new state of the Commutation event. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the COM Bit */ - TIMx->CR2 |= TIM_CR2_CCUS; - } - else - { - /* Reset the COM Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS); - } -} - -/** - * @brief Selects the TIMx peripheral Capture Compare DMA source. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select - * the TIM peripheral. - * @param NewState: new state of the Capture Compare DMA source - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the CCDS Bit */ - TIMx->CR2 |= TIM_CR2_CCDS; - } - else - { - /* Reset the CCDS Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS); - } -} - -/** - * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15 - * to select the TIMx peripheral - * @param NewState: new state of the Capture Compare Preload Control bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST5_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the CCPC Bit */ - TIMx->CR2 |= TIM_CR2_CCPC; - } - else - { - /* Reset the CCPC Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC); - } -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR1. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1PE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= TIM_OCPreload; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR2. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select - * the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2PE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR3. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3PE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= TIM_OCPreload; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR4. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4PE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 1 Fast feature. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1FE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= TIM_OCFast; - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 2 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select - * the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2FE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 3 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3FE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= TIM_OCFast; - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 4 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4FE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF1 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1CE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= TIM_OCClear; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF2 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2CE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF3 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3CE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= TIM_OCClear; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF4 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4CE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx channel 1 polarity. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC1 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - tmpccer = TIMx->CCER; - /* Set or Reset the CC1P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P); - tmpccer |= TIM_OCPolarity; - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 1N polarity. - * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC1N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC1NP Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP); - tmpccer |= TIM_OCNPolarity; - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 2 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC2 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - tmpccer = TIMx->CCER; - /* Set or Reset the CC2P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 4); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 2N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC2N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC2NP Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 3 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC3 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - tmpccer = TIMx->CCER; - /* Set or Reset the CC3P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 8); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 3N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC3N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC3NP Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 4 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC4 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - tmpccer = TIMx->CCER; - /* Set or Reset the CC4P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 12); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. - * @retval None - */ -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCX(TIM_CCx)); - - tmp = CCER_CCE_Set << TIM_Channel; - - /* Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t)~ tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel xN. - * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. - * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. - * @retval None - */ -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCXN(TIM_CCxN)); - - tmp = CCER_CCNE_Set << TIM_Channel; - - /* Reset the CCxNE Bit */ - TIMx->CCER &= (uint16_t) ~tmp; - - /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); -} - -/** - * @brief Selects the TIM Output Compare Mode. - * @note This function disables the selected channel before changing the Output - * Compare Mode. - * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_OCMode: specifies the TIM Output Compare Mode. - * This parameter can be one of the following values: - * @arg TIM_OCMode_Timing - * @arg TIM_OCMode_Active - * @arg TIM_OCMode_Toggle - * @arg TIM_OCMode_PWM1 - * @arg TIM_OCMode_PWM2 - * @arg TIM_ForcedAction_Active - * @arg TIM_ForcedAction_InActive - * @retval None - */ -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) -{ - uint32_t tmp = 0; - uint16_t tmp1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_OCM(TIM_OCMode)); - - tmp = (uint32_t) TIMx; - tmp += CCMR_Offset; - - tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; - - /* Disable the Channel: Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t) ~tmp1; - - if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) - { - tmp += (TIM_Channel>>1); - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= TIM_OCMode; - } - else - { - tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M); - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); - } -} - -/** - * @brief Enables or Disables the TIMx Update event. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param NewState: new state of the TIMx UDIS bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the Update Disable Bit */ - TIMx->CR1 |= TIM_CR1_UDIS; - } - else - { - /* Reset the Update Disable Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS); - } -} - -/** - * @brief Configures the TIMx Update Request Interrupt source. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_UpdateSource: specifies the Update source. - * This parameter can be one of the following values: - * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow - or the setting of UG bit, or an update generation - through the slave mode controller. - * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow. - * @retval None - */ -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); - if (TIM_UpdateSource != TIM_UpdateSource_Global) - { - /* Set the URS Bit */ - TIMx->CR1 |= TIM_CR1_URS; - } - else - { - /* Reset the URS Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS); - } -} - -/** - * @brief Enables or disables the TIMx's Hall sensor interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param NewState: new state of the TIMx Hall sensor interface. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the TI1S Bit */ - TIMx->CR2 |= TIM_CR2_TI1S; - } - else - { - /* Reset the TI1S Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S); - } -} - -/** - * @brief Selects the TIMx's One Pulse Mode. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_OPMode: specifies the OPM Mode to be used. - * This parameter can be one of the following values: - * @arg TIM_OPMode_Single - * @arg TIM_OPMode_Repetitive - * @retval None - */ -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); - /* Reset the OPM Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM); - /* Configure the OPM Mode */ - TIMx->CR1 |= TIM_OPMode; -} - -/** - * @brief Selects the TIMx Trigger Output Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_TRGOSource: specifies the Trigger Output source. - * This paramter can be one of the following values: - * - * - For all TIMx - * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO). - * - * - For all TIMx except TIM6 and TIM7 - * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag - * is to be set, as soon as a capture or compare match occurs (TRGO). - * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO). - * - * @retval None - */ -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST7_PERIPH(TIMx)); - assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); - /* Reset the MMS Bits */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS); - /* Select the TRGO source */ - TIMx->CR2 |= TIM_TRGOSource; -} - -/** - * @brief Selects the TIMx Slave Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_SlaveMode: specifies the Timer Slave Mode. - * This parameter can be one of the following values: - * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes - * the counter and triggers an update of the registers. - * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high. - * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI. - * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter. - * @retval None - */ -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); - /* Reset the SMS Bits */ - TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS); - /* Select the Slave Mode */ - TIMx->SMCR |= TIM_SlaveMode; -} - -/** - * @brief Sets or Resets the TIMx Master/Slave Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. - * This parameter can be one of the following values: - * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer - * and its slaves (through TRGO). - * @arg TIM_MasterSlaveMode_Disable: No action - * @retval None - */ -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); - /* Reset the MSM Bit */ - TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM); - - /* Set or Reset the MSM Bit */ - TIMx->SMCR |= TIM_MasterSlaveMode; -} - -/** - * @brief Sets the TIMx Counter Register value - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param Counter: specifies the Counter register new value. - * @retval None - */ -void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - /* Set the Counter Register value */ - TIMx->CNT = Counter; -} - -/** - * @brief Sets the TIMx Autoreload Register value - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param Autoreload: specifies the Autoreload register new value. - * @retval None - */ -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - /* Set the Autoreload Register value */ - TIMx->ARR = Autoreload; -} - -/** - * @brief Sets the TIMx Capture Compare1 Register value - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param Compare1: specifies the Capture Compare1 register new value. - * @retval None - */ -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - /* Set the Capture Compare1 Register value */ - TIMx->CCR1 = Compare1; -} - -/** - * @brief Sets the TIMx Capture Compare2 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param Compare2: specifies the Capture Compare2 register new value. - * @retval None - */ -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* Set the Capture Compare2 Register value */ - TIMx->CCR2 = Compare2; -} - -/** - * @brief Sets the TIMx Capture Compare3 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare3: specifies the Capture Compare3 register new value. - * @retval None - */ -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* Set the Capture Compare3 Register value */ - TIMx->CCR3 = Compare3; -} - -/** - * @brief Sets the TIMx Capture Compare4 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare4: specifies the Capture Compare4 register new value. - * @retval None - */ -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* Set the Capture Compare4 Register value */ - TIMx->CCR4 = Compare4; -} - -/** - * @brief Sets the TIMx Input Capture 1 prescaler. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - /* Reset the IC1PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC); - /* Set the IC1PSC value */ - TIMx->CCMR1 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 2 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - /* Reset the IC2PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC); - /* Set the IC2PSC value */ - TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); -} - -/** - * @brief Sets the TIMx Input Capture 3 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - /* Reset the IC3PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC); - /* Set the IC3PSC value */ - TIMx->CCMR2 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 4 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - /* Reset the IC4PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC); - /* Set the IC4PSC value */ - TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); -} - -/** - * @brief Sets the TIMx Clock Division value. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select - * the TIM peripheral. - * @param TIM_CKD: specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CKD_DIV1: TDTS = Tck_tim - * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim - * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim - * @retval None - */ -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_CKD_DIV(TIM_CKD)); - /* Reset the CKD Bits */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD); - /* Set the CKD value */ - TIMx->CR1 |= TIM_CKD; -} - -/** - * @brief Gets the TIMx Input Capture 1 value. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @retval Capture Compare 1 Register value. - */ -uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - /* Get the Capture 1 Register value */ - return TIMx->CCR1; -} - -/** - * @brief Gets the TIMx Input Capture 2 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @retval Capture Compare 2 Register value. - */ -uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* Get the Capture 2 Register value */ - return TIMx->CCR2; -} - -/** - * @brief Gets the TIMx Input Capture 3 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @retval Capture Compare 3 Register value. - */ -uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* Get the Capture 3 Register value */ - return TIMx->CCR3; -} - -/** - * @brief Gets the TIMx Input Capture 4 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @retval Capture Compare 4 Register value. - */ -uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* Get the Capture 4 Register value */ - return TIMx->CCR4; -} - -/** - * @brief Gets the TIMx Counter value. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @retval Counter Register value. - */ -uint16_t TIM_GetCounter(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - /* Get the Counter Register value */ - return TIMx->CNT; -} - -/** - * @brief Gets the TIMx Prescaler value. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @retval Prescaler Register value. - */ -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - /* Get the Prescaler Register value */ - return TIMx->PSC; -} - -/** - * @brief Checks whether the specified TIM flag is set or not. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag - * @note - * - TIM6 and TIM7 can have only one update flag. - * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, - * TIM_FLAG_CC2 or TIM_FLAG_Trigger. - * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. - * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. - * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. - * @retval The new state of TIM_FLAG (SET or RESET). - */ -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); - - if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's pending flags. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag - * @note - * - TIM6 and TIM7 can have only one update flag. - * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, - * TIM_FLAG_CC2 or TIM_FLAG_Trigger. - * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. - * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. - * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. - * @retval None - */ -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG)); - - /* Clear the flags */ - TIMx->SR = (uint16_t)~TIM_FLAG; -} - -/** - * @brief Checks whether the TIM interrupt has occurred or not. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_IT: specifies the TIM interrupt source to check. - * This parameter can be one of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * @note - * - TIM6 and TIM7 can generate only an update interrupt. - * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, - * TIM_IT_CC2 or TIM_IT_Trigger. - * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. - * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. - * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. - * @retval The new state of the TIM_IT(SET or RESET). - */ -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itstatus = 0x0, itenable = 0x0; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_IT(TIM_IT)); - - itstatus = TIMx->SR & TIM_IT; - - itenable = TIMx->DIER & TIM_IT; - if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's interrupt pending bits. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_IT: specifies the pending bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM1 update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * @note - * - TIM6 and TIM7 can generate only an update interrupt. - * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, - * TIM_IT_CC2 or TIM_IT_Trigger. - * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. - * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. - * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. - * @retval None - */ -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IT(TIM_IT)); - /* Clear the IT pending Bit */ - TIMx->SR = (uint16_t)~TIM_IT; -} - -/** - * @brief Configure the TI1 as Input. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0; - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E); - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - /* Select the Input and set the filter */ - tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F))); - tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || - (TIMx == TIM4) ||(TIMx == TIM5)) - { - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); - } - else - { - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); - } - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E); - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 4); - /* Select the Input and set the filter */ - tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F))); - tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); - tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); - - if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || - (TIMx == TIM4) ||(TIMx == TIM5)) - { - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); - } - else - { - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E); - } - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E); - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 8); - /* Select the Input and set the filter */ - tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F))); - tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || - (TIMx == TIM4) ||(TIMx == TIM5)) - { - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); - } - else - { - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E); - } - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E); - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 12); - /* Select the Input and set the filter */ - tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F))); - tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); - tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); - - if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || - (TIMx == TIM4) ||(TIMx == TIM5)) - { - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); - } - else - { - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E); - } - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c deleted file mode 100644 index a3f16f15e..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c +++ /dev/null @@ -1,1058 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_usart.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the USART firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_usart.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup USART - * @brief USART driver modules - * @{ - */ - -/** @defgroup USART_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Private_Defines - * @{ - */ - -#define CR1_UE_Set ((uint16_t)0x2000) /*!< USART Enable Mask */ -#define CR1_UE_Reset ((uint16_t)0xDFFF) /*!< USART Disable Mask */ - -#define CR1_WAKE_Mask ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */ - -#define CR1_RWU_Set ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */ -#define CR1_RWU_Reset ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */ -#define CR1_SBK_Set ((uint16_t)0x0001) /*!< USART Break Character send Mask */ -#define CR1_CLEAR_Mask ((uint16_t)0xE9F3) /*!< USART CR1 Mask */ -#define CR2_Address_Mask ((uint16_t)0xFFF0) /*!< USART address Mask */ - -#define CR2_LINEN_Set ((uint16_t)0x4000) /*!< USART LIN Enable Mask */ -#define CR2_LINEN_Reset ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */ - -#define CR2_LBDL_Mask ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */ -#define CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /*!< USART CR2 STOP Bits Mask */ -#define CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /*!< USART CR2 Clock Mask */ - -#define CR3_SCEN_Set ((uint16_t)0x0020) /*!< USART SC Enable Mask */ -#define CR3_SCEN_Reset ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */ - -#define CR3_NACK_Set ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */ -#define CR3_NACK_Reset ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */ - -#define CR3_HDSEL_Set ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */ -#define CR3_HDSEL_Reset ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */ - -#define CR3_IRLP_Mask ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */ -#define CR3_CLEAR_Mask ((uint16_t)0xFCFF) /*!< USART CR3 Mask */ - -#define CR3_IREN_Set ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */ -#define CR3_IREN_Reset ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */ -#define GTPR_LSB_Mask ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */ -#define GTPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */ -#define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */ - -/* USART OverSampling-8 Mask */ -#define CR1_OVER8_Set ((u16)0x8000) /* USART OVER8 mode Enable Mask */ -#define CR1_OVER8_Reset ((u16)0x7FFF) /* USART OVER8 mode Disable Mask */ - -/* USART One Bit Sampling Mask */ -#define CR3_ONEBITE_Set ((u16)0x0800) /* USART ONEBITE mode Enable Mask */ -#define CR3_ONEBITE_Reset ((u16)0xF7FF) /* USART ONEBITE mode Disable Mask */ - -/** - * @} - */ - -/** @defgroup USART_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the USARTx peripheral registers to their default reset values. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @retval None - */ -void USART_DeInit(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - if (USARTx == USART1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); - } - else if (USARTx == USART2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); - } - else if (USARTx == USART3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); - } - else if (USARTx == UART4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); - } - else - { - if (USARTx == UART5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); - } - } -} - -/** - * @brief Initializes the USARTx peripheral according to the specified - * parameters in the USART_InitStruct . - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - * that contains the configuration information for the specified USART - * peripheral. - * @retval None - */ -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) -{ - uint32_t tmpreg = 0x00, apbclock = 0x00; - uint32_t integerdivider = 0x00; - uint32_t fractionaldivider = 0x00; - uint32_t usartxbase = 0; - RCC_ClocksTypeDef RCC_ClocksStatus; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); - assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); - assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); - assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); - assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); - assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); - /* The hardware flow control is available only for USART1, USART2 and USART3 */ - if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - usartxbase = (uint32_t)USARTx; - -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - /* Clear STOP[13:12] bits */ - tmpreg &= CR2_STOP_CLEAR_Mask; - /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ - /* Set STOP[13:12] bits according to USART_StopBits value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; - - /* Write to USART CR2 */ - USARTx->CR2 = (uint16_t)tmpreg; - -/*---------------------------- USART CR1 Configuration -----------------------*/ - tmpreg = USARTx->CR1; - /* Clear M, PCE, PS, TE and RE bits */ - tmpreg &= CR1_CLEAR_Mask; - /* Configure the USART Word Length, Parity and mode ----------------------- */ - /* Set the M bits according to USART_WordLength value */ - /* Set PCE and PS bits according to USART_Parity value */ - /* Set TE and RE bits according to USART_Mode value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | - USART_InitStruct->USART_Mode; - /* Write to USART CR1 */ - USARTx->CR1 = (uint16_t)tmpreg; - -/*---------------------------- USART CR3 Configuration -----------------------*/ - tmpreg = USARTx->CR3; - /* Clear CTSE and RTSE bits */ - tmpreg &= CR3_CLEAR_Mask; - /* Configure the USART HFC -------------------------------------------------*/ - /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ - tmpreg |= USART_InitStruct->USART_HardwareFlowControl; - /* Write to USART CR3 */ - USARTx->CR3 = (uint16_t)tmpreg; - -/*---------------------------- USART BRR Configuration -----------------------*/ - /* Configure the USART Baud Rate -------------------------------------------*/ - RCC_GetClocksFreq(&RCC_ClocksStatus); - if (usartxbase == USART1_BASE) - { - apbclock = RCC_ClocksStatus.PCLK2_Frequency; - } - else - { - apbclock = RCC_ClocksStatus.PCLK1_Frequency; - } - - /* Determine the integer part */ - if ((USARTx->CR1 & CR1_OVER8_Set) != 0) - { - /* Integer part computing in case Oversampling mode is 8 Samples */ - integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); - } - else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ - { - /* Integer part computing in case Oversampling mode is 16 Samples */ - integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); - } - tmpreg = (integerdivider / 100) << 4; - - /* Determine the fractional part */ - fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); - - /* Implement the fractional part in the register */ - if ((USARTx->CR1 & CR1_OVER8_Set) != 0) - { - tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); - } - else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ - { - tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); - } - - /* Write to USART BRR */ - USARTx->BRR = (uint16_t)tmpreg; -} - -/** - * @brief Fills each USART_InitStruct member with its default value. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - * which will be initialized. - * @retval None - */ -void USART_StructInit(USART_InitTypeDef* USART_InitStruct) -{ - /* USART_InitStruct members default value */ - USART_InitStruct->USART_BaudRate = 9600; - USART_InitStruct->USART_WordLength = USART_WordLength_8b; - USART_InitStruct->USART_StopBits = USART_StopBits_1; - USART_InitStruct->USART_Parity = USART_Parity_No ; - USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; -} - -/** - * @brief Initializes the USARTx peripheral Clock according to the - * specified parameters in the USART_ClockInitStruct . - * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef - * structure that contains the configuration information for the specified - * USART peripheral. - * @note The Smart Card and Synchronous modes are not available for UART4 and UART5. - * @retval None - */ -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - uint32_t tmpreg = 0x00; - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); - assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); - assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); - assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); - -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - /* Clear CLKEN, CPOL, CPHA and LBCL bits */ - tmpreg &= CR2_CLOCK_CLEAR_Mask; - /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ - /* Set CLKEN bit according to USART_Clock value */ - /* Set CPOL bit according to USART_CPOL value */ - /* Set CPHA bit according to USART_CPHA value */ - /* Set LBCL bit according to USART_LastBit value */ - tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | - USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; - /* Write to USART CR2 */ - USARTx->CR2 = (uint16_t)tmpreg; -} - -/** - * @brief Fills each USART_ClockInitStruct member with its default value. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef - * structure which will be initialized. - * @retval None - */ -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - /* USART_ClockInitStruct members default value */ - USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; - USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; - USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; - USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; -} - -/** - * @brief Enables or disables the specified USART peripheral. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USARTx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected USART by setting the UE bit in the CR1 register */ - USARTx->CR1 |= CR1_UE_Set; - } - else - { - /* Disable the selected USART by clearing the UE bit in the CR1 register */ - USARTx->CR1 &= CR1_UE_Reset; - } -} - -/** - * @brief Enables or disables the specified USART interrupts. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Transmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @param NewState: new state of the specified USARTx interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) -{ - uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; - uint32_t usartxbase = 0x00; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CONFIG_IT(USART_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - usartxbase = (uint32_t)USARTx; - - /* Get the USART register index */ - usartreg = (((uint8_t)USART_IT) >> 0x05); - - /* Get the interrupt position */ - itpos = USART_IT & IT_Mask; - itmask = (((uint32_t)0x01) << itpos); - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - usartxbase += 0x0C; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - usartxbase += 0x10; - } - else /* The IT is in CR3 register */ - { - usartxbase += 0x14; - } - if (NewState != DISABLE) - { - *(__IO uint32_t*)usartxbase |= itmask; - } - else - { - *(__IO uint32_t*)usartxbase &= ~itmask; - } -} - -/** - * @brief Enables or disables the USART’s DMA interface. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_DMAReq: specifies the DMA request. - * This parameter can be any combination of the following values: - * @arg USART_DMAReq_Tx: USART DMA transmit request - * @arg USART_DMAReq_Rx: USART DMA receive request - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @note The DMA mode is not available for UART5 except in the STM32 - * High density value line devices(STM32F10X_HD_VL). - * @retval None - */ -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DMAREQ(USART_DMAReq)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the DMA transfer for selected requests by setting the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 |= USART_DMAReq; - } - else - { - /* Disable the DMA transfer for selected requests by clearing the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 &= (uint16_t)~USART_DMAReq; - } -} - -/** - * @brief Sets the address of the USART node. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_Address: Indicates the address of the USART node. - * @retval None - */ -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_ADDRESS(USART_Address)); - - /* Clear the USART address */ - USARTx->CR2 &= CR2_Address_Mask; - /* Set the USART address node */ - USARTx->CR2 |= USART_Address; -} - -/** - * @brief Selects the USART WakeUp method. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_WakeUp: specifies the USART wakeup method. - * This parameter can be one of the following values: - * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection - * @arg USART_WakeUp_AddressMark: WakeUp by an address mark - * @retval None - */ -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_WAKEUP(USART_WakeUp)); - - USARTx->CR1 &= CR1_WAKE_Mask; - USARTx->CR1 |= USART_WakeUp; -} - -/** - * @brief Determines if the USART is in mute mode or not. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USART mute mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ - USARTx->CR1 |= CR1_RWU_Set; - } - else - { - /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ - USARTx->CR1 &= CR1_RWU_Reset; - } -} - -/** - * @brief Sets the USART LIN Break detection length. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_LINBreakDetectLength: specifies the LIN break detection length. - * This parameter can be one of the following values: - * @arg USART_LINBreakDetectLength_10b: 10-bit break detection - * @arg USART_LINBreakDetectLength_11b: 11-bit break detection - * @retval None - */ -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); - - USARTx->CR2 &= CR2_LBDL_Mask; - USARTx->CR2 |= USART_LINBreakDetectLength; -} - -/** - * @brief Enables or disables the USART’s LIN mode. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USART LIN mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - USARTx->CR2 |= CR2_LINEN_Set; - } - else - { - /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ - USARTx->CR2 &= CR2_LINEN_Reset; - } -} - -/** - * @brief Transmits single data through the USARTx peripheral. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param Data: the data to transmit. - * @retval None - */ -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DATA(Data)); - - /* Transmit Data */ - USARTx->DR = (Data & (uint16_t)0x01FF); -} - -/** - * @brief Returns the most recent received data by the USARTx peripheral. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @retval The received data. - */ -uint16_t USART_ReceiveData(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Receive Data */ - return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); -} - -/** - * @brief Transmits break characters. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @retval None - */ -void USART_SendBreak(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Send break characters */ - USARTx->CR1 |= CR1_SBK_Set; -} - -/** - * @brief Sets the specified USART guard time. - * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. - * @param USART_GuardTime: specifies the guard time. - * @note The guard time bits are not available for UART4 and UART5. - * @retval None - */ -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - - /* Clear the USART Guard time */ - USARTx->GTPR &= GTPR_LSB_Mask; - /* Set the USART guard time */ - USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); -} - -/** - * @brief Sets the system clock prescaler. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_Prescaler: specifies the prescaler clock. - * @note The function is used for IrDA mode with UART4 and UART5. - * @retval None - */ -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Clear the USART prescaler */ - USARTx->GTPR &= GTPR_MSB_Mask; - /* Set the USART prescaler */ - USARTx->GTPR |= USART_Prescaler; -} - -/** - * @brief Enables or disables the USART’s Smart Card mode. - * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. - * @param NewState: new state of the Smart Card mode. - * This parameter can be: ENABLE or DISABLE. - * @note The Smart Card mode is not available for UART4 and UART5. - * @retval None - */ -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the SC mode by setting the SCEN bit in the CR3 register */ - USARTx->CR3 |= CR3_SCEN_Set; - } - else - { - /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ - USARTx->CR3 &= CR3_SCEN_Reset; - } -} - -/** - * @brief Enables or disables NACK transmission. - * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. - * @param NewState: new state of the NACK transmission. - * This parameter can be: ENABLE or DISABLE. - * @note The Smart Card mode is not available for UART4 and UART5. - * @retval None - */ -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ - USARTx->CR3 |= CR3_NACK_Set; - } - else - { - /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ - USARTx->CR3 &= CR3_NACK_Reset; - } -} - -/** - * @brief Enables or disables the USART’s Half Duplex communication. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USART Communication. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - USARTx->CR3 |= CR3_HDSEL_Set; - } - else - { - /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ - USARTx->CR3 &= CR3_HDSEL_Reset; - } -} - - -/** - * @brief Enables or disables the USART's 8x oversampling mode. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USART one bit sampling method. - * This parameter can be: ENABLE or DISABLE. - * @note - * This function has to be called before calling USART_Init() - * function in order to have correct baudrate Divider value. - * @retval None - */ -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ - USARTx->CR1 |= CR1_OVER8_Set; - } - else - { - /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ - USARTx->CR1 &= CR1_OVER8_Reset; - } -} - -/** - * @brief Enables or disables the USART's one bit sampling method. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USART one bit sampling method. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ - USARTx->CR3 |= CR3_ONEBITE_Set; - } - else - { - /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */ - USARTx->CR3 &= CR3_ONEBITE_Reset; - } -} - -/** - * @brief Configures the USART's IrDA interface. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_IrDAMode: specifies the IrDA mode. - * This parameter can be one of the following values: - * @arg USART_IrDAMode_LowPower - * @arg USART_IrDAMode_Normal - * @retval None - */ -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); - - USARTx->CR3 &= CR3_IRLP_Mask; - USARTx->CR3 |= USART_IrDAMode; -} - -/** - * @brief Enables or disables the USART's IrDA interface. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the IrDA mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ - USARTx->CR3 |= CR3_IREN_Set; - } - else - { - /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ - USARTx->CR3 &= CR3_IREN_Reset; - } -} - -/** - * @brief Checks whether the specified USART flag is set or not. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) - * @arg USART_FLAG_LBD: LIN Break detection flag - * @arg USART_FLAG_TXE: Transmit data register empty flag - * @arg USART_FLAG_TC: Transmission Complete flag - * @arg USART_FLAG_RXNE: Receive data register not empty flag - * @arg USART_FLAG_IDLE: Idle Line detection flag - * @arg USART_FLAG_ORE: OverRun Error flag - * @arg USART_FLAG_NE: Noise Error flag - * @arg USART_FLAG_FE: Framing Error flag - * @arg USART_FLAG_PE: Parity Error flag - * @retval The new state of USART_FLAG (SET or RESET). - */ -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_FLAG(USART_FLAG)); - /* The CTS flag is not available for UART4 and UART5 */ - if (USART_FLAG == USART_FLAG_CTS) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the USARTx's pending flags. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). - * @arg USART_FLAG_LBD: LIN Break detection flag. - * @arg USART_FLAG_TC: Transmission Complete flag. - * @arg USART_FLAG_RXNE: Receive data register not empty flag. - * - * @note - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) flags are cleared by software - * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) - * followed by a read operation to USART_DR register (USART_ReceiveData()). - * - RXNE flag can be also cleared by a read to the USART_DR register - * (USART_ReceiveData()). - * - TC flag can be also cleared by software sequence: a read operation to - * USART_SR register (USART_GetFlagStatus()) followed by a write operation - * to USART_DR register (USART_SendData()). - * - TXE flag is cleared only by a write to the USART_DR register - * (USART_SendData()). - * @retval None - */ -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); - /* The CTS flag is not available for UART4 and UART5 */ - if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - USARTx->SR = (uint16_t)~USART_FLAG; -} - -/** - * @brief Checks whether the specified USART interrupt has occurred or not. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_IT: specifies the USART interrupt source to check. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Tansmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_ORE: OverRun Error interrupt - * @arg USART_IT_NE: Noise Error interrupt - * @arg USART_IT_FE: Framing Error interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @retval The new state of USART_IT (SET or RESET). - */ -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) -{ - uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_GET_IT(USART_IT)); - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - /* Get the USART register index */ - usartreg = (((uint8_t)USART_IT) >> 0x05); - /* Get the interrupt position */ - itmask = USART_IT & IT_Mask; - itmask = (uint32_t)0x01 << itmask; - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - itmask &= USARTx->CR1; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - itmask &= USARTx->CR2; - } - else /* The IT is in CR3 register */ - { - itmask &= USARTx->CR3; - } - - bitpos = USART_IT >> 0x08; - bitpos = (uint32_t)0x01 << bitpos; - bitpos &= USARTx->SR; - if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/** - * @brief Clears the USARTx's interrupt pending bits. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_IT: specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TC: Transmission complete interrupt. - * @arg USART_IT_RXNE: Receive Data register not empty interrupt. - * - * @note - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) pending bits are cleared by - * software sequence: a read operation to USART_SR register - * (USART_GetITStatus()) followed by a read operation to USART_DR register - * (USART_ReceiveData()). - * - RXNE pending bit can be also cleared by a read to the USART_DR register - * (USART_ReceiveData()). - * - TC pending bit can be also cleared by software sequence: a read - * operation to USART_SR register (USART_GetITStatus()) followed by a write - * operation to USART_DR register (USART_SendData()). - * - TXE pending bit is cleared only by a write to the USART_DR register - * (USART_SendData()). - * @retval None - */ -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) -{ - uint16_t bitpos = 0x00, itmask = 0x00; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_IT(USART_IT)); - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - bitpos = USART_IT >> 0x08; - itmask = ((uint16_t)0x01 << (uint16_t)bitpos); - USARTx->SR = (uint16_t)~itmask; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c deleted file mode 100644 index 77a7ce517..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c +++ /dev/null @@ -1,224 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_wwdg.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief This file provides all the WWDG firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_wwdg.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup WWDG - * @brief WWDG driver modules - * @{ - */ - -/** @defgroup WWDG_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup WWDG_Private_Defines - * @{ - */ - -/* ----------- WWDG registers bit address in the alias region ----------- */ -#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) - -/* Alias word address of EWI bit */ -#define CFR_OFFSET (WWDG_OFFSET + 0x04) -#define EWI_BitNumber 0x09 -#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) - -/* --------------------- WWDG registers bit mask ------------------------ */ - -/* CR register bit mask */ -#define CR_WDGA_Set ((uint32_t)0x00000080) - -/* CFR register bit mask */ -#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) -#define CFR_W_Mask ((uint32_t)0xFFFFFF80) -#define BIT_Mask ((uint8_t)0x7F) - -/** - * @} - */ - -/** @defgroup WWDG_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup WWDG_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup WWDG_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup WWDG_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the WWDG peripheral registers to their default reset values. - * @param None - * @retval None - */ -void WWDG_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); -} - -/** - * @brief Sets the WWDG Prescaler. - * @param WWDG_Prescaler: specifies the WWDG Prescaler. - * This parameter can be one of the following values: - * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 - * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 - * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 - * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 - * @retval None - */ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); - /* Clear WDGTB[1:0] bits */ - tmpreg = WWDG->CFR & CFR_WDGTB_Mask; - /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ - tmpreg |= WWDG_Prescaler; - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Sets the WWDG window value. - * @param WindowValue: specifies the window value to be compared to the downcounter. - * This parameter value must be lower than 0x80. - * @retval None - */ -void WWDG_SetWindowValue(uint8_t WindowValue) -{ - __IO uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); - /* Clear W[6:0] bits */ - - tmpreg = WWDG->CFR & CFR_W_Mask; - - /* Set W[6:0] bits according to WindowValue value */ - tmpreg |= WindowValue & (uint32_t) BIT_Mask; - - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Enables the WWDG Early Wakeup interrupt(EWI). - * @param None - * @retval None - */ -void WWDG_EnableIT(void) -{ - *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; -} - -/** - * @brief Sets the WWDG counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F. - * @retval None - */ -void WWDG_SetCounter(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - /* Write to T[6:0] bits to configure the counter value, no need to do - a read-modify-write; writing a 0 to WDGA bit does nothing */ - WWDG->CR = Counter & BIT_Mask; -} - -/** - * @brief Enables WWDG and load the counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F. - * @retval None - */ -void WWDG_Enable(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - WWDG->CR = CR_WDGA_Set | Counter; -} - -/** - * @brief Checks whether the Early Wakeup interrupt flag is set or not. - * @param None - * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) - */ -FlagStatus WWDG_GetFlagStatus(void) -{ - return (FlagStatus)(WWDG->SR); -} - -/** - * @brief Clears Early Wakeup interrupt flag. - * @param None - * @retval None - */ -void WWDG_ClearFlag(void) -{ - WWDG->SR = (uint32_t)RESET; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Release_Notes.html b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Release_Notes.html deleted file mode 100644 index e753bf3df..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Release_Notes.html +++ /dev/null @@ -1,1031 +0,0 @@ - - - - - - - - - - - - - - - -Release Notes for STM32F10x Standard Peripherals Library - - - - -
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Release -Notes for STM32F10x Standard Peripherals Library (StdPeriph_Lib)

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Copyright 2011 STMicroelectronics

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Contents

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  1. STM32F10x Standard Peripherals Library -update History
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  2. License
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STM32F10x Standard -Peripherals Library update History


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V3.5.0 / 08-April-2011

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Main -Changes

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  • Specific system_stm32f10x.c file provided for each example
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  • HTML file containing the examples list, with main features, provided in the root folder (allow search on key word/feature)
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  • Template projects updated to save configuration time and easy the examples use
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  • Refreshed example list vs. previous version:
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    • Add two new Examples: MPU and TIM DMA Burst    
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    • xWDG examples enhanced, ex. accurate IWDG timeout thanks to LSI freq measure w/ Timer
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    • NVIC and SysTick examples enhanced to provide more details how to use them w/ CMSIS layer
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Contents

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Development Toolchains and Compilers

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  • IAR Embedded Workbench for ARM (EWARM) toolchain V5.50.5
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  • Hitex IDE/Debugger - (HiTOP) toolchain V5.40.0051
  • RealView Microcontroller -Development Kit (MDK-ARM) toolchain V4.13 -
  • Raisonance IDE RIDE7 -(RIDE) toolchain (RIDE7 IDE:7.30.10, RKitARM for RIDE7:1.30.10)
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  • Atollic TrueSTUDIO STM32 -(TrueSTUDIO) toolchain V1.4.0
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3.4.0 - 10/15/2010

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  • Add support for STM32F10x High-density Value line devices.
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  • Add 3 examples: FSMC OneNAND, I2C TSENSOR (Temperature Sensro) and I2C IOExpander.
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  • Utilities STM32  EVAL drivers enhancements:
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    • I2C EEPROM, Temperature Sensor and IO Expander drivers updated to use the DMA for read/write transfer and add more robustness.
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    • SD Card (SDIO) driver updated to add more robustness.
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  1. Libraries
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  • CMSIS
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  • STM32F10x_StdPeriph_Driver
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  • STM32F10x_StdPeriph_Examples
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  • STM32F10x_StdPeriph_Template
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  1. Utilities
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3.3.0 - 04/16/2010

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  • Add support for STM32F10x XL-density devices. 
  • Add template project for TrueSTUDIO toolchain.
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  1. Libraries
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  • CMSIS
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  • STM32F10x_StdPeriph_Driver
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  1. Project
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  • STM32F10x_StdPeriph_Examples
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  • STM32F10x_StdPeriph_Template
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  1. Utilities
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  • STM32_EVAL
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3.2.0 - 03/01/2010

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  1. General
-
  • Add support for STM32 Low-density Value line (STM32F100x4/6) and Medium-density Value line (STM32F100x8/B) devices.
    • -
  • New CMSIS V1.30 release
    • -
-
  1. Libraries
-
  • CMSIS
- -
  • STM32F10x_StdPeriph_Driver
- -
  1. Project
-
  • STM32F10x_StdPeriph_Examples
- -
  • STM32F10x_StdPeriph_Template
- -
  1. Utilities
-
  • STM32_EVAL
- -

V3.1.2 - - 09/28/2009

-
  1. General
-
  • Add support for Hitex - Development Tools HiTOP.
-
  1. Libraries
-
  • CMSIS
-
    • system_stm32f10x.c: SetSysClockTo56() - function, change the flash latency to 2 instead of 1
-
  • STM32F10x_StdPeriph_Driver
-
    • stm32f10x_tim.c: in TIM_OCxInit() functions, - add new instruction to set the CCxS bits (x= 1, 2, 3, 4) - to 0, i.e. the channel CCx is configured as output. In the previous - version these functions was assuming that the CCxS bits are - reset; if a channel was previously configured in input, a call to - this function doesn't allow using it in output mode. This is resolved - with this modification. 
-
    • stm32f10x_spi.h: I2S_InitTypeDef - structure, change the type of I2S_AudioFreq field - to uint32_t instead of uint16_t. This modification is - needed to support I2S 96KHz frequency (available in Connectivity - Line devices).
-
    • stm32f10x_flash.c: FLASH_EraseOptionBytes() - function, add note to clarify this function behavior.
-
  1. Project
-
  • STM32F10x_StdPeriph_Examples
-
    • I2C\EEPROM example
      • i2c_ee.c: I2C_EE_BufferRead() - function, the following line was removed         -                   -                   -      

                  /* Clear EV6 by setting - again the PE bit */
-        I2C_Cmd(I2C_EE, ENABLE);

-
    • RCC example
      • main.c: SetSysClockTo56() - function, change the flash latency to 2 instead of 1
-
  • Template
-
    • Add template projects - for HiTOP toolchain to support Medium-density (Template\HiTOP\STM3210B-EVAL), - High-density (Template\HiTOP\STM3210E-EVAL) and Connectivity line - (Template\HiTOP\STM3210C-EVAL) devices.
-

V3.1.0 -- 06/19/2009

  1. General
  • Update to support the additional peripherals and features embedded in the STM32F10x Connectivity Line devices.
  • Doxygen -documentation enhanced to give more detail about driver function’s -parameters: description, allowed values and required preconditions. -This is mainly relevant for peripheral initialization structure’s -members (PPP_InitTypeDef).
  • C++ support
  1. Libraries
  • CMSIS
    • stm32f10x.h
      • Add new define STM32F10X_CL to configure the library for Connectivity Line devices (default configuration)
      • Interrupt Number Definition (IRQn)
      • Add definition for Connectivity Line devices peripheral’s interrupts
      • For STM32 Low Density Devices, the SPI2_IRQn was removed since there is no SPI2 in these devices.
      • Add register's definitions, bits definitions and memory mapping for new peripherals (Ethernet and CAN2)
      • RCC, DBGMCU, EXTI, CAN, GPIO and AFIO bits definitions updated
      • AFIO_MAPR_SPI1 _REMAP define declaration corrected to AFIO_MAPR_SPI1_REMAP
      • Tailor HSE_Value to the to the selected device
    • system_stm32f10x.c
      • Clock configuration functions updated to support Connectivity line devices
      • Change SetSysClockTo20 function to SetSysClockTo24
    • startup
      • Add new startup files startup_stm32f10x_cl.s  for Connectivity Line devices
      • For STM32 Low Density Devices, the SPI2_IRQHandler was removed since there is no SPI2 in these devices.
      • Use CMSIS Core Peripheral Access Layer V1.20
  • STM32F10x_StdPeriph_Driver
    • CAN: update to support CAN2 peripheral, with no impact on the API
      • Add new instance CAN2
      • Filter number updated
      • Add new function CAN_SlaveStartBank
    • RCC: update to support Connectivity Line devices, with no impact on the API
      • RCC_DeInit and RCC_GetSYSCLKSource functions updated
      • Function’s parameters list updated
      • Add new functions
        • RCC_PREDIV1Config, RCC_PREDIV2Config
        • RCC_PLL2Config, RCC_PLL2Cmd
        • RCC_PLL3Config, RCC_PLL3Cmd
        • RCC_OTGFSCLKConfig
        • RCC_I2S2CLKConfig, RCC_I2S3CLKConfig
        • RCC_AHBPeriphResetCmd
        • RCC_APB2Periph_ALL and RCC_APB1Periph_ALL parameters removed
    • GPIO
      • Update GPIO_PinRemapConfig function with 4 new AF remap
      • Add new function GPIO_ETH_MediaInterfaceConfig
    • EXTI
      • Add new internal EXTI Line 19 connected to ETH wakeup
    • DBGMCU
      • Add new define DBGMCU_CAN2_STOP
    • DAC
      • Add -new define DAC_Trigger_T3_TRGO (to be used instead of -DAC_Trigger_T8_TRGO, since TIM8 not available in Connectivity Line -devices)
    • SPI/I2S
      • I2S_Init function updated to support new clock scheme implemented in Connectivity Line devices
      • Update I2S_AudioFreq defines to support frequency up to 96 KHz
    • FLASH
      • Update FLASH_EnableWriteProtection function header and parameter list  to support Connectivity Line devices
  1. Project
    • STM32F10x_StdPeriph_Examples
      • Almost -examples updated to run on Connectivity Line devices and -STMicroelectronics STM3210C-EVAL evaluation board. Refer to the readme -file provided within each example for more information on how to use -the example with a specific board.
      • TIM: add new example TIM_Input_Capture
      • I2C: M24C08_EEPROM example renamed to EEPROM
    • Template
      • Template -projects for EWARMv5, RIDE and RVMDK updated to support Connectivity -Line devices and STMicroelectronics STM3210C-EVAL evaluation board.
  1. Utilities
  • Implement -a new abstraction layer to interact with the Human Interface resources; -buttons, LEDs, LCD and COM ports (USARTs) available on -STMicroelectronics STM3210C-EVAL (Connectivity line), STM3210E-EVAL -(High-Density) and STM3210B-EVAL (Medium-Density) evaluation boards. -The stm32_eval.c driver provides a common API to interact with buttons, -LEDs and COM ports, while these resources hardware  definitions is -made in the header file of each evaluation board (stm3210x_eval.h). A -common API is provided to manage the LCD across the supported boards, -with a separate driver for each board stm3210x_eval_lcd.c.
-

V3.0.0 -- 04/06/2009

-
  1. General
  • STM3210x FW Library renamed to STM32F10x Standard Peripherals Library (StdPeriph_Lib)
  • STM32F10x Standard Peripherals Library is full CMSIS compliant
  • STM32F10x Standard Peripherals Library Structure is updated.
  • STM32F10x Standard Peripherals Package Architecture is enhanced
  • STM32F10x Standard Peripherals Library User Manual  with *.chm format
  1. library
  • CAN driver updated
    • CAN driver was updated to support STM32F10xxx connectivity line products.
    • CAN peripheral was renamed as CAN1. All occurrences related to CAN were also renamed as CAN1 in the different drivers.
  • I2C driver
    • I2C event assert macro missing in stm32f10x_i2c.h file.
  • DBGMCU
    • Wrong -defines in stm32f10x_dbgmcu.h: DBGMCU_TIM5_STOP, DBGMCU_TIM6_STOP, -DBGMCU_TIM7_STOP and  DBGMCU_TIM8_STOP defines values are wrong.

  • FSMC
    • Remove the FSMC AddressLowMapping configuration
  1. examples
  • FSMC NOR driver Timings are updated.
  • Add CAN "Normal" example
  • TIM "6Steps" example wave forms updated
  • NVIC "CM3_LPModes" and "System_Handlers" examples removed

For more details, please -refer to AN2953 "How to migrate from the STM32F10xxx firmware library -V2.0.3 to the STM32F10xxx standard peripheral library V3.0.0".

-

V2.0.3 -- 09/22/2008

-
    -
  1. General
    2. -
-
    -
  • stm32f10xfwlib_contents_html -file updated:
    • -
      -
    • Description -of firmware library package content
      • -
    • Easy-to-use -firmware library examples: add description of how to use the project -template to run the selected example
      • -
    -
-
    -
  1. library
    2. -
-
    -
  • stm32f10x_map.h: -add all STM32 Hardware registers bits definitions
    • -
  • stm32f10x_conf.h: -add a define for HSEStartUp_TimeOut
    • -
  • stm32f10x_fsmc.h/.c:
    • -
      -
    • FSMC_MemoryType_CRAM is changed -to FSMC_MemoryType_PSRAM
      • -
    • FSMC_AsyncWait member -removed from FSMC_NORSRAMInitTypeDef -structure
      • -
    • FSMC_BusTurnAroundDuration parameter -removed in case of write configuration
      • -
    -
  • stm32f10x_rcc.h/.c:
    • -
      -
    • RCC_FLAG_HSIRDY -define value changed to 0x21.
      • -
    • StartUpCounterand HSEStatus -variables are now local for RCC_WaitForHSEStartUp -function.
      • -
    -
  • stm32f10x_i2c.h/.c: -
    • -
      -
    • Add new -event: EV8: I2C_EVENT_MASTER_BYTE_TRANSMITTING
      • -
    -
  • stm32f10x_tim.c: -
    • -
      -
    • "=" operator -changed to "|=" inside TIM_SelectOCxM -function
      • -
    -
  • stm32f10x_can.c: -Definitions names changed
    • -
-
    -
  1. examples
    2. -
-
    -
  • I2C Interrupt -example
    • -
      -
    • Example -updated according to I2C driver update
      • -
    -
  • I2C -M24C08_EEPROM example
    • -
      -
    • i2c_ee.c -file: add a loop on I2C_FLAG_BUSY in I2C_EE_PageWrite and
      • -
    • I2C_EE_BufferRead -functions
      • -
    • i2c_ee.c -file: add STOP condition in I2C_EE_WaitEepromStandbyState function
      • -
    -
  • SDIO example
    • -
      -
    • Example -updated to support SD Card V2.0 and SD High Capacity cards.
      • -
    -
  • USART Polling -example
    • -
      -
    • USART TC flag -check changed by USART TXE flag check
      • -
    -
-

V2.0.2 -- 07/11/2008

-
    -
  1. library
    2. -
-
    -
  • stm32f10x_spi.c -/.h
    • -
      -
    • SPI_I2S_ClearFlag -function: some flags are removed from the possible flags parameters -list. This function can clear only CRCERR flag.
      • -
    -
-
    -
      -
    • SPI_I2S_ClearITPendingBit -function: some pending bits are removed from the possible -pending bits parameters list. This function can clear only CRCERR -pending -bit.        - 
      • -
    -
-
    -
  • stm32f10x_i2c.c -/.h
    • -
      -
    • I2C_ClearFlag -function: some flags are removed from the possible flags parameters -list. This function can clear only SMBALER, TIMEOUT, PECERR, OVR, AF, -ARLO and BERR flags. The passed parameter can be any combination of -above flags.
      • -
    -
-
    -
  • I2C_GetITStatus -function checks on interrupt pending bit and the interrupt enable bit.
    • -
-
    -
  • I2C_ClearITPendingBit -function: some pending bits are removed from the possible pending bits -parameters list. This function can clear only SMBALER, TIMEOUT, PECERR, -OVR, AF, ARLO and BERR pending bits. The passed parameter can be any -combination of above pending bits. 
    • -
  •  stm32f10x_usart.c -/.h
    • -
      -
    •  USART_ClearFlag -function: some flags are removed from the possible flags parameters -list. This function can clear only CTS, LBD, TC and RXNE -flags.            - 
      • -
    -
-
    -
      -
    • USART_GetITStatus function: -IS_USART_IT macro is changed to IS_USART_GET_IT
      • -
    • USART_ClearITPendingBit function: -some pending bits are removed from the possible pending bits parameters -list. This function can clear only CTS, LBD, TC and RXNE pending -bits.         - 
      • -
    -
-
    -
  • stm32f10x_tim.c
    • -
      -
    • remove -IS_TIM_PERIPH_FLAG(TIMx, -TIM_FLAG) macro from TIM_ClearFlag function.
      • -
    -
-
    -
  • stm32f10x_wwdg.c
    • -
      -
    • use register -direct access in the WWDG_GetFlagStatus -function instead of bit banding access.
      • -
    -
-
    -
  • stm32f10x_gpio.c
    • -
      -
    • GPIO_Init function -update.
      • -
    -
-
    -
  1. examples
    2. -
-
    -
  • I2C Interrupt -example
    • -
      -
    • The example -is changed to provide a description of how to manage -data transfer from master transmitter to slave receiver and -from slave transmitter to master receiver using interrupts.
      • -
    -
-
    -
      -
    • add main.h -file.
      • -
    -
-
    -
  • I2C -10bitAddress example
    • -
      -
    • Updated -according to the I2C driver update.
      • -
    -
-
    -
  • I2C DualAddress -example
    • -
      -
    • Updated -according to the I2C driver update.
      • -
    -
-
    -
  • I2C SMBus -example
    • -
      -
    • Updated -according to the I2C driver update
      • -
    -
-
    -
  • USART DMA_Interrupt -example
    • -
      -
    • Updated -according to the USART driver update.
      • -
    -
-
    -
  • USART -Smartcard example
    • -
      -
    • Updated -according to the USART driver update.
      • -
    -
-
    -
  • DAC Examples
    • -
      -
    • GPIO_Configuration -function updated: Once the DAC channel is enabled, the corresponding -GPIO pin is automatically connected to the DAC converter. In order to -avoid parasitic consumption, the GPIO pin should  -be configured in analog.
      • -
    -
-
    -
  • RTC LSI_Calib -example
    • -
      -
    • Example -Update: add main.h -file.
      • -
    -
-

V2.0.1 -- 06/13/2008

-
    -
  • Remove the -Firmware License Agreement file.
    • -
  • Update the -source files's -header to remove reference to the License.
    • -
-

V2.0 -- 05/23/2008

-
    -
  1. General
    2. -
-
    -
  • The FWLib -V2.0 is an update of the V1.0 to support the extra peripherals and -features embedded in the STM32 High-density -devices.   
    • -
  • Add Firmware -License Agreement file.
    • -
  • For more -details about the Firmware Library, please refer to the User. manual -"UM0427 ARM«-based 32-bit MCU STM32F101xx and STM32F103xx -Firmware  Library"  available for download from the -ST microcontrollers website: www.st.com/stm32. -
    • -
  • Glossary
    • -
      -
    • Medium-density -devices are STM32F101xx and STM32F103xx microcontrollers where the -Flash memory density ranges between 32 and 128 Kbytes.
      • -
    • High-density -devices are STM32F101xx and STM32F103xx microcontrollers where the -Flash memory density ranges between 256 and 512 -Kbytes.   
      • -
    -
-
    -
  1. library
    2. -
-
    -
  • Add driver -for new peripherals: FSMC, SDIO and DAC. 
    • -
  • stm32f10x_spi.c -/.h
    • -
      -
    • driver update to -support new I2S functionality.
      • -
    -
  • Add driver -for DBGMCU and CRC modules    
    • -
  • stm32f10x_dma.c -/.h
    • -
      -
    • driver update to -support DMA2 channels.
      • -
    -
  • stm32f10x_adc.c -/.h
    • -
      -
    • driver update to -support ADC3.
      • -
    -
  • stm32f10x_usart.c -/.h
    • -
      -
    • driver update to -support UART4 and UART5.
      • -
    • new USART_ClockInitTypeDef -structure derived from USART_InitTypeDef -one (for USART synchronous parameters).
      • -
    -
  • Timer -peripherals driver
    • -
      -
    • stm32f10x_tim1.c -/.h and stm32f10x_tim.c /.h drivers merged in one single driver: -stm32f10x_tim.c /.h
      • -
    • update to support -new timer peripherals: TIM5, TIM6, TIM7 and TIM8.
      • -
    • add new macro -for function parameters test.
      • -
    • TIM_TimeBaseInit, TIM_PrescalerConfig -and TIM_GenerateEvent -functions updated.
      • -
    • TIM_TIxExternalClockConfig, -TIM_ETRClockMode1Config, TIM_ETRClockMode2Config, TIM_ETRConfig, -TIM_SetIC1Prescaler, TIM_SetIC2Prescaler, TIM_SetIC3Prescaler and -TIM_SetIC4Prescaler functions prototype update.
      • -
    -
  • stm32f10x_gpio.c -/.h
    • -
      -
    • driver update to -support GPIOF and GPIOG.
      • -
    -
  • stm32f10x_lib.c -/.h, stm32f10x_map.h, stm32f10x_conf.h
    • -
      -
    • update to add new -peripherals register declarations and header files inclusion.
      • -
    -
  • stm32f10x_nvic.c -/.h           -
    • -
  •  stm32f10x_itc.c -/.h
    • -
  • stm32f10x_vector.c -/.s            -
    • -
      -
    • update to support -the new peripherals interrupt vector.
      • -
    -
  • stm32f10x_rcc.c -/.h
    • -
      -
    • driver update to -support new peripherals clock & reset enable/disable.
      • -
    • HSE -Oscillator start up timeout increased to 0x01FF.
      • -
    • RCC_DeInit function -update.
      • -
    -
  • stm32f10x_bkp.c -/.h
    • -
      -
    • driver update to -support the new 32 backup registers.
      • -
    -
  • stm32f10x_map.h
    • -
  • stm32f10x_can.c -
    • -
      -
    • CAN register -numbering update
      • -
    -
  • stm32f10x_flash.h -
    • -
      -
    • update macro -"IS_FLASH_ADDRESS" to support memory size up to 512KB.
      • -
    -
  • stm32f10x_flash.c -
    • -
      -
    • FLASH_EnableWriteProtection function: -update "FLASH_Pages" -paramter -values  description.
      • -
    -
  • stm32f10x_exti.c
    • -
      -
    • EXTI_Init function -update.
      • -
    -
  • stm32f10x_type.h
    • -
      -
    • 'S32_MIN' -type corrected to "#define S32_MIN ((s32)-2147483648)".
      • -
    -
  • stm32f10x_ppp.h
    • -
      -
    • in all macros, -put the passed parameter between parenthesis.
      • -
    -
  • stm32f10x_can.c
    • -
      -
    • extended ID coded in -29-bit long.
      • -
    • CAN -initialization acknowledge error fixed.
      • -
    -
  • stm32f10x_usart.c
    • -
      -
    • change "&=" -instead of "="  in USART_ClearITPendingBit  -and USART_ClearFlag -functions.
      • -
    -
  • stm32f10x_adc.c
    • -
      -
    • replace "&=" -by "="  in ADC_ClearITPendingBit -and ADC_ClearFlag -functions.
      • -
    -
  • stm32f10x_i2c.c
    • -
      -
    • replace "&=" -by "="  in I2C_ClearITPendingBit and I2C_ClearFlag functions.
      • -
    -
  • stm32f10x_tim.c
    • -
      -
    • replace "&=" -by "="  in TIM_ClearITPendingBit -and TIM_ClearFlag -functions.
      • -
    -
-
    -
  1. project
    2. -
-
    -
  • stm32f10x_it.c
    • -
      -
    • update file -description.
      • -
    -
  • Add template -projects for EWARM v5 and HiTOP -toolchains.           -
    • -
-
    -
  1. examples
    2. -
-
    -
  • FWLib V1.0 -examples ported to run on STMicroelectronics STM3210E-EVAL evaluation -board (in addition to STM3210B-EVAL)
    • -
  • Add new -examples for FSMC, SDIO, DAC and I2S (run only on High-density -devices).
    • -
  • Add new -examples for ADC, DMA and RTC peripherals.
    • -
  • Add new -example for CRC module.
    • -
  • Examples -folder renamed, use of short name instead of examplex -(x: 1 2 ...).
    • -
-

V1.0 -- 10/08/2007

-
    -
  1. library
    2. -
-
    -
  • Add template -project with RIDE toolchain. -
    • -
  • In all -stm32f10x_ppp.c and stm32f10x_conf.h files: change "assert" macro name -to "assert_param".
    • -
      -
    •   -Note: If you are using the FW Library V0.3 in your application and you -want to migrate to V1.0, you have to update your applications -ôstm32f10x_conf.h file with the latest one (provided with V1.0).
      • -
    -
  • stm32f10x_conf.h
    • -
      -
    • Remove '#undef -assert'
      • -
    • Change -'#define DEBUG' by '#define DEBUG    1'
      • -
    -
  • stm32f10x_type.h
    • -
      -
    • Add new -types: sc32, sc16, sc8, vsc32, vsc16 and vsc8 
      • -
    -
  • stm32f10x_it.c -
    • -
      -
    • Add basic -fault exception handling: in "HardFaultException", -"MemManageException",  -"BusFaultException" -and "UsageFaultException" -ISR the following code was added:
      • -
    -
-
-

     -/* Go to infinite loop when exception occurs */
-     while (1)
-     {
-     }

-
-
    -
  • stm32f10x_rcc.c
    • -
      -
    • "RCC_WaitForHSEStartUp()" -function updated to resolve issue with high GNU compiler optimization.
      • -
    -
  • stm32f10x_gpio.h
    • -
  • '#define -GPIO_Remap1_CAN ((u32)0x001D2000)' changed to '#define GPIO_Remap1_CAN -((u32)0x001D4000)'.
    • -
  • stm32f10x_rtc.c/.h
    • -
      -
    • "RTC_GetPrescaler" -function removed.
      • -
    -
  • stm32f10x_bkp.c/.h
    • -
  • add "BKP_RTCOutputConfig()" -function to allow to select the RTC output source(Calib -clock, RTC Alarm or RTC Second) to output on Tamper pin and remove "BKP_RTCCalibrationClockOutputCmd()" -function.      
    • -
  • stm32f10x_can.h
    • -
      -
    • CAN -synchronization jump width defines updated
      • -
    • '#define -CAN_SJW_0tq' ==> '#define CAN_SJW_1tq'
      • -
    • '#define -CAN_SJW_1tq' ==> '#define CAN_SJW_2tq'
      • -
    • '#define -CAN_SJW_2tq' ==> '#define CAN_SJW_3tq'
      • -
    • '#define -CAN_SJW_3tq' ==> '#define CAN_SJW_4tq'
      • -
    -
  • stm32f10x_tim1.c/.h
    • -
      -
    • "TIM1_OCxNPolarityConfig(u16 -TIM1_OCPolarity)" function: change parameter name to 'TIM1_OCNPolarity' -
      • -
    • change -'TIM1_ICSelection_TRGI' by 'TIM1_ICSelection_TRC'
      • -
    -
  • stm32f10x_tim.c/.h
    • -
      -
    • change 'TIM_ICSelection_TRGI' -by 'TIM_ICSelection_TRC'
      • -
    -
-
    -
  1. examples
    2. -
-
    -
  • ADC examples -3 & 4 updated   
    • -
  • DEBUG example
    • -
  • Example -modified to support RIDE specific printf -function implementation
    • -
  • I2C example5
    • -
      -
    • i2c_ee.c: add -the following function prototypes: "void GPIO_Configuration(void)"  -add "void I2C_Configuration(void)"
      • -
    -
  • Add GPIO pin -toggle example.
    • -
  • BKP, CAN, -DMA, NVIC and I2C examples readme files updated.
    • -
  • Use decimal -(instead of hexadecimal) values constants in TIM, TIM1 and IWDG -examples.
    • -
  • USART
    • -
      -
    • example 12
      • -
        -
      • USART3 ISR -updated
        • -
      • Timeout -define "SC_Receive_Timeout" -updated to 0x4000
        • -
      -
    • example 7
      • -
        -
      • Example -modified to support RIDE specific printf -function implementation
        • -
      -
    -
  • RTC example
    • -
      -
    • Example -modified to support RIDE specific printf -function implementation
      • -
    • Change "BKP_RTCCalibrationClockOutputCmd()" -function  by "RTC_ClockOutput()"
      • -
    • LSI removed -as RTC clock source
      • -
    -
  • IWDG example
    • -
      -
    • LSI frequency -value changed from 32 KHz to 40 KHz 
      • -
    -
  • Update the -STM32F10x evaluation board name from STM32F10x-EVAL to STM3210B-EVAL
    • -
-

V0.3 -- 05/21/2007

-
    -
  • Created.
    • -
-

License

-

The -enclosed firmware and all the related documentation are not covered by -a License Agreement, if you need such License you can contact your -local STMicroelectronics office.

-

THE -PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO -SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR -ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY -CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY -CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH -THEIR PRODUCTS.

-

 

-
-
-

For complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers -visit www.st.com/STM32

-
-

-
-
-

 

-
- \ No newline at end of file diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/fonts.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/fonts.c deleted file mode 100644 index 92d5b9178..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/fonts.c +++ /dev/null @@ -1,997 +0,0 @@ -/** - ****************************************************************************** - * @file fonts.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file provides text fonts for STM32xx-EVAL's LCD driver. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "fonts.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup Common - * @{ - */ - -/** @addtogroup FONTS - * @brief This file includes the Fonts driver of STM32-EVAL boards. - * @{ - */ - -/** @defgroup FONTS_Private_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup FONTS_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup FONTS_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup FONTS_Private_Variables - * @{ - */ -const uint16_t ASCII16x24_Table [] = { -/** - * @brief Space ' ' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief '!' - */ - 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, - 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, 0x0000, - 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief '"' - */ - 0x0000, 0x0000, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief '#' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C60, 0x0C60, - 0x0C60, 0x0630, 0x0630, 0x1FFE, 0x1FFE, 0x0630, 0x0738, 0x0318, - 0x1FFE, 0x1FFE, 0x0318, 0x0318, 0x018C, 0x018C, 0x018C, 0x0000, -/** - * @brief '$' - */ - 0x0000, 0x0080, 0x03E0, 0x0FF8, 0x0E9C, 0x1C8C, 0x188C, 0x008C, - 0x0098, 0x01F8, 0x07E0, 0x0E80, 0x1C80, 0x188C, 0x188C, 0x189C, - 0x0CB8, 0x0FF0, 0x03E0, 0x0080, 0x0080, 0x0000, 0x0000, 0x0000, -/** - * @brief '%' - */ - 0x0000, 0x0000, 0x0000, 0x180E, 0x0C1B, 0x0C11, 0x0611, 0x0611, - 0x0311, 0x0311, 0x019B, 0x018E, 0x38C0, 0x6CC0, 0x4460, 0x4460, - 0x4430, 0x4430, 0x4418, 0x6C18, 0x380C, 0x0000, 0x0000, 0x0000, -/** - * @brief '&' - */ - 0x0000, 0x01E0, 0x03F0, 0x0738, 0x0618, 0x0618, 0x0330, 0x01F0, - 0x00F0, 0x00F8, 0x319C, 0x330E, 0x1E06, 0x1C06, 0x1C06, 0x3F06, - 0x73FC, 0x21F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief ''' - */ - 0x0000, 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief '(' - */ - 0x0000, 0x0200, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x0060, 0x0060, - 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, - 0x0060, 0x0060, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0200, 0x0000, -/** - * @brief ')' - */ - 0x0000, 0x0020, 0x0060, 0x00C0, 0x0180, 0x0180, 0x0300, 0x0300, - 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, - 0x0300, 0x0300, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0020, 0x0000, -/** - * @brief '*' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, - 0x06D8, 0x07F8, 0x01E0, 0x0330, 0x0738, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief '+' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, - 0x0180, 0x0180, 0x0180, 0x3FFC, 0x3FFC, 0x0180, 0x0180, 0x0180, - 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief ',' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, -/** - * @brief '-' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x07E0, 0x07E0, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief '.' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief '/' - */ - 0x0000, 0x0C00, 0x0C00, 0x0600, 0x0600, 0x0600, 0x0300, 0x0300, - 0x0300, 0x0380, 0x0180, 0x0180, 0x0180, 0x00C0, 0x00C0, 0x00C0, - 0x0060, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief '0' - */ - 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x180C, 0x180C, 0x180C, - 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C18, 0x0E38, - 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief '1' - */ - 0x0000, 0x0100, 0x0180, 0x01C0, 0x01F0, 0x0198, 0x0188, 0x0180, - 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, - 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief '2' - */ - 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x1800, - 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, - 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief '3' - */ - 0x0000, 0x01E0, 0x07F8, 0x0E18, 0x0C0C, 0x0C0C, 0x0C00, 0x0600, - 0x03C0, 0x07C0, 0x0C00, 0x1800, 0x1800, 0x180C, 0x180C, 0x0C18, - 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief '4' - */ - 0x0000, 0x0C00, 0x0E00, 0x0F00, 0x0F00, 0x0D80, 0x0CC0, 0x0C60, - 0x0C60, 0x0C30, 0x0C18, 0x0C0C, 0x3FFC, 0x3FFC, 0x0C00, 0x0C00, - 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief '5' - */ - 0x0000, 0x0FF8, 0x0FF8, 0x0018, 0x0018, 0x000C, 0x03EC, 0x07FC, - 0x0E1C, 0x1C00, 0x1800, 0x1800, 0x1800, 0x180C, 0x0C1C, 0x0E18, - 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief '6' - */ - 0x0000, 0x07C0, 0x0FF0, 0x1C38, 0x1818, 0x0018, 0x000C, 0x03CC, - 0x0FEC, 0x0E3C, 0x1C1C, 0x180C, 0x180C, 0x180C, 0x1C18, 0x0E38, - 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief '7' - */ - 0x0000, 0x1FFC, 0x1FFC, 0x0C00, 0x0600, 0x0600, 0x0300, 0x0380, - 0x0180, 0x01C0, 0x00C0, 0x00E0, 0x0060, 0x0060, 0x0070, 0x0030, - 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief '8' - */ - 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x0C18, 0x0C18, 0x0638, - 0x07F0, 0x07F0, 0x0C18, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C38, - 0x0FF8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief '9' - */ - 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C1C, 0x180C, 0x180C, 0x180C, - 0x1C1C, 0x1E38, 0x1BF8, 0x19E0, 0x1800, 0x0C00, 0x0C00, 0x0E1C, - 0x07F8, 0x01F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief ':' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief ';' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, 0x0000, -/** - * @brief '<' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x1000, 0x1C00, 0x0F80, 0x03E0, 0x00F8, 0x0018, 0x00F8, 0x03E0, - 0x0F80, 0x1C00, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief '=' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x1FF8, 0x0000, 0x0000, 0x0000, 0x1FF8, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief '>' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0008, 0x0038, 0x01F0, 0x07C0, 0x1F00, 0x1800, 0x1F00, 0x07C0, - 0x01F0, 0x0038, 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief '?' - */ - 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x0C00, - 0x0600, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x0000, 0x0000, - 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief '@' - */ - 0x0000, 0x0000, 0x07E0, 0x1818, 0x2004, 0x29C2, 0x4A22, 0x4411, - 0x4409, 0x4409, 0x4409, 0x2209, 0x1311, 0x0CE2, 0x4002, 0x2004, - 0x1818, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'A' - */ - 0x0000, 0x0380, 0x0380, 0x06C0, 0x06C0, 0x06C0, 0x0C60, 0x0C60, - 0x1830, 0x1830, 0x1830, 0x3FF8, 0x3FF8, 0x701C, 0x600C, 0x600C, - 0xC006, 0xC006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'B' - */ - 0x0000, 0x03FC, 0x0FFC, 0x0C0C, 0x180C, 0x180C, 0x180C, 0x0C0C, - 0x07FC, 0x0FFC, 0x180C, 0x300C, 0x300C, 0x300C, 0x300C, 0x180C, - 0x1FFC, 0x07FC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'C' - */ - 0x0000, 0x07C0, 0x1FF0, 0x3838, 0x301C, 0x700C, 0x6006, 0x0006, - 0x0006, 0x0006, 0x0006, 0x0006, 0x0006, 0x6006, 0x700C, 0x301C, - 0x1FF0, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'D' - */ - 0x0000, 0x03FE, 0x0FFE, 0x0E06, 0x1806, 0x1806, 0x3006, 0x3006, - 0x3006, 0x3006, 0x3006, 0x3006, 0x3006, 0x1806, 0x1806, 0x0E06, - 0x0FFE, 0x03FE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'E' - */ - 0x0000, 0x3FFC, 0x3FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, - 0x1FFC, 0x1FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, - 0x3FFC, 0x3FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'F' - */ - 0x0000, 0x3FF8, 0x3FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, - 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, - 0x0018, 0x0018, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'G' - */ - 0x0000, 0x0FE0, 0x3FF8, 0x783C, 0x600E, 0xE006, 0xC007, 0x0003, - 0x0003, 0xFE03, 0xFE03, 0xC003, 0xC007, 0xC006, 0xC00E, 0xF03C, - 0x3FF8, 0x0FE0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'H' - */ - 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, - 0x3FFC, 0x3FFC, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, - 0x300C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'I' - */ - 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, - 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, - 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'J' - */ - 0x0000, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, - 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0618, 0x0618, 0x0738, - 0x03F0, 0x01E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'K' - */ - 0x0000, 0x3006, 0x1806, 0x0C06, 0x0606, 0x0306, 0x0186, 0x00C6, - 0x0066, 0x0076, 0x00DE, 0x018E, 0x0306, 0x0606, 0x0C06, 0x1806, - 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'L' - */ - 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, - 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, - 0x1FF8, 0x1FF8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'M' - */ - 0x0000, 0xE00E, 0xF01E, 0xF01E, 0xF01E, 0xD836, 0xD836, 0xD836, - 0xD836, 0xCC66, 0xCC66, 0xCC66, 0xC6C6, 0xC6C6, 0xC6C6, 0xC6C6, - 0xC386, 0xC386, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'N' - */ - 0x0000, 0x300C, 0x301C, 0x303C, 0x303C, 0x306C, 0x306C, 0x30CC, - 0x30CC, 0x318C, 0x330C, 0x330C, 0x360C, 0x360C, 0x3C0C, 0x3C0C, - 0x380C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'O' - */ - 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xC003, 0xC003, - 0xC003, 0xC003, 0xC003, 0xC003, 0xC003, 0x6006, 0x700E, 0x381C, - 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'P' - */ - 0x0000, 0x0FFC, 0x1FFC, 0x380C, 0x300C, 0x300C, 0x300C, 0x300C, - 0x180C, 0x1FFC, 0x07FC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, - 0x000C, 0x000C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'Q' - */ - 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xE003, 0xC003, - 0xC003, 0xC003, 0xC003, 0xC003, 0xE007, 0x6306, 0x3F0E, 0x3C1C, - 0x3FF8, 0xF7E0, 0xC000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'R' - */ - 0x0000, 0x0FFE, 0x1FFE, 0x3806, 0x3006, 0x3006, 0x3006, 0x3806, - 0x1FFE, 0x07FE, 0x0306, 0x0606, 0x0C06, 0x1806, 0x1806, 0x3006, - 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'S' - */ - 0x0000, 0x03E0, 0x0FF8, 0x0C1C, 0x180C, 0x180C, 0x000C, 0x001C, - 0x03F8, 0x0FE0, 0x1E00, 0x3800, 0x3006, 0x3006, 0x300E, 0x1C1C, - 0x0FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'T' - */ - 0x0000, 0x7FFE, 0x7FFE, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, - 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, - 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'U' - */ - 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, - 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x1818, - 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'V' - */ - 0x0000, 0x6003, 0x3006, 0x3006, 0x3006, 0x180C, 0x180C, 0x180C, - 0x0C18, 0x0C18, 0x0E38, 0x0630, 0x0630, 0x0770, 0x0360, 0x0360, - 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'W' - */ - 0x0000, 0x6003, 0x61C3, 0x61C3, 0x61C3, 0x3366, 0x3366, 0x3366, - 0x3366, 0x3366, 0x3366, 0x1B6C, 0x1B6C, 0x1B6C, 0x1A2C, 0x1E3C, - 0x0E38, 0x0E38, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'X' - */ - 0x0000, 0xE00F, 0x700C, 0x3018, 0x1830, 0x0C70, 0x0E60, 0x07C0, - 0x0380, 0x0380, 0x03C0, 0x06E0, 0x0C70, 0x1C30, 0x1818, 0x300C, - 0x600E, 0xE007, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'Y' - */ - 0x0000, 0xC003, 0x6006, 0x300C, 0x381C, 0x1838, 0x0C30, 0x0660, - 0x07E0, 0x03C0, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, - 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'Z' - */ - 0x0000, 0x7FFC, 0x7FFC, 0x6000, 0x3000, 0x1800, 0x0C00, 0x0600, - 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, 0x000C, 0x0006, - 0x7FFE, 0x7FFE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief '[' - */ - 0x0000, 0x03E0, 0x03E0, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, - 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, - 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x03E0, 0x03E0, 0x0000, -/** - * @brief '\' - */ - 0x0000, 0x0030, 0x0030, 0x0060, 0x0060, 0x0060, 0x00C0, 0x00C0, - 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0300, 0x0300, 0x0300, - 0x0600, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief ']' - */ - 0x0000, 0x03E0, 0x03E0, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, - 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, - 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x03E0, 0x03E0, 0x0000, -/** - * @brief '^' - */ - 0x0000, 0x0000, 0x01C0, 0x01C0, 0x0360, 0x0360, 0x0360, 0x0630, - 0x0630, 0x0C18, 0x0C18, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief '_' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief ''' - */ - 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'a' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03F0, 0x07F8, - 0x0C1C, 0x0C0C, 0x0F00, 0x0FF0, 0x0CF8, 0x0C0C, 0x0C0C, 0x0F1C, - 0x0FF8, 0x18F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'b' - */ - 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x03D8, 0x0FF8, - 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38, - 0x0FF8, 0x03D8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'c' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x07F0, - 0x0E30, 0x0C18, 0x0018, 0x0018, 0x0018, 0x0018, 0x0C18, 0x0E30, - 0x07F0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'd' - */ - 0x0000, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x1BC0, 0x1FF0, - 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30, - 0x1FF0, 0x1BC0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'e' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0, - 0x0C30, 0x1818, 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x1838, 0x1C30, - 0x0FF0, 0x07C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'f' - */ - 0x0000, 0x0F80, 0x0FC0, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0, - 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, - 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'g' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0DE0, 0x0FF8, - 0x0E18, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0E18, - 0x0FF8, 0x0DE0, 0x0C00, 0x0C0C, 0x061C, 0x07F8, 0x01F0, 0x0000, -/** - * @brief 'h' - */ - 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x07D8, 0x0FF8, - 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, - 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'i' - */ - 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, - 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, - 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'j' - */ - 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, - 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, - 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00F8, 0x0078, 0x0000, -/** - * @brief 'k' - */ - 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0C0C, 0x060C, - 0x030C, 0x018C, 0x00CC, 0x006C, 0x00FC, 0x019C, 0x038C, 0x030C, - 0x060C, 0x0C0C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'l' - */ - 0x0000, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, - 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, - 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'm' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3C7C, 0x7EFF, - 0xE3C7, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, - 0xC183, 0xC183, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'n' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0798, 0x0FF8, - 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, - 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'o' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0, - 0x0C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C30, - 0x0FF0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'p' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03D8, 0x0FF8, - 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38, - 0x0FF8, 0x03D8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0000, -/** - * @brief 'q' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1BC0, 0x1FF0, - 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30, - 0x1FF0, 0x1BC0, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x0000, -/** - * @brief 'r' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x07B0, 0x03F0, - 0x0070, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, - 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 's' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03E0, 0x03F0, - 0x0E38, 0x0C18, 0x0038, 0x03F0, 0x07C0, 0x0C00, 0x0C18, 0x0E38, - 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 't' - */ - 0x0000, 0x0000, 0x0080, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0, - 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, - 0x07C0, 0x0780, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'u' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1818, 0x1818, - 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C38, - 0x1FF0, 0x19E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'v' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x180C, 0x0C18, - 0x0C18, 0x0C18, 0x0630, 0x0630, 0x0630, 0x0360, 0x0360, 0x0360, - 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'w' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x41C1, 0x41C1, - 0x61C3, 0x6363, 0x6363, 0x6363, 0x3636, 0x3636, 0x3636, 0x1C1C, - 0x1C1C, 0x1C1C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'x' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x381C, 0x1C38, - 0x0C30, 0x0660, 0x0360, 0x0360, 0x0360, 0x0360, 0x0660, 0x0C30, - 0x1C38, 0x381C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief 'y' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3018, 0x1830, - 0x1830, 0x1870, 0x0C60, 0x0C60, 0x0CE0, 0x06C0, 0x06C0, 0x0380, - 0x0380, 0x0380, 0x0180, 0x0180, 0x01C0, 0x00F0, 0x0070, 0x0000, -/** - * @brief 'z' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1FFC, 0x1FFC, - 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, - 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -/** - * @brief '{' - */ - 0x0000, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, - 0x00C0, 0x0060, 0x0060, 0x0030, 0x0060, 0x0040, 0x00C0, 0x00C0, - 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0000, 0x0000, -/** - * @brief '|' - */ - 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, - 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, - 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, -/** - * @brief '}' - */ - 0x0000, 0x0060, 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0180, - 0x0180, 0x0300, 0x0300, 0x0600, 0x0300, 0x0100, 0x0180, 0x0180, - 0x0180, 0x0180, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0000, 0x0000, -/** - * @brief '~' - */ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x10F0, 0x1FF8, 0x0F08, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}; - -const uint16_t ASCII12x12_Table [] = { - 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, - 0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x0000,0x2000,0x0000,0x0000, - 0x0000,0x5000,0x5000,0x5000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, - 0x0000,0x0900,0x0900,0x1200,0x7f00,0x1200,0x7f00,0x1200,0x2400,0x2400,0x0000,0x0000, - 0x1000,0x3800,0x5400,0x5000,0x5000,0x3800,0x1400,0x5400,0x5400,0x3800,0x1000,0x0000, - 0x0000,0x3080,0x4900,0x4900,0x4a00,0x32c0,0x0520,0x0920,0x0920,0x10c0,0x0000,0x0000, - 0x0000,0x0c00,0x1200,0x1200,0x1400,0x1800,0x2500,0x2300,0x2300,0x1d80,0x0000,0x0000, - 0x0000,0x4000,0x4000,0x4000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, - 0x0000,0x0800,0x1000,0x1000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x1000,0x1000, - 0x0000,0x4000,0x2000,0x2000,0x1000,0x1000,0x1000,0x1000,0x1000,0x1000,0x2000,0x2000, - 0x0000,0x2000,0x7000,0x2000,0x5000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, - 0x0000,0x0000,0x0000,0x0800,0x0800,0x7f00,0x0800,0x0800,0x0000,0x0000,0x0000,0x0000, - 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x2000,0x4000, - 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x7000,0x0000,0x0000,0x0000,0x0000,0x0000, - 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x0000,0x0000, - 0x0000,0x1000,0x1000,0x1000,0x2000,0x2000,0x2000,0x2000,0x4000,0x4000,0x0000,0x0000, - 0x0000,0x1000,0x2800,0x4400,0x4400,0x4400,0x4400,0x4400,0x2800,0x1000,0x0000,0x0000, - 0x0000,0x1000,0x3000,0x5000,0x1000,0x1000,0x1000,0x1000,0x1000,0x1000,0x0000,0x0000, - 0x0000,0x3000,0x4800,0x4400,0x0400,0x0800,0x1000,0x2000,0x4000,0x7c00,0x0000,0x0000, - 0x0000,0x3000,0x4800,0x0400,0x0800,0x1000,0x0800,0x4400,0x4800,0x3000,0x0000,0x0000, - 0x0000,0x0800,0x1800,0x1800,0x2800,0x2800,0x4800,0x7c00,0x0800,0x0800,0x0000,0x0000, - 0x0000,0x3c00,0x2000,0x4000,0x7000,0x4800,0x0400,0x4400,0x4800,0x3000,0x0000,0x0000, - 0x0000,0x1800,0x2400,0x4000,0x5000,0x6800,0x4400,0x4400,0x2800,0x1000,0x0000,0x0000, - 0x0000,0x7c00,0x0400,0x0800,0x1000,0x1000,0x1000,0x2000,0x2000,0x2000,0x0000,0x0000, - 0x0000,0x1000,0x2800,0x4400,0x2800,0x1000,0x2800,0x4400,0x2800,0x1000,0x0000,0x0000, - 0x0000,0x1000,0x2800,0x4400,0x4400,0x2c00,0x1400,0x0400,0x4800,0x3000,0x0000,0x0000, - 0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x0000,0x0000, - 0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x2000,0x4000, - 0x0000,0x0000,0x0400,0x0800,0x3000,0x4000,0x3000,0x0800,0x0400,0x0000,0x0000,0x0000, - 0x0000,0x0000,0x0000,0x7c00,0x0000,0x0000,0x7c00,0x0000,0x0000,0x0000,0x0000,0x0000, - 0x0000,0x0000,0x4000,0x2000,0x1800,0x0400,0x1800,0x2000,0x4000,0x0000,0x0000,0x0000, - 0x0000,0x3800,0x6400,0x4400,0x0400,0x0800,0x1000,0x1000,0x0000,0x1000,0x0000,0x0000, - 0x0000,0x0f80,0x1040,0x2ea0,0x51a0,0x5120,0x5120,0x5120,0x5320,0x4dc0,0x2020,0x1040, - 0x0000,0x0800,0x1400,0x1400,0x1400,0x2200,0x3e00,0x2200,0x4100,0x4100,0x0000,0x0000, - 0x0000,0x3c00,0x2200,0x2200,0x2200,0x3c00,0x2200,0x2200,0x2200,0x3c00,0x0000,0x0000, - 0x0000,0x0e00,0x1100,0x2100,0x2000,0x2000,0x2000,0x2100,0x1100,0x0e00,0x0000,0x0000, - 0x0000,0x3c00,0x2200,0x2100,0x2100,0x2100,0x2100,0x2100,0x2200,0x3c00,0x0000,0x0000, - 0x0000,0x3e00,0x2000,0x2000,0x2000,0x3e00,0x2000,0x2000,0x2000,0x3e00,0x0000,0x0000, - 0x0000,0x3e00,0x2000,0x2000,0x2000,0x3c00,0x2000,0x2000,0x2000,0x2000,0x0000,0x0000, - 0x0000,0x0e00,0x1100,0x2100,0x2000,0x2700,0x2100,0x2100,0x1100,0x0e00,0x0000,0x0000, - 0x0000,0x2100,0x2100,0x2100,0x2100,0x3f00,0x2100,0x2100,0x2100,0x2100,0x0000,0x0000, - 0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x0000,0x0000, - 0x0000,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x4800,0x4800,0x3000,0x0000,0x0000, - 0x0000,0x2200,0x2400,0x2800,0x2800,0x3800,0x2800,0x2400,0x2400,0x2200,0x0000,0x0000, - 0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x3e00,0x0000,0x0000, - 0x0000,0x2080,0x3180,0x3180,0x3180,0x2a80,0x2a80,0x2a80,0x2a80,0x2480,0x0000,0x0000, - 0x0000,0x2100,0x3100,0x3100,0x2900,0x2900,0x2500,0x2300,0x2300,0x2100,0x0000,0x0000, - 0x0000,0x0c00,0x1200,0x2100,0x2100,0x2100,0x2100,0x2100,0x1200,0x0c00,0x0000,0x0000, - 0x0000,0x3c00,0x2200,0x2200,0x2200,0x3c00,0x2000,0x2000,0x2000,0x2000,0x0000,0x0000, - 0x0000,0x0c00,0x1200,0x2100,0x2100,0x2100,0x2100,0x2100,0x1600,0x0d00,0x0100,0x0000, - 0x0000,0x3e00,0x2100,0x2100,0x2100,0x3e00,0x2400,0x2200,0x2100,0x2080,0x0000,0x0000, - 0x0000,0x1c00,0x2200,0x2200,0x2000,0x1c00,0x0200,0x2200,0x2200,0x1c00,0x0000,0x0000, - 0x0000,0x3e00,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x0000,0x0000, - 0x0000,0x2100,0x2100,0x2100,0x2100,0x2100,0x2100,0x2100,0x1200,0x0c00,0x0000,0x0000, - 0x0000,0x4100,0x4100,0x2200,0x2200,0x2200,0x1400,0x1400,0x1400,0x0800,0x0000,0x0000, - 0x0000,0x4440,0x4a40,0x2a40,0x2a80,0x2a80,0x2a80,0x2a80,0x2a80,0x1100,0x0000,0x0000, - 0x0000,0x4100,0x2200,0x1400,0x1400,0x0800,0x1400,0x1400,0x2200,0x4100,0x0000,0x0000, - 0x0000,0x4100,0x2200,0x2200,0x1400,0x0800,0x0800,0x0800,0x0800,0x0800,0x0000,0x0000, - 0x0000,0x7e00,0x0200,0x0400,0x0800,0x1000,0x1000,0x2000,0x4000,0x7e00,0x0000,0x0000, - 0x0000,0x3000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000, - 0x0000,0x4000,0x4000,0x2000,0x2000,0x2000,0x2000,0x2000,0x1000,0x1000,0x0000,0x0000, - 0x0000,0x6000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000, - 0x0000,0x1000,0x2800,0x2800,0x2800,0x4400,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, - 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x7e00, - 0x4000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, - 0x0000,0x0000,0x0000,0x3800,0x4400,0x0400,0x3c00,0x4400,0x4400,0x3c00,0x0000,0x0000, - 0x0000,0x4000,0x4000,0x5800,0x6400,0x4400,0x4400,0x4400,0x6400,0x5800,0x0000,0x0000, - 0x0000,0x0000,0x0000,0x3000,0x4800,0x4000,0x4000,0x4000,0x4800,0x3000,0x0000,0x0000, - 0x0000,0x0400,0x0400,0x3400,0x4c00,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0000,0x0000, - 0x0000,0x0000,0x0000,0x3800,0x4400,0x4400,0x7c00,0x4000,0x4400,0x3800,0x0000,0x0000, - 0x0000,0x6000,0x4000,0xe000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000, - 0x0000,0x0000,0x0000,0x3400,0x4c00,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0400,0x4400, - 0x0000,0x4000,0x4000,0x5800,0x6400,0x4400,0x4400,0x4400,0x4400,0x4400,0x0000,0x0000, - 0x0000,0x4000,0x0000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000, - 0x0000,0x4000,0x0000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000, - 0x0000,0x4000,0x4000,0x4800,0x5000,0x6000,0x5000,0x5000,0x4800,0x4800,0x0000,0x0000, - 0x0000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000, - 0x0000,0x0000,0x0000,0x5200,0x6d00,0x4900,0x4900,0x4900,0x4900,0x4900,0x0000,0x0000, - 0x0000,0x0000,0x0000,0x5800,0x6400,0x4400,0x4400,0x4400,0x4400,0x4400,0x0000,0x0000, - 0x0000,0x0000,0x0000,0x3800,0x4400,0x4400,0x4400,0x4400,0x4400,0x3800,0x0000,0x0000, - 0x0000,0x0000,0x0000,0x5800,0x6400,0x4400,0x4400,0x4400,0x6400,0x5800,0x4000,0x4000, - 0x0000,0x0000,0x0000,0x3400,0x4c00,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0400,0x0400, - 0x0000,0x0000,0x0000,0x5000,0x6000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000, - 0x0000,0x0000,0x0000,0x3000,0x4800,0x4000,0x3000,0x0800,0x4800,0x3000,0x0000,0x0000, - 0x0000,0x4000,0x4000,0xe000,0x4000,0x4000,0x4000,0x4000,0x4000,0x6000,0x0000,0x0000, - 0x0000,0x0000,0x0000,0x4400,0x4400,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0000,0x0000, - 0x0000,0x0000,0x0000,0x4400,0x4400,0x2800,0x2800,0x2800,0x2800,0x1000,0x0000,0x0000, - 0x0000,0x0000,0x0000,0x4900,0x4900,0x5500,0x5500,0x5500,0x5500,0x2200,0x0000,0x0000, - 0x0000,0x0000,0x0000,0x4400,0x2800,0x2800,0x1000,0x2800,0x2800,0x4400,0x0000,0x0000, - 0x0000,0x0000,0x0000,0x4400,0x4400,0x2800,0x2800,0x2800,0x1000,0x1000,0x1000,0x1000, - 0x0000,0x0000,0x0000,0x7800,0x0800,0x1000,0x2000,0x2000,0x4000,0x7800,0x0000,0x0000, - 0x0000,0x1000,0x2000,0x2000,0x2000,0x2000,0x4000,0x2000,0x2000,0x2000,0x2000,0x2000, - 0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000, - 0x0000,0x4000,0x2000,0x2000,0x2000,0x2000,0x1000,0x2000,0x2000,0x2000,0x2000,0x2000, - 0x0000,0x0000,0x0000,0x0000,0x7400,0x5800,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, - 0x0000,0x0000,0x7000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x7000,0x0000,0x0000}; - -const uint16_t ASCII8x12_Table [] = { - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x10,0x00, - 0x00,0x00,0x00,0x28,0x28,0x28,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x14,0x14,0x3e,0x14,0x28,0x7c,0x28,0x28,0x00, - 0x00,0x00,0x10,0x38,0x54,0x50,0x38,0x14,0x14,0x54,0x38,0x10, - 0x00,0x00,0x00,0x44,0xa8,0xa8,0x50,0x14,0x1a,0x2a,0x24,0x00, - 0x00,0x00,0x00,0x20,0x50,0x50,0x20,0xe8,0x98,0x98,0x60,0x00, - 0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x40,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80, - 0x00,0x00,0x00,0x80,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40, - 0x00,0x00,0x00,0x40,0xe0,0x40,0xa0,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x20,0x20,0xf8,0x20,0x20,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x40, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00, - 0x00,0x00,0x00,0x20,0x20,0x20,0x40,0x40,0x80,0x80,0x80,0x00, - 0x00,0x00,0x00,0x60,0x90,0x90,0x90,0x90,0x90,0x90,0x60,0x00, - 0x00,0x00,0x00,0x20,0x60,0xa0,0x20,0x20,0x20,0x20,0x20,0x00, - 0x00,0x00,0x00,0x60,0x90,0x10,0x10,0x20,0x40,0x80,0xf0,0x00, - 0x00,0x00,0x00,0x60,0x90,0x10,0x60,0x10,0x10,0x90,0x60,0x00, - 0x00,0x00,0x00,0x10,0x30,0x50,0x50,0x90,0xf8,0x10,0x10,0x00, - 0x00,0x00,0x00,0x70,0x40,0x80,0xe0,0x10,0x10,0x90,0x60,0x00, - 0x00,0x00,0x00,0x60,0x90,0x80,0xa0,0xd0,0x90,0x90,0x60,0x00, - 0x00,0x00,0x00,0xf0,0x10,0x20,0x20,0x20,0x40,0x40,0x40,0x00, - 0x00,0x00,0x00,0x60,0x90,0x90,0x60,0x90,0x90,0x90,0x60,0x00, - 0x00,0x00,0x00,0x60,0x90,0x90,0xb0,0x50,0x10,0x90,0x60,0x00, - 0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x40,0x00, - 0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x40,0x40, - 0x00,0x00,0x00,0x00,0x00,0x10,0x60,0x80,0x60,0x10,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0xf0,0x00,0xf0,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x80,0x60,0x10,0x60,0x80,0x00,0x00, - 0x00,0x00,0x00,0x60,0x90,0x10,0x20,0x40,0x40,0x00,0x40,0x00, - 0x00,0x00,0x00,0x1c,0x22,0x5b,0xa5,0xa5,0xa5,0xa5,0x9e,0x41, - 0x00,0x00,0x00,0x20,0x50,0x50,0x50,0x50,0x70,0x88,0x88,0x00, - 0x00,0x00,0x00,0xf0,0x88,0x88,0xf0,0x88,0x88,0x88,0xf0,0x00, - 0x00,0x00,0x00,0x38,0x44,0x84,0x80,0x80,0x84,0x44,0x38,0x00, - 0x00,0x00,0x00,0xe0,0x90,0x88,0x88,0x88,0x88,0x90,0xe0,0x00, - 0x00,0x00,0x00,0xf8,0x80,0x80,0xf8,0x80,0x80,0x80,0xf8,0x00, - 0x00,0x00,0x00,0x78,0x40,0x40,0x70,0x40,0x40,0x40,0x40,0x00, - 0x00,0x00,0x00,0x38,0x44,0x84,0x80,0x9c,0x84,0x44,0x38,0x00, - 0x00,0x00,0x00,0x88,0x88,0x88,0xf8,0x88,0x88,0x88,0x88,0x00, - 0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00, - 0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x90,0x90,0x60,0x00, - 0x00,0x00,0x00,0x88,0x90,0xa0,0xe0,0xa0,0x90,0x90,0x88,0x00, - 0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0xf0,0x00, - 0x00,0x00,0x00,0x82,0xc6,0xc6,0xaa,0xaa,0xaa,0xaa,0x92,0x00, - 0x00,0x00,0x00,0x84,0xc4,0xa4,0xa4,0x94,0x94,0x8c,0x84,0x00, - 0x00,0x00,0x00,0x30,0x48,0x84,0x84,0x84,0x84,0x48,0x30,0x00, - 0x00,0x00,0x00,0xf0,0x88,0x88,0x88,0xf0,0x80,0x80,0x80,0x00, - 0x00,0x00,0x00,0x30,0x48,0x84,0x84,0x84,0x84,0x58,0x34,0x04, - 0x00,0x00,0x00,0x78,0x44,0x44,0x78,0x50,0x48,0x44,0x42,0x00, - 0x00,0x00,0x00,0x70,0x88,0x80,0x70,0x08,0x88,0x88,0x70,0x00, - 0x00,0x00,0x00,0xf8,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00, - 0x00,0x00,0x00,0x84,0x84,0x84,0x84,0x84,0x84,0x48,0x30,0x00, - 0x00,0x00,0x00,0x88,0x88,0x50,0x50,0x50,0x50,0x50,0x20,0x00, - 0x00,0x00,0x00,0x92,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0x44,0x00, - 0x00,0x00,0x00,0x84,0x48,0x48,0x30,0x30,0x48,0x48,0x84,0x00, - 0x00,0x00,0x00,0x88,0x50,0x50,0x20,0x20,0x20,0x20,0x20,0x00, - 0x00,0x00,0x00,0xf8,0x08,0x10,0x20,0x20,0x40,0x80,0xf8,0x00, - 0x00,0x00,0x00,0xc0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80, - 0x00,0x00,0x00,0x80,0x80,0x40,0x40,0x40,0x40,0x20,0x20,0x00, - 0x00,0x00,0x00,0xc0,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40, - 0x00,0x00,0x00,0x40,0xa0,0xa0,0xa0,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf8, - 0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0xe0,0x10,0x70,0x90,0x90,0x70,0x00, - 0x00,0x00,0x00,0x80,0x80,0xa0,0xd0,0x90,0x90,0xd0,0xa0,0x00, - 0x00,0x00,0x00,0x00,0x00,0x60,0x90,0x80,0x80,0x90,0x60,0x00, - 0x00,0x00,0x00,0x10,0x10,0x50,0xb0,0x90,0x90,0xb0,0x50,0x00, - 0x00,0x00,0x00,0x00,0x00,0x60,0x90,0xf0,0x80,0x90,0x60,0x00, - 0x00,0x00,0x00,0xc0,0x80,0xc0,0x80,0x80,0x80,0x80,0x80,0x00, - 0x00,0x00,0x00,0x00,0x00,0x50,0xb0,0x90,0x90,0xb0,0x50,0x10, - 0x00,0x00,0x00,0x80,0x80,0xa0,0xd0,0x90,0x90,0x90,0x90,0x00, - 0x00,0x00,0x00,0x80,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x00, - 0x00,0x00,0x00,0x80,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80, - 0x00,0x00,0x00,0x80,0x80,0x90,0xa0,0xc0,0xa0,0x90,0x90,0x00, - 0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00, - 0x00,0x00,0x00,0x00,0x00,0xa6,0xda,0x92,0x92,0x92,0x92,0x00, - 0x00,0x00,0x00,0x00,0x00,0xa0,0xd0,0x90,0x90,0x90,0x90,0x00, - 0x00,0x00,0x00,0x00,0x00,0x60,0x90,0x90,0x90,0x90,0x60,0x00, - 0x00,0x00,0x00,0x00,0x00,0xa0,0xd0,0x90,0x90,0xd0,0xa0,0x80, - 0x00,0x00,0x00,0x00,0x00,0x50,0xb0,0x90,0x90,0xb0,0x50,0x10, - 0x00,0x00,0x00,0x00,0x00,0xa0,0xc0,0x80,0x80,0x80,0x80,0x00, - 0x00,0x00,0x00,0x00,0x00,0xe0,0x90,0x40,0x20,0x90,0x60,0x00, - 0x00,0x00,0x00,0x80,0x80,0xc0,0x80,0x80,0x80,0x80,0xc0,0x00, - 0x00,0x00,0x00,0x00,0x00,0x90,0x90,0x90,0x90,0xb0,0x50,0x00, - 0x00,0x00,0x00,0x00,0x00,0x88,0x88,0x50,0x50,0x50,0x20,0x00, - 0x00,0x00,0x00,0x00,0x00,0x92,0xaa,0xaa,0xaa,0xaa,0x44,0x00, - 0x00,0x00,0x00,0x00,0x00,0x88,0x50,0x20,0x20,0x50,0x88,0x00, - 0x00,0x00,0x00,0x00,0x00,0x88,0x50,0x50,0x50,0x20,0x20,0x20, - 0x00,0x00,0x00,0x00,0x00,0xf0,0x10,0x20,0x40,0x80,0xf0,0x00, - 0x00,0x00,0x00,0xc0,0x80,0x80,0x80,0x00,0x80,0x80,0x80,0x80, - 0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80, - 0x00,0x00,0x00,0xc0,0x40,0x40,0x40,0x20,0x40,0x40,0x40,0x40, - 0x00,0x00,0x00,0x00,0x00,0x00,0xe8,0xb0,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0xe0,0xa0,0xa0,0xa0,0xa0,0xa0,0xe0,0x00}; - -const uint16_t ASCII8x8_Table [] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x40, - 0xa0, 0xa0, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x24, 0x24, 0xfe, 0x48, 0xfc, 0x48, 0x48, - 0x38, 0x54, 0x50, 0x38, 0x14, 0x14, 0x54, 0x38, - 0x44, 0xa8, 0xa8, 0x50, 0x14, 0x1a, 0x2a, 0x24, - 0x10, 0x28, 0x28, 0x10, 0x74, 0x4c, 0x4c, 0x30, - 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x08, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x08, - 0x10, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x10, - 0x00, 0x00, 0x24, 0x18, 0x3c, 0x18, 0x24, 0x00, - 0x00, 0x00, 0x10, 0x10, 0x7c, 0x10, 0x10, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x10, - 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, - 0x08, 0x08, 0x08, 0x10, 0x10, 0x20, 0x20, 0x20, - 0x18, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x18, - 0x08, 0x18, 0x28, 0x08, 0x08, 0x08, 0x08, 0x08, - 0x38, 0x44, 0x00, 0x04, 0x08, 0x10, 0x20, 0x7c, - 0x18, 0x24, 0x04, 0x18, 0x04, 0x04, 0x24, 0x18, - 0x04, 0x0c, 0x14, 0x24, 0x44, 0x7e, 0x04, 0x04, - 0x3c, 0x20, 0x20, 0x38, 0x04, 0x04, 0x24, 0x18, - 0x18, 0x24, 0x20, 0x38, 0x24, 0x24, 0x24, 0x18, - 0x3c, 0x04, 0x08, 0x08, 0x08, 0x10, 0x10, 0x10, - 0x18, 0x24, 0x24, 0x18, 0x24, 0x24, 0x24, 0x18, - 0x18, 0x24, 0x24, 0x24, 0x1c, 0x04, 0x24, 0x18, - 0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x00, 0x00, - 0x00, 0x00, 0x08, 0x00, 0x00, 0x08, 0x10, 0x00, - 0x00, 0x00, 0x04, 0x18, 0x20, 0x18, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x3c, 0x00, 0x3c, 0x00, 0x00, - 0x00, 0x00, 0x20, 0x18, 0x04, 0x18, 0x20, 0x00, - 0x18, 0x24, 0x04, 0x08, 0x10, 0x10, 0x00, 0x10, - 0x3c, 0x42, 0x99, 0xa5, 0xa5, 0x9d, 0x42, 0x38, - 0x38, 0x44, 0x44, 0x44, 0x7c, 0x44, 0x44, 0x44, - 0x78, 0x44, 0x44, 0x78, 0x44, 0x44, 0x44, 0x78, - 0x1c, 0x22, 0x42, 0x40, 0x40, 0x42, 0x22, 0x1c, - 0x70, 0x48, 0x44, 0x44, 0x44, 0x44, 0x48, 0x70, - 0x7c, 0x40, 0x40, 0x7c, 0x40, 0x40, 0x40, 0x7c, - 0x3c, 0x20, 0x20, 0x38, 0x20, 0x20, 0x20, 0x20, - 0x1c, 0x22, 0x42, 0x40, 0x4e, 0x42, 0x22, 0x1c, - 0x44, 0x44, 0x44, 0x7c, 0x44, 0x44, 0x44, 0x44, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x04, 0x04, 0x04, 0x04, 0x04, 0x24, 0x24, 0x18, - 0x44, 0x48, 0x50, 0x70, 0x50, 0x48, 0x48, 0x44, - 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x3c, - 0x82, 0xc6, 0xc6, 0xaa, 0xaa, 0xaa, 0xaa, 0x92, - 0x42, 0x62, 0x52, 0x52, 0x4a, 0x4a, 0x46, 0x42, - 0x18, 0x24, 0x42, 0x42, 0x42, 0x42, 0x24, 0x18, - 0x78, 0x44, 0x44, 0x44, 0x78, 0x40, 0x40, 0x40, - 0x18, 0x24, 0x42, 0x42, 0x42, 0x42, 0x2c, 0x1a, - 0x78, 0x44, 0x44, 0x78, 0x50, 0x48, 0x44, 0x42, - 0x38, 0x44, 0x40, 0x38, 0x04, 0x44, 0x44, 0x38, - 0x7c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x24, 0x18, - 0x44, 0x44, 0x28, 0x28, 0x28, 0x28, 0x28, 0x10, - 0x92, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x44, - 0x42, 0x24, 0x24, 0x18, 0x18, 0x24, 0x24, 0x42, - 0x44, 0x28, 0x28, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x7c, 0x04, 0x08, 0x10, 0x10, 0x20, 0x40, 0x7c, - 0x1c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x1c, - 0x10, 0x10, 0x08, 0x08, 0x08, 0x08, 0x04, 0x04, - 0x1c, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x1c, - 0x10, 0x28, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x20, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x18, 0x04, 0x1c, 0x24, 0x24, 0x1c, - 0x20, 0x20, 0x28, 0x34, 0x24, 0x24, 0x34, 0x28, - 0x00, 0x00, 0x18, 0x24, 0x20, 0x20, 0x24, 0x18, - 0x04, 0x04, 0x14, 0x2c, 0x24, 0x24, 0x2c, 0x14, - 0x00, 0x00, 0x18, 0x24, 0x3c, 0x20, 0x24, 0x18, - 0x00, 0x18, 0x10, 0x10, 0x18, 0x10, 0x10, 0x10, - 0x00, 0x18, 0x24, 0x24, 0x18, 0x04, 0x24, 0x18, - 0x20, 0x20, 0x28, 0x34, 0x24, 0x24, 0x24, 0x24, - 0x10, 0x00, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x08, 0x00, 0x08, 0x08, 0x08, 0x08, 0x28, 0x10, - 0x20, 0x20, 0x24, 0x28, 0x30, 0x28, 0x24, 0x24, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x00, 0x00, 0xa6, 0xda, 0x92, 0x92, 0x92, 0x92, - 0x00, 0x00, 0x28, 0x34, 0x24, 0x24, 0x24, 0x24, - 0x00, 0x00, 0x18, 0x24, 0x24, 0x24, 0x24, 0x18, - 0x00, 0x28, 0x34, 0x24, 0x38, 0x20, 0x20, 0x20, - 0x00, 0x14, 0x2c, 0x24, 0x1c, 0x04, 0x04, 0x04, - 0x00, 0x00, 0x2c, 0x30, 0x20, 0x20, 0x20, 0x20, - 0x00, 0x00, 0x18, 0x24, 0x10, 0x08, 0x24, 0x18, - 0x00, 0x10, 0x38, 0x10, 0x10, 0x10, 0x10, 0x18, - 0x00, 0x00, 0x24, 0x24, 0x24, 0x24, 0x2c, 0x14, - 0x00, 0x00, 0x44, 0x44, 0x28, 0x28, 0x28, 0x10, - 0x00, 0x00, 0x92, 0xaa, 0xaa, 0xaa, 0xaa, 0x44, - 0x00, 0x00, 0x44, 0x28, 0x10, 0x10, 0x28, 0x44, - 0x00, 0x28, 0x28, 0x28, 0x10, 0x10, 0x10, 0x10, - 0x00, 0x00, 0x3c, 0x04, 0x08, 0x10, 0x20, 0x3c, - 0x00, 0x08, 0x10, 0x10, 0x20, 0x10, 0x10, 0x08, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x00, 0x10, 0x08, 0x08, 0x04, 0x08, 0x08, 0x10, - 0x00, 0x00, 0x00, 0x60, 0x92, 0x0c, 0x00, 0x00, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; - - -sFONT Font16x24 = { - ASCII16x24_Table, - 16, /* Width */ - 24, /* Height */ -}; - -sFONT Font12x12 = { - ASCII12x12_Table, - 12, /* Width */ - 12, /* Height */ -}; - -sFONT Font8x12 = { - ASCII8x12_Table, - 8, /* Width */ - 12, /* Height */ -}; - - -sFONT Font8x8 = { - ASCII8x8_Table, - 8, /* Width */ - 8, /* Height */ -}; - -/** - * @} - */ - - -/** @defgroup FONTS_Private_Function_Prototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup FONTS_Private_Functions - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/fonts.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/fonts.h deleted file mode 100644 index 8e7450eec..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/fonts.h +++ /dev/null @@ -1,118 +0,0 @@ -/** - ****************************************************************************** - * @file fonts.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief Header for fonts.c - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FONTS_H -#define __FONTS_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup Common - * @{ - */ - -/** @addtogroup FONTS - * @{ - */ - -/** @defgroup FONTS_Exported_Types - * @{ - */ -typedef struct _tFont -{ - const uint16_t *table; - uint16_t Width; - uint16_t Height; - -} sFONT; - -extern sFONT Font16x24; -extern sFONT Font12x12; -extern sFONT Font8x12; -extern sFONT Font8x8; - -/** - * @} - */ - -/** @defgroup FONTS_Exported_Constants - * @{ - */ -#define LINE(x) ((x) * (((sFONT *)LCD_GetFont())->Height)) - -/** - * @} - */ - -/** @defgroup FONTS_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup FONTS_Exported_Functions - * @{ - */ -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __FONTS_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_ee.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_ee.c deleted file mode 100644 index 690e2dc90..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_ee.c +++ /dev/null @@ -1,854 +0,0 @@ -/** - ****************************************************************************** - * @file stm32_eval_i2c_ee.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file provides a set of functions needed to manage the I2C M24CXX - * EEPROM memory mounted on STM32xx-EVAL board (refer to stm32_eval.h - * to know about the boards supporting this memory). - * - * =================================================================== - * Note: This driver is intended for STM32F10x families devices only. - * =================================================================== - * - * It implements a high level communication layer for read and write - * from/to this memory. The needed STM32 hardware resources (I2C and - * GPIO) are defined in stm32xx_eval.h file, and the initialization is - * performed in sEE_LowLevel_Init() function declared in stm32xx_eval.c - * file. - * You can easily tailor this driver to any other development board, - * by just adapting the defines for hardware resources and - * sEE_LowLevel_Init() function. - * - * @note In this driver, basic read and write functions (sEE_ReadBuffer() - * and sEE_WritePage()) use the DMA to perform the data transfer - * to/from EEPROM memory (except when number of requested data is - * equal to 1). Thus, after calling these two functions, user - * application may perform other tasks while DMA is transferring - * data. The application should then monitor the variable holding - * the number of data in order to determine when the transfer is - * completed (variable decremented to 0). Stopping transfer tasks - * are performed into DMA interrupt handlers (which are integrated - * into this driver). - * - * +-----------------------------------------------------------------+ - * | Pin assignment | - * +---------------------------------------+-----------+-------------+ - * | STM32 I2C Pins | sEE | Pin | - * +---------------------------------------+-----------+-------------+ - * | . | E0(GND) | 1 (0V) | - * | . | E1(GND) | 2 (0V) | - * | . | E2(GND) | 3 (0V) | - * | . | E0(VSS) | 4 (0V) | - * | sEE_I2C_SDA_PIN/ SDA | SDA | 5 | - * | sEE_I2C_SCL_PIN/ SCL | SCL | 6 | - * | . | /WC(VDD)| 7 (3.3V) | - * | . | VDD | 8 (3.3V) | - * +---------------------------------------+-----------+-------------+ - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32_eval_i2c_ee.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup Common - * @{ - */ - -/** @addtogroup STM32_EVAL_I2C_EE - * @brief This file includes the I2C EEPROM driver of STM32-EVAL boards. - * @{ - */ - -/** @defgroup STM32_EVAL_I2C_EE_Private_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32_EVAL_I2C_EE_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32_EVAL_I2C_EE_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32_EVAL_I2C_EE_Private_Variables - * @{ - */ -__IO uint16_t sEEAddress = 0; -__IO uint32_t sEETimeout = sEE_LONG_TIMEOUT; -__IO uint16_t* sEEDataReadPointer; -__IO uint8_t* sEEDataWritePointer; -__IO uint8_t sEEDataNum; -/** - * @} - */ - - -/** @defgroup STM32_EVAL_I2C_EE_Private_Function_Prototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32_EVAL_I2C_EE_Private_Functions - * @{ - */ - -/** - * @brief DeInitializes peripherals used by the I2C EEPROM driver. - * @param None - * @retval None - */ -void sEE_DeInit(void) -{ - sEE_LowLevel_DeInit(); -} - -/** - * @brief Initializes peripherals used by the I2C EEPROM driver. - * @param None - * @retval None - */ -void sEE_Init(void) -{ - I2C_InitTypeDef I2C_InitStructure; - - sEE_LowLevel_Init(); - - /*!< I2C configuration */ - /* sEE_I2C configuration */ - I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; - I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2; - I2C_InitStructure.I2C_OwnAddress1 = I2C_SLAVE_ADDRESS7; - I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; - I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; - I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED; - - /* sEE_I2C Peripheral Enable */ - I2C_Cmd(sEE_I2C, ENABLE); - /* Apply sEE_I2C configuration after enabling it */ - I2C_Init(sEE_I2C, &I2C_InitStructure); - - /* Enable the sEE_I2C peripheral DMA requests */ - I2C_DMACmd(sEE_I2C, ENABLE); - -#if defined (sEE_M24C64_32) - /*!< Select the EEPROM address according to the state of E0, E1, E2 pins */ - sEEAddress = sEE_HW_ADDRESS; -#elif defined (sEE_M24C08) - /*!< depending on the sEE Address selected in the i2c_ee.h file */ - #ifdef sEE_Block0_ADDRESS - /*!< Select the sEE Block0 to write on */ - sEEAddress = sEE_Block0_ADDRESS; - #endif - - #ifdef sEE_Block1_ADDRESS - /*!< Select the sEE Block1 to write on */ - sEEAddress = sEE_Block1_ADDRESS; - #endif - - #ifdef sEE_Block2_ADDRESS - /*!< Select the sEE Block2 to write on */ - sEEAddress = sEE_Block2_ADDRESS; - #endif - - #ifdef sEE_Block3_ADDRESS - /*!< Select the sEE Block3 to write on */ - sEEAddress = sEE_Block3_ADDRESS; - #endif -#endif /*!< sEE_M24C64_32 */ -} - -/** - * @brief Reads a block of data from the EEPROM. - * @param pBuffer : pointer to the buffer that receives the data read from - * the EEPROM. - * @param ReadAddr : EEPROM's internal address to start reading from. - * @param NumByteToRead : pointer to the variable holding number of bytes to - * be read from the EEPROM. - * - * @note The variable pointed by NumByteToRead is reset to 0 when all the - * data are read from the EEPROM. Application should monitor this - * variable in order know when the transfer is complete. - * - * @note When number of data to be read is higher than 1, this function just - * configures the communication and enable the DMA channel to transfer data. - * Meanwhile, the user application may perform other tasks. - * When number of data to be read is 1, then the DMA is not used. The byte - * is read in polling mode. - * - * @retval sEE_OK (0) if operation is correctly performed, else return value - * different from sEE_OK (0) or the timeout user callback. - */ -uint32_t sEE_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t* NumByteToRead) -{ - /* Set the pointer to the Number of data to be read. This pointer will be used - by the DMA Transfer Completer interrupt Handler in order to reset the - variable to 0. User should check on this variable in order to know if the - DMA transfer has been complete or not. */ - sEEDataReadPointer = NumByteToRead; - - /*!< While the bus is busy */ - sEETimeout = sEE_LONG_TIMEOUT; - while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BUSY)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /*!< Send START condition */ - I2C_GenerateSTART(sEE_I2C, ENABLE); - - /*!< Test on EV5 and clear it (cleared by reading SR1 then writing to DR) */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /*!< Send EEPROM address for write */ - I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Transmitter); - - /*!< Test on EV6 and clear it */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - -#ifdef sEE_M24C08 - - /*!< Send the EEPROM's internal address to read from: Only one byte address */ - I2C_SendData(sEE_I2C, ReadAddr); - -#elif defined (sEE_M24C64_32) - - /*!< Send the EEPROM's internal address to read from: MSB of the address first */ - I2C_SendData(sEE_I2C, (uint8_t)((ReadAddr & 0xFF00) >> 8)); - - /*!< Test on EV8 and clear it */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /*!< Send the EEPROM's internal address to read from: LSB of the address */ - I2C_SendData(sEE_I2C, (uint8_t)(ReadAddr & 0x00FF)); - -#endif /*!< sEE_M24C08 */ - - /*!< Test on EV8 and clear it */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BTF) == RESET) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /*!< Send STRAT condition a second time */ - I2C_GenerateSTART(sEE_I2C, ENABLE); - - /*!< Test on EV5 and clear it (cleared by reading SR1 then writing to DR) */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /*!< Send EEPROM address for read */ - I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Receiver); - - /* If number of data to be read is 1, then DMA couldn't be used */ - /* One Byte Master Reception procedure (POLLING) ---------------------------*/ - if ((uint16_t)(*NumByteToRead) < 2) - { - /* Wait on ADDR flag to be set (ADDR is still not cleared at this level */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_ADDR) == RESET) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /*!< Disable Acknowledgement */ - I2C_AcknowledgeConfig(sEE_I2C, DISABLE); - - /* Call User callback for critical section start (should typically disable interrupts) */ - sEE_EnterCriticalSection_UserCallback(); - - /* Clear ADDR register by reading SR1 then SR2 register (SR1 has already been read) */ - (void)sEE_I2C->SR2; - - /*!< Send STOP Condition */ - I2C_GenerateSTOP(sEE_I2C, ENABLE); - - /* Call User callback for critical section end (should typically re-enable interrupts) */ - sEE_ExitCriticalSection_UserCallback(); - - /* Wait for the byte to be received */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_RXNE) == RESET) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /*!< Read the byte received from the EEPROM */ - *pBuffer = I2C_ReceiveData(sEE_I2C); - - /*!< Decrement the read bytes counter */ - (uint16_t)(*NumByteToRead)--; - - /* Wait to make sure that STOP control bit has been cleared */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(sEE_I2C->CR1 & I2C_CR1_STOP) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /*!< Re-Enable Acknowledgement to be ready for another reception */ - I2C_AcknowledgeConfig(sEE_I2C, ENABLE); - } - else/* More than one Byte Master Reception procedure (DMA) -----------------*/ - { - /*!< Test on EV6 and clear it */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /* Configure the DMA Rx Channel with the buffer address and the buffer size */ - sEE_LowLevel_DMAConfig((uint32_t)pBuffer, (uint16_t)(*NumByteToRead), sEE_DIRECTION_RX); - - /* Inform the DMA that the next End Of Transfer Signal will be the last one */ - I2C_DMALastTransferCmd(sEE_I2C, ENABLE); - - /* Enable the DMA Rx Channel */ - DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, ENABLE); - } - - /* If all operations OK, return sEE_OK (0) */ - return sEE_OK; -} - -/** - * @brief Writes more than one byte to the EEPROM with a single WRITE cycle. - * - * @note The number of bytes (combined to write start address) must not - * cross the EEPROM page boundary. This function can only write into - * the boundaries of an EEPROM page. - * This function doesn't check on boundaries condition (in this driver - * the function sEE_WriteBuffer() which calls sEE_WritePage() is - * responsible of checking on Page boundaries). - * - * @param pBuffer : pointer to the buffer containing the data to be written to - * the EEPROM. - * @param WriteAddr : EEPROM's internal address to write to. - * @param NumByteToWrite : pointer to the variable holding number of bytes to - * be written into the EEPROM. - * - * @note The variable pointed by NumByteToWrite is reset to 0 when all the - * data are written to the EEPROM. Application should monitor this - * variable in order know when the transfer is complete. - * - * @note This function just configure the communication and enable the DMA - * channel to transfer data. Meanwhile, the user application may perform - * other tasks in parallel. - * - * @retval sEE_OK (0) if operation is correctly performed, else return value - * different from sEE_OK (0) or the timeout user callback. - */ -uint32_t sEE_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t* NumByteToWrite) -{ - /* Set the pointer to the Number of data to be written. This pointer will be used - by the DMA Transfer Completer interrupt Handler in order to reset the - variable to 0. User should check on this variable in order to know if the - DMA transfer has been complete or not. */ - sEEDataWritePointer = NumByteToWrite; - - /*!< While the bus is busy */ - sEETimeout = sEE_LONG_TIMEOUT; - while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BUSY)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /*!< Send START condition */ - I2C_GenerateSTART(sEE_I2C, ENABLE); - - /*!< Test on EV5 and clear it */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /*!< Send EEPROM address for write */ - sEETimeout = sEE_FLAG_TIMEOUT; - I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Transmitter); - - /*!< Test on EV6 and clear it */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - -#ifdef sEE_M24C08 - - /*!< Send the EEPROM's internal address to write to : only one byte Address */ - I2C_SendData(sEE_I2C, WriteAddr); - -#elif defined(sEE_M24C64_32) - - /*!< Send the EEPROM's internal address to write to : MSB of the address first */ - I2C_SendData(sEE_I2C, (uint8_t)((WriteAddr & 0xFF00) >> 8)); - - /*!< Test on EV8 and clear it */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /*!< Send the EEPROM's internal address to write to : LSB of the address */ - I2C_SendData(sEE_I2C, (uint8_t)(WriteAddr & 0x00FF)); - -#endif /*!< sEE_M24C08 */ - - /*!< Test on EV8 and clear it */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /* Configure the DMA Tx Channel with the buffer address and the buffer size */ - sEE_LowLevel_DMAConfig((uint32_t)pBuffer, (uint8_t)(*NumByteToWrite), sEE_DIRECTION_TX); - - /* Enable the DMA Tx Channel */ - DMA_Cmd(sEE_I2C_DMA_CHANNEL_TX, ENABLE); - - /* If all operations OK, return sEE_OK (0) */ - return sEE_OK; -} - -/** - * @brief Writes buffer of data to the I2C EEPROM. - * @param pBuffer : pointer to the buffer containing the data to be written - * to the EEPROM. - * @param WriteAddr : EEPROM's internal address to write to. - * @param NumByteToWrite : number of bytes to write to the EEPROM. - * @retval None - */ -void sEE_WriteBuffer(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite) -{ - uint8_t NumOfPage = 0, NumOfSingle = 0, count = 0; - uint16_t Addr = 0; - - Addr = WriteAddr % sEE_PAGESIZE; - count = sEE_PAGESIZE - Addr; - NumOfPage = NumByteToWrite / sEE_PAGESIZE; - NumOfSingle = NumByteToWrite % sEE_PAGESIZE; - - /*!< If WriteAddr is sEE_PAGESIZE aligned */ - if(Addr == 0) - { - /*!< If NumByteToWrite < sEE_PAGESIZE */ - if(NumOfPage == 0) - { - /* Store the number of data to be written */ - sEEDataNum = NumOfSingle; - /* Start writing data */ - sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); - /* Wait transfer through DMA to be complete */ - sEETimeout = sEE_LONG_TIMEOUT; - while (sEEDataNum > 0) - { - if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; - } - sEE_WaitEepromStandbyState(); - } - /*!< If NumByteToWrite > sEE_PAGESIZE */ - else - { - while(NumOfPage--) - { - /* Store the number of data to be written */ - sEEDataNum = sEE_PAGESIZE; - sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); - /* Wait transfer through DMA to be complete */ - sEETimeout = sEE_LONG_TIMEOUT; - while (sEEDataNum > 0) - { - if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; - } - sEE_WaitEepromStandbyState(); - WriteAddr += sEE_PAGESIZE; - pBuffer += sEE_PAGESIZE; - } - - if(NumOfSingle!=0) - { - /* Store the number of data to be written */ - sEEDataNum = NumOfSingle; - sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); - /* Wait transfer through DMA to be complete */ - sEETimeout = sEE_LONG_TIMEOUT; - while (sEEDataNum > 0) - { - if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; - } - sEE_WaitEepromStandbyState(); - } - } - } - /*!< If WriteAddr is not sEE_PAGESIZE aligned */ - else - { - /*!< If NumByteToWrite < sEE_PAGESIZE */ - if(NumOfPage== 0) - { - /*!< If the number of data to be written is more than the remaining space - in the current page: */ - if (NumByteToWrite > count) - { - /* Store the number of data to be written */ - sEEDataNum = count; - /*!< Write the data conained in same page */ - sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); - /* Wait transfer through DMA to be complete */ - sEETimeout = sEE_LONG_TIMEOUT; - while (sEEDataNum > 0) - { - if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; - } - sEE_WaitEepromStandbyState(); - - /* Store the number of data to be written */ - sEEDataNum = (NumByteToWrite - count); - /*!< Write the remaining data in the following page */ - sEE_WritePage((uint8_t*)(pBuffer + count), (WriteAddr + count), (uint8_t*)(&sEEDataNum)); - /* Wait transfer through DMA to be complete */ - sEETimeout = sEE_LONG_TIMEOUT; - while (sEEDataNum > 0) - { - if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; - } - sEE_WaitEepromStandbyState(); - } - else - { - /* Store the number of data to be written */ - sEEDataNum = NumOfSingle; - sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); - /* Wait transfer through DMA to be complete */ - sEETimeout = sEE_LONG_TIMEOUT; - while (sEEDataNum > 0) - { - if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; - } - sEE_WaitEepromStandbyState(); - } - } - /*!< If NumByteToWrite > sEE_PAGESIZE */ - else - { - NumByteToWrite -= count; - NumOfPage = NumByteToWrite / sEE_PAGESIZE; - NumOfSingle = NumByteToWrite % sEE_PAGESIZE; - - if(count != 0) - { - /* Store the number of data to be written */ - sEEDataNum = count; - sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); - /* Wait transfer through DMA to be complete */ - sEETimeout = sEE_LONG_TIMEOUT; - while (sEEDataNum > 0) - { - if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; - } - sEE_WaitEepromStandbyState(); - WriteAddr += count; - pBuffer += count; - } - - while(NumOfPage--) - { - /* Store the number of data to be written */ - sEEDataNum = sEE_PAGESIZE; - sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); - /* Wait transfer through DMA to be complete */ - sEETimeout = sEE_LONG_TIMEOUT; - while (sEEDataNum > 0) - { - if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; - } - sEE_WaitEepromStandbyState(); - WriteAddr += sEE_PAGESIZE; - pBuffer += sEE_PAGESIZE; - } - if(NumOfSingle != 0) - { - /* Store the number of data to be written */ - sEEDataNum = NumOfSingle; - sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); - /* Wait transfer through DMA to be complete */ - sEETimeout = sEE_LONG_TIMEOUT; - while (sEEDataNum > 0) - { - if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; - } - sEE_WaitEepromStandbyState(); - } - } - } -} - -/** - * @brief Wait for EEPROM Standby state. - * - * @note This function allows to wait and check that EEPROM has finished the - * last Write operation. It is mostly used after Write operation: after - * receiving the buffer to be written, the EEPROM may need additional - * time to actually perform the write operation. During this time, it - * doesn't answer to I2C packets addressed to it. Once the write operation - * is complete the EEPROM responds to its address. - * - * @note It is not necessary to call this function after sEE_WriteBuffer() - * function (sEE_WriteBuffer() already calls this function after each - * write page operation). - * - * @param None - * @retval sEE_OK (0) if operation is correctly performed, else return value - * different from sEE_OK (0) or the timeout user callback. - */ -uint32_t sEE_WaitEepromStandbyState(void) -{ - __IO uint16_t tmpSR1 = 0; - __IO uint32_t sEETrials = 0; - - /*!< While the bus is busy */ - sEETimeout = sEE_LONG_TIMEOUT; - while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BUSY)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /* Keep looping till the slave acknowledge his address or maximum number - of trials is reached (this number is defined by sEE_MAX_TRIALS_NUMBER define - in stm32_eval_i2c_ee.h file) */ - while (1) - { - /*!< Send START condition */ - I2C_GenerateSTART(sEE_I2C, ENABLE); - - /*!< Test on EV5 and clear it */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /*!< Send EEPROM address for write */ - I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Transmitter); - - /* Wait for ADDR flag to be set (Slave acknowledged his address) */ - sEETimeout = sEE_LONG_TIMEOUT; - do - { - /* Get the current value of the SR1 register */ - tmpSR1 = sEE_I2C->SR1; - - /* Update the timeout value and exit if it reach 0 */ - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - /* Keep looping till the Address is acknowledged or the AF flag is - set (address not acknowledged at time) */ - while((tmpSR1 & (I2C_SR1_ADDR | I2C_SR1_AF)) == 0); - - /* Check if the ADDR flag has been set */ - if (tmpSR1 & I2C_SR1_ADDR) - { - /* Clear ADDR Flag by reading SR1 then SR2 registers (SR1 have already - been read) */ - (void)sEE_I2C->SR2; - - /*!< STOP condition */ - I2C_GenerateSTOP(sEE_I2C, ENABLE); - - /* Exit the function */ - return sEE_OK; - } - else - { - /*!< Clear AF flag */ - I2C_ClearFlag(sEE_I2C, I2C_FLAG_AF); - } - - /* Check if the maximum allowed numbe of trials has bee reached */ - if (sEETrials++ == sEE_MAX_TRIALS_NUMBER) - { - /* If the maximum number of trials has been reached, exit the function */ - return sEE_TIMEOUT_UserCallback(); - } - } -} - -/** - * @brief This function handles the DMA Tx Channel interrupt Handler. - * @param None - * @retval None - */ -void sEE_I2C_DMA_TX_IRQHandler(void) -{ - /* Check if the DMA transfer is complete */ - if(DMA_GetFlagStatus(sEE_I2C_DMA_FLAG_TX_TC) != RESET) - { - /* Disable the DMA Tx Channel and Clear all its Flags */ - DMA_Cmd(sEE_I2C_DMA_CHANNEL_TX, DISABLE); - DMA_ClearFlag(sEE_I2C_DMA_FLAG_TX_GL); - - /*!< Wait till all data have been physically transferred on the bus */ - sEETimeout = sEE_LONG_TIMEOUT; - while(!I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BTF)) - { - if((sEETimeout--) == 0) sEE_TIMEOUT_UserCallback(); - } - - /*!< Send STOP condition */ - I2C_GenerateSTOP(sEE_I2C, ENABLE); - - /* Perform a read on SR1 and SR2 register to clear eventualaly pending flags */ - (void)sEE_I2C->SR1; - (void)sEE_I2C->SR2; - - /* Reset the variable holding the number of data to be written */ - *sEEDataWritePointer = 0; - } -} - -/** - * @brief This function handles the DMA Rx Channel interrupt Handler. - * @param None - * @retval None - */ -void sEE_I2C_DMA_RX_IRQHandler(void) -{ - /* Check if the DMA transfer is complete */ - if(DMA_GetFlagStatus(sEE_I2C_DMA_FLAG_RX_TC) != RESET) - { - /*!< Send STOP Condition */ - I2C_GenerateSTOP(sEE_I2C, ENABLE); - - /* Disable the DMA Rx Channel and Clear all its Flags */ - DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, DISABLE); - DMA_ClearFlag(sEE_I2C_DMA_FLAG_RX_GL); - - /* Reset the variable holding the number of data to be read */ - *sEEDataReadPointer = 0; - } -} - -#ifdef USE_DEFAULT_TIMEOUT_CALLBACK -/** - * @brief Basic management of the timeout situation. - * @param None. - * @retval None. - */ -uint32_t sEE_TIMEOUT_UserCallback(void) -{ - /* Block communication and all processes */ - while (1) - { - } -} -#endif /* USE_DEFAULT_TIMEOUT_CALLBACK */ - -#ifdef USE_DEFAULT_CRITICAL_CALLBACK -/** - * @brief Start critical section: these callbacks should be typically used - * to disable interrupts when entering a critical section of I2C communication - * You may use default callbacks provided into this driver by uncommenting the - * define USE_DEFAULT_CRITICAL_CALLBACK. - * Or you can comment that line and implement these callbacks into your - * application. - * @param None. - * @retval None. - */ -void sEE_EnterCriticalSection_UserCallback(void) -{ - __disable_irq(); -} - -/** - * @brief Start and End of critical section: these callbacks should be typically used - * to re-enable interrupts when exiting a critical section of I2C communication - * You may use default callbacks provided into this driver by uncommenting the - * define USE_DEFAULT_CRITICAL_CALLBACK. - * Or you can comment that line and implement these callbacks into your - * application. - * @param None. - * @retval None. - */ -void sEE_ExitCriticalSection_UserCallback(void) -{ - __enable_irq(); -} -#endif /* USE_DEFAULT_CRITICAL_CALLBACK */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_ee.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_ee.h deleted file mode 100644 index dbed88e9e..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_ee.h +++ /dev/null @@ -1,201 +0,0 @@ -/** - ****************************************************************************** - * @file stm32_eval_i2c_ee.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains all the functions prototypes for the stm32_eval_i2c_ee - * firmware driver. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32_EVAL_I2C_EE_H -#define __STM32_EVAL_I2C_EE_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32_eval.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup Common - * @{ - */ - -/** @addtogroup STM32_EVAL_I2C_EE - * @{ - */ - -/** @defgroup STM32_EVAL_I2C_EE_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup STM32_EVAL_I2C_EE_Exported_Constants - * @{ - */ - -/* Uncomment this line to use the default start and end of critical section - callbacks (it disables then enabled all interrupts) */ -#define USE_DEFAULT_CRITICAL_CALLBACK -/* Start and End of critical section: these callbacks should be typically used - to disable interrupts when entering a critical section of I2C communication - You may use default callbacks provided into this driver by uncommenting the - define USE_DEFAULT_CRITICAL_CALLBACK. - Or you can comment that line and implement these callbacks into your - application */ - -/* Uncomment the following line to use the default sEE_TIMEOUT_UserCallback() - function implemented in stm32_evel_i2c_ee.c file. - sEE_TIMEOUT_UserCallback() function is called whenever a timeout condition - occure during communication (waiting on an event that doesn't occur, bus - errors, busy devices ...). */ -/* #define USE_DEFAULT_TIMEOUT_CALLBACK */ - -#if !defined (sEE_M24C08) && !defined (sEE_M24C64_32) -/* Use the defines below the choose the EEPROM type */ -/* #define sEE_M24C08*/ /* Support the device: M24C08. */ -/* note: Could support: M24C01, M24C02, M24C04 and M24C16 if the blocks and - HW address are correctly defined*/ -#define sEE_M24C64_32 /* Support the devices: M24C32 and M24C64 */ -#endif - -#ifdef sEE_M24C64_32 -/* For M24C32 and M24C64 devices, E0,E1 and E2 pins are all used for device - address selection (ne need for additional address lines). According to the - Harware connection on the board (on STM3210C-EVAL board E0 = E1 = E2 = 0) */ - - #define sEE_HW_ADDRESS 0xA0 /* E0 = E1 = E2 = 0 */ - -#elif defined (sEE_M24C08) -/* The M24C08W contains 4 blocks (128byte each) with the adresses below: E2 = 0 - EEPROM Addresses defines */ - #define sEE_Block0_ADDRESS 0xA0 /* E2 = 0 */ - /*#define sEE_Block1_ADDRESS 0xA2*/ /* E2 = 0 */ - /*#define sEE_Block2_ADDRESS 0xA4*/ /* E2 = 0 */ - /*#define sEE_Block3_ADDRESS 0xA6*/ /* E2 = 0 */ - -#endif /* sEE_M24C64_32 */ - -#define I2C_SPEED 300000 -#define I2C_SLAVE_ADDRESS7 0xA0 - -#if defined (sEE_M24C08) - #define sEE_PAGESIZE 16 -#elif defined (sEE_M24C64_32) - #define sEE_PAGESIZE 32 -#endif - -/* Maximum Timeout values for flags and events waiting loops. These timeouts are - not based on accurate values, they just guarantee that the application will - not remain stuck if the I2C communication is corrupted. - You may modify these timeout values depending on CPU frequency and application - conditions (interrupts routines ...). */ -#define sEE_FLAG_TIMEOUT ((uint32_t)0x1000) -#define sEE_LONG_TIMEOUT ((uint32_t)(10 * sEE_FLAG_TIMEOUT)) - -/* Maximum number of trials for sEE_WaitEepromStandbyState() function */ -#define sEE_MAX_TRIALS_NUMBER 150 - -/* Defintions for the state of the DMA transfer */ -#define sEE_STATE_READY 0 -#define sEE_STATE_BUSY 1 -#define sEE_STATE_ERROR 2 - -#define sEE_OK 0 -#define sEE_FAIL 1 - -/** - * @} - */ - -/** @defgroup STM32_EVAL_I2C_EE_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32_EVAL_I2C_EE_Exported_Functions - * @{ - */ -void sEE_DeInit(void); -void sEE_Init(void); -uint32_t sEE_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t* NumByteToRead); -uint32_t sEE_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t* NumByteToWrite); -void sEE_WriteBuffer(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite); -uint32_t sEE_WaitEepromStandbyState(void); - -/* USER Callbacks: These are functions for which prototypes only are declared in - EEPROM driver and that should be implemented into user applicaiton. */ -/* sEE_TIMEOUT_UserCallback() function is called whenever a timeout condition - occure during communication (waiting on an event that doesn't occur, bus - errors, busy devices ...). - You can use the default timeout callback implementation by uncommenting the - define USE_DEFAULT_TIMEOUT_CALLBACK in stm32_evel_i2c_ee.h file. - Typically the user implementation of this callback should reset I2C peripheral - and re-initialize communication or in worst case reset all the application. */ -uint32_t sEE_TIMEOUT_UserCallback(void); - -/* Start and End of critical section: these callbacks should be typically used - to disable interrupts when entering a critical section of I2C communication - You may use default callbacks provided into this driver by uncommenting the - define USE_DEFAULT_CRITICAL_CALLBACK in stm32_evel_i2c_ee.h file.. - Or you can comment that line and implement these callbacks into your - application */ -void sEE_EnterCriticalSection_UserCallback(void); -void sEE_ExitCriticalSection_UserCallback(void); - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32_EVAL_I2C_EE_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - - diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_tsensor.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_tsensor.c deleted file mode 100644 index 8dd73438c..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_tsensor.c +++ /dev/null @@ -1,977 +0,0 @@ -/** - ****************************************************************************** - * @file stm32_eval_i2c_tsensor.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file provides a set of functions needed to manage the I2C LM75 - * temperature sensor mounted on STM32xx-EVAL board (refer to stm32_eval.h - * to know about the boards supporting this sensor). - * It implements a high level communication layer for read and write - * from/to this sensor. The needed STM32 hardware resources (I2C and - * GPIO) are defined in stm32xx_eval.h file, and the initialization is - * performed in LM75_LowLevel_Init() function declared in stm32xx_eval.c - * file. - * - * Note: - * ----- - * This driver uses the DMA method to send and receive data on I2C bus, - * which allows higher efficiency and reliability of the communication. - * - * You can easily tailor this driver to any other development board, - * by just adapting the defines for hardware resources and - * LM75_LowLevel_Init() function. - * - * +-----------------------------------------------------------------+ - * | Pin assignment | - * +---------------------------------------+-----------+-------------+ - * | STM32 I2C Pins | STLM75 | Pin | - * +---------------------------------------+-----------+-------------+ - * | LM75_I2C_SDA_PIN/ SDA | SDA | 1 | - * | LM75_I2C_SCL_PIN/ SCL | SCL | 2 | - * | LM75_I2C_SMBUSALERT_PIN/ SMBUS ALERT | OS/INT | 3 | - * | . | GND | 4 (0V) | - * | . | GND | 5 (0V) | - * | . | GND | 6 (0V) | - * | . | GND | 7 (0V) | - * | . | VDD | 8 (3.3V)| - * +---------------------------------------+-----------+-------------+ - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32_eval_i2c_tsensor.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup Common - * @{ - */ - -/** @addtogroup STM32_EVAL_I2C_TSENSOR - * @brief This file includes the LM75 Temperature Sensor driver of - * STM32-EVAL boards. - * @{ - */ - -/** @defgroup STM32_EVAL_I2C_TSENSOR_Private_Types - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32_EVAL_I2C_TSENSOR_Private_Defines - * @{ - */ -#define LM75_SD_SET 0x01 /*!< Set SD bit in the configuration register */ -#define LM75_SD_RESET 0xFE /*!< Reset SD bit in the configuration register */ -/** - * @} - */ - -/** @defgroup STM32_EVAL_I2C_TSENSOR_Private_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32_EVAL_I2C_TSENSOR_Private_Variables - * @{ - */ - -__IO uint32_t LM75_Timeout = LM75_LONG_TIMEOUT; -/** - * @} - */ - -/** @defgroup STM32_EVAL_I2C_TSENSOR_Private_Function_Prototypes - * @{ - */ -static void LM75_DMA_Config(LM75_DMADirection_TypeDef Direction, uint8_t* buffer, uint8_t NumData); - -/** - * @} - */ - - -/** @defgroup STM32_EVAL_I2C_TSENSOR_Private_Functions - * @{ - */ - -/** - * @brief DeInitializes the LM75_I2C. - * @param None - * @retval None - */ -void LM75_DeInit(void) -{ - LM75_LowLevel_DeInit(); -} - -/** - * @brief Initializes the LM75_I2C. - * @param None - * @retval None - */ -void LM75_Init(void) -{ - I2C_InitTypeDef I2C_InitStructure; - - LM75_LowLevel_Init(); - - I2C_DeInit(LM75_I2C); - - /*!< LM75_I2C Init */ - I2C_InitStructure.I2C_Mode = I2C_Mode_SMBusHost; - I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2; - I2C_InitStructure.I2C_OwnAddress1 = 0x00; - I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; - I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; - I2C_InitStructure.I2C_ClockSpeed = LM75_I2C_SPEED; - I2C_Init(LM75_I2C, &I2C_InitStructure); - - /*!< Enable SMBus Alert interrupt */ - I2C_ITConfig(LM75_I2C, I2C_IT_ERR, ENABLE); - - /*!< LM75_I2C Init */ - I2C_Cmd(LM75_I2C, ENABLE); -} - - -/** - * @brief Configure the DMA Peripheral used to handle communication via I2C. - * @param None - * @retval None - */ - -static void LM75_DMA_Config(LM75_DMADirection_TypeDef Direction, uint8_t* buffer, uint8_t NumData) -{ - DMA_InitTypeDef DMA_InitStructure; - - RCC_AHBPeriphClockCmd(LM75_DMA_CLK, ENABLE); - - /* Initialize the DMA_PeripheralBaseAddr member */ - DMA_InitStructure.DMA_PeripheralBaseAddr = LM75_I2C_DR; - /* Initialize the DMA_MemoryBaseAddr member */ - DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)buffer; - /* Initialize the DMA_PeripheralInc member */ - DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - /* Initialize the DMA_MemoryInc member */ - DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - /* Initialize the DMA_PeripheralDataSize member */ - DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - /* Initialize the DMA_MemoryDataSize member */ - DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - /* Initialize the DMA_Mode member */ - DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; - /* Initialize the DMA_Priority member */ - DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; - /* Initialize the DMA_M2M member */ - DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; - - /* If using DMA for Reception */ - if (Direction == LM75_DMA_RX) - { - /* Initialize the DMA_DIR member */ - DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; - - /* Initialize the DMA_BufferSize member */ - DMA_InitStructure.DMA_BufferSize = NumData; - - DMA_DeInit(LM75_DMA_RX_CHANNEL); - - DMA_Init(LM75_DMA_RX_CHANNEL, &DMA_InitStructure); - } - /* If using DMA for Transmission */ - else if (Direction == LM75_DMA_TX) - { - /* Initialize the DMA_DIR member */ - DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST; - - /* Initialize the DMA_BufferSize member */ - DMA_InitStructure.DMA_BufferSize = NumData; - - DMA_DeInit(LM75_DMA_TX_CHANNEL); - - DMA_Init(LM75_DMA_TX_CHANNEL, &DMA_InitStructure); - } -} - - -/** - * @brief Checks the LM75 status. - * @param None - * @retval ErrorStatus: LM75 Status (ERROR or SUCCESS). - */ -ErrorStatus LM75_GetStatus(void) -{ - uint32_t I2C_TimeOut = I2C_TIMEOUT; - - /*!< Clear the LM75_I2C AF flag */ - I2C_ClearFlag(LM75_I2C, I2C_FLAG_AF); - - /*!< Enable LM75_I2C acknowledgement if it is already disabled by other function */ - I2C_AcknowledgeConfig(LM75_I2C, ENABLE); - - /*---------------------------- Transmission Phase ---------------------------*/ - - /*!< Send LM75_I2C START condition */ - I2C_GenerateSTART(LM75_I2C, ENABLE); - - /*!< Test on LM75_I2C EV5 and clear it */ - while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) && I2C_TimeOut) /*!< EV5 */ - { - I2C_TimeOut--; - } - if (I2C_TimeOut == 0) - { - return ERROR; - } - - I2C_TimeOut = I2C_TIMEOUT; - - /*!< Send STLM75 slave address for write */ - I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter); - - while ((!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) && I2C_TimeOut)/* EV6 */ - { - I2C_TimeOut--; - } - - if ((I2C_GetFlagStatus(LM75_I2C, I2C_FLAG_AF) != 0x00) || (I2C_TimeOut == 0)) - { - return ERROR; - } - else - { - return SUCCESS; - } -} -/** - * @brief Read the specified register from the LM75. - * @param RegName: specifies the LM75 register to be read. - * This member can be one of the following values: - * - LM75_REG_TEMP: temperature register - * - LM75_REG_TOS: Over-limit temperature register - * - LM75_REG_THYS: Hysteresis temperature register - * @retval LM75 register value. - */ -uint16_t LM75_ReadReg(uint8_t RegName) -{ - uint8_t LM75_BufferRX[2] ={0,0}; - uint16_t tmp = 0; - - /* Test on BUSY Flag */ - LM75_Timeout = LM75_LONG_TIMEOUT; - while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Configure DMA Peripheral */ - LM75_DMA_Config(LM75_DMA_RX, (uint8_t*)LM75_BufferRX, 2); - - /* Enable DMA NACK automatic generation */ - I2C_DMALastTransferCmd(LM75_I2C, ENABLE); - - /* Enable the I2C peripheral */ - I2C_GenerateSTART(LM75_I2C, ENABLE); - - /* Test on SB Flag */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Send device address for write */ - I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter); - - /* Test on ADDR Flag */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Send the device's internal address to write to */ - I2C_SendData(LM75_I2C, RegName); - - /* Test on TXE FLag (data sent) */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF))) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Send START condition a second time */ - I2C_GenerateSTART(LM75_I2C, ENABLE); - - /* Test on SB Flag */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Send LM75 address for read */ - I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Receiver); - - /* Test on ADDR Flag */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Enable I2C DMA request */ - I2C_DMACmd(LM75_I2C,ENABLE); - - /* Enable DMA RX Channel */ - DMA_Cmd(LM75_DMA_RX_CHANNEL, ENABLE); - - /* Wait until DMA Transfer Complete */ - LM75_Timeout = LM75_LONG_TIMEOUT; - while (!DMA_GetFlagStatus(LM75_DMA_RX_TCFLAG)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Send STOP Condition */ - I2C_GenerateSTOP(LM75_I2C, ENABLE); - - /* Disable DMA RX Channel */ - DMA_Cmd(LM75_DMA_RX_CHANNEL, DISABLE); - - /* Disable I2C DMA request */ - I2C_DMACmd(LM75_I2C,DISABLE); - - /* Clear DMA RX Transfer Complete Flag */ - DMA_ClearFlag(LM75_DMA_RX_TCFLAG); - - /*!< Store LM75_I2C received data */ - tmp = (uint16_t)(LM75_BufferRX[0] << 8); - tmp |= LM75_BufferRX[1]; - - /* return a Reg value */ - return (uint16_t)tmp; -} - -/** - * @brief Write to the specified register of the LM75. - * @param RegName: specifies the LM75 register to be written. - * This member can be one of the following values: - * - LM75_REG_TOS: Over-limit temperature register - * - LM75_REG_THYS: Hysteresis temperature register - * @param RegValue: value to be written to LM75 register. - * @retval None - */ -uint8_t LM75_WriteReg(uint8_t RegName, uint16_t RegValue) -{ - uint8_t LM75_BufferTX[2] ={0,0}; - LM75_BufferTX[0] = (uint8_t)(RegValue >> 8); - LM75_BufferTX[1] = (uint8_t)(RegValue); - - /* Test on BUSY Flag */ - LM75_Timeout = LM75_LONG_TIMEOUT; - while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Configure DMA Peripheral */ - LM75_DMA_Config(LM75_DMA_TX, (uint8_t*)LM75_BufferTX, 2); - - /* Enable the I2C peripheral */ - I2C_GenerateSTART(LM75_I2C, ENABLE); - - /* Test on SB Flag */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB) == RESET) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Transmit the slave address and enable writing operation */ - I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter); - - /* Test on ADDR Flag */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Transmit the first address for r/w operations */ - I2C_SendData(LM75_I2C, RegName); - - /* Test on TXE FLag (data sent) */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF))) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Enable I2C DMA request */ - I2C_DMACmd(LM75_I2C,ENABLE); - - /* Enable DMA TX Channel */ - DMA_Cmd(LM75_DMA_TX_CHANNEL, ENABLE); - - /* Wait until DMA Transfer Complete */ - LM75_Timeout = LM75_LONG_TIMEOUT; - while (!DMA_GetFlagStatus(LM75_DMA_TX_TCFLAG)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Wait until BTF Flag is set before generating STOP */ - LM75_Timeout = LM75_LONG_TIMEOUT; - while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Send STOP Condition */ - I2C_GenerateSTOP(LM75_I2C, ENABLE); - - /* Disable DMA TX Channel */ - DMA_Cmd(LM75_DMA_TX_CHANNEL, DISABLE); - - /* Disable I2C DMA request */ - I2C_DMACmd(LM75_I2C,DISABLE); - - /* Clear DMA TX Transfer Complete Flag */ - DMA_ClearFlag(LM75_DMA_TX_TCFLAG); - - return LM75_OK; -} - -/** - * @brief Read Temperature register of LM75: double temperature value. - * @param None - * @retval LM75 measured temperature value. - */ -uint16_t LM75_ReadTemp(void) -{ - uint8_t LM75_BufferRX[2] ={0,0}; - uint16_t tmp = 0; - - /* Test on BUSY Flag */ - LM75_Timeout = LM75_LONG_TIMEOUT; - while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Configure DMA Peripheral */ - LM75_DMA_Config(LM75_DMA_RX, (uint8_t*)LM75_BufferRX, 2); - - /* Enable DMA NACK automatic generation */ - I2C_DMALastTransferCmd(LM75_I2C, ENABLE); - - /* Enable the I2C peripheral */ - I2C_GenerateSTART(LM75_I2C, ENABLE); - - /* Test on SB Flag */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Send device address for write */ - I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter); - - /* Test on ADDR Flag */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Send the device's internal address to write to */ - I2C_SendData(LM75_I2C, LM75_REG_TEMP); - - /* Test on TXE FLag (data sent) */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF))) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Send START condition a second time */ - I2C_GenerateSTART(LM75_I2C, ENABLE); - - /* Test on SB Flag */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Send LM75 address for read */ - I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Receiver); - - /* Test on ADDR Flag */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Enable I2C DMA request */ - I2C_DMACmd(LM75_I2C,ENABLE); - - /* Enable DMA RX Channel */ - DMA_Cmd(LM75_DMA_RX_CHANNEL, ENABLE); - - /* Wait until DMA Transfer Complete */ - LM75_Timeout = LM75_LONG_TIMEOUT; - while (!DMA_GetFlagStatus(LM75_DMA_RX_TCFLAG)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Send STOP Condition */ - I2C_GenerateSTOP(LM75_I2C, ENABLE); - - /* Disable DMA RX Channel */ - DMA_Cmd(LM75_DMA_RX_CHANNEL, DISABLE); - - /* Disable I2C DMA request */ - I2C_DMACmd(LM75_I2C,DISABLE); - - /* Clear DMA RX Transfer Complete Flag */ - DMA_ClearFlag(LM75_DMA_RX_TCFLAG); - - /*!< Store LM75_I2C received data */ - tmp = (uint16_t)(LM75_BufferRX[0] << 8); - tmp |= LM75_BufferRX[1]; - - /*!< Return Temperature value */ - return (uint16_t)(tmp >> 7); -} - -/** - * @brief Read the configuration register from the LM75. - * @param None - * @retval LM75 configuration register value. - */ -uint8_t LM75_ReadConfReg(void) -{ - uint8_t LM75_BufferRX[2] ={0,0}; - - /* Test on BUSY Flag */ - LM75_Timeout = LM75_LONG_TIMEOUT; - while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Configure DMA Peripheral */ - LM75_DMA_Config(LM75_DMA_RX, (uint8_t*)LM75_BufferRX, 2); - - /* Enable DMA NACK automatic generation */ - I2C_DMALastTransferCmd(LM75_I2C, ENABLE); - - /* Enable the I2C peripheral */ - I2C_GenerateSTART(LM75_I2C, ENABLE); - - /* Test on SB Flag */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Send device address for write */ - I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter); - - /* Test on ADDR Flag */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Send the device's internal address to write to */ - I2C_SendData(LM75_I2C, LM75_REG_CONF); - - /* Test on TXE FLag (data sent) */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF))) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Send START condition a second time */ - I2C_GenerateSTART(LM75_I2C, ENABLE); - - /* Test on SB Flag */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Send LM75 address for read */ - I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Receiver); - - /* Test on ADDR Flag */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Enable I2C DMA request */ - I2C_DMACmd(LM75_I2C,ENABLE); - - /* Enable DMA RX Channel */ - DMA_Cmd(LM75_DMA_RX_CHANNEL, ENABLE); - - /* Wait until DMA Transfer Complete */ - LM75_Timeout = LM75_LONG_TIMEOUT; - while (!DMA_GetFlagStatus(LM75_DMA_RX_TCFLAG)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Send STOP Condition */ - I2C_GenerateSTOP(LM75_I2C, ENABLE); - - /* Disable DMA RX Channel */ - DMA_Cmd(LM75_DMA_RX_CHANNEL, DISABLE); - - /* Disable I2C DMA request */ - I2C_DMACmd(LM75_I2C,DISABLE); - - /* Clear DMA RX Transfer Complete Flag */ - DMA_ClearFlag(LM75_DMA_RX_TCFLAG); - - /*!< Return Temperature value */ - return (uint8_t)LM75_BufferRX[0]; -} - -/** - * @brief Write to the configuration register of the LM75. - * @param RegValue: sepecifies the value to be written to LM75 configuration - * register. - * @retval None - */ -uint8_t LM75_WriteConfReg(uint8_t RegValue) -{ - uint8_t LM75_BufferTX = 0; - LM75_BufferTX = (uint8_t)(RegValue); - - /* Test on BUSY Flag */ - LM75_Timeout = LM75_LONG_TIMEOUT; - while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Configure DMA Peripheral */ - LM75_DMA_Config(LM75_DMA_TX, (uint8_t*)(&LM75_BufferTX), 1); - - /* Enable the I2C peripheral */ - I2C_GenerateSTART(LM75_I2C, ENABLE); - - /* Test on SB Flag */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB) == RESET) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Transmit the slave address and enable writing operation */ - I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter); - - /* Test on ADDR Flag */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Transmit the first address for r/w operations */ - I2C_SendData(LM75_I2C, LM75_REG_CONF); - - /* Test on TXE FLag (data sent) */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF))) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Enable I2C DMA request */ - I2C_DMACmd(LM75_I2C,ENABLE); - - /* Enable DMA TX Channel */ - DMA_Cmd(LM75_DMA_TX_CHANNEL, ENABLE); - - /* Wait until DMA Transfer Complete */ - LM75_Timeout = LM75_LONG_TIMEOUT; - while (!DMA_GetFlagStatus(LM75_DMA_TX_TCFLAG)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Wait until BTF Flag is set before generating STOP */ - LM75_Timeout = LM75_LONG_TIMEOUT; - while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF))) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Send STOP Condition */ - I2C_GenerateSTOP(LM75_I2C, ENABLE); - - /* Disable DMA TX Channel */ - DMA_Cmd(LM75_DMA_TX_CHANNEL, DISABLE); - - /* Disable I2C DMA request */ - I2C_DMACmd(LM75_I2C,DISABLE); - - /* Clear DMA TX Transfer Complete Flag */ - DMA_ClearFlag(LM75_DMA_TX_TCFLAG); - - return LM75_OK; - -} - -/** - * @brief Enables or disables the LM75. - * @param NewState: specifies the LM75 new status. This parameter can be ENABLE - * or DISABLE. - * @retval None - */ -uint8_t LM75_ShutDown(FunctionalState NewState) -{ - uint8_t LM75_BufferRX[2] ={0,0}; - uint8_t LM75_BufferTX = 0; - __IO uint8_t RegValue = 0; - - /* Test on BUSY Flag */ - LM75_Timeout = LM75_LONG_TIMEOUT; - while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Configure DMA Peripheral */ - LM75_DMA_Config(LM75_DMA_RX, (uint8_t*)LM75_BufferRX, 2); - - /* Enable DMA NACK automatic generation */ - I2C_DMALastTransferCmd(LM75_I2C, ENABLE); - - /* Enable the I2C peripheral */ - I2C_GenerateSTART(LM75_I2C, ENABLE); - - /* Test on SB Flag */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Send device address for write */ - I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter); - - /* Test on ADDR Flag */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Send the device's internal address to write to */ - I2C_SendData(LM75_I2C, LM75_REG_CONF); - - /* Test on TXE FLag (data sent) */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF))) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Send START condition a second time */ - I2C_GenerateSTART(LM75_I2C, ENABLE); - - /* Test on SB Flag */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Send LM75 address for read */ - I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Receiver); - - /* Test on ADDR Flag */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Enable I2C DMA request */ - I2C_DMACmd(LM75_I2C,ENABLE); - - /* Enable DMA RX Channel */ - DMA_Cmd(LM75_DMA_RX_CHANNEL, ENABLE); - - /* Wait until DMA Transfer Complete */ - LM75_Timeout = LM75_LONG_TIMEOUT; - while (!DMA_GetFlagStatus(LM75_DMA_RX_TCFLAG)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Send STOP Condition */ - I2C_GenerateSTOP(LM75_I2C, ENABLE); - - /* Disable DMA RX Channel */ - DMA_Cmd(LM75_DMA_RX_CHANNEL, DISABLE); - - /* Disable I2C DMA request */ - I2C_DMACmd(LM75_I2C,DISABLE); - - /* Clear DMA RX Transfer Complete Flag */ - DMA_ClearFlag(LM75_DMA_RX_TCFLAG); - - /*!< Get received data */ - RegValue = (uint8_t)LM75_BufferRX[0]; - - /*---------------------------- Transmission Phase ---------------------------*/ - - /*!< Enable or disable SD bit */ - if (NewState != DISABLE) - { - /*!< Enable LM75 */ - LM75_BufferTX = RegValue & LM75_SD_RESET; - } - else - { - /*!< Disable LM75 */ - LM75_BufferTX = RegValue | LM75_SD_SET; - } - - /* Test on BUSY Flag */ - LM75_Timeout = LM75_LONG_TIMEOUT; - while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Configure DMA Peripheral */ - LM75_DMA_Config(LM75_DMA_TX, (uint8_t*)(&LM75_BufferTX), 1); - - /* Enable the I2C peripheral */ - I2C_GenerateSTART(LM75_I2C, ENABLE); - - /* Test on SB Flag */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB) == RESET) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Transmit the slave address and enable writing operation */ - I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter); - - /* Test on ADDR Flag */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Transmit the first address for r/w operations */ - I2C_SendData(LM75_I2C, LM75_REG_CONF); - - /* Test on TXE FLag (data sent) */ - LM75_Timeout = LM75_FLAG_TIMEOUT; - while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF))) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Enable I2C DMA request */ - I2C_DMACmd(LM75_I2C,ENABLE); - - /* Enable DMA TX Channel */ - DMA_Cmd(LM75_DMA_TX_CHANNEL, ENABLE); - - /* Wait until DMA Transfer Complete */ - LM75_Timeout = LM75_LONG_TIMEOUT; - while (!DMA_GetFlagStatus(LM75_DMA_TX_TCFLAG)) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Wait until BTF Flag is set before generating STOP */ - LM75_Timeout = LM75_LONG_TIMEOUT; - while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF))) - { - if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback(); - } - - /* Send STOP Condition */ - I2C_GenerateSTOP(LM75_I2C, ENABLE); - - /* Disable DMA TX Channel */ - DMA_Cmd(LM75_DMA_TX_CHANNEL, DISABLE); - - /* Disable I2C DMA request */ - I2C_DMACmd(LM75_I2C,DISABLE); - - /* Clear DMA TX Transfer Complete Flag */ - DMA_ClearFlag(LM75_DMA_TX_TCFLAG); - - return LM75_OK; -} - -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_tsensor.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_tsensor.h deleted file mode 100644 index 2e0437b26..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_tsensor.h +++ /dev/null @@ -1,173 +0,0 @@ -/** - ****************************************************************************** - * @file stm32_eval_i2c_tsensor.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains all the functions prototypes for the - * stm32_eval_i2c_tsensor firmware driver. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32_EVAL_I2C_TSENSOR_H -#define __STM32_EVAL_I2C_TSENSOR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32_eval.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup Common - * @{ - */ - -/** @addtogroup STM32_EVAL_I2C_TSENSOR - * @{ - */ - -/** @defgroup STM32_EVAL_I2C_TSENSOR_Exported_Types - * @{ - */ - - /** - * @brief IOE DMA Direction - */ -typedef enum -{ - LM75_DMA_TX = 0, - LM75_DMA_RX = 1 -}LM75_DMADirection_TypeDef; - -/** - * @brief TSENSOR Status - */ -typedef enum -{ - LM75_OK = 0, - LM75_FAIL -}LM75_Status_TypDef; - -/** - * @} - */ - -/** @defgroup STM32_EVAL_I2C_TSENSOR_Exported_Constants - * @{ - */ - -/* Uncomment the following line to use Timeout_User_Callback LM75_TimeoutUserCallback(). - If This Callback is enabled, it should be implemented by user in main function . - LM75_TimeoutUserCallback() function is called whenever a timeout condition - occure during communication (waiting on an event that doesn't occur, bus - errors, busy devices ...). */ -/* #define USE_TIMEOUT_USER_CALLBACK */ - -/* Maximum Timeout values for flags and events waiting loops. These timeouts are - not based on accurate values, they just guarantee that the application will - not remain stuck if the I2C communication is corrupted. - You may modify these timeout values depending on CPU frequency and application - conditions (interrupts routines ...). */ -#define LM75_FLAG_TIMEOUT ((uint32_t)0x1000) -#define LM75_LONG_TIMEOUT ((uint32_t)(10 * LM75_FLAG_TIMEOUT)) - - -/** - * @brief Block Size - */ -#define LM75_REG_TEMP 0x00 /*!< Temperature Register of LM75 */ -#define LM75_REG_CONF 0x01 /*!< Configuration Register of LM75 */ -#define LM75_REG_THYS 0x02 /*!< Temperature Register of LM75 */ -#define LM75_REG_TOS 0x03 /*!< Over-temp Shutdown threshold Register of LM75 */ -#define I2C_TIMEOUT ((uint32_t)0x3FFFF) /*!< I2C Time out */ -#define LM75_ADDR 0x90 /*!< LM75 address */ -#define LM75_I2C_SPEED 100000 /*!< I2C Speed */ - - - -/** - * @} - */ - -/** @defgroup STM32_EVAL_I2C_TSENSOR_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32_EVAL_I2C_TSENSOR_Exported_Functions - * @{ - */ -void LM75_DeInit(void); -void LM75_Init(void); -ErrorStatus LM75_GetStatus(void); -uint16_t LM75_ReadTemp(void); -uint16_t LM75_ReadReg(uint8_t RegName); -uint8_t LM75_WriteReg(uint8_t RegName, uint16_t RegValue); -uint8_t LM75_ReadConfReg(void); -uint8_t LM75_WriteConfReg(uint8_t RegValue); -uint8_t LM75_ShutDown(FunctionalState NewState); - -/** - * @brief Timeout user callback function. This function is called when a timeout - * condition occurs during communication with IO Expander. Only protoype - * of this function is decalred in IO Expander driver. Its implementation - * may be done into user application. This function may typically stop - * current operations and reset the I2C peripheral and IO Expander. - * To enable this function use uncomment the define USE_TIMEOUT_USER_CALLBACK - * at the top of this file. - */ -#ifdef USE_TIMEOUT_USER_CALLBACK - uint8_t LM75_TIMEOUT_UserCallback(void); -#else - #define LM75_TIMEOUT_UserCallback() LM75_FAIL -#endif /* USE_TIMEOUT_USER_CALLBACK */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32_EVAL_I2C_TSENSOR_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_sdio_sd.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_sdio_sd.c deleted file mode 100644 index 2f1143f6f..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_sdio_sd.c +++ /dev/null @@ -1,2502 +0,0 @@ -/** - ****************************************************************************** - * @file stm32_eval_sdio_sd.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file provides a set of functions needed to manage the SDIO SD - * Card memory mounted on STM32xx-EVAL board (refer to stm32_eval.h - * to know about the boards supporting this memory). - * - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * It implements a high level communication layer for read and write - * from/to this memory. The needed STM32 hardware resources (SDIO and - * GPIO) are defined in stm32xx_eval.h file, and the initialization is - * performed in SD_LowLevel_Init() function declared in stm32xx_eval.c - * file. - * You can easily tailor this driver to any other development board, - * by just adapting the defines for hardware resources and - * SD_LowLevel_Init() function. - * - * A - SD Card Initialization and configuration - * ============================================ - * - To initialize the SD Card, use the SD_Init() function. It - * Initializes the SD Card and put it into StandBy State (Ready - * for data transfer). This function provide the following operations: - * - * 1 - Apply the SD Card initialization process at 400KHz and check - * the SD Card type (Standard Capacity or High Capacity). You - * can change or adapt this frequency by adjusting the - * "SDIO_INIT_CLK_DIV" define inside the stm32xx_eval.h file. - * The SD Card frequency (SDIO_CK) is computed as follows: - * - * +---------------------------------------------+ - * | SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) | - * +---------------------------------------------+ - * - * In initialization mode and according to the SD Card standard, - * make sure that the SDIO_CK frequency don't exceed 400KHz. - * - * 2 - Get the SD CID and CSD data. All these information are - * managed by the SDCardInfo structure. This structure provide - * also ready computed SD Card capacity and Block size. - * - * 3 - Configure the SD Card Data transfer frequency. By Default, - * the card transfer frequency is set to 24MHz. You can change - * or adapt this frequency by adjusting the "SDIO_TRANSFER_CLK_DIV" - * define inside the stm32xx_eval.h file. - * The SD Card frequency (SDIO_CK) is computed as follows: - * - * +---------------------------------------------+ - * | SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) | - * +---------------------------------------------+ - * - * In transfer mode and according to the SD Card standard, - * make sure that the SDIO_CK frequency don't exceed 25MHz - * and 50MHz in High-speed mode switch. - * To be able to use a frequency higher than 24MHz, you should - * use the SDIO peripheral in bypass mode. Refer to the - * corresponding reference manual for more details. - * - * 4 - Select the corresponding SD Card according to the address - * read with the step 2. - * - * 5 - Configure the SD Card in wide bus mode: 4-bits data. - * - * B - SD Card Read operation - * ========================== - * - You can read SD card by using two function: SD_ReadBlock() and - * SD_ReadMultiBlocks() functions. These functions support only - * 512-byte block length. - * - The SD_ReadBlock() function read only one block (512-byte). This - * function can transfer the data using DMA controller or using - * polling mode. To select between DMA or polling mode refer to - * "SD_DMA_MODE" or "SD_POLLING_MODE" inside the stm32_eval_sdio_sd.h - * file and uncomment the corresponding line. By default the SD DMA - * mode is selected - * - The SD_ReadMultiBlocks() function read only mutli blocks (multiple - * of 512-byte). - * - Any read operation should be followed by two functions to check - * if the DMA Controller and SD Card status. - * - SD_ReadWaitOperation(): this function insure that the DMA - * controller has finished all data transfer. - * - SD_GetStatus(): to check that the SD Card has finished the - * data transfer and it is ready for data. - * - * - The DMA transfer is finished by the SDIO Data End interrupt. User - * has to call the SD_ProcessIRQ() function inside the SDIO_IRQHandler(). - * Don't forget to enable the SDIO_IRQn interrupt using the NVIC controller. - * - * C - SD Card Write operation - * =========================== - * - You can write SD card by using two function: SD_WriteBlock() and - * SD_WriteMultiBlocks() functions. These functions support only - * 512-byte block length. - * - The SD_WriteBlock() function write only one block (512-byte). This - * function can transfer the data using DMA controller or using - * polling mode. To select between DMA or polling mode refer to - * "SD_DMA_MODE" or "SD_POLLING_MODE" inside the stm32_eval_sdio_sd.h - * file and uncomment the corresponding line. By default the SD DMA - * mode is selected - * - The SD_WriteMultiBlocks() function write only mutli blocks (multiple - * of 512-byte). - * - Any write operation should be followed by two functions to check - * if the DMA Controller and SD Card status. - * - SD_ReadWaitOperation(): this function insure that the DMA - * controller has finished all data transfer. - * - SD_GetStatus(): to check that the SD Card has finished the - * data transfer and it is ready for data. - * - * - The DMA transfer is finished by the SDIO Data End interrupt. User - * has to call the SD_ProcessIRQ() function inside the SDIO_IRQHandler(). - * Don't forget to enable the SDIO_IRQn interrupt using the NVIC controller. - - * - * D - SD card status - * ================== - * - At any time, you can check the SD Card status and get the SD card - * state by using the SD_GetStatus() function. This function checks - * first if the SD card is still connected and then get the internal - * SD Card transfer state. - * - You can also get the SD card SD Status register by using the - * SD_SendSDStatus() function. - * - * E - Programming Model - * ===================== - * Status = SD_Init(); // Initialization Step as described in section A - * - * // SDIO Interrupt ENABLE - * NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn; - * NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; - * NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; - * NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - * NVIC_Init(&NVIC_InitStructure); - * - * // Write operation as described in Section C - * Status = SD_WriteBlock(buffer, address, 512); - * Status = SD_WaitWriteOperation(); - * while(SD_GetStatus() != SD_TRANSFER_OK); - * - * Status = SD_WriteMultiBlocks(buffer, address, 512, NUMBEROFBLOCKS); - * Status = SD_WaitWriteOperation(); - * while(SD_GetStatus() != SD_TRANSFER_OK); - * - * // Read operation as described in Section B - * Status = SD_ReadBlock(buffer, address, 512); - * Status = SD_WaitReadOperation(); - * while(SD_GetStatus() != SD_TRANSFER_OK); - * - * Status = SD_ReadMultiBlocks(buffer, address, 512, NUMBEROFBLOCKS); - * Status = SD_WaitReadOperation(); - * while(SD_GetStatus() != SD_TRANSFER_OK); - * - * - * STM32 SDIO Pin assignment - * ========================= - * +-----------------------------------------------------------+ - * | Pin assignment | - * +-----------------------------+---------------+-------------+ - * | STM32 SDIO Pins | SD | Pin | - * +-----------------------------+---------------+-------------+ - * | SDIO D2 | D2 | 1 | - * | SDIO D3 | D3 | 2 | - * | SDIO CMD | CMD | 3 | - * | | VCC | 4 (3.3 V)| - * | SDIO CLK | CLK | 5 | - * | | GND | 6 (0 V) | - * | SDIO D0 | D0 | 7 | - * | SDIO D1 | D1 | 8 | - * +-----------------------------+---------------+-------------+ - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32_eval_sdio_sd.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup Common - * @{ - */ - -/** @addtogroup STM32_EVAL_SDIO_SD - * @brief This file provides all the SD Card driver firmware functions. - * @{ - */ - -/** @defgroup STM32_EVAL_SDIO_SD_Private_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32_EVAL_SDIO_SD_Private_Defines - * @{ - */ -/** - * @brief SDIO Static flags, TimeOut, FIFO Address - */ -#define NULL 0 -#define SDIO_STATIC_FLAGS ((uint32_t)0x000005FF) -#define SDIO_CMD0TIMEOUT ((uint32_t)0x00010000) - -/** - * @brief Mask for errors Card Status R1 (OCR Register) - */ -#define SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000) -#define SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000) -#define SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000) -#define SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000) -#define SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000) -#define SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000) -#define SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000) -#define SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000) -#define SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000) -#define SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000) -#define SD_OCR_CC_ERROR ((uint32_t)0x00100000) -#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000) -#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000) -#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000) -#define SD_OCR_CID_CSD_OVERWRIETE ((uint32_t)0x00010000) -#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000) -#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000) -#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000) -#define SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008) -#define SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008) - -/** - * @brief Masks for R6 Response - */ -#define SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000) -#define SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000) -#define SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000) - -#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000) -#define SD_HIGH_CAPACITY ((uint32_t)0x40000000) -#define SD_STD_CAPACITY ((uint32_t)0x00000000) -#define SD_CHECK_PATTERN ((uint32_t)0x000001AA) - -#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF) -#define SD_ALLZERO ((uint32_t)0x00000000) - -#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000) -#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000) -#define SD_CARD_LOCKED ((uint32_t)0x02000000) - -#define SD_DATATIMEOUT ((uint32_t)0xFFFFFFFF) -#define SD_0TO7BITS ((uint32_t)0x000000FF) -#define SD_8TO15BITS ((uint32_t)0x0000FF00) -#define SD_16TO23BITS ((uint32_t)0x00FF0000) -#define SD_24TO31BITS ((uint32_t)0xFF000000) -#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF) - -#define SD_HALFFIFO ((uint32_t)0x00000008) -#define SD_HALFFIFOBYTES ((uint32_t)0x00000020) - -/** - * @brief Command Class Supported - */ -#define SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080) -#define SD_CCCC_WRITE_PROT ((uint32_t)0x00000040) -#define SD_CCCC_ERASE ((uint32_t)0x00000020) - -/** - * @brief Following commands are SD Card Specific commands. - * SDIO_APP_CMD should be sent before sending these commands. - */ -#define SDIO_SEND_IF_COND ((uint32_t)0x00000008) - -/** - * @} - */ - - -/** @defgroup STM32_EVAL_SDIO_SD_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32_EVAL_SDIO_SD_Private_Variables - * @{ - */ -static uint32_t CardType = SDIO_STD_CAPACITY_SD_CARD_V1_1; -static uint32_t CSD_Tab[4], CID_Tab[4], RCA = 0; -static uint8_t SDSTATUS_Tab[16]; -__IO uint32_t StopCondition = 0; -__IO SD_Error TransferError = SD_OK; -__IO uint32_t TransferEnd = 0; -SD_CardInfo SDCardInfo; - -SDIO_InitTypeDef SDIO_InitStructure; -SDIO_CmdInitTypeDef SDIO_CmdInitStructure; -SDIO_DataInitTypeDef SDIO_DataInitStructure; -/** - * @} - */ - - -/** @defgroup STM32_EVAL_SDIO_SD_Private_Function_Prototypes - * @{ - */ -static SD_Error CmdError(void); -static SD_Error CmdResp1Error(uint8_t cmd); -static SD_Error CmdResp7Error(void); -static SD_Error CmdResp3Error(void); -static SD_Error CmdResp2Error(void); -static SD_Error CmdResp6Error(uint8_t cmd, uint16_t *prca); -static SD_Error SDEnWideBus(FunctionalState NewState); -static SD_Error IsCardProgramming(uint8_t *pstatus); -static SD_Error FindSCR(uint16_t rca, uint32_t *pscr); -uint8_t convert_from_bytes_to_power_of_two(uint16_t NumberOfBytes); - -/** - * @} - */ - - -/** @defgroup STM32_EVAL_SDIO_SD_Private_Functions - * @{ - */ - -/** - * @brief DeInitializes the SDIO interface. - * @param None - * @retval None - */ -void SD_DeInit(void) -{ - SD_LowLevel_DeInit(); -} - -/** - * @brief Initializes the SD Card and put it into StandBy State (Ready for data - * transfer). - * @param None - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_Init(void) -{ - SD_Error errorstatus = SD_OK; - - /* SDIO Peripheral Low Level Init */ - SD_LowLevel_Init(); - - SDIO_DeInit(); - - errorstatus = SD_PowerON(); - - if (errorstatus != SD_OK) - { - /*!< CMD Response TimeOut (wait for CMDSENT flag) */ - return(errorstatus); - } - - errorstatus = SD_InitializeCards(); - - if (errorstatus != SD_OK) - { - /*!< CMD Response TimeOut (wait for CMDSENT flag) */ - return(errorstatus); - } - - /*!< Configure the SDIO peripheral */ - /*!< SDIOCLK = HCLK, SDIO_CK = HCLK/(2 + SDIO_TRANSFER_CLK_DIV) */ - /*!< on STM32F2xx devices, SDIOCLK is fixed to 48MHz */ - SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV; - SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; - SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; - SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; - SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b; - SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; - SDIO_Init(&SDIO_InitStructure); - - if (errorstatus == SD_OK) - { - /*----------------- Read CSD/CID MSD registers ------------------*/ - errorstatus = SD_GetCardInfo(&SDCardInfo); - } - - if (errorstatus == SD_OK) - { - /*----------------- Select Card --------------------------------*/ - errorstatus = SD_SelectDeselect((uint32_t) (SDCardInfo.RCA << 16)); - } - - if (errorstatus == SD_OK) - { - errorstatus = SD_EnableWideBusOperation(SDIO_BusWide_4b); - } - - return(errorstatus); -} - -/** - * @brief Gets the cuurent sd card data transfer status. - * @param None - * @retval SDTransferState: Data Transfer state. - * This value can be: - * - SD_TRANSFER_OK: No data transfer is acting - * - SD_TRANSFER_BUSY: Data transfer is acting - */ -SDTransferState SD_GetStatus(void) -{ - SDCardState cardstate = SD_CARD_TRANSFER; - - cardstate = SD_GetState(); - - if (cardstate == SD_CARD_TRANSFER) - { - return(SD_TRANSFER_OK); - } - else if(cardstate == SD_CARD_ERROR) - { - return (SD_TRANSFER_ERROR); - } - else - { - return(SD_TRANSFER_BUSY); - } -} - -/** - * @brief Returns the current card's state. - * @param None - * @retval SDCardState: SD Card Error or SD Card Current State. - */ -SDCardState SD_GetState(void) -{ - uint32_t resp1 = 0; - - if(SD_Detect()== SD_PRESENT) - { - if (SD_SendStatus(&resp1) != SD_OK) - { - return SD_CARD_ERROR; - } - else - { - return (SDCardState)((resp1 >> 9) & 0x0F); - } - } - else - { - return SD_CARD_ERROR; - } -} - -/** - * @brief Detect if SD card is correctly plugged in the memory slot. - * @param None - * @retval Return if SD is detected or not - */ -uint8_t SD_Detect(void) -{ - __IO uint8_t status = SD_PRESENT; - - /*!< Check GPIO to detect SD */ - if (GPIO_ReadInputDataBit(SD_DETECT_GPIO_PORT, SD_DETECT_PIN) != Bit_RESET) - { - status = SD_NOT_PRESENT; - } - return status; -} - -/** - * @brief Enquires cards about their operating voltage and configures - * clock controls. - * @param None - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_PowerON(void) -{ - SD_Error errorstatus = SD_OK; - uint32_t response = 0, count = 0, validvoltage = 0; - uint32_t SDType = SD_STD_CAPACITY; - - /*!< Power ON Sequence -----------------------------------------------------*/ - /*!< Configure the SDIO peripheral */ - /*!< SDIOCLK = HCLK, SDIO_CK = HCLK/(2 + SDIO_INIT_CLK_DIV) */ - /*!< on STM32F2xx devices, SDIOCLK is fixed to 48MHz */ - /*!< SDIO_CK for initialization should not exceed 400 KHz */ - SDIO_InitStructure.SDIO_ClockDiv = SDIO_INIT_CLK_DIV; - SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; - SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; - SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; - SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b; - SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; - SDIO_Init(&SDIO_InitStructure); - - /*!< Set Power State to ON */ - SDIO_SetPowerState(SDIO_PowerState_ON); - - /*!< Enable SDIO Clock */ - SDIO_ClockCmd(ENABLE); - - /*!< CMD0: GO_IDLE_STATE ---------------------------------------------------*/ - /*!< No CMD response required */ - SDIO_CmdInitStructure.SDIO_Argument = 0x0; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_GO_IDLE_STATE; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_No; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdError(); - - if (errorstatus != SD_OK) - { - /*!< CMD Response TimeOut (wait for CMDSENT flag) */ - return(errorstatus); - } - - /*!< CMD8: SEND_IF_COND ----------------------------------------------------*/ - /*!< Send CMD8 to verify SD card interface operating condition */ - /*!< Argument: - [31:12]: Reserved (shall be set to '0') - - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) - - [7:0]: Check Pattern (recommended 0xAA) */ - /*!< CMD Response: R7 */ - SDIO_CmdInitStructure.SDIO_Argument = SD_CHECK_PATTERN; - SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SEND_IF_COND; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp7Error(); - - if (errorstatus == SD_OK) - { - CardType = SDIO_STD_CAPACITY_SD_CARD_V2_0; /*!< SD Card 2.0 */ - SDType = SD_HIGH_CAPACITY; - } - else - { - /*!< CMD55 */ - SDIO_CmdInitStructure.SDIO_Argument = 0x00; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - errorstatus = CmdResp1Error(SD_CMD_APP_CMD); - } - /*!< CMD55 */ - SDIO_CmdInitStructure.SDIO_Argument = 0x00; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - errorstatus = CmdResp1Error(SD_CMD_APP_CMD); - - /*!< If errorstatus is Command TimeOut, it is a MMC card */ - /*!< If errorstatus is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch) - or SD card 1.x */ - if (errorstatus == SD_OK) - { - /*!< SD CARD */ - /*!< Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ - while ((!validvoltage) && (count < SD_MAX_VOLT_TRIAL)) - { - - /*!< SEND CMD55 APP_CMD with RCA as 0 */ - SDIO_CmdInitStructure.SDIO_Argument = 0x00; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_APP_CMD); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - SDIO_CmdInitStructure.SDIO_Argument = SD_VOLTAGE_WINDOW_SD | SDType; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_OP_COND; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp3Error(); - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - response = SDIO_GetResponse(SDIO_RESP1); - validvoltage = (((response >> 31) == 1) ? 1 : 0); - count++; - } - if (count >= SD_MAX_VOLT_TRIAL) - { - errorstatus = SD_INVALID_VOLTRANGE; - return(errorstatus); - } - - if (response &= SD_HIGH_CAPACITY) - { - CardType = SDIO_HIGH_CAPACITY_SD_CARD; - } - - }/*!< else MMC Card */ - - return(errorstatus); -} - -/** - * @brief Turns the SDIO output signals off. - * @param None - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_PowerOFF(void) -{ - SD_Error errorstatus = SD_OK; - - /*!< Set Power State to OFF */ - SDIO_SetPowerState(SDIO_PowerState_OFF); - - return(errorstatus); -} - -/** - * @brief Intialises all cards or single card as the case may be Card(s) come - * into standby state. - * @param None - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_InitializeCards(void) -{ - SD_Error errorstatus = SD_OK; - uint16_t rca = 0x01; - - if (SDIO_GetPowerState() == SDIO_PowerState_OFF) - { - errorstatus = SD_REQUEST_NOT_APPLICABLE; - return(errorstatus); - } - - if (SDIO_SECURE_DIGITAL_IO_CARD != CardType) - { - /*!< Send CMD2 ALL_SEND_CID */ - SDIO_CmdInitStructure.SDIO_Argument = 0x0; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_ALL_SEND_CID; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Long; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp2Error(); - - if (SD_OK != errorstatus) - { - return(errorstatus); - } - - CID_Tab[0] = SDIO_GetResponse(SDIO_RESP1); - CID_Tab[1] = SDIO_GetResponse(SDIO_RESP2); - CID_Tab[2] = SDIO_GetResponse(SDIO_RESP3); - CID_Tab[3] = SDIO_GetResponse(SDIO_RESP4); - } - if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_SECURE_DIGITAL_IO_COMBO_CARD == CardType) - || (SDIO_HIGH_CAPACITY_SD_CARD == CardType)) - { - /*!< Send CMD3 SET_REL_ADDR with argument 0 */ - /*!< SD Card publishes its RCA. */ - SDIO_CmdInitStructure.SDIO_Argument = 0x00; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_REL_ADDR; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp6Error(SD_CMD_SET_REL_ADDR, &rca); - - if (SD_OK != errorstatus) - { - return(errorstatus); - } - } - - if (SDIO_SECURE_DIGITAL_IO_CARD != CardType) - { - RCA = rca; - - /*!< Send CMD9 SEND_CSD with argument as card's RCA */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)(rca << 16); - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEND_CSD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Long; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp2Error(); - - if (SD_OK != errorstatus) - { - return(errorstatus); - } - - CSD_Tab[0] = SDIO_GetResponse(SDIO_RESP1); - CSD_Tab[1] = SDIO_GetResponse(SDIO_RESP2); - CSD_Tab[2] = SDIO_GetResponse(SDIO_RESP3); - CSD_Tab[3] = SDIO_GetResponse(SDIO_RESP4); - } - - errorstatus = SD_OK; /*!< All cards get intialized */ - - return(errorstatus); -} - -/** - * @brief Returns information about specific card. - * @param cardinfo: pointer to a SD_CardInfo structure that contains all SD card - * information. - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo) -{ - SD_Error errorstatus = SD_OK; - uint8_t tmp = 0; - - cardinfo->CardType = (uint8_t)CardType; - cardinfo->RCA = (uint16_t)RCA; - - /*!< Byte 0 */ - tmp = (uint8_t)((CSD_Tab[0] & 0xFF000000) >> 24); - cardinfo->SD_csd.CSDStruct = (tmp & 0xC0) >> 6; - cardinfo->SD_csd.SysSpecVersion = (tmp & 0x3C) >> 2; - cardinfo->SD_csd.Reserved1 = tmp & 0x03; - - /*!< Byte 1 */ - tmp = (uint8_t)((CSD_Tab[0] & 0x00FF0000) >> 16); - cardinfo->SD_csd.TAAC = tmp; - - /*!< Byte 2 */ - tmp = (uint8_t)((CSD_Tab[0] & 0x0000FF00) >> 8); - cardinfo->SD_csd.NSAC = tmp; - - /*!< Byte 3 */ - tmp = (uint8_t)(CSD_Tab[0] & 0x000000FF); - cardinfo->SD_csd.MaxBusClkFrec = tmp; - - /*!< Byte 4 */ - tmp = (uint8_t)((CSD_Tab[1] & 0xFF000000) >> 24); - cardinfo->SD_csd.CardComdClasses = tmp << 4; - - /*!< Byte 5 */ - tmp = (uint8_t)((CSD_Tab[1] & 0x00FF0000) >> 16); - cardinfo->SD_csd.CardComdClasses |= (tmp & 0xF0) >> 4; - cardinfo->SD_csd.RdBlockLen = tmp & 0x0F; - - /*!< Byte 6 */ - tmp = (uint8_t)((CSD_Tab[1] & 0x0000FF00) >> 8); - cardinfo->SD_csd.PartBlockRead = (tmp & 0x80) >> 7; - cardinfo->SD_csd.WrBlockMisalign = (tmp & 0x40) >> 6; - cardinfo->SD_csd.RdBlockMisalign = (tmp & 0x20) >> 5; - cardinfo->SD_csd.DSRImpl = (tmp & 0x10) >> 4; - cardinfo->SD_csd.Reserved2 = 0; /*!< Reserved */ - - if ((CardType == SDIO_STD_CAPACITY_SD_CARD_V1_1) || (CardType == SDIO_STD_CAPACITY_SD_CARD_V2_0)) - { - cardinfo->SD_csd.DeviceSize = (tmp & 0x03) << 10; - - /*!< Byte 7 */ - tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF); - cardinfo->SD_csd.DeviceSize |= (tmp) << 2; - - /*!< Byte 8 */ - tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24); - cardinfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6; - - cardinfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3; - cardinfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07); - - /*!< Byte 9 */ - tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16); - cardinfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5; - cardinfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2; - cardinfo->SD_csd.DeviceSizeMul = (tmp & 0x03) << 1; - /*!< Byte 10 */ - tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8); - cardinfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7; - - cardinfo->CardCapacity = (cardinfo->SD_csd.DeviceSize + 1) ; - cardinfo->CardCapacity *= (1 << (cardinfo->SD_csd.DeviceSizeMul + 2)); - cardinfo->CardBlockSize = 1 << (cardinfo->SD_csd.RdBlockLen); - cardinfo->CardCapacity *= cardinfo->CardBlockSize; - } - else if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) - { - /*!< Byte 7 */ - tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF); - cardinfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16; - - /*!< Byte 8 */ - tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24); - - cardinfo->SD_csd.DeviceSize |= (tmp << 8); - - /*!< Byte 9 */ - tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16); - - cardinfo->SD_csd.DeviceSize |= (tmp); - - /*!< Byte 10 */ - tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8); - - cardinfo->CardCapacity = (cardinfo->SD_csd.DeviceSize + 1) * 512 * 1024; - cardinfo->CardBlockSize = 512; - } - - - cardinfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6; - cardinfo->SD_csd.EraseGrMul = (tmp & 0x3F) << 1; - - /*!< Byte 11 */ - tmp = (uint8_t)(CSD_Tab[2] & 0x000000FF); - cardinfo->SD_csd.EraseGrMul |= (tmp & 0x80) >> 7; - cardinfo->SD_csd.WrProtectGrSize = (tmp & 0x7F); - - /*!< Byte 12 */ - tmp = (uint8_t)((CSD_Tab[3] & 0xFF000000) >> 24); - cardinfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7; - cardinfo->SD_csd.ManDeflECC = (tmp & 0x60) >> 5; - cardinfo->SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2; - cardinfo->SD_csd.MaxWrBlockLen = (tmp & 0x03) << 2; - - /*!< Byte 13 */ - tmp = (uint8_t)((CSD_Tab[3] & 0x00FF0000) >> 16); - cardinfo->SD_csd.MaxWrBlockLen |= (tmp & 0xC0) >> 6; - cardinfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5; - cardinfo->SD_csd.Reserved3 = 0; - cardinfo->SD_csd.ContentProtectAppli = (tmp & 0x01); - - /*!< Byte 14 */ - tmp = (uint8_t)((CSD_Tab[3] & 0x0000FF00) >> 8); - cardinfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7; - cardinfo->SD_csd.CopyFlag = (tmp & 0x40) >> 6; - cardinfo->SD_csd.PermWrProtect = (tmp & 0x20) >> 5; - cardinfo->SD_csd.TempWrProtect = (tmp & 0x10) >> 4; - cardinfo->SD_csd.FileFormat = (tmp & 0x0C) >> 2; - cardinfo->SD_csd.ECC = (tmp & 0x03); - - /*!< Byte 15 */ - tmp = (uint8_t)(CSD_Tab[3] & 0x000000FF); - cardinfo->SD_csd.CSD_CRC = (tmp & 0xFE) >> 1; - cardinfo->SD_csd.Reserved4 = 1; - - - /*!< Byte 0 */ - tmp = (uint8_t)((CID_Tab[0] & 0xFF000000) >> 24); - cardinfo->SD_cid.ManufacturerID = tmp; - - /*!< Byte 1 */ - tmp = (uint8_t)((CID_Tab[0] & 0x00FF0000) >> 16); - cardinfo->SD_cid.OEM_AppliID = tmp << 8; - - /*!< Byte 2 */ - tmp = (uint8_t)((CID_Tab[0] & 0x000000FF00) >> 8); - cardinfo->SD_cid.OEM_AppliID |= tmp; - - /*!< Byte 3 */ - tmp = (uint8_t)(CID_Tab[0] & 0x000000FF); - cardinfo->SD_cid.ProdName1 = tmp << 24; - - /*!< Byte 4 */ - tmp = (uint8_t)((CID_Tab[1] & 0xFF000000) >> 24); - cardinfo->SD_cid.ProdName1 |= tmp << 16; - - /*!< Byte 5 */ - tmp = (uint8_t)((CID_Tab[1] & 0x00FF0000) >> 16); - cardinfo->SD_cid.ProdName1 |= tmp << 8; - - /*!< Byte 6 */ - tmp = (uint8_t)((CID_Tab[1] & 0x0000FF00) >> 8); - cardinfo->SD_cid.ProdName1 |= tmp; - - /*!< Byte 7 */ - tmp = (uint8_t)(CID_Tab[1] & 0x000000FF); - cardinfo->SD_cid.ProdName2 = tmp; - - /*!< Byte 8 */ - tmp = (uint8_t)((CID_Tab[2] & 0xFF000000) >> 24); - cardinfo->SD_cid.ProdRev = tmp; - - /*!< Byte 9 */ - tmp = (uint8_t)((CID_Tab[2] & 0x00FF0000) >> 16); - cardinfo->SD_cid.ProdSN = tmp << 24; - - /*!< Byte 10 */ - tmp = (uint8_t)((CID_Tab[2] & 0x0000FF00) >> 8); - cardinfo->SD_cid.ProdSN |= tmp << 16; - - /*!< Byte 11 */ - tmp = (uint8_t)(CID_Tab[2] & 0x000000FF); - cardinfo->SD_cid.ProdSN |= tmp << 8; - - /*!< Byte 12 */ - tmp = (uint8_t)((CID_Tab[3] & 0xFF000000) >> 24); - cardinfo->SD_cid.ProdSN |= tmp; - - /*!< Byte 13 */ - tmp = (uint8_t)((CID_Tab[3] & 0x00FF0000) >> 16); - cardinfo->SD_cid.Reserved1 |= (tmp & 0xF0) >> 4; - cardinfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8; - - /*!< Byte 14 */ - tmp = (uint8_t)((CID_Tab[3] & 0x0000FF00) >> 8); - cardinfo->SD_cid.ManufactDate |= tmp; - - /*!< Byte 15 */ - tmp = (uint8_t)(CID_Tab[3] & 0x000000FF); - cardinfo->SD_cid.CID_CRC = (tmp & 0xFE) >> 1; - cardinfo->SD_cid.Reserved2 = 1; - - return(errorstatus); -} - -/** - * @brief Enables wide bus opeartion for the requeseted card if supported by - * card. - * @param WideMode: Specifies the SD card wide bus mode. - * This parameter can be one of the following values: - * @arg SDIO_BusWide_8b: 8-bit data transfer (Only for MMC) - * @arg SDIO_BusWide_4b: 4-bit data transfer - * @arg SDIO_BusWide_1b: 1-bit data transfer - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_GetCardStatus(SD_CardStatus *cardstatus) -{ - SD_Error errorstatus = SD_OK; - uint8_t tmp = 0; - - errorstatus = SD_SendSDStatus((uint32_t *)SDSTATUS_Tab); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - /*!< Byte 0 */ - tmp = (uint8_t)((SDSTATUS_Tab[0] & 0xC0) >> 6); - cardstatus->DAT_BUS_WIDTH = tmp; - - /*!< Byte 0 */ - tmp = (uint8_t)((SDSTATUS_Tab[0] & 0x20) >> 5); - cardstatus->SECURED_MODE = tmp; - - /*!< Byte 2 */ - tmp = (uint8_t)((SDSTATUS_Tab[2] & 0xFF)); - cardstatus->SD_CARD_TYPE = tmp << 8; - - /*!< Byte 3 */ - tmp = (uint8_t)((SDSTATUS_Tab[3] & 0xFF)); - cardstatus->SD_CARD_TYPE |= tmp; - - /*!< Byte 4 */ - tmp = (uint8_t)(SDSTATUS_Tab[4] & 0xFF); - cardstatus->SIZE_OF_PROTECTED_AREA = tmp << 24; - - /*!< Byte 5 */ - tmp = (uint8_t)(SDSTATUS_Tab[5] & 0xFF); - cardstatus->SIZE_OF_PROTECTED_AREA |= tmp << 16; - - /*!< Byte 6 */ - tmp = (uint8_t)(SDSTATUS_Tab[6] & 0xFF); - cardstatus->SIZE_OF_PROTECTED_AREA |= tmp << 8; - - /*!< Byte 7 */ - tmp = (uint8_t)(SDSTATUS_Tab[7] & 0xFF); - cardstatus->SIZE_OF_PROTECTED_AREA |= tmp; - - /*!< Byte 8 */ - tmp = (uint8_t)((SDSTATUS_Tab[8] & 0xFF)); - cardstatus->SPEED_CLASS = tmp; - - /*!< Byte 9 */ - tmp = (uint8_t)((SDSTATUS_Tab[9] & 0xFF)); - cardstatus->PERFORMANCE_MOVE = tmp; - - /*!< Byte 10 */ - tmp = (uint8_t)((SDSTATUS_Tab[10] & 0xF0) >> 4); - cardstatus->AU_SIZE = tmp; - - /*!< Byte 11 */ - tmp = (uint8_t)(SDSTATUS_Tab[11] & 0xFF); - cardstatus->ERASE_SIZE = tmp << 8; - - /*!< Byte 12 */ - tmp = (uint8_t)(SDSTATUS_Tab[12] & 0xFF); - cardstatus->ERASE_SIZE |= tmp; - - /*!< Byte 13 */ - tmp = (uint8_t)((SDSTATUS_Tab[13] & 0xFC) >> 2); - cardstatus->ERASE_TIMEOUT = tmp; - - /*!< Byte 13 */ - tmp = (uint8_t)((SDSTATUS_Tab[13] & 0x3)); - cardstatus->ERASE_OFFSET = tmp; - - return(errorstatus); -} - -/** - * @brief Enables wide bus opeartion for the requeseted card if supported by - * card. - * @param WideMode: Specifies the SD card wide bus mode. - * This parameter can be one of the following values: - * @arg SDIO_BusWide_8b: 8-bit data transfer (Only for MMC) - * @arg SDIO_BusWide_4b: 4-bit data transfer - * @arg SDIO_BusWide_1b: 1-bit data transfer - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_EnableWideBusOperation(uint32_t WideMode) -{ - SD_Error errorstatus = SD_OK; - - /*!< MMC Card doesn't support this feature */ - if (SDIO_MULTIMEDIA_CARD == CardType) - { - errorstatus = SD_UNSUPPORTED_FEATURE; - return(errorstatus); - } - else if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_HIGH_CAPACITY_SD_CARD == CardType)) - { - if (SDIO_BusWide_8b == WideMode) - { - errorstatus = SD_UNSUPPORTED_FEATURE; - return(errorstatus); - } - else if (SDIO_BusWide_4b == WideMode) - { - errorstatus = SDEnWideBus(ENABLE); - - if (SD_OK == errorstatus) - { - /*!< Configure the SDIO peripheral */ - SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV; - SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; - SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; - SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; - SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_4b; - SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; - SDIO_Init(&SDIO_InitStructure); - } - } - else - { - errorstatus = SDEnWideBus(DISABLE); - - if (SD_OK == errorstatus) - { - /*!< Configure the SDIO peripheral */ - SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV; - SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; - SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; - SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; - SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b; - SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; - SDIO_Init(&SDIO_InitStructure); - } - } - } - - return(errorstatus); -} - -/** - * @brief Selects od Deselects the corresponding card. - * @param addr: Address of the Card to be selected. - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_SelectDeselect(uint32_t addr) -{ - SD_Error errorstatus = SD_OK; - - /*!< Send CMD7 SDIO_SEL_DESEL_CARD */ - SDIO_CmdInitStructure.SDIO_Argument = addr; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEL_DESEL_CARD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SEL_DESEL_CARD); - - return(errorstatus); -} - -/** - * @brief Allows to read one block from a specified address in a card. The Data - * transfer can be managed by DMA mode or Polling mode. - * @note This operation should be followed by two functions to check if the - * DMA Controller and SD Card status. - * - SD_ReadWaitOperation(): this function insure that the DMA - * controller has finished all data transfer. - * - SD_GetStatus(): to check that the SD Card has finished the - * data transfer and it is ready for data. - * @param readbuff: pointer to the buffer that will contain the received data - * @param ReadAddr: Address from where data are to be read. - * @param BlockSize: the SD card Data block size. The Block size should be 512. - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_ReadBlock(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize) -{ - SD_Error errorstatus = SD_OK; -#if defined (SD_POLLING_MODE) - uint32_t count = 0, *tempbuff = (uint32_t *)readbuff; -#endif - - TransferError = SD_OK; - TransferEnd = 0; - StopCondition = 0; - - SDIO->DCTRL = 0x0; - - - if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) - { - BlockSize = 512; - ReadAddr /= 512; - } - - SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; - SDIO_DataInitStructure.SDIO_DataLength = BlockSize; - SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4; - SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO; - SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; - SDIO_DataConfig(&SDIO_DataInitStructure); - - /*!< Send CMD17 READ_SINGLE_BLOCK */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)ReadAddr; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_READ_SINGLE_BLOCK; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_READ_SINGLE_BLOCK); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - -#if defined (SD_POLLING_MODE) - /*!< In case of single block transfer, no need of stop transfer at all.*/ - /*!< Polling mode */ - while (!(SDIO->STA &(SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))) - { - if (SDIO_GetFlagStatus(SDIO_FLAG_RXFIFOHF) != RESET) - { - for (count = 0; count < 8; count++) - { - *(tempbuff + count) = SDIO_ReadData(); - } - tempbuff += 8; - } - } - - if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT); - errorstatus = SD_DATA_TIMEOUT; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL); - errorstatus = SD_DATA_CRC_FAIL; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_RXOVERR); - errorstatus = SD_RX_OVERRUN; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_STBITERR); - errorstatus = SD_START_BIT_ERR; - return(errorstatus); - } - while (SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET) - { - *tempbuff = SDIO_ReadData(); - tempbuff++; - } - - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - -#elif defined (SD_DMA_MODE) - SDIO_ITConfig(SDIO_IT_DATAEND, ENABLE); - SDIO_DMACmd(ENABLE); - SD_LowLevel_DMA_RxConfig((uint32_t *)readbuff, BlockSize); -#endif - - return(errorstatus); -} - -/** - * @brief Allows to read blocks from a specified address in a card. The Data - * transfer can be managed by DMA mode or Polling mode. - * @note This operation should be followed by two functions to check if the - * DMA Controller and SD Card status. - * - SD_ReadWaitOperation(): this function insure that the DMA - * controller has finished all data transfer. - * - SD_GetStatus(): to check that the SD Card has finished the - * data transfer and it is ready for data. - * @param readbuff: pointer to the buffer that will contain the received data. - * @param ReadAddr: Address from where data are to be read. - * @param BlockSize: the SD card Data block size. The Block size should be 512. - * @param NumberOfBlocks: number of blocks to be read. - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_ReadMultiBlocks(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks) -{ - SD_Error errorstatus = SD_OK; - TransferError = SD_OK; - TransferEnd = 0; - StopCondition = 1; - - SDIO->DCTRL = 0x0; - - if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) - { - BlockSize = 512; - ReadAddr /= 512; - } - - /*!< Set Block Size for Card */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); - - if (SD_OK != errorstatus) - { - return(errorstatus); - } - - SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; - SDIO_DataInitStructure.SDIO_DataLength = NumberOfBlocks * BlockSize; - SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4; - SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO; - SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; - SDIO_DataConfig(&SDIO_DataInitStructure); - - /*!< Send CMD18 READ_MULT_BLOCK with argument data address */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)ReadAddr; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_READ_MULT_BLOCK; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_READ_MULT_BLOCK); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - SDIO_ITConfig(SDIO_IT_DATAEND, ENABLE); - SDIO_DMACmd(ENABLE); - SD_LowLevel_DMA_RxConfig((uint32_t *)readbuff, (NumberOfBlocks * BlockSize)); - - return(errorstatus); -} - -/** - * @brief This function waits until the SDIO DMA data transfer is finished. - * This function should be called after SDIO_ReadMultiBlocks() function - * to insure that all data sent by the card are already transferred by - * the DMA controller. - * @param None. - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_WaitReadOperation(void) -{ - SD_Error errorstatus = SD_OK; - - while ((SD_DMAEndOfTransferStatus() == RESET) && (TransferEnd == 0) && (TransferError == SD_OK)) - {} - - if (TransferError != SD_OK) - { - return(TransferError); - } - - return(errorstatus); -} - -/** - * @brief Allows to write one block starting from a specified address in a card. - * The Data transfer can be managed by DMA mode or Polling mode. - * @note This operation should be followed by two functions to check if the - * DMA Controller and SD Card status. - * - SD_ReadWaitOperation(): this function insure that the DMA - * controller has finished all data transfer. - * - SD_GetStatus(): to check that the SD Card has finished the - * data transfer and it is ready for data. - * @param writebuff: pointer to the buffer that contain the data to be transferred. - * @param WriteAddr: Address from where data are to be read. - * @param BlockSize: the SD card Data block size. The Block size should be 512. - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_WriteBlock(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize) -{ - SD_Error errorstatus = SD_OK; - -#if defined (SD_POLLING_MODE) - uint32_t bytestransferred = 0, count = 0, restwords = 0; - uint32_t *tempbuff = (uint32_t *)writebuff; -#endif - - TransferError = SD_OK; - TransferEnd = 0; - StopCondition = 0; - - SDIO->DCTRL = 0x0; - - - if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) - { - BlockSize = 512; - WriteAddr /= 512; - } - - /*!< Send CMD24 WRITE_SINGLE_BLOCK */ - SDIO_CmdInitStructure.SDIO_Argument = WriteAddr; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_WRITE_SINGLE_BLOCK); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; - SDIO_DataInitStructure.SDIO_DataLength = BlockSize; - SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4; - SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToCard; - SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; - SDIO_DataConfig(&SDIO_DataInitStructure); - - /*!< In case of single data block transfer no need of stop command at all */ -#if defined (SD_POLLING_MODE) - while (!(SDIO->STA & (SDIO_FLAG_DBCKEND | SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_STBITERR))) - { - if (SDIO_GetFlagStatus(SDIO_FLAG_TXFIFOHE) != RESET) - { - if ((512 - bytestransferred) < 32) - { - restwords = ((512 - bytestransferred) % 4 == 0) ? ((512 - bytestransferred) / 4) : (( 512 - bytestransferred) / 4 + 1); - for (count = 0; count < restwords; count++, tempbuff++, bytestransferred += 4) - { - SDIO_WriteData(*tempbuff); - } - } - else - { - for (count = 0; count < 8; count++) - { - SDIO_WriteData(*(tempbuff + count)); - } - tempbuff += 8; - bytestransferred += 32; - } - } - } - if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT); - errorstatus = SD_DATA_TIMEOUT; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL); - errorstatus = SD_DATA_CRC_FAIL; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_TXUNDERR) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_TXUNDERR); - errorstatus = SD_TX_UNDERRUN; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_STBITERR); - errorstatus = SD_START_BIT_ERR; - return(errorstatus); - } -#elif defined (SD_DMA_MODE) - SDIO_ITConfig(SDIO_IT_DATAEND, ENABLE); - SD_LowLevel_DMA_TxConfig((uint32_t *)writebuff, BlockSize); - SDIO_DMACmd(ENABLE); -#endif - - return(errorstatus); -} - -/** - * @brief Allows to write blocks starting from a specified address in a card. - * The Data transfer can be managed by DMA mode only. - * @note This operation should be followed by two functions to check if the - * DMA Controller and SD Card status. - * - SD_ReadWaitOperation(): this function insure that the DMA - * controller has finished all data transfer. - * - SD_GetStatus(): to check that the SD Card has finished the - * data transfer and it is ready for data. - * @param WriteAddr: Address from where data are to be read. - * @param writebuff: pointer to the buffer that contain the data to be transferred. - * @param BlockSize: the SD card Data block size. The Block size should be 512. - * @param NumberOfBlocks: number of blocks to be written. - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_WriteMultiBlocks(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks) -{ - SD_Error errorstatus = SD_OK; - __IO uint32_t count = 0; - - TransferError = SD_OK; - TransferEnd = 0; - StopCondition = 1; - - SDIO->DCTRL = 0x0; - - if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) - { - BlockSize = 512; - WriteAddr /= 512; - } - - /*!< To improve performance */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) (RCA << 16); - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - - errorstatus = CmdResp1Error(SD_CMD_APP_CMD); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - /*!< To improve performance */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)NumberOfBlocks; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCK_COUNT; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SET_BLOCK_COUNT); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - - /*!< Send CMD25 WRITE_MULT_BLOCK with argument data address */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)WriteAddr; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_WRITE_MULT_BLOCK; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_WRITE_MULT_BLOCK); - - if (SD_OK != errorstatus) - { - return(errorstatus); - } - - SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; - SDIO_DataInitStructure.SDIO_DataLength = NumberOfBlocks * BlockSize; - SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4; - SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToCard; - SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; - SDIO_DataConfig(&SDIO_DataInitStructure); - - SDIO_ITConfig(SDIO_IT_DATAEND, ENABLE); - SDIO_DMACmd(ENABLE); - SD_LowLevel_DMA_TxConfig((uint32_t *)writebuff, (NumberOfBlocks * BlockSize)); - - return(errorstatus); -} - -/** - * @brief This function waits until the SDIO DMA data transfer is finished. - * This function should be called after SDIO_WriteBlock() and - * SDIO_WriteMultiBlocks() function to insure that all data sent by the - * card are already transferred by the DMA controller. - * @param None. - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_WaitWriteOperation(void) -{ - SD_Error errorstatus = SD_OK; - - while ((SD_DMAEndOfTransferStatus() == RESET) && (TransferEnd == 0) && (TransferError == SD_OK)) - {} - - if (TransferError != SD_OK) - { - return(TransferError); - } - - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - - return(errorstatus); -} - -/** - * @brief Gets the cuurent data transfer state. - * @param None - * @retval SDTransferState: Data Transfer state. - * This value can be: - * - SD_TRANSFER_OK: No data transfer is acting - * - SD_TRANSFER_BUSY: Data transfer is acting - */ -SDTransferState SD_GetTransferState(void) -{ - if (SDIO->STA & (SDIO_FLAG_TXACT | SDIO_FLAG_RXACT)) - { - return(SD_TRANSFER_BUSY); - } - else - { - return(SD_TRANSFER_OK); - } -} - -/** - * @brief Aborts an ongoing data transfer. - * @param None - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_StopTransfer(void) -{ - SD_Error errorstatus = SD_OK; - - /*!< Send CMD12 STOP_TRANSMISSION */ - SDIO->ARG = 0x0; - SDIO->CMD = 0x44C; - errorstatus = CmdResp1Error(SD_CMD_STOP_TRANSMISSION); - - return(errorstatus); -} - -/** - * @brief Allows to erase memory area specified for the given card. - * @param startaddr: the start address. - * @param endaddr: the end address. - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_Erase(uint32_t startaddr, uint32_t endaddr) -{ - SD_Error errorstatus = SD_OK; - uint32_t delay = 0; - __IO uint32_t maxdelay = 0; - uint8_t cardstate = 0; - - /*!< Check if the card coomnd class supports erase command */ - if (((CSD_Tab[1] >> 20) & SD_CCCC_ERASE) == 0) - { - errorstatus = SD_REQUEST_NOT_APPLICABLE; - return(errorstatus); - } - - maxdelay = 120000 / ((SDIO->CLKCR & 0xFF) + 2); - - if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) - { - errorstatus = SD_LOCK_UNLOCK_FAILED; - return(errorstatus); - } - - if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) - { - startaddr /= 512; - endaddr /= 512; - } - - /*!< According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ - if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_HIGH_CAPACITY_SD_CARD == CardType)) - { - /*!< Send CMD32 SD_ERASE_GRP_START with argument as addr */ - SDIO_CmdInitStructure.SDIO_Argument = startaddr; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_ERASE_GRP_START; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SD_ERASE_GRP_START); - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - /*!< Send CMD33 SD_ERASE_GRP_END with argument as addr */ - SDIO_CmdInitStructure.SDIO_Argument = endaddr; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_ERASE_GRP_END; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SD_ERASE_GRP_END); - if (errorstatus != SD_OK) - { - return(errorstatus); - } - } - - /*!< Send CMD38 ERASE */ - SDIO_CmdInitStructure.SDIO_Argument = 0; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_ERASE; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_ERASE); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - for (delay = 0; delay < maxdelay; delay++) - {} - - /*!< Wait till the card is in programming state */ - errorstatus = IsCardProgramming(&cardstate); - - while ((errorstatus == SD_OK) && ((SD_CARD_PROGRAMMING == cardstate) || (SD_CARD_RECEIVING == cardstate))) - { - errorstatus = IsCardProgramming(&cardstate); - } - - return(errorstatus); -} - -/** - * @brief Returns the current card's status. - * @param pcardstatus: pointer to the buffer that will contain the SD card - * status (Card Status register). - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_SendStatus(uint32_t *pcardstatus) -{ - SD_Error errorstatus = SD_OK; - - SDIO->ARG = (uint32_t) RCA << 16; - SDIO->CMD = 0x44D; - - errorstatus = CmdResp1Error(SD_CMD_SEND_STATUS); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - *pcardstatus = SDIO->RESP1; - return(errorstatus); -} - -/** - * @brief Returns the current SD card's status. - * @param psdstatus: pointer to the buffer that will contain the SD card status - * (SD Status register). - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_SendSDStatus(uint32_t *psdstatus) -{ - SD_Error errorstatus = SD_OK; - uint32_t count = 0; - - if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) - { - errorstatus = SD_LOCK_UNLOCK_FAILED; - return(errorstatus); - } - - /*!< Set block size for card if it is not equal to current block size for card. */ - SDIO_CmdInitStructure.SDIO_Argument = 64; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - /*!< CMD55 */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - errorstatus = CmdResp1Error(SD_CMD_APP_CMD); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; - SDIO_DataInitStructure.SDIO_DataLength = 64; - SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_64b; - SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO; - SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; - SDIO_DataConfig(&SDIO_DataInitStructure); - - /*!< Send ACMD13 SD_APP_STAUS with argument as card's RCA.*/ - SDIO_CmdInitStructure.SDIO_Argument = 0; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_STAUS; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - errorstatus = CmdResp1Error(SD_CMD_SD_APP_STAUS); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - while (!(SDIO->STA &(SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))) - { - if (SDIO_GetFlagStatus(SDIO_FLAG_RXFIFOHF) != RESET) - { - for (count = 0; count < 8; count++) - { - *(psdstatus + count) = SDIO_ReadData(); - } - psdstatus += 8; - } - } - - if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT); - errorstatus = SD_DATA_TIMEOUT; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL); - errorstatus = SD_DATA_CRC_FAIL; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_RXOVERR); - errorstatus = SD_RX_OVERRUN; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_STBITERR); - errorstatus = SD_START_BIT_ERR; - return(errorstatus); - } - - while (SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET) - { - *psdstatus = SDIO_ReadData(); - psdstatus++; - } - - /*!< Clear all the static status flags*/ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - - return(errorstatus); -} - -/** - * @brief Allows to process all the interrupts that are high. - * @param None - * @retval SD_Error: SD Card Error code. - */ -SD_Error SD_ProcessIRQSrc(void) -{ - if (StopCondition == 1) - { - SDIO->ARG = 0x0; - SDIO->CMD = 0x44C; - TransferError = CmdResp1Error(SD_CMD_STOP_TRANSMISSION); - } - else - { - TransferError = SD_OK; - } - SDIO_ClearITPendingBit(SDIO_IT_DATAEND); - SDIO_ITConfig(SDIO_IT_DATAEND, DISABLE); - TransferEnd = 1; - return(TransferError); -} - -/** - * @brief Checks for error conditions for CMD0. - * @param None - * @retval SD_Error: SD Card Error code. - */ -static SD_Error CmdError(void) -{ - SD_Error errorstatus = SD_OK; - uint32_t timeout; - - timeout = SDIO_CMD0TIMEOUT; /*!< 10000 */ - - while ((timeout > 0) && (SDIO_GetFlagStatus(SDIO_FLAG_CMDSENT) == RESET)) - { - timeout--; - } - - if (timeout == 0) - { - errorstatus = SD_CMD_RSP_TIMEOUT; - return(errorstatus); - } - - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - - return(errorstatus); -} - -/** - * @brief Checks for error conditions for R7 response. - * @param None - * @retval SD_Error: SD Card Error code. - */ -static SD_Error CmdResp7Error(void) -{ - SD_Error errorstatus = SD_OK; - uint32_t status; - uint32_t timeout = SDIO_CMD0TIMEOUT; - - status = SDIO->STA; - - while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) && (timeout > 0)) - { - timeout--; - status = SDIO->STA; - } - - if ((timeout == 0) || (status & SDIO_FLAG_CTIMEOUT)) - { - /*!< Card is not V2.0 complient or card does not support the set voltage range */ - errorstatus = SD_CMD_RSP_TIMEOUT; - SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); - return(errorstatus); - } - - if (status & SDIO_FLAG_CMDREND) - { - /*!< Card is SD V2.0 compliant */ - errorstatus = SD_OK; - SDIO_ClearFlag(SDIO_FLAG_CMDREND); - return(errorstatus); - } - return(errorstatus); -} - -/** - * @brief Checks for error conditions for R1 response. - * @param cmd: The sent command index. - * @retval SD_Error: SD Card Error code. - */ -static SD_Error CmdResp1Error(uint8_t cmd) -{ - while (!(SDIO->STA & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))) - { - } - - SDIO->ICR = SDIO_STATIC_FLAGS; - - return (SD_Error)(SDIO->RESP1 & SD_OCR_ERRORBITS); -} - -/** - * @brief Checks for error conditions for R3 (OCR) response. - * @param None - * @retval SD_Error: SD Card Error code. - */ -static SD_Error CmdResp3Error(void) -{ - SD_Error errorstatus = SD_OK; - uint32_t status; - - status = SDIO->STA; - - while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))) - { - status = SDIO->STA; - } - - if (status & SDIO_FLAG_CTIMEOUT) - { - errorstatus = SD_CMD_RSP_TIMEOUT; - SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); - return(errorstatus); - } - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - return(errorstatus); -} - -/** - * @brief Checks for error conditions for R2 (CID or CSD) response. - * @param None - * @retval SD_Error: SD Card Error code. - */ -static SD_Error CmdResp2Error(void) -{ - SD_Error errorstatus = SD_OK; - uint32_t status; - - status = SDIO->STA; - - while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND))) - { - status = SDIO->STA; - } - - if (status & SDIO_FLAG_CTIMEOUT) - { - errorstatus = SD_CMD_RSP_TIMEOUT; - SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); - return(errorstatus); - } - else if (status & SDIO_FLAG_CCRCFAIL) - { - errorstatus = SD_CMD_CRC_FAIL; - SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL); - return(errorstatus); - } - - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - - return(errorstatus); -} - -/** - * @brief Checks for error conditions for R6 (RCA) response. - * @param cmd: The sent command index. - * @param prca: pointer to the variable that will contain the SD card relative - * address RCA. - * @retval SD_Error: SD Card Error code. - */ -static SD_Error CmdResp6Error(uint8_t cmd, uint16_t *prca) -{ - SD_Error errorstatus = SD_OK; - uint32_t status; - uint32_t response_r1; - - status = SDIO->STA; - - while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND))) - { - status = SDIO->STA; - } - - if (status & SDIO_FLAG_CTIMEOUT) - { - errorstatus = SD_CMD_RSP_TIMEOUT; - SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); - return(errorstatus); - } - else if (status & SDIO_FLAG_CCRCFAIL) - { - errorstatus = SD_CMD_CRC_FAIL; - SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL); - return(errorstatus); - } - - /*!< Check response received is of desired command */ - if (SDIO_GetCommandResponse() != cmd) - { - errorstatus = SD_ILLEGAL_CMD; - return(errorstatus); - } - - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - - /*!< We have received response, retrieve it. */ - response_r1 = SDIO_GetResponse(SDIO_RESP1); - - if (SD_ALLZERO == (response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED))) - { - *prca = (uint16_t) (response_r1 >> 16); - return(errorstatus); - } - - if (response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) - { - return(SD_GENERAL_UNKNOWN_ERROR); - } - - if (response_r1 & SD_R6_ILLEGAL_CMD) - { - return(SD_ILLEGAL_CMD); - } - - if (response_r1 & SD_R6_COM_CRC_FAILED) - { - return(SD_COM_CRC_FAILED); - } - - return(errorstatus); -} - -/** - * @brief Enables or disables the SDIO wide bus mode. - * @param NewState: new state of the SDIO wide bus mode. - * This parameter can be: ENABLE or DISABLE. - * @retval SD_Error: SD Card Error code. - */ -static SD_Error SDEnWideBus(FunctionalState NewState) -{ - SD_Error errorstatus = SD_OK; - - uint32_t scr[2] = {0, 0}; - - if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) - { - errorstatus = SD_LOCK_UNLOCK_FAILED; - return(errorstatus); - } - - /*!< Get SCR Register */ - errorstatus = FindSCR(RCA, scr); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - /*!< If wide bus operation to be enabled */ - if (NewState == ENABLE) - { - /*!< If requested card supports wide bus operation */ - if ((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO) - { - /*!< Send CMD55 APP_CMD with argument as card's RCA.*/ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_APP_CMD); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - /*!< Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ - SDIO_CmdInitStructure.SDIO_Argument = 0x2; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_APP_SD_SET_BUSWIDTH); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - return(errorstatus); - } - else - { - errorstatus = SD_REQUEST_NOT_APPLICABLE; - return(errorstatus); - } - } /*!< If wide bus operation to be disabled */ - else - { - /*!< If requested card supports 1 bit mode operation */ - if ((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO) - { - /*!< Send CMD55 APP_CMD with argument as card's RCA.*/ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - - errorstatus = CmdResp1Error(SD_CMD_APP_CMD); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - /*!< Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ - SDIO_CmdInitStructure.SDIO_Argument = 0x00; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_APP_SD_SET_BUSWIDTH); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - return(errorstatus); - } - else - { - errorstatus = SD_REQUEST_NOT_APPLICABLE; - return(errorstatus); - } - } -} - -/** - * @brief Checks if the SD card is in programming state. - * @param pstatus: pointer to the variable that will contain the SD card state. - * @retval SD_Error: SD Card Error code. - */ -static SD_Error IsCardProgramming(uint8_t *pstatus) -{ - SD_Error errorstatus = SD_OK; - __IO uint32_t respR1 = 0, status = 0; - - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEND_STATUS; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - status = SDIO->STA; - while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))) - { - status = SDIO->STA; - } - - if (status & SDIO_FLAG_CTIMEOUT) - { - errorstatus = SD_CMD_RSP_TIMEOUT; - SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); - return(errorstatus); - } - else if (status & SDIO_FLAG_CCRCFAIL) - { - errorstatus = SD_CMD_CRC_FAIL; - SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL); - return(errorstatus); - } - - status = (uint32_t)SDIO_GetCommandResponse(); - - /*!< Check response received is of desired command */ - if (status != SD_CMD_SEND_STATUS) - { - errorstatus = SD_ILLEGAL_CMD; - return(errorstatus); - } - - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - - - /*!< We have received response, retrieve it for analysis */ - respR1 = SDIO_GetResponse(SDIO_RESP1); - - /*!< Find out card status */ - *pstatus = (uint8_t) ((respR1 >> 9) & 0x0000000F); - - if ((respR1 & SD_OCR_ERRORBITS) == SD_ALLZERO) - { - return(errorstatus); - } - - if (respR1 & SD_OCR_ADDR_OUT_OF_RANGE) - { - return(SD_ADDR_OUT_OF_RANGE); - } - - if (respR1 & SD_OCR_ADDR_MISALIGNED) - { - return(SD_ADDR_MISALIGNED); - } - - if (respR1 & SD_OCR_BLOCK_LEN_ERR) - { - return(SD_BLOCK_LEN_ERR); - } - - if (respR1 & SD_OCR_ERASE_SEQ_ERR) - { - return(SD_ERASE_SEQ_ERR); - } - - if (respR1 & SD_OCR_BAD_ERASE_PARAM) - { - return(SD_BAD_ERASE_PARAM); - } - - if (respR1 & SD_OCR_WRITE_PROT_VIOLATION) - { - return(SD_WRITE_PROT_VIOLATION); - } - - if (respR1 & SD_OCR_LOCK_UNLOCK_FAILED) - { - return(SD_LOCK_UNLOCK_FAILED); - } - - if (respR1 & SD_OCR_COM_CRC_FAILED) - { - return(SD_COM_CRC_FAILED); - } - - if (respR1 & SD_OCR_ILLEGAL_CMD) - { - return(SD_ILLEGAL_CMD); - } - - if (respR1 & SD_OCR_CARD_ECC_FAILED) - { - return(SD_CARD_ECC_FAILED); - } - - if (respR1 & SD_OCR_CC_ERROR) - { - return(SD_CC_ERROR); - } - - if (respR1 & SD_OCR_GENERAL_UNKNOWN_ERROR) - { - return(SD_GENERAL_UNKNOWN_ERROR); - } - - if (respR1 & SD_OCR_STREAM_READ_UNDERRUN) - { - return(SD_STREAM_READ_UNDERRUN); - } - - if (respR1 & SD_OCR_STREAM_WRITE_OVERRUN) - { - return(SD_STREAM_WRITE_OVERRUN); - } - - if (respR1 & SD_OCR_CID_CSD_OVERWRIETE) - { - return(SD_CID_CSD_OVERWRITE); - } - - if (respR1 & SD_OCR_WP_ERASE_SKIP) - { - return(SD_WP_ERASE_SKIP); - } - - if (respR1 & SD_OCR_CARD_ECC_DISABLED) - { - return(SD_CARD_ECC_DISABLED); - } - - if (respR1 & SD_OCR_ERASE_RESET) - { - return(SD_ERASE_RESET); - } - - if (respR1 & SD_OCR_AKE_SEQ_ERROR) - { - return(SD_AKE_SEQ_ERROR); - } - - return(errorstatus); -} - -/** - * @brief Find the SD card SCR register value. - * @param rca: selected card address. - * @param pscr: pointer to the buffer that will contain the SCR value. - * @retval SD_Error: SD Card Error code. - */ -static SD_Error FindSCR(uint16_t rca, uint32_t *pscr) -{ - uint32_t index = 0; - SD_Error errorstatus = SD_OK; - uint32_t tempscr[2] = {0, 0}; - - /*!< Set Block Size To 8 Bytes */ - /*!< Send CMD55 APP_CMD with argument as card's RCA */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)8; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - /*!< Send CMD55 APP_CMD with argument as card's RCA */ - SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_APP_CMD); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; - SDIO_DataInitStructure.SDIO_DataLength = 8; - SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_8b; - SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO; - SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; - SDIO_DataConfig(&SDIO_DataInitStructure); - - - /*!< Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ - SDIO_CmdInitStructure.SDIO_Argument = 0x0; - SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_SEND_SCR; - SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; - SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; - SDIO_SendCommand(&SDIO_CmdInitStructure); - - errorstatus = CmdResp1Error(SD_CMD_SD_APP_SEND_SCR); - - if (errorstatus != SD_OK) - { - return(errorstatus); - } - - while (!(SDIO->STA & (SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))) - { - if (SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET) - { - *(tempscr + index) = SDIO_ReadData(); - index++; - } - } - - if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT); - errorstatus = SD_DATA_TIMEOUT; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL); - errorstatus = SD_DATA_CRC_FAIL; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_RXOVERR); - errorstatus = SD_RX_OVERRUN; - return(errorstatus); - } - else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET) - { - SDIO_ClearFlag(SDIO_FLAG_STBITERR); - errorstatus = SD_START_BIT_ERR; - return(errorstatus); - } - - /*!< Clear all the static flags */ - SDIO_ClearFlag(SDIO_STATIC_FLAGS); - - *(pscr + 1) = ((tempscr[0] & SD_0TO7BITS) << 24) | ((tempscr[0] & SD_8TO15BITS) << 8) | ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24); - - *(pscr) = ((tempscr[1] & SD_0TO7BITS) << 24) | ((tempscr[1] & SD_8TO15BITS) << 8) | ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24); - - return(errorstatus); -} - -/** - * @brief Converts the number of bytes in power of two and returns the power. - * @param NumberOfBytes: number of bytes. - * @retval None - */ -uint8_t convert_from_bytes_to_power_of_two(uint16_t NumberOfBytes) -{ - uint8_t count = 0; - - while (NumberOfBytes != 1) - { - NumberOfBytes >>= 1; - count++; - } - return(count); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_sdio_sd.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_sdio_sd.h deleted file mode 100644 index 1746e2cf0..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_sdio_sd.h +++ /dev/null @@ -1,397 +0,0 @@ -/** - ****************************************************************************** - * @file stm32_eval_sdio_sd.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains all the functions prototypes for the SD Card - * stm32_eval_sdio_sd driver firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32_EVAL_SDIO_SD_H -#define __STM32_EVAL_SDIO_SD_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32_eval.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup Common - * @{ - */ - -/** @addtogroup STM32_EVAL_SDIO_SD - * @{ - */ - -/** @defgroup STM32_EVAL_SDIO_SD_Exported_Types - * @{ - */ -typedef enum -{ -/** - * @brief SDIO specific error defines - */ - SD_CMD_CRC_FAIL = (1), /*!< Command response received (but CRC check failed) */ - SD_DATA_CRC_FAIL = (2), /*!< Data bock sent/received (CRC check Failed) */ - SD_CMD_RSP_TIMEOUT = (3), /*!< Command response timeout */ - SD_DATA_TIMEOUT = (4), /*!< Data time out */ - SD_TX_UNDERRUN = (5), /*!< Transmit FIFO under-run */ - SD_RX_OVERRUN = (6), /*!< Receive FIFO over-run */ - SD_START_BIT_ERR = (7), /*!< Start bit not detected on all data signals in widE bus mode */ - SD_CMD_OUT_OF_RANGE = (8), /*!< CMD's argument was out of range.*/ - SD_ADDR_MISALIGNED = (9), /*!< Misaligned address */ - SD_BLOCK_LEN_ERR = (10), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */ - SD_ERASE_SEQ_ERR = (11), /*!< An error in the sequence of erase command occurs.*/ - SD_BAD_ERASE_PARAM = (12), /*!< An Invalid selection for erase groups */ - SD_WRITE_PROT_VIOLATION = (13), /*!< Attempt to program a write protect block */ - SD_LOCK_UNLOCK_FAILED = (14), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */ - SD_COM_CRC_FAILED = (15), /*!< CRC check of the previous command failed */ - SD_ILLEGAL_CMD = (16), /*!< Command is not legal for the card state */ - SD_CARD_ECC_FAILED = (17), /*!< Card internal ECC was applied but failed to correct the data */ - SD_CC_ERROR = (18), /*!< Internal card controller error */ - SD_GENERAL_UNKNOWN_ERROR = (19), /*!< General or Unknown error */ - SD_STREAM_READ_UNDERRUN = (20), /*!< The card could not sustain data transfer in stream read operation. */ - SD_STREAM_WRITE_OVERRUN = (21), /*!< The card could not sustain data programming in stream mode */ - SD_CID_CSD_OVERWRITE = (22), /*!< CID/CSD overwrite error */ - SD_WP_ERASE_SKIP = (23), /*!< only partial address space was erased */ - SD_CARD_ECC_DISABLED = (24), /*!< Command has been executed without using internal ECC */ - SD_ERASE_RESET = (25), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */ - SD_AKE_SEQ_ERROR = (26), /*!< Error in sequence of authentication. */ - SD_INVALID_VOLTRANGE = (27), - SD_ADDR_OUT_OF_RANGE = (28), - SD_SWITCH_ERROR = (29), - SD_SDIO_DISABLED = (30), - SD_SDIO_FUNCTION_BUSY = (31), - SD_SDIO_FUNCTION_FAILED = (32), - SD_SDIO_UNKNOWN_FUNCTION = (33), - -/** - * @brief Standard error defines - */ - SD_INTERNAL_ERROR, - SD_NOT_CONFIGURED, - SD_REQUEST_PENDING, - SD_REQUEST_NOT_APPLICABLE, - SD_INVALID_PARAMETER, - SD_UNSUPPORTED_FEATURE, - SD_UNSUPPORTED_HW, - SD_ERROR, - SD_OK = 0 -} SD_Error; - -/** - * @brief SDIO Transfer state - */ -typedef enum -{ - SD_TRANSFER_OK = 0, - SD_TRANSFER_BUSY = 1, - SD_TRANSFER_ERROR -} SDTransferState; - -/** - * @brief SD Card States - */ -typedef enum -{ - SD_CARD_READY = ((uint32_t)0x00000001), - SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002), - SD_CARD_STANDBY = ((uint32_t)0x00000003), - SD_CARD_TRANSFER = ((uint32_t)0x00000004), - SD_CARD_SENDING = ((uint32_t)0x00000005), - SD_CARD_RECEIVING = ((uint32_t)0x00000006), - SD_CARD_PROGRAMMING = ((uint32_t)0x00000007), - SD_CARD_DISCONNECTED = ((uint32_t)0x00000008), - SD_CARD_ERROR = ((uint32_t)0x000000FF) -}SDCardState; - - -/** - * @brief Card Specific Data: CSD Register - */ -typedef struct -{ - __IO uint8_t CSDStruct; /*!< CSD structure */ - __IO uint8_t SysSpecVersion; /*!< System specification version */ - __IO uint8_t Reserved1; /*!< Reserved */ - __IO uint8_t TAAC; /*!< Data read access-time 1 */ - __IO uint8_t NSAC; /*!< Data read access-time 2 in CLK cycles */ - __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ - __IO uint16_t CardComdClasses; /*!< Card command classes */ - __IO uint8_t RdBlockLen; /*!< Max. read data block length */ - __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ - __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */ - __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */ - __IO uint8_t DSRImpl; /*!< DSR implemented */ - __IO uint8_t Reserved2; /*!< Reserved */ - __IO uint32_t DeviceSize; /*!< Device Size */ - __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ - __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ - __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ - __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ - __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */ - __IO uint8_t EraseGrSize; /*!< Erase group size */ - __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */ - __IO uint8_t WrProtectGrSize; /*!< Write protect group size */ - __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */ - __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */ - __IO uint8_t WrSpeedFact; /*!< Write speed factor */ - __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */ - __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ - __IO uint8_t Reserved3; /*!< Reserded */ - __IO uint8_t ContentProtectAppli; /*!< Content protection application */ - __IO uint8_t FileFormatGrouop; /*!< File format group */ - __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ - __IO uint8_t PermWrProtect; /*!< Permanent write protection */ - __IO uint8_t TempWrProtect; /*!< Temporary write protection */ - __IO uint8_t FileFormat; /*!< File Format */ - __IO uint8_t ECC; /*!< ECC code */ - __IO uint8_t CSD_CRC; /*!< CSD CRC */ - __IO uint8_t Reserved4; /*!< always 1*/ -} SD_CSD; - -/** - * @brief Card Identification Data: CID Register - */ -typedef struct -{ - __IO uint8_t ManufacturerID; /*!< ManufacturerID */ - __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */ - __IO uint32_t ProdName1; /*!< Product Name part1 */ - __IO uint8_t ProdName2; /*!< Product Name part2*/ - __IO uint8_t ProdRev; /*!< Product Revision */ - __IO uint32_t ProdSN; /*!< Product Serial Number */ - __IO uint8_t Reserved1; /*!< Reserved1 */ - __IO uint16_t ManufactDate; /*!< Manufacturing Date */ - __IO uint8_t CID_CRC; /*!< CID CRC */ - __IO uint8_t Reserved2; /*!< always 1 */ -} SD_CID; - -/** - * @brief SD Card Status - */ -typedef struct -{ - __IO uint8_t DAT_BUS_WIDTH; - __IO uint8_t SECURED_MODE; - __IO uint16_t SD_CARD_TYPE; - __IO uint32_t SIZE_OF_PROTECTED_AREA; - __IO uint8_t SPEED_CLASS; - __IO uint8_t PERFORMANCE_MOVE; - __IO uint8_t AU_SIZE; - __IO uint16_t ERASE_SIZE; - __IO uint8_t ERASE_TIMEOUT; - __IO uint8_t ERASE_OFFSET; -} SD_CardStatus; - - -/** - * @brief SD Card information - */ -typedef struct -{ - SD_CSD SD_csd; - SD_CID SD_cid; - uint32_t CardCapacity; /*!< Card Capacity */ - uint32_t CardBlockSize; /*!< Card Block Size */ - uint16_t RCA; - uint8_t CardType; -} SD_CardInfo; - -/** - * @} - */ - -/** @defgroup STM32_EVAL_SDIO_SD_Exported_Constants - * @{ - */ - -/** - * @brief SDIO Commands Index - */ -#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) -#define SD_CMD_SEND_OP_COND ((uint8_t)1) -#define SD_CMD_ALL_SEND_CID ((uint8_t)2) -#define SD_CMD_SET_REL_ADDR ((uint8_t)3) /*!< SDIO_SEND_REL_ADDR for SD Card */ -#define SD_CMD_SET_DSR ((uint8_t)4) -#define SD_CMD_SDIO_SEN_OP_COND ((uint8_t)5) -#define SD_CMD_HS_SWITCH ((uint8_t)6) -#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) -#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8) -#define SD_CMD_SEND_CSD ((uint8_t)9) -#define SD_CMD_SEND_CID ((uint8_t)10) -#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD Card doesn't support it */ -#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) -#define SD_CMD_SEND_STATUS ((uint8_t)13) -#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14) -#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15) -#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) -#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) -#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) -#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19) -#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< SD Card doesn't support it */ -#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< SD Card doesn't support it */ -#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) -#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) -#define SD_CMD_PROG_CID ((uint8_t)26) /*!< reserved for manufacturers */ -#define SD_CMD_PROG_CSD ((uint8_t)27) -#define SD_CMD_SET_WRITE_PROT ((uint8_t)28) -#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29) -#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30) -#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< To set the address of the first write - block to be erased. (For SD card only) */ -#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< To set the address of the last write block of the - continuous range to be erased. (For SD card only) */ -#define SD_CMD_ERASE_GRP_START ((uint8_t)35) /*!< To set the address of the first write block to be erased. - (For MMC card only spec 3.31) */ - -#define SD_CMD_ERASE_GRP_END ((uint8_t)36) /*!< To set the address of the last write block of the - continuous range to be erased. (For MMC card only spec 3.31) */ - -#define SD_CMD_ERASE ((uint8_t)38) -#define SD_CMD_FAST_IO ((uint8_t)39) /*!< SD Card doesn't support it */ -#define SD_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD Card doesn't support it */ -#define SD_CMD_LOCK_UNLOCK ((uint8_t)42) -#define SD_CMD_APP_CMD ((uint8_t)55) -#define SD_CMD_GEN_CMD ((uint8_t)56) -#define SD_CMD_NO_CMD ((uint8_t)64) - -/** - * @brief Following commands are SD Card Specific commands. - * SDIO_APP_CMD should be sent before sending these commands. - */ -#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< For SD Card only */ -#define SD_CMD_SD_APP_STAUS ((uint8_t)13) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< For SD Card only */ -#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< For SD Card only */ -#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) /*!< For SD I/O Card only */ -#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O Card only */ - -/** - * @brief Following commands are SD Card Specific security commands. - * SDIO_APP_CMD should be sent before sending these commands. - */ -#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43) /*!< For SD Card only */ -#define SD_CMD_SD_APP_GET_MID ((uint8_t)44) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) /*!< For SD Card only */ -#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) /*!< For SD Card only */ -#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) /*!< For SD Card only */ -#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) /*!< For SD Card only */ - -/* Uncomment the following line to select the SDIO Data transfer mode */ -#define SD_DMA_MODE ((uint32_t)0x00000000) -/*#define SD_POLLING_MODE ((uint32_t)0x00000002)*/ - -/** - * @brief SD detection on its memory slot - */ -#define SD_PRESENT ((uint8_t)0x01) -#define SD_NOT_PRESENT ((uint8_t)0x00) - -/** - * @brief Supported SD Memory Cards - */ -#define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000) -#define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001) -#define SDIO_HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002) -#define SDIO_MULTIMEDIA_CARD ((uint32_t)0x00000003) -#define SDIO_SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004) -#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005) -#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006) -#define SDIO_HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007) - -/** - * @} - */ - -/** @defgroup STM32_EVAL_SDIO_SD_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32_EVAL_SDIO_SD_Exported_Functions - * @{ - */ -void SD_DeInit(void); -SD_Error SD_Init(void); -SDTransferState SD_GetStatus(void); -SDCardState SD_GetState(void); -uint8_t SD_Detect(void); -SD_Error SD_PowerON(void); -SD_Error SD_PowerOFF(void); -SD_Error SD_InitializeCards(void); -SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo); -SD_Error SD_GetCardStatus(SD_CardStatus *cardstatus); -SD_Error SD_EnableWideBusOperation(uint32_t WideMode); -SD_Error SD_SelectDeselect(uint32_t addr); -SD_Error SD_ReadBlock(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize); -SD_Error SD_ReadMultiBlocks(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks); -SD_Error SD_WriteBlock(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize); -SD_Error SD_WriteMultiBlocks(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks); -SDTransferState SD_GetTransferState(void); -SD_Error SD_StopTransfer(void); -SD_Error SD_Erase(uint32_t startaddr, uint32_t endaddr); -SD_Error SD_SendStatus(uint32_t *pcardstatus); -SD_Error SD_SendSDStatus(uint32_t *psdstatus); -SD_Error SD_ProcessIRQSrc(void); -SD_Error SD_WaitReadOperation(void); -SD_Error SD_WaitWriteOperation(void); -#ifdef __cplusplus -} -#endif - -#endif /* __STM32_EVAL_SDIO_SD_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_flash.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_flash.c deleted file mode 100644 index 880a1da2e..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_flash.c +++ /dev/null @@ -1,541 +0,0 @@ -/** - ****************************************************************************** - * @file stm32_eval_spi_flash.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file provides a set of functions needed to manage the SPI M25Pxxx - * FLASH memory mounted on STM32xx-EVAL board (refer to stm32_eval.h - * to know about the boards supporting this memory). - * It implements a high level communication layer for read and write - * from/to this memory. The needed STM32 hardware resources (SPI and - * GPIO) are defined in stm32xx_eval.h file, and the initialization is - * performed in sFLASH_LowLevel_Init() function declared in stm32xx_eval.c - * file. - * You can easily tailor this driver to any other development board, - * by just adapting the defines for hardware resources and - * sFLASH_LowLevel_Init() function. - * - * +-----------------------------------------------------------+ - * | Pin assignment | - * +-----------------------------+---------------+-------------+ - * | STM32 SPI Pins | sFLASH | Pin | - * +-----------------------------+---------------+-------------+ - * | sFLASH_CS_PIN | ChipSelect(/S)| 1 | - * | sFLASH_SPI_MISO_PIN / MISO | DataOut(Q) | 2 | - * | | VCC | 3 (3.3 V)| - * | | GND | 4 (0 V) | - * | sFLASH_SPI_MOSI_PIN / MOSI | DataIn(D) | 5 | - * | sFLASH_SPI_SCK_PIN / SCLK | Clock(C) | 6 | - * | | VCC | 7 (3.3 V)| - * | | VCC | 8 (3.3 V)| - * +-----------------------------+---------------+-------------+ - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32_eval_spi_flash.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup Common - * @{ - */ - -/** @addtogroup STM32_EVAL_SPI_FLASH - * @brief This file includes the M25Pxxx SPI FLASH driver of STM32-EVAL boards. - * @{ - */ - -/** @defgroup STM32_EVAL_SPI_FLASH_Private_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32_EVAL_SPI_FLASH_Private_Defines - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32_EVAL_SPI_FLASH_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32_EVAL_SPI_FLASH_Private_Variables - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32_EVAL_SPI_FLASH_Private_Function_Prototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32_EVAL_SPI_FLASH_Private_Functions - * @{ - */ - -/** - * @brief DeInitializes the peripherals used by the SPI FLASH driver. - * @param None - * @retval None - */ -void sFLASH_DeInit(void) -{ - sFLASH_LowLevel_DeInit(); -} - -/** - * @brief Initializes the peripherals used by the SPI FLASH driver. - * @param None - * @retval None - */ -void sFLASH_Init(void) -{ - SPI_InitTypeDef SPI_InitStructure; - - sFLASH_LowLevel_Init(); - - /*!< Deselect the FLASH: Chip Select high */ - sFLASH_CS_HIGH(); - - /*!< SPI configuration */ - SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; - SPI_InitStructure.SPI_Mode = SPI_Mode_Master; - SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; - SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; - SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; - SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; -#else - SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4; -#endif - - SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; - SPI_InitStructure.SPI_CRCPolynomial = 7; - SPI_Init(sFLASH_SPI, &SPI_InitStructure); - - /*!< Enable the sFLASH_SPI */ - SPI_Cmd(sFLASH_SPI, ENABLE); -} - -/** - * @brief Erases the specified FLASH sector. - * @param SectorAddr: address of the sector to erase. - * @retval None - */ -void sFLASH_EraseSector(uint32_t SectorAddr) -{ - /*!< Send write enable instruction */ - sFLASH_WriteEnable(); - - /*!< Sector Erase */ - /*!< Select the FLASH: Chip Select low */ - sFLASH_CS_LOW(); - /*!< Send Sector Erase instruction */ - sFLASH_SendByte(sFLASH_CMD_SE); - /*!< Send SectorAddr high nibble address byte */ - sFLASH_SendByte((SectorAddr & 0xFF0000) >> 16); - /*!< Send SectorAddr medium nibble address byte */ - sFLASH_SendByte((SectorAddr & 0xFF00) >> 8); - /*!< Send SectorAddr low nibble address byte */ - sFLASH_SendByte(SectorAddr & 0xFF); - /*!< Deselect the FLASH: Chip Select high */ - sFLASH_CS_HIGH(); - - /*!< Wait the end of Flash writing */ - sFLASH_WaitForWriteEnd(); -} - -/** - * @brief Erases the entire FLASH. - * @param None - * @retval None - */ -void sFLASH_EraseBulk(void) -{ - /*!< Send write enable instruction */ - sFLASH_WriteEnable(); - - /*!< Bulk Erase */ - /*!< Select the FLASH: Chip Select low */ - sFLASH_CS_LOW(); - /*!< Send Bulk Erase instruction */ - sFLASH_SendByte(sFLASH_CMD_BE); - /*!< Deselect the FLASH: Chip Select high */ - sFLASH_CS_HIGH(); - - /*!< Wait the end of Flash writing */ - sFLASH_WaitForWriteEnd(); -} - -/** - * @brief Writes more than one byte to the FLASH with a single WRITE cycle - * (Page WRITE sequence). - * @note The number of byte can't exceed the FLASH page size. - * @param pBuffer: pointer to the buffer containing the data to be written - * to the FLASH. - * @param WriteAddr: FLASH's internal address to write to. - * @param NumByteToWrite: number of bytes to write to the FLASH, must be equal - * or less than "sFLASH_PAGESIZE" value. - * @retval None - */ -void sFLASH_WritePage(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite) -{ - /*!< Enable the write access to the FLASH */ - sFLASH_WriteEnable(); - - /*!< Select the FLASH: Chip Select low */ - sFLASH_CS_LOW(); - /*!< Send "Write to Memory " instruction */ - sFLASH_SendByte(sFLASH_CMD_WRITE); - /*!< Send WriteAddr high nibble address byte to write to */ - sFLASH_SendByte((WriteAddr & 0xFF0000) >> 16); - /*!< Send WriteAddr medium nibble address byte to write to */ - sFLASH_SendByte((WriteAddr & 0xFF00) >> 8); - /*!< Send WriteAddr low nibble address byte to write to */ - sFLASH_SendByte(WriteAddr & 0xFF); - - /*!< while there is data to be written on the FLASH */ - while (NumByteToWrite--) - { - /*!< Send the current byte */ - sFLASH_SendByte(*pBuffer); - /*!< Point on the next byte to be written */ - pBuffer++; - } - - /*!< Deselect the FLASH: Chip Select high */ - sFLASH_CS_HIGH(); - - /*!< Wait the end of Flash writing */ - sFLASH_WaitForWriteEnd(); -} - -/** - * @brief Writes block of data to the FLASH. In this function, the number of - * WRITE cycles are reduced, using Page WRITE sequence. - * @param pBuffer: pointer to the buffer containing the data to be written - * to the FLASH. - * @param WriteAddr: FLASH's internal address to write to. - * @param NumByteToWrite: number of bytes to write to the FLASH. - * @retval None - */ -void sFLASH_WriteBuffer(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite) -{ - uint8_t NumOfPage = 0, NumOfSingle = 0, Addr = 0, count = 0, temp = 0; - - Addr = WriteAddr % sFLASH_SPI_PAGESIZE; - count = sFLASH_SPI_PAGESIZE - Addr; - NumOfPage = NumByteToWrite / sFLASH_SPI_PAGESIZE; - NumOfSingle = NumByteToWrite % sFLASH_SPI_PAGESIZE; - - if (Addr == 0) /*!< WriteAddr is sFLASH_PAGESIZE aligned */ - { - if (NumOfPage == 0) /*!< NumByteToWrite < sFLASH_PAGESIZE */ - { - sFLASH_WritePage(pBuffer, WriteAddr, NumByteToWrite); - } - else /*!< NumByteToWrite > sFLASH_PAGESIZE */ - { - while (NumOfPage--) - { - sFLASH_WritePage(pBuffer, WriteAddr, sFLASH_SPI_PAGESIZE); - WriteAddr += sFLASH_SPI_PAGESIZE; - pBuffer += sFLASH_SPI_PAGESIZE; - } - - sFLASH_WritePage(pBuffer, WriteAddr, NumOfSingle); - } - } - else /*!< WriteAddr is not sFLASH_PAGESIZE aligned */ - { - if (NumOfPage == 0) /*!< NumByteToWrite < sFLASH_PAGESIZE */ - { - if (NumOfSingle > count) /*!< (NumByteToWrite + WriteAddr) > sFLASH_PAGESIZE */ - { - temp = NumOfSingle - count; - - sFLASH_WritePage(pBuffer, WriteAddr, count); - WriteAddr += count; - pBuffer += count; - - sFLASH_WritePage(pBuffer, WriteAddr, temp); - } - else - { - sFLASH_WritePage(pBuffer, WriteAddr, NumByteToWrite); - } - } - else /*!< NumByteToWrite > sFLASH_PAGESIZE */ - { - NumByteToWrite -= count; - NumOfPage = NumByteToWrite / sFLASH_SPI_PAGESIZE; - NumOfSingle = NumByteToWrite % sFLASH_SPI_PAGESIZE; - - sFLASH_WritePage(pBuffer, WriteAddr, count); - WriteAddr += count; - pBuffer += count; - - while (NumOfPage--) - { - sFLASH_WritePage(pBuffer, WriteAddr, sFLASH_SPI_PAGESIZE); - WriteAddr += sFLASH_SPI_PAGESIZE; - pBuffer += sFLASH_SPI_PAGESIZE; - } - - if (NumOfSingle != 0) - { - sFLASH_WritePage(pBuffer, WriteAddr, NumOfSingle); - } - } - } -} - -/** - * @brief Reads a block of data from the FLASH. - * @param pBuffer: pointer to the buffer that receives the data read from the FLASH. - * @param ReadAddr: FLASH's internal address to read from. - * @param NumByteToRead: number of bytes to read from the FLASH. - * @retval None - */ -void sFLASH_ReadBuffer(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t NumByteToRead) -{ - /*!< Select the FLASH: Chip Select low */ - sFLASH_CS_LOW(); - - /*!< Send "Read from Memory " instruction */ - sFLASH_SendByte(sFLASH_CMD_READ); - - /*!< Send ReadAddr high nibble address byte to read from */ - sFLASH_SendByte((ReadAddr & 0xFF0000) >> 16); - /*!< Send ReadAddr medium nibble address byte to read from */ - sFLASH_SendByte((ReadAddr& 0xFF00) >> 8); - /*!< Send ReadAddr low nibble address byte to read from */ - sFLASH_SendByte(ReadAddr & 0xFF); - - while (NumByteToRead--) /*!< while there is data to be read */ - { - /*!< Read a byte from the FLASH */ - *pBuffer = sFLASH_SendByte(sFLASH_DUMMY_BYTE); - /*!< Point to the next location where the byte read will be saved */ - pBuffer++; - } - - /*!< Deselect the FLASH: Chip Select high */ - sFLASH_CS_HIGH(); -} - -/** - * @brief Reads FLASH identification. - * @param None - * @retval FLASH identification - */ -uint32_t sFLASH_ReadID(void) -{ - uint32_t Temp = 0, Temp0 = 0, Temp1 = 0, Temp2 = 0; - - /*!< Select the FLASH: Chip Select low */ - sFLASH_CS_LOW(); - - /*!< Send "RDID " instruction */ - sFLASH_SendByte(0x9F); - - /*!< Read a byte from the FLASH */ - Temp0 = sFLASH_SendByte(sFLASH_DUMMY_BYTE); - - /*!< Read a byte from the FLASH */ - Temp1 = sFLASH_SendByte(sFLASH_DUMMY_BYTE); - - /*!< Read a byte from the FLASH */ - Temp2 = sFLASH_SendByte(sFLASH_DUMMY_BYTE); - - /*!< Deselect the FLASH: Chip Select high */ - sFLASH_CS_HIGH(); - - Temp = (Temp0 << 16) | (Temp1 << 8) | Temp2; - - return Temp; -} - -/** - * @brief Initiates a read data byte (READ) sequence from the Flash. - * This is done by driving the /CS line low to select the device, then the READ - * instruction is transmitted followed by 3 bytes address. This function exit - * and keep the /CS line low, so the Flash still being selected. With this - * technique the whole content of the Flash is read with a single READ instruction. - * @param ReadAddr: FLASH's internal address to read from. - * @retval None - */ -void sFLASH_StartReadSequence(uint32_t ReadAddr) -{ - /*!< Select the FLASH: Chip Select low */ - sFLASH_CS_LOW(); - - /*!< Send "Read from Memory " instruction */ - sFLASH_SendByte(sFLASH_CMD_READ); - - /*!< Send the 24-bit address of the address to read from -------------------*/ - /*!< Send ReadAddr high nibble address byte */ - sFLASH_SendByte((ReadAddr & 0xFF0000) >> 16); - /*!< Send ReadAddr medium nibble address byte */ - sFLASH_SendByte((ReadAddr& 0xFF00) >> 8); - /*!< Send ReadAddr low nibble address byte */ - sFLASH_SendByte(ReadAddr & 0xFF); -} - -/** - * @brief Reads a byte from the SPI Flash. - * @note This function must be used only if the Start_Read_Sequence function - * has been previously called. - * @param None - * @retval Byte Read from the SPI Flash. - */ -uint8_t sFLASH_ReadByte(void) -{ - return (sFLASH_SendByte(sFLASH_DUMMY_BYTE)); -} - -/** - * @brief Sends a byte through the SPI interface and return the byte received - * from the SPI bus. - * @param byte: byte to send. - * @retval The value of the received byte. - */ -uint8_t sFLASH_SendByte(uint8_t byte) -{ - /*!< Loop while DR register in not emplty */ - while (SPI_I2S_GetFlagStatus(sFLASH_SPI, SPI_I2S_FLAG_TXE) == RESET); - - /*!< Send byte through the SPI1 peripheral */ - SPI_I2S_SendData(sFLASH_SPI, byte); - - /*!< Wait to receive a byte */ - while (SPI_I2S_GetFlagStatus(sFLASH_SPI, SPI_I2S_FLAG_RXNE) == RESET); - - /*!< Return the byte read from the SPI bus */ - return SPI_I2S_ReceiveData(sFLASH_SPI); -} - -/** - * @brief Sends a Half Word through the SPI interface and return the Half Word - * received from the SPI bus. - * @param HalfWord: Half Word to send. - * @retval The value of the received Half Word. - */ -uint16_t sFLASH_SendHalfWord(uint16_t HalfWord) -{ - /*!< Loop while DR register in not emplty */ - while (SPI_I2S_GetFlagStatus(sFLASH_SPI, SPI_I2S_FLAG_TXE) == RESET); - - /*!< Send Half Word through the sFLASH peripheral */ - SPI_I2S_SendData(sFLASH_SPI, HalfWord); - - /*!< Wait to receive a Half Word */ - while (SPI_I2S_GetFlagStatus(sFLASH_SPI, SPI_I2S_FLAG_RXNE) == RESET); - - /*!< Return the Half Word read from the SPI bus */ - return SPI_I2S_ReceiveData(sFLASH_SPI); -} - -/** - * @brief Enables the write access to the FLASH. - * @param None - * @retval None - */ -void sFLASH_WriteEnable(void) -{ - /*!< Select the FLASH: Chip Select low */ - sFLASH_CS_LOW(); - - /*!< Send "Write Enable" instruction */ - sFLASH_SendByte(sFLASH_CMD_WREN); - - /*!< Deselect the FLASH: Chip Select high */ - sFLASH_CS_HIGH(); -} - -/** - * @brief Polls the status of the Write In Progress (WIP) flag in the FLASH's - * status register and loop until write opertaion has completed. - * @param None - * @retval None - */ -void sFLASH_WaitForWriteEnd(void) -{ - uint8_t flashstatus = 0; - - /*!< Select the FLASH: Chip Select low */ - sFLASH_CS_LOW(); - - /*!< Send "Read Status Register" instruction */ - sFLASH_SendByte(sFLASH_CMD_RDSR); - - /*!< Loop as long as the memory is busy with a write cycle */ - do - { - /*!< Send a dummy byte to generate the clock needed by the FLASH - and put the value of the status register in FLASH_Status variable */ - flashstatus = sFLASH_SendByte(sFLASH_DUMMY_BYTE); - - } - while ((flashstatus & sFLASH_WIP_FLAG) == SET); /* Write in progress */ - - /*!< Deselect the FLASH: Chip Select high */ - sFLASH_CS_HIGH(); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_flash.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_flash.h deleted file mode 100644 index cada05d2f..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_flash.h +++ /dev/null @@ -1,151 +0,0 @@ -/** - ****************************************************************************** - * @file stm32_eval_spi_flash.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains all the functions prototypes for the stm32_eval_spi_flash - * firmware driver. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32_EVAL_SPI_FLASH_H -#define __STM32_EVAL_SPI_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32_eval.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup Common - * @{ - */ - -/** @addtogroup STM32_EVAL_SPI_FLASH - * @{ - */ - -/** @defgroup STM32_EVAL_SPI_FLASH_Exported_Types - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32_EVAL_SPI_FLASH_Exported_Constants - * @{ - */ -/** - * @brief M25P SPI Flash supported commands - */ -#define sFLASH_CMD_WRITE 0x02 /*!< Write to Memory instruction */ -#define sFLASH_CMD_WRSR 0x01 /*!< Write Status Register instruction */ -#define sFLASH_CMD_WREN 0x06 /*!< Write enable instruction */ -#define sFLASH_CMD_READ 0x03 /*!< Read from Memory instruction */ -#define sFLASH_CMD_RDSR 0x05 /*!< Read Status Register instruction */ -#define sFLASH_CMD_RDID 0x9F /*!< Read identification */ -#define sFLASH_CMD_SE 0xD8 /*!< Sector Erase instruction */ -#define sFLASH_CMD_BE 0xC7 /*!< Bulk Erase instruction */ - -#define sFLASH_WIP_FLAG 0x01 /*!< Write In Progress (WIP) flag */ - -#define sFLASH_DUMMY_BYTE 0xA5 -#define sFLASH_SPI_PAGESIZE 0x100 - -#define sFLASH_M25P128_ID 0x202018 -#define sFLASH_M25P64_ID 0x202017 - -/** - * @} - */ - -/** @defgroup STM32_EVAL_SPI_FLASH_Exported_Macros - * @{ - */ -/** - * @brief Select sFLASH: Chip Select pin low - */ -#define sFLASH_CS_LOW() GPIO_ResetBits(sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN) -/** - * @brief Deselect sFLASH: Chip Select pin high - */ -#define sFLASH_CS_HIGH() GPIO_SetBits(sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN) -/** - * @} - */ - - - -/** @defgroup STM32_EVAL_SPI_FLASH_Exported_Functions - * @{ - */ -/** - * @brief High layer functions - */ -void sFLASH_DeInit(void); -void sFLASH_Init(void); -void sFLASH_EraseSector(uint32_t SectorAddr); -void sFLASH_EraseBulk(void); -void sFLASH_WritePage(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite); -void sFLASH_WriteBuffer(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite); -void sFLASH_ReadBuffer(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t NumByteToRead); -uint32_t sFLASH_ReadID(void); -void sFLASH_StartReadSequence(uint32_t ReadAddr); - -/** - * @brief Low layer functions - */ -uint8_t sFLASH_ReadByte(void); -uint8_t sFLASH_SendByte(uint8_t byte); -uint16_t sFLASH_SendHalfWord(uint16_t HalfWord); -void sFLASH_WriteEnable(void); -void sFLASH_WaitForWriteEnd(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32_EVAL_SPI_FLASH_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_sd.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_sd.c deleted file mode 100644 index cf077cc62..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_sd.c +++ /dev/null @@ -1,901 +0,0 @@ -/** - ****************************************************************************** - * @file stm32_eval_spi_sd.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file provides a set of functions needed to manage the SPI SD - * Card memory mounted on STM32xx-EVAL board (refer to stm32_eval.h - * to know about the boards supporting this memory). - * It implements a high level communication layer for read and write - * from/to this memory. The needed STM32 hardware resources (SPI and - * GPIO) are defined in stm32xx_eval.h file, and the initialization is - * performed in SD_LowLevel_Init() function declared in stm32xx_eval.c - * file. - * You can easily tailor this driver to any other development board, - * by just adapting the defines for hardware resources and - * SD_LowLevel_Init() function. - * - * +-------------------------------------------------------+ - * | Pin assignment | - * +-------------------------+---------------+-------------+ - * | STM32 SPI Pins | SD | Pin | - * +-------------------------+---------------+-------------+ - * | SD_SPI_CS_PIN | ChipSelect | 1 | - * | SD_SPI_MOSI_PIN / MOSI | DataIn | 2 | - * | | GND | 3 (0 V) | - * | | VDD | 4 (3.3 V)| - * | SD_SPI_SCK_PIN / SCLK | Clock | 5 | - * | | GND | 6 (0 V) | - * | SD_SPI_MISO_PIN / MISO | DataOut | 7 | - * +-------------------------+---------------+-------------+ - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32_eval_spi_sd.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup Common - * @{ - */ - -/** @addtogroup STM32_EVAL_SPI_SD - * @brief This file includes the SD card driver of STM32-EVAL boards. - * @{ - */ - -/** @defgroup STM32_EVAL_SPI_SD_Private_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32_EVAL_SPI_SD_Private_Defines - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32_EVAL_SPI_SD_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32_EVAL_SPI_SD_Private_Variables - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32_EVAL_SPI_SD_Private_Function_Prototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32_EVAL_SPI_SD_Private_Functions - * @{ - */ - -/** - * @brief DeInitializes the SD/SD communication. - * @param None - * @retval None - */ -void SD_DeInit(void) -{ - SD_LowLevel_DeInit(); -} - -/** - * @brief Initializes the SD/SD communication. - * @param None - * @retval The SD Response: - * - SD_RESPONSE_FAILURE: Sequence failed - * - SD_RESPONSE_NO_ERROR: Sequence succeed - */ -SD_Error SD_Init(void) -{ - uint32_t i = 0; - - /*!< Initialize SD_SPI */ - SD_LowLevel_Init(); - - /*!< SD chip select high */ - SD_CS_HIGH(); - - /*!< Send dummy byte 0xFF, 10 times with CS high */ - /*!< Rise CS and MOSI for 80 clocks cycles */ - for (i = 0; i <= 9; i++) - { - /*!< Send dummy byte 0xFF */ - SD_WriteByte(SD_DUMMY_BYTE); - } - /*------------Put SD in SPI mode--------------*/ - /*!< SD initialized and set to SPI mode properly */ - return (SD_GoIdleState()); -} - -/** - * @brief Detect if SD card is correctly plugged in the memory slot. - * @param None - * @retval Return if SD is detected or not - */ -uint8_t SD_Detect(void) -{ - __IO uint8_t status = SD_PRESENT; - - /*!< Check GPIO to detect SD */ - if (GPIO_ReadInputData(SD_DETECT_GPIO_PORT) & SD_DETECT_PIN) - { - status = SD_NOT_PRESENT; - } - return status; -} - -/** - * @brief Returns information about specific card. - * @param cardinfo: pointer to a SD_CardInfo structure that contains all SD - * card information. - * @retval The SD Response: - * - SD_RESPONSE_FAILURE: Sequence failed - * - SD_RESPONSE_NO_ERROR: Sequence succeed - */ -SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo) -{ - SD_Error status = SD_RESPONSE_FAILURE; - - status = SD_GetCSDRegister(&(cardinfo->SD_csd)); - status = SD_GetCIDRegister(&(cardinfo->SD_cid)); - cardinfo->CardCapacity = (cardinfo->SD_csd.DeviceSize + 1) ; - cardinfo->CardCapacity *= (1 << (cardinfo->SD_csd.DeviceSizeMul + 2)); - cardinfo->CardBlockSize = 1 << (cardinfo->SD_csd.RdBlockLen); - cardinfo->CardCapacity *= cardinfo->CardBlockSize; - - /*!< Returns the reponse */ - return status; -} - -/** - * @brief Reads a block of data from the SD. - * @param pBuffer: pointer to the buffer that receives the data read from the - * SD. - * @param ReadAddr: SD's internal address to read from. - * @param BlockSize: the SD card Data block size. - * @retval The SD Response: - * - SD_RESPONSE_FAILURE: Sequence failed - * - SD_RESPONSE_NO_ERROR: Sequence succeed - */ -SD_Error SD_ReadBlock(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize) -{ - uint32_t i = 0; - SD_Error rvalue = SD_RESPONSE_FAILURE; - - /*!< SD chip select low */ - SD_CS_LOW(); - - /*!< Send CMD17 (SD_CMD_READ_SINGLE_BLOCK) to read one block */ - SD_SendCmd(SD_CMD_READ_SINGLE_BLOCK, ReadAddr, 0xFF); - - /*!< Check if the SD acknowledged the read block command: R1 response (0x00: no errors) */ - if (!SD_GetResponse(SD_RESPONSE_NO_ERROR)) - { - /*!< Now look for the data token to signify the start of the data */ - if (!SD_GetResponse(SD_START_DATA_SINGLE_BLOCK_READ)) - { - /*!< Read the SD block data : read NumByteToRead data */ - for (i = 0; i < BlockSize; i++) - { - /*!< Save the received data */ - *pBuffer = SD_ReadByte(); - - /*!< Point to the next location where the byte read will be saved */ - pBuffer++; - } - /*!< Get CRC bytes (not really needed by us, but required by SD) */ - SD_ReadByte(); - SD_ReadByte(); - /*!< Set response value to success */ - rvalue = SD_RESPONSE_NO_ERROR; - } - } - /*!< SD chip select high */ - SD_CS_HIGH(); - - /*!< Send dummy byte: 8 Clock pulses of delay */ - SD_WriteByte(SD_DUMMY_BYTE); - - /*!< Returns the reponse */ - return rvalue; -} - -/** - * @brief Reads multiple block of data from the SD. - * @param pBuffer: pointer to the buffer that receives the data read from the - * SD. - * @param ReadAddr: SD's internal address to read from. - * @param BlockSize: the SD card Data block size. - * @param NumberOfBlocks: number of blocks to be read. - * @retval The SD Response: - * - SD_RESPONSE_FAILURE: Sequence failed - * - SD_RESPONSE_NO_ERROR: Sequence succeed - */ -SD_Error SD_ReadMultiBlocks(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks) -{ - uint32_t i = 0, Offset = 0; - SD_Error rvalue = SD_RESPONSE_FAILURE; - - /*!< SD chip select low */ - SD_CS_LOW(); - /*!< Data transfer */ - while (NumberOfBlocks--) - { - /*!< Send CMD17 (SD_CMD_READ_SINGLE_BLOCK) to read one block */ - SD_SendCmd (SD_CMD_READ_SINGLE_BLOCK, ReadAddr + Offset, 0xFF); - /*!< Check if the SD acknowledged the read block command: R1 response (0x00: no errors) */ - if (SD_GetResponse(SD_RESPONSE_NO_ERROR)) - { - return SD_RESPONSE_FAILURE; - } - /*!< Now look for the data token to signify the start of the data */ - if (!SD_GetResponse(SD_START_DATA_SINGLE_BLOCK_READ)) - { - /*!< Read the SD block data : read NumByteToRead data */ - for (i = 0; i < BlockSize; i++) - { - /*!< Read the pointed data */ - *pBuffer = SD_ReadByte(); - /*!< Point to the next location where the byte read will be saved */ - pBuffer++; - } - /*!< Set next read address*/ - Offset += 512; - /*!< get CRC bytes (not really needed by us, but required by SD) */ - SD_ReadByte(); - SD_ReadByte(); - /*!< Set response value to success */ - rvalue = SD_RESPONSE_NO_ERROR; - } - else - { - /*!< Set response value to failure */ - rvalue = SD_RESPONSE_FAILURE; - } - } - /*!< SD chip select high */ - SD_CS_HIGH(); - /*!< Send dummy byte: 8 Clock pulses of delay */ - SD_WriteByte(SD_DUMMY_BYTE); - /*!< Returns the reponse */ - return rvalue; -} - -/** - * @brief Writes a block on the SD - * @param pBuffer: pointer to the buffer containing the data to be written on - * the SD. - * @param WriteAddr: address to write on. - * @param BlockSize: the SD card Data block size. - * @retval The SD Response: - * - SD_RESPONSE_FAILURE: Sequence failed - * - SD_RESPONSE_NO_ERROR: Sequence succeed - */ -SD_Error SD_WriteBlock(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize) -{ - uint32_t i = 0; - SD_Error rvalue = SD_RESPONSE_FAILURE; - - /*!< SD chip select low */ - SD_CS_LOW(); - - /*!< Send CMD24 (SD_CMD_WRITE_SINGLE_BLOCK) to write multiple block */ - SD_SendCmd(SD_CMD_WRITE_SINGLE_BLOCK, WriteAddr, 0xFF); - - /*!< Check if the SD acknowledged the write block command: R1 response (0x00: no errors) */ - if (!SD_GetResponse(SD_RESPONSE_NO_ERROR)) - { - /*!< Send a dummy byte */ - SD_WriteByte(SD_DUMMY_BYTE); - - /*!< Send the data token to signify the start of the data */ - SD_WriteByte(0xFE); - - /*!< Write the block data to SD : write count data by block */ - for (i = 0; i < BlockSize; i++) - { - /*!< Send the pointed byte */ - SD_WriteByte(*pBuffer); - /*!< Point to the next location where the byte read will be saved */ - pBuffer++; - } - /*!< Put CRC bytes (not really needed by us, but required by SD) */ - SD_ReadByte(); - SD_ReadByte(); - - /*!< Read data response */ - if (SD_GetDataResponse() == SD_DATA_OK) - { - rvalue = SD_RESPONSE_NO_ERROR; - } - } - /*!< SD chip select high */ - SD_CS_HIGH(); - /*!< Send dummy byte: 8 Clock pulses of delay */ - SD_WriteByte(SD_DUMMY_BYTE); - - /*!< Returns the reponse */ - return rvalue; -} - -/** - * @brief Writes many blocks on the SD - * @param pBuffer: pointer to the buffer containing the data to be written on - * the SD. - * @param WriteAddr: address to write on. - * @param BlockSize: the SD card Data block size. - * @param NumberOfBlocks: number of blocks to be written. - * @retval The SD Response: - * - SD_RESPONSE_FAILURE: Sequence failed - * - SD_RESPONSE_NO_ERROR: Sequence succeed - */ -SD_Error SD_WriteMultiBlocks(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks) -{ - uint32_t i = 0, Offset = 0; - SD_Error rvalue = SD_RESPONSE_FAILURE; - - /*!< SD chip select low */ - SD_CS_LOW(); - /*!< Data transfer */ - while (NumberOfBlocks--) - { - /*!< Send CMD24 (SD_CMD_WRITE_SINGLE_BLOCK) to write blocks */ - SD_SendCmd(SD_CMD_WRITE_SINGLE_BLOCK, WriteAddr + Offset, 0xFF); - /*!< Check if the SD acknowledged the write block command: R1 response (0x00: no errors) */ - if (SD_GetResponse(SD_RESPONSE_NO_ERROR)) - { - return SD_RESPONSE_FAILURE; - } - /*!< Send dummy byte */ - SD_WriteByte(SD_DUMMY_BYTE); - /*!< Send the data token to signify the start of the data */ - SD_WriteByte(SD_START_DATA_SINGLE_BLOCK_WRITE); - /*!< Write the block data to SD : write count data by block */ - for (i = 0; i < BlockSize; i++) - { - /*!< Send the pointed byte */ - SD_WriteByte(*pBuffer); - /*!< Point to the next location where the byte read will be saved */ - pBuffer++; - } - /*!< Set next write address */ - Offset += 512; - /*!< Put CRC bytes (not really needed by us, but required by SD) */ - SD_ReadByte(); - SD_ReadByte(); - /*!< Read data response */ - if (SD_GetDataResponse() == SD_DATA_OK) - { - /*!< Set response value to success */ - rvalue = SD_RESPONSE_NO_ERROR; - } - else - { - /*!< Set response value to failure */ - rvalue = SD_RESPONSE_FAILURE; - } - } - /*!< SD chip select high */ - SD_CS_HIGH(); - /*!< Send dummy byte: 8 Clock pulses of delay */ - SD_WriteByte(SD_DUMMY_BYTE); - /*!< Returns the reponse */ - return rvalue; -} - -/** - * @brief Read the CSD card register. - * Reading the contents of the CSD register in SPI mode is a simple - * read-block transaction. - * @param SD_csd: pointer on an SCD register structure - * @retval The SD Response: - * - SD_RESPONSE_FAILURE: Sequence failed - * - SD_RESPONSE_NO_ERROR: Sequence succeed - */ -SD_Error SD_GetCSDRegister(SD_CSD* SD_csd) -{ - uint32_t i = 0; - SD_Error rvalue = SD_RESPONSE_FAILURE; - uint8_t CSD_Tab[16]; - - /*!< SD chip select low */ - SD_CS_LOW(); - /*!< Send CMD9 (CSD register) or CMD10(CSD register) */ - SD_SendCmd(SD_CMD_SEND_CSD, 0, 0xFF); - /*!< Wait for response in the R1 format (0x00 is no errors) */ - if (!SD_GetResponse(SD_RESPONSE_NO_ERROR)) - { - if (!SD_GetResponse(SD_START_DATA_SINGLE_BLOCK_READ)) - { - for (i = 0; i < 16; i++) - { - /*!< Store CSD register value on CSD_Tab */ - CSD_Tab[i] = SD_ReadByte(); - } - } - /*!< Get CRC bytes (not really needed by us, but required by SD) */ - SD_WriteByte(SD_DUMMY_BYTE); - SD_WriteByte(SD_DUMMY_BYTE); - /*!< Set response value to success */ - rvalue = SD_RESPONSE_NO_ERROR; - } - /*!< SD chip select high */ - SD_CS_HIGH(); - /*!< Send dummy byte: 8 Clock pulses of delay */ - SD_WriteByte(SD_DUMMY_BYTE); - - /*!< Byte 0 */ - SD_csd->CSDStruct = (CSD_Tab[0] & 0xC0) >> 6; - SD_csd->SysSpecVersion = (CSD_Tab[0] & 0x3C) >> 2; - SD_csd->Reserved1 = CSD_Tab[0] & 0x03; - - /*!< Byte 1 */ - SD_csd->TAAC = CSD_Tab[1]; - - /*!< Byte 2 */ - SD_csd->NSAC = CSD_Tab[2]; - - /*!< Byte 3 */ - SD_csd->MaxBusClkFrec = CSD_Tab[3]; - - /*!< Byte 4 */ - SD_csd->CardComdClasses = CSD_Tab[4] << 4; - - /*!< Byte 5 */ - SD_csd->CardComdClasses |= (CSD_Tab[5] & 0xF0) >> 4; - SD_csd->RdBlockLen = CSD_Tab[5] & 0x0F; - - /*!< Byte 6 */ - SD_csd->PartBlockRead = (CSD_Tab[6] & 0x80) >> 7; - SD_csd->WrBlockMisalign = (CSD_Tab[6] & 0x40) >> 6; - SD_csd->RdBlockMisalign = (CSD_Tab[6] & 0x20) >> 5; - SD_csd->DSRImpl = (CSD_Tab[6] & 0x10) >> 4; - SD_csd->Reserved2 = 0; /*!< Reserved */ - - SD_csd->DeviceSize = (CSD_Tab[6] & 0x03) << 10; - - /*!< Byte 7 */ - SD_csd->DeviceSize |= (CSD_Tab[7]) << 2; - - /*!< Byte 8 */ - SD_csd->DeviceSize |= (CSD_Tab[8] & 0xC0) >> 6; - - SD_csd->MaxRdCurrentVDDMin = (CSD_Tab[8] & 0x38) >> 3; - SD_csd->MaxRdCurrentVDDMax = (CSD_Tab[8] & 0x07); - - /*!< Byte 9 */ - SD_csd->MaxWrCurrentVDDMin = (CSD_Tab[9] & 0xE0) >> 5; - SD_csd->MaxWrCurrentVDDMax = (CSD_Tab[9] & 0x1C) >> 2; - SD_csd->DeviceSizeMul = (CSD_Tab[9] & 0x03) << 1; - /*!< Byte 10 */ - SD_csd->DeviceSizeMul |= (CSD_Tab[10] & 0x80) >> 7; - - SD_csd->EraseGrSize = (CSD_Tab[10] & 0x40) >> 6; - SD_csd->EraseGrMul = (CSD_Tab[10] & 0x3F) << 1; - - /*!< Byte 11 */ - SD_csd->EraseGrMul |= (CSD_Tab[11] & 0x80) >> 7; - SD_csd->WrProtectGrSize = (CSD_Tab[11] & 0x7F); - - /*!< Byte 12 */ - SD_csd->WrProtectGrEnable = (CSD_Tab[12] & 0x80) >> 7; - SD_csd->ManDeflECC = (CSD_Tab[12] & 0x60) >> 5; - SD_csd->WrSpeedFact = (CSD_Tab[12] & 0x1C) >> 2; - SD_csd->MaxWrBlockLen = (CSD_Tab[12] & 0x03) << 2; - - /*!< Byte 13 */ - SD_csd->MaxWrBlockLen |= (CSD_Tab[13] & 0xC0) >> 6; - SD_csd->WriteBlockPaPartial = (CSD_Tab[13] & 0x20) >> 5; - SD_csd->Reserved3 = 0; - SD_csd->ContentProtectAppli = (CSD_Tab[13] & 0x01); - - /*!< Byte 14 */ - SD_csd->FileFormatGrouop = (CSD_Tab[14] & 0x80) >> 7; - SD_csd->CopyFlag = (CSD_Tab[14] & 0x40) >> 6; - SD_csd->PermWrProtect = (CSD_Tab[14] & 0x20) >> 5; - SD_csd->TempWrProtect = (CSD_Tab[14] & 0x10) >> 4; - SD_csd->FileFormat = (CSD_Tab[14] & 0x0C) >> 2; - SD_csd->ECC = (CSD_Tab[14] & 0x03); - - /*!< Byte 15 */ - SD_csd->CSD_CRC = (CSD_Tab[15] & 0xFE) >> 1; - SD_csd->Reserved4 = 1; - - /*!< Return the reponse */ - return rvalue; -} - -/** - * @brief Read the CID card register. - * Reading the contents of the CID register in SPI mode is a simple - * read-block transaction. - * @param SD_cid: pointer on an CID register structure - * @retval The SD Response: - * - SD_RESPONSE_FAILURE: Sequence failed - * - SD_RESPONSE_NO_ERROR: Sequence succeed - */ -SD_Error SD_GetCIDRegister(SD_CID* SD_cid) -{ - uint32_t i = 0; - SD_Error rvalue = SD_RESPONSE_FAILURE; - uint8_t CID_Tab[16]; - - /*!< SD chip select low */ - SD_CS_LOW(); - - /*!< Send CMD10 (CID register) */ - SD_SendCmd(SD_CMD_SEND_CID, 0, 0xFF); - - /*!< Wait for response in the R1 format (0x00 is no errors) */ - if (!SD_GetResponse(SD_RESPONSE_NO_ERROR)) - { - if (!SD_GetResponse(SD_START_DATA_SINGLE_BLOCK_READ)) - { - /*!< Store CID register value on CID_Tab */ - for (i = 0; i < 16; i++) - { - CID_Tab[i] = SD_ReadByte(); - } - } - /*!< Get CRC bytes (not really needed by us, but required by SD) */ - SD_WriteByte(SD_DUMMY_BYTE); - SD_WriteByte(SD_DUMMY_BYTE); - /*!< Set response value to success */ - rvalue = SD_RESPONSE_NO_ERROR; - } - /*!< SD chip select high */ - SD_CS_HIGH(); - /*!< Send dummy byte: 8 Clock pulses of delay */ - SD_WriteByte(SD_DUMMY_BYTE); - - /*!< Byte 0 */ - SD_cid->ManufacturerID = CID_Tab[0]; - - /*!< Byte 1 */ - SD_cid->OEM_AppliID = CID_Tab[1] << 8; - - /*!< Byte 2 */ - SD_cid->OEM_AppliID |= CID_Tab[2]; - - /*!< Byte 3 */ - SD_cid->ProdName1 = CID_Tab[3] << 24; - - /*!< Byte 4 */ - SD_cid->ProdName1 |= CID_Tab[4] << 16; - - /*!< Byte 5 */ - SD_cid->ProdName1 |= CID_Tab[5] << 8; - - /*!< Byte 6 */ - SD_cid->ProdName1 |= CID_Tab[6]; - - /*!< Byte 7 */ - SD_cid->ProdName2 = CID_Tab[7]; - - /*!< Byte 8 */ - SD_cid->ProdRev = CID_Tab[8]; - - /*!< Byte 9 */ - SD_cid->ProdSN = CID_Tab[9] << 24; - - /*!< Byte 10 */ - SD_cid->ProdSN |= CID_Tab[10] << 16; - - /*!< Byte 11 */ - SD_cid->ProdSN |= CID_Tab[11] << 8; - - /*!< Byte 12 */ - SD_cid->ProdSN |= CID_Tab[12]; - - /*!< Byte 13 */ - SD_cid->Reserved1 |= (CID_Tab[13] & 0xF0) >> 4; - SD_cid->ManufactDate = (CID_Tab[13] & 0x0F) << 8; - - /*!< Byte 14 */ - SD_cid->ManufactDate |= CID_Tab[14]; - - /*!< Byte 15 */ - SD_cid->CID_CRC = (CID_Tab[15] & 0xFE) >> 1; - SD_cid->Reserved2 = 1; - - /*!< Return the reponse */ - return rvalue; -} - -/** - * @brief Send 5 bytes command to the SD card. - * @param Cmd: The user expected command to send to SD card. - * @param Arg: The command argument. - * @param Crc: The CRC. - * @retval None - */ -void SD_SendCmd(uint8_t Cmd, uint32_t Arg, uint8_t Crc) -{ - uint32_t i = 0x00; - - uint8_t Frame[6]; - - Frame[0] = (Cmd | 0x40); /*!< Construct byte 1 */ - - Frame[1] = (uint8_t)(Arg >> 24); /*!< Construct byte 2 */ - - Frame[2] = (uint8_t)(Arg >> 16); /*!< Construct byte 3 */ - - Frame[3] = (uint8_t)(Arg >> 8); /*!< Construct byte 4 */ - - Frame[4] = (uint8_t)(Arg); /*!< Construct byte 5 */ - - Frame[5] = (Crc); /*!< Construct CRC: byte 6 */ - - for (i = 0; i < 6; i++) - { - SD_WriteByte(Frame[i]); /*!< Send the Cmd bytes */ - } -} - -/** - * @brief Get SD card data response. - * @param None - * @retval The SD status: Read data response xxx01 - * - status 010: Data accecpted - * - status 101: Data rejected due to a crc error - * - status 110: Data rejected due to a Write error. - * - status 111: Data rejected due to other error. - */ -uint8_t SD_GetDataResponse(void) -{ - uint32_t i = 0; - uint8_t response, rvalue; - - while (i <= 64) - { - /*!< Read resonse */ - response = SD_ReadByte(); - /*!< Mask unused bits */ - response &= 0x1F; - switch (response) - { - case SD_DATA_OK: - { - rvalue = SD_DATA_OK; - break; - } - case SD_DATA_CRC_ERROR: - return SD_DATA_CRC_ERROR; - case SD_DATA_WRITE_ERROR: - return SD_DATA_WRITE_ERROR; - default: - { - rvalue = SD_DATA_OTHER_ERROR; - break; - } - } - /*!< Exit loop in case of data ok */ - if (rvalue == SD_DATA_OK) - break; - /*!< Increment loop counter */ - i++; - } - - /*!< Wait null data */ - while (SD_ReadByte() == 0); - - /*!< Return response */ - return response; -} - -/** - * @brief Returns the SD response. - * @param None - * @retval The SD Response: - * - SD_RESPONSE_FAILURE: Sequence failed - * - SD_RESPONSE_NO_ERROR: Sequence succeed - */ -SD_Error SD_GetResponse(uint8_t Response) -{ - uint32_t Count = 0xFFF; - - /*!< Check if response is got or a timeout is happen */ - while ((SD_ReadByte() != Response) && Count) - { - Count--; - } - if (Count == 0) - { - /*!< After time out */ - return SD_RESPONSE_FAILURE; - } - else - { - /*!< Right response got */ - return SD_RESPONSE_NO_ERROR; - } -} - -/** - * @brief Returns the SD status. - * @param None - * @retval The SD status. - */ -uint16_t SD_GetStatus(void) -{ - uint16_t Status = 0; - - /*!< SD chip select low */ - SD_CS_LOW(); - - /*!< Send CMD13 (SD_SEND_STATUS) to get SD status */ - SD_SendCmd(SD_CMD_SEND_STATUS, 0, 0xFF); - - Status = SD_ReadByte(); - Status |= (uint16_t)(SD_ReadByte() << 8); - - /*!< SD chip select high */ - SD_CS_HIGH(); - - /*!< Send dummy byte 0xFF */ - SD_WriteByte(SD_DUMMY_BYTE); - - return Status; -} - -/** - * @brief Put SD in Idle state. - * @param None - * @retval The SD Response: - * - SD_RESPONSE_FAILURE: Sequence failed - * - SD_RESPONSE_NO_ERROR: Sequence succeed - */ -SD_Error SD_GoIdleState(void) -{ - /*!< SD chip select low */ - SD_CS_LOW(); - - /*!< Send CMD0 (SD_CMD_GO_IDLE_STATE) to put SD in SPI mode */ - SD_SendCmd(SD_CMD_GO_IDLE_STATE, 0, 0x95); - - /*!< Wait for In Idle State Response (R1 Format) equal to 0x01 */ - if (SD_GetResponse(SD_IN_IDLE_STATE)) - { - /*!< No Idle State Response: return response failue */ - return SD_RESPONSE_FAILURE; - } - /*----------Activates the card initialization process-----------*/ - do - { - /*!< SD chip select high */ - SD_CS_HIGH(); - - /*!< Send Dummy byte 0xFF */ - SD_WriteByte(SD_DUMMY_BYTE); - - /*!< SD chip select low */ - SD_CS_LOW(); - - /*!< Send CMD1 (Activates the card process) until response equal to 0x0 */ - SD_SendCmd(SD_CMD_SEND_OP_COND, 0, 0xFF); - /*!< Wait for no error Response (R1 Format) equal to 0x00 */ - } - while (SD_GetResponse(SD_RESPONSE_NO_ERROR)); - - /*!< SD chip select high */ - SD_CS_HIGH(); - - /*!< Send dummy byte 0xFF */ - SD_WriteByte(SD_DUMMY_BYTE); - - return SD_RESPONSE_NO_ERROR; -} - -/** - * @brief Write a byte on the SD. - * @param Data: byte to send. - * @retval None - */ -uint8_t SD_WriteByte(uint8_t Data) -{ - /*!< Wait until the transmit buffer is empty */ - while(SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_TXE) == RESET) - { - } - - /*!< Send the byte */ - SPI_I2S_SendData(SD_SPI, Data); - - /*!< Wait to receive a byte*/ - while(SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_RXNE) == RESET) - { - } - - /*!< Return the byte read from the SPI bus */ - return SPI_I2S_ReceiveData(SD_SPI); -} - -/** - * @brief Read a byte from the SD. - * @param None - * @retval The received byte. - */ -uint8_t SD_ReadByte(void) -{ - uint8_t Data = 0; - - /*!< Wait until the transmit buffer is empty */ - while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_TXE) == RESET) - { - } - /*!< Send the byte */ - SPI_I2S_SendData(SD_SPI, SD_DUMMY_BYTE); - - /*!< Wait until a data is received */ - while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_RXNE) == RESET) - { - } - /*!< Get the received data */ - Data = SPI_I2S_ReceiveData(SD_SPI); - - /*!< Return the shifted data */ - return Data; -} - -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_sd.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_sd.h deleted file mode 100644 index 96c28880b..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_sd.h +++ /dev/null @@ -1,280 +0,0 @@ -/** - ****************************************************************************** - * @file stm32_eval_spi_sd.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains all the functions prototypes for the stm32_eval_spi_sd - * firmware driver. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32_EVAL_SPI_SD_H -#define __STM32_EVAL_SPI_SD_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32_eval.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup Common - * @{ - */ - -/** @addtogroup STM32_EVAL_SPI_SD - * @{ - */ - -/** @defgroup STM32_EVAL_SPI_SD_Exported_Types - * @{ - */ - -typedef enum -{ -/** - * @brief SD reponses and error flags - */ - SD_RESPONSE_NO_ERROR = (0x00), - SD_IN_IDLE_STATE = (0x01), - SD_ERASE_RESET = (0x02), - SD_ILLEGAL_COMMAND = (0x04), - SD_COM_CRC_ERROR = (0x08), - SD_ERASE_SEQUENCE_ERROR = (0x10), - SD_ADDRESS_ERROR = (0x20), - SD_PARAMETER_ERROR = (0x40), - SD_RESPONSE_FAILURE = (0xFF), - -/** - * @brief Data response error - */ - SD_DATA_OK = (0x05), - SD_DATA_CRC_ERROR = (0x0B), - SD_DATA_WRITE_ERROR = (0x0D), - SD_DATA_OTHER_ERROR = (0xFF) -} SD_Error; - -/** - * @brief Card Specific Data: CSD Register - */ -typedef struct -{ - __IO uint8_t CSDStruct; /*!< CSD structure */ - __IO uint8_t SysSpecVersion; /*!< System specification version */ - __IO uint8_t Reserved1; /*!< Reserved */ - __IO uint8_t TAAC; /*!< Data read access-time 1 */ - __IO uint8_t NSAC; /*!< Data read access-time 2 in CLK cycles */ - __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ - __IO uint16_t CardComdClasses; /*!< Card command classes */ - __IO uint8_t RdBlockLen; /*!< Max. read data block length */ - __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ - __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */ - __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */ - __IO uint8_t DSRImpl; /*!< DSR implemented */ - __IO uint8_t Reserved2; /*!< Reserved */ - __IO uint32_t DeviceSize; /*!< Device Size */ - __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ - __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ - __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ - __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ - __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */ - __IO uint8_t EraseGrSize; /*!< Erase group size */ - __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */ - __IO uint8_t WrProtectGrSize; /*!< Write protect group size */ - __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */ - __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */ - __IO uint8_t WrSpeedFact; /*!< Write speed factor */ - __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */ - __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ - __IO uint8_t Reserved3; /*!< Reserded */ - __IO uint8_t ContentProtectAppli; /*!< Content protection application */ - __IO uint8_t FileFormatGrouop; /*!< File format group */ - __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ - __IO uint8_t PermWrProtect; /*!< Permanent write protection */ - __IO uint8_t TempWrProtect; /*!< Temporary write protection */ - __IO uint8_t FileFormat; /*!< File Format */ - __IO uint8_t ECC; /*!< ECC code */ - __IO uint8_t CSD_CRC; /*!< CSD CRC */ - __IO uint8_t Reserved4; /*!< always 1*/ -} SD_CSD; - -/** - * @brief Card Identification Data: CID Register - */ -typedef struct -{ - __IO uint8_t ManufacturerID; /*!< ManufacturerID */ - __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */ - __IO uint32_t ProdName1; /*!< Product Name part1 */ - __IO uint8_t ProdName2; /*!< Product Name part2*/ - __IO uint8_t ProdRev; /*!< Product Revision */ - __IO uint32_t ProdSN; /*!< Product Serial Number */ - __IO uint8_t Reserved1; /*!< Reserved1 */ - __IO uint16_t ManufactDate; /*!< Manufacturing Date */ - __IO uint8_t CID_CRC; /*!< CID CRC */ - __IO uint8_t Reserved2; /*!< always 1 */ -} SD_CID; - -/** - * @brief SD Card information - */ -typedef struct -{ - SD_CSD SD_csd; - SD_CID SD_cid; - uint32_t CardCapacity; /*!< Card Capacity */ - uint32_t CardBlockSize; /*!< Card Block Size */ -} SD_CardInfo; - -/** - * @} - */ - -/** @defgroup STM32_EVAL_SPI_SD_Exported_Constants - * @{ - */ - -/** - * @brief Block Size - */ -#define SD_BLOCK_SIZE 0x200 - -/** - * @brief Dummy byte - */ -#define SD_DUMMY_BYTE 0xFF - -/** - * @brief Start Data tokens: - * Tokens (necessary because at nop/idle (and CS active) only 0xff is - * on the data/command line) - */ -#define SD_START_DATA_SINGLE_BLOCK_READ 0xFE /*!< Data token start byte, Start Single Block Read */ -#define SD_START_DATA_MULTIPLE_BLOCK_READ 0xFE /*!< Data token start byte, Start Multiple Block Read */ -#define SD_START_DATA_SINGLE_BLOCK_WRITE 0xFE /*!< Data token start byte, Start Single Block Write */ -#define SD_START_DATA_MULTIPLE_BLOCK_WRITE 0xFD /*!< Data token start byte, Start Multiple Block Write */ -#define SD_STOP_DATA_MULTIPLE_BLOCK_WRITE 0xFD /*!< Data toke stop byte, Stop Multiple Block Write */ - -/** - * @brief SD detection on its memory slot - */ -#define SD_PRESENT ((uint8_t)0x01) -#define SD_NOT_PRESENT ((uint8_t)0x00) - - -/** - * @brief Commands: CMDxx = CMD-number | 0x40 - */ -#define SD_CMD_GO_IDLE_STATE 0 /*!< CMD0 = 0x40 */ -#define SD_CMD_SEND_OP_COND 1 /*!< CMD1 = 0x41 */ -#define SD_CMD_SEND_CSD 9 /*!< CMD9 = 0x49 */ -#define SD_CMD_SEND_CID 10 /*!< CMD10 = 0x4A */ -#define SD_CMD_STOP_TRANSMISSION 12 /*!< CMD12 = 0x4C */ -#define SD_CMD_SEND_STATUS 13 /*!< CMD13 = 0x4D */ -#define SD_CMD_SET_BLOCKLEN 16 /*!< CMD16 = 0x50 */ -#define SD_CMD_READ_SINGLE_BLOCK 17 /*!< CMD17 = 0x51 */ -#define SD_CMD_READ_MULT_BLOCK 18 /*!< CMD18 = 0x52 */ -#define SD_CMD_SET_BLOCK_COUNT 23 /*!< CMD23 = 0x57 */ -#define SD_CMD_WRITE_SINGLE_BLOCK 24 /*!< CMD24 = 0x58 */ -#define SD_CMD_WRITE_MULT_BLOCK 25 /*!< CMD25 = 0x59 */ -#define SD_CMD_PROG_CSD 27 /*!< CMD27 = 0x5B */ -#define SD_CMD_SET_WRITE_PROT 28 /*!< CMD28 = 0x5C */ -#define SD_CMD_CLR_WRITE_PROT 29 /*!< CMD29 = 0x5D */ -#define SD_CMD_SEND_WRITE_PROT 30 /*!< CMD30 = 0x5E */ -#define SD_CMD_SD_ERASE_GRP_START 32 /*!< CMD32 = 0x60 */ -#define SD_CMD_SD_ERASE_GRP_END 33 /*!< CMD33 = 0x61 */ -#define SD_CMD_UNTAG_SECTOR 34 /*!< CMD34 = 0x62 */ -#define SD_CMD_ERASE_GRP_START 35 /*!< CMD35 = 0x63 */ -#define SD_CMD_ERASE_GRP_END 36 /*!< CMD36 = 0x64 */ -#define SD_CMD_UNTAG_ERASE_GROUP 37 /*!< CMD37 = 0x65 */ -#define SD_CMD_ERASE 38 /*!< CMD38 = 0x66 */ - -/** - * @} - */ - -/** @defgroup STM32_EVAL_SPI_SD_Exported_Macros - * @{ - */ -/** - * @brief Select SD Card: ChipSelect pin low - */ -#define SD_CS_LOW() GPIO_ResetBits(SD_CS_GPIO_PORT, SD_CS_PIN) -/** - * @brief Deselect SD Card: ChipSelect pin high - */ -#define SD_CS_HIGH() GPIO_SetBits(SD_CS_GPIO_PORT, SD_CS_PIN) -/** - * @} - */ - -/** @defgroup STM32_EVAL_SPI_SD_Exported_Functions - * @{ - */ -void SD_DeInit(void); -SD_Error SD_Init(void); -uint8_t SD_Detect(void); -SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo); -SD_Error SD_ReadBlock(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize); -SD_Error SD_ReadMultiBlocks(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks); -SD_Error SD_WriteBlock(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize); -SD_Error SD_WriteMultiBlocks(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks); -SD_Error SD_GetCSDRegister(SD_CSD* SD_csd); -SD_Error SD_GetCIDRegister(SD_CID* SD_cid); - -void SD_SendCmd(uint8_t Cmd, uint32_t Arg, uint8_t Crc); -SD_Error SD_GetResponse(uint8_t Response); -uint8_t SD_GetDataResponse(void); -SD_Error SD_GoIdleState(void); -uint16_t SD_GetStatus(void); - -uint8_t SD_WriteByte(uint8_t byte); -uint8_t SD_ReadByte(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32_EVAL_SPI_SD_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Release_Notes.html b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Release_Notes.html deleted file mode 100644 index 8b43b7596..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Release_Notes.html +++ /dev/null @@ -1,328 +0,0 @@ - - - - - - - - - - - - - - - - Release Notes for STM32 Standard Peripherals Library Utilities - - - - - - - - - - -
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Back to Release page

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Release -Notes for STM32 Standard Peripherals Library Utilities (Utilities)

-

Copyright -2011 STMicroelectronics

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-

Contents

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    -
  1. STM32 Standard Peripherals Library Utilities -update History
    2. -
  2. License
    3. -
- - -

STM32 -Standard -Peripherals Library Utilities update History


V4.5.0 / 07-March-2011

-

Main -Changes

- -
  • stm32_eval_sdio_sd.c\.h: driver improvement
    • SD Clock increased to 24MHz to improve the data transfer performance.
    • Add -new functions to check the SDIO peripheral and SD Card status at any -time: SD_WaitReadOperation(), SD_WaitWriteOperation(). The -software sequence is little bit changed but without any impact on -driver API. For more details, refer to the stm32_eval_sdio_sd.c -driver description.
    • Add -new structure containing the SD Status register parameters. This -structure is called by the -         - SD_SendSDStatus() function.
    • Transfers mode updated
      • Read/Write Block using Polling and DMA modes
      • Read/Write Multi Blocks using DMA mode only
      • Interrupt mode removed
    • Data transfer functions are managing only fixed Block size (512-byte) 
  • STM32100B-EVAL
    • stm32100b_eval_cec.c: fix some strict ANSI-C errors
  • STM32100E-EVAL
    • stm32100e_eval_cec.c: fix some strict ANSI-C errors
-

V4.4.0 / 31-December-2010

-

Main -Changes

- -
    -
  • Add new directory for STM32L152-EVAL board containing the following files:
    • -
      -
    • stm32l152_eval.h/.c, stm32l152_eval_lcd.h/.c, stm32l152_eval_glass_lcd.h/.c, stm32l152_eval_i2c_ee.h/.c
      • -
    -
  • Add support for the STM32100E-EVAL Rev B: SPI FLASH CS pin "sFLASH_CS_PIN" changed from PB.02 to PE.06.
    • -
  • stm32100e_eval_lcd.h/.c: Add support for "LCD_ILI9325" LCD controller.
    • -
  • stm32100e_eval_fsmc_onenand.h/.c driver updated to correct asynchronous and synchronous read operations procedures.
    -
    • -
- -

4.3.0 -- 10/15/2010

-
    -
  1. General
    2. -
- -
    - - - - -
  • I2C EEPROM, Temperature Sensor and IOE Expander drivers updated to use the DMA for read/write transfer and add more robustness
    • -
  • SD Card (SDIO) driver updated to add more robustness
  • SPI Flash and SD Card (SPI) drivers: SPI MISO pin configuration changed to Input Floating 
    • -
- - - -
    -
  1. Utilities
    2. -
- - - - - -
    -
  • Add new directory for STM32100E-EVAL board containing the following files:
    • -
      -
    • stm32100e_eval.h/.c, -stm32100e_eval_lcd.h/.c, stm32100e_eval_cec.h/.c, -stm32100e_eval_fsmc_onenand.h/.c, stm32100e_eval_fsmc_sram.h/.c, -stm32100e_eval_ioe.h/.c
      -
      • -
    -
  • Common
    • stm32_eval_sdio_sd.c: -Update the DMA End of Transfer Check loop inside the SD_ReadBlock(), -SD_WriteBlock(), SD_ReadMultiBlocks() and SD_Write MultiBlocks().
    -
    • stm32_eval_i2c_ee.c/.h
      -
    -
      -
      • Enhanced sEE_WaitEepromStandbyState() function for more robustness.
      • Enhanced Read and Write operations to manage I2C limitations.
      • Add Timeout management with user callback implementation which allows recovering from I2C bus errors.
      • Add -critical sections user callbacks allowing to disable then enable -interrupts when I2C operation require to be not interrupted.
    -
    • stm32_eval_i2c_tsensor.c/.h
      -
    -
      -
      • Enhanced I2C communication functions by using DMA for registers Read and Write operations.
      • Add Timeout management with user callback implementation which allows recovering from I2C bus errors.
    -
  • STM32100B_EVAL
    • stm32100b_eval.h: Add LM75 DMA defines.
    -
    • stm32100b_eval_lcd.c: Change "SPI_FLASH" by "sFLASH" in LCD_DrawBMP() function.
    -
  • STM3210B_EVAL
    • stm3210b_eval.h: Add LM75 DMA defines.
    -
    • stm3210b_eval_lcd.c: Change "SPI_FLASH" by "sFLASH" in LCD_DrawBMP() function.
    -
  • STM3210C_EVAL
    • stm3210c_eval.h: Add EEPROM driver Timeout define.
    -
    • stm3210c_eval_lcd.c: Change "SPI_FLASH" by "sFLASH" in LCD_DrawBMP() function.
    • stm3210c_eval_i2c_ioe.c
      • Enhanced I2C communication functions by using DMA for registers Read and Write operations.
      • Add Timeout management with user callback implementation which allows recovering from I2C bus errors.
      • change IOE_I2C_SPEED from "400000" to "300000".
    -
  • STM3210E_EVAL
    • stm3210e_eval.c: change "void SD_WaitForDMAEndOfTransfer(void)" to "uint32_t SD_DMAEndOfTransferStatus(void)".
    -
    • stm3210e_eval.h: Add LM75 DMA defines.
    -
    • stm3210e_eval_fsmc_nand.h: remove "NAND_CMD_AREA_TRUE1" define.
    -
    • stm3210e_eval_fsmc_nand.c: Update FSMC timing in NAND_Init() function to be aligned with AN2784 application note.
    -
    • stm3210e_eval_fsmc_nor.c
      • NOR_Init() function: add FSMC_AsynchronousWait field to FSMC_NORSRAMInitStructure 
    -
    • stm3210e_eval_fsmc_sram.c
      -
    -
      -
      • Update FSMC timing in SRAM_Init() function to be aligned with AN2784 application note.
        -
      -
      • SRAM_Init() function: add FSMC_AsynchronousWait field to FSMC_NORSRAMInitStructure 
      -
    -
    • stm3210e_eval_lcd.c
      • LCD_FSMCConfig() function: add FSMC_AsynchronousWait field to FSMC_NORSRAMInitStructure 
-
    - - -
- -

4.2.0 -- 04/16/2010

-
    -
  1. General
    2. -
- -
    - - -
  • I2C EEPROM driver -update to use the DMA to -perform data transfer to/from EEPROM memory.
    • - - -
- -
    -
  1. Utilities
    2. -
-
    -
  • STM32_EVAL
    • -
-
    -
      -
    • stm32_eval_i2c_ee.c: -updated to use the DMA to perform data transfer to/from -EEPROM memory. For more details, refer to the description provided -within this file.
      • -
    • stm3210c_eval.c: add low level -functions to configure the DMA (needed for I2C EEPROM driver)
      -
      • -
    • stm3210c_eval_ioe.c: add a delay -in IOE_TS_GetState() function to wait till the end of ADC -conversion
      • -
    • stm3210e_eval_fsmc_nor.c: add PD6 pin configuration in -NOR_Init() function
      • -
    • stm3210b_eval_lcd.c: remove the -second ";" from "static void PutPixel(int16_t x, int16_t y);;" 
      • -
    -
-

4.1.0 -- 03/01/2010

-
    -
  1. General
    2. -
-
    -
  • Add support -for STM32 Low-density Value line (STM32F100x4/6) and -Medium-density Value line (STM32F100x8/B) devices.
    • -
  • Add support for the -STMicroelectronics STM32100B-EVAL evaluation board.
    • -
-
    -
  1. Utilities
    2. -
-
    -
  • STM32_EVAL
    • -
-
    -
      -
    • Add new directory -"Common" containing a common drivers for all STM32 evaluation boards: -fonts.h/.c, stm32_eval_i2c_ee.h/.c, stm32_eval_spi_flash.h/.c, - stm32_eval_i2c_tsensor.h/.c, - stm32_eval_spi_sd.h/.c -and stm32_eval_sdio_sd.h/.c
      • -
    • Add new driver for the -STM32100B-EVAL managing Leds, push button and COM ports.
      • -
    • New HDMI CEC High level -driver.
      -
      • -
    • For all LCD drivers new fonts has -been added.
      • -
    • New FSMC memories -drivers for STM3210E-EVAL board: stm3210e_eval_fsmc_sram.h/.c, stm3210e_eval_fsmc_nor.h/.c -and stm3210e_eval_fsmc_nand.h/.c.
      • -
    -
-

License

-

The -enclosed firmware and all the related documentation are not covered by -a License Agreement, if you need such License you can contact your -local STMicroelectronics office.

- - THE -PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO -SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR -ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY -CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY -CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH -THEIR PRODUCTS. - -
-
-

For -complete documentation on STMicroelectronics Microcontrollers visit www.st.com

-
-

-
-
-

 

-
- - \ No newline at end of file diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval.c deleted file mode 100644 index a66b88804..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval.c +++ /dev/null @@ -1,624 +0,0 @@ -/** - ****************************************************************************** - * @file stm32100b_eval.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file provides - * - set of firmware functions to manage Leds, push-button and COM ports - * - low level initialization functions for SD card (on SPI), SPI serial - * flash (sFLASH) and temperature sensor (LM75) - * available on STM32100B-EVAL evaluation board from STMicroelectronics. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32100b_eval.h" -#include "stm32f10x_spi.h" -#include "stm32f10x_i2c.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32100B_EVAL - * @{ - */ - -/** @defgroup STM32100B_EVAL_LOW_LEVEL - * @brief This file provides firmware functions to manage Leds, push-buttons, - * COM ports, SD card on SPI, serial flash (sFLASH) and temperature - * sensor (LM75) available on STM32100B-EVAL evaluation board from - * STMicroelectronics. - * @{ - */ - -/** @defgroup STM32100B_EVAL_LOW_LEVEL_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32100B_EVAL_LOW_LEVEL_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32100B_EVAL_LOW_LEVEL_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32100B_EVAL_LOW_LEVEL_Private_Variables - * @{ - */ -GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT, - LED4_GPIO_PORT}; -const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN, - LED4_PIN}; -const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK, - LED4_GPIO_CLK}; - -GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT, - KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT, - LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT, - DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT}; - -const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN, - KEY_BUTTON_PIN, RIGHT_BUTTON_PIN, - LEFT_BUTTON_PIN, UP_BUTTON_PIN, - DOWN_BUTTON_PIN, SEL_BUTTON_PIN}; - -const uint32_t BUTTON_CLK[BUTTONn] = {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK, - KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK, - LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK, - DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK}; - -const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {WAKEUP_BUTTON_EXTI_LINE, - TAMPER_BUTTON_EXTI_LINE, - KEY_BUTTON_EXTI_LINE, - RIGHT_BUTTON_EXTI_LINE, - LEFT_BUTTON_EXTI_LINE, - UP_BUTTON_EXTI_LINE, - DOWN_BUTTON_EXTI_LINE, - SEL_BUTTON_EXTI_LINE}; - -const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PORT_SOURCE, - TAMPER_BUTTON_EXTI_PORT_SOURCE, - KEY_BUTTON_EXTI_PORT_SOURCE, - RIGHT_BUTTON_EXTI_PORT_SOURCE, - LEFT_BUTTON_EXTI_PORT_SOURCE, - UP_BUTTON_EXTI_PORT_SOURCE, - DOWN_BUTTON_EXTI_PORT_SOURCE, - SEL_BUTTON_EXTI_PORT_SOURCE}; - -const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PIN_SOURCE, - TAMPER_BUTTON_EXTI_PIN_SOURCE, - KEY_BUTTON_EXTI_PIN_SOURCE, - RIGHT_BUTTON_EXTI_PIN_SOURCE, - LEFT_BUTTON_EXTI_PIN_SOURCE, - UP_BUTTON_EXTI_PIN_SOURCE, - DOWN_BUTTON_EXTI_PIN_SOURCE, - SEL_BUTTON_EXTI_PIN_SOURCE}; - -const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn, - KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn, - LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn, - DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn}; - -USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2}; - -GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT}; - -GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT}; - -const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK}; - -const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK}; - -const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK}; - -const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN}; - -const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN}; - -/** - * @} - */ - - -/** @defgroup STM32100B_EVAL_LOW_LEVEL_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - - -/** @defgroup STM32100B_EVAL_LOW_LEVEL_Private_Functions - * @{ - */ - -/** - * @brief Configures LED GPIO. - * @param Led: Specifies the Led to be configured. - * This parameter can be one of following parameters: - * @arg LED1 - * @arg LED2 - * @arg LED3 - * @arg LED4 - * @retval None - */ -void STM_EVAL_LEDInit(Led_TypeDef Led) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable the GPIO_LED Clock */ - RCC_APB2PeriphClockCmd(GPIO_CLK[Led], ENABLE); - - /* Configure the GPIO_LED pin */ - GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led]; - - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure); -} - -/** - * @brief Turns selected LED On. - * @param Led: Specifies the Led to be set on. - * This parameter can be one of following parameters: - * @arg LED1 - * @arg LED2 - * @arg LED3 - * @arg LED4 - * @retval None - */ -void STM_EVAL_LEDOn(Led_TypeDef Led) -{ - GPIO_PORT[Led]->BSRR = GPIO_PIN[Led]; -} - -/** - * @brief Turns selected LED Off. - * @param Led: Specifies the Led to be set off. - * This parameter can be one of following parameters: - * @arg LED1 - * @arg LED2 - * @arg LED3 - * @arg LED4 - * @retval None - */ -void STM_EVAL_LEDOff(Led_TypeDef Led) -{ - GPIO_PORT[Led]->BRR = GPIO_PIN[Led]; -} - -/** - * @brief Toggles the selected LED. - * @param Led: Specifies the Led to be toggled. - * This parameter can be one of following parameters: - * @arg LED1 - * @arg LED2 - * @arg LED3 - * @arg LED4 - * @retval None - */ -void STM_EVAL_LEDToggle(Led_TypeDef Led) -{ - GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led]; -} - -/** - * @brief Configures Button GPIO and EXTI Line. - * @param Button: Specifies the Button to be configured. - * This parameter can be one of following parameters: - * @arg BUTTON_WAKEUP: Wakeup Push Button - * @arg BUTTON_TAMPER: Tamper Push Button - * @arg BUTTON_KEY: Key Push Button - * @arg BUTTON_RIGHT: Joystick Right Push Button - * @arg BUTTON_LEFT: Joystick Left Push Button - * @arg BUTTON_UP: Joystick Up Push Button - * @arg BUTTON_DOWN: Joystick Down Push Button - * @arg BUTTON_SEL: Joystick Sel Push Button - * @param Button_Mode: Specifies Button mode. - * This parameter can be one of following parameters: - * @arg BUTTON_MODE_GPIO: Button will be used as simple IO - * @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt - * generation capability - * @retval None - */ -void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode) -{ - GPIO_InitTypeDef GPIO_InitStructure; - EXTI_InitTypeDef EXTI_InitStructure; - NVIC_InitTypeDef NVIC_InitStructure; - - /* Enable the BUTTON Clock */ - RCC_APB2PeriphClockCmd(BUTTON_CLK[Button] | RCC_APB2Periph_AFIO, ENABLE); - - /* Configure Button pin as input floating */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button]; - GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure); - - - if (Button_Mode == BUTTON_MODE_EXTI) - { - /* Connect Button EXTI Line to Button GPIO Pin */ - GPIO_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]); - - /* Configure Button EXTI line */ - EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button]; - EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; - - if(Button != BUTTON_WAKEUP) - { - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; - } - else - { - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; - } - EXTI_InitStructure.EXTI_LineCmd = ENABLE; - EXTI_Init(&EXTI_InitStructure); - - /* Enable and set Button EXTI Interrupt to the lowest priority */ - NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button]; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - - NVIC_Init(&NVIC_InitStructure); - } -} - -/** - * @brief Returns the selected Button state. - * @param Button: Specifies the Button to be checked. - * This parameter can be one of following parameters: - * @arg BUTTON_WAKEUP: Wakeup Push Button - * @arg BUTTON_TAMPER: Tamper Push Button - * @arg BUTTON_KEY: Key Push Button - * @arg BUTTON_RIGHT: Joystick Right Push Button - * @arg BUTTON_LEFT: Joystick Left Push Button - * @arg BUTTON_UP: Joystick Up Push Button - * @arg BUTTON_DOWN: Joystick Down Push Button - * @arg BUTTON_SEL: Joystick Sel Push Button - * @retval The Button GPIO pin value. - */ -uint32_t STM_EVAL_PBGetState(Button_TypeDef Button) -{ - return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]); -} - - -/** - * @brief Configures COM port. - * @param COM: Specifies the COM port to be configured. - * This parameter can be one of following parameters: - * @arg COM1 - * @arg COM2 - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that - * contains the configuration information for the specified USART peripheral. - * @retval None - */ -void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable GPIO clock */ - RCC_APB2PeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM] | RCC_APB2Periph_AFIO, ENABLE); - - - /* Enable UART clock */ - if (COM == COM1) - { - RCC_APB2PeriphClockCmd(COM_USART_CLK[COM], ENABLE); - } - else - { - /* Enable the USART2 Pins Software Remapping */ - GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE); - RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE); - } - - /* Configure USART Tx as alternate function push-pull */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM]; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure); - - /* Configure USART Rx as input floating */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM]; - GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure); - - /* USART configuration */ - USART_Init(COM_USART[COM], USART_InitStruct); - - /* Enable USART */ - USART_Cmd(COM_USART[COM], ENABLE); -} - -/** - * @brief DeInitializes the SD/SD communication. - * @param None - * @retval None - */ -void SD_LowLevel_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - SPI_Cmd(SD_SPI, DISABLE); /*!< SD_SPI disable */ - SPI_I2S_DeInit(SD_SPI); /*!< DeInitializes the SD_SPI */ - - /*!< SD_SPI Periph clock disable */ - RCC_APB2PeriphClockCmd(SD_SPI_CLK, DISABLE); - - /*!< Configure SD_SPI pins: SCK */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI pins: MISO */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN; - GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI pins: MOSI */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN; - GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */ - GPIO_InitStructure.GPIO_Pin = SD_CS_PIN; - GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */ - GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN; - GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @brief Initializes the SD_SPI and CS pins. - * @param None - * @retval None - */ -void SD_LowLevel_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - SPI_InitTypeDef SPI_InitStructure; - - /*!< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO - and SD_SPI_SCK_GPIO Periph clock enable */ - RCC_APB2PeriphClockCmd(SD_CS_GPIO_CLK | SD_SPI_MOSI_GPIO_CLK | SD_SPI_MISO_GPIO_CLK | - SD_SPI_SCK_GPIO_CLK | SD_DETECT_GPIO_CLK, ENABLE); - - /*!< SD_SPI Periph clock enable */ - RCC_APB2PeriphClockCmd(SD_SPI_CLK, ENABLE); - - - /*!< Configure SD_SPI pins: SCK */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI pins: MOSI */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN; - GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI pins: MISO */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */ - GPIO_InitStructure.GPIO_Pin = SD_CS_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */ - GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure); - - /*!< SD_SPI Config */ - SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; - SPI_InitStructure.SPI_Mode = SPI_Mode_Master; - SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; - SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; - SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; - SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; - SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - - SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; - SPI_InitStructure.SPI_CRCPolynomial = 7; - SPI_Init(SD_SPI, &SPI_InitStructure); - - SPI_Cmd(SD_SPI, ENABLE); /*!< SD_SPI enable */ -} - -/** - * @brief DeInitializes the peripherals used by the SPI FLASH driver. - * @param None - * @retval None - */ -void sFLASH_LowLevel_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< Disable the sFLASH_SPI */ - SPI_Cmd(sFLASH_SPI, DISABLE); - - /*!< DeInitializes the sFLASH_SPI */ - SPI_I2S_DeInit(sFLASH_SPI); - - /*!< sFLASH_SPI Periph clock disable */ - RCC_APB2PeriphClockCmd(sFLASH_SPI_CLK, DISABLE); - - /*!< Configure sFLASH_SPI pins: SCK */ - GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sFLASH_SPI pins: MISO */ - GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN; - GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sFLASH_SPI pins: MOSI */ - GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN; - GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin */ - GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN; - GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @brief Initializes the peripherals used by the SPI FLASH driver. - * @param None - * @retval None - */ -void sFLASH_LowLevel_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO - and sFLASH_SPI_SCK_GPIO Periph clock enable */ - RCC_APB2PeriphClockCmd(sFLASH_CS_GPIO_CLK | sFLASH_SPI_MOSI_GPIO_CLK | sFLASH_SPI_MISO_GPIO_CLK | - sFLASH_SPI_SCK_GPIO_CLK, ENABLE); - - /*!< sFLASH_SPI Periph clock enable */ - RCC_APB2PeriphClockCmd(sFLASH_SPI_CLK, ENABLE); - - /*!< Configure sFLASH_SPI pins: SCK */ - GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sFLASH_SPI pins: MOSI */ - GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN; - GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sFLASH_SPI pins: MISO */ - GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin */ - GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @brief DeInitializes the LM75_I2C. - * @param None - * @retval None - */ -void LM75_LowLevel_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< Disable LM75_I2C */ - I2C_Cmd(LM75_I2C, DISABLE); - /*!< DeInitializes the LM75_I2C */ - I2C_DeInit(LM75_I2C); - - /*!< LM75_I2C Periph clock disable */ - RCC_APB1PeriphClockCmd(LM75_I2C_CLK, DISABLE); - - /*!< Configure LM75_I2C pins: SCL */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure LM75_I2C pins: SDA */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN; - GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure LM75_I2C pin: SMBUS ALERT */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN; - GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @brief Initializes the LM75_I2C.. - * @param None - * @retval None - */ -void LM75_LowLevel_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< LM75_I2C Periph clock enable */ - RCC_APB1PeriphClockCmd(LM75_I2C_CLK, ENABLE); - - /*!< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK - and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable */ - RCC_APB2PeriphClockCmd(LM75_I2C_SCL_GPIO_CLK | LM75_I2C_SDA_GPIO_CLK | - LM75_I2C_SMBUSALERT_GPIO_CLK, ENABLE); - - /*!< Configure LM75_I2C pins: SCL */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD; - GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure LM75_I2C pins: SDA */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN; - GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure LM75_I2C pin: SMBUS ALERT */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval.h deleted file mode 100644 index 4ce0f0048..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval.h +++ /dev/null @@ -1,341 +0,0 @@ -/** - ****************************************************************************** - * @file stm32100b_eval.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains definitions for STM32100B_EVAL's Leds, push-buttons - * COM ports, SD Card on SPI, sFLASH on SPI and Temperature Sensor LM75 on I2C - * hardware resources. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32100B_EVAL_H -#define __STM32100B_EVAL_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32_eval.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32100B_EVAL - * @{ - */ - -/** @addtogroup STM32100B_EVAL_LOW_LEVEL - * @{ - */ - -/** @defgroup STM32100B_EVAL_LOW_LEVEL_Exported_Types - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32100B_EVAL_LOW_LEVEL_Exported_Constants - * @{ - */ -/** @addtogroup STM32100B_EVAL_LOW_LEVEL_LED - * @{ - */ -#define LEDn 4 -#define LED1_PIN GPIO_Pin_6 -#define LED1_GPIO_PORT GPIOC -#define LED1_GPIO_CLK RCC_APB2Periph_GPIOC - -#define LED2_PIN GPIO_Pin_7 -#define LED2_GPIO_PORT GPIOC -#define LED2_GPIO_CLK RCC_APB2Periph_GPIOC - -#define LED3_PIN GPIO_Pin_8 -#define LED3_GPIO_PORT GPIOC -#define LED3_GPIO_CLK RCC_APB2Periph_GPIOC - -#define LED4_PIN GPIO_Pin_9 -#define LED4_GPIO_PORT GPIOC -#define LED4_GPIO_CLK RCC_APB2Periph_GPIOC - -/** - * @} - */ - -/** @addtogroup STM32100B_EVAL_LOW_LEVEL_BUTTON - * @{ - */ -#define BUTTONn 8 - -/** - * @brief Wakeup push-button - */ -#define WAKEUP_BUTTON_PIN GPIO_Pin_0 -#define WAKEUP_BUTTON_GPIO_PORT GPIOA -#define WAKEUP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOA -#define WAKEUP_BUTTON_EXTI_LINE EXTI_Line0 -#define WAKEUP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOA -#define WAKEUP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0 -#define WAKEUP_BUTTON_EXTI_IRQn EXTI0_IRQn -/** - * @brief Tamper push-button - */ -#define TAMPER_BUTTON_PIN GPIO_Pin_13 -#define TAMPER_BUTTON_GPIO_PORT GPIOC -#define TAMPER_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOC -#define TAMPER_BUTTON_EXTI_LINE EXTI_Line13 -#define TAMPER_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOC -#define TAMPER_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13 -#define TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn -/** - * @brief Key push-button - */ -#define KEY_BUTTON_PIN GPIO_Pin_9 -#define KEY_BUTTON_GPIO_PORT GPIOB -#define KEY_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOB -#define KEY_BUTTON_EXTI_LINE EXTI_Line9 -#define KEY_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOB -#define KEY_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource9 -#define KEY_BUTTON_EXTI_IRQn EXTI9_5_IRQn -/** - * @brief Joystick Right push-button - */ -#define RIGHT_BUTTON_PIN GPIO_Pin_1 -#define RIGHT_BUTTON_GPIO_PORT GPIOE -#define RIGHT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOE -#define RIGHT_BUTTON_EXTI_LINE EXTI_Line1 -#define RIGHT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOE -#define RIGHT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource1 -#define RIGHT_BUTTON_EXTI_IRQn EXTI1_IRQn -/** - * @brief Joystick Left push-button - */ -#define LEFT_BUTTON_PIN GPIO_Pin_0 -#define LEFT_BUTTON_GPIO_PORT GPIOE -#define LEFT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOE -#define LEFT_BUTTON_EXTI_LINE EXTI_Line0 -#define LEFT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOE -#define LEFT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0 -#define LEFT_BUTTON_EXTI_IRQn EXTI0_IRQn -/** - * @brief Joystick Up push-button - */ -#define UP_BUTTON_PIN GPIO_Pin_8 -#define UP_BUTTON_GPIO_PORT GPIOD -#define UP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD -#define UP_BUTTON_EXTI_LINE EXTI_Line8 -#define UP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD -#define UP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource8 -#define UP_BUTTON_EXTI_IRQn EXTI9_5_IRQn -/** - * @brief Joystick Down push-button - */ -#define DOWN_BUTTON_PIN GPIO_Pin_14 -#define DOWN_BUTTON_GPIO_PORT GPIOD -#define DOWN_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD -#define DOWN_BUTTON_EXTI_LINE EXTI_Line14 -#define DOWN_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD -#define DOWN_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource14 -#define DOWN_BUTTON_EXTI_IRQn EXTI15_10_IRQn -/** - * @brief Joystick Sel push-button - */ -#define SEL_BUTTON_PIN GPIO_Pin_12 -#define SEL_BUTTON_GPIO_PORT GPIOD -#define SEL_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD -#define SEL_BUTTON_EXTI_LINE EXTI_Line12 -#define SEL_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD -#define SEL_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource12 -#define SEL_BUTTON_EXTI_IRQn EXTI15_10_IRQn -/** - * @} - */ - -/** @addtogroup STM32100B_EVAL_LOW_LEVEL_COM - * @{ - */ -#define COMn 2 - -/** - * @brief Definition for COM port1, connected to USART1 - */ -#define EVAL_COM1 USART1 -#define EVAL_COM1_CLK RCC_APB2Periph_USART1 -#define EVAL_COM1_TX_PIN GPIO_Pin_9 -#define EVAL_COM1_TX_GPIO_PORT GPIOA -#define EVAL_COM1_TX_GPIO_CLK RCC_APB2Periph_GPIOA -#define EVAL_COM1_RX_PIN GPIO_Pin_10 -#define EVAL_COM1_RX_GPIO_PORT GPIOA -#define EVAL_COM1_RX_GPIO_CLK RCC_APB2Periph_GPIOA -#define EVAL_COM1_IRQn USART1_IRQn - -/** - * @brief Definition for COM port2, connected to USART2 (USART2 pins remapped on GPIOD) - */ -#define EVAL_COM2 USART2 -#define EVAL_COM2_CLK RCC_APB1Periph_USART2 -#define EVAL_COM2_TX_PIN GPIO_Pin_5 -#define EVAL_COM2_TX_GPIO_PORT GPIOD -#define EVAL_COM2_TX_GPIO_CLK RCC_APB2Periph_GPIOD -#define EVAL_COM2_RX_PIN GPIO_Pin_6 -#define EVAL_COM2_RX_GPIO_PORT GPIOD -#define EVAL_COM2_RX_GPIO_CLK RCC_APB2Periph_GPIOD -#define EVAL_COM2_IRQn USART2_IRQn - -/** - * @} - */ - -/** @addtogroup STM32100B_EVAL_LOW_LEVEL_SD_SPI - * @{ - */ -/** - * @brief SD SPI Interface pins - */ -#define SD_SPI SPI1 -#define SD_SPI_CLK RCC_APB2Periph_SPI1 -#define SD_SPI_SCK_PIN GPIO_Pin_5 /* PA.05 */ -#define SD_SPI_SCK_GPIO_PORT GPIOA /* GPIOA */ -#define SD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOA -#define SD_SPI_MISO_PIN GPIO_Pin_6 /* PA.06 */ -#define SD_SPI_MISO_GPIO_PORT GPIOA /* GPIOA */ -#define SD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOA -#define SD_SPI_MOSI_PIN GPIO_Pin_7 /* PA.07 */ -#define SD_SPI_MOSI_GPIO_PORT GPIOA /* GPIOA */ -#define SD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOA -#define SD_CS_PIN GPIO_Pin_12 /* PC.12 */ -#define SD_CS_GPIO_PORT GPIOC /* GPIOC */ -#define SD_CS_GPIO_CLK RCC_APB2Periph_GPIOC -#define SD_DETECT_PIN GPIO_Pin_7 /* PE.07 */ -#define SD_DETECT_GPIO_PORT GPIOE /* GPIOE */ -#define SD_DETECT_GPIO_CLK RCC_APB2Periph_GPIOE - -/** - * @} - */ - -/** @addtogroup STM32100B_EVAL_LOW_LEVEL_M25P_FLASH_SPI - * @{ - */ -/** - * @brief M25P FLASH SPI Interface pins - */ -#define sFLASH_SPI SPI1 -#define sFLASH_SPI_CLK RCC_APB2Periph_SPI1 -#define sFLASH_SPI_SCK_PIN GPIO_Pin_5 /* PA.05 */ -#define sFLASH_SPI_SCK_GPIO_PORT GPIOA /* GPIOA */ -#define sFLASH_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOA -#define sFLASH_SPI_MISO_PIN GPIO_Pin_6 /* PA.06 */ -#define sFLASH_SPI_MISO_GPIO_PORT GPIOA /* GPIOA */ -#define sFLASH_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOA -#define sFLASH_SPI_MOSI_PIN GPIO_Pin_7 /* PA.07 */ -#define sFLASH_SPI_MOSI_GPIO_PORT GPIOA /* GPIOA */ -#define sFLASH_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOA -#define sFLASH_CS_PIN GPIO_Pin_9 /* PD.09 */ -#define sFLASH_CS_GPIO_PORT GPIOD /* GPIOD */ -#define sFLASH_CS_GPIO_CLK RCC_APB2Periph_GPIOD - -/** - * @} - */ - -/** @addtogroup STM32100B_EVAL_LOW_LEVEL_TSENSOR_I2C - * @{ - */ -/** - * @brief LM75 Temperature Sensor I2C Interface pins - */ -#define LM75_I2C I2C1 -#define LM75_I2C_CLK RCC_APB1Periph_I2C1 -#define LM75_I2C_SCL_PIN GPIO_Pin_6 /* PB.06 */ -#define LM75_I2C_SCL_GPIO_PORT GPIOB /* GPIOB */ -#define LM75_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB -#define LM75_I2C_SDA_PIN GPIO_Pin_7 /* PB.07 */ -#define LM75_I2C_SDA_GPIO_PORT GPIOB /* GPIOB */ -#define LM75_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB -#define LM75_I2C_SMBUSALERT_PIN GPIO_Pin_5 /* PB.05 */ -#define LM75_I2C_SMBUSALERT_GPIO_PORT GPIOB /* GPIOB */ -#define LM75_I2C_SMBUSALERT_GPIO_CLK RCC_APB2Periph_GPIOB -#define LM75_I2C_DR ((uint32_t)0x40005410) - -#define LM75_DMA_CLK RCC_AHBPeriph_DMA1 -#define LM75_DMA_TX_CHANNEL DMA1_Channel6 -#define LM75_DMA_RX_CHANNEL DMA1_Channel7 -#define LM75_DMA_TX_TCFLAG DMA1_FLAG_TC6 -#define LM75_DMA_RX_TCFLAG DMA1_FLAG_TC7 -/** - * @} - */ -/** - * @} - */ - -/** @defgroup STM32100B_EVAL_LOW_LEVEL_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32100B_EVAL_LOW_LEVEL_Exported_Functions - * @{ - */ -void STM_EVAL_LEDInit(Led_TypeDef Led); -void STM_EVAL_LEDOn(Led_TypeDef Led); -void STM_EVAL_LEDOff(Led_TypeDef Led); -void STM_EVAL_LEDToggle(Led_TypeDef Led); -void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode); -uint32_t STM_EVAL_PBGetState(Button_TypeDef Button); -void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct); -void SD_LowLevel_DeInit(void); -void SD_LowLevel_Init(void); -void sFLASH_LowLevel_DeInit(void); -void sFLASH_LowLevel_Init(void); -void LM75_LowLevel_DeInit(void); -void LM75_LowLevel_Init(void); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32100B_EVAL_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_cec.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_cec.c deleted file mode 100644 index eefc578df..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_cec.c +++ /dev/null @@ -1,1722 +0,0 @@ -/** - ****************************************************************************** - * @file stm32100b_eval_cec.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file provides all the STM32100B-EVAL HDMI-CEC firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32100b_eval_cec.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32100B_EVAL - * @{ - */ - -/** @defgroup STM32100B_EVAL_CEC - * @brief This file includes the CEC Stack driver for HDMI-CEC Module - * of STM32100B-EVAL board. - * @{ - */ - -/** @defgroup STM32100B_EVAL_CEC_Private_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup STM32100B_EVAL_CEC_Private_Defines - * @{ - */ - - -/** - * @} - */ - -/** @defgroup STM32100B_EVAL_CEC_Private_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32100B_EVAL_CEC_Private_Variables - * @{ - */ - -__IO uint32_t ReceivedFrame = 0; -__IO uint32_t SendFrame = 0; -__IO uint32_t BufferCount = 0, TxCounter = 0, RxCounter = 0; -__IO uint8_t BufferPointer[15]; -__IO uint32_t ReceiveStatus = 0; -__IO uint32_t SendStatus = 0; -__IO uint8_t TransErrorCode = 0; -__IO uint8_t RecepErrorCode = 0; -__IO uint8_t MyLogicalAddress = 0; -__IO uint16_t MyPhysicalAddress = 0; -__IO uint8_t DeviceType = 0; -#ifdef HDMI_CEC_USE_DDC -__IO uint8_t pBuffer[256]; -__IO uint16_t NumByteToRead = 255; -#endif -__IO uint8_t CECDevicesNumber = 0; - -HDMI_CEC_Message HDMI_CEC_TX_MessageStructPrivate; -HDMI_CEC_Message HDMI_CEC_RX_MessageStructPrivate; -HDMI_CEC_Message HDMI_CEC_TX_MessageStructure; - -__IO uint8_t FeatureOpcode = 0; -__IO uint8_t AbortReason = 0; -__IO uint8_t DeviceCount = 0; - -HDMI_CEC_Map HDMI_CEC_MapStruct; -HDMI_CEC_Map HDMI_CEC_DeviceMap[14]; - -/* CEC follower addresses */ -uint8_t* HDMI_CEC_Follower_String[13][2] = - { - {(uint8_t *)" TV ", (uint8_t *)"0"}, - {(uint8_t *)"Recording Device 1 ", (uint8_t *)"0"}, - {(uint8_t *)"Recording Device 2 ", (uint8_t *)"0"}, - {(uint8_t *)" Tuner 1 ", (uint8_t *)"0"}, - {(uint8_t *)" Playback Device 1 ", (uint8_t *)"0"}, - {(uint8_t *)" Audio System ", (uint8_t *)"0"}, - {(uint8_t *)" Tuner 2 ", (uint8_t *)"0"}, - {(uint8_t *)" Tuner 3 ", (uint8_t *)"0"}, - {(uint8_t *)" Playback Device 2 ", (uint8_t *)"0"}, - {(uint8_t *)"Recording Device 3 ", (uint8_t *)"0"}, - {(uint8_t *)" Tuner 4 ", (uint8_t *)"0"}, - {(uint8_t *)" Playback Device 3 ", (uint8_t *)"0"}, - {(uint8_t *)" Broadcast ", (uint8_t *)"1"} - }; - -/** - * @} - */ - - -/** @defgroup STM32100B_EVAL_CEC_Private_Function_Prototypes - * @{ - */ -static HDMI_CEC_Error PhysicalAddressDiscovery(void); -static HDMI_CEC_Error LogicalAddressAllocation(void); - - -/** - * @} - */ - - -/** @defgroup STM32100B_EVAL_CEC_Private_Functions - * @{ - */ - -/** - * @brief Initializes the HDMI CEC. - * @param None - * @retval HDMI_CEC_Error: CEC Error code - */ -HDMI_CEC_Error HDMI_CEC_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - CEC_InitTypeDef CEC_InitStructure; - HDMI_CEC_Error errorstatus = HDMI_CEC_OK; - uint8_t sendcount = 0; - -#ifdef HDMI_CEC_USE_DDC - I2C_InitTypeDef I2C_InitStructure; - /* Enable CEC_I2C clocks */ - RCC_APB1PeriphClockCmd(HDMI_CEC_I2C_CLK, ENABLE); - - /* Enable CEC_I2C_GPIO and CEC_HPD_GPIO clocks */ - RCC_APB2PeriphClockCmd(HDMI_CEC_I2C_GPIO_CLK | HDMI_CEC_HPD_GPIO_CLK, ENABLE); -#endif - - /* Enable CEC clocks */ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_CEC, ENABLE); - - /* Enable CEC_LINE_GPIO clocks */ - RCC_APB2PeriphClockCmd(HDMI_CEC_LINE_GPIO_CLK, ENABLE); - - /* Configure CEC_LINE_GPIO as Output open drain */ - GPIO_InitStructure.GPIO_Pin = HDMI_CEC_LINE_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD; - GPIO_Init(HDMI_CEC_LINE_GPIO_PORT, &GPIO_InitStructure); - -#ifdef HDMI_CEC_USE_DDC - /* Configure CEC_I2C_SCL_PIN and CEC_I2C_SDA_PIN as Output open drain */ - GPIO_InitStructure.GPIO_Pin = HDMI_CEC_I2C_SCL_PIN | HDMI_CEC_I2C_SDA_PIN; - GPIO_Init(HDMI_CEC_I2C_GPIO_PORT, &GPIO_InitStructure); - -/* This configuration is only when the HDMI CEC is configured as source. - The HDMI source has to provide the +5V Power signal to the sink. - On STM32100B-EVAL borad, you have to solder the SB4 Solder bridge. - Then, the source will wait for HPD signal to be asserted from the sink. - Once the HPD signal is detected the source shall read the EDID structure - throuhgh the DDC channel. */ - /* Configure CEC_HPD_GPIO as Input pull down */ - GPIO_InitStructure.GPIO_Pin = HDMI_CEC_HPD_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(HDMI_CEC_HPD_GPIO_PORT, &GPIO_InitStructure); - - -/* This configuration is only when the HDMI CEC is configured as sink. - The HDMI sink has to wait for the +5V Power signal from the source. - On STM32100B-EVAL borad, SB4 Solder bridge should be open (default configuration). - Then, the sink will assert the HPD signal to inform the source that the EDID - is ready for read through DDC channel. In this implementation, the EDID structure - is not implemented. */ -/* GPIO_InitStructure.GPIO_Pin = HDMI_CEC_HPD_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_Init(HDMI_CEC_HPD_GPIO_PORT, &GPIO_InitStructure); - - HDMI_CEC_HPD_HIGH(); // Set the Hot plug detect signal */ - - /* Enable CEC_I2C */ - I2C_Cmd(HDMI_CEC_I2C, ENABLE); - - /* I2C configuration */ - I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; - I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2; - I2C_InitStructure.I2C_OwnAddress1 = HDMI_CEC_I2C_SLAVE_ADDRESS7; - I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; - I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; - I2C_InitStructure.I2C_ClockSpeed = HDMI_CEC_I2C_CLOCK_SPEED; - I2C_Init(HDMI_CEC_I2C, &I2C_InitStructure); -#endif - - /* Physical Address discovery */ - errorstatus = PhysicalAddressDiscovery(); - - if (errorstatus != HDMI_CEC_OK) - { - /* Device not connected (Physical Address lost) */ - return(errorstatus); - } - - - /* CEC DeInit */ - CEC_DeInit(); - - /* Configure CEC */ - CEC_InitStructure.CEC_BitTimingMode = CEC_BitTimingStdMode; - CEC_InitStructure.CEC_BitPeriodMode = CEC_BitPeriodStdMode; - CEC_Init(&CEC_InitStructure); - - /* Set Prescaler value for APB1 clock = 24MHz */ - CEC_SetPrescaler(0x4AF); - - /* Enable CEC */ - CEC_Cmd(ENABLE); - - /* Logical Address Allocation */ - sendcount = 0; - errorstatus = LogicalAddressAllocation(); - - while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5) - { - sendcount++; - errorstatus = LogicalAddressAllocation(); - } - - if (errorstatus != HDMI_CEC_OK) - { - /* Device Unregistred */ - return(errorstatus); - } - - HDMI_CEC_CheckConnectedDevices(); - - /* Set the CEC initiator address */ - CEC_OwnAddressConfig(MyLogicalAddress); - - /* Activate CEC interrupts associated to the set of RBTF,RERR, TBTF, TERR flags */ - CEC_ITConfig(ENABLE); - - /* Report physical address*/ - errorstatus = HDMI_CEC_ReportPhysicalAddress(); - sendcount = 0; - - while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5) - { - sendcount++; - errorstatus = HDMI_CEC_ReportPhysicalAddress(); - } - - if (errorstatus != HDMI_CEC_OK) - { - /* Device Unregistred */ - return(errorstatus); - } - - return errorstatus; -} - -/** - * @brief Transmit message by taking data from typedef struct CEC_Meassage - * @param CEC_TX_MessageStructure: pointer to an CEC_Message structure that contains - * the message to be sent. - * @retval HDMI_CEC_Error: CEC Error code - */ -HDMI_CEC_Error HDMI_CEC_TransmitMessage(HDMI_CEC_Message *HDMI_CEC_TX_MessageStructure) -{ - HDMI_CEC_Error errorstatus = HDMI_CEC_OK; - __IO uint32_t count = 0, j = 0; - - SendFrame = 0; - SendStatus = 0; - TxCounter = 0; - BufferCount = 0; - - HDMI_CEC_TX_MessageStructPrivate = *HDMI_CEC_TX_MessageStructure; - - /* Initialize BufferPointer */ - for (j = 0; j < 15; j++) - { - BufferPointer[j] = 0; - } - - BufferPointer[0] = HDMI_CEC_TX_MessageStructPrivate.Opcode; - - for (BufferCount = 1; BufferCount < HDMI_CEC_TX_MessageStructPrivate.TxMessageLength + 1; BufferCount++) - { - BufferPointer[BufferCount] = HDMI_CEC_TX_MessageStructPrivate.Operande[BufferCount-1]; - } - - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - - /* Write single Data in the TX Buffer to Transmit through the CEC peripheral */ - CEC_SendDataByte(HDMI_CEC_TX_MessageStructPrivate.Header); - - /* Initiate Message Transmission */ - CEC_StartOfMessage(); - - while ((SendFrame == 0) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - if (SendStatus == 0) - { - errorstatus = (HDMI_CEC_Error) TransErrorCode; - } - - return errorstatus; -} - - -/** - * @brief Get the ESR register status. - * @param None - * @retval HDMI_CEC_Error: CEC Error code - */ -HDMI_CEC_Error HDMI_CEC_GetErrorStatus (void) -{ - HDMI_CEC_Error errorstatus = HDMI_CEC_OK; - - /* Bit timing error case*/ - if (CEC_GetFlagStatus(CEC_FLAG_BTE) != RESET) - { - errorstatus = HDMI_CEC_BIT_TIMING; - } - /* Bit period error case */ - if (CEC_GetFlagStatus(CEC_FLAG_BPE) != RESET) - { - errorstatus = HDMI_CEC_BIT_PERIOD; - } - /* Recieve error case */ - if (CEC_GetFlagStatus(CEC_FLAG_RBTFE) != RESET) - { - errorstatus = HDMI_CEC_RX_BLOCK_FINISHED; - } - /* Start bit error case*/ - if (CEC_GetFlagStatus(CEC_FLAG_SBE) != RESET) - { - errorstatus = HDMI_CEC_START_BIT; - } - /* Acknowledge error case*/ - if (CEC_GetFlagStatus(CEC_FLAG_ACKE) != RESET) - { - errorstatus = HDMI_CEC_BLOCK_ACKNOWLEDGE; - } - /* Line error case */ - if (CEC_GetFlagStatus(CEC_FLAG_LINE) != RESET) - { - errorstatus = HDMI_CEC_LINE; - } - /* Transfert error case*/ - if (CEC_GetFlagStatus(CEC_FLAG_TBTFE) != RESET) - { - errorstatus = HDMI_CEC_TX_BLOCK_FINISHED; - } - /* Clear All errors */ - CEC_ClearFlag(CEC_FLAG_RERR); - CEC_ClearFlag(CEC_FLAG_TERR); - return errorstatus; -} - -/** - * @brief Allows to process all the interrupts that are high. - * @param None - * @retval None - */ -void HDMI_CEC_ProcessIRQSrc(void) -{ - /********************** Reception *********************************************/ - /* Check if a reception error occured */ - if (CEC_GetFlagStatus(CEC_FLAG_RERR)) - { - /* Set receive status bit (Error) */ - ReceiveStatus = 0; - ReceivedFrame = 1; - RecepErrorCode = HDMI_CEC_GetErrorStatus(); - CEC_ClearFlag(CEC_FLAG_RERR | CEC_FLAG_RSOM | CEC_FLAG_REOM | CEC_FLAG_RBTF); - } - else if (CEC_GetFlagStatus(CEC_FLAG_RBTF)) - { - /* Check if the byte received is the last one of the message */ - if (CEC_GetFlagStatus(CEC_FLAG_REOM)) - { - HDMI_CEC_RX_MessageStructPrivate.Operande[RxCounter-1] = CEC_ReceiveDataByte(); - HDMI_CEC_RX_MessageStructPrivate.RxMessageLength = RxCounter; - ReceiveStatus = SUCCESS; - ReceivedFrame = 1; - } - /* Check if the byte received is a Header */ - else if (CEC_GetFlagStatus(CEC_FLAG_RSOM)) - { - ReceiveStatus = 0; - HDMI_CEC_RX_MessageStructPrivate.Header = CEC_ReceiveDataByte(); - RxCounter = 0; - } - /* Receive each byte except header in the reception buffer */ - else - { - if (RxCounter != 0) - { - HDMI_CEC_RX_MessageStructPrivate.Operande[RxCounter-1] = CEC_ReceiveDataByte(); - RxCounter++; - } - else - { - HDMI_CEC_RX_MessageStructPrivate.Opcode = CEC_ReceiveDataByte(); - RxCounter++; - } - - } - /* Clear all reception flags */ - CEC_ClearFlag(CEC_FLAG_RSOM | CEC_FLAG_REOM | CEC_FLAG_RBTF); - } - - /********************** Transmission ******************************************/ - /* Check if a transmission error occured */ - if (CEC_GetFlagStatus(CEC_FLAG_TERR)) - { - TransErrorCode = HDMI_CEC_GetErrorStatus(); - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - SendFrame = 1; - SendStatus = 0; - } - /* Check if end of message bit is set in the data to be transmitted */ - else if (CEC_GetFlagStatus(CEC_FLAG_TEOM)) - { - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_RBTF); - CEC_EndOfMessageCmd(DISABLE); - SendFrame = 1; - SendStatus = SUCCESS; - } - /* Check if data byte has been sent */ - else if (CEC_GetFlagStatus(CEC_FLAG_TBTRF)) - { - /* Set EOM bit if the byte to be transmitted is the last one of the TransmitBuffer */ - if (TxCounter == (HDMI_CEC_TX_MessageStructPrivate.TxMessageLength)) - { - CEC_SendDataByte(BufferPointer[TxCounter]); - TxCounter++; - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(ENABLE); - } - else - { - /* Put the byte in the TX Buffer */ - CEC_SendDataByte(BufferPointer[TxCounter]); - TxCounter++; - CEC_ClearFlag(CEC_FLAG_TBTRF); - } - } -} - -/** - * @brief Report physical address to all other devices thus allowing any - device to create a map of the network. - * @param None - * @retval HDMI_CEC_Error: CEC Error code. - */ -HDMI_CEC_Error HDMI_CEC_ReportPhysicalAddress(void) -{ - HDMI_CEC_Error errorstatus = HDMI_CEC_OK; - HDMI_CEC_Message HDMI_CEC_TX_Message; - - HDMI_CEC_TX_Message.Header = ((MyLogicalAddress << 4) | 0xF); - HDMI_CEC_TX_Message.Opcode = HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS; - HDMI_CEC_TX_Message.Operande[0] = MyPhysicalAddress >> 8; - HDMI_CEC_TX_Message.Operande[1] = MyPhysicalAddress & 0xFF; - HDMI_CEC_TX_Message.Operande[2] = DeviceType; - HDMI_CEC_TX_Message.TxMessageLength = 0x03; - - errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_Message); - - return errorstatus; -} - -/** - * @brief Handle CEC command receive callback. - * When receiving the STANDBY Opcode commande, the system is entred in - * Stop mode and when wakeup, the PLL is configured as system clock and - * the HSI is selected as PLL source. - * @param None - * @retval None - */ -void HDMI_CEC_CommandCallBack(void) -{ - uint8_t i = 0, sendcount = 0; - HDMI_CEC_Error errorstatus = HDMI_CEC_OK; - EXTI_InitTypeDef EXTI_InitStructure; - - switch (HDMI_CEC_RX_MessageStructPrivate.Opcode) - { - case HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS: - HDMI_CEC_MapStruct.PhysicalAddress_A = HDMI_CEC_RX_MessageStructPrivate.Operande[1] >> 4; - HDMI_CEC_MapStruct.PhysicalAddress_B = HDMI_CEC_RX_MessageStructPrivate.Operande[1] & 0x0F; - HDMI_CEC_MapStruct.PhysicalAddress_C = HDMI_CEC_RX_MessageStructPrivate.Operande[0] >> 4; - HDMI_CEC_MapStruct.PhysicalAddress_D = HDMI_CEC_RX_MessageStructPrivate.Operande[0] & 0x0F; - HDMI_CEC_MapStruct.LogicalAddress = (HDMI_CEC_RX_MessageStructPrivate.Header >> 0x4) & 0x0F; - HDMI_CEC_MapStruct.DeviceType = HDMI_CEC_RX_MessageStructPrivate.Operande[2]; - HDMI_CEC_DeviceMap[DeviceCount] = HDMI_CEC_MapStruct; - HDMI_CEC_Follower_String[(HDMI_CEC_DeviceMap[DeviceCount].LogicalAddress)][1] = (uint8_t *)"1"; - DeviceCount++; - break; - - case HDMI_CEC_OPCODE_STANDBY: - /* CEC Line */ - GPIO_EXTILineConfig(GPIO_PortSourceGPIOB, GPIO_PinSource8); - /* Configure the CEC Line as EXTI Line on Falling Edge */ - EXTI_ClearITPendingBit(EXTI_Line8); - EXTI_InitStructure.EXTI_Line = EXTI_Line8; - EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStructure.EXTI_LineCmd = ENABLE; - EXTI_Init(&EXTI_InitStructure); - /* Request to enter Stop mode */ - PWR_EnterSTOPMode(PWR_Regulator_ON, PWR_STOPEntry_WFI); - - /* Disable the CEC EXTI Line */ - EXTI_InitStructure.EXTI_LineCmd = DISABLE; - EXTI_Init(&EXTI_InitStructure); - /* Configure the PLL Source */ - RCC_PLLConfig(RCC_PLLSource_HSI_Div2, RCC_PLLMul_6); - - /* Enable PLL */ - RCC_PLLCmd(ENABLE); - - /* Wait till PLL is ready */ - while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) - { - } - - /* Select PLL as system clock source */ - RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); - - /* Wait till PLL is used as system clock source */ - while(RCC_GetSYSCLKSource() != 0x08) - { - } - break; - - case HDMI_CEC_OPCODE_GET_CEC_VERSION: - /* Send the Used CEC version */ - HDMI_CEC_TX_MessageStructPrivate.Header = ((MyLogicalAddress << 4) | HDMI_CEC_RX_MessageStructPrivate.Header >> 4); - HDMI_CEC_TX_MessageStructPrivate.Opcode = HDMI_CEC_OPCODE_CEC_VERSION; - HDMI_CEC_TX_MessageStructPrivate.Operande[0] = HDMI_CEC_VERSION; /* CEC Version */ - HDMI_CEC_TX_MessageStructPrivate.TxMessageLength = 0x01; - errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate); - - /* Retransmit message until 5 time */ - while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5) - { - sendcount++; - errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate); - } - break; - - case HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS: - /* Send the Physical address */ - errorstatus = HDMI_CEC_ReportPhysicalAddress(); - sendcount = 0; - /* Retransmit message until 5 time */ - while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5) - { - sendcount++; - errorstatus = HDMI_CEC_ReportPhysicalAddress(); - } - break; - - case HDMI_CEC_OPCODE_FEATURE_ABORT: - /* The device doesn't support the requested message type, or that it cannot - execute it at the present time. */ - FeatureOpcode = HDMI_CEC_RX_MessageStructPrivate.Operande[0]; - AbortReason = HDMI_CEC_RX_MessageStructPrivate.Operande[1]; - break; - - case HDMI_CEC_OPCODE_GIVE_OSD_NAME: - /* Send the OSD name = STM32100B CEC*/ - HDMI_CEC_TX_MessageStructPrivate.Header = ((MyLogicalAddress << 4) | HDMI_CEC_RX_MessageStructPrivate.Header >> 4); - HDMI_CEC_TX_MessageStructPrivate.Opcode = HDMI_CEC_OPCODE_SET_OSD_NAME; - /* STM32100B*/ - HDMI_CEC_TX_MessageStructPrivate.Operande[0] = 0x53; - HDMI_CEC_TX_MessageStructPrivate.Operande[1] = 0x54; - HDMI_CEC_TX_MessageStructPrivate.Operande[2] = 0x4D; - HDMI_CEC_TX_MessageStructPrivate.Operande[3] = 0x33; - HDMI_CEC_TX_MessageStructPrivate.Operande[4] = 0x32; - HDMI_CEC_TX_MessageStructPrivate.Operande[5] = 0x31; - HDMI_CEC_TX_MessageStructPrivate.Operande[6] = 0x30; - HDMI_CEC_TX_MessageStructPrivate.Operande[7] = 0x30; - HDMI_CEC_TX_MessageStructPrivate.Operande[8] = 0x42; - HDMI_CEC_TX_MessageStructPrivate.Operande[9] = 0x20; - /* CEC */ - HDMI_CEC_TX_MessageStructPrivate.Operande[10] = 0x43; - HDMI_CEC_TX_MessageStructPrivate.Operande[11] = 0x45; - HDMI_CEC_TX_MessageStructPrivate.Operande[12] = 0x43; - HDMI_CEC_TX_MessageStructPrivate.TxMessageLength = 13; - errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate); - sendcount = 0; - /* Retransmit message until 5 time */ - while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5) - { - sendcount++; - errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate); - } - break; - - case HDMI_CEC_OPCODE_ROUTING_CHANGE: - for (i = 0;i < 0x14;i++) - { - if ((HDMI_CEC_DeviceMap[i].PhysicalAddress_A == HDMI_CEC_RX_MessageStructPrivate.Operande[1] >> 4) && - (HDMI_CEC_DeviceMap[i].PhysicalAddress_B == HDMI_CEC_RX_MessageStructPrivate.Operande[1]&0x0F) && - (HDMI_CEC_DeviceMap[i].PhysicalAddress_C == HDMI_CEC_RX_MessageStructPrivate.Operande[0] >> 4) && - (HDMI_CEC_DeviceMap[i].PhysicalAddress_D == HDMI_CEC_RX_MessageStructPrivate.Operande[0]&0x0F)) - { - HDMI_CEC_MapStruct.LogicalAddress = (HDMI_CEC_RX_MessageStructPrivate.Header >> 0x4) & 0x0F; - HDMI_CEC_MapStruct.DeviceType = HDMI_CEC_RX_MessageStructPrivate.Operande[2]; - HDMI_CEC_DeviceMap[i] = HDMI_CEC_MapStruct; - } - } - break; - - default: - /* Send Abort feature*/ - HDMI_CEC_TX_MessageStructPrivate.Header = ((MyLogicalAddress << 4) | HDMI_CEC_RX_MessageStructPrivate.Header >> 4); - HDMI_CEC_TX_MessageStructPrivate.Opcode = HDMI_CEC_OPCODE_FEATURE_ABORT; - HDMI_CEC_TX_MessageStructPrivate.Operande[0] = 0x02; /* defines command to be performed */ - HDMI_CEC_TX_MessageStructPrivate.Operande[1] = HDMI_CEC_REFUSED; /* Reason for abort feature */ - HDMI_CEC_TX_MessageStructPrivate.TxMessageLength = 0x02; - errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate); - sendcount = 0; - /* Retransmit message until 5 time */ - while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5) - { - sendcount++; - errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate); - } - break; - - } -} - -/** - * @brief Check the connected CEC devices. - * @param None - * @retval HDMI_CEC_Error - */ -HDMI_CEC_Error HDMI_CEC_CheckConnectedDevices(void) -{ - HDMI_CEC_Error errorstatus = HDMI_CEC_OK; - uint32_t count = 0, i = 1; - - /*----------------------------- TV device ---------------------------*/ - CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte((MyLogicalAddress << 4) | 0x0); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_OK) - { - HDMI_CEC_Follower_String[0][1] = (uint8_t *)"1"; - i++; - errorstatus = HDMI_CEC_OK; - } - - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - - /*----------------------------- Recording device 1 ---------------------------*/ - CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte((MyLogicalAddress << 4) | 0x1); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_OK) - { - HDMI_CEC_Follower_String[1][1] = (uint8_t *)"1"; - i++; - errorstatus = HDMI_CEC_OK; - } - - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - /*----------------------------- Recording device 2 ---------------------------*/ - CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte((MyLogicalAddress << 4) | 0x2); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_OK) - { - HDMI_CEC_Follower_String[2][1] = (uint8_t *)"1"; - i++; - errorstatus = HDMI_CEC_OK; - } - - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - - /*----------------------------- Tuner 1 ---------------------------*/ - CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte((MyLogicalAddress << 4) | 0x3); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_OK) - { - HDMI_CEC_Follower_String[3][1] = (uint8_t *)"1"; - i++; - errorstatus = HDMI_CEC_OK; - } - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - /*----------------------------- Playback device 1 ---------------------------*/ - CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte((MyLogicalAddress << 4) | 0x4); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_OK) - { - HDMI_CEC_Follower_String[4][1] = (uint8_t *)"1"; - i++; - errorstatus = HDMI_CEC_OK; - } - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - - /*----------------------------- Audio system ---------------------------*/ - CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte((MyLogicalAddress << 4) | 0x5); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_OK) - { - HDMI_CEC_Follower_String[5][1] = (uint8_t *)"1"; - i++; - errorstatus = HDMI_CEC_OK; - } - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - - /*----------------------------- Tuner 2 ---------------------------*/ - CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte((MyLogicalAddress << 4) | 0x6); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_OK) - { - HDMI_CEC_Follower_String[6][1] = (uint8_t *)"1"; - i++; - errorstatus = HDMI_CEC_OK; - } - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - - /*----------------------------- Tuner 3 ---------------------------*/ - CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte((MyLogicalAddress << 4) | 0x7); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_OK) - { - HDMI_CEC_Follower_String[7][1] = (uint8_t *)"1"; - i++; - errorstatus = HDMI_CEC_OK; - } - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - - /*----------------------------- Playback device 2 ---------------------------*/ - CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte((MyLogicalAddress << 4) | 0x8); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_OK) - { - HDMI_CEC_Follower_String[8][1] = (uint8_t *)"1"; - i++; - errorstatus = HDMI_CEC_OK; - } - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - - /*----------------------------- Recording device 3 ---------------------------*/ - CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte((MyLogicalAddress << 4) | 0x9); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_OK) - { - HDMI_CEC_Follower_String[9][1] = (uint8_t *)"1"; - i++; - errorstatus = HDMI_CEC_OK; - } - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - /*----------------------------- Tuner 4 ---------------------------*/ - CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte((MyLogicalAddress << 4) | 0xA); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_OK) - { - HDMI_CEC_Follower_String[10][1] = (uint8_t *)"1"; - i++; - errorstatus = HDMI_CEC_OK; - } - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - /*----------------------------- Playback device 3 ---------------------------*/ - CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte((MyLogicalAddress << 4) | 0xB); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_OK) - { - HDMI_CEC_Follower_String[11][1] = (uint8_t *)"1"; - i++; - errorstatus = HDMI_CEC_OK; - } - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - - CECDevicesNumber = i - 1; - - return errorstatus; -} - -/** - * @brief Physical address discovery. - * @param None - * @retval HDMI_CEC_Error: CEC Error code. - */ -static HDMI_CEC_Error PhysicalAddressDiscovery(void) -{ - HDMI_CEC_Error errorstatus = HDMI_CEC_OK; -#ifdef HDMI_CEC_USE_DDC - uint32_t index = 0, i = 0; -#endif - - /*------------------------------ Physical address discovery -----------------*/ - if (HDMI_CEC_ROOT == 0x1) - { - MyPhysicalAddress = 0x0000; - /* The HDMI-CEC here is configured as sink or as a repeater. The configuration - of the +5V power signal and the HPD should be well configured. - Implement here the EDID Structure to be sent to the HDMI source. - For more details please refer to the HDMI specification. - The EDID structure should be sent to the device source using the DDC Channel - and using the HPD signal. */ - } - else - { - -#ifdef HDMI_CEC_USE_DDC - /* The HDMI-CEC here is configured as source or as a repeater. The configuration - of the +5V power signal and the HPD should be well configured. - The source should wait for HPD and then read the EDID structure. */ - while(GPIO_ReadInputDataBit(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN) == RESET) - { - } - /* Wait for 100 ms after HPD was received */ - for(i = 0; i < 0x5FFFF; i++) - { - } - - /* Return the physical address using the I2C by reading the 2 bytes 24 and - 25 form the EDID */ - /* Read the EDID Block 0 and EDID Block 1 at address 0xA0 */ - /*!< While the bus is busy */ - while(I2C_GetFlagStatus(HDMI_CEC_I2C, I2C_FLAG_BUSY)) - { - } - - /*!< Send START condition */ - I2C_GenerateSTART(HDMI_CEC_I2C, ENABLE); - - /*!< Test on EV5 and clear it */ - while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_MODE_SELECT)) - { - } - - /*!< Send EEPROM address for write */ - I2C_Send7bitAddress(HDMI_CEC_I2C, 0xA0, I2C_Direction_Transmitter); - - - /*!< Test on EV6 and clear it */ - while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) - { - } - - /*!< Send the EEPROM's internal address to read from: Only one byte address */ - I2C_SendData(HDMI_CEC_I2C, 0x00); - - /*!< Test on EV8 and clear it */ - while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED)) - { - } - - /*!< Send STRAT condition a second time */ - I2C_GenerateSTART(HDMI_CEC_I2C, ENABLE); - - /*!< Test on EV5 and clear it */ - while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_MODE_SELECT)) - { - } - - /*!< Send EEPROM address for read */ - I2C_Send7bitAddress(HDMI_CEC_I2C, 0xA1, I2C_Direction_Receiver); - - /*!< Test on EV6 and clear it */ - while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)) - { - } - - /* While there is data to be read */ - while (NumByteToRead-- > 1) - { - while(I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_BYTE_RECEIVED)) - { - } - for(i = 0; i < 0xFFF; i++) - { - } - pBuffer[index++] = I2C_ReceiveData(HDMI_CEC_I2C); - } - - /* Disable Acknowledgement */ - I2C_AcknowledgeConfig(HDMI_CEC_I2C, DISABLE); - - /* Send STOP Condition */ - I2C_GenerateSTOP(HDMI_CEC_I2C, ENABLE); - - while(I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_BYTE_RECEIVED)); - pBuffer[index] = I2C_ReceiveData(HDMI_CEC_I2C); - - /* Enable Acknowledgement to be ready for another reception */ - I2C_AcknowledgeConfig(HDMI_CEC_I2C, ENABLE); - MyPhysicalAddress = ((pBuffer[138] << 8) | pBuffer[137]); -#else - MyPhysicalAddress = 0x1000; -#endif - } - - return errorstatus; -} -/** - * @brief Allocate the logical address. - * @param None - * @retval HDMI_CEC_Error: CEC Error code. - */ -static HDMI_CEC_Error LogicalAddressAllocation(void) -{ - HDMI_CEC_Error errorstatus = HDMI_CEC_OK; - uint32_t count = 0; - - /*------------------ Logical address allocation -----------------------------*/ - /* Get the device type */ - /* Device type = CEC_TV */ - if (DeviceType == HDMI_CEC_TV) - { - if (HDMI_CEC_ROOT) - { - MyLogicalAddress = 0x00; - } - else - { - CEC_OwnAddressConfig(0xE); /* Own address = 0xE */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte(0xEE); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the polling message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE) - { - MyLogicalAddress = 0x0E; - errorstatus = HDMI_CEC_OK; - } - else if (errorstatus == HDMI_CEC_OK) - { - MyLogicalAddress = 0x0F; - errorstatus = HDMI_CEC_DEVICE_UNREGISTRED; - } - } - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - } - - /* Device type = CEC_RECORDING */ - if (DeviceType == HDMI_CEC_RECORDING) - { - CEC_OwnAddressConfig(0x1); /* Own address = 0x1 */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte(0x11); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE) - { - MyLogicalAddress = 0x01; - errorstatus = HDMI_CEC_OK; - } - else if (errorstatus == HDMI_CEC_OK) - { - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - - CEC_EndOfMessageCmd(DISABLE); - - CEC_OwnAddressConfig(0x2); /* Own address = 0x2 */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte(0x22); - - /* Start of message */ - CEC_StartOfMessage(); - - count = 0; - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE) - { - MyLogicalAddress = 0x02; - errorstatus = HDMI_CEC_OK; - } - else if (errorstatus == HDMI_CEC_OK) - { - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - - CEC_EndOfMessageCmd(DISABLE); - - CEC_OwnAddressConfig(0x9); /* Own address = 0x9 */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte(0x99); - - /* Start of message */ - CEC_StartOfMessage(); - - count = 0; - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE) - { - MyLogicalAddress = 0x09; - errorstatus = HDMI_CEC_OK; - } - else if (errorstatus == HDMI_CEC_OK) - { - MyLogicalAddress = 0x0F; - errorstatus = HDMI_CEC_DEVICE_UNREGISTRED; - } - } - } - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - CEC_EndOfMessageCmd(DISABLE); - } - - /* Device type = CEC_TUNER */ - if (DeviceType == HDMI_CEC_TUNER) - { - CEC_OwnAddressConfig(0x3); /* Own address = 0x3 */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte(0x33); - - /* Start of message */ - CEC_StartOfMessage(); - - count = 0; - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE) - { - MyLogicalAddress = 0x03; - errorstatus = HDMI_CEC_OK; - } - else if (errorstatus == HDMI_CEC_OK) - { - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - - CEC_EndOfMessageCmd(DISABLE); - - CEC_OwnAddressConfig(0x6); /* Own address = 0x6 */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte(0x66); - - /* Start of message */ - CEC_StartOfMessage(); - - count = 0; - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE) - { - MyLogicalAddress = 0x06; - errorstatus = HDMI_CEC_OK; - } - else if (errorstatus == HDMI_CEC_OK) - { - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - - CEC_EndOfMessageCmd(DISABLE); - - CEC_OwnAddressConfig(0x7); /* Own address = 0x7 */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte(0x77); - - /* Start of message */ - CEC_StartOfMessage(); - - count = 0; - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE) - { - MyLogicalAddress = 0x07; - errorstatus = HDMI_CEC_OK; - } - else if (errorstatus == HDMI_CEC_OK) - { - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - - CEC_EndOfMessageCmd(DISABLE); - - CEC_OwnAddressConfig(0xA); /* Own address = 0xA */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte(0xAA); - - /* Start of message */ - CEC_StartOfMessage(); - - count = 0; - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE) - { - MyLogicalAddress = 0x0A; - errorstatus = HDMI_CEC_OK; - } - else if (errorstatus == HDMI_CEC_OK) - { - MyLogicalAddress = 0x0F; - errorstatus = HDMI_CEC_DEVICE_UNREGISTRED; - } - } - } - } - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - CEC_EndOfMessageCmd(DISABLE); - } - - /* Device type = CEC_PLAYBACK */ - if (DeviceType == HDMI_CEC_PLAYBACK) - { - CEC_OwnAddressConfig(0x4); /* Own address = 0x4 */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte(0x44); - - /* Start of message */ - CEC_StartOfMessage(); - - count = 0; - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE) - { - MyLogicalAddress = 0x04; - errorstatus = HDMI_CEC_OK; - } - else if (errorstatus == HDMI_CEC_OK) - { - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - - CEC_EndOfMessageCmd(DISABLE); - - CEC_OwnAddressConfig(0x8); /* Own address = 0x8 */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte(0x88); - - /* Start of message */ - CEC_StartOfMessage(); - - count = 0; - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE) - { - MyLogicalAddress = 0x08; - errorstatus = HDMI_CEC_OK; - } - else if (errorstatus == HDMI_CEC_OK) - { - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - - CEC_EndOfMessageCmd(DISABLE); - - CEC_OwnAddressConfig(0xB); /* Own address = 0xBB */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte(0xBB); - - /* Start of message */ - CEC_StartOfMessage(); - - count = 0; - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE) - { - MyLogicalAddress = 0x0B; - errorstatus = HDMI_CEC_OK; - } - else if (errorstatus == HDMI_CEC_OK) - { - MyLogicalAddress = 0x0F; - errorstatus = HDMI_CEC_DEVICE_UNREGISTRED; - } - } - } - - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - CEC_EndOfMessageCmd(DISABLE); - } - - /* Device type = CEC Audio System */ - if (DeviceType == HDMI_CEC_AUDIOSYSTEM) - { - CEC_OwnAddressConfig(0x5); /* Own address = 0x5 */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte(0x55); - - /* Start of message */ - CEC_StartOfMessage(); - - count = 0; - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE) - { - MyLogicalAddress = 0x05; - errorstatus = HDMI_CEC_OK; - } - else if (errorstatus == HDMI_CEC_OK) - { - MyLogicalAddress = 0x0F; - errorstatus = HDMI_CEC_DEVICE_UNREGISTRED; - } - - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - CEC_EndOfMessageCmd(DISABLE); - } - - return errorstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - - diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_cec.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_cec.h deleted file mode 100644 index bb13ea4be..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_cec.h +++ /dev/null @@ -1,290 +0,0 @@ -/** - ****************************************************************************** - * @file stm32100b_eval_cec.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains all the functions prototypes for the stm32100b_eval_cec - * firmware driver. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32100B_EVAL_CEC_H -#define __STM32100B_EVAL_CEC_H - -#ifdef __cplusplus -extern "C" -{ -#endif - - /* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32100B_EVAL - * @{ - */ - -/** @defgroup STM32100B_EVAL_CEC - * @{ - */ - -/** @defgroup STM32100B_EVAL_CEC_Exported_Types - * @{ - */ -typedef enum -{ - HDMI_CEC_BIT_TIMING = (1), /*!< CEC Bit Timing Error */ - HDMI_CEC_BIT_PERIOD = (2), /*!< CEC Bit Period Error */ - HDMI_CEC_RX_BLOCK_FINISHED = (3), /*!< CEC Receive Block finished Error */ - HDMI_CEC_START_BIT = (4), /*!< CEC Start Bit Error */ - HDMI_CEC_BLOCK_ACKNOWLEDGE = (5), /*!< CEC Block Acknowledge Error */ - HDMI_CEC_LINE = (6), /*!< CEC Line Error */ - HDMI_CEC_TX_BLOCK_FINISHED = (7), /*!< CEC Transmit Block Transfer finished Error */ - HDMI_CEC_DEVICE_UNREGISTRED = (8), /*!< CEC Device Unregistred */ - HDMI_CEC_TIMEOUT = (9), /*!< CEC TimeOut */ - HDMI_CEC_OK = (10) /*!< CEC OK */ -}HDMI_CEC_Error; - -typedef struct -{ - __IO uint8_t PhysicalAddress_A; - __IO uint8_t PhysicalAddress_B; - __IO uint8_t PhysicalAddress_C; - __IO uint8_t PhysicalAddress_D; - __IO uint8_t LogicalAddress; - __IO uint8_t DeviceType; -}HDMI_CEC_Map; - - -#define HDMI_CEC_TX_MESSAGE_LENGTH_MAX ((uint32_t)0x0000000E) -#define HDMI_CEC_TIMEOUT_VALUE ((uint32_t)0x001FFFFF) - -/** -* @brief CEC Init Structure definition -*/ -typedef struct -{ - __IO uint8_t Header; - __IO uint8_t Opcode; - __IO uint8_t Operande[HDMI_CEC_TX_MESSAGE_LENGTH_MAX]; - __IO uint8_t TxMessageLength; - __IO uint8_t RxMessageLength; -}HDMI_CEC_Message; - -/** -* @} -*/ - -/** @defgroup STM32100B_EVAL_CEC_Exported_Constants - * @{ - */ - -/** - * @brief CEC device types - */ -#define HDMI_CEC_TV 0x00 -#define HDMI_CEC_RECORDING 0x01 -#define HDMI_CEC_TUNER 0x03 -#define HDMI_CEC_PLAYBACK 0x04 -#define HDMI_CEC_AUDIOSYSTEM 0x05 - - -/** - * @brief HDMI CEC I2C Interface pins - */ -#define HDMI_CEC_I2C_SCL_PIN GPIO_Pin_10 -#define HDMI_CEC_I2C_SDA_PIN GPIO_Pin_11 -#define HDMI_CEC_I2C_GPIO_PORT GPIOB -#define HDMI_CEC_I2C_GPIO_CLK RCC_APB2Periph_GPIOB -#define HDMI_CEC_I2C I2C2 -#define HDMI_CEC_I2C_CLK RCC_APB1Periph_I2C2 - -/** - * @brief HDMI CEC HPD (Hot Plug Detect) Interface pin - */ -#define HDMI_CEC_HPD_PIN GPIO_Pin_12 -#define HDMI_CEC_HPD_GPIO_PORT GPIOB -#define HDMI_CEC_HPD_GPIO_CLK RCC_APB2Periph_GPIOB - -/** - * @brief HDMI CEC Interface pin - */ -#define HDMI_CEC_LINE_PIN GPIO_Pin_8 -#define HDMI_CEC_LINE_GPIO_PORT GPIOB -#define HDMI_CEC_LINE_GPIO_CLK RCC_APB2Periph_GPIOB - -#define HDMI_CEC_I2C_SLAVE_ADDRESS7 0xA0 -#define HDMI_CEC_I2C_CLOCK_SPEED 100000 - -/** - * @brief HDMI CEC Root (Mainly for TV with a fixed physical address (0.0.0.0)) - * If you want to configure the STM32100B-EVAL board as CEC Root (Sink) - * change the following define to 0x1 - */ -#define HDMI_CEC_ROOT 0x00 - -/** - * @brief To select if the DDC Channel will be used for physical address discovery - * or not. To use the DDC Channel to read the EDID structure uncomment - * the following line. - * If the device is configured as HMDI source it should read his own physical - * address from the sink that is connected to. - */ -/* #define HDMI_CEC_USE_DDC */ - -/** - * @brief CEC version: V1.3a - */ -#define HDMI_CEC_VERSION 0x04 - -/** - * @brief Reason for Abort feature - */ -#define HDMI_CEC_UNRECOGNIZED_OPCODE 0x00 -#define HDMI_CEC_NOT_CORRECT_MODETORESPOND 0x01 -#define HDMI_CEC_CANNOTPROVIDE_SOURCE 0x02 -#define HDMI_CEC_INVALID_OPERAND 0x03 -#define HDMI_CEC_REFUSED 0x04 - -/** - * @brief HDMI CEC specific commands - */ -#define HDMI_CEC_OPCODE_ACTIVE_SOURCE ((uint8_t) 0x82) -#define HDMI_CEC_OPCODE_IMAGE_VIEW_ON ((uint8_t) 0x04) -#define HDMI_CEC_OPCODE_TEXT_VIEW_ON ((uint8_t) 0x0D) -#define HDMI_CEC_OPCODE_INACTIVE_SOURCE ((uint8_t) 0x9D) -#define HDMI_CEC_OPCODE_REQUEST_ACTIVE_SOURCE ((uint8_t) 0x85) -#define HDMI_CEC_OPCODE_ROUTING_CHANGE ((uint8_t) 0x80) -#define HDMI_CEC_OPCODE_ROUTING_INFORMATION ((uint8_t) 0x81) -#define HDMI_CEC_OPCODE_SET_STREAM_PATH ((uint8_t) 0x86) -#define HDMI_CEC_OPCODE_STANDBY ((uint8_t) 0x36) -#define HDMI_CEC_OPCODE_RECORD_OFF ((uint8_t) 0x0B) -#define HDMI_CEC_OPCODE_RECORD_ON ((uint8_t) 0x09) -#define HDMI_CEC_OPCODE_RECORD_STATUS ((uint8_t) 0x0A) -#define HDMI_CEC_OPCODE_RECORD_TV_SCREEN ((uint8_t) 0x0F) -#define HDMI_CEC_OPCODE_CLEAR_ANALOGUE_TIMER ((uint8_t) 0x33) -#define HDMI_CEC_OPCODE_CLEAR_DIGITAL_TIMER ((uint8_t) 0x99) -#define HDMI_CEC_OPCODE_CLEAR_EXTERNAL_TIMER ((uint8_t) 0xA1) -#define HDMI_CEC_OPCODE_SET_ANALOGUE_TIMER ((uint8_t) 0x34) -#define HDMI_CEC_OPCODE_SET_DIGITAL_TIMER ((uint8_t) 0x97) -#define HDMI_CEC_OPCODE_SET_EXTERNAL_TIMER ((uint8_t) 0xA2) -#define HDMI_CEC_OPCODE_SET_TIMER_PROGRAM_TITLE ((uint8_t) 0x67) -#define HDMI_CEC_OPCODE_TIMER_CLEARED_STATUS ((uint8_t) 0x43) -#define HDMI_CEC_OPCODE_TIMER_STATUS ((uint8_t) 0x35) -#define HDMI_CEC_OPCODE_CEC_VERSION ((uint8_t) 0x9E) -#define HDMI_CEC_OPCODE_GET_CEC_VERSION ((uint8_t) 0x9F) -#define HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS ((uint8_t) 0x83) -#define HDMI_CEC_OPCODE_GET_MENU_LANGUAGE ((uint8_t) 0x91) -#define HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS ((uint8_t) 0x84) -#define HDMI_CEC_OPCODE_SET_MENU_LANGUAGE ((uint8_t) 0x32) -#define HDMI_CEC_OPCODE_DECK_CONTROL ((uint8_t) 0x42) -#define HDMI_CEC_OPCODE_DECK_STATUS ((uint8_t) 0x1B) -#define HDMI_CEC_OPCODE_GIVE_DECK_STATUS ((uint8_t) 0x1A) -#define HDMI_CEC_OPCODE_PLAY ((uint8_t) 0x41) -#define HDMI_CEC_OPCODE_GIVE_TUNER_DEVICE_STATUS ((uint8_t) 0x08) -#define HDMI_CEC_OPCODE_SELECT_ANALOGUE_SERVICE ((uint8_t) 0x92) -#define HDMI_CEC_OPCODE_SELECT_DIGITAL_SERVICE ((uint8_t) 0x93) -#define HDMI_CEC_OPCODE_TUNER_DEVICE_STATUS ((uint8_t) 0x07) -#define HDMI_CEC_OPCODE_TUNER_STEP_DECREMENT ((uint8_t) 0x06) -#define HDMI_CEC_OPCODE_TUNER_STEP_INCREMENT ((uint8_t) 0x05) -#define HDMI_CEC_OPCODE_DEVICE_VENDOR_ID ((uint8_t) 0x87) -#define HDMI_CEC_OPCODE_GIVE_DEVICE_VENDOR_ID ((uint8_t) 0x8C) -#define HDMI_CEC_OPCODE_VENDOR_COMMAND ((uint8_t) 0x89) -#define HDMI_CEC_OPCODE_VENDOR_COMMAND_WITH_ID ((uint8_t) 0xA0) -#define HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_DOWN ((uint8_t) 0x8A) -#define HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_UP ((uint8_t) 0x8B) -#define HDMI_CEC_OPCODE_SET_OSD_STRING ((uint8_t) 0x64) -#define HDMI_CEC_OPCODE_GIVE_OSD_NAME ((uint8_t) 0x46) -#define HDMI_CEC_OPCODE_SET_OSD_NAME ((uint8_t) 0x47) -#define HDMI_CEC_OPCODE_MENU_REQUEST ((uint8_t) 0x8D) -#define HDMI_CEC_OPCODE_MENU_STATUS ((uint8_t) 0x8E) -#define HDMI_CEC_OPCODE_USER_CONTROL_PRESSED ((uint8_t) 0x44) -#define HDMI_CEC_OPCODE_USER_CONTROL_RELEASED ((uint8_t) 0x45) -#define HDMI_CEC_OPCODE_GIVE_DEVICE_POWER_STATUS ((uint8_t) 0x8F) -#define HDMI_CEC_OPCODE_REPORT_POWER_STATUS ((uint8_t) 0x90) -#define HDMI_CEC_OPCODE_FEATURE_ABORT ((uint8_t) 0x00) -#define HDMI_CEC_OPCODE_ABORT ((uint8_t) 0xFF) -#define HDMI_CEC_OPCODE_GIVE_AUDIO_STATUS ((uint8_t) 0x71) -#define HDMI_CEC_OPCODE_GIVE_SYSTEM_AUDIO_MODE_STATUS ((uint8_t) 0x7D) -#define HDMI_CEC_OPCODE_REPORT_AUDIO_STATUS ((uint8_t) 0x7A) -#define HDMI_CEC_OPCODE_SET_SYSTEM_AUDIO_MODE ((uint8_t) 0x72) -#define HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_REQUEST ((uint8_t) 0x70) -#define HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_STATUS ((uint8_t) 0x7E) -#define HDMI_CEC_OPCODE_SET_AUDIO_RATE ((uint8_t) 0x9A) - - -/** - * @} - */ - -/** @defgroup STM32100B_EVAL_CEC_Exported_Macros - * @{ - */ -/* HDMI_CEC_HPD: HDMI HPD pin low */ -#define HDMI_CEC_HPD_LOW() GPIO_ResetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN) -/* HDMI_CEC_HPD: HDMI HPD pin high */ -#define HDMI_CEC_HPD_HIGH() GPIO_SetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN) - -/** - * @} - */ - -/** @defgroup STM32100B_EVAL_CEC_Exported_Functions - * @{ - */ -HDMI_CEC_Error HDMI_CEC_Init(void); -HDMI_CEC_Error HDMI_CEC_TransmitMessage(HDMI_CEC_Message *HDMI_CEC_TX_MessageStructure); -HDMI_CEC_Error HDMI_CEC_GetErrorStatus (void); -void HDMI_CEC_ProcessIRQSrc(void); -HDMI_CEC_Error HDMI_CEC_ReportPhysicalAddress(void); -void HDMI_CEC_CommandCallBack(void); -HDMI_CEC_Error HDMI_CEC_CheckConnectedDevices(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32100B_EVAL_CEC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_lcd.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_lcd.c deleted file mode 100644 index e719b0e25..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_lcd.c +++ /dev/null @@ -1,1875 +0,0 @@ -/** - ****************************************************************************** - * @file stm32100b_eval_lcd.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312), - * AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B) - * Liquid Crystal Display Module of STM32100B-EVAL board. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32100b_eval_lcd.h" -#include "../Common/fonts.c" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32100B_EVAL - * @{ - */ - -/** @defgroup STM32100B_EVAL_LCD - * @brief This file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312), - * AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B) - * Liquid Crystal Display Module of STM32100B-EVAL board. - * @{ - */ - -/** @defgroup STM32100B_EVAL_LCD_Private_Types - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32100B_EVAL_LCD_Private_Defines - * @{ - */ -#define LCD_ILI9320 0x9320 -#define LCD_HX8312 0x8312 -#define LCD_SPFD5408 0x5408 -#define START_BYTE 0x70 -#define SET_INDEX 0x00 -#define READ_STATUS 0x01 -#define LCD_WRITE_REG 0x02 -#define LCD_READ_REG 0x03 -#define MAX_POLY_CORNERS 200 -#define POLY_Y(Z) ((int32_t)((Points + Z)->X)) -#define POLY_X(Z) ((int32_t)((Points + Z)->Y)) -/** - * @} - */ - -/** @defgroup STM32100B_EVAL_LCD_Private_Macros - * @{ - */ -#define ABS(X) ((X) > 0 ? (X) : -(X)) -/** - * @} - */ - -/** @defgroup STM32100B_EVAL_LCD_Private_Variables - * @{ - */ -static sFONT *LCD_Currentfonts; -/* Global variables to set the written text color */ -static __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF; -static __IO uint32_t LCDType = LCD_ILI9320; -/** - * @} - */ - -/** @defgroup STM32100B_EVAL_LCD_Private_Function_Prototypes - * @{ - */ -#ifndef USE_Delay -static void delay(vu32 nCount); -#endif /* USE_Delay*/ - -static void LCD_WriteRegHX8312(uint8_t LCD_Reg, uint8_t LCD_RegValue); -static void LCD_WriteRegILI9320(uint8_t LCD_Reg, uint16_t LCD_RegValue); -static void PutPixel(int16_t x, int16_t y); -static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed); - -/** - * @} - */ - -/** @defgroup STM32100B_EVAL_LCD_Private_Functions - * @{ - */ - -/** - * @brief DeInitializes the LCD. - * @param None - * @retval None - */ -void LCD_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< LCD Display Off */ - LCD_DisplayOff(); - - /*!< LCD_SPI disable */ - SPI_Cmd(LCD_SPI, DISABLE); - - /*!< LCD_SPI DeInit */ - SPI_I2S_DeInit(LCD_SPI); - - /*!< Disable SPI clock */ - RCC_APB1PeriphClockCmd(LCD_SPI_CLK, DISABLE); - - /* Configure NCS in Output Push-Pull mode */ - GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure); - - /* Configure NWR(RNW), RS in Output Push-Pull mode */ - GPIO_InitStructure.GPIO_Pin = LCD_RS_PIN; - GPIO_Init(LCD_RS_GPIO_PORT, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = LCD_NWR_PIN; - GPIO_Init(LCD_NWR_GPIO_PORT, &GPIO_InitStructure); - - /* Configure SPI pins: SCK, MISO and MOSI */ - GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN; - GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN; - GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN; - GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @brief Setups the LCD. - * @param None - * @retval None - */ -void LCD_Setup(void) -{ -/* Configure the LCD Control pins --------------------------------------------*/ - LCD_CtrlLinesConfig(); - -/* Configure the LCD_SPI interface ----------------------------------------------*/ - LCD_SPIConfig(); - - if(LCDType == LCD_ILI9320) - { - _delay_(5); /* Delay 50 ms */ - /* Start Initial Sequence ------------------------------------------------*/ - LCD_WriteReg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */ - LCD_WriteReg(LCD_REG_0, 0x0001); /* Start internal OSC. */ - LCD_WriteReg(LCD_REG_1, 0x0100); /* set SS and SM bit */ - LCD_WriteReg(LCD_REG_2, 0x0700); /* set 1 line inversion */ - LCD_WriteReg(LCD_REG_3, 0x1030); /* set GRAM write direction and BGR=1. */ - LCD_WriteReg(LCD_REG_4, 0x0000); /* Resize register */ - LCD_WriteReg(LCD_REG_8, 0x0202); /* set the back porch and front porch */ - LCD_WriteReg(LCD_REG_9, 0x0000); /* set non-display area refresh cycle ISC[3:0] */ - LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */ - LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */ - LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */ - LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */ - /* Power On sequence -----------------------------------------------------*/ - LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ - _delay_(20); /* Dis-charge capacitor power voltage (200ms) */ - LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ - LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ - LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */ - /* Adjust the Gamma Curve ------------------------------------------------*/ - LCD_WriteReg(LCD_REG_48, 0x0006); - LCD_WriteReg(LCD_REG_49, 0x0101); - LCD_WriteReg(LCD_REG_50, 0x0003); - LCD_WriteReg(LCD_REG_53, 0x0106); - LCD_WriteReg(LCD_REG_54, 0x0b02); - LCD_WriteReg(LCD_REG_55, 0x0302); - LCD_WriteReg(LCD_REG_56, 0x0707); - LCD_WriteReg(LCD_REG_57, 0x0007); - LCD_WriteReg(LCD_REG_60, 0x0600); - LCD_WriteReg(LCD_REG_61, 0x020b); - - /* Set GRAM area ---------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ - LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */ - LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ - LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */ - LCD_WriteReg(LCD_REG_96, 0x2700); /* Gate Scan Line */ - LCD_WriteReg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ - LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */ - /* Partial Display Control -----------------------------------------------*/ - LCD_WriteReg(LCD_REG_128, 0x0000); - LCD_WriteReg(LCD_REG_129, 0x0000); - LCD_WriteReg(LCD_REG_130, 0x0000); - LCD_WriteReg(LCD_REG_131, 0x0000); - LCD_WriteReg(LCD_REG_132, 0x0000); - LCD_WriteReg(LCD_REG_133, 0x0000); - /* Panel Control ---------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_144, 0x0010); - LCD_WriteReg(LCD_REG_146, 0x0000); - LCD_WriteReg(LCD_REG_147, 0x0003); - LCD_WriteReg(LCD_REG_149, 0x0110); - LCD_WriteReg(LCD_REG_151, 0x0000); - LCD_WriteReg(LCD_REG_152, 0x0000); - /* Set GRAM write direction and BGR = 1 */ - /* I/D=01 (Horizontal : increment, Vertical : decrement) */ - /* AM=1 (address is updated in vertical writing direction) */ - LCD_WriteReg(LCD_REG_3, 0x1018); - LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */ - } - else if(LCDType == LCD_SPFD5408) - { - /* Start Initial Sequence --------------------------------------------------*/ - LCD_WriteReg(LCD_REG_227, 0x3008); /* Set internal timing */ - LCD_WriteReg(LCD_REG_231, 0x0012); /* Set internal timing */ - LCD_WriteReg(LCD_REG_239, 0x1231); /* Set internal timing */ - LCD_WriteReg(LCD_REG_1, 0x0100); /* Set SS and SM bit */ - LCD_WriteReg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ - LCD_WriteReg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ - LCD_WriteReg(LCD_REG_4, 0x0000); /* Resize register */ - LCD_WriteReg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ - LCD_WriteReg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ - LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */ - LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */ - LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */ - LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */ - /* Power On sequence -------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ - _delay_(20); /* Dis-charge capacitor power voltage (200ms) */ - LCD_WriteReg(LCD_REG_17, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_16, 0x12B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_18, 0x01BD); /* External reference voltage= Vci */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_19, 0x1400); /* VDV[4:0] for VCOM amplitude */ - LCD_WriteReg(LCD_REG_41, 0x000E); /* VCM[4:0] for VCOMH */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ - LCD_WriteReg(LCD_REG_33, 0x013F); /* GRAM Vertical Address */ - /* Adjust the Gamma Curve --------------------------------------------------*/ - LCD_WriteReg(LCD_REG_48, 0x0007); - LCD_WriteReg(LCD_REG_49, 0x0302); - LCD_WriteReg(LCD_REG_50, 0x0105); - LCD_WriteReg(LCD_REG_53, 0x0206); - LCD_WriteReg(LCD_REG_54, 0x0808); - LCD_WriteReg(LCD_REG_55, 0x0206); - LCD_WriteReg(LCD_REG_56, 0x0504); - LCD_WriteReg(LCD_REG_57, 0x0007); - LCD_WriteReg(LCD_REG_60, 0x0105); - LCD_WriteReg(LCD_REG_61, 0x0808); - /* Set GRAM area -----------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ - LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */ - LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ - LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */ - LCD_WriteReg(LCD_REG_96, 0xA700); /* Gate Scan Line */ - LCD_WriteReg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ - LCD_WriteReg(LCD_REG_106, 0x0000); /* Set scrolling line */ - /* Partial Display Control -------------------------------------------------*/ - LCD_WriteReg(LCD_REG_128, 0x0000); - LCD_WriteReg(LCD_REG_129, 0x0000); - LCD_WriteReg(LCD_REG_130, 0x0000); - LCD_WriteReg(LCD_REG_131, 0x0000); - LCD_WriteReg(LCD_REG_132, 0x0000); - LCD_WriteReg(LCD_REG_133, 0x0000); - /* Panel Control -----------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_144, 0x0010); - LCD_WriteReg(LCD_REG_146, 0x0000); - LCD_WriteReg(LCD_REG_147, 0x0003); - LCD_WriteReg(LCD_REG_149, 0x0110); - LCD_WriteReg(LCD_REG_151, 0x0000); - LCD_WriteReg(LCD_REG_152, 0x0000); - /* Set GRAM write direction and BGR = 1 - I/D=01 (Horizontal : increment, Vertical : decrement) - AM=1 (address is updated in vertical writing direction) */ - LCD_WriteReg(LCD_REG_3, 0x1018); - LCD_WriteReg(LCD_REG_7, 0x0112); /* 262K color and display ON */ - } - else if(LCDType == LCD_HX8312) - { - /* Enable the LCD Oscillator ---------------------------------------------*/ - LCD_WriteReg(LCD_REG_1, 0x10); - LCD_WriteReg(LCD_REG_0, 0xA0); - LCD_WriteReg(LCD_REG_3, 0x01); - _delay_(1); /* Delay 10 ms */ - LCD_WriteReg(LCD_REG_3, 0x00); - LCD_WriteReg(LCD_REG_43, 0x04); - - LCD_WriteReg(LCD_REG_40, 0x18); - LCD_WriteReg(LCD_REG_26, 0x05); - LCD_WriteReg(LCD_REG_37, 0x05); - LCD_WriteReg(LCD_REG_25, 0x00); - - /* LCD Power On ----------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_28, 0x73); - LCD_WriteReg(LCD_REG_36, 0x74); - LCD_WriteReg(LCD_REG_30, 0x01); - LCD_WriteReg(LCD_REG_24, 0xC1); - _delay_(1); /* Delay 10 ms */ - LCD_WriteReg(LCD_REG_24, 0xE1); - LCD_WriteReg(LCD_REG_24, 0xF1); - _delay_(6); /* Delay 60 ms */ - LCD_WriteReg(LCD_REG_24, 0xF5); - _delay_(6); /* Delay 60 ms */ - LCD_WriteReg(LCD_REG_27, 0x09); - _delay_(1); /* Delay 10 ms */ - LCD_WriteReg(LCD_REG_31, 0x11); - LCD_WriteReg(LCD_REG_32, 0x0E); - LCD_WriteReg(LCD_REG_30, 0x81); - _delay_(1); /* Delay 10 ms */ - - /* Chip Set --------------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_157, 0x00); - LCD_WriteReg(LCD_REG_192, 0x00); - - LCD_WriteReg(LCD_REG_14, 0x00); - LCD_WriteReg(LCD_REG_15, 0x00); - LCD_WriteReg(LCD_REG_16, 0x00); - LCD_WriteReg(LCD_REG_17, 0x00); - LCD_WriteReg(LCD_REG_18, 0x00); - LCD_WriteReg(LCD_REG_19, 0x00); - LCD_WriteReg(LCD_REG_20, 0x00); - LCD_WriteReg(LCD_REG_21, 0x00); - LCD_WriteReg(LCD_REG_22, 0x00); - LCD_WriteReg(LCD_REG_23, 0x00); - - LCD_WriteReg(LCD_REG_52, 0x01); - LCD_WriteReg(LCD_REG_53, 0x00); - LCD_WriteReg(LCD_REG_75, 0x00); - LCD_WriteReg(LCD_REG_76, 0x00); - LCD_WriteReg(LCD_REG_78, 0x00); - LCD_WriteReg(LCD_REG_79, 0x00); - LCD_WriteReg(LCD_REG_80, 0x00); - - LCD_WriteReg(LCD_REG_60, 0x00); - LCD_WriteReg(LCD_REG_61, 0x00); - LCD_WriteReg(LCD_REG_62, 0x01); - LCD_WriteReg(LCD_REG_63, 0x3F); - LCD_WriteReg(LCD_REG_64, 0x02); - LCD_WriteReg(LCD_REG_65, 0x02); - LCD_WriteReg(LCD_REG_66, 0x00); - LCD_WriteReg(LCD_REG_67, 0x00); - LCD_WriteReg(LCD_REG_68, 0x00); - LCD_WriteReg(LCD_REG_69, 0x00); - LCD_WriteReg(LCD_REG_70, 0xEF); - LCD_WriteReg(LCD_REG_71, 0x00); - LCD_WriteReg(LCD_REG_72, 0x00); - LCD_WriteReg(LCD_REG_73, 0x01); - LCD_WriteReg(LCD_REG_74, 0x3F); - - LCD_WriteReg(LCD_REG_29, 0x08); /* R29:Gate scan direction setting */ - - LCD_WriteReg(LCD_REG_134, 0x00); - LCD_WriteReg(LCD_REG_135, 0x30); - LCD_WriteReg(LCD_REG_136, 0x02); - LCD_WriteReg(LCD_REG_137, 0x05); - - LCD_WriteReg(LCD_REG_141, 0x01); /* R141:Register set-up mode for one line clock */ - LCD_WriteReg(LCD_REG_139, 0x20); /* R139:One line SYSCLK number in one-line */ - LCD_WriteReg(LCD_REG_51, 0x01); /* R51:N line inversion setting */ - LCD_WriteReg(LCD_REG_55, 0x01); /* R55:Scanning method setting */ - LCD_WriteReg(LCD_REG_118, 0x00); - - /* Gamma Set -------------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_143, 0x10); - LCD_WriteReg(LCD_REG_144, 0x67); - LCD_WriteReg(LCD_REG_145, 0x07); - LCD_WriteReg(LCD_REG_146, 0x65); - LCD_WriteReg(LCD_REG_147, 0x07); - LCD_WriteReg(LCD_REG_148, 0x01); - LCD_WriteReg(LCD_REG_149, 0x76); - LCD_WriteReg(LCD_REG_150, 0x56); - LCD_WriteReg(LCD_REG_151, 0x00); - LCD_WriteReg(LCD_REG_152, 0x06); - LCD_WriteReg(LCD_REG_153, 0x03); - LCD_WriteReg(LCD_REG_154, 0x00); - - /* Display On ------------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_1, 0x50); - LCD_WriteReg(LCD_REG_5, 0x04); - LCD_WriteReg(LCD_REG_0, 0x80); - LCD_WriteReg(LCD_REG_59, 0x01); - _delay_(4); /* Delay 40 ms */ - LCD_WriteReg(LCD_REG_0, 0x20); - } -} - - -/** - * @brief Initializes the LCD. - * @param None - * @retval None - */ -void STM32100B_LCD_Init(void) -{ - /* Setups the LCD */ - LCD_Setup(); - /* Try to read new LCD controller ID 0x9320 */ - if (LCD_ReadReg(LCD_REG_0) == LCD_ILI9320) - { - LCDType = LCD_ILI9320; - } - else - { - LCDType = LCD_SPFD5408; - /* Setups the LCD */ - LCD_Setup(); - /* Try to read new LCD controller ID 0x5408 */ - if (LCD_ReadReg(LCD_REG_0) != LCD_SPFD5408) - { - LCDType = LCD_HX8312; - /* Setups the LCD */ - LCD_Setup(); - } - } - LCD_SetFont(&LCD_DEFAULT_FONT); -} - -/** - * @brief Sets the LCD Text and Background colors. - * @param _TextColor: specifies the Text Color. - * @param _BackColor: specifies the Background Color. - * @retval None - */ -void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor) -{ - TextColor = _TextColor; - BackColor = _BackColor; -} - -/** - * @brief Gets the LCD Text and Background colors. - * @param _TextColor: pointer to the variable that will contain the Text - Color. - * @param _BackColor: pointer to the variable that will contain the Background - Color. - * @retval None - */ -void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor) -{ - *_TextColor = TextColor; *_BackColor = BackColor; -} - -/** - * @brief Sets the Text color. - * @param Color: specifies the Text color code RGB(5-6-5). - * @retval None - */ -void LCD_SetTextColor(__IO uint16_t Color) -{ - TextColor = Color; -} - - -/** - * @brief Sets the Background color. - * @param Color: specifies the Background color code RGB(5-6-5). - * @retval None - */ -void LCD_SetBackColor(__IO uint16_t Color) -{ - BackColor = Color; -} - -/** - * @brief Sets the Text Font. - * @param fonts: specifies the font to be used. - * @retval None - */ -void LCD_SetFont(sFONT *fonts) -{ - LCD_Currentfonts = fonts; -} - -/** - * @brief Gets the Text Font. - * @param None. - * @retval the used font. - */ -sFONT *LCD_GetFont(void) -{ - return LCD_Currentfonts; -} - -/** - * @brief Clears the selected line. - * @param Line: the Line to be cleared. - * This parameter can be one of the following values: - * @arg Linex: where x can be 0..n - * @retval None - */ -void LCD_ClearLine(uint8_t Line) -{ - uint16_t refcolumn = LCD_PIXEL_WIDTH - 1; - /* Send the string character by character on lCD */ - while (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width) - { - /* Display one character on LCD */ - LCD_DisplayChar(Line, refcolumn, ' '); - /* Decrement the column position by 16 */ - refcolumn -= LCD_Currentfonts->Width; - } -} - - -/** - * @brief Clears the hole LCD. - * @param Color: the color of the background. - * @retval None - */ -void LCD_Clear(uint16_t Color) -{ - uint32_t index = 0; - - LCD_SetCursor(0x00, 0x013F); - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - } - for(index = 0; index < 76800; index++) - { - LCD_WriteRAM(Color); - } - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); - } -} - - -/** - * @brief Sets the cursor position. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @retval None - */ -void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos) -{ - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteReg(LCD_REG_32, Xpos); - LCD_WriteReg(LCD_REG_33, Ypos); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteReg(LCD_REG_66, Xpos); - LCD_WriteReg(LCD_REG_67, ((Ypos & 0x100)>> 8)); - LCD_WriteReg(LCD_REG_68, (Ypos & 0xFF)); - } -} - - -/** - * @brief Draws a character on LCD. - * @param Xpos: the Line where to display the character shape. - * @param Ypos: start column address. - * @param c: pointer to the character data. - * @retval None - */ -void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c) -{ - uint32_t index = 0, i = 0; - uint8_t Xaddress = 0; - - Xaddress = Xpos; - - LCD_SetCursor(Xaddress, Ypos); - - for(index = 0; index < LCD_Currentfonts->Height; index++) - { - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - } - for(i = 0; i < LCD_Currentfonts->Width; i++) - { - if((((c[index] & ((0x80 << ((LCD_Currentfonts->Width / 12 ) * 8 ) ) >> i)) == 0x00) &&(LCD_Currentfonts->Width <= 12))|| - (((c[index] & (0x1 << i)) == 0x00)&&(LCD_Currentfonts->Width > 12 ))) - - { - LCD_WriteRAM(BackColor); - } - else - { - LCD_WriteRAM(TextColor); - } - } - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); - } - Xaddress++; - LCD_SetCursor(Xaddress, Ypos); - } -} - - -/** - * @brief Displays one character (16dots width, 24dots height). - * @param Line: the Line where to display the character shape . - * This parameter can be one of the following values: - * @arg Linex: where x can be 0..9 - * @param Column: start column address. - * @param Ascii: character ascii code, must be between 0x20 and 0x7E. - * @retval None - */ -void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii) -{ - Ascii -= 32; - LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]); -} - - -/** - * @brief Displays a maximum of 20 char on the LCD. - * @param Line: the Line where to display the character shape . - * This parameter can be one of the following values: - * @arg Linex: where x can be 0..9 - * @param *ptr: pointer to string to display on LCD. - * @retval None - */ -void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr) -{ - uint16_t refcolumn = LCD_PIXEL_WIDTH - 1; - - /* Send the string character by character on lCD */ - while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width)) - { - /* Display one character on LCD */ - LCD_DisplayChar(Line, refcolumn, *ptr); - /* Decrement the column position by 16 */ - refcolumn -= LCD_Currentfonts->Width; - /* Point on the next character */ - ptr++; - } -} - - -/** - * @brief Sets a display window - * @param Xpos: specifies the X buttom left position. - * @param Ypos: specifies the Y buttom left position. - * @param Height: display window height. - * @param Width: display window width. - * @retval None - */ -void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width) -{ - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - /* Horizontal GRAM Start Address */ - if(Xpos >= Height) - { - LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1)); - } - else - { - LCD_WriteReg(LCD_REG_80, 0); - } - /* Horizontal GRAM End Address */ - LCD_WriteReg(LCD_REG_81, Xpos); - /* Vertical GRAM Start Address */ - if(Ypos >= Width) - { - LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1)); - } - else - { - LCD_WriteReg(LCD_REG_82, 0); - } - /* Vertical GRAM End Address */ - LCD_WriteReg(LCD_REG_83, Ypos); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteReg(LCD_REG_1, 0xD0); - LCD_WriteReg(LCD_REG_5, 0x14); - - LCD_WriteReg(LCD_REG_69, (Xpos - Height + 1)); - LCD_WriteReg(LCD_REG_70, Xpos); - - LCD_WriteReg(LCD_REG_71, (((Ypos - Width + 1) & 0x100)>> 8)); - LCD_WriteReg(LCD_REG_72, ((Ypos - Width + 1) & 0xFF)); - LCD_WriteReg(LCD_REG_73, ((Ypos & 0x100)>> 8)); - LCD_WriteReg(LCD_REG_74, (Ypos & 0xFF)); - } - LCD_SetCursor(Xpos, Ypos); -} - - -/** - * @brief Disables LCD Window mode. - * @param None - * @retval None - */ -void LCD_WindowModeDisable(void) -{ - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_SetDisplayWindow(239, 0x13F, 240, 320); - LCD_WriteReg(LCD_REG_3, 0x1018); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteReg(LCD_REG_1, 0x50); - LCD_WriteReg(LCD_REG_5, 0x04); - } - -} - -/** - * @brief Displays a line. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Length: line length. - * @param Direction: line direction. - * This parameter can be one of the following values: Vertical or Horizontal. - * @retval None - */ -void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction) -{ - uint32_t i = 0; - - LCD_SetCursor(Xpos, Ypos); - if(Direction == LCD_DIR_HORIZONTAL) - { - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - } - for(i = 0; i < Length; i++) - { - LCD_WriteRAM(TextColor); - } - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); - } - } - else - { - for(i = 0; i < Length; i++) - { - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAMWord(TextColor); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteRAM(TextColor); - } - Xpos++; - LCD_SetCursor(Xpos, Ypos); - } - } -} - - -/** - * @brief Displays a rectangle. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Height: display rectangle height. - * @param Width: display rectangle width. - * @retval None - */ -void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width) -{ - LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL); - LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL); - - LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL); - LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL); -} - - -/** - * @brief Displays a circle. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Radius - * @retval None - */ -void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius) -{ - int32_t D;/* Decision Variable */ - uint32_t CurX;/* Current X Value */ - uint32_t CurY;/* Current Y Value */ - - D = 3 - (Radius << 1); - CurX = 0; - CurY = Radius; - - while (CurX <= CurY) - { - LCD_SetCursor(Xpos + CurX, Ypos + CurY); - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAMWord(TextColor); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteRAM(TextColor); - } - LCD_SetCursor(Xpos + CurX, Ypos - CurY); - - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAMWord(TextColor); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteRAM(TextColor); - } - LCD_SetCursor(Xpos - CurX, Ypos + CurY); - - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAMWord(TextColor); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteRAM(TextColor); - } - LCD_SetCursor(Xpos - CurX, Ypos - CurY); - - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAMWord(TextColor); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteRAM(TextColor); - } - LCD_SetCursor(Xpos + CurY, Ypos + CurX); - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAMWord(TextColor); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteRAM(TextColor); - } - LCD_SetCursor(Xpos + CurY, Ypos - CurX); - - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAMWord(TextColor); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteRAM(TextColor); - } - LCD_SetCursor(Xpos - CurY, Ypos + CurX); - - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAMWord(TextColor); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteRAM(TextColor); - } - LCD_SetCursor(Xpos - CurY, Ypos - CurX); - - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAMWord(TextColor); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteRAM(TextColor); - } - if (D < 0) - { - D += (CurX << 2) + 6; - } - else - { - D += ((CurX - CurY) << 2) + 10; - CurY--; - } - CurX++; - } -} - - -/** - * @brief Displays a monocolor picture. - * @param Pict: pointer to the picture array. - * @retval None - */ -void LCD_DrawMonoPict(const uint32_t *Pict) -{ - uint32_t index = 0, i = 0; - LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1)); - - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - } - - for(index = 0; index < 2400; index++) - { - for(i = 0; i < 32; i++) - { - if((Pict[index] & (1 << i)) == 0x00) - { - LCD_WriteRAM(BackColor); - } - else - { - LCD_WriteRAM(TextColor); - } - } - } - - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); - } -} - -#ifdef USE_LCD_DrawBMP -/** - * @brief Displays a bitmap picture loaded in the SPI Flash. - * @param BmpAddress: Bmp picture address in the SPI Flash. - * @retval None - */ -void LCD_DrawBMP(uint32_t BmpAddress) -{ - uint32_t i = 0, size = 0; - /* Read bitmap size */ - sFLASH_ReadBuffer((uint8_t*)&size, BmpAddress + 2, 4); - /* get bitmap data address offset */ - sFLASH_ReadBuffer((uint8_t*)&i, BmpAddress + 10, 4); - - size = (size - i)/2; - sFLASH_StartReadSequence(BmpAddress + i); - /* Disable LCD_SPI */ - SPI_Cmd(LCD_SPI, DISABLE); - /* SPI in 16-bit mode */ - SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_16b); - /* Enable LCD_SPI */ - SPI_Cmd(LCD_SPI, ENABLE); - - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - /* Set GRAM write direction and BGR = 1 */ - /* I/D=00 (Horizontal : decrement, Vertical : decrement) */ - /* AM=1 (address is updated in vertical writing direction) */ - LCD_WriteReg(LCD_REG_3, 0x1008); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - } - - /* Read bitmap data from SPI Flash and send them to LCD */ - for(i = 0; i < size; i++) - { - LCD_WriteRAM(__REV16(sFLASH_SendHalfWord(0xA5A5))); - } - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); - } - - /* Deselect the FLASH: Chip Select high */ - sFLASH_CS_HIGH(); - /* Disable LCD_SPI */ - SPI_Cmd(LCD_SPI, DISABLE); - /* SPI in 8-bit mode */ - SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_8b); - /* Enable LCD_SPI */ - SPI_Cmd(LCD_SPI, ENABLE); - - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - /* Set GRAM write direction and BGR = 1 */ - /* I/D = 01 (Horizontal : increment, Vertical : decrement) */ - /* AM = 1 (address is updated in vertical writing direction) */ - LCD_WriteReg(LCD_REG_3, 0x1018); - } -} -#endif /* USE_LCD_DrawBMP */ - -/** - * @brief Displays a full rectangle. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Height: rectangle height. - * @param Width: rectangle width. - * @retval None - */ -void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height) -{ - LCD_SetTextColor(TextColor); - - LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL); - LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL); - - LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL); - LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL); - - Width -= 2; - Height--; - Ypos--; - - LCD_SetTextColor(BackColor); - - while(Height--) - { - LCD_DrawLine(++Xpos, Ypos, Width, LCD_DIR_HORIZONTAL); - } - - LCD_SetTextColor(TextColor); -} - -/** - * @brief Displays a full circle. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Radius - * @retval None - */ -void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius) -{ - int32_t D; /* Decision Variable */ - uint32_t CurX;/* Current X Value */ - uint32_t CurY;/* Current Y Value */ - - D = 3 - (Radius << 1); - - CurX = 0; - CurY = Radius; - - LCD_SetTextColor(BackColor); - - while (CurX <= CurY) - { - if(CurY > 0) - { - LCD_DrawLine(Xpos - CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL); - LCD_DrawLine(Xpos + CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL); - } - - if(CurX > 0) - { - LCD_DrawLine(Xpos - CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL); - LCD_DrawLine(Xpos + CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL); - } - if (D < 0) - { - D += (CurX << 2) + 6; - } - else - { - D += ((CurX - CurY) << 2) + 10; - CurY--; - } - CurX++; - } - - LCD_SetTextColor(TextColor); - LCD_DrawCircle(Xpos, Ypos, Radius); -} - -/** - * @brief Displays an uni line (between two points). - * @param x1: specifies the point 1 x position. - * @param y1: specifies the point 1 y position. - * @param x2: specifies the point 2 x position. - * @param y2: specifies the point 2 y position. - * @retval None - */ -void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2) -{ - int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0, - yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0, - curpixel = 0; - - deltax = ABS(x2 - x1); /* The difference between the x's */ - deltay = ABS(y2 - y1); /* The difference between the y's */ - x = x1; /* Start x off at the first pixel */ - y = y1; /* Start y off at the first pixel */ - - if (x2 >= x1) /* The x-values are increasing */ - { - xinc1 = 1; - xinc2 = 1; - } - else /* The x-values are decreasing */ - { - xinc1 = -1; - xinc2 = -1; - } - - if (y2 >= y1) /* The y-values are increasing */ - { - yinc1 = 1; - yinc2 = 1; - } - else /* The y-values are decreasing */ - { - yinc1 = -1; - yinc2 = -1; - } - - if (deltax >= deltay) /* There is at least one x-value for every y-value */ - { - xinc1 = 0; /* Don't change the x when numerator >= denominator */ - yinc2 = 0; /* Don't change the y for every iteration */ - den = deltax; - num = deltax / 2; - numadd = deltay; - numpixels = deltax; /* There are more x-values than y-values */ - } - else /* There is at least one y-value for every x-value */ - { - xinc2 = 0; /* Don't change the x for every iteration */ - yinc1 = 0; /* Don't change the y when numerator >= denominator */ - den = deltay; - num = deltay / 2; - numadd = deltax; - numpixels = deltay; /* There are more y-values than x-values */ - } - - for (curpixel = 0; curpixel <= numpixels; curpixel++) - { - PutPixel(x, y); /* Draw the current pixel */ - num += numadd; /* Increase the numerator by the top of the fraction */ - if (num >= den) /* Check if numerator >= denominator */ - { - num -= den; /* Calculate the new numerator value */ - x += xinc1; /* Change the x as appropriate */ - y += yinc1; /* Change the y as appropriate */ - } - x += xinc2; /* Change the x as appropriate */ - y += yinc2; /* Change the y as appropriate */ - } -} - -/** - * @brief Displays an polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_PolyLine(pPoint Points, uint16_t PointCount) -{ - int16_t X = 0, Y = 0; - - if(PointCount < 2) - { - return; - } - - while(--PointCount) - { - X = Points->X; - Y = Points->Y; - Points++; - LCD_DrawUniLine(X, Y, Points->X, Points->Y); - } -} - -/** - * @brief Displays an relative polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @param Closed: specifies if the draw is closed or not. - * 1: closed, 0 : not closed. - * @retval None - */ -static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed) -{ - int16_t X = 0, Y = 0; - pPoint First = Points; - - if(PointCount < 2) - { - return; - } - X = Points->X; - Y = Points->Y; - while(--PointCount) - { - Points++; - LCD_DrawUniLine(X, Y, X + Points->X, Y + Points->Y); - X = X + Points->X; - Y = Y + Points->Y; - } - if(Closed) - { - LCD_DrawUniLine(First->X, First->Y, X, Y); - } -} - -/** - * @brief Displays a closed polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount) -{ - LCD_PolyLine(Points, PointCount); - LCD_DrawUniLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y); -} - -/** - * @brief Displays a relative polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount) -{ - LCD_PolyLineRelativeClosed(Points, PointCount, 0); -} - -/** - * @brief Displays a closed relative polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount) -{ - LCD_PolyLineRelativeClosed(Points, PointCount, 1); -} - - -/** - * @brief Displays a full polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_FillPolyLine(pPoint Points, uint16_t PointCount) -{ - /* public-domain code by Darel Rex Finley, 2007 */ - uint16_t nodes = 0, nodeX[MAX_POLY_CORNERS], pixelX = 0, pixelY = 0, i = 0, - j = 0, swap = 0; - uint16_t IMAGE_LEFT = 0, IMAGE_RIGHT = 0, IMAGE_TOP = 0, IMAGE_BOTTOM = 0; - - IMAGE_LEFT = IMAGE_RIGHT = Points->X; - IMAGE_TOP= IMAGE_BOTTOM = Points->Y; - - for(i = 1; i < PointCount; i++) - { - pixelX = POLY_X(i); - if(pixelX < IMAGE_LEFT) - { - IMAGE_LEFT = pixelX; - } - if(pixelX > IMAGE_RIGHT) - { - IMAGE_RIGHT = pixelX; - } - - pixelY = POLY_Y(i); - if(pixelY < IMAGE_TOP) - { - IMAGE_TOP = pixelY; - } - if(pixelY > IMAGE_BOTTOM) - { - IMAGE_BOTTOM = pixelY; - } - } - - LCD_SetTextColor(BackColor); - - /* Loop through the rows of the image. */ - for (pixelY = IMAGE_TOP; pixelY < IMAGE_BOTTOM; pixelY++) - { - /* Build a list of nodes. */ - nodes = 0; j = PointCount-1; - - for (i = 0; i < PointCount; i++) - { - if (POLY_Y(i)<(double) pixelY && POLY_Y(j)>=(double) pixelY || POLY_Y(j)<(double) pixelY && POLY_Y(i)>=(double) pixelY) - { - nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i))); - } - j = i; - } - - /* Sort the nodes, via a simple "Bubble" sort. */ - i = 0; - while (i < nodes-1) - { - if (nodeX[i]>nodeX[i+1]) - { - swap = nodeX[i]; - nodeX[i] = nodeX[i+1]; - nodeX[i+1] = swap; - if(i) - { - i--; - } - } - else - { - i++; - } - } - - /* Fill the pixels between node pairs. */ - for (i = 0; i < nodes; i+=2) - { - if(nodeX[i] >= IMAGE_RIGHT) - { - break; - } - if(nodeX[i+1] > IMAGE_LEFT) - { - if (nodeX[i] < IMAGE_LEFT) - { - nodeX[i]=IMAGE_LEFT; - } - if(nodeX[i+1] > IMAGE_RIGHT) - { - nodeX[i+1] = IMAGE_RIGHT; - } - LCD_SetTextColor(BackColor); - LCD_DrawLine(pixelY, nodeX[i+1], nodeX[i+1] - nodeX[i], LCD_DIR_HORIZONTAL); - LCD_SetTextColor(TextColor); - PutPixel(pixelY, nodeX[i+1]); - PutPixel(pixelY, nodeX[i]); - /* for (j=nodeX[i]; j>8); - - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET) - { - } - - SPI_I2S_SendData(LCD_SPI, (LCD_RegValue & 0xFF)); - - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET) - { - } - - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); -} - - -/** - * @brief Reads the selected LCD Register. - * @param LCD_Reg: address of the selected register. - * @retval LCD Register Value. - */ -uint16_t LCD_ReadReg(uint8_t LCD_Reg) -{ - uint16_t tmp = 0; - uint8_t i = 0; - - /* LCD_SPI prescaler: 4 */ - LCD_SPI->CR1 &= 0xFFC7; - LCD_SPI->CR1 |= 0x0008; - /* Write 16-bit Index (then Read Reg) */ - LCD_WriteRegIndex(LCD_Reg); - /* Read 16-bit Reg */ - /* Reset LCD control line(/CS) and Send Start-Byte */ - LCD_nCS_StartByte(START_BYTE | LCD_READ_REG); - - for(i = 0; i < 5; i++) - { - SPI_I2S_SendData(LCD_SPI, 0xFF); - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET) - { - } - /* One byte of invalid dummy data read after the start byte */ - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET) - { - } - SPI_I2S_ReceiveData(LCD_SPI); - } - - SPI_I2S_SendData(LCD_SPI, 0xFF); - - /* Read upper byte */ - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET) - { - } - - /* Read lower byte */ - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET) - { - } - tmp = SPI_I2S_ReceiveData(LCD_SPI); - - - SPI_I2S_SendData(LCD_SPI, 0xFF); - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET) - { - } - - /* Read lower byte */ - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET) - { - } - - tmp = ((tmp & 0xFF) << 8) | SPI_I2S_ReceiveData(LCD_SPI); - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); - - /* LCD_SPI prescaler: 2 */ - LCD_SPI->CR1 &= 0xFFC7; - - return tmp; -} - - -/** - * @brief Prepare to write to the LCD RAM. - * @param None - * @retval None - */ -void LCD_WriteRAM_Prepare(void) -{ - LCD_WriteRegIndex(LCD_REG_34); /* Select GRAM Reg */ - - /* Reset LCD control line(/CS) and Send Start-Byte */ - LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG); -} - - -/** - * @brief Writes 1 word to the LCD RAM. - * @param RGB_Code: the pixel color in RGB mode (5-6-5). - * @retval None - */ -void LCD_WriteRAMWord(uint16_t RGB_Code) -{ - - LCD_WriteRAM_Prepare(); - - LCD_WriteRAM(RGB_Code); - - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); -} - - -/** - * @brief Writes to the selected LCD HX8312 register. - * @param LCD_Reg: address of the selected register. - * @param LCD_RegValue: value to write to the selected register. - * @retval None - */ -static void LCD_WriteRegHX8312(uint8_t LCD_Reg, uint8_t LCD_RegValue) -{ - uint16_t tmp = 0; - - LCD_CtrlLinesWrite(LCD_NWR_GPIO_PORT, LCD_NWR_PIN, Bit_RESET); - LCD_CtrlLinesWrite(LCD_RS_GPIO_PORT, LCD_RS_PIN, Bit_RESET); - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET); - - tmp = LCD_Reg << 8; - tmp |= LCD_RegValue; - - SPI_I2S_SendData(LCD_SPI, tmp); - - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET) - { - } - - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); -} - - -/** - * @brief Writes to the selected LCD register. - * @param LCD_Reg: address of the selected register. - * @param LCD_RegValue: value to write to the selected register. - * @retval None - */ -void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue) -{ - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRegILI9320(LCD_Reg, LCD_RegValue); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteRegHX8312(LCD_Reg, ((uint8_t)LCD_RegValue)); - } -} - - -/** - * @brief Writes to the LCD RAM. - * @param RGB_Code: the pixel color in RGB mode (5-6-5). - * @retval None - */ -void LCD_WriteRAM(uint16_t RGB_Code) -{ - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - SPI_I2S_SendData(LCD_SPI, RGB_Code >> 8); - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET) - { - } - SPI_I2S_SendData(LCD_SPI, RGB_Code & 0xFF); - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET) - { - } - } - - if(LCDType == LCD_HX8312) - { - LCD_CtrlLinesWrite(LCD_NWR_GPIO_PORT, LCD_NWR_PIN, Bit_RESET); - LCD_CtrlLinesWrite(LCD_RS_GPIO_PORT, LCD_RS_PIN, Bit_SET); - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET); - SPI_I2S_SendData(LCD_SPI, RGB_Code); - - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET) - { - } - - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); - } -} - - -/** - * @brief Power on the LCD. - * @param None - * @retval None - */ -void LCD_PowerOn(void) -{ - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - /* Power On sequence ---------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ - _delay_(20); /* Dis-charge capacitor power voltage (200ms) */ - LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ - _delay_(5); /* delay 50 ms */ - LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ - LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ - _delay_(5); /* delay 50 ms */ - LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */ - } - else if(LCDType == LCD_HX8312) - { - /* Power On Set */ - LCD_WriteReg(LCD_REG_28, 0x73); - LCD_WriteReg(LCD_REG_36, 0x74); - LCD_WriteReg(LCD_REG_30, 0x01); - LCD_WriteReg(LCD_REG_24, 0xC1); - _delay_(1); /* Delay 10 ms */ - LCD_WriteReg(LCD_REG_24, 0xE1); - LCD_WriteReg(LCD_REG_24, 0xF1); - _delay_(6); /* Delay 60 ms */ - LCD_WriteReg(LCD_REG_24, 0xF5); - _delay_(6); /* Delay 60 ms */ - LCD_WriteReg(LCD_REG_27, 0x09); - _delay_(1); /* Delay 10 ms */ - LCD_WriteReg(LCD_REG_31, 0x11); - LCD_WriteReg(LCD_REG_32, 0x0E); - LCD_WriteReg(LCD_REG_30, 0x81); - _delay_(1); /* Delay 10 ms */ - } -} - - -/** - * @brief Enables the Display. - * @param None - * @retval None - */ -void LCD_DisplayOn(void) -{ - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - /* Display On */ - LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */ - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteReg(LCD_REG_1, 0x50); - LCD_WriteReg(LCD_REG_5, 0x04); - /* Display On */ - LCD_WriteReg(LCD_REG_0, 0x80); - LCD_WriteReg(LCD_REG_59, 0x01); - _delay_(4); /* Delay 40 ms */ - LCD_WriteReg(LCD_REG_0, 0x20); - } -} - - -/** - * @brief Disables the Display. - * @param None - * @retval None - */ -void LCD_DisplayOff(void) -{ - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - /* Display Off */ - LCD_WriteReg(LCD_REG_7, 0x0); - } - else if(LCDType == LCD_HX8312) - { - /* Display Off */ - LCD_WriteReg(LCD_REG_0, 0xA0); - _delay_(4); /* Delay 40 ms */ - LCD_WriteReg(LCD_REG_59, 0x00); - } -} - - -/** - * @brief Configures LCD control lines in Output Push-Pull mode. - * @param None - * @retval None - */ -void LCD_CtrlLinesConfig(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable GPIO clock */ - RCC_APB2PeriphClockCmd(LCD_NCS_GPIO_CLK | LCD_NWR_GPIO_CLK | LCD_RS_GPIO_CLK, ENABLE); - - /* Configure NCS in Output Push-Pull mode */ - GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure); - - /* Configure NWR(RNW), RS in Output Push-Pull mode */ - GPIO_InitStructure.GPIO_Pin = LCD_RS_PIN; - GPIO_Init(LCD_RS_GPIO_PORT, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = LCD_NWR_PIN; - GPIO_Init(LCD_NWR_GPIO_PORT, &GPIO_InitStructure); - - LCD_CtrlLinesWrite(LCD_NWR_GPIO_PORT, LCD_NWR_PIN, Bit_SET); - LCD_CtrlLinesWrite(LCD_RS_GPIO_PORT, LCD_RS_PIN, Bit_SET); -} - - -/** - * @brief Sets or reset LCD control lines. - * @param GPIOx: where x can be B or D to select the GPIO peripheral. - * @param CtrlPins: the Control line. - * This parameter can be: - * @arg LCD_NCS_PIN: Chip Select pin - * @arg LCD_NWR_PIN: Read/Write Selection pin - * @arg LCD_RS_PIN: Register/RAM Selection pin - * @param BitVal: specifies the value to be written to the selected bit. - * This parameter can be: - * @arg Bit_RESET: to clear the port pin - * @arg Bit_SET: to set the port pin - * @retval None - */ -void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal) -{ - /* Set or Reset the control line */ - GPIO_WriteBit(GPIOx, CtrlPins, BitVal); -} - - -/** - * @brief Configures the LCD_SPI interface. - * @param None - * @retval None - */ -void LCD_SPIConfig(void) -{ - SPI_InitTypeDef SPI_InitStructure; - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable GPIO clock */ - RCC_APB2PeriphClockCmd(LCD_SPI_SCK_GPIO_CLK | LCD_SPI_MISO_GPIO_CLK | LCD_SPI_MOSI_GPIO_CLK, ENABLE); - - /* Enable SPI clock */ - RCC_APB1PeriphClockCmd(LCD_SPI_CLK, ENABLE); - - /* Configure SPI pins: SCK, MISO and MOSI */ - GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN; - GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN; - GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); - - SPI_I2S_DeInit(LCD_SPI); - - /* SPI Config */ - SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; - SPI_InitStructure.SPI_Mode = SPI_Mode_Master; - - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; - SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; - SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; - } - else if(LCDType == LCD_HX8312) - { - SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b; - SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; - SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; - } - SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; - SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; - - SPI_Init(LCD_SPI, &SPI_InitStructure); - - /* SPI enable */ - SPI_Cmd(LCD_SPI, ENABLE); -} - -/** - * @brief Displays a pixel. - * @param x: pixel x. - * @param y: pixel y. - * @retval None - */ -static void PutPixel(int16_t x, int16_t y) -{ - if(x < 0 || x > 239 || y < 0 || y > 319) - { - return; - } - LCD_DrawLine(x, y, 1, LCD_DIR_HORIZONTAL); -} - -#ifndef USE_Delay -/** - * @brief Inserts a delay time. - * @param nCount: specifies the delay time length. - * @retval None - */ -static void delay(vu32 nCount) -{ - vu32 index = 0; - for(index = (34000 * nCount); index != 0; index--) - { - } -} -#endif /* USE_Delay*/ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_lcd.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_lcd.h deleted file mode 100644 index 0de289c6c..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_lcd.h +++ /dev/null @@ -1,393 +0,0 @@ -/** - ****************************************************************************** - * @file stm32100b_eval_lcd.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains all the functions prototypes for the stm32100b_eval_lcd - * firmware driver. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32100B_EVAL_LCD_H -#define __STM32100B_EVAL_LCD_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" -#include "../Common/fonts.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32100B_EVAL - * @{ - */ - -/** @addtogroup STM32100B_EVAL_LCD - * @{ - */ - - -/** @defgroup STM32100B_EVAL_LCD_Exported_Types - * @{ - */ -typedef struct -{ - int16_t X; - int16_t Y; -} Point, * pPoint; -/** - * @} - */ - -/** @defgroup STM32100B_EVAL_LCD_Exported_Constants - * @{ - */ - -/** - * @brief Uncomment the line below if you want to use LCD_DrawBMP function to - * display a bitmap picture on the LCD. This function assumes that the bitmap - * file is loaded in the SPI Flash (mounted on STM32100B-EVAL board), however - * user can tailor it according to his application hardware requirement. - */ -/*#define USE_LCD_DrawBMP*/ - -/** - * @brief Uncomment the line below if you want to use user defined Delay function - * (for precise timing), otherwise default _delay_ function defined within - * this driver is used (less precise timing). - */ -/* #define USE_Delay */ - -#ifdef USE_Delay -#include "main.h" - - #define _delay_ Delay /* !< User can provide more timing precise _delay_ function - (with 10ms time base), using SysTick for example */ -#else - #define _delay_ delay /* !< Default _delay_ function with less precise timing */ -#endif - - -/** - * @brief LCD Control pins - */ -#define LCD_NCS_PIN GPIO_Pin_2 -#define LCD_NCS_GPIO_PORT GPIOB -#define LCD_NCS_GPIO_CLK RCC_APB2Periph_GPIOB -#define LCD_NWR_PIN GPIO_Pin_15 -#define LCD_NWR_GPIO_PORT GPIOD -#define LCD_NWR_GPIO_CLK RCC_APB2Periph_GPIOD -#define LCD_RS_PIN GPIO_Pin_7 -#define LCD_RS_GPIO_PORT GPIOD -#define LCD_RS_GPIO_CLK RCC_APB2Periph_GPIOD - -/** - * @brief LCD SPI Interface pins - */ -#define LCD_SPI SPI2 -#define LCD_SPI_CLK RCC_APB1Periph_SPI2 -#define LCD_SPI_SCK_PIN GPIO_Pin_13 -#define LCD_SPI_SCK_GPIO_PORT GPIOB -#define LCD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOB -#define LCD_SPI_MISO_PIN GPIO_Pin_14 -#define LCD_SPI_MISO_GPIO_PORT GPIOB -#define LCD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOB -#define LCD_SPI_MOSI_PIN GPIO_Pin_15 -#define LCD_SPI_MOSI_GPIO_PORT GPIOB -#define LCD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOB - - -/** - * @brief LCD Registers - */ -#define LCD_REG_0 0x00 -#define LCD_REG_1 0x01 -#define LCD_REG_2 0x02 -#define LCD_REG_3 0x03 -#define LCD_REG_4 0x04 -#define LCD_REG_5 0x05 -#define LCD_REG_6 0x06 -#define LCD_REG_7 0x07 -#define LCD_REG_8 0x08 -#define LCD_REG_9 0x09 -#define LCD_REG_10 0x0A -#define LCD_REG_12 0x0C -#define LCD_REG_13 0x0D -#define LCD_REG_14 0x0E -#define LCD_REG_15 0x0F -#define LCD_REG_16 0x10 -#define LCD_REG_17 0x11 -#define LCD_REG_18 0x12 -#define LCD_REG_19 0x13 -#define LCD_REG_20 0x14 -#define LCD_REG_21 0x15 -#define LCD_REG_22 0x16 -#define LCD_REG_23 0x17 -#define LCD_REG_24 0x18 -#define LCD_REG_25 0x19 -#define LCD_REG_26 0x1A -#define LCD_REG_27 0x1B -#define LCD_REG_28 0x1C -#define LCD_REG_29 0x1D -#define LCD_REG_30 0x1E -#define LCD_REG_31 0x1F -#define LCD_REG_32 0x20 -#define LCD_REG_33 0x21 -#define LCD_REG_34 0x22 -#define LCD_REG_36 0x24 -#define LCD_REG_37 0x25 -#define LCD_REG_40 0x28 -#define LCD_REG_41 0x29 -#define LCD_REG_43 0x2B -#define LCD_REG_45 0x2D -#define LCD_REG_48 0x30 -#define LCD_REG_49 0x31 -#define LCD_REG_50 0x32 -#define LCD_REG_51 0x33 -#define LCD_REG_52 0x34 -#define LCD_REG_53 0x35 -#define LCD_REG_54 0x36 -#define LCD_REG_55 0x37 -#define LCD_REG_56 0x38 -#define LCD_REG_57 0x39 -#define LCD_REG_59 0x3B -#define LCD_REG_60 0x3C -#define LCD_REG_61 0x3D -#define LCD_REG_62 0x3E -#define LCD_REG_63 0x3F -#define LCD_REG_64 0x40 -#define LCD_REG_65 0x41 -#define LCD_REG_66 0x42 -#define LCD_REG_67 0x43 -#define LCD_REG_68 0x44 -#define LCD_REG_69 0x45 -#define LCD_REG_70 0x46 -#define LCD_REG_71 0x47 -#define LCD_REG_72 0x48 -#define LCD_REG_73 0x49 -#define LCD_REG_74 0x4A -#define LCD_REG_75 0x4B -#define LCD_REG_76 0x4C -#define LCD_REG_77 0x4D -#define LCD_REG_78 0x4E -#define LCD_REG_79 0x4F -#define LCD_REG_80 0x50 -#define LCD_REG_81 0x51 -#define LCD_REG_82 0x52 -#define LCD_REG_83 0x53 -#define LCD_REG_96 0x60 -#define LCD_REG_97 0x61 -#define LCD_REG_106 0x6A -#define LCD_REG_118 0x76 -#define LCD_REG_128 0x80 -#define LCD_REG_129 0x81 -#define LCD_REG_130 0x82 -#define LCD_REG_131 0x83 -#define LCD_REG_132 0x84 -#define LCD_REG_133 0x85 -#define LCD_REG_134 0x86 -#define LCD_REG_135 0x87 -#define LCD_REG_136 0x88 -#define LCD_REG_137 0x89 -#define LCD_REG_139 0x8B -#define LCD_REG_140 0x8C -#define LCD_REG_141 0x8D -#define LCD_REG_143 0x8F -#define LCD_REG_144 0x90 -#define LCD_REG_145 0x91 -#define LCD_REG_146 0x92 -#define LCD_REG_147 0x93 -#define LCD_REG_148 0x94 -#define LCD_REG_149 0x95 -#define LCD_REG_150 0x96 -#define LCD_REG_151 0x97 -#define LCD_REG_152 0x98 -#define LCD_REG_153 0x99 -#define LCD_REG_154 0x9A -#define LCD_REG_157 0x9D -#define LCD_REG_192 0xC0 -#define LCD_REG_193 0xC1 -#define LCD_REG_227 0xE3 -#define LCD_REG_229 0xE5 -#define LCD_REG_231 0xE7 -#define LCD_REG_239 0xEF - - -/** - * @brief LCD color - */ -#define LCD_COLOR_WHITE 0xFFFF -#define LCD_COLOR_BLACK 0x0000 -#define LCD_COLOR_GREY 0xF7DE -#define LCD_COLOR_BLUE 0x001F -#define LCD_COLOR_BLUE2 0x051F -#define LCD_COLOR_RED 0xF800 -#define LCD_COLOR_MAGENTA 0xF81F -#define LCD_COLOR_GREEN 0x07E0 -#define LCD_COLOR_CYAN 0x7FFF -#define LCD_COLOR_YELLOW 0xFFE0 - -/** - * @brief LCD Lines depending on the chosen fonts. - */ -#define LCD_LINE_0 LINE(0) -#define LCD_LINE_1 LINE(1) -#define LCD_LINE_2 LINE(2) -#define LCD_LINE_3 LINE(3) -#define LCD_LINE_4 LINE(4) -#define LCD_LINE_5 LINE(5) -#define LCD_LINE_6 LINE(6) -#define LCD_LINE_7 LINE(7) -#define LCD_LINE_8 LINE(8) -#define LCD_LINE_9 LINE(9) -#define LCD_LINE_10 LINE(10) -#define LCD_LINE_11 LINE(11) -#define LCD_LINE_12 LINE(12) -#define LCD_LINE_13 LINE(13) -#define LCD_LINE_14 LINE(14) -#define LCD_LINE_15 LINE(15) -#define LCD_LINE_16 LINE(16) -#define LCD_LINE_17 LINE(17) -#define LCD_LINE_18 LINE(18) -#define LCD_LINE_19 LINE(19) -#define LCD_LINE_20 LINE(20) -#define LCD_LINE_21 LINE(21) -#define LCD_LINE_22 LINE(22) -#define LCD_LINE_23 LINE(23) -#define LCD_LINE_24 LINE(24) -#define LCD_LINE_25 LINE(25) -#define LCD_LINE_26 LINE(26) -#define LCD_LINE_27 LINE(27) -#define LCD_LINE_28 LINE(28) -#define LCD_LINE_29 LINE(29) - - -/** - * @brief LCD default font - */ -#define LCD_DEFAULT_FONT Font16x24 - -/** - * @brief LCD Direction - */ -#define LCD_DIR_HORIZONTAL 0x0000 -#define LCD_DIR_VERTICAL 0x0001 - -/** - * @brief LCD Size (Width and Height) - */ -#define LCD_PIXEL_WIDTH 0x0140 -#define LCD_PIXEL_HEIGHT 0x00F0 - -/** - * @} - */ - -/** @defgroup STM32100B_EVAL_LCD_Exported_Macros - * @{ - */ -#define ASSEMBLE_RGB(R, G, B) ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3)) - -/** - * @} - */ - -/** @defgroup STM32100B_EVAL_LCD_Exported_Functions - * @{ - */ -void LCD_DeInit(void); -void LCD_Setup(void); -void STM32100B_LCD_Init(void); -void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor); -void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor); -void LCD_SetTextColor(__IO uint16_t Color); -void LCD_SetBackColor(__IO uint16_t Color); -void LCD_ClearLine(uint8_t Line); -void LCD_Clear(uint16_t Color); -void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos); -void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c); -void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii); -void LCD_SetFont(sFONT *fonts); -sFONT *LCD_GetFont(void); -void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr); -void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width); -void LCD_WindowModeDisable(void); -void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction); -void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width); -void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius); -void LCD_DrawMonoPict(const uint32_t *Pict); -void LCD_DrawBMP(uint32_t BmpAddress); -void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2); -void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height); -void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius); -void LCD_PolyLine(pPoint Points, uint16_t PointCount); -void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount); -void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount); -void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount); -void LCD_FillPolyLine(pPoint Points, uint16_t PointCount); -void LCD_nCS_StartByte(uint8_t Start_Byte); -void LCD_WriteRegIndex(uint8_t LCD_Reg); -void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue); -void LCD_WriteRAM_Prepare(void); -void LCD_WriteRAMWord(uint16_t RGB_Code); -uint16_t LCD_ReadReg(uint8_t LCD_Reg); -void LCD_WriteRAM(uint16_t RGB_Code); -void LCD_PowerOn(void); -void LCD_DisplayOn(void); -void LCD_DisplayOff(void); - - -void LCD_CtrlLinesConfig(void); -void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal); -void LCD_SPIConfig(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32100B_EVAL_LCD_H */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval.c deleted file mode 100644 index 04964b0bf..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval.c +++ /dev/null @@ -1,762 +0,0 @@ -/** - ****************************************************************************** - * @file stm32100e_eval.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file provides - * - set of firmware functions to manage Leds, push-button and COM ports - * - low level initialization functions for SD card (on SDIO), SPI serial - * flash (sFLASH) and temperature sensor (LM75) - * available on STM32100E-EVAL evaluation board from STMicroelectronics. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32100e_eval.h" -#include "stm32f10x_spi.h" -#include "stm32f10x_i2c.h" -#include "stm32f10x_dma.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32100E_EVAL - * @{ - */ - -/** @defgroup STM32100E_EVAL_LOW_LEVEL - * @brief This file provides firmware functions to manage Leds, push-buttons, - * COM ports, SD card on SDIO, serial flash (sFLASH), serial EEPROM (sEE) - * and temperature sensor (LM75) available on STM32100E-EVAL evaluation - * board from STMicroelectronics. - * @{ - */ - -/** @defgroup STM32100E_EVAL_LOW_LEVEL_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32100E_EVAL_LOW_LEVEL_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32100E_EVAL_LOW_LEVEL_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32100E_EVAL_LOW_LEVEL_Private_Variables - * @{ - */ -GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT, - LED4_GPIO_PORT}; -const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN, - LED4_PIN}; -const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK, - LED4_GPIO_CLK}; - -GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT, - KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT, - LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT, - DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT}; - -const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN, - KEY_BUTTON_PIN, RIGHT_BUTTON_PIN, - LEFT_BUTTON_PIN, UP_BUTTON_PIN, - DOWN_BUTTON_PIN, SEL_BUTTON_PIN}; - -const uint32_t BUTTON_CLK[BUTTONn] = {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK, - KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK, - LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK, - DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK}; - -const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {WAKEUP_BUTTON_EXTI_LINE, - TAMPER_BUTTON_EXTI_LINE, - KEY_BUTTON_EXTI_LINE, - RIGHT_BUTTON_EXTI_LINE, - LEFT_BUTTON_EXTI_LINE, - UP_BUTTON_EXTI_LINE, - DOWN_BUTTON_EXTI_LINE, - SEL_BUTTON_EXTI_LINE}; - -const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PORT_SOURCE, - TAMPER_BUTTON_EXTI_PORT_SOURCE, - KEY_BUTTON_EXTI_PORT_SOURCE, - RIGHT_BUTTON_EXTI_PORT_SOURCE, - LEFT_BUTTON_EXTI_PORT_SOURCE, - UP_BUTTON_EXTI_PORT_SOURCE, - DOWN_BUTTON_EXTI_PORT_SOURCE, - SEL_BUTTON_EXTI_PORT_SOURCE}; - -const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PIN_SOURCE, - TAMPER_BUTTON_EXTI_PIN_SOURCE, - KEY_BUTTON_EXTI_PIN_SOURCE, - RIGHT_BUTTON_EXTI_PIN_SOURCE, - LEFT_BUTTON_EXTI_PIN_SOURCE, - UP_BUTTON_EXTI_PIN_SOURCE, - DOWN_BUTTON_EXTI_PIN_SOURCE, - SEL_BUTTON_EXTI_PIN_SOURCE}; - -const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn, - KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn, - LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn, - DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn}; - -USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2}; - -GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT}; - -GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT}; - -const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK}; - -const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK}; - -const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK}; - -const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN}; - -const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN}; - -DMA_InitTypeDef sEEDMA_InitStructure; - -/** - * @} - */ - - -/** @defgroup STM32100E_EVAL_LOW_LEVEL_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - - -/** @defgroup STM32100E_EVAL_LOW_LEVEL_Private_Functions - * @{ - */ - -/** - * @brief Configures LED GPIO. - * @param Led: Specifies the Led to be configured. - * This parameter can be one of following parameters: - * @arg LED1 - * @arg LED2 - * @arg LED3 - * @arg LED4 - * @retval None - */ -void STM_EVAL_LEDInit(Led_TypeDef Led) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable the GPIO_LED Clock */ - RCC_APB2PeriphClockCmd(GPIO_CLK[Led], ENABLE); - - /* Configure the GPIO_LED pin */ - GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led]; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - - GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure); -} - -/** - * @brief Turns selected LED On. - * @param Led: Specifies the Led to be set on. - * This parameter can be one of following parameters: - * @arg LED1 - * @arg LED2 - * @arg LED3 - * @arg LED4 - * @retval None - */ -void STM_EVAL_LEDOn(Led_TypeDef Led) -{ - GPIO_PORT[Led]->BSRR = GPIO_PIN[Led]; -} - -/** - * @brief Turns selected LED Off. - * @param Led: Specifies the Led to be set off. - * This parameter can be one of following parameters: - * @arg LED1 - * @arg LED2 - * @arg LED3 - * @arg LED4 - * @retval None - */ -void STM_EVAL_LEDOff(Led_TypeDef Led) -{ - GPIO_PORT[Led]->BRR = GPIO_PIN[Led]; -} - -/** - * @brief Toggles the selected LED. - * @param Led: Specifies the Led to be toggled. - * This parameter can be one of following parameters: - * @arg LED1 - * @arg LED2 - * @arg LED3 - * @arg LED4 - * @retval None - */ -void STM_EVAL_LEDToggle(Led_TypeDef Led) -{ - GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led]; -} - -/** - * @brief Configures Button GPIO and EXTI Line. - * @param Button: Specifies the Button to be configured. - * This parameter can be one of following parameters: - * @arg BUTTON_WAKEUP: Wakeup Push Button - * @arg BUTTON_TAMPER: Tamper Push Button - * @arg BUTTON_KEY: Key Push Button - * @arg BUTTON_RIGHT: Joystick Right Push Button - * @arg BUTTON_LEFT: Joystick Left Push Button - * @arg BUTTON_UP: Joystick Up Push Button - * @arg BUTTON_DOWN: Joystick Down Push Button - * @arg BUTTON_SEL: Joystick Sel Push Button - * @param Button_Mode: Specifies Button mode. - * This parameter can be one of following parameters: - * @arg BUTTON_MODE_GPIO: Button will be used as simple IO - * @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt - * generation capability - * @retval None - */ -void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode) -{ - GPIO_InitTypeDef GPIO_InitStructure; - EXTI_InitTypeDef EXTI_InitStructure; - NVIC_InitTypeDef NVIC_InitStructure; - - /* Enable the BUTTON Clock */ - RCC_APB2PeriphClockCmd(BUTTON_CLK[Button] | RCC_APB2Periph_AFIO, ENABLE); - - /* Configure Button pin as input floating */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button]; - GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure); - - - if (Button_Mode == BUTTON_MODE_EXTI) - { - /* Connect Button EXTI Line to Button GPIO Pin */ - GPIO_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]); - - /* Configure Button EXTI line */ - EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button]; - EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; - - if(Button != BUTTON_WAKEUP) - { - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; - } - else - { - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; - } - EXTI_InitStructure.EXTI_LineCmd = ENABLE; - EXTI_Init(&EXTI_InitStructure); - - /* Enable and set Button EXTI Interrupt to the lowest priority */ - NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button]; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - - NVIC_Init(&NVIC_InitStructure); - } -} - -/** - * @brief Returns the selected Button state. - * @param Button: Specifies the Button to be checked. - * This parameter can be one of following parameters: - * @arg BUTTON_WAKEUP: Wakeup Push Button - * @arg BUTTON_TAMPER: Tamper Push Button - * @arg BUTTON_KEY: Key Push Button - * @arg BUTTON_RIGHT: Joystick Right Push Button - * @arg BUTTON_LEFT: Joystick Left Push Button - * @arg BUTTON_UP: Joystick Up Push Button - * @arg BUTTON_DOWN: Joystick Down Push Button - * @arg BUTTON_SEL: Joystick Sel Push Button - * @retval The Button GPIO pin value. - */ -uint32_t STM_EVAL_PBGetState(Button_TypeDef Button) -{ - return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]); -} - -/** - * @brief Configures COM port. - * @param COM: Specifies the COM port to be configured. - * This parameter can be one of following parameters: - * @arg COM1 - * @arg COM2 - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that - * contains the configuration information for the specified USART peripheral. - * @retval None - */ -void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable GPIO clock */ - RCC_APB2PeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM] | RCC_APB2Periph_AFIO, ENABLE); - - /* Enable UART clock */ - if (COM == COM1) - { - RCC_APB2PeriphClockCmd(COM_USART_CLK[COM], ENABLE); - } - else - { - RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE); - } - - /* Configure USART Tx as alternate function push-pull */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM]; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure); - - /* Configure USART Rx as input floating */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM]; - GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure); - - /* USART configuration */ - USART_Init(COM_USART[COM], USART_InitStruct); - - /* Enable USART */ - USART_Cmd(COM_USART[COM], ENABLE); -} - -/** - * @brief DeInitializes the SD/SD communication. - * @param None - * @retval None - */ -void SD_LowLevel_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - SPI_Cmd(SD_SPI, DISABLE); /*!< SD_SPI disable */ - SPI_I2S_DeInit(SD_SPI); /*!< DeInitializes the SD_SPI */ - - /*!< SD_SPI Periph clock disable */ - RCC_APB1PeriphClockCmd(SD_SPI_CLK, DISABLE); - - /*!< Configure SD_SPI pins: SCK */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI pins: MISO */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN; - GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI pins: MOSI */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN; - GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */ - GPIO_InitStructure.GPIO_Pin = SD_CS_PIN; - GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */ - GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN; - GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @brief Initializes the SD_SPI and CS pins. - * @param None - * @retval None - */ -void SD_LowLevel_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - SPI_InitTypeDef SPI_InitStructure; - - /*!< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO - and SD_SPI_SCK_GPIO Periph clock enable */ - RCC_APB2PeriphClockCmd(SD_CS_GPIO_CLK | SD_SPI_MOSI_GPIO_CLK | SD_SPI_MISO_GPIO_CLK | - SD_SPI_SCK_GPIO_CLK | SD_DETECT_GPIO_CLK, ENABLE); - - /*!< SD_SPI Periph clock enable */ - RCC_APB1PeriphClockCmd(SD_SPI_CLK, ENABLE); - - /*!< Configure SD_SPI pins: SCK */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI pins: MOSI */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN; - GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI pins: MISO */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN; - GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */ - GPIO_InitStructure.GPIO_Pin = SD_CS_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */ - GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure); - - /*!< SD_SPI Config */ - SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; - SPI_InitStructure.SPI_Mode = SPI_Mode_Master; - SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; - SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; - SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; - SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; - SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; - SPI_InitStructure.SPI_CRCPolynomial = 7; - SPI_Init(SD_SPI, &SPI_InitStructure); - - SPI_Cmd(SD_SPI, ENABLE); /*!< SD_SPI enable */ -} - -/** - * @brief DeInitializes peripherals used by the I2C EEPROM driver. - * @param None - * @retval None - */ -void sEE_LowLevel_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - NVIC_InitTypeDef NVIC_InitStructure; - - /* sEE_I2C Peripheral Disable */ - I2C_Cmd(sEE_I2C, DISABLE); - - /* sEE_I2C DeInit */ - I2C_DeInit(sEE_I2C); - - /*!< sEE_I2C Periph clock disable */ - RCC_APB1PeriphClockCmd(sEE_I2C_CLK, DISABLE); - - /*!< GPIO configuration */ - /*!< Configure sEE_I2C pins: SCL */ - GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sEE_I2C pins: SDA */ - GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN; - GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); - - /* Configure and enable I2C DMA TX Channel interrupt */ - NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO; - NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE; - NVIC_Init(&NVIC_InitStructure); - - /* Configure and enable I2C DMA RX Channel interrupt */ - NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO; - NVIC_Init(&NVIC_InitStructure); - - /* Disable and Deinitialize the DMA channels */ - DMA_Cmd(sEE_I2C_DMA_CHANNEL_TX, DISABLE); - DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, DISABLE); - DMA_DeInit(sEE_I2C_DMA_CHANNEL_TX); - DMA_DeInit(sEE_I2C_DMA_CHANNEL_RX); -} - -/** - * @brief Initializes peripherals used by the I2C EEPROM driver. - * @param None - * @retval None - */ -void sEE_LowLevel_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - NVIC_InitTypeDef NVIC_InitStructure; - - /*!< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable */ - RCC_APB2PeriphClockCmd(sEE_I2C_SCL_GPIO_CLK | sEE_I2C_SDA_GPIO_CLK, ENABLE); - - /*!< sEE_I2C Periph clock enable */ - RCC_APB1PeriphClockCmd(sEE_I2C_CLK, ENABLE); - - /*!< GPIO configuration */ - /*!< Configure sEE_I2C pins: SCL */ - GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD; - GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sEE_I2C pins: SDA */ - GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN; - GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); - - /* Configure and enable I2C DMA TX Channel interrupt */ - NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); - - /* Configure and enable I2C DMA RX Channel interrupt */ - NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO; - NVIC_Init(&NVIC_InitStructure); - - /*!< I2C DMA TX and RX channels configuration */ - /* Enable the DMA clock */ - RCC_AHBPeriphClockCmd(sEE_I2C_DMA_CLK, ENABLE); - - /* I2C TX DMA Channel configuration */ - DMA_DeInit(sEE_I2C_DMA_CHANNEL_TX); - sEEDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)sEE_I2C_DR_Address; - sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)0; /* This parameter will be configured durig communication */ - sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST; /* This parameter will be configured durig communication */ - sEEDMA_InitStructure.DMA_BufferSize = 0xFFFF; /* This parameter will be configured durig communication */ - sEEDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - sEEDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - sEEDMA_InitStructure.DMA_PeripheralDataSize = DMA_MemoryDataSize_Byte; - sEEDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - sEEDMA_InitStructure.DMA_Mode = DMA_Mode_Normal; - sEEDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; - sEEDMA_InitStructure.DMA_M2M = DMA_M2M_Disable; - DMA_Init(sEE_I2C_DMA_CHANNEL_TX, &sEEDMA_InitStructure); - - /* I2C RX DMA Channel configuration */ - DMA_DeInit(sEE_I2C_DMA_CHANNEL_RX); - DMA_Init(sEE_I2C_DMA_CHANNEL_RX, &sEEDMA_InitStructure); - - /* Enable the DMA Channels Interrupts */ - DMA_ITConfig(sEE_I2C_DMA_CHANNEL_TX, DMA_IT_TC, ENABLE); - DMA_ITConfig(sEE_I2C_DMA_CHANNEL_RX, DMA_IT_TC, ENABLE); -} - -/** - * @brief Initializes DMA channel used by the I2C EEPROM driver. - * @param None - * @retval None - */ -void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction) -{ - /* Initialize the DMA with the new parameters */ - if (Direction == sEE_DIRECTION_TX) - { - /* Configure the DMA Tx Channel with the buffer address and the buffer size */ - sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)pBuffer; - sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST; - sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize; - DMA_Init(sEE_I2C_DMA_CHANNEL_TX, &sEEDMA_InitStructure); - } - else - { - /* Configure the DMA Rx Channel with the buffer address and the buffer size */ - sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)pBuffer; - sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; - sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize; - DMA_Init(sEE_I2C_DMA_CHANNEL_RX, &sEEDMA_InitStructure); - } -} - -/** - * @brief DeInitializes the peripherals used by the SPI FLASH driver. - * @param None - * @retval None - */ -void sFLASH_LowLevel_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< Disable the sFLASH_SPI */ - SPI_Cmd(sFLASH_SPI, DISABLE); - - /*!< DeInitializes the sFLASH_SPI */ - SPI_I2S_DeInit(sFLASH_SPI); - - /*!< sFLASH_SPI Periph clock disable */ - RCC_APB2PeriphClockCmd(sFLASH_SPI_CLK, DISABLE); - - /*!< Configure sFLASH_SPI pins: SCK */ - GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sFLASH_SPI pins: MISO */ - GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN; - GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sFLASH_SPI pins: MOSI */ - GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN; - GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin */ - GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN; - GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @brief Initializes the peripherals used by the SPI FLASH driver. - * @param None - * @retval None - */ -void sFLASH_LowLevel_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO - and sFLASH_SPI_SCK_GPIO Periph clock enable */ - RCC_APB2PeriphClockCmd(sFLASH_CS_GPIO_CLK | sFLASH_SPI_MOSI_GPIO_CLK | sFLASH_SPI_MISO_GPIO_CLK | - sFLASH_SPI_SCK_GPIO_CLK, ENABLE); - - /*!< sFLASH_SPI Periph clock enable */ - RCC_APB2PeriphClockCmd(sFLASH_SPI_CLK, ENABLE); - - /*!< Configure sFLASH_SPI pins: SCK */ - GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sFLASH_SPI pins: MOSI */ - GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN; - GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sFLASH_SPI pins: MISO */ - GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin */ - GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @brief DeInitializes the LM75_I2C. - * @param None - * @retval None - */ -void LM75_LowLevel_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< Disable LM75_I2C */ - I2C_Cmd(LM75_I2C, DISABLE); - /*!< DeInitializes the LM75_I2C */ - I2C_DeInit(LM75_I2C); - - /*!< LM75_I2C Periph clock disable */ - RCC_APB1PeriphClockCmd(LM75_I2C_CLK, DISABLE); - - /*!< Configure LM75_I2C pins: SCL */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure LM75_I2C pins: SDA */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN; - GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure LM75_I2C pin: SMBUS ALERT */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN; - GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @brief Initializes the LM75_I2C.. - * @param None - * @retval None - */ -void LM75_LowLevel_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< LM75_I2C Periph clock enable */ - RCC_APB1PeriphClockCmd(LM75_I2C_CLK, ENABLE); - - /*!< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK - and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable */ - RCC_APB2PeriphClockCmd(LM75_I2C_SCL_GPIO_CLK | LM75_I2C_SDA_GPIO_CLK | - LM75_I2C_SMBUSALERT_GPIO_CLK, ENABLE); - - /*!< Configure LM75_I2C pins: SCL */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD; - GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure LM75_I2C pins: SDA */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN; - GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure LM75_I2C pin: SMBUS ALERT */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval.h deleted file mode 100644 index fedb659ea..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval.h +++ /dev/null @@ -1,393 +0,0 @@ -/** - ****************************************************************************** - * @file stm32100e_eval.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains definitions for STM32100E_EVAL's Leds, push-buttons - * COM ports, sFLASH (on SPI) and Temperature Sensor LM75 (on I2C) - * hardware resources. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32100E_EVAL_H -#define __STM32100E_EVAL_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32_eval.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32100E_EVAL - * @{ - */ - -/** @addtogroup STM32100E_EVAL_LOW_LEVEL - * @{ - */ - -/** @defgroup STM32100E_EVAL_LOW_LEVEL_Exported_Types - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32100E_EVAL_LOW_LEVEL_Exported_Constants - * @{ - */ -/** @addtogroup STM32100E_EVAL_LOW_LEVEL_LED - * @{ - */ -#define LEDn 4 - -#define LED1_PIN GPIO_Pin_6 -#define LED1_GPIO_PORT GPIOF -#define LED1_GPIO_CLK RCC_APB2Periph_GPIOF - -#define LED2_PIN GPIO_Pin_7 -#define LED2_GPIO_PORT GPIOF -#define LED2_GPIO_CLK RCC_APB2Periph_GPIOF - -#define LED3_PIN GPIO_Pin_8 -#define LED3_GPIO_PORT GPIOF -#define LED3_GPIO_CLK RCC_APB2Periph_GPIOF - -#define LED4_PIN GPIO_Pin_9 -#define LED4_GPIO_PORT GPIOF -#define LED4_GPIO_CLK RCC_APB2Periph_GPIOF - -/** - * @} - */ - -/** @addtogroup STM32100E_EVAL_LOW_LEVEL_BUTTON - * @{ - */ -#define BUTTONn 8 - -/** - * @brief Wakeup push-button - */ -#define WAKEUP_BUTTON_PIN GPIO_Pin_0 -#define WAKEUP_BUTTON_GPIO_PORT GPIOA -#define WAKEUP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOA -#define WAKEUP_BUTTON_EXTI_LINE EXTI_Line0 -#define WAKEUP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOA -#define WAKEUP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0 -#define WAKEUP_BUTTON_EXTI_IRQn EXTI0_IRQn -/** - * @brief Tamper push-button - */ -#define TAMPER_BUTTON_PIN GPIO_Pin_13 -#define TAMPER_BUTTON_GPIO_PORT GPIOC -#define TAMPER_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOC -#define TAMPER_BUTTON_EXTI_LINE EXTI_Line13 -#define TAMPER_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOC -#define TAMPER_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13 -#define TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn -/** - * @brief Key push-button - */ -#define KEY_BUTTON_PIN GPIO_Pin_8 -#define KEY_BUTTON_GPIO_PORT GPIOG -#define KEY_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG -#define KEY_BUTTON_EXTI_LINE EXTI_Line8 -#define KEY_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG -#define KEY_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource8 -#define KEY_BUTTON_EXTI_IRQn EXTI9_5_IRQn -/** - * @brief Joystick Right push-button - */ -#define RIGHT_BUTTON_PIN GPIO_Pin_13 -#define RIGHT_BUTTON_GPIO_PORT GPIOG -#define RIGHT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG -#define RIGHT_BUTTON_EXTI_LINE EXTI_Line13 -#define RIGHT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG -#define RIGHT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13 -#define RIGHT_BUTTON_EXTI_IRQn EXTI15_10_IRQn -/** - * @brief Joystick Left push-button - */ -#define LEFT_BUTTON_PIN GPIO_Pin_14 -#define LEFT_BUTTON_GPIO_PORT GPIOG -#define LEFT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG -#define LEFT_BUTTON_EXTI_LINE EXTI_Line14 -#define LEFT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG -#define LEFT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource14 -#define LEFT_BUTTON_EXTI_IRQn EXTI15_10_IRQn -/** - * @brief Joystick Up push-button - */ -#define UP_BUTTON_PIN GPIO_Pin_15 -#define UP_BUTTON_GPIO_PORT GPIOG -#define UP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG -#define UP_BUTTON_EXTI_LINE EXTI_Line15 -#define UP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG -#define UP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource15 -#define UP_BUTTON_EXTI_IRQn EXTI15_10_IRQn -/** - * @brief Joystick Down push-button - */ -#define DOWN_BUTTON_PIN GPIO_Pin_11 -#define DOWN_BUTTON_GPIO_PORT GPIOG -#define DOWN_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG -#define DOWN_BUTTON_EXTI_LINE EXTI_Line11 -#define DOWN_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG -#define DOWN_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource11 -#define DOWN_BUTTON_EXTI_IRQn EXTI15_10_IRQn -/** - * @brief Joystick Sel push-button - */ -#define SEL_BUTTON_PIN GPIO_Pin_7 -#define SEL_BUTTON_GPIO_PORT GPIOG -#define SEL_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG -#define SEL_BUTTON_EXTI_LINE EXTI_Line7 -#define SEL_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG -#define SEL_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource7 -#define SEL_BUTTON_EXTI_IRQn EXTI9_5_IRQn -/** - * @} - */ - -/** @addtogroup STM32100E_EVAL_LOW_LEVEL_COM - * @{ - */ -#define COMn 2 - -/** - * @brief Definition for COM port1, connected to USART1 - */ -#define EVAL_COM1 USART1 -#define EVAL_COM1_CLK RCC_APB2Periph_USART1 -#define EVAL_COM1_TX_PIN GPIO_Pin_9 -#define EVAL_COM1_TX_GPIO_PORT GPIOA -#define EVAL_COM1_TX_GPIO_CLK RCC_APB2Periph_GPIOA -#define EVAL_COM1_RX_PIN GPIO_Pin_10 -#define EVAL_COM1_RX_GPIO_PORT GPIOA -#define EVAL_COM1_RX_GPIO_CLK RCC_APB2Periph_GPIOA -#define EVAL_COM1_IRQn USART1_IRQn - -/** - * @brief Definition for COM port2, connected to USART2 - */ -#define EVAL_COM2 USART2 -#define EVAL_COM2_CLK RCC_APB1Periph_USART2 -#define EVAL_COM2_TX_PIN GPIO_Pin_2 -#define EVAL_COM2_TX_GPIO_PORT GPIOA -#define EVAL_COM2_TX_GPIO_CLK RCC_APB2Periph_GPIOA -#define EVAL_COM2_RX_PIN GPIO_Pin_3 -#define EVAL_COM2_RX_GPIO_PORT GPIOA -#define EVAL_COM2_RX_GPIO_CLK RCC_APB2Periph_GPIOA -#define EVAL_COM2_IRQn USART2_IRQn - -/** - * @} - */ - -/** @addtogroup STM32100E_EVAL_LOW_LEVEL_SD_FLASH - * @{ - */ -/** - * @brief SD SPI Interface pins - */ -#define SD_SPI SPI2 -#define SD_SPI_CLK RCC_APB1Periph_SPI2 -#define SD_SPI_SCK_PIN GPIO_Pin_13 /* PC.13 */ -#define SD_SPI_SCK_GPIO_PORT GPIOB /* GPIOB */ -#define SD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOB -#define SD_SPI_MISO_PIN GPIO_Pin_14 /* PC.14 */ -#define SD_SPI_MISO_GPIO_PORT GPIOB /* GPIOB */ -#define SD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOB -#define SD_SPI_MOSI_PIN GPIO_Pin_15 /* PB.15 */ -#define SD_SPI_MOSI_GPIO_PORT GPIOB /* GPIOB */ -#define SD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOB -#define SD_CS_PIN GPIO_Pin_6 /* PG.06 */ -#define SD_CS_GPIO_PORT GPIOG /* GPIOG */ -#define SD_CS_GPIO_CLK RCC_APB2Periph_GPIOG -#define SD_DETECT_PIN GPIO_Pin_11 /* PF.11 */ -#define SD_DETECT_GPIO_PORT GPIOF /* GPIOF */ -#define SD_DETECT_GPIO_CLK RCC_APB2Periph_GPIOF - -/** - * @} - */ - -/** @addtogroup STM3210C_EVAL_LOW_LEVEL_I2C_EE - * @{ - */ -/** - * @brief I2C EEPROM Interface pins - */ -#define sEE_I2C I2C2 -#define sEE_I2C_CLK RCC_APB1Periph_I2C2 -#define sEE_I2C_SCL_PIN GPIO_Pin_10 /* PB.10 */ -#define sEE_I2C_SCL_GPIO_PORT GPIOB /* GPIOB */ -#define sEE_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB -#define sEE_I2C_SDA_PIN GPIO_Pin_11 /* PB.11 */ -#define sEE_I2C_SDA_GPIO_PORT GPIOB /* GPIOB */ -#define sEE_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB -#define sEE_M24C64_32 - -#define sEE_I2C_DMA DMA1 -#define sEE_I2C_DMA_CHANNEL_TX DMA1_Channel4 -#define sEE_I2C_DMA_CHANNEL_RX DMA1_Channel5 -#define sEE_I2C_DMA_FLAG_TX_TC DMA1_IT_TC4 -#define sEE_I2C_DMA_FLAG_TX_GL DMA1_IT_GL4 -#define sEE_I2C_DMA_FLAG_RX_TC DMA1_IT_TC5 -#define sEE_I2C_DMA_FLAG_RX_GL DMA1_IT_GL5 -#define sEE_I2C_DMA_CLK RCC_AHBPeriph_DMA1 -#define sEE_I2C_DR_Address ((uint32_t)0x40005810) -#define sEE_USE_DMA - -#define sEE_I2C_DMA_TX_IRQn DMA1_Channel4_IRQn -#define sEE_I2C_DMA_RX_IRQn DMA1_Channel5_IRQn -#define sEE_I2C_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler -#define sEE_I2C_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler -#define sEE_I2C_DMA_PREPRIO 0 -#define sEE_I2C_DMA_SUBPRIO 0 - -#define sEE_DIRECTION_TX 0 -#define sEE_DIRECTION_RX 1 - -/* Time constant for the delay caclulation allowing to have a millisecond - incrementing counter. This value should be equal to (System Clock / 1000). - ie. if system clock = 24MHz then sEE_TIME_CONST should be 24. */ -#define sEE_TIME_CONST 24 - -/** - * @} - */ - -/** @addtogroup STM32100E_EVAL_LOW_LEVEL_M25P_FLASH_SPI - * @{ - */ -/** - * @brief M25P FLASH SPI Interface pins - */ -#define sFLASH_SPI SPI1 -#define sFLASH_SPI_CLK RCC_APB2Periph_SPI1 -#define sFLASH_SPI_SCK_PIN GPIO_Pin_5 /* PA.05 */ -#define sFLASH_SPI_SCK_GPIO_PORT GPIOA /* GPIOA */ -#define sFLASH_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOA -#define sFLASH_SPI_MISO_PIN GPIO_Pin_6 /* PA.06 */ -#define sFLASH_SPI_MISO_GPIO_PORT GPIOA /* GPIOA */ -#define sFLASH_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOA -#define sFLASH_SPI_MOSI_PIN GPIO_Pin_7 /* PA.07 */ -#define sFLASH_SPI_MOSI_GPIO_PORT GPIOA /* GPIOA */ -#define sFLASH_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOA -#define sFLASH_CS_PIN GPIO_Pin_6 /* PE.06 */ -#define sFLASH_CS_GPIO_PORT GPIOE /* GPIOE */ -#define sFLASH_CS_GPIO_CLK RCC_APB2Periph_GPIOE - -/** - * @} - */ - - -/** @addtogroup STM32100E_EVAL_LOW_LEVEL_TSENSOR_I2C - * @{ - */ -/** - * @brief LM75 Temperature Sensor I2C Interface pins - */ -#define LM75_I2C I2C2 -#define LM75_I2C_CLK RCC_APB1Periph_I2C2 -#define LM75_I2C_SCL_PIN GPIO_Pin_10 /* PB.10 */ -#define LM75_I2C_SCL_GPIO_PORT GPIOB /* GPIOB */ -#define LM75_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB -#define LM75_I2C_SDA_PIN GPIO_Pin_11 /* PB.11 */ -#define LM75_I2C_SDA_GPIO_PORT GPIOB /* GPIOB */ -#define LM75_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB -#define LM75_I2C_SMBUSALERT_PIN GPIO_Pin_12 /* PB.12 */ -#define LM75_I2C_SMBUSALERT_GPIO_PORT GPIOB /* GPIOB */ -#define LM75_I2C_SMBUSALERT_GPIO_CLK RCC_APB2Periph_GPIOB -#define LM75_I2C_DR ((uint32_t)0x40005810) - -#define LM75_DMA_CLK RCC_AHBPeriph_DMA1 -#define LM75_DMA_TX_CHANNEL DMA1_Channel4 -#define LM75_DMA_RX_CHANNEL DMA1_Channel5 -#define LM75_DMA_TX_TCFLAG DMA1_FLAG_TC4 -#define LM75_DMA_RX_TCFLAG DMA1_FLAG_TC5 - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup STM32100E_EVAL_LOW_LEVEL_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32100E_EVAL_LOW_LEVEL_Exported_Functions - * @{ - */ -void STM_EVAL_LEDInit(Led_TypeDef Led); -void STM_EVAL_LEDOn(Led_TypeDef Led); -void STM_EVAL_LEDOff(Led_TypeDef Led); -void STM_EVAL_LEDToggle(Led_TypeDef Led); -void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode); -uint32_t STM_EVAL_PBGetState(Button_TypeDef Button); -void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct); -void SD_LowLevel_DeInit(void); -void SD_LowLevel_Init(void); -void sEE_LowLevel_DeInit(void); -void sEE_LowLevel_Init(void); -void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction); -void sFLASH_LowLevel_DeInit(void); -void sFLASH_LowLevel_Init(void); -void LM75_LowLevel_DeInit(void); -void LM75_LowLevel_Init(void); -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __STM32100E_EVAL_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_cec.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_cec.c deleted file mode 100644 index a7595c303..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_cec.c +++ /dev/null @@ -1,1722 +0,0 @@ -/** - ****************************************************************************** - * @file stm32100e_eval_cec.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file provides all the STM32100E-EVAL HDMI-CEC firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32100e_eval_cec.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32100E_EVAL - * @{ - */ - -/** @defgroup STM32100E_EVAL_CEC - * @brief This file includes the CEC Stack driver for HDMI-CEC Module - * of STM32100E-EVAL board. - * @{ - */ - -/** @defgroup STM32100E_EVAL_CEC_Private_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup STM32100E_EVAL_CEC_Private_Defines - * @{ - */ - - -/** - * @} - */ - -/** @defgroup STM32100E_EVAL_CEC_Private_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32100E_EVAL_CEC_Private_Variables - * @{ - */ - -__IO uint32_t ReceivedFrame = 0; -__IO uint32_t SendFrame = 0; -__IO uint32_t BufferCount = 0, TxCounter = 0, RxCounter = 0; -__IO uint8_t BufferPointer[15]; -__IO uint32_t ReceiveStatus = 0; -__IO uint32_t SendStatus = 0; -__IO uint8_t TransErrorCode = 0; -__IO uint8_t RecepErrorCode = 0; -__IO uint8_t MyLogicalAddress = 0; -__IO uint16_t MyPhysicalAddress = 0; -__IO uint8_t DeviceType = 0; -#ifdef HDMI_CEC_USE_DDC -__IO uint8_t pBuffer[256]; -__IO uint16_t NumByteToRead = 255; -#endif -__IO uint8_t CECDevicesNumber = 0; - -HDMI_CEC_Message HDMI_CEC_TX_MessageStructPrivate; -HDMI_CEC_Message HDMI_CEC_RX_MessageStructPrivate; -HDMI_CEC_Message HDMI_CEC_TX_MessageStructure; - -__IO uint8_t FeatureOpcode = 0; -__IO uint8_t AbortReason = 0; -__IO uint8_t DeviceCount = 0; - -HDMI_CEC_Map HDMI_CEC_MapStruct; -HDMI_CEC_Map HDMI_CEC_DeviceMap[14]; - -/* CEC follower addresses */ -uint8_t* HDMI_CEC_Follower_String[13][2] = - { - {(uint8_t*)" TV ", (uint8_t*)"0"}, - {(uint8_t*)"Recording Device 1 ", (uint8_t*)"0"}, - {(uint8_t*)"Recording Device 2 ", (uint8_t*)"0"}, - {(uint8_t*)" Tuner 1 ", (uint8_t*)"0"}, - {(uint8_t*)" Playback Device 1 ", (uint8_t*)"0"}, - {(uint8_t*)" Audio System ", (uint8_t*)"0"}, - {(uint8_t*)" Tuner 2 ", (uint8_t*)"0"}, - {(uint8_t*)" Tuner 3 ", (uint8_t*)"0"}, - {(uint8_t*)" Playback Device 2 ", (uint8_t*)"0"}, - {(uint8_t*)"Recording Device 3 ", (uint8_t*)"0"}, - {(uint8_t*)" Tuner 4 ", (uint8_t*)"0"}, - {(uint8_t*)" Playback Device 3 ", (uint8_t*)"0"}, - {(uint8_t*)" Broadcast ", (uint8_t*)"1"} - }; - -/** - * @} - */ - - -/** @defgroup STM32100E_EVAL_CEC_Private_Function_Prototypes - * @{ - */ -static HDMI_CEC_Error PhysicalAddressDiscovery(void); -static HDMI_CEC_Error LogicalAddressAllocation(void); - - -/** - * @} - */ - - -/** @defgroup STM32100E_EVAL_CEC_Private_Functions - * @{ - */ - -/** - * @brief Initializes the HDMI CEC. - * @param None - * @retval HDMI_CEC_Error: CEC Error code - */ -HDMI_CEC_Error HDMI_CEC_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - CEC_InitTypeDef CEC_InitStructure; - HDMI_CEC_Error errorstatus = HDMI_CEC_OK; - uint8_t sendcount = 0; - -#ifdef HDMI_CEC_USE_DDC - I2C_InitTypeDef I2C_InitStructure; - /* Enable CEC_I2C clocks */ - RCC_APB1PeriphClockCmd(HDMI_CEC_I2C_CLK, ENABLE); - - /* Enable CEC_I2C_GPIO and CEC_HPD_GPIO clocks */ - RCC_APB2PeriphClockCmd(HDMI_CEC_I2C_GPIO_CLK | HDMI_CEC_HPD_GPIO_CLK, ENABLE); -#endif - - /* Enable CEC clocks */ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_CEC, ENABLE); - - /* Enable CEC_LINE_GPIO clocks */ - RCC_APB2PeriphClockCmd(HDMI_CEC_LINE_GPIO_CLK, ENABLE); - - /* Configure CEC_LINE_GPIO as Output open drain */ - GPIO_InitStructure.GPIO_Pin = HDMI_CEC_LINE_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD; - GPIO_Init(HDMI_CEC_LINE_GPIO_PORT, &GPIO_InitStructure); - -#ifdef HDMI_CEC_USE_DDC - /* Configure CEC_I2C_SCL_PIN and CEC_I2C_SDA_PIN as Output open drain */ - GPIO_InitStructure.GPIO_Pin = HDMI_CEC_I2C_SCL_PIN | HDMI_CEC_I2C_SDA_PIN; - GPIO_Init(HDMI_CEC_I2C_GPIO_PORT, &GPIO_InitStructure); - -/* This configuration is only when the HDMI CEC is configured as source. - The HDMI source has to provide the +5V Power signal to the sink. - On STM32100E-EVAL borad, you have to solder the SB4 Solder bridge. - Then, the source will wait for HPD signal to be asserted from the sink. - Once the HPD signal is detected the source shall read the EDID structure - throuhgh the DDC channel. */ - /* Configure CEC_HPD_GPIO as Input pull down */ - GPIO_InitStructure.GPIO_Pin = HDMI_CEC_HPD_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(HDMI_CEC_HPD_GPIO_PORT, &GPIO_InitStructure); - - -/* This configuration is only when the HDMI CEC is configured as sink. - The HDMI sink has to wait for the +5V Power signal from the source. - On STM32100E-EVAL borad, SB4 Solder bridge should be open (default configuration). - Then, the sink will assert the HPD signal to inform the source that the EDID - is ready for read through DDC channel. In this implementation, the EDID structure - is not implemented. */ -/* GPIO_InitStructure.GPIO_Pin = HDMI_CEC_HPD_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_Init(HDMI_CEC_HPD_GPIO_PORT, &GPIO_InitStructure); - - HDMI_CEC_HPD_HIGH(); // Set the Hot plug detect signal */ - - /* Enable CEC_I2C */ - I2C_Cmd(HDMI_CEC_I2C, ENABLE); - - /* I2C configuration */ - I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; - I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2; - I2C_InitStructure.I2C_OwnAddress1 = HDMI_CEC_I2C_SLAVE_ADDRESS7; - I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; - I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; - I2C_InitStructure.I2C_ClockSpeed = HDMI_CEC_I2C_CLOCK_SPEED; - I2C_Init(HDMI_CEC_I2C, &I2C_InitStructure); -#endif - - /* Physical Address discovery */ - errorstatus = PhysicalAddressDiscovery(); - - if (errorstatus != HDMI_CEC_OK) - { - /* Device not connected (Physical Address lost) */ - return(errorstatus); - } - - - /* CEC DeInit */ - CEC_DeInit(); - - /* Configure CEC */ - CEC_InitStructure.CEC_BitTimingMode = CEC_BitTimingStdMode; - CEC_InitStructure.CEC_BitPeriodMode = CEC_BitPeriodStdMode; - CEC_Init(&CEC_InitStructure); - - /* Set Prescaler value for APB1 clock = 24MHz */ - CEC_SetPrescaler(0x4AF); - - /* Enable CEC */ - CEC_Cmd(ENABLE); - - /* Logical Address Allocation */ - sendcount = 0; - errorstatus = LogicalAddressAllocation(); - - while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5) - { - sendcount++; - errorstatus = LogicalAddressAllocation(); - } - - if (errorstatus != HDMI_CEC_OK) - { - /* Device Unregistred */ - return(errorstatus); - } - - HDMI_CEC_CheckConnectedDevices(); - - /* Set the CEC initiator address */ - CEC_OwnAddressConfig(MyLogicalAddress); - - /* Activate CEC interrupts associated to the set of RBTF,RERR, TBTF, TERR flags */ - CEC_ITConfig(ENABLE); - - /* Report physical address*/ - errorstatus = HDMI_CEC_ReportPhysicalAddress(); - sendcount = 0; - - while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5) - { - sendcount++; - errorstatus = HDMI_CEC_ReportPhysicalAddress(); - } - - if (errorstatus != HDMI_CEC_OK) - { - /* Device Unregistred */ - return(errorstatus); - } - - return errorstatus; -} - -/** - * @brief Transmit message by taking data from typedef struct CEC_Meassage - * @param CEC_TX_MessageStructure: pointer to an CEC_Message structure that contains - * the message to be sent. - * @retval HDMI_CEC_Error: CEC Error code - */ -HDMI_CEC_Error HDMI_CEC_TransmitMessage(HDMI_CEC_Message *HDMI_CEC_TX_MessageStructure) -{ - HDMI_CEC_Error errorstatus = HDMI_CEC_OK; - __IO uint32_t count = 0, j = 0; - - SendFrame = 0; - SendStatus = 0; - TxCounter = 0; - BufferCount = 0; - - HDMI_CEC_TX_MessageStructPrivate = *HDMI_CEC_TX_MessageStructure; - - /* Initialize BufferPointer */ - for (j = 0; j < 15; j++) - { - BufferPointer[j] = 0; - } - - BufferPointer[0] = HDMI_CEC_TX_MessageStructPrivate.Opcode; - - for (BufferCount = 1; BufferCount < HDMI_CEC_TX_MessageStructPrivate.TxMessageLength + 1; BufferCount++) - { - BufferPointer[BufferCount] = HDMI_CEC_TX_MessageStructPrivate.Operande[BufferCount-1]; - } - - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - - /* Write single Data in the TX Buffer to Transmit through the CEC peripheral */ - CEC_SendDataByte(HDMI_CEC_TX_MessageStructPrivate.Header); - - /* Initiate Message Transmission */ - CEC_StartOfMessage(); - - while ((SendFrame == 0) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - if (SendStatus == 0) - { - errorstatus = (HDMI_CEC_Error) TransErrorCode; - } - - return errorstatus; -} - - -/** - * @brief Get the ESR register status. - * @param None - * @retval HDMI_CEC_Error: CEC Error code - */ -HDMI_CEC_Error HDMI_CEC_GetErrorStatus (void) -{ - HDMI_CEC_Error errorstatus = HDMI_CEC_OK; - - /* Bit timing error case*/ - if (CEC_GetFlagStatus(CEC_FLAG_BTE) != RESET) - { - errorstatus = HDMI_CEC_BIT_TIMING; - } - /* Bit period error case */ - if (CEC_GetFlagStatus(CEC_FLAG_BPE) != RESET) - { - errorstatus = HDMI_CEC_BIT_PERIOD; - } - /* Recieve error case */ - if (CEC_GetFlagStatus(CEC_FLAG_RBTFE) != RESET) - { - errorstatus = HDMI_CEC_RX_BLOCK_FINISHED; - } - /* Start bit error case*/ - if (CEC_GetFlagStatus(CEC_FLAG_SBE) != RESET) - { - errorstatus = HDMI_CEC_START_BIT; - } - /* Acknowledge error case*/ - if (CEC_GetFlagStatus(CEC_FLAG_ACKE) != RESET) - { - errorstatus = HDMI_CEC_BLOCK_ACKNOWLEDGE; - } - /* Line error case */ - if (CEC_GetFlagStatus(CEC_FLAG_LINE) != RESET) - { - errorstatus = HDMI_CEC_LINE; - } - /* Transfert error case*/ - if (CEC_GetFlagStatus(CEC_FLAG_TBTFE) != RESET) - { - errorstatus = HDMI_CEC_TX_BLOCK_FINISHED; - } - /* Clear All errors */ - CEC_ClearFlag(CEC_FLAG_RERR); - CEC_ClearFlag(CEC_FLAG_TERR); - return errorstatus; -} - -/** - * @brief Allows to process all the interrupts that are high. - * @param None - * @retval None - */ -void HDMI_CEC_ProcessIRQSrc(void) -{ - /********************** Reception *********************************************/ - /* Check if a reception error occured */ - if (CEC_GetFlagStatus(CEC_FLAG_RERR)) - { - /* Set receive status bit (Error) */ - ReceiveStatus = 0; - ReceivedFrame = 1; - RecepErrorCode = HDMI_CEC_GetErrorStatus(); - CEC_ClearFlag(CEC_FLAG_RERR | CEC_FLAG_RSOM | CEC_FLAG_REOM | CEC_FLAG_RBTF); - } - else if (CEC_GetFlagStatus(CEC_FLAG_RBTF)) - { - /* Check if the byte received is the last one of the message */ - if (CEC_GetFlagStatus(CEC_FLAG_REOM)) - { - HDMI_CEC_RX_MessageStructPrivate.Operande[RxCounter-1] = CEC_ReceiveDataByte(); - HDMI_CEC_RX_MessageStructPrivate.RxMessageLength = RxCounter; - ReceiveStatus = SUCCESS; - ReceivedFrame = 1; - } - /* Check if the byte received is a Header */ - else if (CEC_GetFlagStatus(CEC_FLAG_RSOM)) - { - ReceiveStatus = 0; - HDMI_CEC_RX_MessageStructPrivate.Header = CEC_ReceiveDataByte(); - RxCounter = 0; - } - /* Receive each byte except header in the reception buffer */ - else - { - if (RxCounter != 0) - { - HDMI_CEC_RX_MessageStructPrivate.Operande[RxCounter-1] = CEC_ReceiveDataByte(); - RxCounter++; - } - else - { - HDMI_CEC_RX_MessageStructPrivate.Opcode = CEC_ReceiveDataByte(); - RxCounter++; - } - - } - /* Clear all reception flags */ - CEC_ClearFlag(CEC_FLAG_RSOM | CEC_FLAG_REOM | CEC_FLAG_RBTF); - } - - /********************** Transmission ******************************************/ - /* Check if a transmission error occured */ - if (CEC_GetFlagStatus(CEC_FLAG_TERR)) - { - TransErrorCode = HDMI_CEC_GetErrorStatus(); - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - SendFrame = 1; - SendStatus = 0; - } - /* Check if end of message bit is set in the data to be transmitted */ - else if (CEC_GetFlagStatus(CEC_FLAG_TEOM)) - { - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_RBTF); - CEC_EndOfMessageCmd(DISABLE); - SendFrame = 1; - SendStatus = SUCCESS; - } - /* Check if data byte has been sent */ - else if (CEC_GetFlagStatus(CEC_FLAG_TBTRF)) - { - /* Set EOM bit if the byte to be transmitted is the last one of the TransmitBuffer */ - if (TxCounter == (HDMI_CEC_TX_MessageStructPrivate.TxMessageLength)) - { - CEC_SendDataByte(BufferPointer[TxCounter]); - TxCounter++; - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(ENABLE); - } - else - { - /* Put the byte in the TX Buffer */ - CEC_SendDataByte(BufferPointer[TxCounter]); - TxCounter++; - CEC_ClearFlag(CEC_FLAG_TBTRF); - } - } -} - -/** - * @brief Report physical address to all other devices thus allowing any - device to create a map of the network. - * @param None - * @retval HDMI_CEC_Error: CEC Error code. - */ -HDMI_CEC_Error HDMI_CEC_ReportPhysicalAddress(void) -{ - HDMI_CEC_Error errorstatus = HDMI_CEC_OK; - HDMI_CEC_Message HDMI_CEC_TX_Message; - - HDMI_CEC_TX_Message.Header = ((MyLogicalAddress << 4) | 0xF); - HDMI_CEC_TX_Message.Opcode = HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS; - HDMI_CEC_TX_Message.Operande[0] = MyPhysicalAddress >> 8; - HDMI_CEC_TX_Message.Operande[1] = MyPhysicalAddress & 0xFF; - HDMI_CEC_TX_Message.Operande[2] = DeviceType; - HDMI_CEC_TX_Message.TxMessageLength = 0x03; - - errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_Message); - - return errorstatus; -} - -/** - * @brief Handle CEC command receive callback. - * When receiving the STANDBY Opcode commande, the system is entred in - * Stop mode and when wakeup, the PLL is configured as system clock and - * the HSI is selected as PLL source. - * @param None - * @retval None - */ -void HDMI_CEC_CommandCallBack(void) -{ - uint8_t i = 0, sendcount = 0; - HDMI_CEC_Error errorstatus = HDMI_CEC_OK; - EXTI_InitTypeDef EXTI_InitStructure; - - switch (HDMI_CEC_RX_MessageStructPrivate.Opcode) - { - case HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS: - HDMI_CEC_MapStruct.PhysicalAddress_A = HDMI_CEC_RX_MessageStructPrivate.Operande[1] >> 4; - HDMI_CEC_MapStruct.PhysicalAddress_B = HDMI_CEC_RX_MessageStructPrivate.Operande[1] & 0x0F; - HDMI_CEC_MapStruct.PhysicalAddress_C = HDMI_CEC_RX_MessageStructPrivate.Operande[0] >> 4; - HDMI_CEC_MapStruct.PhysicalAddress_D = HDMI_CEC_RX_MessageStructPrivate.Operande[0] & 0x0F; - HDMI_CEC_MapStruct.LogicalAddress = (HDMI_CEC_RX_MessageStructPrivate.Header >> 0x4) & 0x0F; - HDMI_CEC_MapStruct.DeviceType = HDMI_CEC_RX_MessageStructPrivate.Operande[2]; - HDMI_CEC_DeviceMap[DeviceCount] = HDMI_CEC_MapStruct; - HDMI_CEC_Follower_String[(HDMI_CEC_DeviceMap[DeviceCount].LogicalAddress)][1] = (uint8_t*)"1"; - DeviceCount++; - break; - - case HDMI_CEC_OPCODE_STANDBY: - /* CEC Line */ - GPIO_EXTILineConfig(GPIO_PortSourceGPIOB, GPIO_PinSource8); - /* Configure the CEC Line as EXTI Line on Falling Edge */ - EXTI_ClearITPendingBit(EXTI_Line8); - EXTI_InitStructure.EXTI_Line = EXTI_Line8; - EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStructure.EXTI_LineCmd = ENABLE; - EXTI_Init(&EXTI_InitStructure); - /* Request to enter Stop mode */ - PWR_EnterSTOPMode(PWR_Regulator_ON, PWR_STOPEntry_WFI); - - /* Disable the CEC EXTI Line */ - EXTI_InitStructure.EXTI_LineCmd = DISABLE; - EXTI_Init(&EXTI_InitStructure); - /* Configure the PLL Source */ - RCC_PLLConfig(RCC_PLLSource_HSI_Div2, RCC_PLLMul_6); - - /* Enable PLL */ - RCC_PLLCmd(ENABLE); - - /* Wait till PLL is ready */ - while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) - { - } - - /* Select PLL as system clock source */ - RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); - - /* Wait till PLL is used as system clock source */ - while(RCC_GetSYSCLKSource() != 0x08) - { - } - break; - - case HDMI_CEC_OPCODE_GET_CEC_VERSION: - /* Send the Used CEC version */ - HDMI_CEC_TX_MessageStructPrivate.Header = ((MyLogicalAddress << 4) | HDMI_CEC_RX_MessageStructPrivate.Header >> 4); - HDMI_CEC_TX_MessageStructPrivate.Opcode = HDMI_CEC_OPCODE_CEC_VERSION; - HDMI_CEC_TX_MessageStructPrivate.Operande[0] = HDMI_CEC_VERSION; /* CEC Version */ - HDMI_CEC_TX_MessageStructPrivate.TxMessageLength = 0x01; - errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate); - - /* Retransmit message until 5 time */ - while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5) - { - sendcount++; - errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate); - } - break; - - case HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS: - /* Send the Physical address */ - errorstatus = HDMI_CEC_ReportPhysicalAddress(); - sendcount = 0; - /* Retransmit message until 5 time */ - while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5) - { - sendcount++; - errorstatus = HDMI_CEC_ReportPhysicalAddress(); - } - break; - - case HDMI_CEC_OPCODE_FEATURE_ABORT: - /* The device doesn't support the requested message type, or that it cannot - execute it at the present time. */ - FeatureOpcode = HDMI_CEC_RX_MessageStructPrivate.Operande[0]; - AbortReason = HDMI_CEC_RX_MessageStructPrivate.Operande[1]; - break; - - case HDMI_CEC_OPCODE_GIVE_OSD_NAME: - /* Send the OSD name = STM32100E CEC*/ - HDMI_CEC_TX_MessageStructPrivate.Header = ((MyLogicalAddress << 4) | HDMI_CEC_RX_MessageStructPrivate.Header >> 4); - HDMI_CEC_TX_MessageStructPrivate.Opcode = HDMI_CEC_OPCODE_SET_OSD_NAME; - /* STM32100E*/ - HDMI_CEC_TX_MessageStructPrivate.Operande[0] = 0x53; - HDMI_CEC_TX_MessageStructPrivate.Operande[1] = 0x54; - HDMI_CEC_TX_MessageStructPrivate.Operande[2] = 0x4D; - HDMI_CEC_TX_MessageStructPrivate.Operande[3] = 0x33; - HDMI_CEC_TX_MessageStructPrivate.Operande[4] = 0x32; - HDMI_CEC_TX_MessageStructPrivate.Operande[5] = 0x31; - HDMI_CEC_TX_MessageStructPrivate.Operande[6] = 0x30; - HDMI_CEC_TX_MessageStructPrivate.Operande[7] = 0x30; - HDMI_CEC_TX_MessageStructPrivate.Operande[8] = 0x45; - HDMI_CEC_TX_MessageStructPrivate.Operande[9] = 0x20; - /* CEC */ - HDMI_CEC_TX_MessageStructPrivate.Operande[10] = 0x43; - HDMI_CEC_TX_MessageStructPrivate.Operande[11] = 0x45; - HDMI_CEC_TX_MessageStructPrivate.Operande[12] = 0x43; - HDMI_CEC_TX_MessageStructPrivate.TxMessageLength = 13; - errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate); - sendcount = 0; - /* Retransmit message until 5 time */ - while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5) - { - sendcount++; - errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate); - } - break; - - case HDMI_CEC_OPCODE_ROUTING_CHANGE: - for (i = 0;i < 0x14;i++) - { - if ((HDMI_CEC_DeviceMap[i].PhysicalAddress_A == HDMI_CEC_RX_MessageStructPrivate.Operande[1] >> 4) && - (HDMI_CEC_DeviceMap[i].PhysicalAddress_B == HDMI_CEC_RX_MessageStructPrivate.Operande[1]&0x0F) && - (HDMI_CEC_DeviceMap[i].PhysicalAddress_C == HDMI_CEC_RX_MessageStructPrivate.Operande[0] >> 4) && - (HDMI_CEC_DeviceMap[i].PhysicalAddress_D == HDMI_CEC_RX_MessageStructPrivate.Operande[0]&0x0F)) - { - HDMI_CEC_MapStruct.LogicalAddress = (HDMI_CEC_RX_MessageStructPrivate.Header >> 0x4) & 0x0F; - HDMI_CEC_MapStruct.DeviceType = HDMI_CEC_RX_MessageStructPrivate.Operande[2]; - HDMI_CEC_DeviceMap[i] = HDMI_CEC_MapStruct; - } - } - break; - - default: - /* Send Abort feature*/ - HDMI_CEC_TX_MessageStructPrivate.Header = ((MyLogicalAddress << 4) | HDMI_CEC_RX_MessageStructPrivate.Header >> 4); - HDMI_CEC_TX_MessageStructPrivate.Opcode = HDMI_CEC_OPCODE_FEATURE_ABORT; - HDMI_CEC_TX_MessageStructPrivate.Operande[0] = 0x02; /* defines command to be performed */ - HDMI_CEC_TX_MessageStructPrivate.Operande[1] = HDMI_CEC_REFUSED; /* Reason for abort feature */ - HDMI_CEC_TX_MessageStructPrivate.TxMessageLength = 0x02; - errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate); - sendcount = 0; - /* Retransmit message until 5 time */ - while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5) - { - sendcount++; - errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate); - } - break; - - } -} - -/** - * @brief Check the connected CEC devices. - * @param None - * @retval HDMI_CEC_Error - */ -HDMI_CEC_Error HDMI_CEC_CheckConnectedDevices(void) -{ - HDMI_CEC_Error errorstatus = HDMI_CEC_OK; - uint32_t count = 0, i = 1; - - /*----------------------------- TV device ---------------------------*/ - CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte((MyLogicalAddress << 4) | 0x0); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_OK) - { - HDMI_CEC_Follower_String[0][1] = (uint8_t*)"1"; - i++; - errorstatus = HDMI_CEC_OK; - } - - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - - /*----------------------------- Recording device 1 ---------------------------*/ - CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte((MyLogicalAddress << 4) | 0x1); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_OK) - { - HDMI_CEC_Follower_String[1][1] = (uint8_t*)"1"; - i++; - errorstatus = HDMI_CEC_OK; - } - - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - /*----------------------------- Recording device 2 ---------------------------*/ - CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte((MyLogicalAddress << 4) | 0x2); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_OK) - { - HDMI_CEC_Follower_String[2][1] = (uint8_t*)"1"; - i++; - errorstatus = HDMI_CEC_OK; - } - - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - - /*----------------------------- Tuner 1 ---------------------------*/ - CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte((MyLogicalAddress << 4) | 0x3); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_OK) - { - HDMI_CEC_Follower_String[3][1] = (uint8_t *)"1"; - i++; - errorstatus = HDMI_CEC_OK; - } - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - /*----------------------------- Playback device 1 ---------------------------*/ - CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte((MyLogicalAddress << 4) | 0x4); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_OK) - { - HDMI_CEC_Follower_String[4][1] = (uint8_t *)"1"; - i++; - errorstatus = HDMI_CEC_OK; - } - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - - /*----------------------------- Audio system ---------------------------*/ - CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte((MyLogicalAddress << 4) | 0x5); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_OK) - { - HDMI_CEC_Follower_String[5][1] = (uint8_t *)"1"; - i++; - errorstatus = HDMI_CEC_OK; - } - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - - /*----------------------------- Tuner 2 ---------------------------*/ - CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte((MyLogicalAddress << 4) | 0x6); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_OK) - { - HDMI_CEC_Follower_String[6][1] = (uint8_t *)"1"; - i++; - errorstatus = HDMI_CEC_OK; - } - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - - /*----------------------------- Tuner 3 ---------------------------*/ - CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte((MyLogicalAddress << 4) | 0x7); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_OK) - { - HDMI_CEC_Follower_String[7][1] = (uint8_t *)"1"; - i++; - errorstatus = HDMI_CEC_OK; - } - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - - /*----------------------------- Playback device 2 ---------------------------*/ - CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte((MyLogicalAddress << 4) | 0x8); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_OK) - { - HDMI_CEC_Follower_String[8][1] = (uint8_t *)"1"; - i++; - errorstatus = HDMI_CEC_OK; - } - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - - /*----------------------------- Recording device 3 ---------------------------*/ - CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte((MyLogicalAddress << 4) | 0x9); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_OK) - { - HDMI_CEC_Follower_String[9][1] = (uint8_t *)"1"; - i++; - errorstatus = HDMI_CEC_OK; - } - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - /*----------------------------- Tuner 4 ---------------------------*/ - CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte((MyLogicalAddress << 4) | 0xA); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_OK) - { - HDMI_CEC_Follower_String[10][1] = (uint8_t *)"1"; - i++; - errorstatus = HDMI_CEC_OK; - } - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - /*----------------------------- Playback device 3 ---------------------------*/ - CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte((MyLogicalAddress << 4) | 0xB); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_OK) - { - HDMI_CEC_Follower_String[11][1] = (uint8_t *)"1"; - i++; - errorstatus = HDMI_CEC_OK; - } - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - - CECDevicesNumber = i - 1; - - return errorstatus; -} - -/** - * @brief Physical address discovery. - * @param None - * @retval HDMI_CEC_Error: CEC Error code. - */ -static HDMI_CEC_Error PhysicalAddressDiscovery(void) -{ - HDMI_CEC_Error errorstatus = HDMI_CEC_OK; -#ifdef HDMI_CEC_USE_DDC - uint32_t index = 0, i = 0; -#endif - - /*------------------------------ Physical address discovery -----------------*/ - if (HDMI_CEC_ROOT == 0x1) - { - MyPhysicalAddress = 0x0000; - /* The HDMI-CEC here is configured as sink or as a repeater. The configuration - of the +5V power signal and the HPD should be well configured. - Implement here the EDID Structure to be sent to the HDMI source. - For more details please refer to the HDMI specification. - The EDID structure should be sent to the device source using the DDC Channel - and using the HPD signal. */ - } - else - { - -#ifdef HDMI_CEC_USE_DDC - /* The HDMI-CEC here is configured as source or as a repeater. The configuration - of the +5V power signal and the HPD should be well configured. - The source should wait for HPD and then read the EDID structure. */ - while(GPIO_ReadInputDataBit(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN) == RESET) - { - } - /* Wait for 100 ms after HPD was received */ - for(i = 0; i < 0x5FFFF; i++) - { - } - - /* Return the physical address using the I2C by reading the 2 bytes 24 and - 25 form the EDID */ - /* Read the EDID Block 0 and EDID Block 1 at address 0xA0 */ - /*!< While the bus is busy */ - while(I2C_GetFlagStatus(HDMI_CEC_I2C, I2C_FLAG_BUSY)) - { - } - - /*!< Send START condition */ - I2C_GenerateSTART(HDMI_CEC_I2C, ENABLE); - - /*!< Test on EV5 and clear it */ - while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_MODE_SELECT)) - { - } - - /*!< Send EEPROM address for write */ - I2C_Send7bitAddress(HDMI_CEC_I2C, 0xA0, I2C_Direction_Transmitter); - - - /*!< Test on EV6 and clear it */ - while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) - { - } - - /*!< Send the EEPROM's internal address to read from: Only one byte address */ - I2C_SendData(HDMI_CEC_I2C, 0x00); - - /*!< Test on EV8 and clear it */ - while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED)) - { - } - - /*!< Send STRAT condition a second time */ - I2C_GenerateSTART(HDMI_CEC_I2C, ENABLE); - - /*!< Test on EV5 and clear it */ - while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_MODE_SELECT)) - { - } - - /*!< Send EEPROM address for read */ - I2C_Send7bitAddress(HDMI_CEC_I2C, 0xA1, I2C_Direction_Receiver); - - /*!< Test on EV6 and clear it */ - while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)) - { - } - - /* While there is data to be read */ - while (NumByteToRead-- > 1) - { - while(I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_BYTE_RECEIVED)) - { - } - for(i = 0; i < 0xFFF; i++) - { - } - pBuffer[index++] = I2C_ReceiveData(HDMI_CEC_I2C); - } - - /* Disable Acknowledgement */ - I2C_AcknowledgeConfig(HDMI_CEC_I2C, DISABLE); - - /* Send STOP Condition */ - I2C_GenerateSTOP(HDMI_CEC_I2C, ENABLE); - - while(I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_BYTE_RECEIVED)); - pBuffer[index] = I2C_ReceiveData(HDMI_CEC_I2C); - - /* Enable Acknowledgement to be ready for another reception */ - I2C_AcknowledgeConfig(HDMI_CEC_I2C, ENABLE); - MyPhysicalAddress = ((pBuffer[138] << 8) | pBuffer[137]); -#else - MyPhysicalAddress = 0x1000; -#endif - } - - return errorstatus; -} -/** - * @brief Allocate the logical address. - * @param None - * @retval HDMI_CEC_Error: CEC Error code. - */ -static HDMI_CEC_Error LogicalAddressAllocation(void) -{ - HDMI_CEC_Error errorstatus = HDMI_CEC_OK; - uint32_t count = 0; - - /*------------------ Logical address allocation -----------------------------*/ - /* Get the device type */ - /* Device type = CEC_TV */ - if (DeviceType == HDMI_CEC_TV) - { - if (HDMI_CEC_ROOT) - { - MyLogicalAddress = 0x00; - } - else - { - CEC_OwnAddressConfig(0xE); /* Own address = 0xE */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte(0xEE); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the polling message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE) - { - MyLogicalAddress = 0x0E; - errorstatus = HDMI_CEC_OK; - } - else if (errorstatus == HDMI_CEC_OK) - { - MyLogicalAddress = 0x0F; - errorstatus = HDMI_CEC_DEVICE_UNREGISTRED; - } - } - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF); - CEC_EndOfMessageCmd(DISABLE); - } - - /* Device type = CEC_RECORDING */ - if (DeviceType == HDMI_CEC_RECORDING) - { - CEC_OwnAddressConfig(0x1); /* Own address = 0x1 */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte(0x11); - - /* Start of message */ - CEC_StartOfMessage(); - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE) - { - MyLogicalAddress = 0x01; - errorstatus = HDMI_CEC_OK; - } - else if (errorstatus == HDMI_CEC_OK) - { - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - - CEC_EndOfMessageCmd(DISABLE); - - CEC_OwnAddressConfig(0x2); /* Own address = 0x2 */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte(0x22); - - /* Start of message */ - CEC_StartOfMessage(); - - count = 0; - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE) - { - MyLogicalAddress = 0x02; - errorstatus = HDMI_CEC_OK; - } - else if (errorstatus == HDMI_CEC_OK) - { - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - - CEC_EndOfMessageCmd(DISABLE); - - CEC_OwnAddressConfig(0x9); /* Own address = 0x9 */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte(0x99); - - /* Start of message */ - CEC_StartOfMessage(); - - count = 0; - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE) - { - MyLogicalAddress = 0x09; - errorstatus = HDMI_CEC_OK; - } - else if (errorstatus == HDMI_CEC_OK) - { - MyLogicalAddress = 0x0F; - errorstatus = HDMI_CEC_DEVICE_UNREGISTRED; - } - } - } - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - CEC_EndOfMessageCmd(DISABLE); - } - - /* Device type = CEC_TUNER */ - if (DeviceType == HDMI_CEC_TUNER) - { - CEC_OwnAddressConfig(0x3); /* Own address = 0x3 */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte(0x33); - - /* Start of message */ - CEC_StartOfMessage(); - - count = 0; - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE) - { - MyLogicalAddress = 0x03; - errorstatus = HDMI_CEC_OK; - } - else if (errorstatus == HDMI_CEC_OK) - { - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - - CEC_EndOfMessageCmd(DISABLE); - - CEC_OwnAddressConfig(0x6); /* Own address = 0x6 */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte(0x66); - - /* Start of message */ - CEC_StartOfMessage(); - - count = 0; - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE) - { - MyLogicalAddress = 0x06; - errorstatus = HDMI_CEC_OK; - } - else if (errorstatus == HDMI_CEC_OK) - { - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - - CEC_EndOfMessageCmd(DISABLE); - - CEC_OwnAddressConfig(0x7); /* Own address = 0x7 */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte(0x77); - - /* Start of message */ - CEC_StartOfMessage(); - - count = 0; - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE) - { - MyLogicalAddress = 0x07; - errorstatus = HDMI_CEC_OK; - } - else if (errorstatus == HDMI_CEC_OK) - { - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - - CEC_EndOfMessageCmd(DISABLE); - - CEC_OwnAddressConfig(0xA); /* Own address = 0xA */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte(0xAA); - - /* Start of message */ - CEC_StartOfMessage(); - - count = 0; - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE) - { - MyLogicalAddress = 0x0A; - errorstatus = HDMI_CEC_OK; - } - else if (errorstatus == HDMI_CEC_OK) - { - MyLogicalAddress = 0x0F; - errorstatus = HDMI_CEC_DEVICE_UNREGISTRED; - } - } - } - } - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - CEC_EndOfMessageCmd(DISABLE); - } - - /* Device type = CEC_PLAYBACK */ - if (DeviceType == HDMI_CEC_PLAYBACK) - { - CEC_OwnAddressConfig(0x4); /* Own address = 0x4 */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte(0x44); - - /* Start of message */ - CEC_StartOfMessage(); - - count = 0; - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE) - { - MyLogicalAddress = 0x04; - errorstatus = HDMI_CEC_OK; - } - else if (errorstatus == HDMI_CEC_OK) - { - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - - CEC_EndOfMessageCmd(DISABLE); - - CEC_OwnAddressConfig(0x8); /* Own address = 0x8 */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte(0x88); - - /* Start of message */ - CEC_StartOfMessage(); - - count = 0; - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE) - { - MyLogicalAddress = 0x08; - errorstatus = HDMI_CEC_OK; - } - else if (errorstatus == HDMI_CEC_OK) - { - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - - CEC_EndOfMessageCmd(DISABLE); - - CEC_OwnAddressConfig(0xB); /* Own address = 0xBB */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte(0xBB); - - /* Start of message */ - CEC_StartOfMessage(); - - count = 0; - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE) - { - MyLogicalAddress = 0x0B; - errorstatus = HDMI_CEC_OK; - } - else if (errorstatus == HDMI_CEC_OK) - { - MyLogicalAddress = 0x0F; - errorstatus = HDMI_CEC_DEVICE_UNREGISTRED; - } - } - } - - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - CEC_EndOfMessageCmd(DISABLE); - } - - /* Device type = CEC Audio System */ - if (DeviceType == HDMI_CEC_AUDIOSYSTEM) - { - CEC_OwnAddressConfig(0x5); /* Own address = 0x5 */ - - CEC_EndOfMessageCmd(ENABLE); - - CEC_SendDataByte(0x55); - - /* Start of message */ - CEC_StartOfMessage(); - - count = 0; - - /* Wait till the header message is sent */ - while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE)) - { - count++; - } - - if (count >= HDMI_CEC_TIMEOUT_VALUE) - { - errorstatus = HDMI_CEC_TIMEOUT; - return(errorstatus); - } - - errorstatus = HDMI_CEC_GetErrorStatus(); - - if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE) - { - MyLogicalAddress = 0x05; - errorstatus = HDMI_CEC_OK; - } - else if (errorstatus == HDMI_CEC_OK) - { - MyLogicalAddress = 0x0F; - errorstatus = HDMI_CEC_DEVICE_UNREGISTRED; - } - - /* Clear CEC CSR register */ - CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR); - CEC_EndOfMessageCmd(DISABLE); - } - - return errorstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - - diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_cec.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_cec.h deleted file mode 100644 index e98c82c46..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_cec.h +++ /dev/null @@ -1,290 +0,0 @@ -/** - ****************************************************************************** - * @file stm32100e_eval_cec.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains all the functions prototypes for the stm32100e_eval_cec - * firmware driver. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32100E_EVAL_CEC_H -#define __STM32100E_EVAL_CEC_H - -#ifdef __cplusplus -extern "C" -{ -#endif - - /* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32100E_EVAL - * @{ - */ - -/** @defgroup STM32100E_EVAL_CEC - * @{ - */ - -/** @defgroup STM32100E_EVAL_CEC_Exported_Types - * @{ - */ -typedef enum -{ - HDMI_CEC_BIT_TIMING = (1), /*!< CEC Bit Timing Error */ - HDMI_CEC_BIT_PERIOD = (2), /*!< CEC Bit Period Error */ - HDMI_CEC_RX_BLOCK_FINISHED = (3), /*!< CEC Receive Block finished Error */ - HDMI_CEC_START_BIT = (4), /*!< CEC Start Bit Error */ - HDMI_CEC_BLOCK_ACKNOWLEDGE = (5), /*!< CEC Block Acknowledge Error */ - HDMI_CEC_LINE = (6), /*!< CEC Line Error */ - HDMI_CEC_TX_BLOCK_FINISHED = (7), /*!< CEC Transmit Block Transfer finished Error */ - HDMI_CEC_DEVICE_UNREGISTRED = (8), /*!< CEC Device Unregistred */ - HDMI_CEC_TIMEOUT = (9), /*!< CEC TimeOut */ - HDMI_CEC_OK = (10) /*!< CEC OK */ -}HDMI_CEC_Error; - -typedef struct -{ - __IO uint8_t PhysicalAddress_A; - __IO uint8_t PhysicalAddress_B; - __IO uint8_t PhysicalAddress_C; - __IO uint8_t PhysicalAddress_D; - __IO uint8_t LogicalAddress; - __IO uint8_t DeviceType; -}HDMI_CEC_Map; - - -#define HDMI_CEC_TX_MESSAGE_LENGTH_MAX ((uint32_t)0x0000000E) -#define HDMI_CEC_TIMEOUT_VALUE ((uint32_t)0x001FFFFF) - -/** -* @brief CEC Init Structure definition -*/ -typedef struct -{ - __IO uint8_t Header; - __IO uint8_t Opcode; - __IO uint8_t Operande[HDMI_CEC_TX_MESSAGE_LENGTH_MAX]; - __IO uint8_t TxMessageLength; - __IO uint8_t RxMessageLength; -}HDMI_CEC_Message; - -/** -* @} -*/ - -/** @defgroup STM32100E_EVAL_CEC_Exported_Constants - * @{ - */ - -/** - * @brief CEC device types - */ -#define HDMI_CEC_TV 0x00 -#define HDMI_CEC_RECORDING 0x01 -#define HDMI_CEC_TUNER 0x03 -#define HDMI_CEC_PLAYBACK 0x04 -#define HDMI_CEC_AUDIOSYSTEM 0x05 - - -/** - * @brief HDMI CEC I2C Interface pins - */ -#define HDMI_CEC_I2C_SCL_PIN GPIO_Pin_6 -#define HDMI_CEC_I2C_SDA_PIN GPIO_Pin_7 -#define HDMI_CEC_I2C_GPIO_PORT GPIOB -#define HDMI_CEC_I2C_GPIO_CLK RCC_APB2Periph_GPIOB -#define HDMI_CEC_I2C I2C1 -#define HDMI_CEC_I2C_CLK RCC_APB1Periph_I2C1 - -/** - * @brief HDMI CEC HPD (Hot Plug Detect) Interface pin - */ -#define HDMI_CEC_HPD_PIN GPIO_Pin_9 -#define HDMI_CEC_HPD_GPIO_PORT GPIOB -#define HDMI_CEC_HPD_GPIO_CLK RCC_APB2Periph_GPIOB - -/** - * @brief HDMI CEC Interface pin - */ -#define HDMI_CEC_LINE_PIN GPIO_Pin_8 -#define HDMI_CEC_LINE_GPIO_PORT GPIOB -#define HDMI_CEC_LINE_GPIO_CLK RCC_APB2Periph_GPIOB - -#define HDMI_CEC_I2C_SLAVE_ADDRESS7 0xA0 -#define HDMI_CEC_I2C_CLOCK_SPEED 100000 - -/** - * @brief HDMI CEC Root (Mainly for TV with a fixed physical address (0.0.0.0)) - * If you want to configure the STM32100E-EVAL board as CEC Root (Sink) - * change the following define to 0x1 - */ -#define HDMI_CEC_ROOT 0x00 - -/** - * @brief To select if the DDC Channel will be used for physical address discovery - * or not. To use the DDC Channel to read the EDID structure uncomment - * the following line. - * If the device is configured as HMDI source it should read his own physical - * address from the sink that is connected to. - */ -/* #define HDMI_CEC_USE_DDC */ - -/** - * @brief CEC version: V1.3a - */ -#define HDMI_CEC_VERSION 0x04 - -/** - * @brief Reason for Abort feature - */ -#define HDMI_CEC_UNRECOGNIZED_OPCODE 0x00 -#define HDMI_CEC_NOT_CORRECT_MODETORESPOND 0x01 -#define HDMI_CEC_CANNOTPROVIDE_SOURCE 0x02 -#define HDMI_CEC_INVALID_OPERAND 0x03 -#define HDMI_CEC_REFUSED 0x04 - -/** - * @brief HDMI CEC specific commands - */ -#define HDMI_CEC_OPCODE_ACTIVE_SOURCE ((uint8_t) 0x82) -#define HDMI_CEC_OPCODE_IMAGE_VIEW_ON ((uint8_t) 0x04) -#define HDMI_CEC_OPCODE_TEXT_VIEW_ON ((uint8_t) 0x0D) -#define HDMI_CEC_OPCODE_INACTIVE_SOURCE ((uint8_t) 0x9D) -#define HDMI_CEC_OPCODE_REQUEST_ACTIVE_SOURCE ((uint8_t) 0x85) -#define HDMI_CEC_OPCODE_ROUTING_CHANGE ((uint8_t) 0x80) -#define HDMI_CEC_OPCODE_ROUTING_INFORMATION ((uint8_t) 0x81) -#define HDMI_CEC_OPCODE_SET_STREAM_PATH ((uint8_t) 0x86) -#define HDMI_CEC_OPCODE_STANDBY ((uint8_t) 0x36) -#define HDMI_CEC_OPCODE_RECORD_OFF ((uint8_t) 0x0B) -#define HDMI_CEC_OPCODE_RECORD_ON ((uint8_t) 0x09) -#define HDMI_CEC_OPCODE_RECORD_STATUS ((uint8_t) 0x0A) -#define HDMI_CEC_OPCODE_RECORD_TV_SCREEN ((uint8_t) 0x0F) -#define HDMI_CEC_OPCODE_CLEAR_ANALOGUE_TIMER ((uint8_t) 0x33) -#define HDMI_CEC_OPCODE_CLEAR_DIGITAL_TIMER ((uint8_t) 0x99) -#define HDMI_CEC_OPCODE_CLEAR_EXTERNAL_TIMER ((uint8_t) 0xA1) -#define HDMI_CEC_OPCODE_SET_ANALOGUE_TIMER ((uint8_t) 0x34) -#define HDMI_CEC_OPCODE_SET_DIGITAL_TIMER ((uint8_t) 0x97) -#define HDMI_CEC_OPCODE_SET_EXTERNAL_TIMER ((uint8_t) 0xA2) -#define HDMI_CEC_OPCODE_SET_TIMER_PROGRAM_TITLE ((uint8_t) 0x67) -#define HDMI_CEC_OPCODE_TIMER_CLEARED_STATUS ((uint8_t) 0x43) -#define HDMI_CEC_OPCODE_TIMER_STATUS ((uint8_t) 0x35) -#define HDMI_CEC_OPCODE_CEC_VERSION ((uint8_t) 0x9E) -#define HDMI_CEC_OPCODE_GET_CEC_VERSION ((uint8_t) 0x9F) -#define HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS ((uint8_t) 0x83) -#define HDMI_CEC_OPCODE_GET_MENU_LANGUAGE ((uint8_t) 0x91) -#define HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS ((uint8_t) 0x84) -#define HDMI_CEC_OPCODE_SET_MENU_LANGUAGE ((uint8_t) 0x32) -#define HDMI_CEC_OPCODE_DECK_CONTROL ((uint8_t) 0x42) -#define HDMI_CEC_OPCODE_DECK_STATUS ((uint8_t) 0x1B) -#define HDMI_CEC_OPCODE_GIVE_DECK_STATUS ((uint8_t) 0x1A) -#define HDMI_CEC_OPCODE_PLAY ((uint8_t) 0x41) -#define HDMI_CEC_OPCODE_GIVE_TUNER_DEVICE_STATUS ((uint8_t) 0x08) -#define HDMI_CEC_OPCODE_SELECT_ANALOGUE_SERVICE ((uint8_t) 0x92) -#define HDMI_CEC_OPCODE_SELECT_DIGITAL_SERVICE ((uint8_t) 0x93) -#define HDMI_CEC_OPCODE_TUNER_DEVICE_STATUS ((uint8_t) 0x07) -#define HDMI_CEC_OPCODE_TUNER_STEP_DECREMENT ((uint8_t) 0x06) -#define HDMI_CEC_OPCODE_TUNER_STEP_INCREMENT ((uint8_t) 0x05) -#define HDMI_CEC_OPCODE_DEVICE_VENDOR_ID ((uint8_t) 0x87) -#define HDMI_CEC_OPCODE_GIVE_DEVICE_VENDOR_ID ((uint8_t) 0x8C) -#define HDMI_CEC_OPCODE_VENDOR_COMMAND ((uint8_t) 0x89) -#define HDMI_CEC_OPCODE_VENDOR_COMMAND_WITH_ID ((uint8_t) 0xA0) -#define HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_DOWN ((uint8_t) 0x8A) -#define HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_UP ((uint8_t) 0x8B) -#define HDMI_CEC_OPCODE_SET_OSD_STRING ((uint8_t) 0x64) -#define HDMI_CEC_OPCODE_GIVE_OSD_NAME ((uint8_t) 0x46) -#define HDMI_CEC_OPCODE_SET_OSD_NAME ((uint8_t) 0x47) -#define HDMI_CEC_OPCODE_MENU_REQUEST ((uint8_t) 0x8D) -#define HDMI_CEC_OPCODE_MENU_STATUS ((uint8_t) 0x8E) -#define HDMI_CEC_OPCODE_USER_CONTROL_PRESSED ((uint8_t) 0x44) -#define HDMI_CEC_OPCODE_USER_CONTROL_RELEASED ((uint8_t) 0x45) -#define HDMI_CEC_OPCODE_GIVE_DEVICE_POWER_STATUS ((uint8_t) 0x8F) -#define HDMI_CEC_OPCODE_REPORT_POWER_STATUS ((uint8_t) 0x90) -#define HDMI_CEC_OPCODE_FEATURE_ABORT ((uint8_t) 0x00) -#define HDMI_CEC_OPCODE_ABORT ((uint8_t) 0xFF) -#define HDMI_CEC_OPCODE_GIVE_AUDIO_STATUS ((uint8_t) 0x71) -#define HDMI_CEC_OPCODE_GIVE_SYSTEM_AUDIO_MODE_STATUS ((uint8_t) 0x7D) -#define HDMI_CEC_OPCODE_REPORT_AUDIO_STATUS ((uint8_t) 0x7A) -#define HDMI_CEC_OPCODE_SET_SYSTEM_AUDIO_MODE ((uint8_t) 0x72) -#define HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_REQUEST ((uint8_t) 0x70) -#define HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_STATUS ((uint8_t) 0x7E) -#define HDMI_CEC_OPCODE_SET_AUDIO_RATE ((uint8_t) 0x9A) - - -/** - * @} - */ - -/** @defgroup STM32100E_EVAL_CEC_Exported_Macros - * @{ - */ -/* HDMI_CEC_HPD: HDMI HPD pin low */ -#define HDMI_CEC_HPD_LOW() GPIO_ResetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN) -/* HDMI_CEC_HPD: HDMI HPD pin high */ -#define HDMI_CEC_HPD_HIGH() GPIO_SetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN) - -/** - * @} - */ - -/** @defgroup STM32100E_EVAL_CEC_Exported_Functions - * @{ - */ -HDMI_CEC_Error HDMI_CEC_Init(void); -HDMI_CEC_Error HDMI_CEC_TransmitMessage(HDMI_CEC_Message *HDMI_CEC_TX_MessageStructure); -HDMI_CEC_Error HDMI_CEC_GetErrorStatus (void); -void HDMI_CEC_ProcessIRQSrc(void); -HDMI_CEC_Error HDMI_CEC_ReportPhysicalAddress(void); -void HDMI_CEC_CommandCallBack(void); -HDMI_CEC_Error HDMI_CEC_CheckConnectedDevices(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32100E_EVAL_CEC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_onenand.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_onenand.c deleted file mode 100644 index 6f9442071..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_onenand.c +++ /dev/null @@ -1,482 +0,0 @@ -/** - ****************************************************************************** - * @file stm32100e_eval_fsmc_onenand.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file provides a set of functions needed to drive the - * KFG1216U2A/B-DIB6 OneNAND memory mounted on STM32100E-EVAL board. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32100e_eval_fsmc_onenand.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32100E_EVAL - * @{ - */ - -/** @addtogroup STM32100E_EVAL_FSMC_ONENAND - * @brief This file provides a set of functions needed to drive the - * KFG1216x2A-xxB5 OneNAND memory mounted on STM32100E-EVAL board. - * @{ - */ - -/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Defines - * @{ - */ -#define BANK1_ONENAND1_ADDR ((uint32_t)0x60000000) -#define ONENAND_BOOTPARTITION_ADDR ((uint32_t)BANK1_ONENAND1_ADDR) - - -/** - * @} - */ - -/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Macros - * @{ - */ -#define OneNAND_WRITE(Address, Data) (*(__IO uint16_t *)(Address) = (Data)) - -/** - * @} - */ - - -/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Variables - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Function_Prototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Functions - * @{ - */ - -/** - * @brief Configures the FSMC and GPIOs to interface with the OneNAND memory. - * This function must be called before any write/read operation on the - * OneNAND. - * @param None - * @retval None - */ -void OneNAND_Init(void) -{ - FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; - FSMC_NORSRAMTimingInitTypeDef p; - GPIO_InitTypeDef GPIO_InitStructure; - - - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE); - -/*-- GPIO Configuration ------------------------------------------------------*/ - /* OneNAND Data lines configuration */ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE | - RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO, ENABLE); - -/*-- GPIO Configuration ------------------------------------------------------*/ - /*!< OneNAND Data lines configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 | - GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | - GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | - GPIO_Pin_15; - GPIO_Init(GPIOE, &GPIO_InitStructure); - - /*!< OneNAND Address lines configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | - GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | - GPIO_Pin_14 | GPIO_Pin_15; - GPIO_Init(GPIOF, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | - GPIO_Pin_4 | GPIO_Pin_5; - GPIO_Init(GPIOG, &GPIO_InitStructure); - - /*!< CLK, NOE and NWE configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 |GPIO_Pin_5; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - /*!< NE1 configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - /*!< NL configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; - GPIO_Init(GPIOB, &GPIO_InitStructure); - GPIO_PinRemapConfig(GPIO_Remap_FSMC_NADV, DISABLE); - - /*!< NWAIT configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - /*-- FSMC Configuration ----------------------------------------------------*/ - p.FSMC_AddressSetupTime = 0x01; - p.FSMC_AddressHoldTime = 0x00; - p.FSMC_DataSetupTime = 0x05; - p.FSMC_BusTurnAroundDuration = 0x02; - p.FSMC_CLKDivision = 0x1; - p.FSMC_DataLatency = 0x01; - p.FSMC_AccessMode = FSMC_AccessMode_B; - - FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM1; - FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; - FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_NOR; - FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; - FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Enable; - FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Enable; - FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; - FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; - - FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); - FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE); -} - -/** - * @brief Resets the OneNAND memory. - * @param None - * @retval None - */ -void OneNAND_Reset(void) -{ - OneNAND_WRITE(ONENAND_BOOTPARTITION_ADDR, OneNAND_CMD_RESET); -} - -/** - * @brief Reads OneNAND memory's Manufacturer and Device Code. - * @param OneNAND_ID: pointer to a OneNAND_IDTypeDef structure which will hold - * the Manufacturer and Device Code. - * @retval None - */ -void OneNAND_ReadID(OneNAND_IDTypeDef* OneNAND_ID) -{ - uint16_t status = 0x0; - - /* Wait till no ongoing operation */ - status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); - - while((status & 0x8000) == 0x8000) - { - status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); - } - - /* Read ID data */ - OneNAND_ID->Manufacturer_ID = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_MANUFACTERID); - OneNAND_ID->Device_ID = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_DEVICEID); - - *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION) = 0x40E0; -} - -/** - * @brief Unlocks the specified OneNAND memory block (128Kb). - * @param BlockNumber: specifies the block number to be erased. This parameter - * should be between 0 and 511. - * @retval OneNAND memory Interrupt Status. - */ -uint16_t OneNAND_UnlockBlock(uint32_t BlockNumber) -{ - uint16_t status = 0; - - /* Wait till no ongoing operation */ - status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); - - while((status & 0x8000) == 0x8000) - { - status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); - } - - *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBLOCKADDRESS) = BlockNumber; - *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000; - *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_UNLOCK; - - /* Wait till the command is completed */ - status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT); - - while((status & 0x8000) != 0x8000) - { - status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT); - } - - /* Get the Controller Status */ - status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); - - return (status); -} - -/** - * @brief Erases the specified OneNAND memory block (128Kb). - * @param BlockNumber: specifies the block number to be erased. This parameter - * should be between 0 and 511. - * @retval OneNAND memory Interrupt Status. - */ -uint16_t OneNAND_EraseBlock(uint32_t BlockNumber) -{ - uint16_t status = 0x0; - - /* Wait till no ongoing operation */ - status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); - - while((status & 0x8000) == 0x8000) - { - status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); - } - - /* Erase operation */ - *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = BlockNumber; - *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000; - *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_ERASE; - - /* Wait till no error is generated */ - status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); - - while((status & 0x0400) == 0x0400) - { - status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); - } - - /* Wait till the command is completed */ - status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT); - - while((status & 0x8000) != 0x8000) - { - status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT); - } - - /* Get the Controller Status */ - status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); - - return (status); -} - -/** - * @brief Writes a Half-word buffer to the OneNAND memory. - * @param pBuffer: pointer to buffer. - * @param WriteAddr: OneNAND memory internal address from which the data will be - * written. - * @param NumHalfwordToWrite: number of half-words to write. - * @retval OneNAND memory Controller Status. - */ -uint16_t OneNAND_WriteBuffer(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToWrite) -{ - uint32_t datacounter = 0; - uint16_t status = 0; - - /* Load the buffer to be written into the DATA RAM0*/ - for(datacounter = 0; datacounter < NumHalfwordToWrite; datacounter++) - { - *(__IO uint16_t *)((BANK1_ONENAND1_ADDR + OneNAND_DATA_RAM_0_0_ADD) + (2*datacounter)) = pBuffer[datacounter]; - } - - /* Write operation from DATA RAM0 to NAND address*/ - *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = Address.Block; /* NAND Flash block address*/ - *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESINT8_T) = (uint16_t)(Address.Page << 2); /* NAND Flash start page address */ - *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBUFFER) = OneNAND_DATA_RAM_0_0_REG;/* BufferRAM Sector Count (BSC) and BufferRAM Sector Address (BSA).*/ - *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000; - *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_PROGRAM; /* Command */ - - /* Wait till the command is completed */ - status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT); - - while((status & 0x8000) != 0x8000) - { - status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT); - } - - /* Wait till the write interrupt is set */ - status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT); - - while((status & 0x40) != 0x40) - { - status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT); - } - - /* Get the Controller Status */ - status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); - - return (status); -} - -/** - * @brief Reads a block of data from the OneNAND memory using asynchronous mode. - * @param pBuffer: pointer to the buffer that receives the data read from the - * OneNAND memory. - * @param ReadAddr: OneNAND memory internal address to read from. - * @param NumHalfwordToRead: number of half-words to read. - * @retval None - */ -void OneNAND_AsynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead) -{ - uint16_t datatmp = 0x0, index = 0; - uint16_t status = 0; - - datatmp = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION); - - /* Set the asynchronous read mode */ - OneNAND_WRITE(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION, (datatmp& 0x7FFF)); - - /* Load data from the read address to the DATA RAM 1 setor 1 */ - *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = Address.Block; /* NAND Flash block address*/ - *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESINT8_T) = (uint16_t)(Address.Page << 2); - *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBUFFER) = OneNAND_DATA_RAM_1_0_REG; - *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000; - *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_LOAD; /* Command */ - - /* Wait till the command is completed */ - status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT); - - while((status & 0x8000) != 0x8000) - { - status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT); - } - - /* Read Controller status */ - status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); - - /* Read data */ - for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /* While there is data to read */ - { - /* Read a Halfword from the memory */ - *pBuffer++ = *(__IO uint16_t *)((BANK1_ONENAND1_ADDR + OneNAND_DATA_RAM_1_0_ADD)+ 2*index); - index++; - } -} - -/** - * @brief Reads a block of data from the OneNAND memory using synchronous mode. - * @param pBuffer: pointer to the buffer that receives the data read from the - * OneNAND memory. - * @param ReadAddr: OneNAND memory internal address to read from. - * @param NumHalfwordToRead: number of half-words to read. - * @retval None - */ -void OneNAND_SynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead) -{ - uint16_t index = 0; - uint16_t status = 0; - - /* Set the asynchronous read mode */ - OneNAND_WRITE(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION, 0xB4C0); - - - /* Load data from the read address to the DATA RAM 1 setor 1 */ - *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = Address.Block; /* NAND Flash block address*/ - *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESINT8_T) = (uint16_t)(Address.Page << 2); - *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBUFFER) = OneNAND_DATA_RAM_1_0_REG; - *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000; - *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_LOAD; /* Command */ - - /* Wait till the command is completed */ - status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT); - - while((status & 0x8000) != 0x8000) - { - status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT); - } - - /* Read Controller status */ - status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); - - /* Read data */ - for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /* While there is data to read */ - { - *pBuffer++ = *(__IO uint16_t *)((BANK1_ONENAND1_ADDR + OneNAND_DATA_RAM_1_0_ADD + 2*index)); - index++; - } -} - -/** - * @brief Reads the OneNAND memory Interrupt status. - * @param None - * @retval OneNAND memory Interrupt Status. - */ -uint16_t OneNAND_ReadStatus(void) -{ - __IO uint16_t status = 0x0; - - /* Read Status */ - return (status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT)); -} - -/** - * @brief Reads the OneNAND Controller status. - * @param None - * @retval OneNAND Controller Status. - */ -uint16_t OneNAND_ReadControllerStatus(void) -{ - __IO uint16_t status = 0x0; - - /* Read Controller Status */ - return (status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS)); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_onenand.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_onenand.h deleted file mode 100644 index d8bada815..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_onenand.h +++ /dev/null @@ -1,189 +0,0 @@ -/** - ****************************************************************************** - * @file stm32100e_eval_fsmc_onenand.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains all the functions prototypes for the - * stm32100e_eval_fsmc_onenand firmware driver. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32100E_EVAL_FSMC_ONENAND_H -#define __STM32100E_EVAL_FSMC_ONENAND_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32100E_EVAL - * @{ - */ - -/** @addtogroup STM32100E_EVAL_FSMC_ONENAND - * @{ - */ - -/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Exported_Types - * @{ - */ -typedef struct -{ - uint16_t Manufacturer_ID; - uint16_t Device_ID; -}OneNAND_IDTypeDef; - -/* OneNand Status */ -typedef enum -{ - OneNAND_SUCCESS = 0, - OneNAND_ONGOING, - OneNAND_ERROR, - OneNAND_TIMEOUT -}OneNAND_Status; - -typedef struct -{ - uint16_t Block; - uint16_t Page; -} OneNAND_ADDRESS; -/** - * @} - */ - -/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Exported_Constants - * @{ - */ -/** - * @brief OneNAND memory command - */ -#define OneNAND_CMD_ERASE ((uint16_t)0x0094) -#define OneNAND_CMD_PROGRAM ((uint16_t)0x0080) -#define OneNAND_CMD_RESET ((uint16_t)0x00F0) -#define OneNAND_CMD_READ_ID ((uint16_t)0x0090) -#define OneNAND_CMD_UNLOCK ((uint16_t)0x0023) -#define OneNAND_CMD_LOAD ((uint16_t)0x0000) - -/** - * @brief OneNand Register description - */ -#define OneNAND_REG_MANUFACTERID ((uint32_t)0x1E000) /* Manufacturer identification */ -#define OneNAND_REG_DEVICEID ((uint32_t)0x1E002) /* Device identification */ -#define OneNAND_REG_DATABUFFERSIZE ((uint32_t)0x1E006) /* Data Buffer size */ -#define OneNAND_REG_BOOTBUFFERSIZE ((uint32_t)0x1E008) /* Boot Buffer size */ -#define OneNAND_REG_AMOUNTOFBUFFERS ((uint32_t)0x1E00A) /* Amount of data/boot buffers */ -#define OneNAND_REG_TECHNOLOGY ((uint32_t)0x1E00C) /* Info about technology */ -#define OneNAND_REG_STARTADDRESS1 ((uint32_t)0x1E200) /* Nand Flash Block Address */ -#define OneNAND_REG_STARTADDRESS3 ((uint32_t)0x1E204) /* Destination Block address for copy back program */ -#define OneNAND_REG_STARTADDRESS4 ((uint32_t)0x1E206) /* Destination Page & sector address for copy back program */ -#define OneNAND_REG_STARTADDRESINT8_T ((uint32_t)0x1E20E) /* Nand Flash Page & sector address */ -#define OneNAND_REG_STARTBUFFER ((uint32_t)0x1E400) /* The meaning is with which buffer to start and how many - buffers to use for the data transfer */ -#define OneNAND_REG_COMMAND ((uint32_t)0x1E440) /* Host control and memory operation commands*/ -#define OneNAND_REG_SYSTEMCONFIGURATION ((uint32_t)0x1E442) /* Memory and host interface configuration */ -#define OneNAND_REG_CONTROLSTATUS ((uint32_t)0x1E480) /* Control status and result of memory operation */ -#define OneNAND_REG_INTERRUPT ((uint32_t)0x1E482) /* Memory Command Completion Interrupt Status */ -#define OneNAND_REG_STARTBLOCKADDRESS ((uint32_t)0x1E498) /* Start memory block address in Write Protection mode */ -#define OneNAND_REG_WRITEPROTECTIONSTATUS ((uint32_t)0x1E49C) /* Current memory Write Protection status */ - -/** - * @brief OneNand Memory partition description - */ -#define OneNAND_DATA_RAM_0_0_ADD ((uint32_t)0x0400) /* DataRAM Main page0/sector0 */ -#define OneNAND_DATA_RAM_0_0_REG ((uint32_t)0x0800) /* DataRAM 0_0 is selected with 4 sector */ - -#define OneNAND_DATA_RAM_0_1_ADD ((uint32_t)0x0600) /* DataRAM Main page0/sector1 */ -#define OneNAND_DATA_RAM_0_1_REG ((uint32_t)0x0900) /* DataRAM 0_1 is selected with 4 sector */ - -#define OneNAND_DATA_RAM_0_2_ADD ((uint32_t)0x0800) /* DataRAM Main page0/sector2 */ -#define OneNAND_DATA_RAM_0_2_REG ((uint32_t)0x0A00) /* DataRAM 0_2 is selected with 4 sector */ - -#define OneNAND_DATA_RAM_0_3_ADD ((uint32_t)0x0A00) /* DataRAM Main page0/sector3 */ -#define OneNAND_DATA_RAM_0_3_REG ((uint32_t)0x0B00) /* DataRAM 0_3 is selected with 4 sector */ - -#define OneNAND_DATA_RAM_1_0_ADD ((uint32_t)0x0C00) /* DataRAM Main page1/sector0 */ -#define OneNAND_DATA_RAM_1_0_REG ((uint32_t)0x0C00) /* DataRAM 1_0 is selected with 4 sector */ - -#define OneNAND_DATA_RAM_1_1_ADD ((uint32_t)0x0E00) /* DataRAM Main page1/sector1 */ -#define OneNAND_DATA_RAM_1_1_REG ((uint32_t)0x0D00) /* DataRAM 1_1 is selected with 4 sector */ - -#define OneNAND_DATA_RAM_1_2_ADD ((uint32_t)0x1000) /* DataRAM Main page1/sector2 */ -#define OneNAND_DATA_RAM_1_2_REG ((uint32_t)0x0E00) /* DataRAM 1_2 is selected with 4 sector */ - -#define OneNAND_DATA_RAM_1_3_ADD ((uint32_t)0x1200) /* DataRAM Main page1/sector3 */ -#define OneNAND_DATA_RAM_1_3_REG ((uint32_t)0x0F00) /* DataRAM 1_3 is selected with 4 sector */ - -/** - * @} - */ - -/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Exported_Functions - * @{ - */ -void OneNAND_Init(void); -void OneNAND_Reset(void); -void OneNAND_ReadID(OneNAND_IDTypeDef* OneNAND_ID); -uint16_t OneNAND_UnlockBlock(uint32_t BlockNumber); -uint16_t OneNAND_EraseBlock(uint32_t BlockNumber); -uint16_t OneNAND_WriteBuffer(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToWrite); -void OneNAND_AsynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead); -void OneNAND_SynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead); -uint16_t OneNAND_ReadStatus(void); -uint16_t OneNAND_ReadControllerStatus(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32100E_EVAL_FSMC_ONENAND_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_sram.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_sram.c deleted file mode 100644 index 4645fe217..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_sram.c +++ /dev/null @@ -1,237 +0,0 @@ -/** - ****************************************************************************** - * @file stm32100e_eval_fsmc_sram.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file provides a set of functions needed to drive the - * IS61WV102416BLL SRAM memory mounted on STM32100E-EVAL board. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32100e_eval_fsmc_sram.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32100E_EVAL - * @{ - */ - -/** @addtogroup STM32100E_EVAL_FSMC_SRAM - * @brief This file provides a set of functions needed to drive the - * IS61WV102416BLL SRAM memory mounted on STM32100E-EVAL board. - * @{ - */ - -/** @defgroup STM32100E_EVAL_FSMC_SRAM_Private_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32100E_EVAL_FSMC_SRAM_Private_Defines - * @{ - */ -/** - * @brief FSMC Bank 1 NOR/SRAM3 - */ -#define Bank1_SRAM3_ADDR ((uint32_t)0x68000000) -/** - * @} - */ - - -/** @defgroup STM32100E_EVAL_FSMC_SRAM_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32100E_EVAL_FSMC_SRAM_Private_Variables - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32100E_EVAL_FSMC_SRAM_Private_Function_Prototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32100E_EVAL_FSMC_SRAM_Private_Functions - * @{ - */ - -/** - * @brief Configures the FSMC and GPIOs to interface with the SRAM memory. - * This function must be called before any write/read operation - * on the SRAM. - * @param None - * @retval None - */ -void SRAM_Init(void) -{ - FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; - FSMC_NORSRAMTimingInitTypeDef p; - GPIO_InitTypeDef GPIO_InitStructure; - - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE | - RCC_APB2Periph_GPIOF, ENABLE); - -/*-- GPIO Configuration ------------------------------------------------------*/ - /*!< SRAM Data lines configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 | - GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | - GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | - GPIO_Pin_15; - GPIO_Init(GPIOE, &GPIO_InitStructure); - - /*!< SRAM Address lines configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | - GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | - GPIO_Pin_14 | GPIO_Pin_15; - GPIO_Init(GPIOF, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | - GPIO_Pin_4 | GPIO_Pin_5; - GPIO_Init(GPIOG, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - /*!< NOE and NWE configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 |GPIO_Pin_5; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - /*!< NE3 configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; - GPIO_Init(GPIOG, &GPIO_InitStructure); - - /*!< NBL0, NBL1 configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1; - GPIO_Init(GPIOE, &GPIO_InitStructure); - -/*-- FSMC Configuration ------------------------------------------------------*/ - p.FSMC_AddressSetupTime = 0; - p.FSMC_AddressHoldTime = 0; - p.FSMC_DataSetupTime = 3; - p.FSMC_BusTurnAroundDuration = 0; - p.FSMC_CLKDivision = 0; - p.FSMC_DataLatency = 0; - p.FSMC_AccessMode = FSMC_AccessMode_A; - - FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3; - FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; - FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; - FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; - FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; - FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; - FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; - - FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); - - /*!< Enable FSMC Bank1_SRAM Bank */ - FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE); -} - -/** - * @brief Writes a Half-word buffer to the FSMC SRAM memory. - * @param pBuffer : pointer to buffer. - * @param WriteAddr : SRAM memory internal address from which the data will be - * written. - * @param NumHalfwordToWrite : number of half-words to write. - * @retval None - */ -void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite) -{ - for(; NumHalfwordToWrite != 0; NumHalfwordToWrite--) /*!< while there is data to write */ - { - /*!< Transfer data to the memory */ - *(uint16_t *) (Bank1_SRAM3_ADDR + WriteAddr) = *pBuffer++; - - /*!< Increment the address*/ - WriteAddr += 2; - } -} - -/** - * @brief Reads a block of data from the FSMC SRAM memory. - * @param pBuffer : pointer to the buffer that receives the data read from the - * SRAM memory. - * @param ReadAddr : SRAM memory internal address to read from. - * @param NumHalfwordToRead : number of half-words to read. - * @retval None - */ -void SRAM_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead) -{ - for(; NumHalfwordToRead != 0; NumHalfwordToRead--) /*!< while there is data to read */ - { - /*!< Read a half-word from the memory */ - *pBuffer++ = *(__IO uint16_t*) (Bank1_SRAM3_ADDR + ReadAddr); - - /*!< Increment the address*/ - ReadAddr += 2; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_sram.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_sram.h deleted file mode 100644 index 1c80a4ca9..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_sram.h +++ /dev/null @@ -1,104 +0,0 @@ -/** - ****************************************************************************** - * @file stm32100e_eval_fsmc_sram.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains all the functions prototypes for the - * stm32100e_eval_fsmc_sram firmware driver. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32100E_EVAL_FSMC_SRAM_H -#define __STM32100E_EVAL_FSMC_SRAM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32100E_EVAL - * @{ - */ - -/** @addtogroup STM32100E_EVAL_FSMC_SRAM - * @{ - */ - -/** @defgroup STM32100E_EVAL_FSMC_SRAM_Exported_Types - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32100E_EVAL_FSMC_SRAM_Exported_Constants - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32100E_EVAL_FSMC_SRAM_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32100E_EVAL_FSMC_SRAM_Exported_Functions - * @{ - */ - -void SRAM_Init(void); -void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite); -void SRAM_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32100E_EVAL_FSMC_SRAM_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_ioe.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_ioe.c deleted file mode 100644 index a9e733553..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_ioe.c +++ /dev/null @@ -1,1405 +0,0 @@ -/** - ****************************************************************************** - * @file stm32100e_eval_ioe.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file includes the IO Expander driver for STMPE811 IO Expander - * devices. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - - /* File Info : --------------------------------------------------------------- - - Note: - ----- - - This driver uses the DMA method for sending and receiving data on I2C bus - which allow higher efficiency and reliability of the communication. - - SUPPORTED FEATURES: - - Touch Screen Features: Single point mode (Polling/Interrupt). - - TempSensor Feature: accuracy not determined (Polling). - - IO Read/write : Set/Reset and Read (Polling/Interrupt). - - UNSUPPORTED FEATURES: - - Row ADC Feature is not supported (not implemented on STM32100E-EVAL board) - - Joystick: config and Read (Polling/Interrupt) - ----------------------------------------------------------------------------*/ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32100e_eval_ioe.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32100E_EVAL - * @{ - */ - -/** @defgroup STM32100E_EVAL_IOE - * @brief This file includes the IO Expander driver for STMPE811 IO Expander - * devices. - * @{ - */ - -/** @defgroup STM32100E_EVAL_IOE_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32100E_EVAL_IOE_Private_Defines - * @{ - */ -#define TIMEOUT_MAX 0x1000 /* _x? (x - _x): (_x - x); - yDiff = y > _y? (y - _y): (_y - y); - if (xDiff + yDiff > 5) - { - _x = x; - _y = y; - } - } - /* Update the X position */ - TS_State.X = _x; - - /* Update the Y position */ - TS_State.Y = _y; - /* Update the Z Pression index */ - TS_State.Z = IOE_TS_Read_Z(); - - /* Clear the interrupt pending bit and enable the FIFO again */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x01); - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x00); - - /* Return pointer to the updated structure */ - return &TS_State; -} - -/** - * @brief Returns the temperature row value (in 16 bit format). - * @param None - * @retval The temperature row value. - */ -uint32_t IOE_TempSens_GetData(void) -{ - static __IO uint32_t tmp = 0; - - /* Aquire data enable */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TEMP_CTRL, 0x03); - - /* Enable the TEMPSENS module */ - tmp = (uint32_t)((I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_TEMP_DATA) & 0x03) << 8); - tmp |= (uint32_t)I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_TEMP_DATA + 1); - - tmp = (uint32_t)((33 * tmp * 100) / 751); - tmp = (uint32_t)((tmp + 5) / 10); - - /* return the temprature row value */ - return tmp; -} - -/** - * @brief Checks the selected Global interrupt source pending bit - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR. - * @param Global_IT: the Global interrupt source to be checked, could be: - * @arg Global_IT_GPIO : All IOs interrupt - * @arg Global_IT_ADC : ADC interrupt - * @arg Global_IT_TEMP : Temperature Sensor interrupts - * @arg Global_IT_FE : Touch Screen Controller FIFO Error interrupt - * @arg Global_IT_FF : Touch Screen Controller FIFO Full interrupt - * @arg Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt - * @arg Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt - * @arg Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt - * @retval Status of the checked flag. Could be SET or RESET. - */ -FlagStatus IOE_GetGITStatus(uint8_t DeviceAddr, uint8_t Global_IT) -{ - __IO uint8_t tmp = 0; - - /* get the Interrupt status */ - tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_STA); - - if ((tmp & (uint8_t)Global_IT) != 0) - { - return SET; - } - else - { - return RESET; - } -} - -/** - * @brief Clears the selected Global interrupt pending bit(s) - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR. - * @param Global_IT: the Global interrupt to be cleared, could be any combination - * of the following values: - * @arg Global_IT_GPIO : All IOs interrupt - * @arg Global_IT_ADC : ADC interrupt - * @arg Global_IT_TEMP : Temperature Sensor interrupts - * @arg Global_IT_FE : Touch Screen Controller FIFO Error interrupt - * @arg Global_IT_FF : Touch Screen Controller FIFO Full interrupt - * @arg Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt - * @arg Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt - * @arg Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt - * @retval IOE_OK: if all initializations are OK. Other value if error. - */ -uint8_t IOE_ClearGITPending(uint8_t DeviceAddr, uint8_t Global_IT) -{ - /* Write 1 to the bits that have to be cleared */ - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_STA, Global_IT); - - /* If all OK return IOE_OK */ - return IOE_OK; -} - -/** - * @brief Checks the status of the selected IO interrupt pending bit - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR. - * @param IO_IT: the IO interrupt to be checked could be IO_ITx Where x can be - * from 0 to 7. - * @retval Status of the checked flag. Could be SET or RESET. - */ -FlagStatus IOE_GetIOITStatus(uint8_t DeviceAddr, uint8_t IO_IT) -{ - uint8_t tmp = 0; - - /* get the Interrupt status */ - tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_STA); - - if ((tmp & (uint8_t)IO_IT) != 0) - { - return SET; - } - else - { - return RESET; - } -} - -/** - * @brief Clears the selected IO interrupt pending bit(s). - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR. - * @param IO_IT: the IO interrupt to be checked could be IO_ITx Where x can be - * from 0 to 7. - * @retval IOE_OK: if all initializations are OK. Other value if error. - */ -uint8_t IOE_ClearIOITPending(uint8_t DeviceAddr, uint8_t IO_IT) -{ - /* Write 1 to the bits that have to be cleared */ - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_STA, IO_IT); - - /* Clear the Edge detection pending bit*/ - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_ED, IO_IT); - - /* Clear the Rising edge pending bit */ - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_RE, IO_IT); - - /* Clear the Falling edge pending bit */ - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_FE, IO_IT); - - return IOE_OK; - -} -/** - * @brief Checks if the selected device is correctly configured and - * communicates correctly ont the I2C bus. - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR. - * @retval IOE_OK if IOE is operational. Other value if failure. - */ -uint8_t IOE_IsOperational(uint8_t DeviceAddr) -{ - /* Return Error if the ID is not correct */ - if( IOE_ReadID(DeviceAddr) != (uint16_t)STMPE811_ID ) - { - /* Check if a Timeout occured */ - if (IOE_TimeOut == 0) - { - return(IOE_TimeoutUserCallback()); - } - else - { - return IOE_FAILURE; /* ID is not Correct */ - } - } - else - { - return IOE_OK; /* ID is correct */ - } -} - -/** - * @brief Resets the IO Expander by Software (SYS_CTRL1, RESET bit). - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR. - * @retval IOE_OK: if all initializations are OK. Other value if error. - */ -uint8_t IOE_Reset(uint8_t DeviceAddr) -{ - /* Power Down the IO_Expander */ - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL1, 0x02); - - /* wait for a delay to insure registers erasing */ - _delay_(2); - - /* Power On the Codec after the power off => all registers are reinitialized*/ - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL1, 0x00); - - /* If all OK return IOE_OK */ - return IOE_OK; -} - -/** - * @brief Reads the selected device's ID. - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR. - * @retval The Device ID (two bytes). - */ -uint16_t IOE_ReadID(uint8_t DeviceAddr) -{ - uint16_t tmp = 0; - - /* Read device ID */ - tmp = I2C_ReadDeviceRegister(DeviceAddr, 0); - tmp = (uint32_t)(tmp << 8); - tmp |= (uint32_t)I2C_ReadDeviceRegister(DeviceAddr, 1); - - /* Return the ID */ - return (uint16_t)tmp; -} - -/** - * @brief Configures the selcted IO Expander functionalities. - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR. - * @param Fct: the functions to be configured. could be any - * combination of the following values: - * @arg IOE_IO_FCT : IO function - * @arg IOE_TS_FCT : Touch Screen function - * @arg IOE_ADC_FCT : ADC function - * @arg IOE_TEMPSENS_FCT : Tempreature Sensor function - * @retval IOE_OK: if all initializations are OK. Other value if error. - */ -uint8_t IOE_FnctCmd(uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState) -{ - uint8_t tmp = 0; - - /* Get the register value */ - tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL2); - - if (NewState != DISABLE) - { - /* Set the Functionalities to be Enabled */ - tmp &= ~(uint8_t)Fct; - } - else - { - /* Set the Functionalities to be Disabled */ - tmp |= (uint8_t)Fct; - } - - /* Set the register value */ - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL2, tmp); - - /* If all OK return IOE_OK */ - return IOE_OK; -} - -/** - * @brief Configures the selected pin direction (to be an input or an output) - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR. - * @param IO_Pin: IO_Pin_x: Where x can be from 0 to 7. - * @param Direction: could be Direction_IN or Direction_OUT. - * @retval IOE_OK: if all initializations are OK. Other value if error. - */ -uint8_t IOE_IOPinConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction) -{ - uint8_t tmp = 0; - - /* Get all the Pins direction */ - tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_DIR); - - if (Direction != Direction_IN) - { - tmp |= (uint8_t)IO_Pin; - } - else - { - tmp &= ~(uint8_t)IO_Pin; - } - - /* Write the register new value */ - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_DIR, tmp); - - /* If all OK return IOE_OK */ - return IOE_OK; -} - -/** - * @brief Enables or disables the Global interrupt. - * @param DeviceAddr: The address of the IOExpander, could be :I OE_1_ADDR. - * @param NewState: could be ENABLE or DISABLE. - * @retval IOE_OK: if all initializations are OK. Other value if error. - */ -uint8_t IOE_GITCmd(uint8_t DeviceAddr, FunctionalState NewState) -{ - uint8_t tmp = 0; - - /* Read the Interrupt Control register */ - I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_CTRL); - - if (NewState != DISABLE) - { - /* Set the global interrupts to be Enabled */ - tmp |= (uint8_t)IOE_GIT_EN; - } - else - { - /* Set the global interrupts to be Disabled */ - tmp &= ~(uint8_t)IOE_GIT_EN; - } - - /* Write Back the Interrupt Control register */ - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_CTRL, tmp); - - /* If all OK return IOE_OK */ - return IOE_OK; -} - -/** - * @brief Configures the selected source to generate or not a global interrupt - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR - * @param Global_IT: the interrupt source to be configured, could be: - * @arg Global_IT_GPIO : All IOs interrupt - * @arg Global_IT_ADC : ADC interrupt - * @arg Global_IT_TEMP : Temperature Sensor interrupts - * @arg Global_IT_FE : Touch Screen Controller FIFO Error interrupt - * @arg Global_IT_FF : Touch Screen Controller FIFO Full interrupt - * @arg Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt - * @arg Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt - * @arg Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt - * @retval IOE_OK: if all initializations are OK. Other value if error. - */ -uint8_t IOE_GITConfig(uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState) -{ - uint8_t tmp = 0; - - /* Get the current value of the INT_EN register */ - tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_EN); - - if (NewState != DISABLE) - { - /* Set the interrupts to be Enabled */ - tmp |= (uint8_t)Global_IT; - } - else - { - /* Set the interrupts to be Disabled */ - tmp &= ~(uint8_t)Global_IT; - } - /* Set the register */ - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_EN, tmp); - - /* If all OK return IOE_OK */ - return IOE_OK; -} - -/** - * @brief Configures the selected pins to generate an interrupt or not. - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR. - * @param IO_IT: The IO interrupt to be configured. This parameter could be any - * combination of the following values: - * @arg IO_IT_x: where x can be from 0 to 7. - * @param NewState: could be ENABLE or DISABLE. - * @retval IOE_OK: if all initializations are OK. Other value if error. - */ -uint8_t IOE_IOITConfig(uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState) -{ - uint8_t tmp = 0; - - tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_EN); - - if (NewState != DISABLE) - { - /* Set the interrupts to be Enabled */ - tmp |= (uint8_t)IO_IT; - } - else - { - /* Set the interrupts to be Disabled */ - tmp &= ~(uint8_t)IO_IT; - } - - /* Set the register */ - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_EN, tmp); - - /* If all OK return IOE_OK */ - return IOE_OK; -} - -/** - * @brief Configures the touch Screen Controller (Single point detection) - * @param None - * @retval IOE_OK if all initializations are OK. Other value if error. - */ -uint8_t IOE_TS_Config(void) -{ - uint8_t tmp = 0; - - /* Enable TSC Fct: already done in IOE_Config */ - tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2); - tmp &= ~(uint32_t)(IOE_TS_FCT | IOE_ADC_FCT); - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2, tmp); - - /* Enable the TSC gloabl interrupts */ - tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_INT_EN); - tmp |= (uint32_t)(IOE_GIT_TOUCH | IOE_GIT_FTH | IOE_GIT_FOV); - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_EN, tmp); - - /* Select Sample Time, bit number and ADC Reference */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_ADC_CTRL1, 0x49); - - /* Wait for ~20 ms */ - _delay_(2); - - /* Select the ADC clock speed: 3.25 MHz */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_ADC_CTRL2, 0x01); - - /* Select TSC pins in non default mode */ - tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_AF); - tmp &= ~(uint8_t)TOUCH_IO_ALL; - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_AF, tmp); - - /* Select 2 nF filter capacitor */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_CFG, 0x9A); - - /* Select single point reading */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_TH, 0x01); - - /* Write 0x01 to clear the FIFO memory content. */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x01); - - /* Write 0x00 to put the FIFO back into operation mode */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x00); - - /* set the data format for Z value: 7 fractional part and 1 whole part */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_FRACT_XYZ, 0x01); - - /* set the driving capability of the device for TSC pins: 50mA */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_I_DRIVE, 0x01); - - /* Use no tracking index, touchscreen controller operation mode (XYZ) and - enable the TSC */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_CTRL, 0x01); - - /* Clear all the status pending bits */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_STA, 0xFF); - - /* Initialize the TS structure to their default values */ - TS_State.TouchDetected = TS_State.X = TS_State.Y = TS_State.Z = 0; - - /* All configuration done */ - return IOE_OK; -} - -/** - * @brief Configures and enables the Temperature sensor module. - * @param None - * @retval IOE_OK if all initializations are OK. Other value if error. - */ -uint8_t IOE_TempSens_Config(void) -{ - __IO uint8_t tmp = 0; - - /* Enable Temperature Sensor Fct: already done in IOE_Config */ - tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2); - tmp &= ~(uint32_t)(IOE_TEMPSENS_FCT | IOE_ADC_FCT); - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2, tmp); - - /* Enable the TEMPSENS module */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TEMP_CTRL, 0x01); - - /* Aquire data enable */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TEMP_CTRL, 0x3); - - /* All configuration done */ - return IOE_OK; -} - -/** - * @brief Configures the selected pin to be in Alternate function or not - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR. - * @param IO_Pin: IO_Pin_x, Where x can be from 0 to 7. - * @param NewState: State of the AF for the selected pin, could be - * ENABLE or DISABLE. - * @retval IOE_OK: if all initializations are OK. Other value if error. - */ -uint8_t IOE_IOAFConfig(uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState) -{ - uint8_t tmp = 0; - - /* Get the current state of the GPIO_AF register */ - tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_AF); - - if (NewState != DISABLE) - { - /* Enable the selected pins alternate function */ - tmp |= (uint8_t)IO_Pin; - } - else - { - /* Disable the selected pins alternate function */ - tmp &= ~(uint8_t)IO_Pin; - } - - /* Write back the new valu in GPIO_AF register */ - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_AF, tmp); - - /* If all OK return IOE_OK */ - return IOE_OK; -} - -/** - * @brief Configures the Edge for which a transition is detectable for the - * the selected pin. - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR. - * @param IO_Pin: IO_Pin_x, Where x can be from 0 to 7. - * @param Edge: The edge which will be detected. This parameter can be one or a - * a combination of follwing values: EDGE_FALLING and EDGE_RISING . - * @retval IOE_OK: if all initializations are OK. Other value if error. - */ -uint8_t IOE_IOEdgeConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge) -{ - uint8_t tmp1 = 0, tmp2 = 0; - - /* Get the registers values */ - tmp1 = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_FE); - tmp2 = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_RE); - - /* Disable the Falling Edge */ - tmp1 &= ~(uint8_t)IO_Pin; - /* Disable the Falling Edge */ - tmp2 &= ~(uint8_t)IO_Pin; - - /* Enable the Falling edge if selected */ - if (Edge & EDGE_FALLING) - { - tmp1 |= (uint8_t)IO_Pin; - } - - /* Enable the Rising edge if selected */ - if (Edge & EDGE_RISING) - { - tmp2 |= (uint8_t)IO_Pin; - } - - /* Write back the registers values */ - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_FE, tmp1); - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_RE, tmp2); - - /* if OK return 0 */ - return IOE_OK; -} - -/** - * @brief Configures the Interrupt line active state and format (level/edge) - * @param Polarity: could be - * @arg Polarity_Low: Interrupt line is active Low/Falling edge - * @arg Polarity_High: Interrupt line is active High/Rising edge - * @param Type: Interrupt line activity type, could be one of the following values - * @arg Type_Level: Interrupt line is active in level model - * @arg Type_Edge: Interrupt line is active in edge model - * @retval IOE_OK: if all initializations are OK. Other value if error. - */ -uint8_t IOE_ITOutConfig(uint8_t Polarity, uint8_t Type) -{ - uint8_t tmp = 0; - - /* Get the register IOE_REG_INT_CTRL value */ - tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_INT_CTRL); - - /* Mask the polarity and type bits */ - tmp &= ~(uint8_t)0x06; - - /* Modify the Interrupt Output line configuration */ - tmp |= (uint8_t)(Polarity | Type); - - /* Set the register */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_CTRL, tmp); - - /* If all OK return IOE_OK */ - return IOE_OK; -} - -/** - * @brief Writes a value in a register of the device through I2C. - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR. - * @param RegisterAddr: The target register adress - * @param RegisterValue: The target register value to be written - * @retval IOE_OK: if all operations are OK. Other value if error. - */ -uint8_t I2C_WriteDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue) -{ - uint32_t read_verif = 0; - uint8_t IOE_BufferTX = 0; - - /* Get Value to be written */ - IOE_BufferTX = RegisterValue; - - /* Configure DMA Peripheral */ - IOE_DMA_Config(IOE_DMA_TX, (uint8_t*)(&IOE_BufferTX)); - - /* Enable the I2C peripheral */ - I2C_GenerateSTART(IOE_I2C, ENABLE); - - /* Test on SB Flag */ - IOE_TimeOut = TIMEOUT_MAX; - while (I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB) == RESET) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Transmit the slave address and enable writing operation */ - I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter); - - /* Test on ADDR Flag */ - IOE_TimeOut = TIMEOUT_MAX; - while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Transmit the first address for r/w operations */ - I2C_SendData(IOE_I2C, RegisterAddr); - - /* Test on TXE FLag (data dent) */ - IOE_TimeOut = TIMEOUT_MAX; - while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF))) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Enable I2C DMA request */ - I2C_DMACmd(IOE_I2C,ENABLE); - - /* Enable DMA TX Channel */ - DMA_Cmd(IOE_DMA_TX_CHANNEL, ENABLE); - - /* Wait until DMA Transfer Complete */ - IOE_TimeOut = TIMEOUT_MAX; - while (!DMA_GetFlagStatus(IOE_DMA_TX_TCFLAG)) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Wait until BTF Flag is set before generating STOP */ - IOE_TimeOut = 2 * TIMEOUT_MAX; - while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF))) - { - } - - /* Send STOP Condition */ - I2C_GenerateSTOP(IOE_I2C, ENABLE); - - /* Disable DMA TX Channel */ - DMA_Cmd(IOE_DMA_TX_CHANNEL, DISABLE); - - /* Disable I2C DMA request */ - I2C_DMACmd(IOE_I2C,DISABLE); - - /* Clear DMA TX Transfer Complete Flag */ - DMA_ClearFlag(IOE_DMA_TX_TCFLAG); - -#ifdef VERIFY_WRITTENDATA - /* Verify (if needed) that the loaded data is correct */ - - /* Read the just written register*/ - read_verif = I2C_ReadDeviceRegister(DeviceAddr, RegisterAddr); - /* Load the register and verify its value */ - if (read_verif != RegisterValue) - { - /* Control data wrongly tranfered */ - read_verif = IOE_FAILURE; - } - else - { - /* Control data correctly transfered */ - read_verif = 0; - } -#endif - - /* Return the verifying value: 0 (Passed) or 1 (Failed) */ - return read_verif; -} - -/** - * @brief Reads a register of the device through I2C. - * @param DeviceAddr: The address of the device, could be : IOE_1_ADDR. - * @param RegisterAddr: The target register adress (between 00x and 0x24) - * @retval The value of the read register (0xAA if Timout occured) - */ -uint8_t I2C_ReadDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr) -{ - uint8_t IOE_BufferRX[2] = {0x00, 0x00}; - - /* Configure DMA Peripheral */ - IOE_DMA_Config(IOE_DMA_RX, (uint8_t*)IOE_BufferRX); - - /* Enable DMA NACK automatic generation */ - I2C_DMALastTransferCmd(IOE_I2C, ENABLE); - - /* Enable the I2C peripheral */ - I2C_GenerateSTART(IOE_I2C, ENABLE); - - /* Test on SB Flag */ - IOE_TimeOut = TIMEOUT_MAX; - while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB)) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Send device address for write */ - I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter); - - /* Test on ADDR Flag */ - IOE_TimeOut = TIMEOUT_MAX; - while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Send the device's internal address to write to */ - I2C_SendData(IOE_I2C, RegisterAddr); - - /* Test on TXE FLag (data dent) */ - IOE_TimeOut = TIMEOUT_MAX; - while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF))) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Send START condition a second time */ - I2C_GenerateSTART(IOE_I2C, ENABLE); - - /* Test on SB Flag */ - IOE_TimeOut = TIMEOUT_MAX; - while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB)) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Send IOExpander address for read */ - I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Receiver); - - /* Test on ADDR Flag */ - IOE_TimeOut = TIMEOUT_MAX; - while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Enable I2C DMA request */ - I2C_DMACmd(IOE_I2C,ENABLE); - - /* Enable DMA RX Channel */ - DMA_Cmd(IOE_DMA_RX_CHANNEL, ENABLE); - - /* Wait until DMA Transfer Complete */ - IOE_TimeOut = 2 * TIMEOUT_MAX; - while (!DMA_GetFlagStatus(IOE_DMA_RX_TCFLAG)) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Send STOP Condition */ - I2C_GenerateSTOP(IOE_I2C, ENABLE); - - /* Disable DMA RX Channel */ - DMA_Cmd(IOE_DMA_RX_CHANNEL, DISABLE); - - /* Disable I2C DMA request */ - I2C_DMACmd(IOE_I2C,DISABLE); - - /* Clear DMA RX Transfer Complete Flag */ - DMA_ClearFlag(IOE_DMA_RX_TCFLAG); - - /* return a pointer to the IOE_Buffer */ - return (uint8_t)IOE_BufferRX[0]; -} - - -/** - * @brief Reads a buffer of 2 bytes from the device registers. - * @param DeviceAddr: The address of the device, could be : IOE_1_ADDR. - * @param RegisterAddr: The target register adress (between 00x and 0x24) - * @retval A pointer to the buffer containing the two returned bytes (in halfword). - */ -uint16_t I2C_ReadDataBuffer(uint8_t DeviceAddr, uint32_t RegisterAddr) -{ - uint8_t tmp= 0; - uint8_t IOE_BufferRX[2] = {0x00, 0x00}; - - /* Configure DMA Peripheral */ - IOE_DMA_Config(IOE_DMA_RX, (uint8_t*)IOE_BufferRX); - - /* Enable DMA NACK automatic generation */ - I2C_DMALastTransferCmd(IOE_I2C, ENABLE); - - /* Enable the I2C peripheral */ - I2C_GenerateSTART(IOE_I2C, ENABLE); - - /* Test on SB Flag */ - IOE_TimeOut = TIMEOUT_MAX; - while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB)) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Send device address for write */ - I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter); - - /* Test on ADDR Flag */ - IOE_TimeOut = TIMEOUT_MAX; - while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Send the device's internal address to write to */ - I2C_SendData(IOE_I2C, RegisterAddr); - - /* Test on TXE FLag (data dent) */ - IOE_TimeOut = TIMEOUT_MAX; - while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF))) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Send START condition a second time */ - I2C_GenerateSTART(IOE_I2C, ENABLE); - - /* Test on SB Flag */ - IOE_TimeOut = TIMEOUT_MAX; - while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB)) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Send IOExpander address for read */ - I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Receiver); - - /* Test on ADDR Flag */ - IOE_TimeOut = TIMEOUT_MAX; - while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Enable I2C DMA request */ - I2C_DMACmd(IOE_I2C,ENABLE); - - /* Enable DMA RX Channel */ - DMA_Cmd(IOE_DMA_RX_CHANNEL, ENABLE); - - /* Wait until DMA Transfer Complete */ - IOE_TimeOut = 2 * TIMEOUT_MAX; - while (!DMA_GetFlagStatus(IOE_DMA_RX_TCFLAG)) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Send STOP Condition */ - I2C_GenerateSTOP(IOE_I2C, ENABLE); - - /* Disable DMA RX Channel */ - DMA_Cmd(IOE_DMA_RX_CHANNEL, DISABLE); - - /* Disable I2C DMA request */ - I2C_DMACmd(IOE_I2C,DISABLE); - - /* Clear DMA RX Transfer Complete Flag */ - DMA_ClearFlag(IOE_DMA_RX_TCFLAG); - - /* Reorganize received data */ - tmp = IOE_BufferRX[0]; - IOE_BufferRX[0] = IOE_BufferRX[1]; - IOE_BufferRX[1] = tmp; - - /* return a pointer to the IOE_Buffer */ - return *(uint16_t *)IOE_BufferRX; -} - -/** - * @brief Return Touch Screen X position value - * @param None - * @retval X position. - */ -static uint16_t IOE_TS_Read_X(void) -{ - int32_t x, xr; - - x = I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_Y); - - /* first correction */ - xr = (x * 320) >> 12; - /* second correction */ - xr = ((xr * 32)/29) - 17; - - if(xr <= 0) - xr = 0; - - return (uint16_t)(xr); -} - -/** - * @brief Return Touch Screen Y position value - * @param None - * @retval Y position. - */ -static uint16_t IOE_TS_Read_Y(void) -{ - int32_t y, yr; - y= I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_X); - - yr= (y * 240) >> 12; - yr = ((yr * 240) / 217) - 12; - - if(yr <= 0) - yr = 0; - - return (uint16_t)(yr); -} - -/** - * @brief Return Touch Screen Z position value - * @param None - * @retval Z position. - */ -static uint16_t IOE_TS_Read_Z(void) -{ - uint32_t z; - z = I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_Z); - - - if(z <= 0) - z = 0; - - return (uint16_t)(z); -} - -/** - * @brief Initializes the GPIO pins used by the IO expander. - * @param None - * @retval None - */ -static void IOE_GPIO_Config(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable IOE_I2C and IOE_I2C_PORT & Alternate Function clocks */ - RCC_APB1PeriphClockCmd(IOE_I2C_CLK, ENABLE); - RCC_APB2PeriphClockCmd(IOE_I2C_SCL_GPIO_CLK | IOE_I2C_SDA_GPIO_CLK | IOE_IT_GPIO_CLK - | RCC_APB2Periph_AFIO, ENABLE); - - /* Reset IOE_I2C IP */ - RCC_APB1PeriphResetCmd(IOE_I2C_CLK, ENABLE); - - /* Release reset signal of IOE_I2C IP */ - RCC_APB1PeriphResetCmd(IOE_I2C_CLK, DISABLE); - - /* IOE_I2C SCL and SDA pins configuration */ - GPIO_InitStructure.GPIO_Pin = IOE_I2C_SCL_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD; - GPIO_Init(IOE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure); - - /* IOE_I2C SCL and SDA pins configuration */ - GPIO_InitStructure.GPIO_Pin = IOE_I2C_SDA_PIN; - GPIO_Init(IOE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); - - /* Set EXTI pin as Input PullUp - IO_Expander_INT */ - GPIO_InitStructure.GPIO_Pin = IOE_IT_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(IOE_IT_GPIO_PORT, &GPIO_InitStructure); - - /* Connect IO Expander IT line to EXTI line */ - GPIO_EXTILineConfig(IOE_IT_EXTI_PORT_SOURCE, IOE_IT_EXTI_PIN_SOURCE); -} - - -/** - * @brief Configure the I2C Peripheral used to communicate with IO_Expanders. - * @param None - * @retval None - */ -static void IOE_I2C_Config(void) -{ - I2C_InitTypeDef I2C_InitStructure; - - /* IOE_I2C configuration */ - I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; - I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2; - I2C_InitStructure.I2C_OwnAddress1 = 0x00; - I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; - I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; - I2C_InitStructure.I2C_ClockSpeed = IOE_I2C_SPEED; - - I2C_Init(IOE_I2C, &I2C_InitStructure); -} - - -/** - * @brief Configure the DMA Peripheral used to handle communication via I2C. - * @param None - * @retval None - */ - -static void IOE_DMA_Config(IOE_DMADirection_TypeDef Direction, uint8_t* buffer) -{ - DMA_InitTypeDef DMA_InitStructure; - - RCC_AHBPeriphClockCmd(IOE_DMA_CLK, ENABLE); - - /* Initialize the DMA_PeripheralBaseAddr member */ - DMA_InitStructure.DMA_PeripheralBaseAddr = IOE_I2C_DR; - /* Initialize the DMA_MemoryBaseAddr member */ - DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)buffer; - /* Initialize the DMA_PeripheralInc member */ - DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - /* Initialize the DMA_MemoryInc member */ - DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - /* Initialize the DMA_PeripheralDataSize member */ - DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - /* Initialize the DMA_MemoryDataSize member */ - DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - /* Initialize the DMA_Mode member */ - DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; - /* Initialize the DMA_Priority member */ - DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; - /* Initialize the DMA_M2M member */ - DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; - - /* If using DMA for Reception */ - if (Direction == IOE_DMA_RX) - { - /* Initialize the DMA_DIR member */ - DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; - - /* Initialize the DMA_BufferSize member */ - DMA_InitStructure.DMA_BufferSize = 2; - - DMA_DeInit(IOE_DMA_RX_CHANNEL); - - DMA_Init(IOE_DMA_RX_CHANNEL, &DMA_InitStructure); - } - /* If using DMA for Transmission */ - else if (Direction == IOE_DMA_TX) - { - /* Initialize the DMA_DIR member */ - DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST; - - /* Initialize the DMA_BufferSize member */ - DMA_InitStructure.DMA_BufferSize = 1; - - DMA_DeInit(IOE_DMA_TX_CHANNEL); - - DMA_Init(IOE_DMA_TX_CHANNEL, &DMA_InitStructure); - } -} - -/** - * @brief Configures the IO expander Interrupt line and GPIO in EXTI mode. - * @param None - * @retval None - */ -static void IOE_EXTI_Config(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - NVIC_InitTypeDef NVIC_InitStructure; - EXTI_InitTypeDef EXTI_InitStructure; - - /* Enable Button GPIO clock */ - RCC_APB2PeriphClockCmd(IOE_IT_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE); - - /* Configure Button pin as input floating */ - GPIO_InitStructure.GPIO_Pin = IOE_IT_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(IOE_IT_GPIO_PORT, &GPIO_InitStructure); - - /* Connect Button EXTI Line to Button GPIO Pin */ - GPIO_EXTILineConfig(IOE_IT_EXTI_PORT_SOURCE, IOE_IT_EXTI_PIN_SOURCE); - - /* Configure Button EXTI line */ - EXTI_InitStructure.EXTI_Line = IOE_IT_EXTI_LINE; - EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling; - EXTI_InitStructure.EXTI_LineCmd = ENABLE; - EXTI_Init(&EXTI_InitStructure); - - /* Enable and set Button EXTI Interrupt to the lowest priority */ - NVIC_InitStructure.NVIC_IRQChannel = IOE_IT_EXTI_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); -} - -#ifndef USE_Delay -/** - * @brief Inserts a delay time. - * @param nCount: specifies the delay time length. - * @retval None - */ -static void delay(__IO uint32_t nCount) -{ - __IO uint32_t index = 0; - for(index = (100000 * nCount); index != 0; index--) - { - } -} -#endif /* USE_Delay*/ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_ioe.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_ioe.h deleted file mode 100644 index a68433529..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_ioe.h +++ /dev/null @@ -1,491 +0,0 @@ -/** - ****************************************************************************** - * @file stm32100e_eval_ioe.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains all the functions prototypes for the IO Expander - * firmware driver. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - - /* File Info : --------------------------------------------------------------- - SUPPORTED FEATURES: - - Touch Screen Features: Single point mode (Polling/Interrupt). - - TempSensor Feature: accuracy not determined (Polling). - - IO Read/write : Set/Reset and Read (Polling/Interrupt). - - UNSUPPORTED FEATURES: - - Row ADC Feature is not supported (not implemented on STM32100E-EVAL board) - - Joystick: config and Read (Polling/Interrupt) -----------------------------------------------------------------------------*/ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32100E_EVAL_IOE_H -#define __STM32100E_EVAL_IOE_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32100E_EVAL - * @{ - */ - -/** @defgroup STM32100E_EVAL_IOE - * @{ - */ - -/** @defgroup STM32100E_EVAL_IOE_Exported_Types - * @{ - */ - -/** - * @brief Touch Screen Information structure - */ -typedef struct -{ - uint16_t TouchDetected; - uint16_t X; - uint16_t Y; - uint16_t Z; -}TS_STATE; - - -/** - * @brief IO_Expander Error codes - */ -typedef enum -{ - IOE_OK = 0, - IOE_FAILURE, - IOE_TIMEOUT, - PARAM_ERROR, - IOE1_NOT_OPERATIONAL -}IOE_Status_TypDef; - -/** - * @brief IO bit values - */ -typedef enum -{ - BitReset = 0, - BitSet = 1 -}IOE_BitValue_TypeDef; - -/** - * @brief IOE DMA Direction - */ -typedef enum -{ - IOE_DMA_TX = 0, - IOE_DMA_RX = 1 -}IOE_DMADirection_TypeDef; - -/** - * @} - */ - -/** @defgroup STM32100E_EVAL_IOE_Exported_Constants - * @{ - */ - -/** - * @brief Uncomment the line below to enable verfying each written byte in write - * operation. The I2C_WriteDeviceRegister() function will then compare the - * written and read data and return error status if a mismatch occurs. - */ -/* #define VERIFY_WRITTENDATA */ - -/** - * @brief Uncomment the line below if you want to use user defined Delay function - * (for precise timing), otherwise default _delay_ function defined within - * this driver is used (less precise timing). - */ -/* #define USE_Delay */ - -/** - * @brief Uncomment the line below if you want to use user timeout callback. - * Function prototypes is declared in this file but function body may be - * implemented into user application. - */ -/* #define USE_TIMEOUT_USER_CALLBACK */ - -#ifdef USE_Delay -#include "main.h" - - #define _delay_ Delay /* !< User can provide more timing precise _delay_ function - (with 10ms time base), using SysTick for example */ -#else - #define _delay_ delay /* !< Default _delay_ function with less precise timing */ -#endif - -/*------------------------------------------------------------------------------ - Hardware Configuration -------------------------------------------------------------------------------*/ -/** - * @brief I2C port definitions - */ -#define IOE_I2C I2C2 -#define IOE_I2C_CLK RCC_APB1Periph_I2C2 -#define IOE_I2C_SCL_PIN GPIO_Pin_10 -#define IOE_I2C_SCL_GPIO_PORT GPIOB -#define IOE_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB -#define IOE_I2C_SDA_PIN GPIO_Pin_11 -#define IOE_I2C_SDA_GPIO_PORT GPIOB -#define IOE_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB -#define IOE_I2C_DR ((uint32_t)0x40005810) -#define IOE_I2C_SPEED 300000 - -/** - * @brief IOE DMA definitions - */ -#define IOE_DMA DMA1 -#define IOE_DMA_CLK RCC_AHBPeriph_DMA1 -#define IOE_DMA_TX_CHANNEL DMA1_Channel4 -#define IOE_DMA_RX_CHANNEL DMA1_Channel5 -#define IOE_DMA_TX_TCFLAG DMA1_FLAG_TC4 -#define IOE_DMA_RX_TCFLAG DMA1_FLAG_TC5 - - -/** - * @brief IO Expander Interrupt line on EXTI - */ -#define IOE_IT_PIN GPIO_Pin_12 -#define IOE_IT_GPIO_PORT GPIOA -#define IOE_IT_GPIO_CLK RCC_APB2Periph_GPIOA -#define IOE_IT_EXTI_PORT_SOURCE GPIO_PortSourceGPIOA -#define IOE_IT_EXTI_PIN_SOURCE GPIO_PinSource12 -#define IOE_IT_EXTI_LINE EXTI_Line12 -#define IOE_IT_EXTI_IRQn EXTI15_10_IRQn - - -/** - * @brief The 7 bits IO Expanders adresses and chip IDs - */ -#define IOE_1_ADDR 0x82 -#define STMPE811_ID 0x0811 - - -/*------------------------------------------------------------------------------ - Functional and Interrupt Management -------------------------------------------------------------------------------*/ -/** - * @brief IO Expander Functionalities definitions - */ -#define IOE_ADC_FCT 0x01 -#define IOE_TS_FCT 0x02 -#define IOE_IO_FCT 0x04 -#define IOE_TEMPSENS_FCT 0x08 - -/** - * @brief Interrupt source configuration definitons - */ -#define IOE_ITSRC_TSC 0x01 /* IO_Exapnder 1 */ -#define IOE_ITSRC_TEMPSENS 0x08 /* IO_Exapnder 1 */ - -/** - * @brief Glaobal Interrupts definitions - */ -#define IOE_GIT_GPIO 0x80 -#define IOE_GIT_ADC 0x40 -#define IOE_GIT_TEMP 0x20 -#define IOE_GIT_FE 0x10 -#define IOE_GIT_FF 0x08 -#define IOE_GIT_FOV 0x04 -#define IOE_GIT_FTH 0x02 -#define IOE_GIT_TOUCH 0x01 - -/** - * @brief IO Exapanders Pins definition - */ -#define IO1_IN_ALL_PINS (uint32_t)(IO_Pin_ALL) -#define IO1_OUT_ALL_PINS (uint32_t)(IO_Pin_ALL) - - -/*------------------------------------------------------------------------------ - STMPE811 device register definition -------------------------------------------------------------------------------*/ -/** - * @brief Identification registers - */ -#define IOE_REG_CHP_ID 0x00 -#define IOE_REG_ID_VER 0x02 - -/** - * @brief General Control Registers - */ -#define IOE_REG_SYS_CTRL1 0x03 -#define IOE_REG_SYS_CTRL2 0x04 -#define IOE_REG_SPI_CFG 0x08 - -/** - * @brief Interrupt Control register - */ -#define IOE_REG_INT_CTRL 0x09 -#define IOE_REG_INT_EN 0x0A -#define IOE_REG_INT_STA 0x0B -#define IOE_REG_GPIO_INT_EN 0x0C -#define IOE_REG_GPIO_INT_STA 0x0D - -/** - * @brief GPIO Registers - */ -#define IOE_REG_GPIO_SET_PIN 0x10 -#define IOE_REG_GPIO_CLR_PIN 0x11 -#define IOE_REG_GPIO_MP_STA 0x12 -#define IOE_REG_GPIO_DIR 0x13 -#define IOE_REG_GPIO_ED 0x14 -#define IOE_REG_GPIO_RE 0x15 -#define IOE_REG_GPIO_FE 0x16 -#define IOE_REG_GPIO_AF 0x17 - -/** - * @brief ADC Registers - */ -#define IOE_REG_ADC_INT_EN 0x0E -#define IOE_REG_ADC_INT_STA 0x0F -#define IOE_REG_ADC_CTRL1 0x20 -#define IOE_REG_ADC_CTRL2 0x21 -#define IOE_REG_ADC_CAPT 0x22 -#define IOE_REG_ADC_DATA_CH0 0x30 /* 16-Bit register */ -#define IOE_REG_ADC_DATA_CH1 0x32 /* 16-Bit register */ -#define IOE_REG_ADC_DATA_CH2 0x34 /* 16-Bit register */ -#define IOE_REG_ADC_DATA_CH3 0x36 /* 16-Bit register */ -#define IOE_REG_ADC_DATA_CH4 0x38 /* 16-Bit register */ -#define IOE_REG_ADC_DATA_CH5 0x3A /* 16-Bit register */ -#define IOE_REG_ADC_DATA_CH6 0x3B /* 16-Bit register */ -#define IOE_REG_ADC_DATA_CH7 0x3C /* 16-Bit register */ - -/** - * @brief TouchScreen Registers - */ -#define IOE_REG_TSC_CTRL 0x40 -#define IOE_REG_TSC_CFG 0x41 -#define IOE_REG_WDM_TR_X 0x42 -#define IOE_REG_WDM_TR_Y 0x44 -#define IOE_REG_WDM_BL_X 0x46 -#define IOE_REG_WDM_BL_Y 0x48 -#define IOE_REG_FIFO_TH 0x4A -#define IOE_REG_FIFO_STA 0x4B -#define IOE_REG_FIFO_SIZE 0x4C -#define IOE_REG_TSC_DATA_X 0x4D -#define IOE_REG_TSC_DATA_Y 0x4F -#define IOE_REG_TSC_DATA_Z 0x51 -#define IOE_REG_TSC_DATA_XYZ 0x52 -#define IOE_REG_TSC_FRACT_XYZ 0x56 -#define IOE_REG_TSC_DATA 0x57 -#define IOE_REG_TSC_I_DRIVE 0x58 -#define IOE_REG_TSC_SHIELD 0x59 - -/** - * @brief Temperature Sensor registers - */ -#define IOE_REG_TEMP_CTRL 0x60 -#define IOE_REG_TEMP_DATA 0x61 -#define IOE_REG_TEMP_TH 0x62 - -/*------------------------------------------------------------------------------ - Functions parameters defines -------------------------------------------------------------------------------*/ -/** - * @brief Touch Screen Pins definition - */ -#define TOUCH_YD IO_Pin_1 /* IO_Exapnader_1 */ /* Input */ -#define TOUCH_XD IO_Pin_2 /* IO_Exapnader_1 */ /* Input */ -#define TOUCH_YU IO_Pin_3 /* IO_Exapnader_1 */ /* Input */ -#define TOUCH_XU IO_Pin_4 /* IO_Exapnader_1 */ /* Input */ -#define TOUCH_IO_ALL (uint32_t)(IO_Pin_1 | IO_Pin_2 | IO_Pin_3 | IO_Pin_4) - -/** - * @brief IO Pins - */ -#define IO_Pin_0 0x01 -#define IO_Pin_1 0x02 -#define IO_Pin_2 0x04 -#define IO_Pin_3 0x08 -#define IO_Pin_4 0x10 -#define IO_Pin_5 0x20 -#define IO_Pin_6 0x40 -#define IO_Pin_7 0x80 -#define IO_Pin_ALL 0xFF - -/** - * @brief IO Pin directions - */ -#define Direction_IN 0x00 -#define Direction_OUT 0x01 - -/** - * @brief Interrupt Line output parameters - */ -#define Polarity_Low 0x00 -#define Polarity_High 0x04 -#define Type_Level 0x00 -#define Type_Edge 0x02 - -/** - * @brief IO Interrupts - */ -#define IO_IT_0 0x01 -#define IO_IT_1 0x02 -#define IO_IT_2 0x04 -#define IO_IT_3 0x08 -#define IO_IT_4 0x10 -#define IO_IT_5 0x20 -#define IO_IT_6 0x40 -#define IO_IT_7 0x80 -#define ALL_IT 0xFF -#define IOE_TS_IT (uint8_t)(IO_IT_0 | IO_IT_1 | IO_IT_2) - -/** - * @brief Edge detection value - */ -#define EDGE_FALLING 0x01 -#define EDGE_RISING 0x02 - -/** - * @brief Global interrupt Enable bit - */ -#define IOE_GIT_EN 0x01 - -/** - * @} - */ - - - -/** @defgroup STM32100E_EVAL_IOE_Exported_Macros - * @{ - */ -/** - * @} - */ - - - -/** @defgroup STM32100E_EVAL_IOE_Exported_Functions - * @{ - */ - -/** - * @brief Configuration and initialization functions - */ -uint8_t IOE_Config(void); -uint8_t IOE_ITConfig(uint32_t IOE_ITSRC_Source); - -/** - * @brief Timeout user callback function. This function is called when a timeout - * condition occurs during communication with IO Expander. Only protoype - * of this function is decalred in IO Expander driver. Its implementation - * may be done into user application. This function may typically stop - * current operations and reset the I2C peripheral and IO Expander. - * To enable this function use uncomment the define USE_TIMEOUT_USER_CALLBACK - * at the top of this file. - */ -#ifdef USE_TIMEOUT_USER_CALLBACK - uint8_t IOE_TimeoutUserCallback(void); -#else - #define IOE_TimeoutUserCallback() IOE_TIMEOUT -#endif /* USE_TIMEOUT_USER_CALLBACK */ - -/** - * @brief IO pins control functions - */ -uint8_t IOE_WriteIOPin(uint8_t IO_Pin, IOE_BitValue_TypeDef BitVal); -uint8_t IOE_ReadIOPin(uint32_t IO_Pin); - -/** - * @brief Touch Screen controller functions - */ -TS_STATE* IOE_TS_GetState(void); - -/** - * @brief Interrupts Mangement functions - */ -FlagStatus IOE_GetGITStatus(uint8_t DeviceAddr, uint8_t Global_IT); -uint8_t IOE_ClearGITPending(uint8_t DeviceAddr, uint8_t IO_IT); -FlagStatus IOE_GetIOITStatus(uint8_t DeviceAddr, uint8_t IO_IT); -uint8_t IOE_ClearIOITPending(uint8_t DeviceAddr, uint8_t IO_IT); - - -/** - * @brief Temperature Sensor functions - */ -uint32_t IOE_TempSens_GetData(void); - - -/** - * @brief IO-Expander Control functions - */ -uint8_t IOE_IsOperational(uint8_t DeviceAddr); -uint8_t IOE_Reset(uint8_t DeviceAddr); -uint16_t IOE_ReadID(uint8_t DeviceAddr); - -uint8_t IOE_FnctCmd(uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState); -uint8_t IOE_IOPinConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction); -uint8_t IOE_GITCmd(uint8_t DeviceAddr, FunctionalState NewState); -uint8_t IOE_GITConfig(uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState); -uint8_t IOE_IOITConfig(uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState); - -/** - * @brief Low Layer functions - */ -uint8_t IOE_TS_Config(void); -uint8_t IOE_TempSens_Config(void); -uint8_t IOE_IOAFConfig(uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState); -uint8_t IOE_IOEdgeConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge); -uint8_t IOE_ITOutConfig(uint8_t Polarity, uint8_t Type); - -uint8_t I2C_WriteDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue); -uint8_t I2C_ReadDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr); -uint16_t I2C_ReadDataBuffer(uint8_t DeviceAddr, uint32_t RegisterAddr); -#ifdef __cplusplus -} - -#endif -#endif /* __STM32100E_EVAL_IOE_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_lcd.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_lcd.c deleted file mode 100644 index 08905d8d1..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_lcd.c +++ /dev/null @@ -1,1419 +0,0 @@ -/** - ****************************************************************************** - * @file stm32100e_eval_lcd.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file includes the LCD driver for AM-240320L8TNQW00H - * (LCD_ILI9320), AM240320D5TOQW01H (LCD_ILI9325) and AM-240320LDTNQW00H - * (LCD_SPFD5408B) Liquid Crystal Display Module of STM32100E-EVAL board. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32100e_eval_lcd.h" -#include "../Common/fonts.c" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32100E_EVAL - * @{ - */ - -/** @defgroup STM32100E_EVAL_LCD - * @brief This file includes the LCD driver for AM-240320L8TNQW00H - * (LCD_ILI9320), AM240320D5TOQW01H (LCD_ILI9325) and AM-240320LDTNQW00H - * (LCD_SPFD5408B) Liquid Crystal Display Module of STM32100E-EVAL board. - * @{ - */ - -/** @defgroup STM32100E_EVAL_LCD_Private_TypesDefinitions - * @{ - */ -typedef struct -{ - __IO uint16_t LCD_REG; - __IO uint16_t LCD_RAM; -} LCD_TypeDef; -/** - * @} - */ - - -/** @defgroup STM32100E_EVAL_LCD_Private_Defines - * @{ - */ -/* Note: LCD /CS is CE4 - Bank 4 of NOR/SRAM Bank 1~4 */ -#define LCD_BASE ((uint32_t)(0x60000000 | 0x0C000000)) -#define LCD ((LCD_TypeDef *) LCD_BASE) -#define MAX_POLY_CORNERS 200 -#define POLY_Y(Z) ((int32_t)((Points + Z)->X)) -#define POLY_X(Z) ((int32_t)((Points + Z)->Y)) -/** - * @} - */ - -/** @defgroup STM32100E_EVAL_LCD_Private_Macros - * @{ - */ -#define ABS(X) ((X) > 0 ? (X) : -(X)) -/** - * @} - */ - -/** @defgroup STM32100E_EVAL_LCD_Private_Variables - * @{ - */ -static sFONT *LCD_Currentfonts; -/* Global variables to set the written text color */ -static __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF; - -/** - * @} - */ - - -/** @defgroup STM32100E_EVAL_LCD_Private_FunctionPrototypes - * @{ - */ -#ifndef USE_Delay -static void delay(vu32 nCount); -#endif /* USE_Delay*/ -static void PutPixel(int16_t x, int16_t y); -static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed); -/** - * @} - */ - - -/** @defgroup STM32100E_EVAL_LCD_Private_Functions - * @{ - */ - -/** - * @brief DeInitializes the LCD. - * @param None - * @retval None - */ -void LCD_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< LCD Display Off */ - LCD_DisplayOff(); - - /* BANK 4 (of NOR/SRAM Bank 1~4) is disabled */ - FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE); - - /*!< LCD_SPI DeInit */ - FSMC_NORSRAMDeInit(FSMC_Bank1_NORSRAM4); - - /* Set PD.00(D2), PD.01(D3), PD.04(NOE), PD.05(NWE), PD.08(D13), PD.09(D14), - PD.10(D15), PD.14(D0), PD.15(D1) as input floating */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | - GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 | - GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(GPIOD, &GPIO_InitStructure); - /* Set PE.07(D4), PE.08(D5), PE.09(D6), PE.10(D7), PE.11(D8), PE.12(D9), PE.13(D10), - PE.14(D11), PE.15(D12) as alternate function push pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | - GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | - GPIO_Pin_15; - GPIO_Init(GPIOE, &GPIO_InitStructure); - /* Set PF.00(A0 (RS)) as alternate function push pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; - GPIO_Init(GPIOF, &GPIO_InitStructure); - /* Set PG.12(NE4 (LCD/CS)) as alternate function push pull - CE3(LCD /CS) */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; - GPIO_Init(GPIOG, &GPIO_InitStructure); -} - -/** - * @brief Initializes the LCD. - * @param None - * @retval None - */ -void STM32100E_LCD_Init(void) -{ - __IO uint32_t lcdid = 0; - -/* Configure the LCD Control pins --------------------------------------------*/ - LCD_CtrlLinesConfig(); -/* Configure the FSMC Parallel interface -------------------------------------*/ - LCD_FSMCConfig(); - - _delay_(5); /* delay 50 ms */ - - /* Read the LCD ID */ - lcdid = LCD_ReadReg(0x00); - - /* Check if the LCD is SPFD5408B Controller */ - if(lcdid == 0x5408) - { - /* Start Initial Sequence ------------------------------------------------*/ - LCD_WriteReg(LCD_REG_1, 0x0100); /* Set SS bit */ - LCD_WriteReg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ - LCD_WriteReg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ - LCD_WriteReg(LCD_REG_4, 0x0000); /* Resize register */ - LCD_WriteReg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ - LCD_WriteReg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ - LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */ - LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB 18-bit System interface setting */ - LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */ - LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity, no impact */ - /* Power On sequence -----------------------------------------------------*/ - LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ - _delay_(20); /* Dis-charge capacitor power voltage (200ms) */ - LCD_WriteReg(LCD_REG_17, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_16, 0x12B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_18, 0x01BD); /* External reference voltage= Vci */ - _delay_(5); - LCD_WriteReg(LCD_REG_19, 0x1400); /* VDV[4:0] for VCOM amplitude */ - LCD_WriteReg(LCD_REG_41, 0x000E); /* VCM[4:0] for VCOMH */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ - LCD_WriteReg(LCD_REG_33, 0x013F); /* GRAM Vertical Address */ - /* Adjust the Gamma Curve (SPFD5408B)-------------------------------------*/ - LCD_WriteReg(LCD_REG_48, 0x0b0d); - LCD_WriteReg(LCD_REG_49, 0x1923); - LCD_WriteReg(LCD_REG_50, 0x1c26); - LCD_WriteReg(LCD_REG_51, 0x261c); - LCD_WriteReg(LCD_REG_52, 0x2419); - LCD_WriteReg(LCD_REG_53, 0x0d0b); - LCD_WriteReg(LCD_REG_54, 0x1006); - LCD_WriteReg(LCD_REG_55, 0x0610); - LCD_WriteReg(LCD_REG_56, 0x0706); - LCD_WriteReg(LCD_REG_57, 0x0304); - LCD_WriteReg(LCD_REG_58, 0x0e05); - LCD_WriteReg(LCD_REG_59, 0x0e01); - LCD_WriteReg(LCD_REG_60, 0x010e); - LCD_WriteReg(LCD_REG_61, 0x050e); - LCD_WriteReg(LCD_REG_62, 0x0403); - LCD_WriteReg(LCD_REG_63, 0x0607); - /* Set GRAM area ---------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ - LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */ - LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ - LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */ - LCD_WriteReg(LCD_REG_96, 0xA700); /* Gate Scan Line */ - LCD_WriteReg(LCD_REG_97, 0x0001); /* NDL, VLE, REV */ - LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */ - /* Partial Display Control -----------------------------------------------*/ - LCD_WriteReg(LCD_REG_128, 0x0000); - LCD_WriteReg(LCD_REG_129, 0x0000); - LCD_WriteReg(LCD_REG_130, 0x0000); - LCD_WriteReg(LCD_REG_131, 0x0000); - LCD_WriteReg(LCD_REG_132, 0x0000); - LCD_WriteReg(LCD_REG_133, 0x0000); - /* Panel Control ---------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_144, 0x0010); - LCD_WriteReg(LCD_REG_146, 0x0000); - LCD_WriteReg(LCD_REG_147, 0x0003); - LCD_WriteReg(LCD_REG_149, 0x0110); - LCD_WriteReg(LCD_REG_151, 0x0000); - LCD_WriteReg(LCD_REG_152, 0x0000); - /* Set GRAM write direction and BGR=1 - I/D=01 (Horizontal : increment, Vertical : decrement) - AM=1 (address is updated in vertical writing direction) */ - LCD_WriteReg(LCD_REG_3, 0x1018); - LCD_WriteReg(LCD_REG_7, 0x0112); /* 262K color and display ON */ - LCD_SetFont(&LCD_DEFAULT_FONT); - return; - } - else if(lcdid == 0x9325) /* Check if the LCD is ILI9325 Controller */ - { - /* Start Initial Sequence ------------------------------------------------*/ - LCD_WriteReg(LCD_REG_0, 0x0001); /* Start internal OSC. */ - LCD_WriteReg(LCD_REG_1, 0x0100); /* Set SS and SM bit */ - LCD_WriteReg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ - LCD_WriteReg(LCD_REG_3, 0x1018); /* Set GRAM write direction and BGR=1. */ - LCD_WriteReg(LCD_REG_4, 0x0000); /* Resize register */ - LCD_WriteReg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ - LCD_WriteReg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ - LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */ - LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */ - LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */ - LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */ - - /* Power On sequence -----------------------------------------------------*/ - LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ - _delay_(20); /* Dis-charge capacitor power voltage (200ms) */ - LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ - LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ - LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */ - - /* Adjust the Gamma Curve (ILI9325)---------------------------------------*/ - LCD_WriteReg(LCD_REG_48, 0x0007); - LCD_WriteReg(LCD_REG_49, 0x0302); - LCD_WriteReg(LCD_REG_50, 0x0105); - LCD_WriteReg(LCD_REG_53, 0x0206); - LCD_WriteReg(LCD_REG_54, 0x0808); - LCD_WriteReg(LCD_REG_55, 0x0206); - LCD_WriteReg(LCD_REG_56, 0x0504); - LCD_WriteReg(LCD_REG_57, 0x0007); - LCD_WriteReg(LCD_REG_60, 0x0105); - LCD_WriteReg(LCD_REG_61, 0x0808); - - /* Set GRAM area ---------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ - LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */ - LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ - LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */ - - LCD_WriteReg(LCD_REG_96, 0xA700); /* Gate Scan Line(GS=1, scan direction is G320~G1) */ - LCD_WriteReg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ - LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */ - - /* Partial Display Control -----------------------------------------------*/ - LCD_WriteReg(LCD_REG_128, 0x0000); - LCD_WriteReg(LCD_REG_129, 0x0000); - LCD_WriteReg(LCD_REG_130, 0x0000); - LCD_WriteReg(LCD_REG_131, 0x0000); - LCD_WriteReg(LCD_REG_132, 0x0000); - LCD_WriteReg(LCD_REG_133, 0x0000); - - /* Panel Control ---------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_144, 0x0010); - LCD_WriteReg(LCD_REG_146, 0x0000); - LCD_WriteReg(LCD_REG_147, 0x0003); - LCD_WriteReg(LCD_REG_149, 0x0110); - LCD_WriteReg(LCD_REG_151, 0x0000); - LCD_WriteReg(LCD_REG_152, 0x0000); - - /* set GRAM write direction and BGR = 1 */ - /* I/D=00 (Horizontal : increment, Vertical : decrement) */ - /* AM=1 (address is updated in vertical writing direction) */ - LCD_WriteReg(LCD_REG_3, 0x1018); - - LCD_WriteReg(LCD_REG_7, 0x0133); /* 262K color and display ON */ - LCD_SetFont(&LCD_DEFAULT_FONT); - return; - } - /* Check if the LCD is ILI9320 Controller */ -/* Start Initial Sequence ----------------------------------------------------*/ - LCD_WriteReg(LCD_REG_229,0x8000); /* Set the internal vcore voltage */ - LCD_WriteReg(LCD_REG_0, 0x0001); /* Start internal OSC. */ - LCD_WriteReg(LCD_REG_1, 0x0100); /* set SS and SM bit */ - LCD_WriteReg(LCD_REG_2, 0x0700); /* set 1 line inversion */ - LCD_WriteReg(LCD_REG_3, 0x1030); /* set GRAM write direction and BGR=1. */ - LCD_WriteReg(LCD_REG_4, 0x0000); /* Resize register */ - LCD_WriteReg(LCD_REG_8, 0x0202); /* set the back porch and front porch */ - LCD_WriteReg(LCD_REG_9, 0x0000); /* set non-display area refresh cycle ISC[3:0] */ - LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */ - LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */ - LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */ - LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */ -/* Power On sequence ---------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ - _delay_(20); /* Dis-charge capacitor power voltage (200ms) */ - LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ - LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ - LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */ -/* Adjust the Gamma Curve ----------------------------------------------------*/ - LCD_WriteReg(LCD_REG_48, 0x0006); - LCD_WriteReg(LCD_REG_49, 0x0101); - LCD_WriteReg(LCD_REG_50, 0x0003); - LCD_WriteReg(LCD_REG_53, 0x0106); - LCD_WriteReg(LCD_REG_54, 0x0b02); - LCD_WriteReg(LCD_REG_55, 0x0302); - LCD_WriteReg(LCD_REG_56, 0x0707); - LCD_WriteReg(LCD_REG_57, 0x0007); - LCD_WriteReg(LCD_REG_60, 0x0600); - LCD_WriteReg(LCD_REG_61, 0x020b); - -/* Set GRAM area -------------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ - LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */ - LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ - LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */ - LCD_WriteReg(LCD_REG_96, 0x2700); /* Gate Scan Line */ - LCD_WriteReg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ - LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */ -/* Partial Display Control ---------------------------------------------------*/ - LCD_WriteReg(LCD_REG_128, 0x0000); - LCD_WriteReg(LCD_REG_129, 0x0000); - LCD_WriteReg(LCD_REG_130, 0x0000); - LCD_WriteReg(LCD_REG_131, 0x0000); - LCD_WriteReg(LCD_REG_132, 0x0000); - LCD_WriteReg(LCD_REG_133, 0x0000); -/* Panel Control -------------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_144, 0x0010); - LCD_WriteReg(LCD_REG_146, 0x0000); - LCD_WriteReg(LCD_REG_147, 0x0003); - LCD_WriteReg(LCD_REG_149, 0x0110); - LCD_WriteReg(LCD_REG_151, 0x0000); - LCD_WriteReg(LCD_REG_152, 0x0000); - /* Set GRAM write direction and BGR = 1 */ - /* I/D=01 (Horizontal : increment, Vertical : decrement) */ - /* AM=1 (address is updated in vertical writing direction) */ - LCD_WriteReg(LCD_REG_3, 0x1018); - LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */ - LCD_SetFont(&LCD_DEFAULT_FONT); -} - -/** - * @brief Sets the LCD Text and Background colors. - * @param _TextColor: specifies the Text Color. - * @param _BackColor: specifies the Background Color. - * @retval None - */ -void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor) -{ - TextColor = _TextColor; - BackColor = _BackColor; -} - -/** - * @brief Gets the LCD Text and Background colors. - * @param _TextColor: pointer to the variable that will contain the Text - Color. - * @param _BackColor: pointer to the variable that will contain the Background - Color. - * @retval None - */ -void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor) -{ - *_TextColor = TextColor; *_BackColor = BackColor; -} - -/** - * @brief Sets the Text color. - * @param Color: specifies the Text color code RGB(5-6-5). - * @retval None - */ -void LCD_SetTextColor(__IO uint16_t Color) -{ - TextColor = Color; -} - - -/** - * @brief Sets the Background color. - * @param Color: specifies the Background color code RGB(5-6-5). - * @retval None - */ -void LCD_SetBackColor(__IO uint16_t Color) -{ - BackColor = Color; -} - -/** - * @brief Sets the Text Font. - * @param fonts: specifies the font to be used. - * @retval None - */ -void LCD_SetFont(sFONT *fonts) -{ - LCD_Currentfonts = fonts; -} - -/** - * @brief Gets the Text Font. - * @param None. - * @retval the used font. - */ -sFONT *LCD_GetFont(void) -{ - return LCD_Currentfonts; -} - -/** - * @brief Clears the selected line. - * @param Line: the Line to be cleared. - * This parameter can be one of the following values: - * @arg Linex: where x can be 0..n - * @retval None - */ -void LCD_ClearLine(uint8_t Line) -{ - uint16_t refcolumn = LCD_PIXEL_WIDTH - 1; - /* Send the string character by character on lCD */ - while (((refcolumn + 1)&0xFFFF) >= LCD_Currentfonts->Width) - { - /* Display one character on LCD */ - LCD_DisplayChar(Line, refcolumn, ' '); - /* Decrement the column position by 16 */ - refcolumn -= LCD_Currentfonts->Width; - } -} - - -/** - * @brief Clears the hole LCD. - * @param Color: the color of the background. - * @retval None - */ -void LCD_Clear(uint16_t Color) -{ - uint32_t index = 0; - - LCD_SetCursor(0x00, 0x013F); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - for(index = 0; index < 76800; index++) - { - LCD->LCD_RAM = Color; - } -} - - -/** - * @brief Sets the cursor position. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @retval None - */ -void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos) -{ - LCD_WriteReg(LCD_REG_32, Xpos); - LCD_WriteReg(LCD_REG_33, Ypos); -} - - -/** - * @brief Draws a character on LCD. - * @param Xpos: the Line where to display the character shape. - * @param Ypos: start column address. - * @param c: pointer to the character data. - * @retval None - */ -void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c) -{ - uint32_t index = 0, i = 0; - uint8_t Xaddress = 0; - - Xaddress = Xpos; - - LCD_SetCursor(Xaddress, Ypos); - - for(index = 0; index < LCD_Currentfonts->Height; index++) - { - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - for(i = 0; i < LCD_Currentfonts->Width; i++) - { - if((((c[index] & ((0x80 << ((LCD_Currentfonts->Width / 12 ) * 8 ) ) >> i)) == 0x00) &&(LCD_Currentfonts->Width <= 12))|| - (((c[index] & (0x1 << i)) == 0x00)&&(LCD_Currentfonts->Width > 12 ))) - - { - LCD_WriteRAM(BackColor); - } - else - { - LCD_WriteRAM(TextColor); - } - } - Xaddress++; - LCD_SetCursor(Xaddress, Ypos); - } -} - - -/** - * @brief Displays one character (16dots width, 24dots height). - * @param Line: the Line where to display the character shape . - * This parameter can be one of the following values: - * @arg Linex: where x can be 0..9 - * @param Column: start column address. - * @param Ascii: character ascii code, must be between 0x20 and 0x7E. - * @retval None - */ -void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii) -{ - Ascii -= 32; - LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]); -} - - -/** - * @brief Displays a maximum of 20 char on the LCD. - * @param Line: the Line where to display the character shape . - * This parameter can be one of the following values: - * @arg Linex: where x can be 0..9 - * @param *ptr: pointer to string to display on LCD. - * @retval None - */ -void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr) -{ - uint16_t refcolumn = LCD_PIXEL_WIDTH - 1; - - /* Send the string character by character on lCD */ - while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width)) - { - /* Display one character on LCD */ - LCD_DisplayChar(Line, refcolumn, *ptr); - /* Decrement the column position by 16 */ - refcolumn -= LCD_Currentfonts->Width; - /* Point on the next character */ - ptr++; - } -} - - -/** - * @brief Sets a display window - * @param Xpos: specifies the X buttom left position. - * @param Ypos: specifies the Y buttom left position. - * @param Height: display window height. - * @param Width: display window width. - * @retval None - */ -void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width) -{ - /* Horizontal GRAM Start Address */ - if(Xpos >= Height) - { - LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1)); - } - else - { - LCD_WriteReg(LCD_REG_80, 0); - } - /* Horizontal GRAM End Address */ - LCD_WriteReg(LCD_REG_81, Xpos); - /* Vertical GRAM Start Address */ - if(Ypos >= Width) - { - LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1)); - } - else - { - LCD_WriteReg(LCD_REG_82, 0); - } - /* Vertical GRAM End Address */ - LCD_WriteReg(LCD_REG_83, Ypos); - LCD_SetCursor(Xpos, Ypos); -} - - -/** - * @brief Disables LCD Window mode. - * @param None - * @retval None - */ -void LCD_WindowModeDisable(void) -{ - LCD_SetDisplayWindow(239, 0x13F, 240, 320); - LCD_WriteReg(LCD_REG_3, 0x1018); -} - - -/** - * @brief Displays a line. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Length: line length. - * @param Direction: line direction. - * This parameter can be one of the following values: Vertical or Horizontal. - * @retval None - */ -void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction) -{ - uint32_t i = 0; - - LCD_SetCursor(Xpos, Ypos); - if(Direction == LCD_DIR_HORIZONTAL) - { - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - for(i = 0; i < Length; i++) - { - LCD_WriteRAM(TextColor); - } - } - else - { - for(i = 0; i < Length; i++) - { - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - LCD_WriteRAM(TextColor); - Xpos++; - LCD_SetCursor(Xpos, Ypos); - } - } -} - - -/** - * @brief Displays a rectangle. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Height: display rectangle height. - * @param Width: display rectangle width. - * @retval None - */ -void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width) -{ - LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL); - LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL); - - LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL); - LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL); -} - - -/** - * @brief Displays a circle. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Radius - * @retval None - */ -void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius) -{ - int32_t D;/* Decision Variable */ - uint32_t CurX;/* Current X Value */ - uint32_t CurY;/* Current Y Value */ - - D = 3 - (Radius << 1); - CurX = 0; - CurY = Radius; - - while (CurX <= CurY) - { - LCD_SetCursor(Xpos + CurX, Ypos + CurY); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - LCD_WriteRAM(TextColor); - LCD_SetCursor(Xpos + CurX, Ypos - CurY); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - LCD_WriteRAM(TextColor); - LCD_SetCursor(Xpos - CurX, Ypos + CurY); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - LCD_WriteRAM(TextColor); - LCD_SetCursor(Xpos - CurX, Ypos - CurY); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - LCD_WriteRAM(TextColor); - LCD_SetCursor(Xpos + CurY, Ypos + CurX); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - LCD_WriteRAM(TextColor); - LCD_SetCursor(Xpos + CurY, Ypos - CurX); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - LCD_WriteRAM(TextColor); - LCD_SetCursor(Xpos - CurY, Ypos + CurX); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - LCD_WriteRAM(TextColor); - LCD_SetCursor(Xpos - CurY, Ypos - CurX); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - LCD_WriteRAM(TextColor); - if (D < 0) - { - D += (CurX << 2) + 6; - } - else - { - D += ((CurX - CurY) << 2) + 10; - CurY--; - } - CurX++; - } -} - - -/** - * @brief Displays a monocolor picture. - * @param Pict: pointer to the picture array. - * @retval None - */ -void LCD_DrawMonoPict(const uint32_t *Pict) -{ - uint32_t index = 0, i = 0; - LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1)); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - for(index = 0; index < 2400; index++) - { - for(i = 0; i < 32; i++) - { - if((Pict[index] & (1 << i)) == 0x00) - { - LCD_WriteRAM(BackColor); - } - else - { - LCD_WriteRAM(TextColor); - } - } - } -} - - -/** - * @brief Displays a bitmap picture loaded in the internal Flash. - * @param BmpAddress: Bmp picture address in the internal Flash. - * @retval None - */ -void LCD_WriteBMP(uint32_t BmpAddress) -{ - uint32_t index = 0, size = 0; - /* Read bitmap size */ - size = *(__IO uint16_t *) (BmpAddress + 2); - size |= (*(__IO uint16_t *) (BmpAddress + 4)) << 16; - /* Get bitmap data address offset */ - index = *(__IO uint16_t *) (BmpAddress + 10); - index |= (*(__IO uint16_t *) (BmpAddress + 12)) << 16; - size = (size - index)/2; - BmpAddress += index; - /* Set GRAM write direction and BGR = 1 */ - /* I/D=00 (Horizontal : decrement, Vertical : decrement) */ - /* AM=1 (address is updated in vertical writing direction) */ - LCD_WriteReg(LCD_REG_3, 0x1008); - - LCD_WriteRAM_Prepare(); - - for(index = 0; index < size; index++) - { - LCD_WriteRAM(*(__IO uint16_t *)BmpAddress); - BmpAddress += 2; - } - - /* Set GRAM write direction and BGR = 1 */ - /* I/D = 01 (Horizontal : increment, Vertical : decrement) */ - /* AM = 1 (address is updated in vertical writing direction) */ - LCD_WriteReg(LCD_REG_3, 0x1018); -} - -/** - * @brief Displays a full rectangle. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Height: rectangle height. - * @param Width: rectangle width. - * @retval None - */ -void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height) -{ - LCD_SetTextColor(TextColor); - - LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL); - LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL); - - LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL); - LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL); - - Width -= 2; - Height--; - Ypos--; - - LCD_SetTextColor(BackColor); - - while(Height--) - { - LCD_DrawLine(++Xpos, Ypos, Width, LCD_DIR_HORIZONTAL); - } - - LCD_SetTextColor(TextColor); -} - -/** - * @brief Displays a full circle. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Radius - * @retval None - */ -void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius) -{ - int32_t D; /* Decision Variable */ - uint32_t CurX;/* Current X Value */ - uint32_t CurY;/* Current Y Value */ - - D = 3 - (Radius << 1); - - CurX = 0; - CurY = Radius; - - LCD_SetTextColor(BackColor); - - while (CurX <= CurY) - { - if(CurY > 0) - { - LCD_DrawLine(Xpos - CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL); - LCD_DrawLine(Xpos + CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL); - } - - if(CurX > 0) - { - LCD_DrawLine(Xpos - CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL); - LCD_DrawLine(Xpos + CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL); - } - if (D < 0) - { - D += (CurX << 2) + 6; - } - else - { - D += ((CurX - CurY) << 2) + 10; - CurY--; - } - CurX++; - } - - LCD_SetTextColor(TextColor); - LCD_DrawCircle(Xpos, Ypos, Radius); -} - -/** - * @brief Displays an uni line (between two points). - * @param x1: specifies the point 1 x position. - * @param y1: specifies the point 1 y position. - * @param x2: specifies the point 2 x position. - * @param y2: specifies the point 2 y position. - * @retval None - */ -void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2) -{ - int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0, - yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0, - curpixel = 0; - - deltax = ABS(x2 - x1); /* The difference between the x's */ - deltay = ABS(y2 - y1); /* The difference between the y's */ - x = x1; /* Start x off at the first pixel */ - y = y1; /* Start y off at the first pixel */ - - if (x2 >= x1) /* The x-values are increasing */ - { - xinc1 = 1; - xinc2 = 1; - } - else /* The x-values are decreasing */ - { - xinc1 = -1; - xinc2 = -1; - } - - if (y2 >= y1) /* The y-values are increasing */ - { - yinc1 = 1; - yinc2 = 1; - } - else /* The y-values are decreasing */ - { - yinc1 = -1; - yinc2 = -1; - } - - if (deltax >= deltay) /* There is at least one x-value for every y-value */ - { - xinc1 = 0; /* Don't change the x when numerator >= denominator */ - yinc2 = 0; /* Don't change the y for every iteration */ - den = deltax; - num = deltax / 2; - numadd = deltay; - numpixels = deltax; /* There are more x-values than y-values */ - } - else /* There is at least one y-value for every x-value */ - { - xinc2 = 0; /* Don't change the x for every iteration */ - yinc1 = 0; /* Don't change the y when numerator >= denominator */ - den = deltay; - num = deltay / 2; - numadd = deltax; - numpixels = deltay; /* There are more y-values than x-values */ - } - - for (curpixel = 0; curpixel <= numpixels; curpixel++) - { - PutPixel(x, y); /* Draw the current pixel */ - num += numadd; /* Increase the numerator by the top of the fraction */ - if (num >= den) /* Check if numerator >= denominator */ - { - num -= den; /* Calculate the new numerator value */ - x += xinc1; /* Change the x as appropriate */ - y += yinc1; /* Change the y as appropriate */ - } - x += xinc2; /* Change the x as appropriate */ - y += yinc2; /* Change the y as appropriate */ - } -} - -/** - * @brief Displays an polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_PolyLine(pPoint Points, uint16_t PointCount) -{ - int16_t X = 0, Y = 0; - - if(PointCount < 2) - { - return; - } - - while(--PointCount) - { - X = Points->X; - Y = Points->Y; - Points++; - LCD_DrawUniLine(X, Y, Points->X, Points->Y); - } -} - -/** - * @brief Displays an relative polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @param Closed: specifies if the draw is closed or not. - * 1: closed, 0 : not closed. - * @retval None - */ -static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed) -{ - int16_t X = 0, Y = 0; - pPoint First = Points; - - if(PointCount < 2) - { - return; - } - X = Points->X; - Y = Points->Y; - while(--PointCount) - { - Points++; - LCD_DrawUniLine(X, Y, X + Points->X, Y + Points->Y); - X = X + Points->X; - Y = Y + Points->Y; - } - if(Closed) - { - LCD_DrawUniLine(First->X, First->Y, X, Y); - } -} - -/** - * @brief Displays a closed polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount) -{ - LCD_PolyLine(Points, PointCount); - LCD_DrawUniLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y); -} - -/** - * @brief Displays a relative polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount) -{ - LCD_PolyLineRelativeClosed(Points, PointCount, 0); -} - -/** - * @brief Displays a closed relative polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount) -{ - LCD_PolyLineRelativeClosed(Points, PointCount, 1); -} - - -/** - * @brief Displays a full polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_FillPolyLine(pPoint Points, uint16_t PointCount) -{ - /* public-domain code by Darel Rex Finley, 2007 */ - uint16_t nodes = 0, nodeX[MAX_POLY_CORNERS], pixelX = 0, pixelY = 0, i = 0, - j = 0, swap = 0; - uint16_t IMAGE_LEFT = 0, IMAGE_RIGHT = 0, IMAGE_TOP = 0, IMAGE_BOTTOM = 0; - - IMAGE_LEFT = IMAGE_RIGHT = Points->X; - IMAGE_TOP= IMAGE_BOTTOM = Points->Y; - - for(i = 1; i < PointCount; i++) - { - pixelX = POLY_X(i); - if(pixelX < IMAGE_LEFT) - { - IMAGE_LEFT = pixelX; - } - if(pixelX > IMAGE_RIGHT) - { - IMAGE_RIGHT = pixelX; - } - - pixelY = POLY_Y(i); - if(pixelY < IMAGE_TOP) - { - IMAGE_TOP = pixelY; - } - if(pixelY > IMAGE_BOTTOM) - { - IMAGE_BOTTOM = pixelY; - } - } - - LCD_SetTextColor(BackColor); - - /* Loop through the rows of the image. */ - for (pixelY = IMAGE_TOP; pixelY < IMAGE_BOTTOM; pixelY++) - { - /* Build a list of nodes. */ - nodes = 0; j = PointCount-1; - - for (i = 0; i < PointCount; i++) - { - if (POLY_Y(i)<(double) pixelY && POLY_Y(j)>=(double) pixelY || POLY_Y(j)<(double) pixelY && POLY_Y(i)>=(double) pixelY) - { - nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i))); - } - j = i; - } - - /* Sort the nodes, via a simple "Bubble" sort. */ - i = 0; - while (i < nodes-1) - { - if (nodeX[i]>nodeX[i+1]) - { - swap = nodeX[i]; - nodeX[i] = nodeX[i+1]; - nodeX[i+1] = swap; - if(i) - { - i--; - } - } - else - { - i++; - } - } - - /* Fill the pixels between node pairs. */ - for (i = 0; i < nodes; i+=2) - { - if(nodeX[i] >= IMAGE_RIGHT) - { - break; - } - if(nodeX[i+1] > IMAGE_LEFT) - { - if (nodeX[i] < IMAGE_LEFT) - { - nodeX[i]=IMAGE_LEFT; - } - if(nodeX[i+1] > IMAGE_RIGHT) - { - nodeX[i+1] = IMAGE_RIGHT; - } - LCD_SetTextColor(BackColor); - LCD_DrawLine(pixelY, nodeX[i+1], nodeX[i+1] - nodeX[i], LCD_DIR_HORIZONTAL); - LCD_SetTextColor(TextColor); - PutPixel(pixelY, nodeX[i+1]); - PutPixel(pixelY, nodeX[i]); - /* for (j=nodeX[i]; jLCD_REG = LCD_Reg; - /* Write 16-bit Reg */ - LCD->LCD_RAM = LCD_RegValue; -} - - -/** - * @brief Reads the selected LCD Register. - * @param LCD_Reg: address of the selected register. - * @retval LCD Register Value. - */ -uint16_t LCD_ReadReg(uint8_t LCD_Reg) -{ - /* Write 16-bit Index (then Read Reg) */ - LCD->LCD_REG = LCD_Reg; - /* Read 16-bit Reg */ - return (LCD->LCD_RAM); -} - - -/** - * @brief Prepare to write to the LCD RAM. - * @param None - * @retval None - */ -void LCD_WriteRAM_Prepare(void) -{ - LCD->LCD_REG = LCD_REG_34; -} - - -/** - * @brief Writes to the LCD RAM. - * @param RGB_Code: the pixel color in RGB mode (5-6-5). - * @retval None - */ -void LCD_WriteRAM(uint16_t RGB_Code) -{ - /* Write 16-bit GRAM Reg */ - LCD->LCD_RAM = RGB_Code; -} - - -/** - * @brief Reads the LCD RAM. - * @param None - * @retval LCD RAM Value. - */ -uint16_t LCD_ReadRAM(void) -{ - /* Write 16-bit Index (then Read Reg) */ - LCD->LCD_REG = LCD_REG_34; /* Select GRAM Reg */ - /* Read 16-bit Reg */ - return LCD->LCD_RAM; -} - - -/** - * @brief Power on the LCD. - * @param None - * @retval None - */ -void LCD_PowerOn(void) -{ -/* Power On sequence ---------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude*/ - _delay_(20); /* Dis-charge capacitor power voltage (200ms) */ - LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ - LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */ -} - - -/** - * @brief Enables the Display. - * @param None - * @retval None - */ -void LCD_DisplayOn(void) -{ - /* Display On */ - LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */ -} - - -/** - * @brief Disables the Display. - * @param None - * @retval None - */ -void LCD_DisplayOff(void) -{ - /* Display Off */ - LCD_WriteReg(LCD_REG_7, 0x0); -} - - -/** - * @brief Configures LCD Control lines (FSMC Pins) in alternate function mode. - * @param None - * @retval None - */ -void LCD_CtrlLinesConfig(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable FSMC, GPIOD, GPIOE, GPIOF, GPIOG and AFIO clocks */ - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE); - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | - RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG | - RCC_APB2Periph_AFIO, ENABLE); - - /* Set PD.00(D2), PD.01(D3), PD.04(NOE), PD.05(NWE), PD.08(D13), PD.09(D14), - PD.10(D15), PD.14(D0), PD.15(D1) as alternate function push pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | - GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 | - GPIO_Pin_15; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - /* Set PE.07(D4), PE.08(D5), PE.09(D6), PE.10(D7), PE.11(D8), PE.12(D9), PE.13(D10), - PE.14(D11), PE.15(D12) as alternate function push pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | - GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | - GPIO_Pin_15; - GPIO_Init(GPIOE, &GPIO_InitStructure); - - /* Set PF.00(A0 (RS)) as alternate function push pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; - GPIO_Init(GPIOF, &GPIO_InitStructure); - - /* Set PG.12(NE4 (LCD/CS)) as alternate function push pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; - GPIO_Init(GPIOG, &GPIO_InitStructure); -} - -/** - * @brief Configures the Parallel interface (FSMC) for LCD(Parallel mode) - * @param None - * @retval None - */ -void LCD_FSMCConfig(void) -{ - FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; - FSMC_NORSRAMTimingInitTypeDef p; -/*-- FSMC Configuration ------------------------------------------------------*/ -/*----------------------- SRAM Bank 4 ----------------------------------------*/ - /* FSMC_Bank1_NORSRAM4 configuration */ - p.FSMC_AddressSetupTime = 1; - p.FSMC_AddressHoldTime = 0; - p.FSMC_DataSetupTime = 2; - p.FSMC_BusTurnAroundDuration = 0; - p.FSMC_CLKDivision = 0; - p.FSMC_DataLatency = 0; - p.FSMC_AccessMode = FSMC_AccessMode_A; - /* Color LCD configuration ------------------------------------ - LCD configured as follow: - - Data/Address MUX = Disable - - Memory Type = SRAM - - Data Width = 16bit - - Write Operation = Enable - - Extended Mode = Enable - - Asynchronous Wait = Disable */ - FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM4; - FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; - FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; - FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; - FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; - FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; - FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; - FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); - /* BANK 4 (of NOR/SRAM Bank) is enabled */ - FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE); -} - -/** - * @brief Displays a pixel. - * @param x: pixel x. - * @param y: pixel y. - * @retval None - */ -static void PutPixel(int16_t x, int16_t y) -{ - if(x < 0 || x > 239 || y < 0 || y > 319) - { - return; - } - LCD_DrawLine(x, y, 1, LCD_DIR_HORIZONTAL); -} - -#ifndef USE_Delay -/** - * @brief Inserts a delay time. - * @param nCount: specifies the delay time length. - * @retval None - */ -static void delay(vu32 nCount) -{ - vu32 index = 0; - for(index = (34000 * nCount); index != 0; index--) - { - } -} -#endif /* USE_Delay*/ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_lcd.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_lcd.h deleted file mode 100644 index f381e960c..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_lcd.h +++ /dev/null @@ -1,359 +0,0 @@ -/** - ****************************************************************************** - * @file stm32100e_eval_lcd.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains all the functions prototypes for the stm32100e_eval_lcd - * firmware driver. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32100E_EVAL_LCD_H -#define __STM32100E_EVAL_LCD_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" -#include "../Common/fonts.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32100E_EVAL - * @{ - */ - -/** @addtogroup STM32100E_EVAL_LCD - * @{ - */ - -/** @defgroup STM32100E_EVAL_LCD_Exported_Types - * @{ - */ -typedef struct -{ - int16_t X; - int16_t Y; -} Point, * pPoint; -/** - * @} - */ - -/** @defgroup STM32100E_EVAL_LCD_Exported_Constants - * @{ - */ - -/** - * @brief Uncomment the line below if you want to use user defined Delay function - * (for precise timing), otherwise default _delay_ function defined within - * this driver is used (less precise timing). - */ -/* #define USE_Delay */ - -#ifdef USE_Delay -#include "main.h" - #define _delay_ Delay /* !< User can provide more timing precise _delay_ function - (with 10ms time base), using SysTick for example */ -#else - #define _delay_ delay /* !< Default _delay_ function with less precise timing */ -#endif - -/** - * @brief LCD Registers - */ -#define LCD_REG_0 0x00 -#define LCD_REG_1 0x01 -#define LCD_REG_2 0x02 -#define LCD_REG_3 0x03 -#define LCD_REG_4 0x04 -#define LCD_REG_5 0x05 -#define LCD_REG_6 0x06 -#define LCD_REG_7 0x07 -#define LCD_REG_8 0x08 -#define LCD_REG_9 0x09 -#define LCD_REG_10 0x0A -#define LCD_REG_12 0x0C -#define LCD_REG_13 0x0D -#define LCD_REG_14 0x0E -#define LCD_REG_15 0x0F -#define LCD_REG_16 0x10 -#define LCD_REG_17 0x11 -#define LCD_REG_18 0x12 -#define LCD_REG_19 0x13 -#define LCD_REG_20 0x14 -#define LCD_REG_21 0x15 -#define LCD_REG_22 0x16 -#define LCD_REG_23 0x17 -#define LCD_REG_24 0x18 -#define LCD_REG_25 0x19 -#define LCD_REG_26 0x1A -#define LCD_REG_27 0x1B -#define LCD_REG_28 0x1C -#define LCD_REG_29 0x1D -#define LCD_REG_30 0x1E -#define LCD_REG_31 0x1F -#define LCD_REG_32 0x20 -#define LCD_REG_33 0x21 -#define LCD_REG_34 0x22 -#define LCD_REG_36 0x24 -#define LCD_REG_37 0x25 -#define LCD_REG_40 0x28 -#define LCD_REG_41 0x29 -#define LCD_REG_43 0x2B -#define LCD_REG_45 0x2D -#define LCD_REG_48 0x30 -#define LCD_REG_49 0x31 -#define LCD_REG_50 0x32 -#define LCD_REG_51 0x33 -#define LCD_REG_52 0x34 -#define LCD_REG_53 0x35 -#define LCD_REG_54 0x36 -#define LCD_REG_55 0x37 -#define LCD_REG_56 0x38 -#define LCD_REG_57 0x39 -#define LCD_REG_58 0x3A -#define LCD_REG_59 0x3B -#define LCD_REG_60 0x3C -#define LCD_REG_61 0x3D -#define LCD_REG_62 0x3E -#define LCD_REG_63 0x3F -#define LCD_REG_64 0x40 -#define LCD_REG_65 0x41 -#define LCD_REG_66 0x42 -#define LCD_REG_67 0x43 -#define LCD_REG_68 0x44 -#define LCD_REG_69 0x45 -#define LCD_REG_70 0x46 -#define LCD_REG_71 0x47 -#define LCD_REG_72 0x48 -#define LCD_REG_73 0x49 -#define LCD_REG_74 0x4A -#define LCD_REG_75 0x4B -#define LCD_REG_76 0x4C -#define LCD_REG_77 0x4D -#define LCD_REG_78 0x4E -#define LCD_REG_79 0x4F -#define LCD_REG_80 0x50 -#define LCD_REG_81 0x51 -#define LCD_REG_82 0x52 -#define LCD_REG_83 0x53 -#define LCD_REG_96 0x60 -#define LCD_REG_97 0x61 -#define LCD_REG_106 0x6A -#define LCD_REG_118 0x76 -#define LCD_REG_128 0x80 -#define LCD_REG_129 0x81 -#define LCD_REG_130 0x82 -#define LCD_REG_131 0x83 -#define LCD_REG_132 0x84 -#define LCD_REG_133 0x85 -#define LCD_REG_134 0x86 -#define LCD_REG_135 0x87 -#define LCD_REG_136 0x88 -#define LCD_REG_137 0x89 -#define LCD_REG_139 0x8B -#define LCD_REG_140 0x8C -#define LCD_REG_141 0x8D -#define LCD_REG_143 0x8F -#define LCD_REG_144 0x90 -#define LCD_REG_145 0x91 -#define LCD_REG_146 0x92 -#define LCD_REG_147 0x93 -#define LCD_REG_148 0x94 -#define LCD_REG_149 0x95 -#define LCD_REG_150 0x96 -#define LCD_REG_151 0x97 -#define LCD_REG_152 0x98 -#define LCD_REG_153 0x99 -#define LCD_REG_154 0x9A -#define LCD_REG_157 0x9D -#define LCD_REG_192 0xC0 -#define LCD_REG_193 0xC1 -#define LCD_REG_229 0xE5 - -/** - * @brief LCD color - */ -#define LCD_COLOR_WHITE 0xFFFF -#define LCD_COLOR_BLACK 0x0000 -#define LCD_COLOR_GREY 0xF7DE -#define LCD_COLOR_BLUE 0x001F -#define LCD_COLOR_BLUE2 0x051F -#define LCD_COLOR_RED 0xF800 -#define LCD_COLOR_MAGENTA 0xF81F -#define LCD_COLOR_GREEN 0x07E0 -#define LCD_COLOR_CYAN 0x7FFF -#define LCD_COLOR_YELLOW 0xFFE0 - -/** - * @brief LCD Lines depending on the chosen fonts. - */ -#define LCD_LINE_0 LINE(0) -#define LCD_LINE_1 LINE(1) -#define LCD_LINE_2 LINE(2) -#define LCD_LINE_3 LINE(3) -#define LCD_LINE_4 LINE(4) -#define LCD_LINE_5 LINE(5) -#define LCD_LINE_6 LINE(6) -#define LCD_LINE_7 LINE(7) -#define LCD_LINE_8 LINE(8) -#define LCD_LINE_9 LINE(9) -#define LCD_LINE_10 LINE(10) -#define LCD_LINE_11 LINE(11) -#define LCD_LINE_12 LINE(12) -#define LCD_LINE_13 LINE(13) -#define LCD_LINE_14 LINE(14) -#define LCD_LINE_15 LINE(15) -#define LCD_LINE_16 LINE(16) -#define LCD_LINE_17 LINE(17) -#define LCD_LINE_18 LINE(18) -#define LCD_LINE_19 LINE(19) -#define LCD_LINE_20 LINE(20) -#define LCD_LINE_21 LINE(21) -#define LCD_LINE_22 LINE(22) -#define LCD_LINE_23 LINE(23) -#define LCD_LINE_24 LINE(24) -#define LCD_LINE_25 LINE(25) -#define LCD_LINE_26 LINE(26) -#define LCD_LINE_27 LINE(27) -#define LCD_LINE_28 LINE(28) -#define LCD_LINE_29 LINE(29) - -/** - * @brief LCD default font - */ -#define LCD_DEFAULT_FONT Font16x24 - -/** - * @brief LCD Direction - */ -#define LCD_DIR_HORIZONTAL 0x0000 -#define LCD_DIR_VERTICAL 0x0001 - -/** - * @brief LCD Size (Width and Height) - */ -#define LCD_PIXEL_WIDTH 0x0140 -#define LCD_PIXEL_HEIGHT 0x00F0 - -/** - * @} - */ - -/** @defgroup STM32100E_EVAL_LCD_Exported_Macros - * @{ - */ -#define ASSEMBLE_RGB(R, G, B) ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3)) -/** - * @} - */ - -/** @defgroup STM32100E_EVAL_LCD_Exported_Functions - * @{ - */ -/** @defgroup - * @{ - */ -void LCD_DeInit(void); -void STM32100E_LCD_Init(void); -void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor); -void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor); -void LCD_SetTextColor(__IO uint16_t Color); -void LCD_SetBackColor(__IO uint16_t Color); -void LCD_ClearLine(uint8_t Line); -void LCD_Clear(uint16_t Color); -void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos); -void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c); -void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii); -void LCD_SetFont(sFONT *fonts); -sFONT *LCD_GetFont(void); -void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr); -void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width); -void LCD_WindowModeDisable(void); -void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction); -void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width); -void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius); -void LCD_DrawMonoPict(const uint32_t *Pict); -void LCD_WriteBMP(uint32_t BmpAddress); -void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2); -void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height); -void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius); -void LCD_PolyLine(pPoint Points, uint16_t PointCount); -void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount); -void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount); -void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount); -void LCD_FillPolyLine(pPoint Points, uint16_t PointCount); -/** - * @} - */ - -/** @defgroup - * @{ - */ -void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue); -uint16_t LCD_ReadReg(uint8_t LCD_Reg); -void LCD_WriteRAM_Prepare(void); -void LCD_WriteRAM(uint16_t RGB_Code); -uint16_t LCD_ReadRAM(void); -void LCD_PowerOn(void); -void LCD_DisplayOn(void); -void LCD_DisplayOff(void); -/** - * @} - */ - -/** @defgroup - * @{ - */ -void LCD_CtrlLinesConfig(void); -void LCD_FSMCConfig(void); -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __STM32100E_EVAL_LCD_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.c deleted file mode 100644 index 8e7768a5d..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.c +++ /dev/null @@ -1,620 +0,0 @@ -/** - ****************************************************************************** - * @file stm3210b_eval.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file provides - * - set of firmware functions to manage Leds, push-button and COM ports - * - low level initialization functions for SD card (on SPI), SPI serial - * flash (sFLASH) and temperature sensor (LM75) - * available on STM3210B-EVAL evaluation board from STMicroelectronics. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm3210b_eval.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM3210B_EVAL - * @{ - */ - -/** @defgroup STM3210B_EVAL_LOW_LEVEL - * @brief This file provides firmware functions to manage Leds, push-buttons, - * COM ports, SD card on SPI, serial flash (sFLASH), serial EEPROM (sEE) - * and temperature sensor (LM75) available on STM3210B-EVAL evaluation - * board from STMicroelectronics. - * @{ - */ - -/** @defgroup STM3210B_EVAL_LOW_LEVEL_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM3210B_EVAL_LOW_LEVEL_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM3210B_EVAL_LOW_LEVEL_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM3210B_EVAL_LOW_LEVEL_Private_Variables - * @{ - */ -GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT, - LED4_GPIO_PORT}; -const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN, - LED4_PIN}; -const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK, - LED4_GPIO_CLK}; - -GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT, - KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT, - LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT, - DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT}; - -const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN, - KEY_BUTTON_PIN, RIGHT_BUTTON_PIN, - LEFT_BUTTON_PIN, UP_BUTTON_PIN, - DOWN_BUTTON_PIN, SEL_BUTTON_PIN}; - -const uint32_t BUTTON_CLK[BUTTONn] = {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK, - KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK, - LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK, - DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK}; - -const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {WAKEUP_BUTTON_EXTI_LINE, - TAMPER_BUTTON_EXTI_LINE, - KEY_BUTTON_EXTI_LINE, - RIGHT_BUTTON_EXTI_LINE, - LEFT_BUTTON_EXTI_LINE, - UP_BUTTON_EXTI_LINE, - DOWN_BUTTON_EXTI_LINE, - SEL_BUTTON_EXTI_LINE}; - -const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PORT_SOURCE, - TAMPER_BUTTON_EXTI_PORT_SOURCE, - KEY_BUTTON_EXTI_PORT_SOURCE, - RIGHT_BUTTON_EXTI_PORT_SOURCE, - LEFT_BUTTON_EXTI_PORT_SOURCE, - UP_BUTTON_EXTI_PORT_SOURCE, - DOWN_BUTTON_EXTI_PORT_SOURCE, - SEL_BUTTON_EXTI_PORT_SOURCE}; - -const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PIN_SOURCE, - TAMPER_BUTTON_EXTI_PIN_SOURCE, - KEY_BUTTON_EXTI_PIN_SOURCE, - RIGHT_BUTTON_EXTI_PIN_SOURCE, - LEFT_BUTTON_EXTI_PIN_SOURCE, - UP_BUTTON_EXTI_PIN_SOURCE, - DOWN_BUTTON_EXTI_PIN_SOURCE, - SEL_BUTTON_EXTI_PIN_SOURCE}; - -const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn, - KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn, - LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn, - DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn}; - -USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2}; - -GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT}; - -GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT}; - -const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK}; - -const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK}; - -const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK}; - -const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN}; - -const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN}; - - -/** - * @} - */ - - -/** @defgroup STM3210B_EVAL_LOW_LEVEL_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - - -/** @defgroup STM3210B_EVAL_LOW_LEVEL_Private_Functions - * @{ - */ - -/** - * @brief Configures LED GPIO. - * @param Led: Specifies the Led to be configured. - * This parameter can be one of following parameters: - * @arg LED1 - * @arg LED2 - * @arg LED3 - * @arg LED4 - * @retval None - */ -void STM_EVAL_LEDInit(Led_TypeDef Led) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable the GPIO_LED Clock */ - RCC_APB2PeriphClockCmd(GPIO_CLK[Led], ENABLE); - - /* Configure the GPIO_LED pin */ - GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led]; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - - GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure); -} - -/** - * @brief Turns selected LED On. - * @param Led: Specifies the Led to be set on. - * This parameter can be one of following parameters: - * @arg LED1 - * @arg LED2 - * @arg LED3 - * @arg LED4 - * @retval None - */ -void STM_EVAL_LEDOn(Led_TypeDef Led) -{ - GPIO_PORT[Led]->BSRR = GPIO_PIN[Led]; -} - -/** - * @brief Turns selected LED Off. - * @param Led: Specifies the Led to be set off. - * This parameter can be one of following parameters: - * @arg LED1 - * @arg LED2 - * @arg LED3 - * @arg LED4 - * @retval None - */ -void STM_EVAL_LEDOff(Led_TypeDef Led) -{ - GPIO_PORT[Led]->BRR = GPIO_PIN[Led]; -} - -/** - * @brief Toggles the selected LED. - * @param Led: Specifies the Led to be toggled. - * This parameter can be one of following parameters: - * @arg LED1 - * @arg LED2 - * @arg LED3 - * @arg LED4 - * @retval None - */ -void STM_EVAL_LEDToggle(Led_TypeDef Led) -{ - GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led]; -} - -/** - * @brief Configures Button GPIO and EXTI Line. - * @param Button: Specifies the Button to be configured. - * This parameter can be one of following parameters: - * @arg BUTTON_WAKEUP: Wakeup Push Button - * @arg BUTTON_TAMPER: Tamper Push Button - * @arg BUTTON_KEY: Key Push Button - * @arg BUTTON_RIGHT: Joystick Right Push Button - * @arg BUTTON_LEFT: Joystick Left Push Button - * @arg BUTTON_UP: Joystick Up Push Button - * @arg BUTTON_DOWN: Joystick Down Push Button - * @arg BUTTON_SEL: Joystick Sel Push Button - * @param Button_Mode: Specifies Button mode. - * This parameter can be one of following parameters: - * @arg BUTTON_MODE_GPIO: Button will be used as simple IO - * @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt - * generation capability - * @retval None - */ -void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode) -{ - GPIO_InitTypeDef GPIO_InitStructure; - EXTI_InitTypeDef EXTI_InitStructure; - NVIC_InitTypeDef NVIC_InitStructure; - - /* Enable the BUTTON Clock */ - RCC_APB2PeriphClockCmd(BUTTON_CLK[Button] | RCC_APB2Periph_AFIO, ENABLE); - - /* Configure Button pin as input floating */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button]; - GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure); - - - if (Button_Mode == BUTTON_MODE_EXTI) - { - /* Connect Button EXTI Line to Button GPIO Pin */ - GPIO_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]); - - /* Configure Button EXTI line */ - EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button]; - EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; - - if(Button != BUTTON_WAKEUP) - { - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; - } - else - { - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; - } - EXTI_InitStructure.EXTI_LineCmd = ENABLE; - EXTI_Init(&EXTI_InitStructure); - - /* Enable and set Button EXTI Interrupt to the lowest priority */ - NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button]; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - - NVIC_Init(&NVIC_InitStructure); - } -} - -/** - * @brief Returns the selected Button state. - * @param Button: Specifies the Button to be checked. - * This parameter can be one of following parameters: - * @arg BUTTON_WAKEUP: Wakeup Push Button - * @arg BUTTON_TAMPER: Tamper Push Button - * @arg BUTTON_KEY: Key Push Button - * @arg BUTTON_RIGHT: Joystick Right Push Button - * @arg BUTTON_LEFT: Joystick Left Push Button - * @arg BUTTON_UP: Joystick Up Push Button - * @arg BUTTON_DOWN: Joystick Down Push Button - * @arg BUTTON_SEL: Joystick Sel Push Button - * @retval The Button GPIO pin value. - */ -uint32_t STM_EVAL_PBGetState(Button_TypeDef Button) -{ - return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]); -} - -/** - * @brief Configures COM port. - * @param COM: Specifies the COM port to be configured. - * This parameter can be one of following parameters: - * @arg COM1 - * @arg COM2 - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that - * contains the configuration information for the specified USART peripheral. - * @retval None - */ -void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable GPIO clock */ - RCC_APB2PeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM] | RCC_APB2Periph_AFIO, ENABLE); - - if (COM == COM1) - { - RCC_APB2PeriphClockCmd(COM_USART_CLK[COM], ENABLE); - } - else - { - /* Enable the USART2 Pins Software Remapping */ - GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE); - RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE); - } - - /* Configure USART Tx as alternate function push-pull */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM]; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure); - - - /* Configure USART Rx as input floating */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM]; - GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure); - - /* USART configuration */ - USART_Init(COM_USART[COM], USART_InitStruct); - - /* Enable USART */ - USART_Cmd(COM_USART[COM], ENABLE); -} - -/** - * @brief DeInitializes the SD/SD communication. - * @param None - * @retval None - */ -void SD_LowLevel_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - SPI_Cmd(SD_SPI, DISABLE); /*!< SD_SPI disable */ - SPI_I2S_DeInit(SD_SPI); /*!< DeInitializes the SD_SPI */ - - /*!< SD_SPI Periph clock disable */ - RCC_APB2PeriphClockCmd(SD_SPI_CLK, DISABLE); - - /*!< Configure SD_SPI pins: SCK */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI pins: MISO */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN; - GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI pins: MOSI */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN; - GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */ - GPIO_InitStructure.GPIO_Pin = SD_CS_PIN; - GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */ - GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN; - GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @brief Initializes the SD_SPI and CS pins. - * @param None - * @retval None - */ -void SD_LowLevel_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - SPI_InitTypeDef SPI_InitStructure; - - /*!< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO - and SD_SPI_SCK_GPIO Periph clock enable */ - RCC_APB2PeriphClockCmd(SD_CS_GPIO_CLK | SD_SPI_MOSI_GPIO_CLK | SD_SPI_MISO_GPIO_CLK | - SD_SPI_SCK_GPIO_CLK | SD_DETECT_GPIO_CLK, ENABLE); - - /*!< SD_SPI Periph clock enable */ - RCC_APB2PeriphClockCmd(SD_SPI_CLK, ENABLE); - - - /*!< Configure SD_SPI pins: SCK */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI pins: MOSI */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN; - GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI pins: MISO */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */ - GPIO_InitStructure.GPIO_Pin = SD_CS_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */ - GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure); - - /*!< SD_SPI Config */ - SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; - SPI_InitStructure.SPI_Mode = SPI_Mode_Master; - SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; - SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; - SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; - SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; - SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4; - SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; - SPI_InitStructure.SPI_CRCPolynomial = 7; - SPI_Init(SD_SPI, &SPI_InitStructure); - - SPI_Cmd(SD_SPI, ENABLE); /*!< SD_SPI enable */ -} - -/** - * @brief DeInitializes the peripherals used by the SPI FLASH driver. - * @param None - * @retval None - */ -void sFLASH_LowLevel_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< Disable the sFLASH_SPI */ - SPI_Cmd(sFLASH_SPI, DISABLE); - - /*!< DeInitializes the sFLASH_SPI */ - SPI_I2S_DeInit(sFLASH_SPI); - - /*!< sFLASH_SPI Periph clock disable */ - RCC_APB2PeriphClockCmd(sFLASH_SPI_CLK, DISABLE); - - /*!< Configure sFLASH_SPI pins: SCK */ - GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sFLASH_SPI pins: MISO */ - GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN; - GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sFLASH_SPI pins: MOSI */ - GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN; - GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin */ - GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN; - GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @brief Initializes the peripherals used by the SPI FLASH driver. - * @param None - * @retval None - */ -void sFLASH_LowLevel_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO - and sFLASH_SPI_SCK_GPIO Periph clock enable */ - RCC_APB2PeriphClockCmd(sFLASH_CS_GPIO_CLK | sFLASH_SPI_MOSI_GPIO_CLK | sFLASH_SPI_MISO_GPIO_CLK | - sFLASH_SPI_SCK_GPIO_CLK, ENABLE); - - /*!< sFLASH_SPI Periph clock enable */ - RCC_APB2PeriphClockCmd(sFLASH_SPI_CLK, ENABLE); - - /*!< Configure sFLASH_SPI pins: SCK */ - GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sFLASH_SPI pins: MOSI */ - GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN; - GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sFLASH_SPI pins: MISO */ - GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin */ - GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @brief DeInitializes the LM75_I2C. - * @param None - * @retval None - */ -void LM75_LowLevel_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< Disable LM75_I2C */ - I2C_Cmd(LM75_I2C, DISABLE); - /*!< DeInitializes the LM75_I2C */ - I2C_DeInit(LM75_I2C); - - /*!< LM75_I2C Periph clock disable */ - RCC_APB1PeriphClockCmd(LM75_I2C_CLK, DISABLE); - - /*!< Configure LM75_I2C pins: SCL */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure LM75_I2C pins: SDA */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN; - GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure LM75_I2C pin: SMBUS ALERT */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN; - GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @brief Initializes the LM75_I2C. - * @param None - * @retval None - */ -void LM75_LowLevel_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< LM75_I2C Periph clock enable */ - RCC_APB1PeriphClockCmd(LM75_I2C_CLK, ENABLE); - - /*!< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK - and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable */ - RCC_APB2PeriphClockCmd(LM75_I2C_SCL_GPIO_CLK | LM75_I2C_SDA_GPIO_CLK | - LM75_I2C_SMBUSALERT_GPIO_CLK, ENABLE); - - /*!< Configure LM75_I2C pins: SCL */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD; - GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure LM75_I2C pins: SDA */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN; - GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure LM75_I2C pin: SMBUS ALERT */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.h deleted file mode 100644 index cd3acded9..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.h +++ /dev/null @@ -1,347 +0,0 @@ -/** - ****************************************************************************** - * @file stm3210b_eval.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains definitions for STM3210B_EVAL's Leds, push-buttons - * COM ports, SD Card (on SPI), sFLASH (on SPI) and Temperature sensor - * LM75 (on I2C) hardware resources. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM3210B_EVAL_H -#define __STM3210B_EVAL_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32_eval.h" -#include "stm32f10x_spi.h" -#include "stm32f10x_i2c.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM3210B_EVAL - * @{ - */ - -/** @addtogroup STM3210B_EVAL_LOW_LEVEL - * @{ - */ - -/** @defgroup STM3210B_EVAL_LOW_LEVEL_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM3210B_EVAL_LOW_LEVEL_Exported_Constants - * @{ - */ -/** @addtogroup STM3210B_EVAL_LOW_LEVEL_LED - * @{ - */ -#define LEDn 4 -#define LED1_PIN GPIO_Pin_6 -#define LED1_GPIO_PORT GPIOC -#define LED1_GPIO_CLK RCC_APB2Periph_GPIOC - -#define LED2_PIN GPIO_Pin_7 -#define LED2_GPIO_PORT GPIOC -#define LED2_GPIO_CLK RCC_APB2Periph_GPIOC - -#define LED3_PIN GPIO_Pin_8 -#define LED3_GPIO_PORT GPIOC -#define LED3_GPIO_CLK RCC_APB2Periph_GPIOC - -#define LED4_PIN GPIO_Pin_9 -#define LED4_GPIO_PORT GPIOC -#define LED4_GPIO_CLK RCC_APB2Periph_GPIOC - -/** - * @} - */ - -/** @addtogroup STM3210B_EVAL_LOW_LEVEL_BUTTON - * @{ - */ -#define BUTTONn 8 - -/** - * @brief Wakeup push-button - */ -#define WAKEUP_BUTTON_PIN GPIO_Pin_0 -#define WAKEUP_BUTTON_GPIO_PORT GPIOA -#define WAKEUP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOA -#define WAKEUP_BUTTON_EXTI_LINE EXTI_Line0 -#define WAKEUP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOA -#define WAKEUP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0 -#define WAKEUP_BUTTON_EXTI_IRQn EXTI0_IRQn -/** - * @brief Tamper push-button - */ -#define TAMPER_BUTTON_PIN GPIO_Pin_13 -#define TAMPER_BUTTON_GPIO_PORT GPIOC -#define TAMPER_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOC -#define TAMPER_BUTTON_EXTI_LINE EXTI_Line13 -#define TAMPER_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOC -#define TAMPER_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13 -#define TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn -/** - * @brief Key push-button - */ -#define KEY_BUTTON_PIN GPIO_Pin_9 -#define KEY_BUTTON_GPIO_PORT GPIOB -#define KEY_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOB -#define KEY_BUTTON_EXTI_LINE EXTI_Line9 -#define KEY_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOB -#define KEY_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource9 -#define KEY_BUTTON_EXTI_IRQn EXTI9_5_IRQn -/** - * @brief Joystick Right push-button - */ -#define RIGHT_BUTTON_PIN GPIO_Pin_0 -#define RIGHT_BUTTON_GPIO_PORT GPIOE -#define RIGHT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOE -#define RIGHT_BUTTON_EXTI_LINE EXTI_Line0 -#define RIGHT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOE -#define RIGHT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0 -#define RIGHT_BUTTON_EXTI_IRQn EXTI0_IRQn -/** - * @brief Joystick Left push-button - */ -#define LEFT_BUTTON_PIN GPIO_Pin_1 -#define LEFT_BUTTON_GPIO_PORT GPIOE -#define LEFT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOE -#define LEFT_BUTTON_EXTI_LINE EXTI_Line1 -#define LEFT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOE -#define LEFT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource1 -#define LEFT_BUTTON_EXTI_IRQn EXTI1_IRQn -/** - * @brief Joystick Up push-button - */ -#define UP_BUTTON_PIN GPIO_Pin_8 -#define UP_BUTTON_GPIO_PORT GPIOD -#define UP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD -#define UP_BUTTON_EXTI_LINE EXTI_Line8 -#define UP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD -#define UP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource8 -#define UP_BUTTON_EXTI_IRQn EXTI9_5_IRQn -/** - * @brief Joystick Down push-button - */ -#define DOWN_BUTTON_PIN GPIO_Pin_14 -#define DOWN_BUTTON_GPIO_PORT GPIOD -#define DOWN_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD -#define DOWN_BUTTON_EXTI_LINE EXTI_Line14 -#define DOWN_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD -#define DOWN_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource14 -#define DOWN_BUTTON_EXTI_IRQn EXTI15_10_IRQn -/** - * @brief Joystick Sel push-button - */ -#define SEL_BUTTON_PIN GPIO_Pin_12 -#define SEL_BUTTON_GPIO_PORT GPIOD -#define SEL_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD -#define SEL_BUTTON_EXTI_LINE EXTI_Line12 -#define SEL_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD -#define SEL_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource12 -#define SEL_BUTTON_EXTI_IRQn EXTI15_10_IRQn -/** - * @} - */ - -/** @addtogroup STM3210B_EVAL_LOW_LEVEL_COM - * @{ - */ -#define COMn 2 - -/** - * @brief Definition for COM port1, connected to USART1 - */ -#define EVAL_COM1 USART1 -#define EVAL_COM1_CLK RCC_APB2Periph_USART1 -#define EVAL_COM1_TX_PIN GPIO_Pin_9 -#define EVAL_COM1_TX_GPIO_PORT GPIOA -#define EVAL_COM1_TX_GPIO_CLK RCC_APB2Periph_GPIOA -#define EVAL_COM1_RX_PIN GPIO_Pin_10 -#define EVAL_COM1_RX_GPIO_PORT GPIOA -#define EVAL_COM1_RX_GPIO_CLK RCC_APB2Periph_GPIOA -#define EVAL_COM1_IRQn USART1_IRQn - -/** - * @brief Definition for COM port2, connected to USART2 (USART2 pins remapped on GPIOD) - */ -#define EVAL_COM2 USART2 -#define EVAL_COM2_CLK RCC_APB1Periph_USART2 -#define EVAL_COM2_TX_PIN GPIO_Pin_5 -#define EVAL_COM2_TX_GPIO_PORT GPIOD -#define EVAL_COM2_TX_GPIO_CLK RCC_APB2Periph_GPIOD -#define EVAL_COM2_RX_PIN GPIO_Pin_6 -#define EVAL_COM2_RX_GPIO_PORT GPIOD -#define EVAL_COM2_RX_GPIO_CLK RCC_APB2Periph_GPIOD -#define EVAL_COM2_IRQn USART2_IRQn - -/** - * @} - */ - -/** @addtogroup STM3210B_EVAL_LOW_LEVEL_SD_SPI - * @{ - */ -/** - * @brief SD SPI Interface pins - */ -#define SD_SPI SPI1 -#define SD_SPI_CLK RCC_APB2Periph_SPI1 -#define SD_SPI_SCK_PIN GPIO_Pin_5 /* PA.05 */ -#define SD_SPI_SCK_GPIO_PORT GPIOA /* GPIOA */ -#define SD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOA -#define SD_SPI_MISO_PIN GPIO_Pin_6 /* PA.06 */ -#define SD_SPI_MISO_GPIO_PORT GPIOA /* GPIOA */ -#define SD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOA -#define SD_SPI_MOSI_PIN GPIO_Pin_7 /* PA.07 */ -#define SD_SPI_MOSI_GPIO_PORT GPIOA /* GPIOA */ -#define SD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOA -#define SD_CS_PIN GPIO_Pin_12 /* PC.12 */ -#define SD_CS_GPIO_PORT GPIOC /* GPIOC */ -#define SD_CS_GPIO_CLK RCC_APB2Periph_GPIOC -#define SD_DETECT_PIN GPIO_Pin_7 /* PE.07 */ -#define SD_DETECT_GPIO_PORT GPIOE /* GPIOE */ -#define SD_DETECT_GPIO_CLK RCC_APB2Periph_GPIOE - -/** - * @} - */ - -/** @addtogroup STM3210B_EVAL_LOW_LEVEL_M25P_FLASH_SPI - * @{ - */ -/** - * @brief M25P FLASH SPI Interface pins - */ -#define sFLASH_SPI SPI1 -#define sFLASH_SPI_CLK RCC_APB2Periph_SPI1 -#define sFLASH_SPI_SCK_PIN GPIO_Pin_5 /* PA.05 */ -#define sFLASH_SPI_SCK_GPIO_PORT GPIOA /* GPIOA */ -#define sFLASH_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOA -#define sFLASH_SPI_MISO_PIN GPIO_Pin_6 /* PA.06 */ -#define sFLASH_SPI_MISO_GPIO_PORT GPIOA /* GPIOA */ -#define sFLASH_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOA -#define sFLASH_SPI_MOSI_PIN GPIO_Pin_7 /* PA.07 */ -#define sFLASH_SPI_MOSI_GPIO_PORT GPIOA /* GPIOA */ -#define sFLASH_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOA -#define sFLASH_CS_PIN GPIO_Pin_4 /* PA.04 */ -#define sFLASH_CS_GPIO_PORT GPIOA /* GPIOA */ -#define sFLASH_CS_GPIO_CLK RCC_APB2Periph_GPIOA - -/** - * @} - */ - -/** @addtogroup STM3210B_EVAL_LOW_LEVEL_TSENSOR_I2C - * @{ - */ -/** - * @brief LM75 Temperature Sensor I2C Interface pins - */ -#define LM75_I2C I2C1 -#define LM75_I2C_CLK RCC_APB1Periph_I2C1 -#define LM75_I2C_SCL_PIN GPIO_Pin_6 /* PB.06 */ -#define LM75_I2C_SCL_GPIO_PORT GPIOB /* GPIOB */ -#define LM75_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB -#define LM75_I2C_SDA_PIN GPIO_Pin_7 /* PB.07 */ -#define LM75_I2C_SDA_GPIO_PORT GPIOB /* GPIOB */ -#define LM75_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB -#define LM75_I2C_SMBUSALERT_PIN GPIO_Pin_5 /* PB.05 */ -#define LM75_I2C_SMBUSALERT_GPIO_PORT GPIOB /* GPIOB */ -#define LM75_I2C_SMBUSALERT_GPIO_CLK RCC_APB2Periph_GPIOB -#define LM75_I2C_DR ((uint32_t)0x40005410) - -#define LM75_DMA_CLK RCC_AHBPeriph_DMA1 -#define LM75_DMA_TX_CHANNEL DMA1_Channel6 -#define LM75_DMA_RX_CHANNEL DMA1_Channel7 -#define LM75_DMA_TX_TCFLAG DMA1_FLAG_TC6 -#define LM75_DMA_RX_TCFLAG DMA1_FLAG_TC7 - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup STM3210B_EVAL_LOW_LEVEL_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup STM3210B_EVAL_LOW_LEVEL_Exported_Functions - * @{ - */ -void STM_EVAL_LEDInit(Led_TypeDef Led); -void STM_EVAL_LEDOn(Led_TypeDef Led); -void STM_EVAL_LEDOff(Led_TypeDef Led); -void STM_EVAL_LEDToggle(Led_TypeDef Led); -void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode); -uint32_t STM_EVAL_PBGetState(Button_TypeDef Button); -void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct); -void SD_LowLevel_DeInit(void); -void SD_LowLevel_Init(void); -void sFLASH_LowLevel_DeInit(void); -void sFLASH_LowLevel_Init(void); -void LM75_LowLevel_DeInit(void); -void LM75_LowLevel_Init(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM3210B_EVAL_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.c deleted file mode 100644 index 2e2e3d658..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.c +++ /dev/null @@ -1,1878 +0,0 @@ -/** - ****************************************************************************** - * @file stm3210b_eval_lcd.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312), - * AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B) - * Liquid Crystal Display Module of STM3210B-EVAL board. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm3210b_eval_lcd.h" -#include "../Common/fonts.c" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM3210B_EVAL - * @{ - */ - -/** @defgroup STM3210B_EVAL_LCD - * @briefThis file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312), - * AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B) - * Liquid Crystal Display Module of STM3210B-EVAL board. - * @{ - */ - -/** @defgroup STM3210B_EVAL_LCD_Private_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM3210B_EVAL_LCD_Private_Defines - * @{ - */ -#define LCD_ILI9320 0x9320 -#define LCD_HX8312 0x8312 -#define LCD_SPFD5408 0x5408 -#define START_BYTE 0x70 -#define SET_INDEX 0x00 -#define READ_STATUS 0x01 -#define LCD_WRITE_REG 0x02 -#define LCD_READ_REG 0x03 -#define MAX_POLY_CORNERS 200 -#define POLY_Y(Z) ((int32_t)((Points + Z)->X)) -#define POLY_X(Z) ((int32_t)((Points + Z)->Y)) -/** - * @} - */ - - -/** @defgroup STM3210B_EVAL_LCD_Private_Macros - * @{ - */ -#define ABS(X) ((X) > 0 ? (X) : -(X)) -/** - * @} - */ - - -/** @defgroup STM3210B_EVAL_LCD_Private_Variables - * @{ - */ -static sFONT *LCD_Currentfonts; -/* Global variables to set the written text color */ -static __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF; -static __IO uint32_t LCDType = LCD_ILI9320; -/** - * @} - */ - - -/** @defgroup STM3210B_EVAL_LCD_Private_Function_Prototypes - * @{ - */ -#ifndef USE_Delay -static void delay(vu32 nCount); -#endif /* USE_Delay*/ - -static void LCD_WriteRegHX8312(uint8_t LCD_Reg, uint8_t LCD_RegValue); -static void LCD_WriteRegILI9320(uint8_t LCD_Reg, uint16_t LCD_RegValue); -static void PutPixel(int16_t x, int16_t y); -static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed); -/** - * @} - */ - - -/** @defgroup STM3210B_EVAL_LCD_Private_Functions - * @{ - */ - -/** - * @brief DeInitializes the LCD. - * @param None - * @retval None - */ -void LCD_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< LCD Display Off */ - LCD_DisplayOff(); - - /*!< LCD_SPI disable */ - SPI_Cmd(LCD_SPI, DISABLE); - - /*!< LCD_SPI DeInit */ - SPI_I2S_DeInit(LCD_SPI); - - /*!< Disable SPI clock */ - RCC_APB1PeriphClockCmd(LCD_SPI_CLK, DISABLE); - - /* Configure NCS in Output Push-Pull mode */ - GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure); - - /* Configure NWR(RNW), RS in Output Push-Pull mode */ - GPIO_InitStructure.GPIO_Pin = LCD_RS_PIN; - GPIO_Init(LCD_RS_GPIO_PORT, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = LCD_NWR_PIN; - GPIO_Init(LCD_NWR_GPIO_PORT, &GPIO_InitStructure); - - /* Configure SPI pins: SCK, MISO and MOSI */ - GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN; - GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN; - GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN; - GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @brief Setups the LCD. - * @param None - * @retval None - */ -void LCD_Setup(void) -{ -/* Configure the LCD Control pins --------------------------------------------*/ - LCD_CtrlLinesConfig(); - -/* Configure the LCD_SPI interface ----------------------------------------------*/ - LCD_SPIConfig(); - if(LCDType == LCD_ILI9320) - { - _delay_(5); /* Delay 50 ms */ - /* Start Initial Sequence ------------------------------------------------*/ - LCD_WriteReg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */ - LCD_WriteReg(LCD_REG_0, 0x0001); /* Start internal OSC. */ - LCD_WriteReg(LCD_REG_1, 0x0100); /* set SS and SM bit */ - LCD_WriteReg(LCD_REG_2, 0x0700); /* set 1 line inversion */ - LCD_WriteReg(LCD_REG_3, 0x1030); /* set GRAM write direction and BGR=1. */ - LCD_WriteReg(LCD_REG_4, 0x0000); /* Resize register */ - LCD_WriteReg(LCD_REG_8, 0x0202); /* set the back porch and front porch */ - LCD_WriteReg(LCD_REG_9, 0x0000); /* set non-display area refresh cycle ISC[3:0] */ - LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */ - LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */ - LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */ - LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */ - /* Power On sequence -----------------------------------------------------*/ - LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ - _delay_(20); /* Dis-charge capacitor power voltage (200ms) */ - LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ - LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ - LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */ - /* Adjust the Gamma Curve ------------------------------------------------*/ - LCD_WriteReg(LCD_REG_48, 0x0006); - LCD_WriteReg(LCD_REG_49, 0x0101); - LCD_WriteReg(LCD_REG_50, 0x0003); - LCD_WriteReg(LCD_REG_53, 0x0106); - LCD_WriteReg(LCD_REG_54, 0x0b02); - LCD_WriteReg(LCD_REG_55, 0x0302); - LCD_WriteReg(LCD_REG_56, 0x0707); - LCD_WriteReg(LCD_REG_57, 0x0007); - LCD_WriteReg(LCD_REG_60, 0x0600); - LCD_WriteReg(LCD_REG_61, 0x020b); - - /* Set GRAM area ---------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ - LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */ - LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ - LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */ - LCD_WriteReg(LCD_REG_96, 0x2700); /* Gate Scan Line */ - LCD_WriteReg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ - LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */ - /* Partial Display Control -----------------------------------------------*/ - LCD_WriteReg(LCD_REG_128, 0x0000); - LCD_WriteReg(LCD_REG_129, 0x0000); - LCD_WriteReg(LCD_REG_130, 0x0000); - LCD_WriteReg(LCD_REG_131, 0x0000); - LCD_WriteReg(LCD_REG_132, 0x0000); - LCD_WriteReg(LCD_REG_133, 0x0000); - /* Panel Control ---------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_144, 0x0010); - LCD_WriteReg(LCD_REG_146, 0x0000); - LCD_WriteReg(LCD_REG_147, 0x0003); - LCD_WriteReg(LCD_REG_149, 0x0110); - LCD_WriteReg(LCD_REG_151, 0x0000); - LCD_WriteReg(LCD_REG_152, 0x0000); - /* Set GRAM write direction and BGR = 1 */ - /* I/D=01 (Horizontal : increment, Vertical : decrement) */ - /* AM=1 (address is updated in vertical writing direction) */ - LCD_WriteReg(LCD_REG_3, 0x1018); - LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */ - } - else if(LCDType == LCD_SPFD5408) - { - /* Start Initial Sequence --------------------------------------------------*/ - LCD_WriteReg(LCD_REG_227, 0x3008); /* Set internal timing */ - LCD_WriteReg(LCD_REG_231, 0x0012); /* Set internal timing */ - LCD_WriteReg(LCD_REG_239, 0x1231); /* Set internal timing */ - LCD_WriteReg(LCD_REG_1, 0x0100); /* Set SS and SM bit */ - LCD_WriteReg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ - LCD_WriteReg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ - LCD_WriteReg(LCD_REG_4, 0x0000); /* Resize register */ - LCD_WriteReg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ - LCD_WriteReg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ - LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */ - LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */ - LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */ - LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */ - /* Power On sequence -------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ - _delay_(20); /* Dis-charge capacitor power voltage (200ms) */ - LCD_WriteReg(LCD_REG_17, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_16, 0x12B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_18, 0x01BD); /* External reference voltage= Vci */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_19, 0x1400); /* VDV[4:0] for VCOM amplitude */ - LCD_WriteReg(LCD_REG_41, 0x000E); /* VCM[4:0] for VCOMH */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ - LCD_WriteReg(LCD_REG_33, 0x013F); /* GRAM Vertical Address */ - /* Adjust the Gamma Curve --------------------------------------------------*/ - LCD_WriteReg(LCD_REG_48, 0x0007); - LCD_WriteReg(LCD_REG_49, 0x0302); - LCD_WriteReg(LCD_REG_50, 0x0105); - LCD_WriteReg(LCD_REG_53, 0x0206); - LCD_WriteReg(LCD_REG_54, 0x0808); - LCD_WriteReg(LCD_REG_55, 0x0206); - LCD_WriteReg(LCD_REG_56, 0x0504); - LCD_WriteReg(LCD_REG_57, 0x0007); - LCD_WriteReg(LCD_REG_60, 0x0105); - LCD_WriteReg(LCD_REG_61, 0x0808); - /* Set GRAM area -----------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ - LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */ - LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ - LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */ - LCD_WriteReg(LCD_REG_96, 0xA700); /* Gate Scan Line */ - LCD_WriteReg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ - LCD_WriteReg(LCD_REG_106, 0x0000); /* Set scrolling line */ - /* Partial Display Control -------------------------------------------------*/ - LCD_WriteReg(LCD_REG_128, 0x0000); - LCD_WriteReg(LCD_REG_129, 0x0000); - LCD_WriteReg(LCD_REG_130, 0x0000); - LCD_WriteReg(LCD_REG_131, 0x0000); - LCD_WriteReg(LCD_REG_132, 0x0000); - LCD_WriteReg(LCD_REG_133, 0x0000); - /* Panel Control -----------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_144, 0x0010); - LCD_WriteReg(LCD_REG_146, 0x0000); - LCD_WriteReg(LCD_REG_147, 0x0003); - LCD_WriteReg(LCD_REG_149, 0x0110); - LCD_WriteReg(LCD_REG_151, 0x0000); - LCD_WriteReg(LCD_REG_152, 0x0000); - /* Set GRAM write direction and BGR = 1 - I/D=01 (Horizontal : increment, Vertical : decrement) - AM=1 (address is updated in vertical writing direction) */ - LCD_WriteReg(LCD_REG_3, 0x1018); - LCD_WriteReg(LCD_REG_7, 0x0112); /* 262K color and display ON */ - } - else if(LCDType == LCD_HX8312) - { - /* Enable the LCD Oscillator ---------------------------------------------*/ - LCD_WriteReg(LCD_REG_1, 0x10); - LCD_WriteReg(LCD_REG_0, 0xA0); - LCD_WriteReg(LCD_REG_3, 0x01); - _delay_(1); /* Delay 10 ms */ - LCD_WriteReg(LCD_REG_3, 0x00); - LCD_WriteReg(LCD_REG_43, 0x04); - - LCD_WriteReg(LCD_REG_40, 0x18); - LCD_WriteReg(LCD_REG_26, 0x05); - LCD_WriteReg(LCD_REG_37, 0x05); - LCD_WriteReg(LCD_REG_25, 0x00); - - /* LCD Power On ----------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_28, 0x73); - LCD_WriteReg(LCD_REG_36, 0x74); - LCD_WriteReg(LCD_REG_30, 0x01); - LCD_WriteReg(LCD_REG_24, 0xC1); - _delay_(1); /* Delay 10 ms */ - LCD_WriteReg(LCD_REG_24, 0xE1); - LCD_WriteReg(LCD_REG_24, 0xF1); - _delay_(6); /* Delay 60 ms */ - LCD_WriteReg(LCD_REG_24, 0xF5); - _delay_(6); /* Delay 60 ms */ - LCD_WriteReg(LCD_REG_27, 0x09); - _delay_(1); /* Delay 10 ms */ - LCD_WriteReg(LCD_REG_31, 0x11); - LCD_WriteReg(LCD_REG_32, 0x0E); - LCD_WriteReg(LCD_REG_30, 0x81); - _delay_(1); /* Delay 10 ms */ - - /* Chip Set --------------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_157, 0x00); - LCD_WriteReg(LCD_REG_192, 0x00); - - LCD_WriteReg(LCD_REG_14, 0x00); - LCD_WriteReg(LCD_REG_15, 0x00); - LCD_WriteReg(LCD_REG_16, 0x00); - LCD_WriteReg(LCD_REG_17, 0x00); - LCD_WriteReg(LCD_REG_18, 0x00); - LCD_WriteReg(LCD_REG_19, 0x00); - LCD_WriteReg(LCD_REG_20, 0x00); - LCD_WriteReg(LCD_REG_21, 0x00); - LCD_WriteReg(LCD_REG_22, 0x00); - LCD_WriteReg(LCD_REG_23, 0x00); - - LCD_WriteReg(LCD_REG_52, 0x01); - LCD_WriteReg(LCD_REG_53, 0x00); - LCD_WriteReg(LCD_REG_75, 0x00); - LCD_WriteReg(LCD_REG_76, 0x00); - LCD_WriteReg(LCD_REG_78, 0x00); - LCD_WriteReg(LCD_REG_79, 0x00); - LCD_WriteReg(LCD_REG_80, 0x00); - - LCD_WriteReg(LCD_REG_60, 0x00); - LCD_WriteReg(LCD_REG_61, 0x00); - LCD_WriteReg(LCD_REG_62, 0x01); - LCD_WriteReg(LCD_REG_63, 0x3F); - LCD_WriteReg(LCD_REG_64, 0x02); - LCD_WriteReg(LCD_REG_65, 0x02); - LCD_WriteReg(LCD_REG_66, 0x00); - LCD_WriteReg(LCD_REG_67, 0x00); - LCD_WriteReg(LCD_REG_68, 0x00); - LCD_WriteReg(LCD_REG_69, 0x00); - LCD_WriteReg(LCD_REG_70, 0xEF); - LCD_WriteReg(LCD_REG_71, 0x00); - LCD_WriteReg(LCD_REG_72, 0x00); - LCD_WriteReg(LCD_REG_73, 0x01); - LCD_WriteReg(LCD_REG_74, 0x3F); - - LCD_WriteReg(LCD_REG_29, 0x08); /* R29:Gate scan direction setting */ - - LCD_WriteReg(LCD_REG_134, 0x00); - LCD_WriteReg(LCD_REG_135, 0x30); - LCD_WriteReg(LCD_REG_136, 0x02); - LCD_WriteReg(LCD_REG_137, 0x05); - - LCD_WriteReg(LCD_REG_141, 0x01); /* R141:Register set-up mode for one line clock */ - LCD_WriteReg(LCD_REG_139, 0x20); /* R139:One line SYSCLK number in one-line */ - LCD_WriteReg(LCD_REG_51, 0x01); /* R51:N line inversion setting */ - LCD_WriteReg(LCD_REG_55, 0x01); /* R55:Scanning method setting */ - LCD_WriteReg(LCD_REG_118, 0x00); - - /* Gamma Set -------------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_143, 0x10); - LCD_WriteReg(LCD_REG_144, 0x67); - LCD_WriteReg(LCD_REG_145, 0x07); - LCD_WriteReg(LCD_REG_146, 0x65); - LCD_WriteReg(LCD_REG_147, 0x07); - LCD_WriteReg(LCD_REG_148, 0x01); - LCD_WriteReg(LCD_REG_149, 0x76); - LCD_WriteReg(LCD_REG_150, 0x56); - LCD_WriteReg(LCD_REG_151, 0x00); - LCD_WriteReg(LCD_REG_152, 0x06); - LCD_WriteReg(LCD_REG_153, 0x03); - LCD_WriteReg(LCD_REG_154, 0x00); - - /* Display On ------------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_1, 0x50); - LCD_WriteReg(LCD_REG_5, 0x04); - LCD_WriteReg(LCD_REG_0, 0x80); - LCD_WriteReg(LCD_REG_59, 0x01); - _delay_(4); /* Delay 40 ms */ - LCD_WriteReg(LCD_REG_0, 0x20); - } -} - - -/** - * @brief Initializes the LCD. - * @param None - * @retval None - */ -void STM3210B_LCD_Init(void) -{ - /* Setups the LCD */ - LCD_Setup(); - /* Try to read new LCD controller ID 0x9320 */ - if (LCD_ReadReg(LCD_REG_0) == LCD_ILI9320) - { - LCDType = LCD_ILI9320; - } - else - { - LCDType = LCD_SPFD5408; - /* Setups the LCD */ - LCD_Setup(); - /* Try to read new LCD controller ID 0x5408 */ - if (LCD_ReadReg(LCD_REG_0) != LCD_SPFD5408) - { - LCDType = LCD_HX8312; - /* Setups the LCD */ - LCD_Setup(); - } - } - LCD_SetFont(&LCD_DEFAULT_FONT); -} - -/** - * @brief Sets the LCD Text and Background colors. - * @param _TextColor: specifies the Text Color. - * @param _BackColor: specifies the Background Color. - * @retval None - */ -void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor) -{ - TextColor = _TextColor; - BackColor = _BackColor; -} - -/** - * @brief Gets the LCD Text and Background colors. - * @param _TextColor: pointer to the variable that will contain the Text - Color. - * @param _BackColor: pointer to the variable that will contain the Background - Color. - * @retval None - */ -void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor) -{ - *_TextColor = TextColor; *_BackColor = BackColor; -} - -/** - * @brief Sets the Text color. - * @param Color: specifies the Text color code RGB(5-6-5). - * @retval None - */ -void LCD_SetTextColor(__IO uint16_t Color) -{ - TextColor = Color; -} - - -/** - * @brief Sets the Background color. - * @param Color: specifies the Background color code RGB(5-6-5). - * @retval None - */ -void LCD_SetBackColor(__IO uint16_t Color) -{ - BackColor = Color; -} - -/** - * @brief Sets the Text Font. - * @param fonts: specifies the font to be used. - * @retval None - */ -void LCD_SetFont(sFONT *fonts) -{ - LCD_Currentfonts = fonts; -} - -/** - * @brief Gets the Text Font. - * @param None. - * @retval the used font. - */ -sFONT *LCD_GetFont(void) -{ - return LCD_Currentfonts; -} - -/** - * @brief Clears the selected line. - * @param Line: the Line to be cleared. - * This parameter can be one of the following values: - * @arg Linex: where x can be 0..n - * @retval None - */ -void LCD_ClearLine(uint8_t Line) -{ - uint16_t refcolumn = LCD_PIXEL_WIDTH - 1; - /* Send the string character by character on lCD */ - while (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width) - { - /* Display one character on LCD */ - LCD_DisplayChar(Line, refcolumn, ' '); - /* Decrement the column position by 16 */ - refcolumn -= LCD_Currentfonts->Width; - } -} - - -/** - * @brief Clears the hole LCD. - * @param Color: the color of the background. - * @retval None - */ -void LCD_Clear(uint16_t Color) -{ - uint32_t index = 0; - - LCD_SetCursor(0x00, 0x013F); - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - } - for(index = 0; index < 76800; index++) - { - LCD_WriteRAM(Color); - } - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); - } -} - - -/** - * @brief Sets the cursor position. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @retval None - */ -void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos) -{ - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteReg(LCD_REG_32, Xpos); - LCD_WriteReg(LCD_REG_33, Ypos); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteReg(LCD_REG_66, Xpos); - LCD_WriteReg(LCD_REG_67, ((Ypos & 0x100)>> 8)); - LCD_WriteReg(LCD_REG_68, (Ypos & 0xFF)); - } -} - - -/** - * @brief Draws a character on LCD. - * @param Xpos: the Line where to display the character shape. - * @param Ypos: start column address. - * @param c: pointer to the character data. - * @retval None - */ -void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c) -{ - uint32_t index = 0, i = 0; - uint8_t Xaddress = 0; - - Xaddress = Xpos; - - LCD_SetCursor(Xaddress, Ypos); - - for(index = 0; index < LCD_Currentfonts->Height; index++) - { - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - } - for(i = 0; i < LCD_Currentfonts->Width; i++) - { - if((((c[index] & ((0x80 << ((LCD_Currentfonts->Width / 12 ) * 8 ) ) >> i)) == 0x00) &&(LCD_Currentfonts->Width <= 12))|| - (((c[index] & (0x1 << i)) == 0x00)&&(LCD_Currentfonts->Width > 12 ))) - - { - LCD_WriteRAM(BackColor); - } - else - { - LCD_WriteRAM(TextColor); - } - } - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); - } - Xaddress++; - LCD_SetCursor(Xaddress, Ypos); - } -} - - -/** - * @brief Displays one character (16dots width, 24dots height). - * @param Line: the Line where to display the character shape . - * This parameter can be one of the following values: - * @arg Linex: where x can be 0..9 - * @param Column: start column address. - * @param Ascii: character ascii code, must be between 0x20 and 0x7E. - * @retval None - */ -void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii) -{ - Ascii -= 32; - LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]); -} - - -/** - * @brief Displays a maximum of 20 char on the LCD. - * @param Line: the Line where to display the character shape . - * This parameter can be one of the following values: - * @arg Linex: where x can be 0..9 - * @param *ptr: pointer to string to display on LCD. - * @retval None - */ -void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr) -{ - uint16_t refcolumn = LCD_PIXEL_WIDTH - 1; - - /* Send the string character by character on lCD */ - while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width)) - { - /* Display one character on LCD */ - LCD_DisplayChar(Line, refcolumn, *ptr); - /* Decrement the column position by 16 */ - refcolumn -= LCD_Currentfonts->Width; - /* Point on the next character */ - ptr++; - } -} - - -/** - * @brief Sets a display window - * @param Xpos: specifies the X buttom left position. - * @param Ypos: specifies the Y buttom left position. - * @param Height: display window height. - * @param Width: display window width. - * @retval None - */ -void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width) -{ - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - /* Horizontal GRAM Start Address */ - if(Xpos >= Height) - { - LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1)); - } - else - { - LCD_WriteReg(LCD_REG_80, 0); - } - /* Horizontal GRAM End Address */ - LCD_WriteReg(LCD_REG_81, Xpos); - /* Vertical GRAM Start Address */ - if(Ypos >= Width) - { - LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1)); - } - else - { - LCD_WriteReg(LCD_REG_82, 0); - } - /* Vertical GRAM End Address */ - LCD_WriteReg(LCD_REG_83, Ypos); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteReg(LCD_REG_1, 0xD0); - LCD_WriteReg(LCD_REG_5, 0x14); - - LCD_WriteReg(LCD_REG_69, (Xpos - Height + 1)); - LCD_WriteReg(LCD_REG_70, Xpos); - - LCD_WriteReg(LCD_REG_71, (((Ypos - Width + 1) & 0x100)>> 8)); - LCD_WriteReg(LCD_REG_72, ((Ypos - Width + 1) & 0xFF)); - LCD_WriteReg(LCD_REG_73, ((Ypos & 0x100)>> 8)); - LCD_WriteReg(LCD_REG_74, (Ypos & 0xFF)); - } - LCD_SetCursor(Xpos, Ypos); -} - - -/** - * @brief Disables LCD Window mode. - * @param None - * @retval None - */ -void LCD_WindowModeDisable(void) -{ - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_SetDisplayWindow(239, 0x13F, 240, 320); - LCD_WriteReg(LCD_REG_3, 0x1018); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteReg(LCD_REG_1, 0x50); - LCD_WriteReg(LCD_REG_5, 0x04); - } - -} - - -/** - * @brief Displays a line. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Length: line length. - * @param Direction: line direction. - * This parameter can be one of the following values: Vertical or Horizontal. - * @retval None - */ -void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction) -{ - uint32_t i = 0; - - LCD_SetCursor(Xpos, Ypos); - if(Direction == LCD_DIR_HORIZONTAL) - { - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - } - for(i = 0; i < Length; i++) - { - LCD_WriteRAM(TextColor); - } - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); - } - } - else - { - for(i = 0; i < Length; i++) - { - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAMWord(TextColor); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteRAM(TextColor); - } - Xpos++; - LCD_SetCursor(Xpos, Ypos); - } - } -} - - -/** - * @brief Displays a rectangle. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Height: display rectangle height. - * @param Width: display rectangle width. - * @retval None - */ -void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width) -{ - LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL); - LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL); - - LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL); - LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL); -} - - -/** - * @brief Displays a circle. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Radius - * @retval None - */ -void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius) -{ - int32_t D;/* Decision Variable */ - uint32_t CurX;/* Current X Value */ - uint32_t CurY;/* Current Y Value */ - - D = 3 - (Radius << 1); - CurX = 0; - CurY = Radius; - - while (CurX <= CurY) - { - LCD_SetCursor(Xpos + CurX, Ypos + CurY); - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAMWord(TextColor); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteRAM(TextColor); - } - LCD_SetCursor(Xpos + CurX, Ypos - CurY); - - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAMWord(TextColor); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteRAM(TextColor); - } - LCD_SetCursor(Xpos - CurX, Ypos + CurY); - - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAMWord(TextColor); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteRAM(TextColor); - } - LCD_SetCursor(Xpos - CurX, Ypos - CurY); - - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAMWord(TextColor); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteRAM(TextColor); - } - LCD_SetCursor(Xpos + CurY, Ypos + CurX); - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAMWord(TextColor); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteRAM(TextColor); - } - LCD_SetCursor(Xpos + CurY, Ypos - CurX); - - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAMWord(TextColor); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteRAM(TextColor); - } - LCD_SetCursor(Xpos - CurY, Ypos + CurX); - - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAMWord(TextColor); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteRAM(TextColor); - } - LCD_SetCursor(Xpos - CurY, Ypos - CurX); - - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAMWord(TextColor); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteRAM(TextColor); - } - if (D < 0) - { - D += (CurX << 2) + 6; - } - else - { - D += ((CurX - CurY) << 2) + 10; - CurY--; - } - CurX++; - } -} - - -/** - * @brief Displays a monocolor picture. - * @param Pict: pointer to the picture array. - * @retval None - */ -void LCD_DrawMonoPict(const uint32_t *Pict) -{ - uint32_t index = 0, i = 0; - LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1)); - - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - } - - for(index = 0; index < 2400; index++) - { - for(i = 0; i < 32; i++) - { - if((Pict[index] & (1 << i)) == 0x00) - { - LCD_WriteRAM(BackColor); - } - else - { - LCD_WriteRAM(TextColor); - } - } - } - - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); - } -} - -#ifdef USE_LCD_DrawBMP -/** - * @brief Displays a bitmap picture loaded in the SPI Flash. - * @param BmpAddress: Bmp picture address in the SPI Flash. - * @retval None - */ -void LCD_DrawBMP(uint32_t BmpAddress) -{ - uint32_t i = 0, size = 0; - /* Read bitmap size */ - sFLASH_ReadBuffer((uint8_t*)&size, BmpAddress + 2, 4); - /* get bitmap data address offset */ - sFLASH_ReadBuffer((uint8_t*)&i, BmpAddress + 10, 4); - - size = (size - i)/2; - sFLASH_StartReadSequence(BmpAddress + i); - /* Disable LCD_SPI */ - SPI_Cmd(LCD_SPI, DISABLE); - /* SPI in 16-bit mode */ - SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_16b); - /* Enable LCD_SPI */ - SPI_Cmd(LCD_SPI, ENABLE); - - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - /* Set GRAM write direction and BGR = 1 */ - /* I/D=00 (Horizontal : decrement, Vertical : decrement) */ - /* AM=1 (address is updated in vertical writing direction) */ - LCD_WriteReg(LCD_REG_3, 0x1008); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - } - - /* Read bitmap data from SPI Flash and send them to LCD */ - for(i = 0; i < size; i++) - { - LCD_WriteRAM(__REV16(sFLASH_SendHalfWord(0xA5A5))); - } - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); - } - - /* Deselect the FLASH: Chip Select high */ - sFLASH_CS_HIGH(); - /* Disable LCD_SPI */ - SPI_Cmd(LCD_SPI, DISABLE); - /* SPI in 8-bit mode */ - SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_8b); - /* Enable LCD_SPI */ - SPI_Cmd(LCD_SPI, ENABLE); - - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - /* Set GRAM write direction and BGR = 1 */ - /* I/D = 01 (Horizontal : increment, Vertical : decrement) */ - /* AM = 1 (address is updated in vertical writing direction) */ - LCD_WriteReg(LCD_REG_3, 0x1018); - } -} -#endif /* USE_LCD_DrawBMP */ - -/** - * @brief Displays a full rectangle. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Height: rectangle height. - * @param Width: rectangle width. - * @retval None - */ -void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height) -{ - LCD_SetTextColor(TextColor); - - LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL); - LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL); - - LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL); - LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL); - - Width -= 2; - Height--; - Ypos--; - - LCD_SetTextColor(BackColor); - - while(Height--) - { - LCD_DrawLine(++Xpos, Ypos, Width, LCD_DIR_HORIZONTAL); - } - - LCD_SetTextColor(TextColor); -} - -/** - * @brief Displays a full circle. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Radius - * @retval None - */ -void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius) -{ - int32_t D; /* Decision Variable */ - uint32_t CurX;/* Current X Value */ - uint32_t CurY;/* Current Y Value */ - - D = 3 - (Radius << 1); - - CurX = 0; - CurY = Radius; - - LCD_SetTextColor(BackColor); - - while (CurX <= CurY) - { - if(CurY > 0) - { - LCD_DrawLine(Xpos - CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL); - LCD_DrawLine(Xpos + CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL); - } - - if(CurX > 0) - { - LCD_DrawLine(Xpos - CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL); - LCD_DrawLine(Xpos + CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL); - } - if (D < 0) - { - D += (CurX << 2) + 6; - } - else - { - D += ((CurX - CurY) << 2) + 10; - CurY--; - } - CurX++; - } - - LCD_SetTextColor(TextColor); - LCD_DrawCircle(Xpos, Ypos, Radius); -} - -/** - * @brief Displays an uni line (between two points). - * @param x1: specifies the point 1 x position. - * @param y1: specifies the point 1 y position. - * @param x2: specifies the point 2 x position. - * @param y2: specifies the point 2 y position. - * @retval None - */ -void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2) -{ - int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0, - yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0, - curpixel = 0; - - deltax = ABS(x2 - x1); /* The difference between the x's */ - deltay = ABS(y2 - y1); /* The difference between the y's */ - x = x1; /* Start x off at the first pixel */ - y = y1; /* Start y off at the first pixel */ - - if (x2 >= x1) /* The x-values are increasing */ - { - xinc1 = 1; - xinc2 = 1; - } - else /* The x-values are decreasing */ - { - xinc1 = -1; - xinc2 = -1; - } - - if (y2 >= y1) /* The y-values are increasing */ - { - yinc1 = 1; - yinc2 = 1; - } - else /* The y-values are decreasing */ - { - yinc1 = -1; - yinc2 = -1; - } - - if (deltax >= deltay) /* There is at least one x-value for every y-value */ - { - xinc1 = 0; /* Don't change the x when numerator >= denominator */ - yinc2 = 0; /* Don't change the y for every iteration */ - den = deltax; - num = deltax / 2; - numadd = deltay; - numpixels = deltax; /* There are more x-values than y-values */ - } - else /* There is at least one y-value for every x-value */ - { - xinc2 = 0; /* Don't change the x for every iteration */ - yinc1 = 0; /* Don't change the y when numerator >= denominator */ - den = deltay; - num = deltay / 2; - numadd = deltax; - numpixels = deltay; /* There are more y-values than x-values */ - } - - for (curpixel = 0; curpixel <= numpixels; curpixel++) - { - PutPixel(x, y); /* Draw the current pixel */ - num += numadd; /* Increase the numerator by the top of the fraction */ - if (num >= den) /* Check if numerator >= denominator */ - { - num -= den; /* Calculate the new numerator value */ - x += xinc1; /* Change the x as appropriate */ - y += yinc1; /* Change the y as appropriate */ - } - x += xinc2; /* Change the x as appropriate */ - y += yinc2; /* Change the y as appropriate */ - } -} - -/** - * @brief Displays an polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_PolyLine(pPoint Points, uint16_t PointCount) -{ - int16_t X = 0, Y = 0; - - if(PointCount < 2) - { - return; - } - - while(--PointCount) - { - X = Points->X; - Y = Points->Y; - Points++; - LCD_DrawUniLine(X, Y, Points->X, Points->Y); - } -} - -/** - * @brief Displays an relative polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @param Closed: specifies if the draw is closed or not. - * 1: closed, 0 : not closed. - * @retval None - */ -static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed) -{ - int16_t X = 0, Y = 0; - pPoint First = Points; - - if(PointCount < 2) - { - return; - } - X = Points->X; - Y = Points->Y; - while(--PointCount) - { - Points++; - LCD_DrawUniLine(X, Y, X + Points->X, Y + Points->Y); - X = X + Points->X; - Y = Y + Points->Y; - } - if(Closed) - { - LCD_DrawUniLine(First->X, First->Y, X, Y); - } -} - -/** - * @brief Displays a closed polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount) -{ - LCD_PolyLine(Points, PointCount); - LCD_DrawUniLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y); -} - -/** - * @brief Displays a relative polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount) -{ - LCD_PolyLineRelativeClosed(Points, PointCount, 0); -} - -/** - * @brief Displays a closed relative polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount) -{ - LCD_PolyLineRelativeClosed(Points, PointCount, 1); -} - - -/** - * @brief Displays a full polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_FillPolyLine(pPoint Points, uint16_t PointCount) -{ - /* public-domain code by Darel Rex Finley, 2007 */ - uint16_t nodes = 0, nodeX[MAX_POLY_CORNERS], pixelX = 0, pixelY = 0, i = 0, - j = 0, swap = 0; - uint16_t IMAGE_LEFT = 0, IMAGE_RIGHT = 0, IMAGE_TOP = 0, IMAGE_BOTTOM = 0; - - IMAGE_LEFT = IMAGE_RIGHT = Points->X; - IMAGE_TOP= IMAGE_BOTTOM = Points->Y; - - for(i = 1; i < PointCount; i++) - { - pixelX = POLY_X(i); - if(pixelX < IMAGE_LEFT) - { - IMAGE_LEFT = pixelX; - } - if(pixelX > IMAGE_RIGHT) - { - IMAGE_RIGHT = pixelX; - } - - pixelY = POLY_Y(i); - if(pixelY < IMAGE_TOP) - { - IMAGE_TOP = pixelY; - } - if(pixelY > IMAGE_BOTTOM) - { - IMAGE_BOTTOM = pixelY; - } - } - - LCD_SetTextColor(BackColor); - - /* Loop through the rows of the image. */ - for (pixelY = IMAGE_TOP; pixelY < IMAGE_BOTTOM; pixelY++) - { - /* Build a list of nodes. */ - nodes = 0; j = PointCount-1; - - for (i = 0; i < PointCount; i++) - { - if (POLY_Y(i)<(double) pixelY && POLY_Y(j)>=(double) pixelY || POLY_Y(j)<(double) pixelY && POLY_Y(i)>=(double) pixelY) - { - nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i))); - } - j = i; - } - - /* Sort the nodes, via a simple "Bubble" sort. */ - i = 0; - while (i < nodes-1) - { - if (nodeX[i]>nodeX[i+1]) - { - swap = nodeX[i]; - nodeX[i] = nodeX[i+1]; - nodeX[i+1] = swap; - if(i) - { - i--; - } - } - else - { - i++; - } - } - - /* Fill the pixels between node pairs. */ - for (i = 0; i < nodes; i+=2) - { - if(nodeX[i] >= IMAGE_RIGHT) - { - break; - } - if(nodeX[i+1] > IMAGE_LEFT) - { - if (nodeX[i] < IMAGE_LEFT) - { - nodeX[i]=IMAGE_LEFT; - } - if(nodeX[i+1] > IMAGE_RIGHT) - { - nodeX[i+1] = IMAGE_RIGHT; - } - LCD_SetTextColor(BackColor); - LCD_DrawLine(pixelY, nodeX[i+1], nodeX[i+1] - nodeX[i], LCD_DIR_HORIZONTAL); - LCD_SetTextColor(TextColor); - PutPixel(pixelY, nodeX[i+1]); - PutPixel(pixelY, nodeX[i]); - /* for (j=nodeX[i]; j>8); - - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET) - { - } - - SPI_I2S_SendData(LCD_SPI, (LCD_RegValue & 0xFF)); - - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET) - { - } - - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); -} - - -/** - * @brief Reads the selected LCD Register. - * @param LCD_Reg: address of the selected register. - * @retval LCD Register Value. - */ -uint16_t LCD_ReadReg(uint8_t LCD_Reg) -{ - uint16_t tmp = 0; - uint8_t i = 0; - - /* LCD_SPI prescaler: 4 */ - LCD_SPI->CR1 &= 0xFFC7; - LCD_SPI->CR1 |= 0x0008; - /* Write 16-bit Index (then Read Reg) */ - LCD_WriteRegIndex(LCD_Reg); - /* Read 16-bit Reg */ - /* Reset LCD control line(/CS) and Send Start-Byte */ - LCD_nCS_StartByte(START_BYTE | LCD_READ_REG); - - for(i = 0; i < 5; i++) - { - SPI_I2S_SendData(LCD_SPI, 0xFF); - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET) - { - } - /* One byte of invalid dummy data read after the start byte */ - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET) - { - } - SPI_I2S_ReceiveData(LCD_SPI); - } - - SPI_I2S_SendData(LCD_SPI, 0xFF); - - /* Read upper byte */ - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET) - { - } - - /* Read lower byte */ - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET) - { - } - tmp = SPI_I2S_ReceiveData(LCD_SPI); - - - SPI_I2S_SendData(LCD_SPI, 0xFF); - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET) - { - } - - /* Read lower byte */ - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET) - { - } - - tmp = ((tmp & 0xFF) << 8) | SPI_I2S_ReceiveData(LCD_SPI); - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); - - /* LCD_SPI prescaler: 2 */ - LCD_SPI->CR1 &= 0xFFC7; - - return tmp; -} - - -/** - * @brief Prepare to write to the LCD RAM. - * @param None - * @retval None - */ -void LCD_WriteRAM_Prepare(void) -{ - LCD_WriteRegIndex(LCD_REG_34); /* Select GRAM Reg */ - - /* Reset LCD control line(/CS) and Send Start-Byte */ - LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG); -} - - -/** - * @brief Writes 1 word to the LCD RAM. - * @param RGB_Code: the pixel color in RGB mode (5-6-5). - * @retval None - */ -void LCD_WriteRAMWord(uint16_t RGB_Code) -{ - - LCD_WriteRAM_Prepare(); - - LCD_WriteRAM(RGB_Code); - - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); -} - - -/** - * @brief Writes to the selected LCD HX8312 register. - * @param LCD_Reg: address of the selected register. - * @param LCD_RegValue: value to write to the selected register. - * @retval None - */ -static void LCD_WriteRegHX8312(uint8_t LCD_Reg, uint8_t LCD_RegValue) -{ - uint16_t tmp = 0; - - LCD_CtrlLinesWrite(LCD_NWR_GPIO_PORT, LCD_NWR_PIN, Bit_RESET); - LCD_CtrlLinesWrite(LCD_RS_GPIO_PORT, LCD_RS_PIN, Bit_RESET); - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET); - - tmp = LCD_Reg << 8; - tmp |= LCD_RegValue; - - SPI_I2S_SendData(LCD_SPI, tmp); - - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET) - { - } - - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); -} - - -/** - * @brief Writes to the selected LCD register. - * @param LCD_Reg: address of the selected register. - * @param LCD_RegValue: value to write to the selected register. - * @retval None - */ -void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue) -{ - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_WriteRegILI9320(LCD_Reg, LCD_RegValue); - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteRegHX8312(LCD_Reg, ((uint8_t)LCD_RegValue)); - } -} - - -/** - * @brief Writes to the LCD RAM. - * @param RGB_Code: the pixel color in RGB mode (5-6-5). - * @retval None - */ -void LCD_WriteRAM(uint16_t RGB_Code) -{ - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - SPI_I2S_SendData(LCD_SPI, RGB_Code >> 8); - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET) - { - } - SPI_I2S_SendData(LCD_SPI, RGB_Code & 0xFF); - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET) - { - } - } - - if(LCDType == LCD_HX8312) - { - LCD_CtrlLinesWrite(LCD_NWR_GPIO_PORT, LCD_NWR_PIN, Bit_RESET); - LCD_CtrlLinesWrite(LCD_RS_GPIO_PORT, LCD_RS_PIN, Bit_SET); - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET); - SPI_I2S_SendData(LCD_SPI, RGB_Code); - - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET) - { - } - - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); - } -} - - -/** - * @brief Power on the LCD. - * @param None - * @retval None - */ -void LCD_PowerOn(void) -{ - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - /* Power On sequence ---------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ - _delay_(20); /* Dis-charge capacitor power voltage (200ms) */ - LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ - _delay_(5); /* delay 50 ms */ - LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ - LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ - _delay_(5); /* delay 50 ms */ - LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */ - } - else if(LCDType == LCD_HX8312) - { - /* Power On Set */ - LCD_WriteReg(LCD_REG_28, 0x73); - LCD_WriteReg(LCD_REG_36, 0x74); - LCD_WriteReg(LCD_REG_30, 0x01); - LCD_WriteReg(LCD_REG_24, 0xC1); - _delay_(1); /* Delay 10 ms */ - LCD_WriteReg(LCD_REG_24, 0xE1); - LCD_WriteReg(LCD_REG_24, 0xF1); - _delay_(6); /* Delay 60 ms */ - LCD_WriteReg(LCD_REG_24, 0xF5); - _delay_(6); /* Delay 60 ms */ - LCD_WriteReg(LCD_REG_27, 0x09); - _delay_(1); /* Delay 10 ms */ - LCD_WriteReg(LCD_REG_31, 0x11); - LCD_WriteReg(LCD_REG_32, 0x0E); - LCD_WriteReg(LCD_REG_30, 0x81); - _delay_(1); /* Delay 10 ms */ - } -} - - -/** - * @brief Enables the Display. - * @param None - * @retval None - */ -void LCD_DisplayOn(void) -{ - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - /* Display On */ - LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */ - } - else if(LCDType == LCD_HX8312) - { - LCD_WriteReg(LCD_REG_1, 0x50); - LCD_WriteReg(LCD_REG_5, 0x04); - /* Display On */ - LCD_WriteReg(LCD_REG_0, 0x80); - LCD_WriteReg(LCD_REG_59, 0x01); - _delay_(4); /* Delay 40 ms */ - LCD_WriteReg(LCD_REG_0, 0x20); - } -} - - -/** - * @brief Disables the Display. - * @param None - * @retval None - */ -void LCD_DisplayOff(void) -{ - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - /* Display Off */ - LCD_WriteReg(LCD_REG_7, 0x0); - } - else if(LCDType == LCD_HX8312) - { - /* Display Off */ - LCD_WriteReg(LCD_REG_0, 0xA0); - _delay_(4); /* Delay 40 ms */ - LCD_WriteReg(LCD_REG_59, 0x00); - } -} - - -/** - * @brief Configures LCD control lines in Output Push-Pull mode. - * @param None - * @retval None - */ -void LCD_CtrlLinesConfig(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable GPIO clock */ - RCC_APB2PeriphClockCmd(LCD_NCS_GPIO_CLK | LCD_NWR_GPIO_CLK | LCD_RS_GPIO_CLK, ENABLE); - - /* Configure NCS in Output Push-Pull mode */ - GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure); - - /* Configure NWR(RNW), RS in Output Push-Pull mode */ - GPIO_InitStructure.GPIO_Pin = LCD_RS_PIN; - GPIO_Init(LCD_RS_GPIO_PORT, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = LCD_NWR_PIN; - GPIO_Init(LCD_NWR_GPIO_PORT, &GPIO_InitStructure); - - LCD_CtrlLinesWrite(LCD_NWR_GPIO_PORT, LCD_NWR_PIN, Bit_SET); - LCD_CtrlLinesWrite(LCD_RS_GPIO_PORT, LCD_RS_PIN, Bit_SET); -} - - -/** - * @brief Sets or reset LCD control lines. - * @param GPIOx: where x can be B or D to select the GPIO peripheral. - * @param CtrlPins: the Control line. - * This parameter can be: - * @arg LCD_NCS_PIN: Chip Select pin - * @arg LCD_NWR_PIN: Read/Write Selection pin - * @arg LCD_RS_PIN: Register/RAM Selection pin - * @param BitVal: specifies the value to be written to the selected bit. - * This parameter can be: - * @arg Bit_RESET: to clear the port pin - * @arg Bit_SET: to set the port pin - * @retval None - */ -void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal) -{ - /* Set or Reset the control line */ - GPIO_WriteBit(GPIOx, CtrlPins, BitVal); -} - -/** - * @brief Configures the LCD_SPI interface. - * @param None - * @retval None - */ -void LCD_SPIConfig(void) -{ - SPI_InitTypeDef SPI_InitStructure; - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable GPIO clock */ - RCC_APB2PeriphClockCmd(LCD_SPI_SCK_GPIO_CLK | LCD_SPI_MISO_GPIO_CLK | LCD_SPI_MOSI_GPIO_CLK, ENABLE); - - /* Enable SPI clock */ - RCC_APB1PeriphClockCmd(LCD_SPI_CLK, ENABLE); - - /* Configure SPI pins: SCK, MISO and MOSI */ - GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN; - GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN; - GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); - - SPI_I2S_DeInit(LCD_SPI); - - /* SPI Config */ - SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; - SPI_InitStructure.SPI_Mode = SPI_Mode_Master; - - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; - SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; - SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; - } - else if(LCDType == LCD_HX8312) - { - SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b; - SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; - SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; - } - SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; - SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; - - SPI_Init(LCD_SPI, &SPI_InitStructure); - - /* SPI enable */ - SPI_Cmd(LCD_SPI, ENABLE); -} - -/** - * @brief Displays a pixel. - * @param x: pixel x. - * @param y: pixel y. - * @retval None - */ -static void PutPixel(int16_t x, int16_t y) -{ - if(x < 0 || x > 239 || y < 0 || y > 319) - { - return; - } - LCD_DrawLine(x, y, 1, LCD_DIR_HORIZONTAL); -} - -#ifndef USE_Delay -/** - * @brief Inserts a delay time. - * @param nCount: specifies the delay time length. - * @retval None - */ -static void delay(vu32 nCount) -{ - vu32 index = 0; - for(index = (100000 * nCount); index != 0; index--) - { - } -} -#endif /* USE_Delay*/ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.h deleted file mode 100644 index 78ba4c52b..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.h +++ /dev/null @@ -1,394 +0,0 @@ -/** - ****************************************************************************** - * @file stm3210b_eval_lcd.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains all the functions prototypes for the stm3210b_eval_lcd - * firmware driver. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM3210B_EVAL_LCD_H -#define __STM3210B_EVAL_LCD_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" -#include "../Common/fonts.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM3210B_EVAL - * @{ - */ - -/** @addtogroup STM3210B_EVAL_LCD - * @{ - */ - - -/** @defgroup STM3210B_EVAL_LCD_Exported_Types - * @{ - */ -typedef struct -{ - int16_t X; - int16_t Y; -} Point, * pPoint; -/** - * @} - */ - - - -/** @defgroup STM3210B_EVAL_LCD_Exported_Constants - * @{ - */ - -/** - * @brief Uncomment the line below if you want to use LCD_DrawBMP function to - * display a bitmap picture on the LCD. This function assumes that the bitmap - * file is loaded in the SPI Flash (mounted on STM3210B-EVAL board), however - * user can tailor it according to his application hardware requirement. - */ -/*#define USE_LCD_DrawBMP*/ - -/** - * @brief Uncomment the line below if you want to use user defined Delay function - * (for precise timing), otherwise default _delay_ function defined within - * this driver is used (less precise timing). - */ -/* #define USE_Delay */ - -#ifdef USE_Delay -#include "main.h" - - #define _delay_ Delay /* !< User can provide more timing precise _delay_ function - (with 10ms time base), using SysTick for example */ -#else - #define _delay_ delay /* !< Default _delay_ function with less precise timing */ -#endif - - -/** - * @brief LCD Control pins - */ -#define LCD_NCS_PIN GPIO_Pin_2 -#define LCD_NCS_GPIO_PORT GPIOB -#define LCD_NCS_GPIO_CLK RCC_APB2Periph_GPIOB -#define LCD_NWR_PIN GPIO_Pin_15 -#define LCD_NWR_GPIO_PORT GPIOD -#define LCD_NWR_GPIO_CLK RCC_APB2Periph_GPIOD -#define LCD_RS_PIN GPIO_Pin_7 -#define LCD_RS_GPIO_PORT GPIOD -#define LCD_RS_GPIO_CLK RCC_APB2Periph_GPIOD - -/** - * @brief LCD SPI Interface pins - */ -#define LCD_SPI SPI2 -#define LCD_SPI_CLK RCC_APB1Periph_SPI2 -#define LCD_SPI_SCK_PIN GPIO_Pin_13 -#define LCD_SPI_SCK_GPIO_PORT GPIOB -#define LCD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOB -#define LCD_SPI_MISO_PIN GPIO_Pin_14 -#define LCD_SPI_MISO_GPIO_PORT GPIOB -#define LCD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOB -#define LCD_SPI_MOSI_PIN GPIO_Pin_15 -#define LCD_SPI_MOSI_GPIO_PORT GPIOB -#define LCD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOB - -/** - * @brief LCD Registers - */ -#define LCD_REG_0 0x00 -#define LCD_REG_1 0x01 -#define LCD_REG_2 0x02 -#define LCD_REG_3 0x03 -#define LCD_REG_4 0x04 -#define LCD_REG_5 0x05 -#define LCD_REG_6 0x06 -#define LCD_REG_7 0x07 -#define LCD_REG_8 0x08 -#define LCD_REG_9 0x09 -#define LCD_REG_10 0x0A -#define LCD_REG_12 0x0C -#define LCD_REG_13 0x0D -#define LCD_REG_14 0x0E -#define LCD_REG_15 0x0F -#define LCD_REG_16 0x10 -#define LCD_REG_17 0x11 -#define LCD_REG_18 0x12 -#define LCD_REG_19 0x13 -#define LCD_REG_20 0x14 -#define LCD_REG_21 0x15 -#define LCD_REG_22 0x16 -#define LCD_REG_23 0x17 -#define LCD_REG_24 0x18 -#define LCD_REG_25 0x19 -#define LCD_REG_26 0x1A -#define LCD_REG_27 0x1B -#define LCD_REG_28 0x1C -#define LCD_REG_29 0x1D -#define LCD_REG_30 0x1E -#define LCD_REG_31 0x1F -#define LCD_REG_32 0x20 -#define LCD_REG_33 0x21 -#define LCD_REG_34 0x22 -#define LCD_REG_36 0x24 -#define LCD_REG_37 0x25 -#define LCD_REG_40 0x28 -#define LCD_REG_41 0x29 -#define LCD_REG_43 0x2B -#define LCD_REG_45 0x2D -#define LCD_REG_48 0x30 -#define LCD_REG_49 0x31 -#define LCD_REG_50 0x32 -#define LCD_REG_51 0x33 -#define LCD_REG_52 0x34 -#define LCD_REG_53 0x35 -#define LCD_REG_54 0x36 -#define LCD_REG_55 0x37 -#define LCD_REG_56 0x38 -#define LCD_REG_57 0x39 -#define LCD_REG_59 0x3B -#define LCD_REG_60 0x3C -#define LCD_REG_61 0x3D -#define LCD_REG_62 0x3E -#define LCD_REG_63 0x3F -#define LCD_REG_64 0x40 -#define LCD_REG_65 0x41 -#define LCD_REG_66 0x42 -#define LCD_REG_67 0x43 -#define LCD_REG_68 0x44 -#define LCD_REG_69 0x45 -#define LCD_REG_70 0x46 -#define LCD_REG_71 0x47 -#define LCD_REG_72 0x48 -#define LCD_REG_73 0x49 -#define LCD_REG_74 0x4A -#define LCD_REG_75 0x4B -#define LCD_REG_76 0x4C -#define LCD_REG_77 0x4D -#define LCD_REG_78 0x4E -#define LCD_REG_79 0x4F -#define LCD_REG_80 0x50 -#define LCD_REG_81 0x51 -#define LCD_REG_82 0x52 -#define LCD_REG_83 0x53 -#define LCD_REG_96 0x60 -#define LCD_REG_97 0x61 -#define LCD_REG_106 0x6A -#define LCD_REG_118 0x76 -#define LCD_REG_128 0x80 -#define LCD_REG_129 0x81 -#define LCD_REG_130 0x82 -#define LCD_REG_131 0x83 -#define LCD_REG_132 0x84 -#define LCD_REG_133 0x85 -#define LCD_REG_134 0x86 -#define LCD_REG_135 0x87 -#define LCD_REG_136 0x88 -#define LCD_REG_137 0x89 -#define LCD_REG_139 0x8B -#define LCD_REG_140 0x8C -#define LCD_REG_141 0x8D -#define LCD_REG_143 0x8F -#define LCD_REG_144 0x90 -#define LCD_REG_145 0x91 -#define LCD_REG_146 0x92 -#define LCD_REG_147 0x93 -#define LCD_REG_148 0x94 -#define LCD_REG_149 0x95 -#define LCD_REG_150 0x96 -#define LCD_REG_151 0x97 -#define LCD_REG_152 0x98 -#define LCD_REG_153 0x99 -#define LCD_REG_154 0x9A -#define LCD_REG_157 0x9D -#define LCD_REG_192 0xC0 -#define LCD_REG_193 0xC1 -#define LCD_REG_227 0xE3 -#define LCD_REG_229 0xE5 -#define LCD_REG_231 0xE7 -#define LCD_REG_239 0xEF - - -/** - * @brief LCD color - */ -#define LCD_COLOR_WHITE 0xFFFF -#define LCD_COLOR_BLACK 0x0000 -#define LCD_COLOR_GREY 0xF7DE -#define LCD_COLOR_BLUE 0x001F -#define LCD_COLOR_BLUE2 0x051F -#define LCD_COLOR_RED 0xF800 -#define LCD_COLOR_MAGENTA 0xF81F -#define LCD_COLOR_GREEN 0x07E0 -#define LCD_COLOR_CYAN 0x7FFF -#define LCD_COLOR_YELLOW 0xFFE0 - -/** - * @brief LCD Lines depending on the chosen fonts. - */ -#define LCD_LINE_0 LINE(0) -#define LCD_LINE_1 LINE(1) -#define LCD_LINE_2 LINE(2) -#define LCD_LINE_3 LINE(3) -#define LCD_LINE_4 LINE(4) -#define LCD_LINE_5 LINE(5) -#define LCD_LINE_6 LINE(6) -#define LCD_LINE_7 LINE(7) -#define LCD_LINE_8 LINE(8) -#define LCD_LINE_9 LINE(9) -#define LCD_LINE_10 LINE(10) -#define LCD_LINE_11 LINE(11) -#define LCD_LINE_12 LINE(12) -#define LCD_LINE_13 LINE(13) -#define LCD_LINE_14 LINE(14) -#define LCD_LINE_15 LINE(15) -#define LCD_LINE_16 LINE(16) -#define LCD_LINE_17 LINE(17) -#define LCD_LINE_18 LINE(18) -#define LCD_LINE_19 LINE(19) -#define LCD_LINE_20 LINE(20) -#define LCD_LINE_21 LINE(21) -#define LCD_LINE_22 LINE(22) -#define LCD_LINE_23 LINE(23) -#define LCD_LINE_24 LINE(24) -#define LCD_LINE_25 LINE(25) -#define LCD_LINE_26 LINE(26) -#define LCD_LINE_27 LINE(27) -#define LCD_LINE_28 LINE(28) -#define LCD_LINE_29 LINE(29) - -/** - * @brief LCD default font - */ -#define LCD_DEFAULT_FONT Font16x24 - -/** - * @brief LCD Direction - */ -#define LCD_DIR_HORIZONTAL 0x0000 -#define LCD_DIR_VERTICAL 0x0001 - -/** - * @brief LCD Size (Width and Height) - */ -#define LCD_PIXEL_WIDTH 0x0140 -#define LCD_PIXEL_HEIGHT 0x00F0 - -/** - * @} - */ - -/** @defgroup STM3210B_EVAL_LCD_Exported_Macros - * @{ - */ -#define ASSEMBLE_RGB(R, G, B) ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3)) -/** - * @} - */ - - - -/** @defgroup STM3210B_EVAL_LCD_Exported_Functions - * @{ - */ -void LCD_DeInit(void); -void LCD_Setup(void); -void STM3210B_LCD_Init(void); -void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor); -void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor); -void LCD_SetTextColor(__IO uint16_t Color); -void LCD_SetBackColor(__IO uint16_t Color); -void LCD_ClearLine(uint8_t Line); -void LCD_Clear(uint16_t Color); -void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos); -void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c); -void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii); -void LCD_SetFont(sFONT *fonts); -sFONT *LCD_GetFont(void); -void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr); -void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width); -void LCD_WindowModeDisable(void); -void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction); -void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width); -void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius); -void LCD_DrawMonoPict(const uint32_t *Pict); -void LCD_DrawBMP(uint32_t BmpAddress); -void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2); -void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height); -void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius); -void LCD_PolyLine(pPoint Points, uint16_t PointCount); -void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount); -void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount); -void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount); -void LCD_FillPolyLine(pPoint Points, uint16_t PointCount); - -void LCD_nCS_StartByte(uint8_t Start_Byte); -void LCD_WriteRegIndex(uint8_t LCD_Reg); -void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue); -void LCD_WriteRAM_Prepare(void); -void LCD_WriteRAMWord(uint16_t RGB_Code); -uint16_t LCD_ReadReg(uint8_t LCD_Reg); -void LCD_WriteRAM(uint16_t RGB_Code); -void LCD_PowerOn(void); -void LCD_DisplayOn(void); -void LCD_DisplayOff(void); - -void LCD_CtrlLinesConfig(void); -void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal); -void LCD_SPIConfig(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM3210B_EVAL_LCD_H */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval.c deleted file mode 100644 index 67d49c234..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval.c +++ /dev/null @@ -1,604 +0,0 @@ -/** - ****************************************************************************** - * @file stm3210c_eval.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file provides - * - set of firmware functions to manage Leds, push-button and COM ports - * - low level initialization functions for SD card (on SPI) and I2C - * serial EEPROM (sEE) - * available on STM3210C-EVAL evaluation board from STMicroelectronics. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm3210c_eval.h" -#include "stm32f10x_spi.h" -#include "stm32f10x_i2c.h" -#include "stm32f10x_dma.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM3210C_EVAL - * @{ - */ - -/** @defgroup STM3210C_EVAL_LOW_LEVEL - * @brief This file provides firmware functions to manage Leds, push-buttons, - * COM ports, SD card on SPI and EEPROM (sEE) available on STM3210C-EVAL - * evaluation board from STMicroelectronics. - * @{ - */ - -/** @defgroup STM3210C_EVAL_LOW_LEVEL_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM3210C_EVAL_LOW_LEVEL_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM3210C_EVAL_LOW_LEVEL_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM3210C_EVAL_LOW_LEVEL_Private_Variables - * @{ - */ -GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT, - LED4_GPIO_PORT}; -const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN, - LED4_PIN}; -const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK, - LED4_GPIO_CLK}; - -GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT, - KEY_BUTTON_GPIO_PORT}; - -const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN, - KEY_BUTTON_PIN}; - -const uint32_t BUTTON_CLK[BUTTONn] = {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK, - KEY_BUTTON_GPIO_CLK}; - -const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {WAKEUP_BUTTON_EXTI_LINE, - TAMPER_BUTTON_EXTI_LINE, - KEY_BUTTON_EXTI_LINE}; - -const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PORT_SOURCE, - TAMPER_BUTTON_EXTI_PORT_SOURCE, - KEY_BUTTON_EXTI_PORT_SOURCE}; - -const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PIN_SOURCE, - TAMPER_BUTTON_EXTI_PIN_SOURCE, - KEY_BUTTON_EXTI_PIN_SOURCE}; - -const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn, - KEY_BUTTON_EXTI_IRQn}; - -USART_TypeDef* COM_USART[COMn] = {EVAL_COM1}; - -GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT}; - -GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT}; - -const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK}; - -const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK}; - -const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK}; - -const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN}; - -const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN}; - -DMA_InitTypeDef sEEDMA_InitStructure; - -/** - * @} - */ - - -/** @defgroup STM3210C_EVAL_LOW_LEVEL_Private_FunctionPrototypes - * @{ - */ -/** - * @} - */ - -/** @defgroup STM3210C_EVAL_LOW_LEVEL_Private_Functions - * @{ - */ - -/** - * @brief Configures LED GPIO. - * @param Led: Specifies the Led to be configured. - * This parameter can be one of following parameters: - * @arg LED1 - * @arg LED2 - * @arg LED3 - * @arg LED4 - * @retval None - */ -void STM_EVAL_LEDInit(Led_TypeDef Led) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable the GPIO_LED Clock */ - RCC_APB2PeriphClockCmd(GPIO_CLK[Led], ENABLE); - - /* Configure the GPIO_LED pin */ - GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led]; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - - GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure); -} - -/** - * @brief Turns selected LED On. - * @param Led: Specifies the Led to be set on. - * This parameter can be one of following parameters: - * @arg LED1 - * @arg LED2 - * @arg LED3 - * @arg LED4 - * @retval None - */ -void STM_EVAL_LEDOn(Led_TypeDef Led) -{ - GPIO_PORT[Led]->BSRR = GPIO_PIN[Led]; -} - -/** - * @brief Turns selected LED Off. - * @param Led: Specifies the Led to be set off. - * This parameter can be one of following parameters: - * @arg LED1 - * @arg LED2 - * @arg LED3 - * @arg LED4 - * @retval None - */ -void STM_EVAL_LEDOff(Led_TypeDef Led) -{ - GPIO_PORT[Led]->BRR = GPIO_PIN[Led]; -} - -/** - * @brief Toggles the selected LED. - * @param Led: Specifies the Led to be toggled. - * This parameter can be one of following parameters: - * @arg LED1 - * @arg LED2 - * @arg LED3 - * @arg LED4 - * @retval None - */ -void STM_EVAL_LEDToggle(Led_TypeDef Led) -{ - GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led]; -} - -/** - * @brief Configures Button GPIO and EXTI Line. - * @param Button: Specifies the Button to be configured. - * This parameter can be one of following parameters: - * @arg BUTTON_WAKEUP: Wakeup Push Button - * @arg BUTTON_TAMPER: Tamper Push Button - * @arg BUTTON_KEY: Key Push Button - * @arg BUTTON_RIGHT: Joystick Right Push Button - * @arg BUTTON_LEFT: Joystick Left Push Button - * @arg BUTTON_UP: Joystick Up Push Button - * @arg BUTTON_DOWN: Joystick Down Push Button - * @arg BUTTON_SEL: Joystick Sel Push Button - * @param Button_Mode: Specifies Button mode. - * This parameter can be one of following parameters: - * @arg BUTTON_MODE_GPIO: Button will be used as simple IO - * @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt - * generation capability - * @retval None - */ -void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode) -{ - GPIO_InitTypeDef GPIO_InitStructure; - EXTI_InitTypeDef EXTI_InitStructure; - NVIC_InitTypeDef NVIC_InitStructure; - - /* Enable the BUTTON Clock */ - RCC_APB2PeriphClockCmd(BUTTON_CLK[Button] | RCC_APB2Periph_AFIO, ENABLE); - - /* Configure Button pin as input floating */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button]; - GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure); - - - if (Button_Mode == BUTTON_MODE_EXTI) - { - /* Connect Button EXTI Line to Button GPIO Pin */ - GPIO_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]); - - /* Configure Button EXTI line */ - EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button]; - EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; - - if(Button != BUTTON_WAKEUP) - { - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; - } - else - { - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; - } - EXTI_InitStructure.EXTI_LineCmd = ENABLE; - EXTI_Init(&EXTI_InitStructure); - - /* Enable and set Button EXTI Interrupt to the lowest priority */ - NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button]; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - - NVIC_Init(&NVIC_InitStructure); - } -} - -/** - * @brief Returns the selected Button state. - * @param Button: Specifies the Button to be checked. - * This parameter can be one of following parameters: - * @arg BUTTON_WAKEUP: Wakeup Push Button - * @arg BUTTON_TAMPER: Tamper Push Button - * @arg BUTTON_KEY: Key Push Button - * @arg BUTTON_RIGHT: Joystick Right Push Button - * @arg BUTTON_LEFT: Joystick Left Push Button - * @arg BUTTON_UP: Joystick Up Push Button - * @arg BUTTON_DOWN: Joystick Down Push Button - * @arg BUTTON_SEL: Joystick Sel Push Button - * @retval The Button GPIO pin value. - */ -uint32_t STM_EVAL_PBGetState(Button_TypeDef Button) -{ - return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]); -} - - -/** - * @brief Configures COM port. - * @param COM: Specifies the COM port to be configured. - * This parameter can be one of following parameters: - * @arg COM1 - * @arg COM2 - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that - * contains the configuration information for the specified USART peripheral. - * @retval None - */ -void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable GPIO clock */ - RCC_APB2PeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM] | RCC_APB2Periph_AFIO, ENABLE); - - if (COM == COM1) - { - /* Enable the USART2 Pins Software Remapping */ - GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE); - RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE); - } - - /* Configure USART Tx as alternate function push-pull */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM]; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure); - - /* Configure USART Rx as input floating */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM]; - GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure); - - /* USART configuration */ - USART_Init(COM_USART[COM], USART_InitStruct); - - /* Enable USART */ - USART_Cmd(COM_USART[COM], ENABLE); -} - -/** - * @brief DeInitializes the SD/SD communication. - * @param None - * @retval None - */ -void SD_LowLevel_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - SPI_Cmd(SD_SPI, DISABLE); /*!< SD_SPI disable */ - SPI_I2S_DeInit(SD_SPI); /*!< DeInitializes the SD_SPI */ - - /*!< SD_SPI Periph clock disable */ - RCC_APB1PeriphClockCmd(SD_SPI_CLK, DISABLE); - /*!< DeRemap SPI3 Pins */ - GPIO_PinRemapConfig(GPIO_Remap_SPI3, DISABLE); - - /*!< Configure SD_SPI pins: SCK */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI pins: MISO */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN; - GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI pins: MOSI */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN; - GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */ - GPIO_InitStructure.GPIO_Pin = SD_CS_PIN; - GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */ - GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN; - GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @brief Initializes the SD_SPI and CS pins. - * @param None - * @retval None - */ -void SD_LowLevel_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - SPI_InitTypeDef SPI_InitStructure; - - /*!< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO - and SD_SPI_SCK_GPIO Periph clock enable */ - RCC_APB2PeriphClockCmd(SD_CS_GPIO_CLK | SD_SPI_MOSI_GPIO_CLK | SD_SPI_MISO_GPIO_CLK | - SD_SPI_SCK_GPIO_CLK | SD_DETECT_GPIO_CLK, ENABLE); - - /*!< SD_SPI Periph clock enable */ - RCC_APB1PeriphClockCmd(SD_SPI_CLK, ENABLE); - /*!< AFIO Periph clock enable */ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); - /*!< Remap SPI3 Pins */ - GPIO_PinRemapConfig(GPIO_Remap_SPI3,ENABLE); - - /*!< Configure SD_SPI pins: SCK */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI pins: MOSI */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN; - GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI pins: MISO */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */ - GPIO_InitStructure.GPIO_Pin = SD_CS_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */ - GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure); - - /*!< SD_SPI Config */ - SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; - SPI_InitStructure.SPI_Mode = SPI_Mode_Master; - SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; - SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; - SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; - SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; - SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; - SPI_InitStructure.SPI_CRCPolynomial = 7; - SPI_Init(SD_SPI, &SPI_InitStructure); - - SPI_Cmd(SD_SPI, ENABLE); /*!< SD_SPI enable */ -} - -/** - * @brief DeInitializes peripherals used by the I2C EEPROM driver. - * @param None - * @retval None - */ -void sEE_LowLevel_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - NVIC_InitTypeDef NVIC_InitStructure; - - /* sEE_I2C Peripheral Disable */ - I2C_Cmd(sEE_I2C, DISABLE); - - /* sEE_I2C DeInit */ - I2C_DeInit(sEE_I2C); - - /*!< sEE_I2C Periph clock disable */ - RCC_APB1PeriphClockCmd(sEE_I2C_CLK, DISABLE); - - /*!< GPIO configuration */ - /*!< Configure sEE_I2C pins: SCL */ - GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sEE_I2C pins: SDA */ - GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN; - GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); - - /* Configure and enable I2C DMA TX Channel interrupt */ - NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO; - NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE; - NVIC_Init(&NVIC_InitStructure); - - /* Configure and enable I2C DMA RX Channel interrupt */ - NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO; - NVIC_Init(&NVIC_InitStructure); - - /* Disable and Deinitialize the DMA channels */ - DMA_Cmd(sEE_I2C_DMA_CHANNEL_TX, DISABLE); - DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, DISABLE); - DMA_DeInit(sEE_I2C_DMA_CHANNEL_TX); - DMA_DeInit(sEE_I2C_DMA_CHANNEL_RX); -} - -/** - * @brief Initializes peripherals used by the I2C EEPROM driver. - * @param None - * @retval None - */ -void sEE_LowLevel_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - NVIC_InitTypeDef NVIC_InitStructure; - - /*!< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable */ - RCC_APB2PeriphClockCmd(sEE_I2C_SCL_GPIO_CLK | sEE_I2C_SDA_GPIO_CLK, ENABLE); - - /*!< sEE_I2C Periph clock enable */ - RCC_APB1PeriphClockCmd(sEE_I2C_CLK, ENABLE); - - /*!< GPIO configuration */ - /*!< Configure sEE_I2C pins: SCL */ - GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD; - GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sEE_I2C pins: SDA */ - GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN; - GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); - - /* Configure and enable I2C DMA TX Channel interrupt */ - NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); - - /* Configure and enable I2C DMA RX Channel interrupt */ - NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO; - NVIC_Init(&NVIC_InitStructure); - - /*!< I2C DMA TX and RX channels configuration */ - /* Enable the DMA clock */ - RCC_AHBPeriphClockCmd(sEE_I2C_DMA_CLK, ENABLE); - - /* I2C TX DMA Channel configuration */ - DMA_DeInit(sEE_I2C_DMA_CHANNEL_TX); - sEEDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)sEE_I2C_DR_Address; - sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)0; /* This parameter will be configured durig communication */ - sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST; /* This parameter will be configured durig communication */ - sEEDMA_InitStructure.DMA_BufferSize = 0xFFFF; /* This parameter will be configured durig communication */ - sEEDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - sEEDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - sEEDMA_InitStructure.DMA_PeripheralDataSize = DMA_MemoryDataSize_Byte; - sEEDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - sEEDMA_InitStructure.DMA_Mode = DMA_Mode_Normal; - sEEDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; - sEEDMA_InitStructure.DMA_M2M = DMA_M2M_Disable; - DMA_Init(sEE_I2C_DMA_CHANNEL_TX, &sEEDMA_InitStructure); - - /* I2C RX DMA Channel configuration */ - DMA_DeInit(sEE_I2C_DMA_CHANNEL_RX); - DMA_Init(sEE_I2C_DMA_CHANNEL_RX, &sEEDMA_InitStructure); - - /* Enable the DMA Channels Interrupts */ - DMA_ITConfig(sEE_I2C_DMA_CHANNEL_TX, DMA_IT_TC, ENABLE); - DMA_ITConfig(sEE_I2C_DMA_CHANNEL_RX, DMA_IT_TC, ENABLE); -} - - -/** - * @brief Initializes DMA channel used by the I2C EEPROM driver. - * @param None - * @retval None - */ -void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction) -{ - /* Initialize the DMA with the new parameters */ - if (Direction == sEE_DIRECTION_TX) - { - /* Configure the DMA Tx Channel with the buffer address and the buffer size */ - sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)pBuffer; - sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST; - sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize; - DMA_Init(sEE_I2C_DMA_CHANNEL_TX, &sEEDMA_InitStructure); - } - else - { - /* Configure the DMA Rx Channel with the buffer address and the buffer size */ - sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)pBuffer; - sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; - sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize; - DMA_Init(sEE_I2C_DMA_CHANNEL_RX, &sEEDMA_InitStructure); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval.h deleted file mode 100644 index bc51d07c3..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval.h +++ /dev/null @@ -1,277 +0,0 @@ -/** - ****************************************************************************** - * @file stm3210c_eval.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains definitions for STM3210C_EVAL's Leds, push-buttons - * COM ports, SD Card on SPI and sEE on I2C hardware resources. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 210 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM3210C_EVAL_H -#define __STM3210C_EVAL_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32_eval.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM3210C_EVAL - * @{ - */ - -/** @addtogroup STM3210C_EVAL_LOW_LEVEL - * @{ - */ - -/** @defgroup STM3210C_EVAL_LOW_LEVEL_Exported_Types - * @{ - */ -/** - * @} - */ - -/** @defgroup STM3210C_EVAL_LOW_LEVEL_Exported_Constants - * @{ - */ - -/** @addtogroup STM3210C_EVAL_LOW_LEVEL_LED - * @{ - */ -#define LEDn 4 - -#define LED1_PIN GPIO_Pin_7 -#define LED1_GPIO_PORT GPIOD -#define LED1_GPIO_CLK RCC_APB2Periph_GPIOD - -#define LED2_PIN GPIO_Pin_13 -#define LED2_GPIO_PORT GPIOD -#define LED2_GPIO_CLK RCC_APB2Periph_GPIOD - -#define LED3_PIN GPIO_Pin_3 -#define LED3_GPIO_PORT GPIOD -#define LED3_GPIO_CLK RCC_APB2Periph_GPIOD - -#define LED4_PIN GPIO_Pin_4 -#define LED4_GPIO_PORT GPIOD -#define LED4_GPIO_CLK RCC_APB2Periph_GPIOD - - -/** - * @} - */ - -/** @addtogroup STM3210C_EVAL_LOW_LEVEL_BUTTON - * @{ - */ -#define BUTTONn 3 /*!< Joystick pins are connected to - an IO Expander (accessible through - I2C1 interface) */ - -/** - * @brief Wakeup push-button - */ -#define WAKEUP_BUTTON_PIN GPIO_Pin_0 -#define WAKEUP_BUTTON_GPIO_PORT GPIOA -#define WAKEUP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOA -#define WAKEUP_BUTTON_EXTI_LINE EXTI_Line0 -#define WAKEUP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOA -#define WAKEUP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0 -#define WAKEUP_BUTTON_EXTI_IRQn EXTI0_IRQn - -/** - * @brief Tamper push-button - */ -#define TAMPER_BUTTON_PIN GPIO_Pin_13 -#define TAMPER_BUTTON_GPIO_PORT GPIOC -#define TAMPER_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOC -#define TAMPER_BUTTON_EXTI_LINE EXTI_Line13 -#define TAMPER_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOC -#define TAMPER_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13 -#define TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn - -/** - * @brief Key push-button - */ -#define KEY_BUTTON_PIN GPIO_Pin_9 -#define KEY_BUTTON_GPIO_PORT GPIOB -#define KEY_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOB -#define KEY_BUTTON_EXTI_LINE EXTI_Line9 -#define KEY_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOB -#define KEY_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource9 -#define KEY_BUTTON_EXTI_IRQn EXTI9_5_IRQn -/** - * @} - */ - -/** @addtogroup STM3210C_EVAL_LOW_LEVEL_COM - * @{ - */ -#define COMn 1 - -/** - * @brief Definition for COM port1, connected to USART2 (USART2 pins remapped on GPIOD) - */ -#define EVAL_COM1 USART2 -#define EVAL_COM1_CLK RCC_APB1Periph_USART2 -#define EVAL_COM1_TX_PIN GPIO_Pin_5 -#define EVAL_COM1_TX_GPIO_PORT GPIOD -#define EVAL_COM1_TX_GPIO_CLK RCC_APB2Periph_GPIOD -#define EVAL_COM1_RX_PIN GPIO_Pin_6 -#define EVAL_COM1_RX_GPIO_PORT GPIOD -#define EVAL_COM1_RX_GPIO_CLK RCC_APB2Periph_GPIOD -#define EVAL_COM1_IRQn USART2_IRQn - -/** - * @} - */ - -/** @addtogroup STM3210B_EVAL_SD_SPI - * @{ - */ -/** - * @brief SD SPI Interface pins - */ -#define SD_SPI SPI3 -#define SD_SPI_CLK RCC_APB1Periph_SPI3 -#define SD_SPI_SCK_PIN GPIO_Pin_10 /* PC.10 */ -#define SD_SPI_SCK_GPIO_PORT GPIOC /* GPIOC */ -#define SD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOC -#define SD_SPI_MISO_PIN GPIO_Pin_11 /* PC.11 */ -#define SD_SPI_MISO_GPIO_PORT GPIOC /* GPIOC */ -#define SD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOC -#define SD_SPI_MOSI_PIN GPIO_Pin_12 /* PC.12 */ -#define SD_SPI_MOSI_GPIO_PORT GPIOC /* GPIOC */ -#define SD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOC -#define SD_CS_PIN GPIO_Pin_4 /* PA.04 */ -#define SD_CS_GPIO_PORT GPIOA /* GPIOA */ -#define SD_CS_GPIO_CLK RCC_APB2Periph_GPIOA -#define SD_DETECT_PIN GPIO_Pin_0 /* PE.00 */ -#define SD_DETECT_GPIO_PORT GPIOE /* GPIOE */ -#define SD_DETECT_GPIO_CLK RCC_APB2Periph_GPIOE - -/** - * @} - */ - -/** @addtogroup STM3210C_EVAL_LOW_LEVEL_I2C_EE - * @{ - */ -/** - * @brief I2C EEPROM Interface pins - */ -#define sEE_I2C I2C1 -#define sEE_I2C_CLK RCC_APB1Periph_I2C1 -#define sEE_I2C_SCL_PIN GPIO_Pin_6 /* PB.06 */ -#define sEE_I2C_SCL_GPIO_PORT GPIOB /* GPIOB */ -#define sEE_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB -#define sEE_I2C_SDA_PIN GPIO_Pin_7 /* PB.07 */ -#define sEE_I2C_SDA_GPIO_PORT GPIOB /* GPIOB */ -#define sEE_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB -#define sEE_M24C64_32 - -#define sEE_I2C_DMA DMA1 -#define sEE_I2C_DMA_CHANNEL_TX DMA1_Channel6 -#define sEE_I2C_DMA_CHANNEL_RX DMA1_Channel7 -#define sEE_I2C_DMA_FLAG_TX_TC DMA1_IT_TC6 -#define sEE_I2C_DMA_FLAG_TX_GL DMA1_IT_GL6 -#define sEE_I2C_DMA_FLAG_RX_TC DMA1_IT_TC7 -#define sEE_I2C_DMA_FLAG_RX_GL DMA1_IT_GL7 -#define sEE_I2C_DMA_CLK RCC_AHBPeriph_DMA1 -#define sEE_I2C_DR_Address ((uint32_t)0x40005410) -#define sEE_USE_DMA - -#define sEE_I2C_DMA_TX_IRQn DMA1_Channel6_IRQn -#define sEE_I2C_DMA_RX_IRQn DMA1_Channel7_IRQn -#define sEE_I2C_DMA_TX_IRQHandler DMA1_Channel6_IRQHandler -#define sEE_I2C_DMA_RX_IRQHandler DMA1_Channel7_IRQHandler -#define sEE_I2C_DMA_PREPRIO 0 -#define sEE_I2C_DMA_SUBPRIO 0 - -#define sEE_DIRECTION_TX 0 -#define sEE_DIRECTION_RX 1 - -/* Time constant for the delay caclulation allowing to have a millisecond - incrementing counter. This value should be equal to (System Clock / 1000). - ie. if system clock = 72MHz then sEE_TIME_CONST should be 72. */ -#define sEE_TIME_CONST 72 - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup STM3210C_EVAL_LOW_LEVEL_Exported_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM3210C_EVAL_LOW_LEVEL_Exported_Functions - * @{ - */ -void STM_EVAL_LEDInit(Led_TypeDef Led); -void STM_EVAL_LEDOn(Led_TypeDef Led); -void STM_EVAL_LEDOff(Led_TypeDef Led); -void STM_EVAL_LEDToggle(Led_TypeDef Led); -void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode); -uint32_t STM_EVAL_PBGetState(Button_TypeDef Button); -void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct); -void SD_LowLevel_DeInit(void); -void SD_LowLevel_Init(void); -void sEE_LowLevel_DeInit(void); -void sEE_LowLevel_Init(void); -void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM3210C_EVAL_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_ioe.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_ioe.c deleted file mode 100644 index 5873564ce..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_ioe.c +++ /dev/null @@ -1,1594 +0,0 @@ -/** - ****************************************************************************** - * @file stm3210c_eval_ioe.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file includes the IO Expander driver for STMPE811 IO Expander - * devices. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - - /* File Info : --------------------------------------------------------------- - - Note: - ----- - - This driver uses the DMA method for sending and receiving data on I2C bus - which allow higher efficiency and reliability of the communication. - - SUPPORTED FEATURES: - - IO Read/write : Set/Reset and Read (Polling/Interrupt) - - Joystick: config and Read (Polling/Interrupt) - - Touch Screen Features: Single point mode (Polling/Interrupt) - - TempSensor Feature: accuracy not determined (Polling). - - UNSUPPORTED FEATURES: - - Row ADC Feature is not supported (not implemented on STM3210C-EVAL board) - ----------------------------------------------------------------------------*/ - -/* Includes ------------------------------------------------------------------*/ -#include "stm3210c_eval_ioe.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM3210C_EVAL - * @{ - */ - -/** @defgroup STM3210C_EVAL_IOE - * @brief This file includes the IO Expander driver for STMPE811 IO Expander - * devices. - * @{ - */ - -/** @defgroup STM3210C_EVAL_IOE_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM3210C_EVAL_IOE_Private_Defines - * @{ - */ -#define TIMEOUT_MAX 0x1000 /* 0; count--); - - if(TS_State.TouchDetected) - { - x = IOE_TS_Read_X(); - y = IOE_TS_Read_Y(); - xDiff = x > _x? (x - _x): (_x - x); - yDiff = y > _y? (y - _y): (_y - y); - if (xDiff + yDiff > 5) - { - _x = x; - _y = y; - } - } - /* Update the X position */ - TS_State.X = _x; - - /* Update the Y position */ - TS_State.Y = _y; - - /* Update the Z Pression index */ - TS_State.Z = IOE_TS_Read_Z(); - - /* Clear the interrupt pending bit and enable the FIFO again */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x01); - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x00); - - /* Return pointer to the updated structure */ - return &TS_State; -} - -/** - * @brief Returns the temperature row value (in 16 bit format). - * @param None - * @retval The temperature row value. - */ -uint32_t IOE_TempSens_GetData(void) -{ - static __IO uint32_t tmp = 0; - - /* Aquire data enable */ - I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_TEMP_CTRL, 0x03); - - /* Enable the TEMPSENS module */ - tmp = (uint32_t)((I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_TEMP_DATA) & 0x03) << 8); - tmp |= (uint32_t)I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_TEMP_DATA + 1); - - tmp = (uint32_t)((33 * tmp * 100) / 751); - tmp = (uint32_t)((tmp + 5) / 10); - - /* return the temprature row value */ - return tmp; -} - -/** - * @brief Checks the selected Global interrupt source pending bit - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR - * or IOE_2_ADDR. - * @param Global_IT: the Global interrupt source to be checked, could be: - * @arg Global_IT_GPIO : All IOs interrupt - * @arg Global_IT_ADC : ADC interrupt - * @arg Global_IT_TEMP : Temperature Sensor interrupts - * @arg Global_IT_FE : Touch Screen Controller FIFO Error interrupt - * @arg Global_IT_FF : Touch Screen Controller FIFO Full interrupt - * @arg Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt - * @arg Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt - * @arg Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt - * @retval Status of the checked flag. Could be SET or RESET. - */ -FlagStatus IOE_GetGITStatus(uint8_t DeviceAddr, uint8_t Global_IT) -{ - __IO uint8_t tmp = 0; - - /* get the Interrupt status */ - tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_STA); - - if ((tmp & (uint8_t)Global_IT) != 0) - { - return SET; - } - else - { - return RESET; - } -} - -/** - * @brief Clears the selected Global interrupt pending bit(s) - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR - * or IOE_2_ADDR. - * @param Global_IT: the Global interrupt to be cleared, could be any combination - * of the following values: - * @arg Global_IT_GPIO : All IOs interrupt - * @arg Global_IT_ADC : ADC interrupt - * @arg Global_IT_TEMP : Temperature Sensor interrupts - * @arg Global_IT_FE : Touch Screen Controller FIFO Error interrupt - * @arg Global_IT_FF : Touch Screen Controller FIFO Full interrupt - * @arg Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt - * @arg Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt - * @arg Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt - * @retval IOE_OK: if all initializations are OK. Other value if error. - */ -uint8_t IOE_ClearGITPending(uint8_t DeviceAddr, uint8_t Global_IT) -{ - /* Write 1 to the bits that have to be cleared */ - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_STA, Global_IT); - - /* If all OK return IOE_OK */ - return IOE_OK; -} - -/** - * @brief Checks the status of the selected IO interrupt pending bit - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR - * or IOE_2_ADDR. - * @param IO_IT: the IO interrupt to be checked could be IO_ITx Where x can be - * from 0 to 7. - * @retval Status of the checked flag. Could be SET or RESET. - */ -FlagStatus IOE_GetIOITStatus(uint8_t DeviceAddr, uint8_t IO_IT) -{ - uint8_t tmp = 0; - - /* get the Interrupt status */ - tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_STA); - - if ((tmp & (uint8_t)IO_IT) != 0) - { - return SET; - } - else - { - return RESET; - } -} - -/** - * @brief Clears the selected IO interrupt pending bit(s). - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR - * or IOE_2_ADDR. - * @param IO_IT: the IO interrupt to be checked could be IO_ITx Where x can be - * from 0 to 7. - * @retval IOE_OK: if all initializations are OK. Other value if error. - */ -uint8_t IOE_ClearIOITPending(uint8_t DeviceAddr, uint8_t IO_IT) -{ - /* Write 1 to the bits that have to be cleared */ - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_STA, IO_IT); - - /* Clear the Edge detection pending bit*/ - I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_GPIO_ED, IO_IT); - - /* Clear the Rising edge pending bit */ - I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_GPIO_RE, IO_IT); - - /* Clear the Falling edge pending bit */ - I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_GPIO_FE, IO_IT); - - /* If all OK return IOE_OK */ - return IOE_OK; -} - -/** - * @brief Checks if the selected device is correctly configured and - * communicates correctly ont the I2C bus. - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR - * or IOE_2_ADDR. - * @retval IOE_OK if IOE is operational. Other value if failure. - */ -uint8_t IOE_IsOperational(uint8_t DeviceAddr) -{ - /* Return Error if the ID is not correct */ - if( IOE_ReadID(DeviceAddr) != (uint16_t)STMPE811_ID ) - { - /* Check if a Timeout occured */ - if (IOE_TimeOut == 0) - { - return (IOE_TimeoutUserCallback()); - } - else - { - return IOE_FAILURE; /* ID is not Correct */ - } - } - else - { - return IOE_OK; /* ID is correct */ - } -} - -/** - * @brief Resets the IO Expander by Software (SYS_CTRL1, RESET bit). - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR - * or IOE_2_ADDR. - * @retval IOE_OK: if all initializations are OK. Other value if error. - */ -uint8_t IOE_Reset(uint8_t DeviceAddr) -{ - /* Power Down the IO_Expander */ - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL1, 0x02); - - /* wait for a delay to insure registers erasing */ - _delay_(2); - - /* Power On the Codec after the power off => all registers are reinitialized*/ - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL1, 0x00); - - /* If all OK return IOE_OK */ - return IOE_OK; -} - -/** - * @brief Reads the selected device's ID. - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR - * or IOE_2_ADDR. - * @retval The Device ID (two bytes). - */ -uint16_t IOE_ReadID(uint8_t DeviceAddr) -{ - uint16_t tmp = 0; - - /* Read device ID */ - tmp = I2C_ReadDeviceRegister(DeviceAddr, 0); - tmp = (uint32_t)(tmp << 8); - tmp |= (uint32_t)I2C_ReadDeviceRegister(DeviceAddr, 1); - - /* Return the ID */ - return (uint16_t)tmp; -} - -/** - * @brief Configures the selcted IO Expander functionalities. - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR - * or IOE_2_ADDR. - * @param IOE_TEMPSENS_FCT: the functions to be configured. could be any - * combination of the following values: - * @arg IOE_IO_FCT : IO function - * @arg IOE_TS_FCT : Touch Screen function - * @arg IOE_ADC_FCT : ADC function - * @arg IOE_TEMPSENS_FCT : Tempreature Sensor function - * @retval IOE_OK: if all initializations are OK. Other value if error. - */ -uint8_t IOE_FnctCmd(uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState) -{ - uint8_t tmp = 0; - - /* Get the register value */ - tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL2); - - if (NewState != DISABLE) - { - /* Set the Functionalities to be Enabled */ - tmp &= ~(uint8_t)Fct; - } - else - { - /* Set the Functionalities to be Disabled */ - tmp |= (uint8_t)Fct; - } - - /* Set the register value */ - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL2, tmp); - - /* If all OK return IOE_OK */ - return IOE_OK; -} - -/** - * @brief Configures the selected pin direction (to be an input or an output) - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR - * or IOE_2_ADDR. - * @param IO_Pin: IO_Pin_x: Where x can be from 0 to 7. - * @param Direction: could be Direction_IN or Direction_OUT. - * @retval IOE_OK: if all initializations are OK. Other value if error. - */ -uint8_t IOE_IOPinConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction) -{ - uint8_t tmp = 0; - - /* Get all the Pins direction */ - tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_DIR); - - if (Direction != Direction_IN) - { - tmp |= (uint8_t)IO_Pin; - } - else - { - tmp &= ~(uint8_t)IO_Pin; - } - - /* Write the register new value */ - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_DIR, tmp); - - /* If all OK return IOE_OK */ - return IOE_OK; -} - -/** - * @brief Enables or disables the Global interrupt. - * @param DeviceAddr: The address of the IOExpander, could be :I OE_1_ADDR - * or IOE_2_ADDR. - * @param NewState: could be ENABLE or DISABLE. - * @retval IOE_OK: if all initializations are OK. Other value if error. - */ -uint8_t IOE_GITCmd(uint8_t DeviceAddr, FunctionalState NewState) -{ - uint8_t tmp = 0; - - /* Read the Interrupt Control register */ - I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_CTRL); - - if (NewState != DISABLE) - { - /* Set the global interrupts to be Enabled */ - tmp |= (uint8_t)IOE_GIT_EN; - } - else - { - /* Set the global interrupts to be Disabled */ - tmp &= ~(uint8_t)IOE_GIT_EN; - } - - /* Write Back the Interrupt Control register */ - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_CTRL, tmp); - - /* If all OK return IOE_OK */ - return IOE_OK; -} - -/** - * @brief Configures the selected source to generate or not a global interrupt - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR - * or IOE_2_ADDR. - * @param Global_IT: the interrupt source to be configured, could be: - * @arg Global_IT_GPIO : All IOs interrupt - * @arg Global_IT_ADC : ADC interrupt - * @arg Global_IT_TEMP : Temperature Sensor interrupts - * @arg Global_IT_FE : Touch Screen Controller FIFO Error interrupt - * @arg Global_IT_FF : Touch Screen Controller FIFO Full interrupt - * @arg Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt - * @arg Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt - * @arg Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt - * @retval IOE_OK: if all initializations are OK. Other value if error. - */ -uint8_t IOE_GITConfig(uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState) -{ - uint8_t tmp = 0; - - /* Get the current value of the INT_EN register */ - tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_EN); - - if (NewState != DISABLE) - { - /* Set the interrupts to be Enabled */ - tmp |= (uint8_t)Global_IT; - } - else - { - /* Set the interrupts to be Disabled */ - tmp &= ~(uint8_t)Global_IT; - } - /* Set the register */ - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_EN, tmp); - - /* If all OK return IOE_OK */ - return IOE_OK; -} - -/** - * @brief Configures the selected pins to generate an interrupt or not. - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR - * or IOE_2_ADDR. - * @param IO_IT: The IO interrupt to be configured. This parameter could be any - * combination of the following values: - * @arg IO_IT_x: where x can be from 0 to 7. - * @param NewState: could be ENABLE or DISABLE. - * @retval IOE_OK: if all initializations are OK. Other value if error. - */ -uint8_t IOE_IOITConfig(uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState) -{ - uint8_t tmp = 0; - - tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_EN); - - if (NewState != DISABLE) - { - /* Set the interrupts to be Enabled */ - tmp |= (uint8_t)IO_IT; - } - else - { - /* Set the interrupts to be Disabled */ - tmp &= ~(uint8_t)IO_IT; - } - - /* Set the register */ - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_EN, tmp); - - /* If all OK return IOE_OK */ - return IOE_OK; -} - -/** - * @brief Configures the touch Screen Controller (Single point detection) - * @param None - * @retval IOE_OK if all initializations are OK. Other value if error. - */ -uint8_t IOE_TS_Config(void) -{ - uint8_t tmp = 0; - - /* Enable TSC Fct: already done in IOE_Config */ - tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2); - tmp &= ~(uint32_t)(IOE_TS_FCT | IOE_ADC_FCT); - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2, tmp); - - /* Enable the TSC gloabl interrupts */ - tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_INT_EN); - tmp |= (uint32_t)(IOE_GIT_TOUCH | IOE_GIT_FTH | IOE_GIT_FOV); - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_EN, tmp); - - /* Select Sample Time, bit number and ADC Reference */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_ADC_CTRL1, 0x49); - - /* Wait for ~20 ms */ - _delay_(2); - - /* Select the ADC clock speed: 3.25 MHz */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_ADC_CTRL2, 0x01); - - /* Select TSC pins in non default mode */ - tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_AF); - tmp &= ~(uint8_t)TOUCH_IO_ALL; - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_AF, tmp); - - /* Select 2 nF filter capacitor */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_CFG, 0x9A); - - /* Select single point reading */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_TH, 0x01); - - /* Write 0x01 to clear the FIFO memory content. */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x01); - - /* Write 0x00 to put the FIFO back into operation mode */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x00); - - /* set the data format for Z value: 7 fractional part and 1 whole part */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_FRACT_XYZ, 0x01); - - /* set the driving capability of the device for TSC pins: 50mA */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_I_DRIVE, 0x01); - - /* Use no tracking index, touchscreen controller operation mode (XYZ) and - enable the TSC */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_CTRL, 0x01); - - /* Clear all the status pending bits */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_STA, 0xFF); - - /* Initialize the TS structure to their default values */ - TS_State.TouchDetected = TS_State.X = TS_State.Y = TS_State.Z = 0; - - /* All configuration done */ - return IOE_OK; -} - -/** - * @brief Configures and enables the Temperature sensor module. - * @param None - * @retval IOE_OK if all initializations are OK. Other value if error. - */ -uint8_t IOE_TempSens_Config(void) -{ - __IO uint8_t tmp = 0; - - /* Enable Temperature Sensor Fct: already done in IOE_Config */ - tmp = I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_SYS_CTRL2); - tmp &= ~(uint32_t)(IOE_TEMPSENS_FCT | IOE_ADC_FCT); - I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_SYS_CTRL2, tmp); - - /* Enable the TEMPSENS module */ - I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_TEMP_CTRL, 0x01); - - /* Aquire data enable */ - I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_TEMP_CTRL, 0x3); - - /* All configuration done */ - return IOE_OK; -} - -/** - * @brief Configures the selected pin to be in Alternate function or not - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR - * or IOE_2_ADDR. - * @param IO_Pin: IO_Pin_x, Where x can be from 0 to 7. - * @param NewState: State of the AF for the selected pin, could be - * ENABLE or DISABLE. - * @retval IOE_OK: if all initializations are OK. Other value if error. - */ -uint8_t IOE_IOAFConfig(uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState) -{ - uint8_t tmp = 0; - - /* Get the current state of the GPIO_AF register */ - tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_AF); - - if (NewState != DISABLE) - { - /* Enable the selected pins alternate function */ - tmp |= (uint8_t)IO_Pin; - } - else - { - /* Disable the selected pins alternate function */ - tmp &= ~(uint8_t)IO_Pin; - } - - /* Write back the new valu in GPIO_AF register */ - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_AF, tmp); - - /* If all OK return IOE_OK */ - return IOE_OK; -} - -/** - * @brief Configures the Edge for which a transition is detectable for the - * the selected pin. - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR - * or IOE_2_ADDR. - * @param IO_Pin: IO_Pin_x, Where x can be from 0 to 7. - * @param Edge: The edge which will be detected. This parameter can be one or a - * a combination of follwing values: EDGE_FALLING and EDGE_RISING . - * @retval IOE_OK: if all initializations are OK. Other value if error. - */ -uint8_t IOE_IOEdgeConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge) -{ - uint8_t tmp1 = 0, tmp2 = 0; - - /* Get the registers values */ - tmp1 = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_FE); - tmp2 = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_RE); - - /* Disable the Falling Edge */ - tmp1 &= ~(uint8_t)IO_Pin; - /* Disable the Falling Edge */ - tmp2 &= ~(uint8_t)IO_Pin; - - /* Enable the Falling edge if selected */ - if (Edge & EDGE_FALLING) - { - tmp1 |= (uint8_t)IO_Pin; - } - - /* Enable the Rising edge if selected */ - if (Edge & EDGE_RISING) - { - tmp2 |= (uint8_t)IO_Pin; - } - - /* Write back the registers values */ - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_FE, tmp1); - I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_RE, tmp2); - - /* if OK return 0 */ - return IOE_OK; -} - -/** - * @brief Configures the Interrupt line active state and format (level/edge) - * @param Polarity: could be - * @arg Polarity_Low: Interrupt line is active Low/Falling edge - * @arg Polarity_High: Interrupt line is active High/Rising edge - * @param Type: Interrupt line activity type, could be one of the following values - * @arg Type_Level: Interrupt line is active in level model - * @arg Type_Edge: Interrupt line is active in edge model - * @retval IOE_OK: if all initializations are OK. Other value if error. - */ -uint8_t IOE_ITOutConfig(uint8_t Polarity, uint8_t Type) -{ - uint8_t tmp = 0; - - /* Get the register IOE_REG_INT_CTRL value */ - tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_INT_CTRL); - - /* Mask the polarity and type bits */ - tmp &= ~(uint8_t)0x06; - - /* Modify the Interrupt Output line configuration */ - tmp |= (uint8_t)(Polarity | Type); - - /* Set the register */ - I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_CTRL, tmp); - - - /* Get the register IOE_REG_INT_CTRL value */ - tmp = I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_INT_CTRL); - /* Mask the polarity and type bits */ - tmp &= ~(uint8_t)0x06; - - /* Modify the Interrupt Output line configuration */ - tmp |= (uint8_t)(Polarity | Type); - - /* Set the register */ - I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_INT_CTRL, tmp); - - /* If all OK return IOE_OK */ - return IOE_OK; -} - -/** - * @brief Writes a value in a register of the device through I2C. - * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR - * or IOE_2_ADDR. - * @param RegisterAddr: The target register adress - * @param RegisterValue: The target register value to be written - * @retval IOE_OK: if all operations are OK. Other value if error. - */ -uint8_t I2C_WriteDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue) -{ - uint32_t read_verif = 0; - uint8_t IOE_BufferTX = 0; - - /* Get Value to be written */ - IOE_BufferTX = RegisterValue; - - /* Configure DMA Peripheral */ - IOE_DMA_Config(IOE_DMA_TX, (uint8_t*)(&IOE_BufferTX)); - - /* Enable the I2C peripheral */ - I2C_GenerateSTART(IOE_I2C, ENABLE); - - /* Test on SB Flag */ - IOE_TimeOut = TIMEOUT_MAX; - while (I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB) == RESET) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Transmit the slave address and enable writing operation */ - I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter); - - /* Test on ADDR Flag */ - IOE_TimeOut = TIMEOUT_MAX; - while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Transmit the first address for r/w operations */ - I2C_SendData(IOE_I2C, RegisterAddr); - - /* Test on TXE FLag (data dent) */ - IOE_TimeOut = TIMEOUT_MAX; - while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF))) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Enable I2C DMA request */ - I2C_DMACmd(IOE_I2C,ENABLE); - - /* Enable DMA TX Channel */ - DMA_Cmd(IOE_DMA_TX_CHANNEL, ENABLE); - - /* Wait until DMA Transfer Complete */ - IOE_TimeOut = TIMEOUT_MAX; - while (!DMA_GetFlagStatus(IOE_DMA_TX_TCFLAG)) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Wait until BTF Flag is set before generating STOP */ - IOE_TimeOut = 2 * TIMEOUT_MAX; - while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF))) - { - } - - /* Send STOP Condition */ - I2C_GenerateSTOP(IOE_I2C, ENABLE); - - /* Disable DMA TX Channel */ - DMA_Cmd(IOE_DMA_TX_CHANNEL, DISABLE); - - /* Disable I2C DMA request */ - I2C_DMACmd(IOE_I2C,DISABLE); - - /* Clear DMA TX Transfer Complete Flag */ - DMA_ClearFlag(IOE_DMA_TX_TCFLAG); - -#ifdef VERIFY_WRITTENDATA - /* Verify (if needed) that the loaded data is correct */ - - /* Read the just written register*/ - read_verif = I2C_ReadDeviceRegister(DeviceAddr, RegisterAddr); - /* Load the register and verify its value */ - if (read_verif != RegisterValue) - { - /* Control data wrongly tranfered */ - read_verif = IOE_FAILURE; - } - else - { - /* Control data correctly transfered */ - read_verif = 0; - } -#endif - - /* Return the verifying value: 0 (Passed) or 1 (Failed) */ - return read_verif; -} - -/** - * @brief Reads a register of the device through I2C. - * @param DeviceAddr: The address of the device, could be : IOE_1_ADDR - * or IOE_2_ADDR. - * @param RegisterAddr: The target register adress (between 00x and 0x24) - * @retval The value of the read register (0xAA if Timout occured) - */ -uint8_t I2C_ReadDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr) -{ - uint8_t IOE_BufferRX[2] = {0x00, 0x00}; - - /* Configure DMA Peripheral */ - IOE_DMA_Config(IOE_DMA_RX, (uint8_t*)IOE_BufferRX); - - /* Enable DMA NACK automatic generation */ - I2C_DMALastTransferCmd(IOE_I2C, ENABLE); - - /* Enable the I2C peripheral */ - I2C_GenerateSTART(IOE_I2C, ENABLE); - - /* Test on SB Flag */ - IOE_TimeOut = TIMEOUT_MAX; - while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB)) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Send device address for write */ - I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter); - - /* Test on ADDR Flag */ - IOE_TimeOut = TIMEOUT_MAX; - while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Send the device's internal address to write to */ - I2C_SendData(IOE_I2C, RegisterAddr); - - /* Test on TXE FLag (data dent) */ - IOE_TimeOut = TIMEOUT_MAX; - while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF))) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Send START condition a second time */ - I2C_GenerateSTART(IOE_I2C, ENABLE); - - /* Test on SB Flag */ - IOE_TimeOut = TIMEOUT_MAX; - while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB)) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Send IOExpander address for read */ - I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Receiver); - - /* Test on ADDR Flag */ - IOE_TimeOut = TIMEOUT_MAX; - while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Enable I2C DMA request */ - I2C_DMACmd(IOE_I2C,ENABLE); - - /* Enable DMA RX Channel */ - DMA_Cmd(IOE_DMA_RX_CHANNEL, ENABLE); - - /* Wait until DMA Transfer Complete */ - IOE_TimeOut = 2 * TIMEOUT_MAX; - while (!DMA_GetFlagStatus(IOE_DMA_RX_TCFLAG)) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Send STOP Condition */ - I2C_GenerateSTOP(IOE_I2C, ENABLE); - - /* Disable DMA RX Channel */ - DMA_Cmd(IOE_DMA_RX_CHANNEL, DISABLE); - - /* Disable I2C DMA request */ - I2C_DMACmd(IOE_I2C,DISABLE); - - /* Clear DMA RX Transfer Complete Flag */ - DMA_ClearFlag(IOE_DMA_RX_TCFLAG); - - /* return a pointer to the IOE_Buffer */ - return (uint8_t)IOE_BufferRX[0]; -} - - -/** - * @brief Reads a buffer of 2 bytes from the device registers. - * @param DeviceAddr: The address of the device, could be : IOE_1_ADDR - * or IOE_2_ADDR. - * @param RegisterAddr: The target register adress (between 00x and 0x24) - * @retval A pointer to the buffer containing the two returned bytes (in halfword). - */ -uint16_t I2C_ReadDataBuffer(uint8_t DeviceAddr, uint32_t RegisterAddr) -{ - uint8_t tmp= 0; - uint8_t IOE_BufferRX[2] = {0x00, 0x00}; - - /* Configure DMA Peripheral */ - IOE_DMA_Config(IOE_DMA_RX, (uint8_t*)IOE_BufferRX); - - /* Enable DMA NACK automatic generation */ - I2C_DMALastTransferCmd(IOE_I2C, ENABLE); - - /* Enable the I2C peripheral */ - I2C_GenerateSTART(IOE_I2C, ENABLE); - - /* Test on SB Flag */ - IOE_TimeOut = TIMEOUT_MAX; - while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB)) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Send device address for write */ - I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter); - - /* Test on ADDR Flag */ - IOE_TimeOut = TIMEOUT_MAX; - while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Send the device's internal address to write to */ - I2C_SendData(IOE_I2C, RegisterAddr); - - /* Test on TXE FLag (data dent) */ - IOE_TimeOut = TIMEOUT_MAX; - while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF))) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Send START condition a second time */ - I2C_GenerateSTART(IOE_I2C, ENABLE); - - /* Test on SB Flag */ - IOE_TimeOut = TIMEOUT_MAX; - while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB)) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Send IOExpander address for read */ - I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Receiver); - - /* Test on ADDR Flag */ - IOE_TimeOut = TIMEOUT_MAX; - while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Enable I2C DMA request */ - I2C_DMACmd(IOE_I2C,ENABLE); - - /* Enable DMA RX Channel */ - DMA_Cmd(IOE_DMA_RX_CHANNEL, ENABLE); - - /* Wait until DMA Transfer Complete */ - IOE_TimeOut = 2 * TIMEOUT_MAX; - while (!DMA_GetFlagStatus(IOE_DMA_RX_TCFLAG)) - { - if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); - } - - /* Send STOP Condition */ - I2C_GenerateSTOP(IOE_I2C, ENABLE); - - /* Disable DMA RX Channel */ - DMA_Cmd(IOE_DMA_RX_CHANNEL, DISABLE); - - /* Disable I2C DMA request */ - I2C_DMACmd(IOE_I2C,DISABLE); - - /* Clear DMA RX Transfer Complete Flag */ - DMA_ClearFlag(IOE_DMA_RX_TCFLAG); - - /* Reorganize received data */ - tmp = IOE_BufferRX[0]; - IOE_BufferRX[0] = IOE_BufferRX[1]; - IOE_BufferRX[1] = tmp; - - /* return a pointer to the IOE_Buffer */ - return *(uint16_t *)IOE_BufferRX; -} - -/** - * @brief Return Touch Screen X position value - * @param None - * @retval X position. - */ -static uint16_t IOE_TS_Read_X(void) -{ - int32_t x, xr; - - x = I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_Y); - - /* first correction */ - xr = (x * 320) >> 12; - /* second correction */ - xr = ((xr * 32)/29) - 17; - - if(xr <= 0) - xr = 0; - - return (uint16_t)(xr); -} - -/** - * @brief Return Touch Screen Y position value - * @param None - * @retval Y position. - */ -static uint16_t IOE_TS_Read_Y(void) -{ - int32_t y, yr; - y= I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_X); - - yr= (y * 240) >> 12; - yr = ((yr * 240) / 217) - 12; - - if(yr <= 0) - yr = 0; - - return (uint16_t)(yr); -} - -/** - * @brief Return Touch Screen Z position value - * @param None - * @retval Z position. - */ -static uint16_t IOE_TS_Read_Z(void) -{ - uint32_t z; - z = I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_Z); - - - if(z <= 0) - z = 0; - - return (uint16_t)(z); -} - -/** - * @brief Initializes the GPIO pins used by the IO expander. - * @param None - * @retval None - */ -static void IOE_GPIO_Config(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable IOE_I2C and IOE_I2C_PORT & Alternate Function clocks */ - RCC_APB1PeriphClockCmd(IOE_I2C_CLK, ENABLE); - RCC_APB2PeriphClockCmd(IOE_I2C_SCL_GPIO_CLK | IOE_I2C_SDA_GPIO_CLK | IOE_IT_GPIO_CLK - | RCC_APB2Periph_AFIO, ENABLE); - - /* Reset IOE_I2C IP */ - RCC_APB1PeriphResetCmd(IOE_I2C_CLK, ENABLE); - - /* Release reset signal of IOE_I2C IP */ - RCC_APB1PeriphResetCmd(IOE_I2C_CLK, DISABLE); - - /* IOE_I2C SCL and SDA pins configuration */ - GPIO_InitStructure.GPIO_Pin = IOE_I2C_SCL_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD; - GPIO_Init(IOE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure); - - /* IOE_I2C SCL and SDA pins configuration */ - GPIO_InitStructure.GPIO_Pin = IOE_I2C_SDA_PIN; - GPIO_Init(IOE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); - - /* Set EXTI pin as Input PullUp - IO_Expander_INT */ - GPIO_InitStructure.GPIO_Pin = IOE_IT_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(IOE_IT_GPIO_PORT, &GPIO_InitStructure); - - /* Connect IO Expander IT line to EXTI line */ - GPIO_EXTILineConfig(IOE_IT_EXTI_PORT_SOURCE, IOE_IT_EXTI_PIN_SOURCE); -} - - -/** - * @brief Configure the I2C Peripheral used to communicate with IO_Expanders. - * @param None - * @retval None - */ -static void IOE_I2C_Config(void) -{ - I2C_InitTypeDef I2C_InitStructure; - - /* IOE_I2C configuration */ - I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; - I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2; - I2C_InitStructure.I2C_OwnAddress1 = 0x00; - I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; - I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; - I2C_InitStructure.I2C_ClockSpeed = IOE_I2C_SPEED; - - I2C_Init(IOE_I2C, &I2C_InitStructure); -} - -/** - * @brief Configure the DMA Peripheral used to handle communication via I2C. - * @param None - * @retval None - */ - -static void IOE_DMA_Config(IOE_DMADirection_TypeDef Direction, uint8_t* buffer) -{ - DMA_InitTypeDef DMA_InitStructure; - - RCC_AHBPeriphClockCmd(IOE_DMA_CLK, ENABLE); - - /* Initialize the DMA_PeripheralBaseAddr member */ - DMA_InitStructure.DMA_PeripheralBaseAddr = IOE_I2C_DR; - /* Initialize the DMA_MemoryBaseAddr member */ - DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)buffer; - /* Initialize the DMA_PeripheralInc member */ - DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - /* Initialize the DMA_MemoryInc member */ - DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - /* Initialize the DMA_PeripheralDataSize member */ - DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - /* Initialize the DMA_MemoryDataSize member */ - DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - /* Initialize the DMA_Mode member */ - DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; - /* Initialize the DMA_Priority member */ - DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; - /* Initialize the DMA_M2M member */ - DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; - - /* If using DMA for Reception */ - if (Direction == IOE_DMA_RX) - { - /* Initialize the DMA_DIR member */ - DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; - - /* Initialize the DMA_BufferSize member */ - DMA_InitStructure.DMA_BufferSize = 2; - - DMA_DeInit(IOE_DMA_RX_CHANNEL); - - DMA_Init(IOE_DMA_RX_CHANNEL, &DMA_InitStructure); - } - /* If using DMA for Transmission */ - else if (Direction == IOE_DMA_TX) - { - /* Initialize the DMA_DIR member */ - DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST; - - /* Initialize the DMA_BufferSize member */ - DMA_InitStructure.DMA_BufferSize = 1; - - DMA_DeInit(IOE_DMA_TX_CHANNEL); - - DMA_Init(IOE_DMA_TX_CHANNEL, &DMA_InitStructure); - } -} - -/** - * @brief Configures the IO expander Interrupt line and GPIO in EXTI mode. - * @param None - * @retval None - */ -static void IOE_EXTI_Config(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - NVIC_InitTypeDef NVIC_InitStructure; - EXTI_InitTypeDef EXTI_InitStructure; - - /* Enable Button GPIO clock */ - RCC_APB2PeriphClockCmd(IOE_IT_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE); - - /* Configure Button pin as input floating */ - GPIO_InitStructure.GPIO_Pin = IOE_IT_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(IOE_IT_GPIO_PORT, &GPIO_InitStructure); - - /* Connect Button EXTI Line to Button GPIO Pin */ - GPIO_EXTILineConfig(IOE_IT_EXTI_PORT_SOURCE, IOE_IT_EXTI_PIN_SOURCE); - - /* Configure Button EXTI line */ - EXTI_InitStructure.EXTI_Line = IOE_IT_EXTI_LINE; - EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling; - EXTI_InitStructure.EXTI_LineCmd = ENABLE; - EXTI_Init(&EXTI_InitStructure); - - /* Enable and set Button EXTI Interrupt to the lowest priority */ - NVIC_InitStructure.NVIC_IRQChannel = IOE_IT_EXTI_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); -} - -#ifndef USE_Delay -/** - * @brief Inserts a delay time. - * @param nCount: specifies the delay time length. - * @retval None - */ -static void delay(__IO uint32_t nCount) -{ - __IO uint32_t index = 0; - for(index = (100000 * nCount); index != 0; index--) - { - } -} -#endif /* USE_Delay*/ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_ioe.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_ioe.h deleted file mode 100644 index aafccbe95..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_ioe.h +++ /dev/null @@ -1,537 +0,0 @@ -/** - ****************************************************************************** - * @file stm3210c_eval_ioe.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains all the functions prototypes for the IO Expander - * firmware driver. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - - /* File Info : --------------------------------------------------------------- - SUPPORTED FEATURES: - - IO Read/write : Set/Reset and Read (Polling/Interrupt) - - Joystick: config and Read (Polling/Interrupt) - - Touch Screen Features: Single point mode (Polling/Interrupt) - - TempSensor Feature: accuracy not determined (Polling). - - UNSUPPORTED FEATURES: - - Row ADC Feature is not supported (not implemented on STM3210C-EVAL board) - ----------------------------------------------------------------------------*/ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM3210C_EVAL_IOE_H -#define __STM3210C_EVAL_IOE_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM3210C_EVAL - * @{ - */ - -/** @defgroup STM3210C_EVAL_IOE - * @{ - */ - -/** @defgroup STM3210C_EVAL_IOE_Exported_Types - * @{ - */ - -/** - * @brief Touch Screen Information structure - */ -typedef struct -{ - uint16_t TouchDetected; - uint16_t X; - uint16_t Y; - uint16_t Z; -}TS_STATE; - -/** - * @brief Joystick State definitions - */ -#ifndef __STM32_EVAL_H -typedef enum -{ - JOY_NONE = 0, - JOY_SEL = 1, - JOY_DOWN = 2, - JOY_LEFT = 3, - JOY_RIGHT = 4, - JOY_UP = 5 -} JOYState_TypeDef -; -#endif /* __STM32_EVAL_H */ - -/** - * @brief IO_Expander Error codes - */ -typedef enum -{ - IOE_OK = 0, - IOE_FAILURE, - IOE_TIMEOUT, - PARAM_ERROR, - IOE1_NOT_OPERATIONAL, - IOE2_NOT_OPERATIONAL -}IOE_Status_TypDef; - -/** - * @brief IO bit values - */ -typedef enum -{ - BitReset = 0, - BitSet = 1 -}IOE_BitValue_TypeDef; - -/** - * @brief IOE DMA Direction - */ -typedef enum -{ - IOE_DMA_TX = 0, - IOE_DMA_RX = 1 -}IOE_DMADirection_TypeDef; - -/** - * @} - */ - - -/** @defgroup STM3210C_EVAL_IOE_Exported_Constants - * @{ - */ - -/** - * @brief Uncomment the line below to enable verfying each written byte in write - * operation. The I2C_WriteDeviceRegister() function will then compare the - * written and read data and return error status if a mismatch occurs. - */ -/* #define VERIFY_WRITTENDATA */ - -/** - * @brief Uncomment the line below if you want to use user defined Delay function - * (for precise timing), otherwise default _delay_ function defined within - * this driver is used (less precise timing). - */ -/* #define USE_Delay */ - -/** - * @brief Uncomment the line below if you want to use user timeout callback. - * Function prototypes is declared in this file but function body may be - * implemented into user application. - */ -/* #define USE_TIMEOUT_USER_CALLBACK */ - -#ifdef USE_Delay -#include "main.h" - - #define _delay_ Delay /* !< User can provide more timing precise _delay_ function - (with 10ms time base), using SysTick for example */ -#else - #define _delay_ delay /* !< Default _delay_ function with less precise timing */ -#endif - -/*------------------------------------------------------------------------------ - Hardware Configuration -------------------------------------------------------------------------------*/ -/** - * @brief I2C port definitions - */ -#define IOE_I2C I2C1 -#define IOE_I2C_CLK RCC_APB1Periph_I2C1 -#define IOE_I2C_SCL_PIN GPIO_Pin_6 -#define IOE_I2C_SCL_GPIO_PORT GPIOB -#define IOE_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB -#define IOE_I2C_SDA_PIN GPIO_Pin_7 -#define IOE_I2C_SDA_GPIO_PORT GPIOB -#define IOE_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB -#define IOE_I2C_DR ((uint32_t)0x40005410) -#define IOE_I2C_SPEED 300000 - -/** - * @brief IOE DMA definitions - */ -#define IOE_DMA DMA1 -#define IOE_DMA_CLK RCC_AHBPeriph_DMA1 -#define IOE_DMA_TX_CHANNEL DMA1_Channel6 -#define IOE_DMA_RX_CHANNEL DMA1_Channel7 -#define IOE_DMA_TX_TCFLAG DMA1_FLAG_TC6 -#define IOE_DMA_RX_TCFLAG DMA1_FLAG_TC7 - - -/** - * @brief IO Expander Interrupt line on EXTI - */ -#define IOE_IT_PIN GPIO_Pin_14 -#define IOE_IT_GPIO_PORT GPIOB -#define IOE_IT_GPIO_CLK RCC_APB2Periph_GPIOB -#define IOE_IT_EXTI_PORT_SOURCE GPIO_PortSourceGPIOB -#define IOE_IT_EXTI_PIN_SOURCE GPIO_PinSource14 -#define IOE_IT_EXTI_LINE EXTI_Line14 -#define IOE_IT_EXTI_IRQn EXTI15_10_IRQn - -/** - * @brief Eval Board IO Pins definition - */ -#define AUDIO_RESET_PIN IO_Pin_2 /* IO_Exapnader_2 */ /* Output */ -#define MII_INT_PIN IO_Pin_0 /* IO_Exapnader_2 */ /* Output */ -#define VBAT_DIV_PIN IO_Pin_0 /* IO_Exapnader_1 */ /* Output */ -#define MEMS_INT1_PIN IO_Pin_3 /* IO_Exapnader_1 */ /* Input */ -#define MEMS_INT2_PIN IO_Pin_2 /* IO_Exapnader_1 */ /* Input */ - - -/** - * @brief Eval Board both IO Exapanders Pins definition - */ -#define IO1_IN_ALL_PINS (uint32_t)(MEMS_INT1_PIN | MEMS_INT2_PIN) -#define IO2_IN_ALL_PINS (uint32_t)(JOY_IO_PINS) -#define IO1_OUT_ALL_PINS (uint32_t)(VBAT_DIV_PIN) -#define IO2_OUT_ALL_PINS (uint32_t)(AUDIO_RESET_PIN | MII_INT_PIN) - -/** - * @brief The 7 bits IO Expanders adresses and chip IDs - */ -#define IOE_1_ADDR 0x82 -#define IOE_2_ADDR 0x88 -#define STMPE811_ID 0x0811 - - -/*------------------------------------------------------------------------------ - Functional and Interrupt Management -------------------------------------------------------------------------------*/ -/** - * @brief IO Expander Functionalities definitions - */ -#define IOE_ADC_FCT 0x01 -#define IOE_TS_FCT 0x02 -#define IOE_IO_FCT 0x04 -#define IOE_TEMPSENS_FCT 0x08 - -/** - * @brief Interrupt source configuration definitons - */ -#define IOE_ITSRC_TSC 0x01 /* IO_Exapnder 1 */ -#define IOE_ITSRC_INMEMS 0x02 /* IO_Exapnder 1 */ -#define IOE_ITSRC_JOYSTICK 0x04 /* IO_Exapnder 2 */ -#define IOE_ITSRC_TEMPSENS 0x08 /* IO_Exapnder 2 */ - -/** - * @brief Glaobal Interrupts definitions - */ -#define IOE_GIT_GPIO 0x80 -#define IOE_GIT_ADC 0x40 -#define IOE_GIT_TEMP 0x20 -#define IOE_GIT_FE 0x10 -#define IOE_GIT_FF 0x08 -#define IOE_GIT_FOV 0x04 -#define IOE_GIT_FTH 0x02 -#define IOE_GIT_TOUCH 0x01 - - -/*------------------------------------------------------------------------------ - STMPE811 device register definition -------------------------------------------------------------------------------*/ -/** - * @brief Identification registers - */ -#define IOE_REG_CHP_ID 0x00 -#define IOE_REG_ID_VER 0x02 - -/** - * @brief General Control Registers - */ -#define IOE_REG_SYS_CTRL1 0x03 -#define IOE_REG_SYS_CTRL2 0x04 -#define IOE_REG_SPI_CFG 0x08 - -/** - * @brief Interrupt Control register - */ -#define IOE_REG_INT_CTRL 0x09 -#define IOE_REG_INT_EN 0x0A -#define IOE_REG_INT_STA 0x0B -#define IOE_REG_GPIO_INT_EN 0x0C -#define IOE_REG_GPIO_INT_STA 0x0D - -/** - * @brief GPIO Registers - */ -#define IOE_REG_GPIO_SET_PIN 0x10 -#define IOE_REG_GPIO_CLR_PIN 0x11 -#define IOE_REG_GPIO_MP_STA 0x12 -#define IOE_REG_GPIO_DIR 0x13 -#define IOE_REG_GPIO_ED 0x14 -#define IOE_REG_GPIO_RE 0x15 -#define IOE_REG_GPIO_FE 0x16 -#define IOE_REG_GPIO_AF 0x17 - -/** - * @brief ADC Registers - */ -#define IOE_REG_ADC_INT_EN 0x0E -#define IOE_REG_ADC_INT_STA 0x0F -#define IOE_REG_ADC_CTRL1 0x20 -#define IOE_REG_ADC_CTRL2 0x21 -#define IOE_REG_ADC_CAPT 0x22 -#define IOE_REG_ADC_DATA_CH0 0x30 /* 16-Bit register */ -#define IOE_REG_ADC_DATA_CH1 0x32 /* 16-Bit register */ -#define IOE_REG_ADC_DATA_CH2 0x34 /* 16-Bit register */ -#define IOE_REG_ADC_DATA_CH3 0x36 /* 16-Bit register */ -#define IOE_REG_ADC_DATA_CH4 0x38 /* 16-Bit register */ -#define IOE_REG_ADC_DATA_CH5 0x3A /* 16-Bit register */ -#define IOE_REG_ADC_DATA_CH6 0x3B /* 16-Bit register */ -#define IOE_REG_ADC_DATA_CH7 0x3C /* 16-Bit register */ - -/** - * @brief TouchScreen Registers - */ -#define IOE_REG_TSC_CTRL 0x40 -#define IOE_REG_TSC_CFG 0x41 -#define IOE_REG_WDM_TR_X 0x42 -#define IOE_REG_WDM_TR_Y 0x44 -#define IOE_REG_WDM_BL_X 0x46 -#define IOE_REG_WDM_BL_Y 0x48 -#define IOE_REG_FIFO_TH 0x4A -#define IOE_REG_FIFO_STA 0x4B -#define IOE_REG_FIFO_SIZE 0x4C -#define IOE_REG_TSC_DATA_X 0x4D -#define IOE_REG_TSC_DATA_Y 0x4F -#define IOE_REG_TSC_DATA_Z 0x51 -#define IOE_REG_TSC_DATA_XYZ 0x52 -#define IOE_REG_TSC_FRACT_XYZ 0x56 -#define IOE_REG_TSC_DATA 0x57 -#define IOE_REG_TSC_I_DRIVE 0x58 -#define IOE_REG_TSC_SHIELD 0x59 - -/** - * @brief Temperature Sensor registers - */ -#define IOE_REG_TEMP_CTRL 0x60 -#define IOE_REG_TEMP_DATA 0x61 -#define IOE_REG_TEMP_TH 0x62 - - -/*------------------------------------------------------------------------------ - Functions parameters defines -------------------------------------------------------------------------------*/ -/** - * @brief Touch Screen Pins definition - */ -#define TOUCH_YD IO_Pin_1 /* IO_Exapnader_1 */ /* Input */ -#define TOUCH_XD IO_Pin_2 /* IO_Exapnader_1 */ /* Input */ -#define TOUCH_YU IO_Pin_3 /* IO_Exapnader_1 */ /* Input */ -#define TOUCH_XU IO_Pin_4 /* IO_Exapnader_1 */ /* Input */ -#define TOUCH_IO_ALL (uint32_t)(IO_Pin_1 | IO_Pin_2 | IO_Pin_3 | IO_Pin_4) - -/** - * @brief JOYSTICK Pins definition - */ -#define JOY_IO_SEL IO_Pin_7 -#define JOY_IO_DOWN IO_Pin_6 -#define JOY_IO_LEFT IO_Pin_5 -#define JOY_IO_RIGHT IO_Pin_4 -#define JOY_IO_UP IO_Pin_3 -#define JOY_IO_NONE JOY_IO_PINS -#define JOY_IO_PINS (uint32_t)(IO_Pin_3 | IO_Pin_4 | IO_Pin_5 | IO_Pin_6 | IO_Pin_7) - -/** - * @brief IO Pins - */ -#define IO_Pin_0 0x01 -#define IO_Pin_1 0x02 -#define IO_Pin_2 0x04 -#define IO_Pin_3 0x08 -#define IO_Pin_4 0x10 -#define IO_Pin_5 0x20 -#define IO_Pin_6 0x40 -#define IO_Pin_7 0x80 -#define IO_Pin_ALL 0xFF - -/** - * @brief IO Pin directions - */ -#define Direction_IN 0x00 -#define Direction_OUT 0x01 - -/** - * @brief Interrupt Line output parameters - */ -#define Polarity_Low 0x00 -#define Polarity_High 0x04 -#define Type_Level 0x00 -#define Type_Edge 0x02 - -/** - * @brief IO Interrupts - */ -#define IO_IT_0 0x01 -#define IO_IT_1 0x02 -#define IO_IT_2 0x04 -#define IO_IT_3 0x08 -#define IO_IT_4 0x10 -#define IO_IT_5 0x20 -#define IO_IT_6 0x40 -#define IO_IT_7 0x80 -#define ALL_IT 0xFF -#define IOE_JOY_IT (uint8_t)(IO_IT_3 | IO_IT_4 | IO_IT_5 | IO_IT_6 | IO_IT_7) -#define IOE_TS_IT (uint8_t)(IO_IT_0 | IO_IT_1 | IO_IT_2) -#define IOE_INMEMS_IT (uint8_t)(IO_IT_2 | IO_IT_3) - -/** - * @brief Edge detection value - */ -#define EDGE_FALLING 0x01 -#define EDGE_RISING 0x02 - -/** - * @brief Global interrupt Enable bit - */ -#define IOE_GIT_EN 0x01 - -/** - * @} - */ - - - -/** @defgroup STM3210C_EVAL_IOE_Exported_Macros - * @{ - */ -/** - * @} - */ - - - -/** @defgroup STM3210C_EVAL_IOE_Exported_Functions - * @{ - */ - -/** - * @brief Configuration and initialization functions - */ -uint8_t IOE_Config(void); -uint8_t IOE_ITConfig(uint32_t IOE_ITSRC_Source); - -/** - * @brief Timeout user callback function. This function is called when a timeout - * condition occurs during communication with IO Expander. Only protoype - * of this function is decalred in IO Expander driver. Its implementation - * may be done into user application. This function may typically stop - * current operations and reset the I2C peripheral and IO Expander. - * To enable this function use uncomment the define USE_TIMEOUT_USER_CALLBACK - * at the top of this file. - */ -#ifdef USE_TIMEOUT_USER_CALLBACK - uint8_t IOE_TimeoutUserCallback(void); -#else - #define IOE_TimeoutUserCallback() IOE_TIMEOUT -#endif /* USE_TIMEOUT_USER_CALLBACK */ - -/** - * @brief IO pins control functions - */ -uint8_t IOE_WriteIOPin(uint8_t IO_Pin, IOE_BitValue_TypeDef BitVal); -uint8_t IOE_ReadIOPin(uint32_t IO_Pin); -JOYState_TypeDef - IOE_JoyStickGetState(void); - -/** - * @brief Touch Screen controller functions - */ -TS_STATE* IOE_TS_GetState(void); - -/** - * @brief Interrupts Mangement functions - */ -FlagStatus IOE_GetGITStatus(uint8_t DeviceAddr, uint8_t Global_IT); -uint8_t IOE_ClearGITPending(uint8_t DeviceAddr, uint8_t IO_IT); -FlagStatus IOE_GetIOITStatus(uint8_t DeviceAddr, uint8_t IO_IT); -uint8_t IOE_ClearIOITPending(uint8_t DeviceAddr, uint8_t IO_IT); - -/** - * @brief Temperature Sensor functions - */ -uint32_t IOE_TempSens_GetData(void); - -/** - * @brief IO-Expander Control functions - */ -uint8_t IOE_IsOperational(uint8_t DeviceAddr); -uint8_t IOE_Reset(uint8_t DeviceAddr); -uint16_t IOE_ReadID(uint8_t DeviceAddr); - -uint8_t IOE_FnctCmd(uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState); -uint8_t IOE_IOPinConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction); -uint8_t IOE_GITCmd(uint8_t DeviceAddr, FunctionalState NewState); -uint8_t IOE_GITConfig(uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState); -uint8_t IOE_IOITConfig(uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState); - -/** - * @brief Low Layer functions - */ -uint8_t IOE_TS_Config(void); -uint8_t IOE_TempSens_Config(void); -uint8_t IOE_IOAFConfig(uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState); -uint8_t IOE_IOEdgeConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge); -uint8_t IOE_ITOutConfig(uint8_t Polarity, uint8_t Type); - -uint8_t I2C_WriteDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue); -uint8_t I2C_ReadDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr); -uint16_t I2C_ReadDataBuffer(uint8_t DeviceAddr, uint32_t RegisterAddr); - -#ifdef __cplusplus -} - -#endif -#endif /* __STM3210C_EVAL_IOE_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_lcd.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_lcd.c deleted file mode 100644 index 5caf01aad..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_lcd.c +++ /dev/null @@ -1,1407 +0,0 @@ -/** - ****************************************************************************** - * @file stm3210c_eval_lcd.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320) - * Liquid Crystal Display Module of STM3210C-EVAL board. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm3210c_eval_lcd.h" -#include "../Common/fonts.c" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM3210C_EVAL - * @{ - */ - -/** @defgroup STM3210C_EVAL_LCD - * @brief This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320) - * Liquid Crystal Display Module of STM3210C-EVAL board. - * @{ - */ - -/** @defgroup STM3210C_EVAL_LCD_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM3210C_EVAL_LCD_Private_Defines - * @{ - */ -#define START_BYTE 0x70 -#define SET_INDEX 0x00 -#define READ_STATUS 0x01 -#define LCD_WRITE_REG 0x02 -#define LCD_READ_REG 0x03 -#define MAX_POLY_CORNERS 200 -#define POLY_Y(Z) ((int32_t)((Points + Z)->X)) -#define POLY_X(Z) ((int32_t)((Points + Z)->Y)) -/** - * @} - */ - - -/** @defgroup STM3210C_EVAL_LCD_Private_Macros - * @{ - */ -#define ABS(X) ((X) > 0 ? (X) : -(X)) -/** - * @} - */ - - -/** @defgroup STM3210C_EVAL_LCD_Private_Variables - * @{ - */ -static sFONT *LCD_Currentfonts; -/* Global variables to set the written text color */ -static __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF; -/** - * @} - */ - - -/** @defgroup STM3210C_EVAL_LCD_Private_FunctionPrototypes - * @{ - */ -#ifndef USE_Delay -static void delay(__IO uint32_t nCount); -#endif /* USE_Delay*/ -static void PutPixel(int16_t x, int16_t y); -static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed); -/** - * @} - */ - - -/** @defgroup STM3210C_EVAL_LCD_Private_Functions - * @{ - */ - -/** - * @brief DeInitializes the LCD. - * @param None - * @retval None - */ -void LCD_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< LCD Display Off */ - LCD_DisplayOff(); - - /*!< LCD_SPI disable */ - SPI_Cmd(LCD_SPI, DISABLE); - - /*!< LCD_SPI DeInit */ - SPI_I2S_DeInit(LCD_SPI); - - /*!< Disable SPI clock */ - RCC_APB1PeriphClockCmd(LCD_SPI_CLK, DISABLE); - GPIO_PinRemapConfig(GPIO_Remap_SPI3, DISABLE); - - /* Configure NCS in Output Push-Pull mode */ - GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure); - - /* Configure SPI pins: SCK, MISO and MOSI */ - GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN; - GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN; - GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN; - GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @brief Setups the LCD. - * @param None - * @retval None - */ -void LCD_Setup(void) -{ -/* Configure the LCD Control pins --------------------------------------------*/ - LCD_CtrlLinesConfig(); - -/* Configure the LCD_SPI interface ----------------------------------------------*/ - LCD_SPIConfig(); - _delay_(5); /* Delay 50 ms */ - /* Start Initial Sequence ------------------------------------------------*/ - LCD_WriteReg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */ - LCD_WriteReg(LCD_REG_0, 0x0001); /* Start internal OSC. */ - LCD_WriteReg(LCD_REG_1, 0x0100); /* set SS and SM bit */ - LCD_WriteReg(LCD_REG_2, 0x0700); /* set 1 line inversion */ - LCD_WriteReg(LCD_REG_3, 0x1030); /* set GRAM write direction and BGR=1. */ - LCD_WriteReg(LCD_REG_4, 0x0000); /* Resize register */ - LCD_WriteReg(LCD_REG_8, 0x0202); /* set the back porch and front porch */ - LCD_WriteReg(LCD_REG_9, 0x0000); /* set non-display area refresh cycle ISC[3:0] */ - LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */ - LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */ - LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */ - LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */ - /* Power On sequence -----------------------------------------------------*/ - LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ - _delay_(20); /* Dis-charge capacitor power voltage (200ms) */ - LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ - LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ - LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */ - /* Adjust the Gamma Curve ------------------------------------------------*/ - LCD_WriteReg(LCD_REG_48, 0x0006); - LCD_WriteReg(LCD_REG_49, 0x0101); - LCD_WriteReg(LCD_REG_50, 0x0003); - LCD_WriteReg(LCD_REG_53, 0x0106); - LCD_WriteReg(LCD_REG_54, 0x0b02); - LCD_WriteReg(LCD_REG_55, 0x0302); - LCD_WriteReg(LCD_REG_56, 0x0707); - LCD_WriteReg(LCD_REG_57, 0x0007); - LCD_WriteReg(LCD_REG_60, 0x0600); - LCD_WriteReg(LCD_REG_61, 0x020b); - - /* Set GRAM area ---------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ - LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */ - LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ - LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */ - LCD_WriteReg(LCD_REG_96, 0x2700); /* Gate Scan Line */ - LCD_WriteReg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ - LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */ - /* Partial Display Control -----------------------------------------------*/ - LCD_WriteReg(LCD_REG_128, 0x0000); - LCD_WriteReg(LCD_REG_129, 0x0000); - LCD_WriteReg(LCD_REG_130, 0x0000); - LCD_WriteReg(LCD_REG_131, 0x0000); - LCD_WriteReg(LCD_REG_132, 0x0000); - LCD_WriteReg(LCD_REG_133, 0x0000); - /* Panel Control ---------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_144, 0x0010); - LCD_WriteReg(LCD_REG_146, 0x0000); - LCD_WriteReg(LCD_REG_147, 0x0003); - LCD_WriteReg(LCD_REG_149, 0x0110); - LCD_WriteReg(LCD_REG_151, 0x0000); - LCD_WriteReg(LCD_REG_152, 0x0000); - /* Set GRAM write direction and BGR = 1 */ - /* I/D=01 (Horizontal : increment, Vertical : decrement) */ - /* AM=1 (address is updated in vertical writing direction) */ - LCD_WriteReg(LCD_REG_3, 0x1018); - LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */ -} - - -/** - * @brief Initializes the LCD. - * @param None - * @retval None - */ -void STM3210C_LCD_Init(void) -{ - /* Setups the LCD */ - LCD_Setup(); - LCD_SetFont(&LCD_DEFAULT_FONT); -} - -/** - * @brief Sets the LCD Text and Background colors. - * @param _TextColor: specifies the Text Color. - * @param _BackColor: specifies the Background Color. - * @retval None - */ -void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor) -{ - TextColor = _TextColor; - BackColor = _BackColor; -} - -/** - * @brief Gets the LCD Text and Background colors. - * @param _TextColor: pointer to the variable that will contain the Text - Color. - * @param _BackColor: pointer to the variable that will contain the Background - Color. - * @retval None - */ -void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor) -{ - *_TextColor = TextColor; *_BackColor = BackColor; -} - -/** - * @brief Sets the Text color. - * @param Color: specifies the Text color code RGB(5-6-5). - * @retval None - */ -void LCD_SetTextColor(__IO uint16_t Color) -{ - TextColor = Color; -} - - -/** - * @brief Sets the Background color. - * @param Color: specifies the Background color code RGB(5-6-5). - * @retval None - */ -void LCD_SetBackColor(__IO uint16_t Color) -{ - BackColor = Color; -} - -/** - * @brief Sets the Text Font. - * @param fonts: specifies the font to be used. - * @retval None - */ -void LCD_SetFont(sFONT *fonts) -{ - LCD_Currentfonts = fonts; -} - -/** - * @brief Gets the Text Font. - * @param None. - * @retval the used font. - */ -sFONT *LCD_GetFont(void) -{ - return LCD_Currentfonts; -} - -/** - * @brief Clears the selected line. - * @param Line: the Line to be cleared. - * This parameter can be one of the following values: - * @arg Linex: where x can be 0..n - * @retval None - */ -void LCD_ClearLine(uint8_t Line) -{ - uint16_t refcolumn = LCD_PIXEL_WIDTH - 1; - /* Send the string character by character on lCD */ - while (((refcolumn + 1)& 0xFFFF) >= LCD_Currentfonts->Width) - { - /* Display one character on LCD */ - LCD_DisplayChar(Line, refcolumn, ' '); - /* Decrement the column position by 16 */ - refcolumn -= LCD_Currentfonts->Width; - } -} - - -/** - * @brief Clears the hole LCD. - * @param Color: the color of the background. - * @retval None - */ -void LCD_Clear(uint16_t Color) -{ - uint32_t index = 0; - - LCD_SetCursor(0x00, 0x013F); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - for(index = 0; index < 76800; index++) - { - LCD_WriteRAM(Color); - } - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); - -} - - -/** - * @brief Sets the cursor position. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @retval None - */ -void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos) -{ - LCD_WriteReg(LCD_REG_32, Xpos); - LCD_WriteReg(LCD_REG_33, Ypos); -} - - -/** - * @brief Draws a character on LCD. - * @param Xpos: the Line where to display the character shape. - * @param Ypos: start column address. - * @param c: pointer to the character data. - * @retval None - */ -void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c) -{ - uint32_t index = 0, i = 0; - uint8_t Xaddress = 0; - - Xaddress = Xpos; - - LCD_SetCursor(Xaddress, Ypos); - - for(index = 0; index < LCD_Currentfonts->Height; index++) - { - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - for(i = 0; i < LCD_Currentfonts->Width; i++) - { - if((((c[index] & ((0x80 << ((LCD_Currentfonts->Width / 12 ) * 8 ) ) >> i)) == 0x00) &&(LCD_Currentfonts->Width <= 12))|| - (((c[index] & (0x1 << i)) == 0x00)&&(LCD_Currentfonts->Width > 12 ))) - - { - LCD_WriteRAM(BackColor); - } - else - { - LCD_WriteRAM(TextColor); - } - } - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); - Xaddress++; - LCD_SetCursor(Xaddress, Ypos); - } -} - - -/** - * @brief Displays one character (16dots width, 24dots height). - * @param Line: the Line where to display the character shape . - * This parameter can be one of the following values: - * @arg Linex: where x can be 0..9 - * @param Column: start column address. - * @param Ascii: character ascii code, must be between 0x20 and 0x7E. - * @retval None - */ -void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii) -{ - Ascii -= 32; - LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]); -} - - -/** - * @brief Displays a maximum of 20 char on the LCD. - * @param Line: the Line where to display the character shape . - * This parameter can be one of the following values: - * @arg Linex: where x can be 0..9 - * @param *ptr: pointer to string to display on LCD. - * @retval None - */ -void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr) -{ - uint16_t refcolumn = LCD_PIXEL_WIDTH - 1; - - /* Send the string character by character on lCD */ - while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width)) - { - /* Display one character on LCD */ - LCD_DisplayChar(Line, refcolumn, *ptr); - /* Decrement the column position by 16 */ - refcolumn -= LCD_Currentfonts->Width; - /* Point on the next character */ - ptr++; - } -} - - -/** - * @brief Sets a display window - * @param Xpos: specifies the X buttom left position. - * @param Ypos: specifies the Y buttom left position. - * @param Height: display window height. - * @param Width: display window width. - * @retval None - */ -void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width) -{ - /* Horizontal GRAM Start Address */ - if(Xpos >= Height) - { - LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1)); - } - else - { - LCD_WriteReg(LCD_REG_80, 0); - } - /* Horizontal GRAM End Address */ - LCD_WriteReg(LCD_REG_81, Xpos); - /* Vertical GRAM Start Address */ - if(Ypos >= Width) - { - LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1)); - } - else - { - LCD_WriteReg(LCD_REG_82, 0); - } - /* Vertical GRAM End Address */ - LCD_WriteReg(LCD_REG_83, Ypos); - LCD_SetCursor(Xpos, Ypos); -} - - -/** - * @brief Disables LCD Window mode. - * @param None - * @retval None - */ -void LCD_WindowModeDisable(void) -{ - LCD_SetDisplayWindow(239, 0x13F, 240, 320); - LCD_WriteReg(LCD_REG_3, 0x1018); -} - - -/** - * @brief Displays a line. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Length: line length. - * @param Direction: line direction. - * This parameter can be one of the following values: Vertical or Horizontal. - * @retval None - */ -void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction) -{ - uint32_t i = 0; - - LCD_SetCursor(Xpos, Ypos); - if(Direction == LCD_DIR_HORIZONTAL) - { - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - for(i = 0; i < Length; i++) - { - LCD_WriteRAM(TextColor); - } - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); - } - else - { - for(i = 0; i < Length; i++) - { - LCD_WriteRAMWord(TextColor); - Xpos++; - LCD_SetCursor(Xpos, Ypos); - } - } -} - - -/** - * @brief Displays a rectangle. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Height: display rectangle height. - * @param Width: display rectangle width. - * @retval None - */ -void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width) -{ - LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL); - LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL); - - LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL); - LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL); -} - - -/** - * @brief Displays a circle. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Radius - * @retval None - */ -void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius) -{ - s32 D;/* Decision Variable */ - uint32_t CurX;/* Current X Value */ - uint32_t CurY;/* Current Y Value */ - - D = 3 - (Radius << 1); - CurX = 0; - CurY = Radius; - - while (CurX <= CurY) - { - LCD_SetCursor(Xpos + CurX, Ypos + CurY); - LCD_WriteRAMWord(TextColor); - LCD_SetCursor(Xpos + CurX, Ypos - CurY); - LCD_WriteRAMWord(TextColor); - LCD_SetCursor(Xpos - CurX, Ypos + CurY); - LCD_WriteRAMWord(TextColor); - LCD_SetCursor(Xpos - CurX, Ypos - CurY); - LCD_WriteRAMWord(TextColor); - LCD_SetCursor(Xpos + CurY, Ypos + CurX); - LCD_WriteRAMWord(TextColor); - LCD_SetCursor(Xpos + CurY, Ypos - CurX); - LCD_WriteRAMWord(TextColor); - LCD_SetCursor(Xpos - CurY, Ypos + CurX); - LCD_WriteRAMWord(TextColor); - LCD_SetCursor(Xpos - CurY, Ypos - CurX); - LCD_WriteRAMWord(TextColor); - if (D < 0) - { - D += (CurX << 2) + 6; - } - else - { - D += ((CurX - CurY) << 2) + 10; - CurY--; - } - CurX++; - } -} - -/** - * @brief Displays a monocolor picture. - * @param Pict: pointer to the picture array. - * @retval None - */ -void LCD_DrawMonoPict(const uint32_t *Pict) -{ - uint32_t index = 0, i = 0; - LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1)); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - for(index = 0; index < 2400; index++) - { - for(i = 0; i < 32; i++) - { - if((Pict[index] & (1 << i)) == 0x00) - { - LCD_WriteRAM(BackColor); - } - else - { - LCD_WriteRAM(TextColor); - } - } - } - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); -} - -#ifdef USE_LCD_DrawBMP -/** - * @brief Displays a bitmap picture loaded in the SPI Flash. - * @param BmpAddress: Bmp picture address in the SPI Flash. - * @retval None - */ -//void LCD_DrawBMP(uint32_t BmpAddress) -//{ -// uint32_t i = 0, size = 0; -// -// /* Read bitmap size */ -// sFLASH_ReadBuffer((uint8_t*)&size, BmpAddress + 2, 4); -// -// /* get bitmap data address offset */ -// sFLASH_ReadBuffer((uint8_t*)&i, BmpAddress + 10, 4); -// -// size = (size - i)/2; -// -// sFLASH_StartReadSequence(BmpAddress + i); -// -// /* Disable LCD_SPI */ -// SPI_Cmd(LCD_SPI, DISABLE); -// /* SPI in 16-bit mode */ -// SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_16b); -// -// /* Enable LCD_SPI */ -// SPI_Cmd(LCD_SPI, ENABLE); -// -// /* Set GRAM write direction and BGR = 1 */ -// /* I/D=00 (Horizontal : decrement, Vertical : decrement) */ -// /* AM=1 (address is updated in vertical writing direction) */ -// LCD_WriteReg(LCD_REG_3, 0x1008); -// -// LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ -// -// /* Read bitmap data from SPI Flash and send them to LCD */ -// for(i = 0; i < size; i++) -// { -// LCD_WriteRAM(__REV_HalfWord(sFLASH_SendHalfWord(0xA5A5))); -// } -// -// LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); -// -// /* Deselect the FLASH: Chip Select high */ -// sFLASH_CS_HIGH(); -// -// /* Disable LCD_SPI */ -// SPI_Cmd(LCD_SPI, DISABLE); -// /* SPI in 8-bit mode */ -// SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_8b); -// -// /* Enable LCD_SPI */ -// SPI_Cmd(LCD_SPI, ENABLE); -// -// /* Set GRAM write direction and BGR = 1 */ -// /* I/D = 01 (Horizontal : increment, Vertical : decrement) */ -// /* AM = 1 (address is updated in vertical writing direction) */ -// LCD_WriteReg(LCD_REG_3, 0x1018); -//} - - -/** - * @brief Displays a bitmap picture loaded in the Internal FLASH. - * @param BmpAddress: Bmp picture address in the Internal FLASH. - * @retval None - */ -void LCD_DrawBMP(const uint16_t *BmpAddress) -{ - uint32_t i = 0, size = 0; - /* Read bitmap size */ - size = BmpAddress[1] | (BmpAddress[2] << 16); - /* get bitmap data address offset */ - i = BmpAddress[5] | (BmpAddress[6] << 16); - size = (size - i)/2; - BmpAddress += i/2; - /* Set GRAM write direction and BGR = 1 */ - /* I/D=00 (Horizontal : decrement, Vertical : decrement) */ - /* AM=1 (address is updated in vertical writing direction) */ - LCD_WriteReg(LCD_REG_3, 0x1008); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - /* Read bitmap data from SPI Flash and send them to LCD */ - for(i = 0; i < size; i++) - { - LCD_WriteRAM(BmpAddress[i]); - } - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); - /* Set GRAM write direction and BGR = 1 */ - /* I/D = 01 (Horizontal : increment, Vertical : decrement) */ - /* AM = 1 (address is updated in vertical writing direction) */ - LCD_WriteReg(LCD_REG_3, 0x1018); -} -#endif - -/** - * @brief Displays a full rectangle. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Height: rectangle height. - * @param Width: rectangle width. - * @retval None - */ -void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height) -{ - LCD_SetTextColor(TextColor); - - LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL); - LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL); - - LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL); - LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL); - - Width -= 2; - Height--; - Ypos--; - - LCD_SetTextColor(BackColor); - - while(Height--) - { - LCD_DrawLine(++Xpos, Ypos, Width, LCD_DIR_HORIZONTAL); - } - - LCD_SetTextColor(TextColor); -} - -/** - * @brief Displays a full circle. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Radius - * @retval None - */ -void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius) -{ - int32_t D; /* Decision Variable */ - uint32_t CurX;/* Current X Value */ - uint32_t CurY;/* Current Y Value */ - - D = 3 - (Radius << 1); - - CurX = 0; - CurY = Radius; - - LCD_SetTextColor(BackColor); - - while (CurX <= CurY) - { - if(CurY > 0) - { - LCD_DrawLine(Xpos - CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL); - LCD_DrawLine(Xpos + CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL); - } - - if(CurX > 0) - { - LCD_DrawLine(Xpos - CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL); - LCD_DrawLine(Xpos + CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL); - } - if (D < 0) - { - D += (CurX << 2) + 6; - } - else - { - D += ((CurX - CurY) << 2) + 10; - CurY--; - } - CurX++; - } - - LCD_SetTextColor(TextColor); - LCD_DrawCircle(Xpos, Ypos, Radius); -} - -/** - * @brief Displays an uni line (between two points). - * @param x1: specifies the point 1 x position. - * @param y1: specifies the point 1 y position. - * @param x2: specifies the point 2 x position. - * @param y2: specifies the point 2 y position. - * @retval None - */ -void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2) -{ - int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0, - yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0, - curpixel = 0; - - deltax = ABS(x2 - x1); /* The difference between the x's */ - deltay = ABS(y2 - y1); /* The difference between the y's */ - x = x1; /* Start x off at the first pixel */ - y = y1; /* Start y off at the first pixel */ - - if (x2 >= x1) /* The x-values are increasing */ - { - xinc1 = 1; - xinc2 = 1; - } - else /* The x-values are decreasing */ - { - xinc1 = -1; - xinc2 = -1; - } - - if (y2 >= y1) /* The y-values are increasing */ - { - yinc1 = 1; - yinc2 = 1; - } - else /* The y-values are decreasing */ - { - yinc1 = -1; - yinc2 = -1; - } - - if (deltax >= deltay) /* There is at least one x-value for every y-value */ - { - xinc1 = 0; /* Don't change the x when numerator >= denominator */ - yinc2 = 0; /* Don't change the y for every iteration */ - den = deltax; - num = deltax / 2; - numadd = deltay; - numpixels = deltax; /* There are more x-values than y-values */ - } - else /* There is at least one y-value for every x-value */ - { - xinc2 = 0; /* Don't change the x for every iteration */ - yinc1 = 0; /* Don't change the y when numerator >= denominator */ - den = deltay; - num = deltay / 2; - numadd = deltax; - numpixels = deltay; /* There are more y-values than x-values */ - } - - for (curpixel = 0; curpixel <= numpixels; curpixel++) - { - PutPixel(x, y); /* Draw the current pixel */ - num += numadd; /* Increase the numerator by the top of the fraction */ - if (num >= den) /* Check if numerator >= denominator */ - { - num -= den; /* Calculate the new numerator value */ - x += xinc1; /* Change the x as appropriate */ - y += yinc1; /* Change the y as appropriate */ - } - x += xinc2; /* Change the x as appropriate */ - y += yinc2; /* Change the y as appropriate */ - } -} - -/** - * @brief Displays an polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_PolyLine(pPoint Points, uint16_t PointCount) -{ - int16_t X = 0, Y = 0; - - if(PointCount < 2) - { - return; - } - - while(--PointCount) - { - X = Points->X; - Y = Points->Y; - Points++; - LCD_DrawUniLine(X, Y, Points->X, Points->Y); - } -} - -/** - * @brief Displays an relative polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @param Closed: specifies if the draw is closed or not. - * 1: closed, 0 : not closed. - * @retval None - */ -static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed) -{ - int16_t X = 0, Y = 0; - pPoint First = Points; - - if(PointCount < 2) - { - return; - } - X = Points->X; - Y = Points->Y; - while(--PointCount) - { - Points++; - LCD_DrawUniLine(X, Y, X + Points->X, Y + Points->Y); - X = X + Points->X; - Y = Y + Points->Y; - } - if(Closed) - { - LCD_DrawUniLine(First->X, First->Y, X, Y); - } -} - -/** - * @brief Displays a closed polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount) -{ - LCD_PolyLine(Points, PointCount); - LCD_DrawUniLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y); -} - -/** - * @brief Displays a relative polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount) -{ - LCD_PolyLineRelativeClosed(Points, PointCount, 0); -} - -/** - * @brief Displays a closed relative polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount) -{ - LCD_PolyLineRelativeClosed(Points, PointCount, 1); -} - - -/** - * @brief Displays a full polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_FillPolyLine(pPoint Points, uint16_t PointCount) -{ - /* public-domain code by Darel Rex Finley, 2007 */ - uint16_t nodes = 0, nodeX[MAX_POLY_CORNERS], pixelX = 0, pixelY = 0, i = 0, - j = 0, swap = 0; - uint16_t IMAGE_LEFT = 0, IMAGE_RIGHT = 0, IMAGE_TOP = 0, IMAGE_BOTTOM = 0; - - IMAGE_LEFT = IMAGE_RIGHT = Points->X; - IMAGE_TOP= IMAGE_BOTTOM = Points->Y; - - for(i = 1; i < PointCount; i++) - { - pixelX = POLY_X(i); - if(pixelX < IMAGE_LEFT) - { - IMAGE_LEFT = pixelX; - } - if(pixelX > IMAGE_RIGHT) - { - IMAGE_RIGHT = pixelX; - } - - pixelY = POLY_Y(i); - if(pixelY < IMAGE_TOP) - { - IMAGE_TOP = pixelY; - } - if(pixelY > IMAGE_BOTTOM) - { - IMAGE_BOTTOM = pixelY; - } - } - - LCD_SetTextColor(BackColor); - - /* Loop through the rows of the image. */ - for (pixelY = IMAGE_TOP; pixelY < IMAGE_BOTTOM; pixelY++) - { - /* Build a list of nodes. */ - nodes = 0; j = PointCount-1; - - for (i = 0; i < PointCount; i++) - { - if (POLY_Y(i)<(double) pixelY && POLY_Y(j)>=(double) pixelY || POLY_Y(j)<(double) pixelY && POLY_Y(i)>=(double) pixelY) - { - nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i))); - } - j = i; - } - - /* Sort the nodes, via a simple "Bubble" sort. */ - i = 0; - while (i < nodes-1) - { - if (nodeX[i]>nodeX[i+1]) - { - swap = nodeX[i]; - nodeX[i] = nodeX[i+1]; - nodeX[i+1] = swap; - if(i) - { - i--; - } - } - else - { - i++; - } - } - - /* Fill the pixels between node pairs. */ - for (i = 0; i < nodes; i+=2) - { - if(nodeX[i] >= IMAGE_RIGHT) - { - break; - } - if(nodeX[i+1] > IMAGE_LEFT) - { - if (nodeX[i] < IMAGE_LEFT) - { - nodeX[i]=IMAGE_LEFT; - } - if(nodeX[i+1] > IMAGE_RIGHT) - { - nodeX[i+1] = IMAGE_RIGHT; - } - LCD_SetTextColor(BackColor); - LCD_DrawLine(pixelY, nodeX[i+1], nodeX[i+1] - nodeX[i], LCD_DIR_HORIZONTAL); - LCD_SetTextColor(TextColor); - PutPixel(pixelY, nodeX[i+1]); - PutPixel(pixelY, nodeX[i]); - /* for (j=nodeX[i]; jCR1 &= 0xFFC7; - LCD_SPI->CR1 |= 0x0008; - /* Write 16-bit Index (then Read Reg) */ - LCD_WriteRegIndex(LCD_Reg); - /* Read 16-bit Reg */ - /* Reset LCD control line(/CS) and Send Start-Byte */ - LCD_nCS_StartByte(START_BYTE | LCD_READ_REG); - - for(i = 0; i < 5; i++) - { - SPI_I2S_SendData(LCD_SPI, 0xFF); - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET) - { - } - /* One byte of invalid dummy data read after the start byte */ - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET) - { - } - SPI_I2S_ReceiveData(LCD_SPI); - } - SPI_I2S_SendData(LCD_SPI, 0xFF); - /* Read upper byte */ - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET) - { - } - /* Read lower byte */ - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET) - { - } - tmp = SPI_I2S_ReceiveData(LCD_SPI); - - - SPI_I2S_SendData(LCD_SPI, 0xFF); - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET) - { - } - /* Read lower byte */ - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET) - { - } - tmp = ((tmp & 0xFF) << 8) | SPI_I2S_ReceiveData(LCD_SPI); - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); - /* LCD_SPI prescaler: 2 */ - LCD_SPI->CR1 &= 0xFFC7; - return tmp; -} - - -/** - * @brief Prepare to write to the LCD RAM. - * @param None - * @retval None - */ -void LCD_WriteRAM_Prepare(void) -{ - LCD_WriteRegIndex(LCD_REG_34); /* Select GRAM Reg */ - /* Reset LCD control line(/CS) and Send Start-Byte */ - LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG); -} - - -/** - * @brief Writes 1 word to the LCD RAM. - * @param RGB_Code: the pixel color in RGB mode (5-6-5). - * @retval None - */ -void LCD_WriteRAMWord(uint16_t RGB_Code) -{ - LCD_WriteRAM_Prepare(); - LCD_WriteRAM(RGB_Code); - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); -} - - -/** - * @brief Writes to the selected LCD register. - * @param LCD_Reg: address of the selected register. - * @param LCD_RegValue: value to write to the selected register. - * @retval None - */ -void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue) -{ - /* Write 16-bit Index (then Write Reg) */ - LCD_WriteRegIndex(LCD_Reg); - /* Write 16-bit Reg */ - /* Reset LCD control line(/CS) and Send Start-Byte */ - LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG); - SPI_I2S_SendData(LCD_SPI, LCD_RegValue>>8); - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET) - { - } - SPI_I2S_SendData(LCD_SPI, (LCD_RegValue & 0xFF)); - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET) - { - } - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); -} - - -/** - * @brief Writes to the LCD RAM. - * @param RGB_Code: the pixel color in RGB mode (5-6-5). - * @retval None - */ -void LCD_WriteRAM(uint16_t RGB_Code) -{ - SPI_I2S_SendData(LCD_SPI, RGB_Code >> 8); - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET) - { - } - SPI_I2S_SendData(LCD_SPI, RGB_Code & 0xFF); - while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET) - { - } -} - - -/** - * @brief Power on the LCD. - * @param None - * @retval None - */ -void LCD_PowerOn(void) -{ - /* Power On sequence ---------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ - _delay_(20); /* Dis-charge capacitor power voltage (200ms) */ - LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ - _delay_(5); /* delay 50 ms */ - LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ - LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ - _delay_(5); /* delay 50 ms */ - LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */ -} - -/** - * @brief Enables the Display. - * @param None - * @retval None - */ -void LCD_DisplayOn(void) -{ - /* Display On */ - LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */ - -} - -/** - * @brief Disables the Display. - * @param None - * @retval None - */ -void LCD_DisplayOff(void) -{ - /* Display Off */ - LCD_WriteReg(LCD_REG_7, 0x0); -} - -/** - * @brief Configures LCD control lines in Output Push-Pull mode. - * @param None - * @retval None - */ -void LCD_CtrlLinesConfig(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable GPIO clock */ - RCC_APB2PeriphClockCmd(LCD_NCS_GPIO_CLK, ENABLE); - - /* Configure NCS in Output Push-Pull mode */ - GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @brief Sets or reset LCD control lines. - * @param GPIOx: where x can be B or D to select the GPIO peripheral. - * @param CtrlPins: the Control line. This parameter can be: - * @arg LCD_NCS_PIN: Chip Select pin - * @param BitVal: specifies the value to be written to the selected bit. - * This parameter can be: - * @arg Bit_RESET: to clear the port pin - * @arg Bit_SET: to set the port pin - * @retval None - */ -void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal) -{ - /* Set or Reset the control line */ - GPIO_WriteBit(GPIOx, CtrlPins, BitVal); -} - - -/** - * @brief Configures the LCD_SPI interface. - * @param None - * @retval None - */ -void LCD_SPIConfig(void) -{ - SPI_InitTypeDef SPI_InitStructure; - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable GPIO clock */ - RCC_APB2PeriphClockCmd(LCD_SPI_SCK_GPIO_CLK | LCD_SPI_MISO_GPIO_CLK | LCD_SPI_MOSI_GPIO_CLK - | RCC_APB2Periph_AFIO, ENABLE); - GPIO_PinRemapConfig(GPIO_Remap_SPI3, ENABLE); - - /* Enable SPI clock */ - RCC_APB1PeriphClockCmd(LCD_SPI_CLK, ENABLE); - - /* Configure SPI pins: SCK, MISO and MOSI */ - GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN; - GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN; - GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); - - SPI_I2S_DeInit(LCD_SPI); - - /* SPI Config */ - SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; - SPI_InitStructure.SPI_Mode = SPI_Mode_Master; - SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; - SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; - SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; - SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; - SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; - SPI_Init(LCD_SPI, &SPI_InitStructure); - - /* SPI enable */ - SPI_Cmd(LCD_SPI, ENABLE); -} - -/** - * @brief Displays a pixel. - * @param x: pixel x. - * @param y: pixel y. - * @retval None - */ -static void PutPixel(int16_t x, int16_t y) -{ - if(x < 0 || x > 239 || y < 0 || y > 319) - { - return; - } - LCD_DrawLine(x, y, 1, LCD_DIR_HORIZONTAL); -} - -#ifndef USE_Delay -/** - * @brief Inserts a delay time. - * @param nCount: specifies the delay time length. - * @retval None - */ -static void delay(__IO uint32_t nCount) -{ - __IO uint32_t index = 0; - for(index = (100000 * nCount); index != 0; index--) - { - } -} -#endif /* USE_Delay*/ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_lcd.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_lcd.h deleted file mode 100644 index 5fb1eeefa..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_lcd.h +++ /dev/null @@ -1,379 +0,0 @@ -/** - ****************************************************************************** - * @file stm3210c_eval_lcd.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains all the functions prototypes for the lcd firmware driver. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM3210C_EVAL_LCD_H -#define __STM3210C_EVAL_LCD_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" -#include "../Common/fonts.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM3210C_EVAL - * @{ - */ - -/** @addtogroup STM3210C_EVAL_LCD - * @{ - */ - - -/** @defgroup STM3210C_EVAL_LCD_Exported_Types - * @{ - */ -typedef struct -{ - int16_t X; - int16_t Y; -} Point, * pPoint; -/** - * @} - */ - -/** @defgroup STM3210C_EVAL_LCD_Exported_Constants - * @{ - */ - -/** - * @brief Uncomment the line below if you want to use LCD_DrawBMP function to - * display a bitmap picture on the LCD. This function assumes that the bitmap - * file is loaded in the SPI Flash (mounted on STM3210C-EVAL board), however - * user can tailor it according to his application hardware requirement. - */ -/*#define USE_LCD_DrawBMP*/ - -/** - * @brief Uncomment the line below if you want to use user defined Delay function - * (for precise timing), otherwise default _delay_ function defined within - * this driver is used (less precise timing). - */ -/* #define USE_Delay */ - -#ifdef USE_Delay -#include "main.h" - - #define _delay_ Delay /* !< User can provide more timing precise _delay_ function - (with 10ms time base), using SysTick for example */ -#else - #define _delay_ delay /* !< Default _delay_ function with less precise timing */ -#endif - -/** - * @brief LCD Control pins - */ -#define LCD_NCS_PIN GPIO_Pin_2 -#define LCD_NCS_GPIO_PORT GPIOB -#define LCD_NCS_GPIO_CLK RCC_APB2Periph_GPIOB - -/** - * @brief LCD SPI Interface pins - */ -#define LCD_SPI SPI3 -#define LCD_SPI_CLK RCC_APB1Periph_SPI3 -#define LCD_SPI_SCK_PIN GPIO_Pin_10 -#define LCD_SPI_SCK_GPIO_PORT GPIOC -#define LCD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOC -#define LCD_SPI_MISO_PIN GPIO_Pin_11 -#define LCD_SPI_MISO_GPIO_PORT GPIOC -#define LCD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOC -#define LCD_SPI_MOSI_PIN GPIO_Pin_12 -#define LCD_SPI_MOSI_GPIO_PORT GPIOC -#define LCD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOC - -/** - * @brief LCD Registers - */ -#define LCD_REG_0 0x00 -#define LCD_REG_1 0x01 -#define LCD_REG_2 0x02 -#define LCD_REG_3 0x03 -#define LCD_REG_4 0x04 -#define LCD_REG_5 0x05 -#define LCD_REG_6 0x06 -#define LCD_REG_7 0x07 -#define LCD_REG_8 0x08 -#define LCD_REG_9 0x09 -#define LCD_REG_10 0x0A -#define LCD_REG_12 0x0C -#define LCD_REG_13 0x0D -#define LCD_REG_14 0x0E -#define LCD_REG_15 0x0F -#define LCD_REG_16 0x10 -#define LCD_REG_17 0x11 -#define LCD_REG_18 0x12 -#define LCD_REG_19 0x13 -#define LCD_REG_20 0x14 -#define LCD_REG_21 0x15 -#define LCD_REG_22 0x16 -#define LCD_REG_23 0x17 -#define LCD_REG_24 0x18 -#define LCD_REG_25 0x19 -#define LCD_REG_26 0x1A -#define LCD_REG_27 0x1B -#define LCD_REG_28 0x1C -#define LCD_REG_29 0x1D -#define LCD_REG_30 0x1E -#define LCD_REG_31 0x1F -#define LCD_REG_32 0x20 -#define LCD_REG_33 0x21 -#define LCD_REG_34 0x22 -#define LCD_REG_36 0x24 -#define LCD_REG_37 0x25 -#define LCD_REG_40 0x28 -#define LCD_REG_41 0x29 -#define LCD_REG_43 0x2B -#define LCD_REG_45 0x2D -#define LCD_REG_48 0x30 -#define LCD_REG_49 0x31 -#define LCD_REG_50 0x32 -#define LCD_REG_51 0x33 -#define LCD_REG_52 0x34 -#define LCD_REG_53 0x35 -#define LCD_REG_54 0x36 -#define LCD_REG_55 0x37 -#define LCD_REG_56 0x38 -#define LCD_REG_57 0x39 -#define LCD_REG_59 0x3B -#define LCD_REG_60 0x3C -#define LCD_REG_61 0x3D -#define LCD_REG_62 0x3E -#define LCD_REG_63 0x3F -#define LCD_REG_64 0x40 -#define LCD_REG_65 0x41 -#define LCD_REG_66 0x42 -#define LCD_REG_67 0x43 -#define LCD_REG_68 0x44 -#define LCD_REG_69 0x45 -#define LCD_REG_70 0x46 -#define LCD_REG_71 0x47 -#define LCD_REG_72 0x48 -#define LCD_REG_73 0x49 -#define LCD_REG_74 0x4A -#define LCD_REG_75 0x4B -#define LCD_REG_76 0x4C -#define LCD_REG_77 0x4D -#define LCD_REG_78 0x4E -#define LCD_REG_79 0x4F -#define LCD_REG_80 0x50 -#define LCD_REG_81 0x51 -#define LCD_REG_82 0x52 -#define LCD_REG_83 0x53 -#define LCD_REG_96 0x60 -#define LCD_REG_97 0x61 -#define LCD_REG_106 0x6A -#define LCD_REG_118 0x76 -#define LCD_REG_128 0x80 -#define LCD_REG_129 0x81 -#define LCD_REG_130 0x82 -#define LCD_REG_131 0x83 -#define LCD_REG_132 0x84 -#define LCD_REG_133 0x85 -#define LCD_REG_134 0x86 -#define LCD_REG_135 0x87 -#define LCD_REG_136 0x88 -#define LCD_REG_137 0x89 -#define LCD_REG_139 0x8B -#define LCD_REG_140 0x8C -#define LCD_REG_141 0x8D -#define LCD_REG_143 0x8F -#define LCD_REG_144 0x90 -#define LCD_REG_145 0x91 -#define LCD_REG_146 0x92 -#define LCD_REG_147 0x93 -#define LCD_REG_148 0x94 -#define LCD_REG_149 0x95 -#define LCD_REG_150 0x96 -#define LCD_REG_151 0x97 -#define LCD_REG_152 0x98 -#define LCD_REG_153 0x99 -#define LCD_REG_154 0x9A -#define LCD_REG_157 0x9D -#define LCD_REG_192 0xC0 -#define LCD_REG_193 0xC1 -#define LCD_REG_229 0xE5 - -/** - * @brief LCD color - */ -#define LCD_COLOR_WHITE 0xFFFF -#define LCD_COLOR_BLACK 0x0000 -#define LCD_COLOR_GREY 0xF7DE -#define LCD_COLOR_BLUE 0x001F -#define LCD_COLOR_BLUE2 0x051F -#define LCD_COLOR_RED 0xF800 -#define LCD_COLOR_MAGENTA 0xF81F -#define LCD_COLOR_GREEN 0x07E0 -#define LCD_COLOR_CYAN 0x7FFF -#define LCD_COLOR_YELLOW 0xFFE0 - -/** - * @brief LCD Lines depending on the chosen fonts. - */ -#define LCD_LINE_0 LINE(0) -#define LCD_LINE_1 LINE(1) -#define LCD_LINE_2 LINE(2) -#define LCD_LINE_3 LINE(3) -#define LCD_LINE_4 LINE(4) -#define LCD_LINE_5 LINE(5) -#define LCD_LINE_6 LINE(6) -#define LCD_LINE_7 LINE(7) -#define LCD_LINE_8 LINE(8) -#define LCD_LINE_9 LINE(9) -#define LCD_LINE_10 LINE(10) -#define LCD_LINE_11 LINE(11) -#define LCD_LINE_12 LINE(12) -#define LCD_LINE_13 LINE(13) -#define LCD_LINE_14 LINE(14) -#define LCD_LINE_15 LINE(15) -#define LCD_LINE_16 LINE(16) -#define LCD_LINE_17 LINE(17) -#define LCD_LINE_18 LINE(18) -#define LCD_LINE_19 LINE(19) -#define LCD_LINE_20 LINE(20) -#define LCD_LINE_21 LINE(21) -#define LCD_LINE_22 LINE(22) -#define LCD_LINE_23 LINE(23) -#define LCD_LINE_24 LINE(24) -#define LCD_LINE_25 LINE(25) -#define LCD_LINE_26 LINE(26) -#define LCD_LINE_27 LINE(27) -#define LCD_LINE_28 LINE(28) -#define LCD_LINE_29 LINE(29) - -/** - * @brief LCD default font - */ -#define LCD_DEFAULT_FONT Font16x24 - -/** - * @brief LCD Direction - */ -#define LCD_DIR_HORIZONTAL 0x0000 -#define LCD_DIR_VERTICAL 0x0001 - -/** - * @brief LCD Size (Width and Height) - */ -#define LCD_PIXEL_WIDTH 0x0140 -#define LCD_PIXEL_HEIGHT 0x00F0 - -/** - * @} - */ - -/** @defgroup STM3210C_EVAL_LCD_Exported_Macros - * @{ - */ -#define ASSEMBLE_RGB(R, G, B) ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3)) -/** - * @} - */ - -/** @defgroup STM3210C_EVAL_LCD_Exported_Functions - * @{ - */ -void LCD_DeInit(void); -void LCD_Setup(void); -void STM3210C_LCD_Init(void); -void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor); -void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor); -void LCD_SetTextColor(__IO uint16_t Color); -void LCD_SetBackColor(__IO uint16_t Color); -void LCD_ClearLine(uint8_t Line); -void LCD_Clear(uint16_t Color); -void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos); -void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c); -void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii); -void LCD_SetFont(sFONT *fonts); -sFONT *LCD_GetFont(void); -void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr); -void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width); -void LCD_WindowModeDisable(void); -void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction); -void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width); -void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius); -void LCD_DrawMonoPict(const uint32_t *Pict); -#ifdef USE_LCD_DrawBMP -//void LCD_DrawBMP(uint32_t BmpAddress); -void LCD_DrawBMP(const uint16_t *BmpAddress); -#endif -void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2); -void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height); -void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius); -void LCD_PolyLine(pPoint Points, uint16_t PointCount); -void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount); -void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount); -void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount); -void LCD_FillPolyLine(pPoint Points, uint16_t PointCount); - -void LCD_nCS_StartByte(uint8_t Start_Byte); -void LCD_WriteRegIndex(uint8_t LCD_Reg); -void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue); -void LCD_WriteRAM_Prepare(void); -void LCD_WriteRAMWord(uint16_t RGB_Code); -uint16_t LCD_ReadReg(uint8_t LCD_Reg); -void LCD_WriteRAM(uint16_t RGB_Code); -void LCD_PowerOn(void); -void LCD_DisplayOn(void); -void LCD_DisplayOff(void); - -void LCD_CtrlLinesConfig(void); -void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal); -void LCD_SPIConfig(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM3210C_EVAL_LCD_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c deleted file mode 100644 index 67e0bdbcb..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c +++ /dev/null @@ -1,667 +0,0 @@ -/** - ****************************************************************************** - * @file stm3210e_eval.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file provides - * - set of firmware functions to manage Leds, push-button and COM ports - * - low level initialization functions for SD card (on SDIO), SPI serial - * flash (sFLASH) and temperature sensor (LM75) - * available on STM3210E-EVAL evaluation board from STMicroelectronics. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm3210e_eval.h" -#include "stm32f10x_spi.h" -#include "stm32f10x_i2c.h" -#include "stm32f10x_sdio.h" -#include "stm32f10x_dma.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM3210E_EVAL - * @{ - */ - -/** @defgroup STM3210E_EVAL_LOW_LEVEL - * @brief This file provides firmware functions to manage Leds, push-buttons, - * COM ports, SD card on SDIO, serial flash (sFLASH), serial EEPROM (sEE) - * and temperature sensor (LM75) available on STM3210E-EVAL evaluation - * board from STMicroelectronics. - * @{ - */ - -/** @defgroup STM3210E_EVAL_LOW_LEVEL_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM3210E_EVAL_LOW_LEVEL_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM3210E_EVAL_LOW_LEVEL_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM3210E_EVAL_LOW_LEVEL_Private_Variables - * @{ - */ -GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT, - LED4_GPIO_PORT}; -const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN, - LED4_PIN}; -const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK, - LED4_GPIO_CLK}; - -GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT, - KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT, - LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT, - DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT}; - -const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN, - KEY_BUTTON_PIN, RIGHT_BUTTON_PIN, - LEFT_BUTTON_PIN, UP_BUTTON_PIN, - DOWN_BUTTON_PIN, SEL_BUTTON_PIN}; - -const uint32_t BUTTON_CLK[BUTTONn] = {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK, - KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK, - LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK, - DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK}; - -const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {WAKEUP_BUTTON_EXTI_LINE, - TAMPER_BUTTON_EXTI_LINE, - KEY_BUTTON_EXTI_LINE, - RIGHT_BUTTON_EXTI_LINE, - LEFT_BUTTON_EXTI_LINE, - UP_BUTTON_EXTI_LINE, - DOWN_BUTTON_EXTI_LINE, - SEL_BUTTON_EXTI_LINE}; - -const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PORT_SOURCE, - TAMPER_BUTTON_EXTI_PORT_SOURCE, - KEY_BUTTON_EXTI_PORT_SOURCE, - RIGHT_BUTTON_EXTI_PORT_SOURCE, - LEFT_BUTTON_EXTI_PORT_SOURCE, - UP_BUTTON_EXTI_PORT_SOURCE, - DOWN_BUTTON_EXTI_PORT_SOURCE, - SEL_BUTTON_EXTI_PORT_SOURCE}; - -const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PIN_SOURCE, - TAMPER_BUTTON_EXTI_PIN_SOURCE, - KEY_BUTTON_EXTI_PIN_SOURCE, - RIGHT_BUTTON_EXTI_PIN_SOURCE, - LEFT_BUTTON_EXTI_PIN_SOURCE, - UP_BUTTON_EXTI_PIN_SOURCE, - DOWN_BUTTON_EXTI_PIN_SOURCE, - SEL_BUTTON_EXTI_PIN_SOURCE}; - -const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn, - KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn, - LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn, - DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn}; - -USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2}; - -GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT}; - -GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT}; - -const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK}; - -const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK}; - -const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK}; - -const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN}; - -const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN}; - -/** - * @} - */ - - -/** @defgroup STM3210E_EVAL_LOW_LEVEL_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - - -/** @defgroup STM3210E_EVAL_LOW_LEVEL_Private_Functions - * @{ - */ - -/** - * @brief Configures LED GPIO. - * @param Led: Specifies the Led to be configured. - * This parameter can be one of following parameters: - * @arg LED1 - * @arg LED2 - * @arg LED3 - * @arg LED4 - * @retval None - */ -void STM_EVAL_LEDInit(Led_TypeDef Led) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable the GPIO_LED Clock */ - RCC_APB2PeriphClockCmd(GPIO_CLK[Led], ENABLE); - - /* Configure the GPIO_LED pin */ - GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led]; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - - GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure); -} - -/** - * @brief Turns selected LED On. - * @param Led: Specifies the Led to be set on. - * This parameter can be one of following parameters: - * @arg LED1 - * @arg LED2 - * @arg LED3 - * @arg LED4 - * @retval None - */ -void STM_EVAL_LEDOn(Led_TypeDef Led) -{ - GPIO_PORT[Led]->BSRR = GPIO_PIN[Led]; -} - -/** - * @brief Turns selected LED Off. - * @param Led: Specifies the Led to be set off. - * This parameter can be one of following parameters: - * @arg LED1 - * @arg LED2 - * @arg LED3 - * @arg LED4 - * @retval None - */ -void STM_EVAL_LEDOff(Led_TypeDef Led) -{ - GPIO_PORT[Led]->BRR = GPIO_PIN[Led]; -} - -/** - * @brief Toggles the selected LED. - * @param Led: Specifies the Led to be toggled. - * This parameter can be one of following parameters: - * @arg LED1 - * @arg LED2 - * @arg LED3 - * @arg LED4 - * @retval None - */ -void STM_EVAL_LEDToggle(Led_TypeDef Led) -{ - GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led]; -} - -/** - * @brief Configures Button GPIO and EXTI Line. - * @param Button: Specifies the Button to be configured. - * This parameter can be one of following parameters: - * @arg BUTTON_WAKEUP: Wakeup Push Button - * @arg BUTTON_TAMPER: Tamper Push Button - * @arg BUTTON_KEY: Key Push Button - * @arg BUTTON_RIGHT: Joystick Right Push Button - * @arg BUTTON_LEFT: Joystick Left Push Button - * @arg BUTTON_UP: Joystick Up Push Button - * @arg BUTTON_DOWN: Joystick Down Push Button - * @arg BUTTON_SEL: Joystick Sel Push Button - * @param Button_Mode: Specifies Button mode. - * This parameter can be one of following parameters: - * @arg BUTTON_MODE_GPIO: Button will be used as simple IO - * @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt - * generation capability - * @retval None - */ -void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode) -{ - GPIO_InitTypeDef GPIO_InitStructure; - EXTI_InitTypeDef EXTI_InitStructure; - NVIC_InitTypeDef NVIC_InitStructure; - - /* Enable the BUTTON Clock */ - RCC_APB2PeriphClockCmd(BUTTON_CLK[Button] | RCC_APB2Periph_AFIO, ENABLE); - - /* Configure Button pin as input floating */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button]; - GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure); - - - if (Button_Mode == BUTTON_MODE_EXTI) - { - /* Connect Button EXTI Line to Button GPIO Pin */ - GPIO_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]); - - /* Configure Button EXTI line */ - EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button]; - EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; - - if(Button != BUTTON_WAKEUP) - { - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; - } - else - { - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; - } - EXTI_InitStructure.EXTI_LineCmd = ENABLE; - EXTI_Init(&EXTI_InitStructure); - - /* Enable and set Button EXTI Interrupt to the lowest priority */ - NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button]; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - - NVIC_Init(&NVIC_InitStructure); - } -} - -/** - * @brief Returns the selected Button state. - * @param Button: Specifies the Button to be checked. - * This parameter can be one of following parameters: - * @arg BUTTON_WAKEUP: Wakeup Push Button - * @arg BUTTON_TAMPER: Tamper Push Button - * @arg BUTTON_KEY: Key Push Button - * @arg BUTTON_RIGHT: Joystick Right Push Button - * @arg BUTTON_LEFT: Joystick Left Push Button - * @arg BUTTON_UP: Joystick Up Push Button - * @arg BUTTON_DOWN: Joystick Down Push Button - * @arg BUTTON_SEL: Joystick Sel Push Button - * @retval The Button GPIO pin value. - */ -uint32_t STM_EVAL_PBGetState(Button_TypeDef Button) -{ - return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]); -} - -/** - * @brief Configures COM port. - * @param COM: Specifies the COM port to be configured. - * This parameter can be one of following parameters: - * @arg COM1 - * @arg COM2 - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that - * contains the configuration information for the specified USART peripheral. - * @retval None - */ -void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable GPIO clock */ - RCC_APB2PeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM] | RCC_APB2Periph_AFIO, ENABLE); - - /* Enable UART clock */ - if (COM == COM1) - { - RCC_APB2PeriphClockCmd(COM_USART_CLK[COM], ENABLE); - } - else - { - RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE); - } - - /* Configure USART Tx as alternate function push-pull */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM]; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure); - - /* Configure USART Rx as input floating */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM]; - GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure); - - /* USART configuration */ - USART_Init(COM_USART[COM], USART_InitStruct); - - /* Enable USART */ - USART_Cmd(COM_USART[COM], ENABLE); -} - -/** - * @brief DeInitializes the SDIO interface. - * @param None - * @retval None - */ -void SD_LowLevel_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< Disable SDIO Clock */ - SDIO_ClockCmd(DISABLE); - - /*!< Set Power State to OFF */ - SDIO_SetPowerState(SDIO_PowerState_OFF); - - /*!< DeInitializes the SDIO peripheral */ - SDIO_DeInit(); - - /*!< Disable the SDIO AHB Clock */ - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_SDIO, DISABLE); - - /*!< Configure PC.08, PC.09, PC.10, PC.11, PC.12 pin: D0, D1, D2, D3, CLK pin */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(GPIOC, &GPIO_InitStructure); - - /*!< Configure PD.02 CMD line */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; - GPIO_Init(GPIOD, &GPIO_InitStructure); -} - -/** - * @brief Initializes the SD Card and put it into StandBy State (Ready for - * data transfer). - * @param None - * @retval None - */ -void SD_LowLevel_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< GPIOC and GPIOD Periph clock enable */ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD | SD_DETECT_GPIO_CLK, ENABLE); - - /*!< Configure PC.08, PC.09, PC.10, PC.11, PC.12 pin: D0, D1, D2, D3, CLK pin */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOC, &GPIO_InitStructure); - - /*!< Configure PD.02 CMD line */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */ - GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure); - - /*!< Enable the SDIO AHB Clock */ - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_SDIO, ENABLE); - - /*!< Enable the DMA2 Clock */ - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE); -} - -/** - * @brief Configures the DMA2 Channel4 for SDIO Tx request. - * @param BufferSRC: pointer to the source buffer - * @param BufferSize: buffer size - * @retval None - */ -void SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize) -{ - - DMA_InitTypeDef DMA_InitStructure; - - DMA_ClearFlag(DMA2_FLAG_TC4 | DMA2_FLAG_TE4 | DMA2_FLAG_HT4 | DMA2_FLAG_GL4); - - /*!< DMA2 Channel4 disable */ - DMA_Cmd(DMA2_Channel4, DISABLE); - - /*!< DMA2 Channel4 Config */ - DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SDIO_FIFO_ADDRESS; - DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)BufferSRC; - DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST; - DMA_InitStructure.DMA_BufferSize = BufferSize / 4; - DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; - DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; - DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; - DMA_InitStructure.DMA_Priority = DMA_Priority_High; - DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; - DMA_Init(DMA2_Channel4, &DMA_InitStructure); - - /*!< DMA2 Channel4 enable */ - DMA_Cmd(DMA2_Channel4, ENABLE); -} - -/** - * @brief Configures the DMA2 Channel4 for SDIO Rx request. - * @param BufferDST: pointer to the destination buffer - * @param BufferSize: buffer size - * @retval None - */ -void SD_LowLevel_DMA_RxConfig(uint32_t *BufferDST, uint32_t BufferSize) -{ - DMA_InitTypeDef DMA_InitStructure; - - DMA_ClearFlag(DMA2_FLAG_TC4 | DMA2_FLAG_TE4 | DMA2_FLAG_HT4 | DMA2_FLAG_GL4); - - /*!< DMA2 Channel4 disable */ - DMA_Cmd(DMA2_Channel4, DISABLE); - - /*!< DMA2 Channel4 Config */ - DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SDIO_FIFO_ADDRESS; - DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)BufferDST; - DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; - DMA_InitStructure.DMA_BufferSize = BufferSize / 4; - DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; - DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; - DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; - DMA_InitStructure.DMA_Priority = DMA_Priority_High; - DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; - DMA_Init(DMA2_Channel4, &DMA_InitStructure); - - /*!< DMA2 Channel4 enable */ - DMA_Cmd(DMA2_Channel4, ENABLE); -} - -/** - * @brief Returns the DMA End Of Transfer Status. - * @param None - * @retval DMA SDIO Channel Status. - */ -uint32_t SD_DMAEndOfTransferStatus(void) -{ - return (uint32_t)DMA_GetFlagStatus(DMA2_FLAG_TC4); -} - -/** - * @brief DeInitializes the peripherals used by the SPI FLASH driver. - * @param None - * @retval None - */ -void sFLASH_LowLevel_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< Disable the sFLASH_SPI */ - SPI_Cmd(sFLASH_SPI, DISABLE); - - /*!< DeInitializes the sFLASH_SPI */ - SPI_I2S_DeInit(sFLASH_SPI); - - /*!< sFLASH_SPI Periph clock disable */ - RCC_APB2PeriphClockCmd(sFLASH_SPI_CLK, DISABLE); - - /*!< Configure sFLASH_SPI pins: SCK */ - GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sFLASH_SPI pins: MISO */ - GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN; - GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sFLASH_SPI pins: MOSI */ - GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN; - GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin */ - GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN; - GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @brief Initializes the peripherals used by the SPI FLASH driver. - * @param None - * @retval None - */ -void sFLASH_LowLevel_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO - and sFLASH_SPI_SCK_GPIO Periph clock enable */ - RCC_APB2PeriphClockCmd(sFLASH_CS_GPIO_CLK | sFLASH_SPI_MOSI_GPIO_CLK | sFLASH_SPI_MISO_GPIO_CLK | - sFLASH_SPI_SCK_GPIO_CLK, ENABLE); - - /*!< sFLASH_SPI Periph clock enable */ - RCC_APB2PeriphClockCmd(sFLASH_SPI_CLK, ENABLE); - - /*!< Configure sFLASH_SPI pins: SCK */ - GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sFLASH_SPI pins: MOSI */ - GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN; - GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sFLASH_SPI pins: MISO */ - GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin */ - GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @brief DeInitializes the LM75_I2C. - * @param None - * @retval None - */ -void LM75_LowLevel_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< Disable LM75_I2C */ - I2C_Cmd(LM75_I2C, DISABLE); - /*!< DeInitializes the LM75_I2C */ - I2C_DeInit(LM75_I2C); - - /*!< LM75_I2C Periph clock disable */ - RCC_APB1PeriphClockCmd(LM75_I2C_CLK, DISABLE); - - /*!< Configure LM75_I2C pins: SCL */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure LM75_I2C pins: SDA */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN; - GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure LM75_I2C pin: SMBUS ALERT */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN; - GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @brief Initializes the LM75_I2C.. - * @param None - * @retval None - */ -void LM75_LowLevel_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< LM75_I2C Periph clock enable */ - RCC_APB1PeriphClockCmd(LM75_I2C_CLK, ENABLE); - - /*!< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK - and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable */ - RCC_APB2PeriphClockCmd(LM75_I2C_SCL_GPIO_CLK | LM75_I2C_SDA_GPIO_CLK | - LM75_I2C_SMBUSALERT_GPIO_CLK, ENABLE); - - /*!< Configure LM75_I2C pins: SCL */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD; - GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure LM75_I2C pins: SDA */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN; - GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure LM75_I2C pin: SMBUS ALERT */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.h deleted file mode 100644 index eebdeba16..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.h +++ /dev/null @@ -1,342 +0,0 @@ -/** - ****************************************************************************** - * @file stm3210e_eval.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains definitions for STM3210E_EVAL's Leds, push-buttons - * COM ports, sFLASH (on SPI) and Temperature Sensor LM75 (on I2C) - * hardware resources. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM3210E_EVAL_H -#define __STM3210E_EVAL_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32_eval.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM3210E_EVAL - * @{ - */ - -/** @addtogroup STM3210E_EVAL_LOW_LEVEL - * @{ - */ - -/** @defgroup STM3210E_EVAL_LOW_LEVEL_Exported_Types - * @{ - */ -/** - * @} - */ - -/** @defgroup STM3210E_EVAL_LOW_LEVEL_Exported_Constants - * @{ - */ -/** @addtogroup STM3210E_EVAL_LOW_LEVEL_LED - * @{ - */ -#define LEDn 4 - -#define LED1_PIN GPIO_Pin_6 -#define LED1_GPIO_PORT GPIOF -#define LED1_GPIO_CLK RCC_APB2Periph_GPIOF - -#define LED2_PIN GPIO_Pin_7 -#define LED2_GPIO_PORT GPIOF -#define LED2_GPIO_CLK RCC_APB2Periph_GPIOF - -#define LED3_PIN GPIO_Pin_8 -#define LED3_GPIO_PORT GPIOF -#define LED3_GPIO_CLK RCC_APB2Periph_GPIOF - -#define LED4_PIN GPIO_Pin_9 -#define LED4_GPIO_PORT GPIOF -#define LED4_GPIO_CLK RCC_APB2Periph_GPIOF - -/** - * @} - */ - -/** @addtogroup STM3210E_EVAL_LOW_LEVEL_BUTTON - * @{ - */ -#define BUTTONn 8 - -/** - * @brief Wakeup push-button - */ -#define WAKEUP_BUTTON_PIN GPIO_Pin_0 -#define WAKEUP_BUTTON_GPIO_PORT GPIOA -#define WAKEUP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOA -#define WAKEUP_BUTTON_EXTI_LINE EXTI_Line0 -#define WAKEUP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOA -#define WAKEUP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource0 -#define WAKEUP_BUTTON_EXTI_IRQn EXTI0_IRQn -/** - * @brief Tamper push-button - */ -#define TAMPER_BUTTON_PIN GPIO_Pin_13 -#define TAMPER_BUTTON_GPIO_PORT GPIOC -#define TAMPER_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOC -#define TAMPER_BUTTON_EXTI_LINE EXTI_Line13 -#define TAMPER_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOC -#define TAMPER_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13 -#define TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn -/** - * @brief Key push-button - */ -#define KEY_BUTTON_PIN GPIO_Pin_8 -#define KEY_BUTTON_GPIO_PORT GPIOG -#define KEY_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG -#define KEY_BUTTON_EXTI_LINE EXTI_Line8 -#define KEY_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG -#define KEY_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource8 -#define KEY_BUTTON_EXTI_IRQn EXTI9_5_IRQn -/** - * @brief Joystick Right push-button - */ -#define RIGHT_BUTTON_PIN GPIO_Pin_13 -#define RIGHT_BUTTON_GPIO_PORT GPIOG -#define RIGHT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG -#define RIGHT_BUTTON_EXTI_LINE EXTI_Line13 -#define RIGHT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG -#define RIGHT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13 -#define RIGHT_BUTTON_EXTI_IRQn EXTI15_10_IRQn -/** - * @brief Joystick Left push-button - */ -#define LEFT_BUTTON_PIN GPIO_Pin_14 -#define LEFT_BUTTON_GPIO_PORT GPIOG -#define LEFT_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG -#define LEFT_BUTTON_EXTI_LINE EXTI_Line14 -#define LEFT_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG -#define LEFT_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource14 -#define LEFT_BUTTON_EXTI_IRQn EXTI15_10_IRQn -/** - * @brief Joystick Up push-button - */ -#define UP_BUTTON_PIN GPIO_Pin_15 -#define UP_BUTTON_GPIO_PORT GPIOG -#define UP_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG -#define UP_BUTTON_EXTI_LINE EXTI_Line15 -#define UP_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG -#define UP_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource15 -#define UP_BUTTON_EXTI_IRQn EXTI15_10_IRQn -/** - * @brief Joystick Down push-button - */ -#define DOWN_BUTTON_PIN GPIO_Pin_3 -#define DOWN_BUTTON_GPIO_PORT GPIOD -#define DOWN_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOD -#define DOWN_BUTTON_EXTI_LINE EXTI_Line3 -#define DOWN_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOD -#define DOWN_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource3 -#define DOWN_BUTTON_EXTI_IRQn EXTI3_IRQn -/** - * @brief Joystick Sel push-button - */ -#define SEL_BUTTON_PIN GPIO_Pin_7 -#define SEL_BUTTON_GPIO_PORT GPIOG -#define SEL_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOG -#define SEL_BUTTON_EXTI_LINE EXTI_Line7 -#define SEL_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOG -#define SEL_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource7 -#define SEL_BUTTON_EXTI_IRQn EXTI9_5_IRQn -/** - * @} - */ - -/** @addtogroup STM3210E_EVAL_LOW_LEVEL_COM - * @{ - */ -#define COMn 2 - -/** - * @brief Definition for COM port1, connected to USART1 - */ -#define EVAL_COM1 USART1 -#define EVAL_COM1_CLK RCC_APB2Periph_USART1 -#define EVAL_COM1_TX_PIN GPIO_Pin_9 -#define EVAL_COM1_TX_GPIO_PORT GPIOA -#define EVAL_COM1_TX_GPIO_CLK RCC_APB2Periph_GPIOA -#define EVAL_COM1_RX_PIN GPIO_Pin_10 -#define EVAL_COM1_RX_GPIO_PORT GPIOA -#define EVAL_COM1_RX_GPIO_CLK RCC_APB2Periph_GPIOA -#define EVAL_COM1_IRQn USART1_IRQn - -/** - * @brief Definition for COM port2, connected to USART2 - */ -#define EVAL_COM2 USART2 -#define EVAL_COM2_CLK RCC_APB1Periph_USART2 -#define EVAL_COM2_TX_PIN GPIO_Pin_2 -#define EVAL_COM2_TX_GPIO_PORT GPIOA -#define EVAL_COM2_TX_GPIO_CLK RCC_APB2Periph_GPIOA -#define EVAL_COM2_RX_PIN GPIO_Pin_3 -#define EVAL_COM2_RX_GPIO_PORT GPIOA -#define EVAL_COM2_RX_GPIO_CLK RCC_APB2Periph_GPIOA -#define EVAL_COM2_IRQn USART2_IRQn - -/** - * @} - */ - -/** @addtogroup STM3210E_EVAL_LOW_LEVEL_SD_FLASH - * @{ - */ -/** - * @brief SD FLASH SDIO Interface - */ - -#define SD_DETECT_PIN GPIO_Pin_11 /* PF.11 */ -#define SD_DETECT_GPIO_PORT GPIOF /* GPIOF */ -#define SD_DETECT_GPIO_CLK RCC_APB2Periph_GPIOF - -#define SDIO_FIFO_ADDRESS ((uint32_t)0x40018080) -/** - * @brief SDIO Intialization Frequency (400KHz max) - */ -#define SDIO_INIT_CLK_DIV ((uint8_t)0xB2) -/** - * @brief SDIO Data Transfer Frequency (25MHz max) - */ -#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x00) - -/** - * @} - */ - -/** @addtogroup STM3210E_EVAL_LOW_LEVEL_M25P_FLASH_SPI - * @{ - */ -/** - * @brief M25P FLASH SPI Interface pins - */ -#define sFLASH_SPI SPI1 -#define sFLASH_SPI_CLK RCC_APB2Periph_SPI1 -#define sFLASH_SPI_SCK_PIN GPIO_Pin_5 /* PA.05 */ -#define sFLASH_SPI_SCK_GPIO_PORT GPIOA /* GPIOA */ -#define sFLASH_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOA -#define sFLASH_SPI_MISO_PIN GPIO_Pin_6 /* PA.06 */ -#define sFLASH_SPI_MISO_GPIO_PORT GPIOA /* GPIOA */ -#define sFLASH_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOA -#define sFLASH_SPI_MOSI_PIN GPIO_Pin_7 /* PA.07 */ -#define sFLASH_SPI_MOSI_GPIO_PORT GPIOA /* GPIOA */ -#define sFLASH_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOA -#define sFLASH_CS_PIN GPIO_Pin_2 /* PB.02 */ -#define sFLASH_CS_GPIO_PORT GPIOB /* GPIOB */ -#define sFLASH_CS_GPIO_CLK RCC_APB2Periph_GPIOB - -/** - * @} - */ - -/** @addtogroup STM3210E_EVAL_LOW_LEVEL_TSENSOR_I2C - * @{ - */ -/** - * @brief LM75 Temperature Sensor I2C Interface pins - */ -#define LM75_I2C I2C1 -#define LM75_I2C_CLK RCC_APB1Periph_I2C1 -#define LM75_I2C_SCL_PIN GPIO_Pin_6 /* PB.06 */ -#define LM75_I2C_SCL_GPIO_PORT GPIOB /* GPIOB */ -#define LM75_I2C_SCL_GPIO_CLK RCC_APB2Periph_GPIOB -#define LM75_I2C_SDA_PIN GPIO_Pin_7 /* PB.07 */ -#define LM75_I2C_SDA_GPIO_PORT GPIOB /* GPIOB */ -#define LM75_I2C_SDA_GPIO_CLK RCC_APB2Periph_GPIOB -#define LM75_I2C_SMBUSALERT_PIN GPIO_Pin_5 /* PB.05 */ -#define LM75_I2C_SMBUSALERT_GPIO_PORT GPIOB /* GPIOB */ -#define LM75_I2C_SMBUSALERT_GPIO_CLK RCC_APB2Periph_GPIOB -#define LM75_I2C_DR ((uint32_t)0x40005410) - -#define LM75_DMA_CLK RCC_AHBPeriph_DMA1 -#define LM75_DMA_TX_CHANNEL DMA1_Channel6 -#define LM75_DMA_RX_CHANNEL DMA1_Channel7 -#define LM75_DMA_TX_TCFLAG DMA1_FLAG_TC6 -#define LM75_DMA_RX_TCFLAG DMA1_FLAG_TC7 -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup STM3210E_EVAL_LOW_LEVEL_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup STM3210E_EVAL_LOW_LEVEL_Exported_Functions - * @{ - */ -void STM_EVAL_LEDInit(Led_TypeDef Led); -void STM_EVAL_LEDOn(Led_TypeDef Led); -void STM_EVAL_LEDOff(Led_TypeDef Led); -void STM_EVAL_LEDToggle(Led_TypeDef Led); -void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode); -uint32_t STM_EVAL_PBGetState(Button_TypeDef Button); -void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct); -void SD_LowLevel_DeInit(void); -void SD_LowLevel_Init(void); -void SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize); -void SD_LowLevel_DMA_RxConfig(uint32_t *BufferDST, uint32_t BufferSize); -uint32_t SD_DMAEndOfTransferStatus(void); -void sFLASH_LowLevel_DeInit(void); -void sFLASH_LowLevel_Init(void); -void LM75_LowLevel_DeInit(void); -void LM75_LowLevel_Init(void); -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __STM3210E_EVAL_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nand.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nand.c deleted file mode 100644 index 1f0a78e5b..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nand.c +++ /dev/null @@ -1,546 +0,0 @@ -/** - ****************************************************************************** - * @file stm3210e_eval_fsmc_nand.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file provides a set of functions needed to drive the - * NAND512W3A2 memory mounted on STM3210E-EVAL board. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm3210e_eval_fsmc_nand.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM3210E_EVAL - * @{ - */ - -/** @addtogroup STM3210E_EVAL_FSMC_NAND - * @brief This file provides a set of functions needed to drive the - * NAND512W3A2 memory mounted on STM3210E-EVAL board. - * @{ - */ - -/** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Defines - * @{ - */ -/** - * @brief FSMC Bank 2 - */ -#define FSMC_Bank_NAND FSMC_Bank2_NAND -#define Bank_NAND_ADDR Bank2_NAND_ADDR -#define Bank2_NAND_ADDR ((uint32_t)0x70000000) -/** - * @} - */ - -/** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Macros - * @{ - */ -#define ROW_ADDRESS (Address.Page + (Address.Block + (Address.Zone * NAND_ZONE_SIZE)) * NAND_BLOCK_SIZE) -/** - * @} - */ - - -/** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Variables - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Function_Prototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Functions - * @{ - */ - -/** - * @brief Configures the FSMC and GPIOs to interface with the NAND memory. - * This function must be called before any write/read operation on the - * NAND. - * @param None - * @retval None - */ -void NAND_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - FSMC_NANDInitTypeDef FSMC_NANDInitStructure; - FSMC_NAND_PCCARDTimingInitTypeDef p; - - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | - RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE); - -/*-- GPIO Configuration ------------------------------------------------------*/ -/*!< CLE, ALE, D0->D3, NOE, NWE and NCE2 NAND pin configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_14 | GPIO_Pin_15 | - GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | - GPIO_Pin_7; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - - GPIO_Init(GPIOD, &GPIO_InitStructure); - -/*!< D4->D7 NAND pin configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10; - - GPIO_Init(GPIOE, &GPIO_InitStructure); - - -/*!< NWAIT NAND pin configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - - GPIO_Init(GPIOD, &GPIO_InitStructure); - -/*!< INT2 NAND pin configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; - GPIO_Init(GPIOG, &GPIO_InitStructure); - - /*-- FSMC Configuration ------------------------------------------------------*/ - p.FSMC_SetupTime = 0x0; - p.FSMC_WaitSetupTime = 0x2; - p.FSMC_HoldSetupTime = 0x1; - p.FSMC_HiZSetupTime = 0x0; - - FSMC_NANDInitStructure.FSMC_Bank = FSMC_Bank2_NAND; - FSMC_NANDInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Enable; - FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NANDInitStructure.FSMC_ECC = FSMC_ECC_Enable; - FSMC_NANDInitStructure.FSMC_ECCPageSize = FSMC_ECCPageSize_512Bytes; - FSMC_NANDInitStructure.FSMC_TCLRSetupTime = 0x00; - FSMC_NANDInitStructure.FSMC_TARSetupTime = 0x00; - FSMC_NANDInitStructure.FSMC_CommonSpaceTimingStruct = &p; - FSMC_NANDInitStructure.FSMC_AttributeSpaceTimingStruct = &p; - - FSMC_NANDInit(&FSMC_NANDInitStructure); - - /*!< FSMC NAND Bank Cmd Test */ - FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE); -} - -/** - * @brief Reads NAND memory's ID. - * @param NAND_ID: pointer to a NAND_IDTypeDef structure which will hold - * the Manufacturer and Device ID. - * @retval None - */ -void NAND_ReadID(NAND_IDTypeDef* NAND_ID) -{ - uint32_t data = 0; - - /*!< Send Command to the command area */ - *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = 0x90; - *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00; - - /*!< Sequence to read ID from NAND flash */ - data = *(__IO uint32_t *)(Bank_NAND_ADDR | DATA_AREA); - - NAND_ID->Maker_ID = ADDR_1st_CYCLE (data); - NAND_ID->Device_ID = ADDR_2nd_CYCLE (data); - NAND_ID->Third_ID = ADDR_3rd_CYCLE (data); - NAND_ID->Fourth_ID = ADDR_4th_CYCLE (data); -} - -/** - * @brief This routine is for writing one or several 512 Bytes Page size. - * @param pBuffer: pointer on the Buffer containing data to be written - * @param Address: First page address - * @param NumPageToWrite: Number of page to write - * @retval New status of the NAND operation. This parameter can be: - * - NAND_TIMEOUT_ERROR: when the previous operation generate - * a Timeout error - * - NAND_READY: when memory is ready for the next operation - * And the new status of the increment address operation. It can be: - * - NAND_VALID_ADDRESS: When the new address is valid address - * - NAND_INVALID_ADDRESS: When the new address is invalid address - */ -uint32_t NAND_WriteSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToWrite) -{ - uint32_t index = 0x00, numpagewritten = 0x00, addressstatus = NAND_VALID_ADDRESS; - uint32_t status = NAND_READY, size = 0x00; - - while((NumPageToWrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY)) - { - /*!< Page write command and address */ - *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A; - *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0; - - *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00; - *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS); - *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS); - *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS); - - /*!< Calculate the size */ - size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpagewritten); - - /*!< Write data */ - for(; index < size; index++) - { - *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index]; - } - - *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1; - - /*!< Check status for successful operation */ - status = NAND_GetStatus(); - - if(status == NAND_READY) - { - numpagewritten++; - - NumPageToWrite--; - - /*!< Calculate Next small page Address */ - addressstatus = NAND_AddressIncrement(&Address); - } - } - - return (status | addressstatus); -} - -/** - * @brief This routine is for sequential read from one or several 512 Bytes Page size. - * @param pBuffer: pointer on the Buffer to fill - * @param Address: First page address - * @param NumPageToRead: Number of page to read - * @retval New status of the NAND operation. This parameter can be: - * - NAND_TIMEOUT_ERROR: when the previous operation generate - * a Timeout error - * - NAND_READY: when memory is ready for the next operation - * And the new status of the increment address operation. It can be: - * - NAND_VALID_ADDRESS: When the new address is valid address - * - NAND_INVALID_ADDRESS: When the new address is invalid address - */ -uint32_t NAND_ReadSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToRead) -{ - uint32_t index = 0x00, numpageread = 0x00, addressstatus = NAND_VALID_ADDRESS; - uint32_t status = NAND_READY, size = 0x00; - - while((NumPageToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS)) - { - /*!< Page Read command and page address */ - *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A; - - *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00; - *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS); - *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS); - *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS); - - /*!< Calculate the size */ - size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpageread); - - /*!< Get Data into Buffer */ - for(; index < size; index++) - { - pBuffer[index]= *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA); - } - - numpageread++; - - NumPageToRead--; - - /*!< Calculate page address */ - addressstatus = NAND_AddressIncrement(&Address); - } - - status = NAND_GetStatus(); - - return (status | addressstatus); -} - -/** - * @brief This routine write the spare area information for the specified - * pages addresses. - * @param pBuffer: pointer on the Buffer containing data to be written - * @param Address: First page address - * @param NumSpareAreaTowrite: Number of Spare Area to write - * @retval New status of the NAND operation. This parameter can be: - * - NAND_TIMEOUT_ERROR: when the previous operation generate - * a Timeout error - * - NAND_READY: when memory is ready for the next operation - * And the new status of the increment address operation. It can be: - * - NAND_VALID_ADDRESS: When the new address is valid address - * - NAND_INVALID_ADDRESS: When the new address is invalid address - */ -uint32_t NAND_WriteSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaTowrite) -{ - uint32_t index = 0x00, numsparesreawritten = 0x00, addressstatus = NAND_VALID_ADDRESS; - uint32_t status = NAND_READY, size = 0x00; - - while((NumSpareAreaTowrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY)) - { - /*!< Page write Spare area command and address */ - *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C; - *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0; - - *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00; - *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS); - *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS); - *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS); - - /*!< Calculate the size */ - size = NAND_SPARE_AREA_SIZE + (NAND_SPARE_AREA_SIZE * numsparesreawritten); - - /*!< Write the data */ - for(; index < size; index++) - { - *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index]; - } - - *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1; - - /*!< Check status for successful operation */ - status = NAND_GetStatus(); - - if(status == NAND_READY) - { - numsparesreawritten++; - - NumSpareAreaTowrite--; - - /*!< Calculate Next page Address */ - addressstatus = NAND_AddressIncrement(&Address); - } - } - - return (status | addressstatus); -} - -/** - * @brief This routine read the spare area information from the specified - * pages addresses. - * @param pBuffer: pointer on the Buffer to fill - * @param Address: First page address - * @param NumSpareAreaToRead: Number of Spare Area to read - * @retval New status of the NAND operation. This parameter can be: - * - NAND_TIMEOUT_ERROR: when the previous operation generate - * a Timeout error - * - NAND_READY: when memory is ready for the next operation - * And the new status of the increment address operation. It can be: - * - NAND_VALID_ADDRESS: When the new address is valid address - * - NAND_INVALID_ADDRESS: When the new address is invalid address - */ -uint32_t NAND_ReadSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaToRead) -{ - uint32_t numsparearearead = 0x00, index = 0x00, addressstatus = NAND_VALID_ADDRESS; - uint32_t status = NAND_READY, size = 0x00; - - while((NumSpareAreaToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS)) - { - /*!< Page Read command and page address */ - *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C; - - *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00; - *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS); - *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS); - *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS); - - /*!< Data Read */ - size = NAND_SPARE_AREA_SIZE + (NAND_SPARE_AREA_SIZE * numsparearearead); - - /*!< Get Data into Buffer */ - for ( ;index < size; index++) - { - pBuffer[index] = *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA); - } - - numsparearearead++; - - NumSpareAreaToRead--; - - /*!< Calculate page address */ - addressstatus = NAND_AddressIncrement(&Address); - } - - status = NAND_GetStatus(); - - return (status | addressstatus); -} - -/** - * @brief This routine erase complete block from NAND FLASH - * @param Address: Any address into block to be erased - * @retval New status of the NAND operation. This parameter can be: - * - NAND_TIMEOUT_ERROR: when the previous operation generate - * a Timeout error - * - NAND_READY: when memory is ready for the next operation - */ -uint32_t NAND_EraseBlock(NAND_ADDRESS Address) -{ - *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE0; - - *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS); - *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS); - *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS); - - *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE1; - - return (NAND_GetStatus()); -} - -/** - * @brief This routine reset the NAND FLASH. - * @param None - * @retval NAND_READY - */ -uint32_t NAND_Reset(void) -{ - *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_RESET; - - return (NAND_READY); -} - -/** - * @brief Get the NAND operation status. - * @param None - * @retval New status of the NAND operation. This parameter can be: - * - NAND_TIMEOUT_ERROR: when the previous operation generate - * a Timeout error - * - NAND_READY: when memory is ready for the next operation - */ -uint32_t NAND_GetStatus(void) -{ - uint32_t timeout = 0x1000000, status = NAND_READY; - - status = NAND_ReadStatus(); - - /*!< Wait for a NAND operation to complete or a TIMEOUT to occur */ - while ((status != NAND_READY) &&( timeout != 0x00)) - { - status = NAND_ReadStatus(); - timeout --; - } - - if(timeout == 0x00) - { - status = NAND_TIMEOUT_ERROR; - } - - /*!< Return the operation status */ - return (status); -} - -/** - * @brief Reads the NAND memory status using the Read status command. - * @param None - * @retval The status of the NAND memory. This parameter can be: - * - NAND_BUSY: when memory is busy - * - NAND_READY: when memory is ready for the next operation - * - NAND_ERROR: when the previous operation gererates error - */ -uint32_t NAND_ReadStatus(void) -{ - uint32_t data = 0x00, status = NAND_BUSY; - - /*!< Read status operation ------------------------------------ */ - *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_STATUS; - data = *(__IO uint8_t *)(Bank_NAND_ADDR); - - if((data & NAND_ERROR) == NAND_ERROR) - { - status = NAND_ERROR; - } - else if((data & NAND_READY) == NAND_READY) - { - status = NAND_READY; - } - else - { - status = NAND_BUSY; - } - - return (status); -} - -/** - * @brief Increment the NAND memory address. - * @param Address: address to be incremented. - * @retval The new status of the increment address operation. It can be: - * - NAND_VALID_ADDRESS: When the new address is valid address - * - NAND_INVALID_ADDRESS: When the new address is invalid address - */ -uint32_t NAND_AddressIncrement(NAND_ADDRESS* Address) -{ - uint32_t status = NAND_VALID_ADDRESS; - - Address->Page++; - - if(Address->Page == NAND_BLOCK_SIZE) - { - Address->Page = 0; - Address->Block++; - - if(Address->Block == NAND_ZONE_SIZE) - { - Address->Block = 0; - Address->Zone++; - - if(Address->Zone == NAND_MAX_ZONE) - { - status = NAND_INVALID_ADDRESS; - } - } - } - - return (status); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nand.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nand.h deleted file mode 100644 index e9c51100f..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nand.h +++ /dev/null @@ -1,177 +0,0 @@ -/** - ****************************************************************************** - * @file stm3210e_eval_fsmc_nand.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains all the functions prototypes for the - * stm3210e_eval_fsmc_nand firmware driver. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM3210E_EVAL_FSMC_NAND_H -#define __STM3210E_EVAL_FSMC_NAND_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM3210E_EVAL - * @{ - */ - -/** @addtogroup STM3210E_EVAL_FSMC_NAND - * @{ - */ - -/** @defgroup STM3210E_EVAL_FSMC_NAND_Exported_Types - * @{ - */ -typedef struct -{ - uint8_t Maker_ID; - uint8_t Device_ID; - uint8_t Third_ID; - uint8_t Fourth_ID; -}NAND_IDTypeDef; - -typedef struct -{ - uint16_t Zone; - uint16_t Block; - uint16_t Page; -} NAND_ADDRESS; -/** - * @} - */ - -/** @defgroup STM3210E_EVAL_FSMC_NAND_Exported_Constants - * @{ - */ -/** - * @brief NAND Area definition for STM3210E-EVAL Board RevD - */ -#define CMD_AREA (uint32_t)(1<<16) /* A16 = CLE high */ -#define ADDR_AREA (uint32_t)(1<<17) /* A17 = ALE high */ - -#define DATA_AREA ((uint32_t)0x00000000) - -/** - * @brief FSMC NAND memory command - */ -#define NAND_CMD_AREA_A ((uint8_t)0x00) -#define NAND_CMD_AREA_B ((uint8_t)0x01) -#define NAND_CMD_AREA_C ((uint8_t)0x50) - -#define NAND_CMD_WRITE0 ((uint8_t)0x80) -#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) - -#define NAND_CMD_ERASE0 ((uint8_t)0x60) -#define NAND_CMD_ERASE1 ((uint8_t)0xD0) - -#define NAND_CMD_READID ((uint8_t)0x90) -#define NAND_CMD_STATUS ((uint8_t)0x70) -#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) -#define NAND_CMD_RESET ((uint8_t)0xFF) - -/** - * @brief NAND memory status - */ -#define NAND_VALID_ADDRESS ((uint32_t)0x00000100) -#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200) -#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400) -#define NAND_BUSY ((uint32_t)0x00000000) -#define NAND_ERROR ((uint32_t)0x00000001) -#define NAND_READY ((uint32_t)0x00000040) - -/** - * @brief FSMC NAND memory parameters - */ -#define NAND_PAGE_SIZE ((uint16_t)0x0200) /* 512 bytes per page w/o Spare Area */ -#define NAND_BLOCK_SIZE ((uint16_t)0x0020) /* 32x512 bytes pages per block */ -#define NAND_ZONE_SIZE ((uint16_t)0x0400) /* 1024 Block per zone */ -#define NAND_SPARE_AREA_SIZE ((uint16_t)0x0010) /* last 16 bytes as spare area */ -#define NAND_MAX_ZONE ((uint16_t)0x0004) /* 4 zones of 1024 block */ - -/** - * @brief FSMC NAND memory address computation - */ -#define ADDR_1st_CYCLE(ADDR) (uint8_t)((ADDR)& 0xFF) /* 1st addressing cycle */ -#define ADDR_2nd_CYCLE(ADDR) (uint8_t)(((ADDR)& 0xFF00) >> 8) /* 2nd addressing cycle */ -#define ADDR_3rd_CYCLE(ADDR) (uint8_t)(((ADDR)& 0xFF0000) >> 16) /* 3rd addressing cycle */ -#define ADDR_4th_CYCLE(ADDR) (uint8_t)(((ADDR)& 0xFF000000) >> 24) /* 4th addressing cycle */ -/** - * @} - */ - -/** @defgroup STM3210E_EVAL_FSMC_NAND_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup STM3210E_EVAL_FSMC_NAND_Exported_Functions - * @{ - */ -void NAND_Init(void); -void NAND_ReadID(NAND_IDTypeDef* NAND_ID); -uint32_t NAND_WriteSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToWrite); -uint32_t NAND_ReadSmallPage (uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToRead); -uint32_t NAND_WriteSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaTowrite); -uint32_t NAND_ReadSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaToRead); -uint32_t NAND_EraseBlock(NAND_ADDRESS Address); -uint32_t NAND_Reset(void); -uint32_t NAND_GetStatus(void); -uint32_t NAND_ReadStatus(void); -uint32_t NAND_AddressIncrement(NAND_ADDRESS* Address); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM3210E_EVAL_FSMC_NAND_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.c deleted file mode 100644 index 26472c26c..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.c +++ /dev/null @@ -1,479 +0,0 @@ -/** - ****************************************************************************** - * @file stm3210e_eval_fsmc_nor.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file provides a set of functions needed to drive the M29W128FL, - * M29W128GL and S29GL128P NOR memories mounted on STM3210E-EVAL board. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm3210e_eval_fsmc_nor.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM3210E_EVAL - * @{ - */ - -/** @addtogroup STM3210E_EVAL_FSMC_NOR - * @brief This file provides a set of functions needed to drive the M29W128FL, - * M29W128GL and S29GL128P NOR memories mounted on STM3210E-EVAL board. - * @{ - */ - -/** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Types - * @{ - */ -/** - * @} - */ - -/** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Defines - * @{ - */ -/** - * @brief FSMC Bank 1 NOR/SRAM2 - */ -#define Bank1_NOR2_ADDR ((uint32_t)0x64000000) - -/* Delay definition */ -#define BlockErase_Timeout ((uint32_t)0x00A00000) -#define ChipErase_Timeout ((uint32_t)0x30000000) -#define Program_Timeout ((uint32_t)0x00001400) -/** - * @} - */ - - -/** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Macros - * @{ - */ -#define ADDR_SHIFT(A) (Bank1_NOR2_ADDR + (2 * (A))) -#define NOR_WRITE(Address, Data) (*(__IO uint16_t *)(Address) = (Data)) -/** - * @} - */ - - -/** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Variables - * @{ - */ -/** - * @} - */ - - -/** @defgroupSTM3210E_EVAL_FSMC_NOR_Private_Function_Prototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Functions - * @{ - */ - -/** - * @brief Configures the FSMC and GPIOs to interface with the NOR memory. - * This function must be called before any write/read operation - * on the NOR. - * @param None - * @retval None - */ -void NOR_Init(void) -{ - FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; - FSMC_NORSRAMTimingInitTypeDef p; - GPIO_InitTypeDef GPIO_InitStructure; - - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | - RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE); - - /*-- GPIO Configuration ------------------------------------------------------*/ - /*!< NOR Data lines configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 | - GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | - GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | - GPIO_Pin_14 | GPIO_Pin_15; - GPIO_Init(GPIOE, &GPIO_InitStructure); - - /*!< NOR Address lines configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | - GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | - GPIO_Pin_14 | GPIO_Pin_15; - GPIO_Init(GPIOF, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | - GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5; - GPIO_Init(GPIOG, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6; - GPIO_Init(GPIOE, &GPIO_InitStructure); - - /*!< NOE and NWE configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - /*!< NE2 configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; - GPIO_Init(GPIOG, &GPIO_InitStructure); - - /*!< Configure PD6 for NOR memory Ready/Busy signal */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - /*-- FSMC Configuration ----------------------------------------------------*/ - p.FSMC_AddressSetupTime = 0x02; - p.FSMC_AddressHoldTime = 0x00; - p.FSMC_DataSetupTime = 0x05; - p.FSMC_BusTurnAroundDuration = 0x00; - p.FSMC_CLKDivision = 0x00; - p.FSMC_DataLatency = 0x00; - p.FSMC_AccessMode = FSMC_AccessMode_B; - - FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; - FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; - FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_NOR; - FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; - FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; - FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; - FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; - - FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); - - /*!< Enable FSMC Bank1_NOR Bank */ - FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE); -} - -/** - * @brief Reads NOR memory's Manufacturer and Device Code. - * @param NOR_ID: pointer to a NOR_IDTypeDef structure which will hold the - * Manufacturer and Device Code. - * @retval None - */ -void NOR_ReadID(NOR_IDTypeDef* NOR_ID) -{ - NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA); - NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055); - NOR_WRITE(ADDR_SHIFT(0x0555), 0x0090); - - NOR_ID->Manufacturer_Code = *(__IO uint16_t *) ADDR_SHIFT(0x0000); - NOR_ID->Device_Code1 = *(__IO uint16_t *) ADDR_SHIFT(0x0001); - NOR_ID->Device_Code2 = *(__IO uint16_t *) ADDR_SHIFT(0x000E); - NOR_ID->Device_Code3 = *(__IO uint16_t *) ADDR_SHIFT(0x000F); -} - -/** - * @brief Erases the specified Nor memory block. - * @param BlockAddr: address of the block to erase. - * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR - * or NOR_TIMEOUT - */ -NOR_Status NOR_EraseBlock(uint32_t BlockAddr) -{ - NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA); - NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055); - NOR_WRITE(ADDR_SHIFT(0x0555), 0x0080); - NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA); - NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055); - NOR_WRITE((Bank1_NOR2_ADDR + BlockAddr), 0x30); - - return (NOR_GetStatus(BlockErase_Timeout)); -} - -/** - * @brief Erases the entire chip. - * @param None - * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR - * or NOR_TIMEOUT - */ -NOR_Status NOR_EraseChip(void) -{ - NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA); - NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055); - NOR_WRITE(ADDR_SHIFT(0x0555), 0x0080); - NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA); - NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055); - NOR_WRITE(ADDR_SHIFT(0x0555), 0x0010); - - return (NOR_GetStatus(ChipErase_Timeout)); -} - -/** - * @brief Writes a half-word to the NOR memory. - * @param WriteAddr: NOR memory internal address to write to. - * @param Data: Data to write. - * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR - * or NOR_TIMEOUT - */ -NOR_Status NOR_WriteHalfWord(uint32_t WriteAddr, uint16_t Data) -{ - NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA); - NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055); - NOR_WRITE(ADDR_SHIFT(0x0555), 0x00A0); - NOR_WRITE((Bank1_NOR2_ADDR + WriteAddr), Data); - - return (NOR_GetStatus(Program_Timeout)); -} - -/** - * @brief Writes a half-word buffer to the FSMC NOR memory. - * @param pBuffer: pointer to buffer. - * @param WriteAddr: NOR memory internal address from which the data will be - * written. - * @param NumHalfwordToWrite: number of Half words to write. - * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR - * or NOR_TIMEOUT - */ -NOR_Status NOR_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite) -{ - NOR_Status status = NOR_ONGOING; - - do - { - /*!< Transfer data to the memory */ - status = NOR_WriteHalfWord(WriteAddr, *pBuffer++); - WriteAddr = WriteAddr + 2; - NumHalfwordToWrite--; - } - while((status == NOR_SUCCESS) && (NumHalfwordToWrite != 0)); - - return (status); -} - -/** - * @brief Writes a half-word buffer to the FSMC NOR memory. This function - * must be used only with S29GL128P NOR memory. - * @param pBuffer: pointer to buffer. - * @param WriteAddr: NOR memory internal address from which the data will be - * written. - * @param NumHalfwordToWrite: number of Half words to write. - * The maximum allowed value is 32 Half words (64 bytes). - * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR - * or NOR_TIMEOUT - */ -NOR_Status NOR_ProgramBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite) -{ - uint32_t lastloadedaddress = 0x00; - uint32_t currentaddress = 0x00; - uint32_t endaddress = 0x00; - - /*!< Initialize variables */ - currentaddress = WriteAddr; - endaddress = WriteAddr + NumHalfwordToWrite - 1; - lastloadedaddress = WriteAddr; - - /*!< Issue unlock command sequence */ - NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA); - - NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055); - - /*!< Write Write Buffer Load Command */ - NOR_WRITE(ADDR_SHIFT(WriteAddr), 0x0025); - NOR_WRITE(ADDR_SHIFT(WriteAddr), (NumHalfwordToWrite - 1)); - - /*!< Load Data into NOR Buffer */ - while(currentaddress <= endaddress) - { - /*!< Store last loaded address & data value (for polling) */ - lastloadedaddress = currentaddress; - - NOR_WRITE(ADDR_SHIFT(currentaddress), *pBuffer++); - currentaddress += 1; - } - - NOR_WRITE(ADDR_SHIFT(lastloadedaddress), 0x29); - - return(NOR_GetStatus(Program_Timeout)); -} - -/** - * @brief Reads a half-word from the NOR memory. - * @param ReadAddr: NOR memory internal address to read from. - * @retval Half-word read from the NOR memory - */ -uint16_t NOR_ReadHalfWord(uint32_t ReadAddr) -{ - NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA); - NOR_WRITE(ADDR_SHIFT(0x002AA), 0x0055); - NOR_WRITE((Bank1_NOR2_ADDR + ReadAddr), 0x00F0 ); - - return (*(__IO uint16_t *)((Bank1_NOR2_ADDR + ReadAddr))); -} - -/** - * @brief Reads a block of data from the FSMC NOR memory. - * @param pBuffer: pointer to the buffer that receives the data read from the - * NOR memory. - * @param ReadAddr: NOR memory internal address to read from. - * @param NumHalfwordToRead : number of Half word to read. - * @retval None - */ -void NOR_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead) -{ - NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA); - NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055); - NOR_WRITE((Bank1_NOR2_ADDR + ReadAddr), 0x00F0); - - for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /*!< while there is data to read */ - { - /*!< Read a Halfword from the NOR */ - *pBuffer++ = *(__IO uint16_t *)((Bank1_NOR2_ADDR + ReadAddr)); - ReadAddr = ReadAddr + 2; - } -} - -/** - * @brief Returns the NOR memory to Read mode. - * @param None - * @retval NOR_SUCCESS - */ -NOR_Status NOR_ReturnToReadMode(void) -{ - NOR_WRITE(Bank1_NOR2_ADDR, 0x00F0); - - return (NOR_SUCCESS); -} - -/** - * @brief Returns the NOR memory to Read mode and resets the errors in the NOR - * memory Status Register. - * @param None - * @retval NOR_SUCCESS - */ -NOR_Status NOR_Reset(void) -{ - NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA); - NOR_WRITE(ADDR_SHIFT(0x002AA), 0x0055); - NOR_WRITE(Bank1_NOR2_ADDR, 0x00F0); - - return (NOR_SUCCESS); -} - -/** - * @brief Returns the NOR operation status. - * @param Timeout: NOR progamming Timeout - * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR - * or NOR_TIMEOUT - */ -NOR_Status NOR_GetStatus(uint32_t Timeout) -{ - uint16_t val1 = 0x00, val2 = 0x00; - NOR_Status status = NOR_ONGOING; - uint32_t timeout = Timeout; - - /*!< Poll on NOR memory Ready/Busy signal ----------------------------------*/ - while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_6) != RESET) && (timeout > 0)) - { - timeout--; - } - - timeout = Timeout; - - while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_6) == RESET) && (timeout > 0)) - { - timeout--; - } - - /*!< Get the NOR memory operation status -----------------------------------*/ - while((Timeout != 0x00) && (status != NOR_SUCCESS)) - { - Timeout--; - - /*!< Read DQ6 and DQ5 */ - val1 = *(__IO uint16_t *)(Bank1_NOR2_ADDR); - val2 = *(__IO uint16_t *)(Bank1_NOR2_ADDR); - - /*!< If DQ6 did not toggle between the two reads then return NOR_Success */ - if((val1 & 0x0040) == (val2 & 0x0040)) - { - return NOR_SUCCESS; - } - - if((val1 & 0x0020) != 0x0020) - { - status = NOR_ONGOING; - } - - val1 = *(__IO uint16_t *)(Bank1_NOR2_ADDR); - val2 = *(__IO uint16_t *)(Bank1_NOR2_ADDR); - - if((val1 & 0x0040) == (val2 & 0x0040)) - { - return NOR_SUCCESS; - } - else if((val1 & 0x0020) == 0x0020) - { - return NOR_ERROR; - } - } - - if(Timeout == 0x00) - { - status = NOR_TIMEOUT; - } - - /*!< Return the operation status */ - return (status); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.h deleted file mode 100644 index c48dafaa4..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.h +++ /dev/null @@ -1,128 +0,0 @@ -/** - ****************************************************************************** - * @file stm3210e_eval_fsmc_nor.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains all the functions prototypes for the - * stm3210e_eval_fsmc_nor firmware driver. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM3210E_EVAL_FSMC_NOR_H -#define __STM3210E_EVAL_FSMC_NOR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM3210E_EVAL - * @{ - */ - -/** @addtogroup STM3210E_EVAL_FSMC_NOR - * @{ - */ - -/** @defgroup STM3210E_EVAL_FSMC_NOR_Exported_Types - * @{ - */ -typedef struct -{ - uint16_t Manufacturer_Code; - uint16_t Device_Code1; - uint16_t Device_Code2; - uint16_t Device_Code3; -}NOR_IDTypeDef; - -/* NOR Status */ -typedef enum -{ - NOR_SUCCESS = 0, - NOR_ONGOING, - NOR_ERROR, - NOR_TIMEOUT -}NOR_Status; -/** - * @} - */ - -/** @defgroup STM3210E_EVAL_FSMC_NOR_Exported_Constants - * @{ - */ -/** - * @} - */ - -/** @defgroup STM3210E_EVAL_FSMC_NOR_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup STM3210E_EVAL_FSMC_NOR_Exported_Functions - * @{ - */ -void NOR_Init(void); -void NOR_ReadID(NOR_IDTypeDef* NOR_ID); -NOR_Status NOR_EraseBlock(uint32_t BlockAddr); -NOR_Status NOR_EraseChip(void); -NOR_Status NOR_WriteHalfWord(uint32_t WriteAddr, uint16_t Data); -NOR_Status NOR_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite); -NOR_Status NOR_ProgramBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite); -uint16_t NOR_ReadHalfWord(uint32_t ReadAddr); -void NOR_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead); -NOR_Status NOR_ReturnToReadMode(void); -NOR_Status NOR_Reset(void); -NOR_Status NOR_GetStatus(uint32_t Timeout); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM3210E_EVAL_FSMC_NOR_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_sram.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_sram.c deleted file mode 100644 index f23331b2f..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_sram.c +++ /dev/null @@ -1,237 +0,0 @@ -/** - ****************************************************************************** - * @file stm3210e_eval_fsmc_sram.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file provides a set of functions needed to drive the - * IS61WV51216BLL SRAM memory mounted on STM3210E-EVAL board. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm3210e_eval_fsmc_sram.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM3210E_EVAL - * @{ - */ - -/** @addtogroup STM3210E_EVAL_FSMC_SRAM - * @brief This file provides a set of functions needed to drive the - * IS61WV51216BLL SRAM memory mounted on STM3210E-EVAL board. - * @{ - */ - -/** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Defines - * @{ - */ -/** - * @brief FSMC Bank 1 NOR/SRAM3 - */ -#define Bank1_SRAM3_ADDR ((uint32_t)0x68000000) -/** - * @} - */ - - -/** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Variables - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Function_Prototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Functions - * @{ - */ - -/** - * @brief Configures the FSMC and GPIOs to interface with the SRAM memory. - * This function must be called before any write/read operation - * on the SRAM. - * @param None - * @retval None - */ -void SRAM_Init(void) -{ - FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; - FSMC_NORSRAMTimingInitTypeDef p; - GPIO_InitTypeDef GPIO_InitStructure; - - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE | - RCC_APB2Periph_GPIOF, ENABLE); - -/*-- GPIO Configuration ------------------------------------------------------*/ - /*!< SRAM Data lines configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 | - GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | - GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | - GPIO_Pin_15; - GPIO_Init(GPIOE, &GPIO_InitStructure); - - /*!< SRAM Address lines configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | - GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | - GPIO_Pin_14 | GPIO_Pin_15; - GPIO_Init(GPIOF, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | - GPIO_Pin_4 | GPIO_Pin_5; - GPIO_Init(GPIOG, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - /*!< NOE and NWE configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 |GPIO_Pin_5; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - /*!< NE3 configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; - GPIO_Init(GPIOG, &GPIO_InitStructure); - - /*!< NBL0, NBL1 configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1; - GPIO_Init(GPIOE, &GPIO_InitStructure); - -/*-- FSMC Configuration ------------------------------------------------------*/ - p.FSMC_AddressSetupTime = 0; - p.FSMC_AddressHoldTime = 0; - p.FSMC_DataSetupTime = 1; - p.FSMC_BusTurnAroundDuration = 0; - p.FSMC_CLKDivision = 0; - p.FSMC_DataLatency = 0; - p.FSMC_AccessMode = FSMC_AccessMode_A; - - FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3; - FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; - FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; - FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; - FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; - FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; - FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; - - FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); - - /*!< Enable FSMC Bank1_SRAM Bank */ - FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE); -} - -/** - * @brief Writes a Half-word buffer to the FSMC SRAM memory. - * @param pBuffer : pointer to buffer. - * @param WriteAddr : SRAM memory internal address from which the data will be - * written. - * @param NumHalfwordToWrite : number of half-words to write. - * @retval None - */ -void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite) -{ - for(; NumHalfwordToWrite != 0; NumHalfwordToWrite--) /*!< while there is data to write */ - { - /*!< Transfer data to the memory */ - *(uint16_t *) (Bank1_SRAM3_ADDR + WriteAddr) = *pBuffer++; - - /*!< Increment the address*/ - WriteAddr += 2; - } -} - -/** - * @brief Reads a block of data from the FSMC SRAM memory. - * @param pBuffer : pointer to the buffer that receives the data read from the - * SRAM memory. - * @param ReadAddr : SRAM memory internal address to read from. - * @param NumHalfwordToRead : number of half-words to read. - * @retval None - */ -void SRAM_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead) -{ - for(; NumHalfwordToRead != 0; NumHalfwordToRead--) /*!< while there is data to read */ - { - /*!< Read a half-word from the memory */ - *pBuffer++ = *(__IO uint16_t*) (Bank1_SRAM3_ADDR + ReadAddr); - - /*!< Increment the address*/ - ReadAddr += 2; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_sram.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_sram.h deleted file mode 100644 index 4a491c75e..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_sram.h +++ /dev/null @@ -1,104 +0,0 @@ -/** - ****************************************************************************** - * @file stm3210e_eval_fsmc_sram.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains all the functions prototypes for the - * stm3210e_eval_fsmc_sram firmware driver. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM3210E_EVAL_FSMC_SRAM_H -#define __STM3210E_EVAL_FSMC_SRAM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM3210E_EVAL - * @{ - */ - -/** @addtogroup STM3210E_EVAL_FSMC_SRAM - * @{ - */ - -/** @defgroup STM3210E_EVAL_FSMC_SRAM_Exported_Types - * @{ - */ -/** - * @} - */ - -/** @defgroup STM3210E_EVAL_FSMC_SRAM_Exported_Constants - * @{ - */ -/** - * @} - */ - -/** @defgroup STM3210E_EVAL_FSMC_SRAM_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup STM3210E_EVAL_FSMC_SRAM_Exported_Functions - * @{ - */ - -void SRAM_Init(void); -void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite); -void SRAM_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM3210E_EVAL_FSMC_SRAM_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_lcd.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_lcd.c deleted file mode 100644 index a9213311b..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_lcd.c +++ /dev/null @@ -1,1329 +0,0 @@ -/** - ****************************************************************************** - * @file stm3210e_eval_lcd.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file includes the LCD driver for AM-240320L8TNQW00H - * (LCD_ILI9320) and AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal - * Display Module of STM3210E-EVAL board. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm3210e_eval_lcd.h" -#include "../Common/fonts.c" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM3210E_EVAL - * @{ - */ - -/** @defgroup STM3210E_EVAL_LCD - * @brief This file includes the LCD driver for AM-240320L8TNQW00H - * (LCD_ILI9320) and AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal - * Display Module of STM3210E-EVAL board. - * @{ - */ - -/** @defgroup STM3210E_EVAL_LCD_Private_TypesDefinitions - * @{ - */ -typedef struct -{ - __IO uint16_t LCD_REG; - __IO uint16_t LCD_RAM; -} LCD_TypeDef; -/** - * @} - */ - - -/** @defgroup STM3210E_EVAL_LCD_Private_Defines - * @{ - */ -/* Note: LCD /CS is CE4 - Bank 4 of NOR/SRAM Bank 1~4 */ -#define LCD_BASE ((uint32_t)(0x60000000 | 0x0C000000)) -#define LCD ((LCD_TypeDef *) LCD_BASE) -#define MAX_POLY_CORNERS 200 -#define POLY_Y(Z) ((int32_t)((Points + Z)->X)) -#define POLY_X(Z) ((int32_t)((Points + Z)->Y)) -/** - * @} - */ - -/** @defgroup STM3210E_EVAL_LCD_Private_Macros - * @{ - */ -#define ABS(X) ((X) > 0 ? (X) : -(X)) -/** - * @} - */ - -/** @defgroup STM3210E_EVAL_LCD_Private_Variables - * @{ - */ -static sFONT *LCD_Currentfonts; -/* Global variables to set the written text color */ -static __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF; - -/** - * @} - */ - - -/** @defgroup STM3210E_EVAL_LCD_Private_FunctionPrototypes - * @{ - */ -#ifndef USE_Delay -static void delay(vu32 nCount); -#endif /* USE_Delay*/ -static void PutPixel(int16_t x, int16_t y); -static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed); -/** - * @} - */ - - -/** @defgroup STM3210E_EVAL_LCD_Private_Functions - * @{ - */ - -/** - * @brief DeInitializes the LCD. - * @param None - * @retval None - */ -void LCD_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< LCD Display Off */ - LCD_DisplayOff(); - - /* BANK 4 (of NOR/SRAM Bank 1~4) is disabled */ - FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE); - - /*!< LCD_SPI DeInit */ - FSMC_NORSRAMDeInit(FSMC_Bank1_NORSRAM4); - - /* Set PD.00(D2), PD.01(D3), PD.04(NOE), PD.05(NWE), PD.08(D13), PD.09(D14), - PD.10(D15), PD.14(D0), PD.15(D1) as input floating */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | - GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 | - GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(GPIOD, &GPIO_InitStructure); - /* Set PE.07(D4), PE.08(D5), PE.09(D6), PE.10(D7), PE.11(D8), PE.12(D9), PE.13(D10), - PE.14(D11), PE.15(D12) as alternate function push pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | - GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | - GPIO_Pin_15; - GPIO_Init(GPIOE, &GPIO_InitStructure); - /* Set PF.00(A0 (RS)) as alternate function push pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; - GPIO_Init(GPIOF, &GPIO_InitStructure); - /* Set PG.12(NE4 (LCD/CS)) as alternate function push pull - CE3(LCD /CS) */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; - GPIO_Init(GPIOG, &GPIO_InitStructure); -} - -/** - * @brief Initializes the LCD. - * @param None - * @retval None - */ -void STM3210E_LCD_Init(void) -{ -/* Configure the LCD Control pins --------------------------------------------*/ - LCD_CtrlLinesConfig(); -/* Configure the FSMC Parallel interface -------------------------------------*/ - LCD_FSMCConfig(); - - _delay_(5); /* delay 50 ms */ - /* Check if the LCD is SPFD5408B Controller */ - if(LCD_ReadReg(0x00) == 0x5408) - { - /* Start Initial Sequence ------------------------------------------------*/ - LCD_WriteReg(LCD_REG_1, 0x0100); /* Set SS bit */ - LCD_WriteReg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ - LCD_WriteReg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ - LCD_WriteReg(LCD_REG_4, 0x0000); /* Resize register */ - LCD_WriteReg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ - LCD_WriteReg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ - LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */ - LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB 18-bit System interface setting */ - LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */ - LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity, no impact */ - /* Power On sequence -----------------------------------------------------*/ - LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ - _delay_(20); /* Dis-charge capacitor power voltage (200ms) */ - LCD_WriteReg(LCD_REG_17, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_16, 0x12B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_18, 0x01BD); /* External reference voltage= Vci */ - _delay_(5); - LCD_WriteReg(LCD_REG_19, 0x1400); /* VDV[4:0] for VCOM amplitude */ - LCD_WriteReg(LCD_REG_41, 0x000E); /* VCM[4:0] for VCOMH */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ - LCD_WriteReg(LCD_REG_33, 0x013F); /* GRAM Vertical Address */ - /* Adjust the Gamma Curve (SPFD5408B)-------------------------------------*/ - LCD_WriteReg(LCD_REG_48, 0x0b0d); - LCD_WriteReg(LCD_REG_49, 0x1923); - LCD_WriteReg(LCD_REG_50, 0x1c26); - LCD_WriteReg(LCD_REG_51, 0x261c); - LCD_WriteReg(LCD_REG_52, 0x2419); - LCD_WriteReg(LCD_REG_53, 0x0d0b); - LCD_WriteReg(LCD_REG_54, 0x1006); - LCD_WriteReg(LCD_REG_55, 0x0610); - LCD_WriteReg(LCD_REG_56, 0x0706); - LCD_WriteReg(LCD_REG_57, 0x0304); - LCD_WriteReg(LCD_REG_58, 0x0e05); - LCD_WriteReg(LCD_REG_59, 0x0e01); - LCD_WriteReg(LCD_REG_60, 0x010e); - LCD_WriteReg(LCD_REG_61, 0x050e); - LCD_WriteReg(LCD_REG_62, 0x0403); - LCD_WriteReg(LCD_REG_63, 0x0607); - /* Set GRAM area ---------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ - LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */ - LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ - LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */ - LCD_WriteReg(LCD_REG_96, 0xA700); /* Gate Scan Line */ - LCD_WriteReg(LCD_REG_97, 0x0001); /* NDL, VLE, REV */ - LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */ - /* Partial Display Control -----------------------------------------------*/ - LCD_WriteReg(LCD_REG_128, 0x0000); - LCD_WriteReg(LCD_REG_129, 0x0000); - LCD_WriteReg(LCD_REG_130, 0x0000); - LCD_WriteReg(LCD_REG_131, 0x0000); - LCD_WriteReg(LCD_REG_132, 0x0000); - LCD_WriteReg(LCD_REG_133, 0x0000); - /* Panel Control ---------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_144, 0x0010); - LCD_WriteReg(LCD_REG_146, 0x0000); - LCD_WriteReg(LCD_REG_147, 0x0003); - LCD_WriteReg(LCD_REG_149, 0x0110); - LCD_WriteReg(LCD_REG_151, 0x0000); - LCD_WriteReg(LCD_REG_152, 0x0000); - /* Set GRAM write direction and BGR=1 - I/D=01 (Horizontal : increment, Vertical : decrement) - AM=1 (address is updated in vertical writing direction) */ - LCD_WriteReg(LCD_REG_3, 0x1018); - LCD_WriteReg(LCD_REG_7, 0x0112); /* 262K color and display ON */ - LCD_SetFont(&LCD_DEFAULT_FONT); - return; - } -/* Start Initial Sequence ----------------------------------------------------*/ - LCD_WriteReg(LCD_REG_229,0x8000); /* Set the internal vcore voltage */ - LCD_WriteReg(LCD_REG_0, 0x0001); /* Start internal OSC. */ - LCD_WriteReg(LCD_REG_1, 0x0100); /* set SS and SM bit */ - LCD_WriteReg(LCD_REG_2, 0x0700); /* set 1 line inversion */ - LCD_WriteReg(LCD_REG_3, 0x1030); /* set GRAM write direction and BGR=1. */ - LCD_WriteReg(LCD_REG_4, 0x0000); /* Resize register */ - LCD_WriteReg(LCD_REG_8, 0x0202); /* set the back porch and front porch */ - LCD_WriteReg(LCD_REG_9, 0x0000); /* set non-display area refresh cycle ISC[3:0] */ - LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */ - LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */ - LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */ - LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */ -/* Power On sequence ---------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ - _delay_(20); /* Dis-charge capacitor power voltage (200ms) */ - LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ - LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ - LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */ -/* Adjust the Gamma Curve ----------------------------------------------------*/ - LCD_WriteReg(LCD_REG_48, 0x0006); - LCD_WriteReg(LCD_REG_49, 0x0101); - LCD_WriteReg(LCD_REG_50, 0x0003); - LCD_WriteReg(LCD_REG_53, 0x0106); - LCD_WriteReg(LCD_REG_54, 0x0b02); - LCD_WriteReg(LCD_REG_55, 0x0302); - LCD_WriteReg(LCD_REG_56, 0x0707); - LCD_WriteReg(LCD_REG_57, 0x0007); - LCD_WriteReg(LCD_REG_60, 0x0600); - LCD_WriteReg(LCD_REG_61, 0x020b); - -/* Set GRAM area -------------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ - LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */ - LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ - LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */ - LCD_WriteReg(LCD_REG_96, 0x2700); /* Gate Scan Line */ - LCD_WriteReg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ - LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */ -/* Partial Display Control ---------------------------------------------------*/ - LCD_WriteReg(LCD_REG_128, 0x0000); - LCD_WriteReg(LCD_REG_129, 0x0000); - LCD_WriteReg(LCD_REG_130, 0x0000); - LCD_WriteReg(LCD_REG_131, 0x0000); - LCD_WriteReg(LCD_REG_132, 0x0000); - LCD_WriteReg(LCD_REG_133, 0x0000); -/* Panel Control -------------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_144, 0x0010); - LCD_WriteReg(LCD_REG_146, 0x0000); - LCD_WriteReg(LCD_REG_147, 0x0003); - LCD_WriteReg(LCD_REG_149, 0x0110); - LCD_WriteReg(LCD_REG_151, 0x0000); - LCD_WriteReg(LCD_REG_152, 0x0000); - /* Set GRAM write direction and BGR = 1 */ - /* I/D=01 (Horizontal : increment, Vertical : decrement) */ - /* AM=1 (address is updated in vertical writing direction) */ - LCD_WriteReg(LCD_REG_3, 0x1018); - LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */ - LCD_SetFont(&LCD_DEFAULT_FONT); -} - -/** - * @brief Sets the LCD Text and Background colors. - * @param _TextColor: specifies the Text Color. - * @param _BackColor: specifies the Background Color. - * @retval None - */ -void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor) -{ - TextColor = _TextColor; - BackColor = _BackColor; -} - -/** - * @brief Gets the LCD Text and Background colors. - * @param _TextColor: pointer to the variable that will contain the Text - Color. - * @param _BackColor: pointer to the variable that will contain the Background - Color. - * @retval None - */ -void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor) -{ - *_TextColor = TextColor; *_BackColor = BackColor; -} - -/** - * @brief Sets the Text color. - * @param Color: specifies the Text color code RGB(5-6-5). - * @retval None - */ -void LCD_SetTextColor(__IO uint16_t Color) -{ - TextColor = Color; -} - - -/** - * @brief Sets the Background color. - * @param Color: specifies the Background color code RGB(5-6-5). - * @retval None - */ -void LCD_SetBackColor(__IO uint16_t Color) -{ - BackColor = Color; -} - -/** - * @brief Sets the Text Font. - * @param fonts: specifies the font to be used. - * @retval None - */ -void LCD_SetFont(sFONT *fonts) -{ - LCD_Currentfonts = fonts; -} - -/** - * @brief Gets the Text Font. - * @param None. - * @retval the used font. - */ -sFONT *LCD_GetFont(void) -{ - return LCD_Currentfonts; -} - -/** - * @brief Clears the selected line. - * @param Line: the Line to be cleared. - * This parameter can be one of the following values: - * @arg Linex: where x can be 0..n - * @retval None - */ -void LCD_ClearLine(uint8_t Line) -{ - uint16_t refcolumn = LCD_PIXEL_WIDTH - 1; - /* Send the string character by character on lCD */ - while (((refcolumn + 1)&0xFFFF) >= LCD_Currentfonts->Width) - { - /* Display one character on LCD */ - LCD_DisplayChar(Line, refcolumn, ' '); - /* Decrement the column position by 16 */ - refcolumn -= LCD_Currentfonts->Width; - } -} - - -/** - * @brief Clears the hole LCD. - * @param Color: the color of the background. - * @retval None - */ -void LCD_Clear(uint16_t Color) -{ - uint32_t index = 0; - - LCD_SetCursor(0x00, 0x013F); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - for(index = 0; index < 76800; index++) - { - LCD->LCD_RAM = Color; - } -} - - -/** - * @brief Sets the cursor position. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @retval None - */ -void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos) -{ - LCD_WriteReg(LCD_REG_32, Xpos); - LCD_WriteReg(LCD_REG_33, Ypos); -} - - -/** - * @brief Draws a character on LCD. - * @param Xpos: the Line where to display the character shape. - * @param Ypos: start column address. - * @param c: pointer to the character data. - * @retval None - */ -void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c) -{ - uint32_t index = 0, i = 0; - uint8_t Xaddress = 0; - - Xaddress = Xpos; - - LCD_SetCursor(Xaddress, Ypos); - - for(index = 0; index < LCD_Currentfonts->Height; index++) - { - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - for(i = 0; i < LCD_Currentfonts->Width; i++) - { - if((((c[index] & ((0x80 << ((LCD_Currentfonts->Width / 12 ) * 8 ) ) >> i)) == 0x00) &&(LCD_Currentfonts->Width <= 12))|| - (((c[index] & (0x1 << i)) == 0x00)&&(LCD_Currentfonts->Width > 12 ))) - - { - LCD_WriteRAM(BackColor); - } - else - { - LCD_WriteRAM(TextColor); - } - } - Xaddress++; - LCD_SetCursor(Xaddress, Ypos); - } -} - - -/** - * @brief Displays one character (16dots width, 24dots height). - * @param Line: the Line where to display the character shape . - * This parameter can be one of the following values: - * @arg Linex: where x can be 0..9 - * @param Column: start column address. - * @param Ascii: character ascii code, must be between 0x20 and 0x7E. - * @retval None - */ -void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii) -{ - Ascii -= 32; - LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]); -} - - -/** - * @brief Displays a maximum of 20 char on the LCD. - * @param Line: the Line where to display the character shape . - * This parameter can be one of the following values: - * @arg Linex: where x can be 0..9 - * @param *ptr: pointer to string to display on LCD. - * @retval None - */ -void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr) -{ - uint16_t refcolumn = LCD_PIXEL_WIDTH - 1; - - /* Send the string character by character on lCD */ - while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width)) - { - /* Display one character on LCD */ - LCD_DisplayChar(Line, refcolumn, *ptr); - /* Decrement the column position by 16 */ - refcolumn -= LCD_Currentfonts->Width; - /* Point on the next character */ - ptr++; - } -} - - -/** - * @brief Sets a display window - * @param Xpos: specifies the X buttom left position. - * @param Ypos: specifies the Y buttom left position. - * @param Height: display window height. - * @param Width: display window width. - * @retval None - */ -void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width) -{ - /* Horizontal GRAM Start Address */ - if(Xpos >= Height) - { - LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1)); - } - else - { - LCD_WriteReg(LCD_REG_80, 0); - } - /* Horizontal GRAM End Address */ - LCD_WriteReg(LCD_REG_81, Xpos); - /* Vertical GRAM Start Address */ - if(Ypos >= Width) - { - LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1)); - } - else - { - LCD_WriteReg(LCD_REG_82, 0); - } - /* Vertical GRAM End Address */ - LCD_WriteReg(LCD_REG_83, Ypos); - LCD_SetCursor(Xpos, Ypos); -} - - -/** - * @brief Disables LCD Window mode. - * @param None - * @retval None - */ -void LCD_WindowModeDisable(void) -{ - LCD_SetDisplayWindow(239, 0x13F, 240, 320); - LCD_WriteReg(LCD_REG_3, 0x1018); -} - - -/** - * @brief Displays a line. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Length: line length. - * @param Direction: line direction. - * This parameter can be one of the following values: Vertical or Horizontal. - * @retval None - */ -void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction) -{ - uint32_t i = 0; - - LCD_SetCursor(Xpos, Ypos); - if(Direction == LCD_DIR_HORIZONTAL) - { - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - for(i = 0; i < Length; i++) - { - LCD_WriteRAM(TextColor); - } - } - else - { - for(i = 0; i < Length; i++) - { - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - LCD_WriteRAM(TextColor); - Xpos++; - LCD_SetCursor(Xpos, Ypos); - } - } -} - - -/** - * @brief Displays a rectangle. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Height: display rectangle height. - * @param Width: display rectangle width. - * @retval None - */ -void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width) -{ - LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL); - LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL); - - LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL); - LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL); -} - - -/** - * @brief Displays a circle. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Radius - * @retval None - */ -void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius) -{ - int32_t D;/* Decision Variable */ - uint32_t CurX;/* Current X Value */ - uint32_t CurY;/* Current Y Value */ - - D = 3 - (Radius << 1); - CurX = 0; - CurY = Radius; - - while (CurX <= CurY) - { - LCD_SetCursor(Xpos + CurX, Ypos + CurY); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - LCD_WriteRAM(TextColor); - LCD_SetCursor(Xpos + CurX, Ypos - CurY); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - LCD_WriteRAM(TextColor); - LCD_SetCursor(Xpos - CurX, Ypos + CurY); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - LCD_WriteRAM(TextColor); - LCD_SetCursor(Xpos - CurX, Ypos - CurY); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - LCD_WriteRAM(TextColor); - LCD_SetCursor(Xpos + CurY, Ypos + CurX); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - LCD_WriteRAM(TextColor); - LCD_SetCursor(Xpos + CurY, Ypos - CurX); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - LCD_WriteRAM(TextColor); - LCD_SetCursor(Xpos - CurY, Ypos + CurX); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - LCD_WriteRAM(TextColor); - LCD_SetCursor(Xpos - CurY, Ypos - CurX); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - LCD_WriteRAM(TextColor); - if (D < 0) - { - D += (CurX << 2) + 6; - } - else - { - D += ((CurX - CurY) << 2) + 10; - CurY--; - } - CurX++; - } -} - - -/** - * @brief Displays a monocolor picture. - * @param Pict: pointer to the picture array. - * @retval None - */ -void LCD_DrawMonoPict(const uint32_t *Pict) -{ - uint32_t index = 0, i = 0; - LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1)); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - for(index = 0; index < 2400; index++) - { - for(i = 0; i < 32; i++) - { - if((Pict[index] & (1 << i)) == 0x00) - { - LCD_WriteRAM(BackColor); - } - else - { - LCD_WriteRAM(TextColor); - } - } - } -} - - -/** - * @brief Displays a bitmap picture loaded in the internal Flash. - * @param BmpAddress: Bmp picture address in the internal Flash. - * @retval None - */ -void LCD_WriteBMP(uint32_t BmpAddress) -{ - uint32_t index = 0, size = 0; - /* Read bitmap size */ - size = *(__IO uint16_t *) (BmpAddress + 2); - size |= (*(__IO uint16_t *) (BmpAddress + 4)) << 16; - /* Get bitmap data address offset */ - index = *(__IO uint16_t *) (BmpAddress + 10); - index |= (*(__IO uint16_t *) (BmpAddress + 12)) << 16; - size = (size - index)/2; - BmpAddress += index; - /* Set GRAM write direction and BGR = 1 */ - /* I/D=00 (Horizontal : decrement, Vertical : decrement) */ - /* AM=1 (address is updated in vertical writing direction) */ - LCD_WriteReg(LCD_REG_3, 0x1008); - - LCD_WriteRAM_Prepare(); - - for(index = 0; index < size; index++) - { - LCD_WriteRAM(*(__IO uint16_t *)BmpAddress); - BmpAddress += 2; - } - - /* Set GRAM write direction and BGR = 1 */ - /* I/D = 01 (Horizontal : increment, Vertical : decrement) */ - /* AM = 1 (address is updated in vertical writing direction) */ - LCD_WriteReg(LCD_REG_3, 0x1018); -} - -/** - * @brief Displays a full rectangle. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Height: rectangle height. - * @param Width: rectangle width. - * @retval None - */ -void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height) -{ - LCD_SetTextColor(TextColor); - - LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL); - LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL); - - LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL); - LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL); - - Width -= 2; - Height--; - Ypos--; - - LCD_SetTextColor(BackColor); - - while(Height--) - { - LCD_DrawLine(++Xpos, Ypos, Width, LCD_DIR_HORIZONTAL); - } - - LCD_SetTextColor(TextColor); -} - -/** - * @brief Displays a full circle. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Radius - * @retval None - */ -void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius) -{ - int32_t D; /* Decision Variable */ - uint32_t CurX;/* Current X Value */ - uint32_t CurY;/* Current Y Value */ - - D = 3 - (Radius << 1); - - CurX = 0; - CurY = Radius; - - LCD_SetTextColor(BackColor); - - while (CurX <= CurY) - { - if(CurY > 0) - { - LCD_DrawLine(Xpos - CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL); - LCD_DrawLine(Xpos + CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL); - } - - if(CurX > 0) - { - LCD_DrawLine(Xpos - CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL); - LCD_DrawLine(Xpos + CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL); - } - if (D < 0) - { - D += (CurX << 2) + 6; - } - else - { - D += ((CurX - CurY) << 2) + 10; - CurY--; - } - CurX++; - } - - LCD_SetTextColor(TextColor); - LCD_DrawCircle(Xpos, Ypos, Radius); -} - -/** - * @brief Displays an uni line (between two points). - * @param x1: specifies the point 1 x position. - * @param y1: specifies the point 1 y position. - * @param x2: specifies the point 2 x position. - * @param y2: specifies the point 2 y position. - * @retval None - */ -void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2) -{ - int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0, - yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0, - curpixel = 0; - - deltax = ABS(x2 - x1); /* The difference between the x's */ - deltay = ABS(y2 - y1); /* The difference between the y's */ - x = x1; /* Start x off at the first pixel */ - y = y1; /* Start y off at the first pixel */ - - if (x2 >= x1) /* The x-values are increasing */ - { - xinc1 = 1; - xinc2 = 1; - } - else /* The x-values are decreasing */ - { - xinc1 = -1; - xinc2 = -1; - } - - if (y2 >= y1) /* The y-values are increasing */ - { - yinc1 = 1; - yinc2 = 1; - } - else /* The y-values are decreasing */ - { - yinc1 = -1; - yinc2 = -1; - } - - if (deltax >= deltay) /* There is at least one x-value for every y-value */ - { - xinc1 = 0; /* Don't change the x when numerator >= denominator */ - yinc2 = 0; /* Don't change the y for every iteration */ - den = deltax; - num = deltax / 2; - numadd = deltay; - numpixels = deltax; /* There are more x-values than y-values */ - } - else /* There is at least one y-value for every x-value */ - { - xinc2 = 0; /* Don't change the x for every iteration */ - yinc1 = 0; /* Don't change the y when numerator >= denominator */ - den = deltay; - num = deltay / 2; - numadd = deltax; - numpixels = deltay; /* There are more y-values than x-values */ - } - - for (curpixel = 0; curpixel <= numpixels; curpixel++) - { - PutPixel(x, y); /* Draw the current pixel */ - num += numadd; /* Increase the numerator by the top of the fraction */ - if (num >= den) /* Check if numerator >= denominator */ - { - num -= den; /* Calculate the new numerator value */ - x += xinc1; /* Change the x as appropriate */ - y += yinc1; /* Change the y as appropriate */ - } - x += xinc2; /* Change the x as appropriate */ - y += yinc2; /* Change the y as appropriate */ - } -} - -/** - * @brief Displays an polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_PolyLine(pPoint Points, uint16_t PointCount) -{ - int16_t X = 0, Y = 0; - - if(PointCount < 2) - { - return; - } - - while(--PointCount) - { - X = Points->X; - Y = Points->Y; - Points++; - LCD_DrawUniLine(X, Y, Points->X, Points->Y); - } -} - -/** - * @brief Displays an relative polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @param Closed: specifies if the draw is closed or not. - * 1: closed, 0 : not closed. - * @retval None - */ -static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed) -{ - int16_t X = 0, Y = 0; - pPoint First = Points; - - if(PointCount < 2) - { - return; - } - X = Points->X; - Y = Points->Y; - while(--PointCount) - { - Points++; - LCD_DrawUniLine(X, Y, X + Points->X, Y + Points->Y); - X = X + Points->X; - Y = Y + Points->Y; - } - if(Closed) - { - LCD_DrawUniLine(First->X, First->Y, X, Y); - } -} - -/** - * @brief Displays a closed polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount) -{ - LCD_PolyLine(Points, PointCount); - LCD_DrawUniLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y); -} - -/** - * @brief Displays a relative polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount) -{ - LCD_PolyLineRelativeClosed(Points, PointCount, 0); -} - -/** - * @brief Displays a closed relative polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount) -{ - LCD_PolyLineRelativeClosed(Points, PointCount, 1); -} - - -/** - * @brief Displays a full polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_FillPolyLine(pPoint Points, uint16_t PointCount) -{ - /* public-domain code by Darel Rex Finley, 2007 */ - uint16_t nodes = 0, nodeX[MAX_POLY_CORNERS], pixelX = 0, pixelY = 0, i = 0, - j = 0, swap = 0; - uint16_t IMAGE_LEFT = 0, IMAGE_RIGHT = 0, IMAGE_TOP = 0, IMAGE_BOTTOM = 0; - - IMAGE_LEFT = IMAGE_RIGHT = Points->X; - IMAGE_TOP= IMAGE_BOTTOM = Points->Y; - - for(i = 1; i < PointCount; i++) - { - pixelX = POLY_X(i); - if(pixelX < IMAGE_LEFT) - { - IMAGE_LEFT = pixelX; - } - if(pixelX > IMAGE_RIGHT) - { - IMAGE_RIGHT = pixelX; - } - - pixelY = POLY_Y(i); - if(pixelY < IMAGE_TOP) - { - IMAGE_TOP = pixelY; - } - if(pixelY > IMAGE_BOTTOM) - { - IMAGE_BOTTOM = pixelY; - } - } - - LCD_SetTextColor(BackColor); - - /* Loop through the rows of the image. */ - for (pixelY = IMAGE_TOP; pixelY < IMAGE_BOTTOM; pixelY++) - { - /* Build a list of nodes. */ - nodes = 0; j = PointCount-1; - - for (i = 0; i < PointCount; i++) - { - if (POLY_Y(i)<(double) pixelY && POLY_Y(j)>=(double) pixelY || POLY_Y(j)<(double) pixelY && POLY_Y(i)>=(double) pixelY) - { - nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i))); - } - j = i; - } - - /* Sort the nodes, via a simple "Bubble" sort. */ - i = 0; - while (i < nodes-1) - { - if (nodeX[i]>nodeX[i+1]) - { - swap = nodeX[i]; - nodeX[i] = nodeX[i+1]; - nodeX[i+1] = swap; - if(i) - { - i--; - } - } - else - { - i++; - } - } - - /* Fill the pixels between node pairs. */ - for (i = 0; i < nodes; i+=2) - { - if(nodeX[i] >= IMAGE_RIGHT) - { - break; - } - if(nodeX[i+1] > IMAGE_LEFT) - { - if (nodeX[i] < IMAGE_LEFT) - { - nodeX[i]=IMAGE_LEFT; - } - if(nodeX[i+1] > IMAGE_RIGHT) - { - nodeX[i+1] = IMAGE_RIGHT; - } - LCD_SetTextColor(BackColor); - LCD_DrawLine(pixelY, nodeX[i+1], nodeX[i+1] - nodeX[i], LCD_DIR_HORIZONTAL); - LCD_SetTextColor(TextColor); - PutPixel(pixelY, nodeX[i+1]); - PutPixel(pixelY, nodeX[i]); - /* for (j=nodeX[i]; jLCD_REG = LCD_Reg; - /* Write 16-bit Reg */ - LCD->LCD_RAM = LCD_RegValue; -} - - -/** - * @brief Reads the selected LCD Register. - * @param LCD_Reg: address of the selected register. - * @retval LCD Register Value. - */ -uint16_t LCD_ReadReg(uint8_t LCD_Reg) -{ - /* Write 16-bit Index (then Read Reg) */ - LCD->LCD_REG = LCD_Reg; - /* Read 16-bit Reg */ - return (LCD->LCD_RAM); -} - - -/** - * @brief Prepare to write to the LCD RAM. - * @param None - * @retval None - */ -void LCD_WriteRAM_Prepare(void) -{ - LCD->LCD_REG = LCD_REG_34; -} - - -/** - * @brief Writes to the LCD RAM. - * @param RGB_Code: the pixel color in RGB mode (5-6-5). - * @retval None - */ -void LCD_WriteRAM(uint16_t RGB_Code) -{ - /* Write 16-bit GRAM Reg */ - LCD->LCD_RAM = RGB_Code; -} - - -/** - * @brief Reads the LCD RAM. - * @param None - * @retval LCD RAM Value. - */ -uint16_t LCD_ReadRAM(void) -{ - /* Write 16-bit Index (then Read Reg) */ - LCD->LCD_REG = LCD_REG_34; /* Select GRAM Reg */ - /* Read 16-bit Reg */ - return LCD->LCD_RAM; -} - - -/** - * @brief Power on the LCD. - * @param None - * @retval None - */ -void LCD_PowerOn(void) -{ -/* Power On sequence ---------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude*/ - _delay_(20); /* Dis-charge capacitor power voltage (200ms) */ - LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ - LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */ -} - - -/** - * @brief Enables the Display. - * @param None - * @retval None - */ -void LCD_DisplayOn(void) -{ - /* Display On */ - LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */ -} - - -/** - * @brief Disables the Display. - * @param None - * @retval None - */ -void LCD_DisplayOff(void) -{ - /* Display Off */ - LCD_WriteReg(LCD_REG_7, 0x0); -} - - -/** - * @brief Configures LCD Control lines (FSMC Pins) in alternate function mode. - * @param None - * @retval None - */ -void LCD_CtrlLinesConfig(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - /* Enable FSMC, GPIOD, GPIOE, GPIOF, GPIOG and AFIO clocks */ - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE); - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | - RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG | - RCC_APB2Periph_AFIO, ENABLE); - /* Set PD.00(D2), PD.01(D3), PD.04(NOE), PD.05(NWE), PD.08(D13), PD.09(D14), - PD.10(D15), PD.14(D0), PD.15(D1) as alternate function push pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | - GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 | - GPIO_Pin_15; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOD, &GPIO_InitStructure); - /* Set PE.07(D4), PE.08(D5), PE.09(D6), PE.10(D7), PE.11(D8), PE.12(D9), PE.13(D10), - PE.14(D11), PE.15(D12) as alternate function push pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | - GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | - GPIO_Pin_15; - GPIO_Init(GPIOE, &GPIO_InitStructure); - /* Set PF.00(A0 (RS)) as alternate function push pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; - GPIO_Init(GPIOF, &GPIO_InitStructure); - /* Set PG.12(NE4 (LCD/CS)) as alternate function push pull - CE3(LCD /CS) */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; - GPIO_Init(GPIOG, &GPIO_InitStructure); -} - - -/** - * @brief Configures the Parallel interface (FSMC) for LCD(Parallel mode) - * @param None - * @retval None - */ -void LCD_FSMCConfig(void) -{ - FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; - FSMC_NORSRAMTimingInitTypeDef p; -/*-- FSMC Configuration ------------------------------------------------------*/ -/*----------------------- SRAM Bank 4 ----------------------------------------*/ - /* FSMC_Bank1_NORSRAM4 configuration */ - p.FSMC_AddressSetupTime = 1; - p.FSMC_AddressHoldTime = 0; - p.FSMC_DataSetupTime = 2; - p.FSMC_BusTurnAroundDuration = 0; - p.FSMC_CLKDivision = 0; - p.FSMC_DataLatency = 0; - p.FSMC_AccessMode = FSMC_AccessMode_A; - /* Color LCD configuration ------------------------------------ - LCD configured as follow: - - Data/Address MUX = Disable - - Memory Type = SRAM - - Data Width = 16bit - - Write Operation = Enable - - Extended Mode = Enable - - Asynchronous Wait = Disable */ - FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM4; - FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; - FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; - FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; - FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; - FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; - FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; - FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); - /* BANK 4 (of NOR/SRAM Bank 1~4) is enabled */ - FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE); -} - -/** - * @brief Displays a pixel. - * @param x: pixel x. - * @param y: pixel y. - * @retval None - */ -static void PutPixel(int16_t x, int16_t y) -{ - if(x < 0 || x > 239 || y < 0 || y > 319) - { - return; - } - LCD_DrawLine(x, y, 1, LCD_DIR_HORIZONTAL); -} - -#ifndef USE_Delay -/** - * @brief Inserts a delay time. - * @param nCount: specifies the delay time length. - * @retval None - */ -static void delay(vu32 nCount) -{ - vu32 index = 0; - for(index = (100000 * nCount); index != 0; index--) - { - } -} -#endif /* USE_Delay*/ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_lcd.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_lcd.h deleted file mode 100644 index 75ba22441..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_lcd.h +++ /dev/null @@ -1,359 +0,0 @@ -/** - ****************************************************************************** - * @file stm3210e_eval_lcd.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains all the functions prototypes for the stm3210e_eval_lcd - * firmware driver. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM3210E_EVAL_LCD_H -#define __STM3210E_EVAL_LCD_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" -#include "../Common/fonts.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM3210E_EVAL - * @{ - */ - -/** @addtogroup STM3210E_EVAL_LCD - * @{ - */ - -/** @defgroup STM3210E_EVAL_LCD_Exported_Types - * @{ - */ -typedef struct -{ - int16_t X; - int16_t Y; -} Point, * pPoint; -/** - * @} - */ - -/** @defgroup STM3210E_EVAL_LCD_Exported_Constants - * @{ - */ - -/** - * @brief Uncomment the line below if you want to use user defined Delay function - * (for precise timing), otherwise default _delay_ function defined within - * this driver is used (less precise timing). - */ -/* #define USE_Delay */ - -#ifdef USE_Delay -#include "main.h" - #define _delay_ Delay /* !< User can provide more timing precise _delay_ function - (with 10ms time base), using SysTick for example */ -#else - #define _delay_ delay /* !< Default _delay_ function with less precise timing */ -#endif - -/** - * @brief LCD Registers - */ -#define LCD_REG_0 0x00 -#define LCD_REG_1 0x01 -#define LCD_REG_2 0x02 -#define LCD_REG_3 0x03 -#define LCD_REG_4 0x04 -#define LCD_REG_5 0x05 -#define LCD_REG_6 0x06 -#define LCD_REG_7 0x07 -#define LCD_REG_8 0x08 -#define LCD_REG_9 0x09 -#define LCD_REG_10 0x0A -#define LCD_REG_12 0x0C -#define LCD_REG_13 0x0D -#define LCD_REG_14 0x0E -#define LCD_REG_15 0x0F -#define LCD_REG_16 0x10 -#define LCD_REG_17 0x11 -#define LCD_REG_18 0x12 -#define LCD_REG_19 0x13 -#define LCD_REG_20 0x14 -#define LCD_REG_21 0x15 -#define LCD_REG_22 0x16 -#define LCD_REG_23 0x17 -#define LCD_REG_24 0x18 -#define LCD_REG_25 0x19 -#define LCD_REG_26 0x1A -#define LCD_REG_27 0x1B -#define LCD_REG_28 0x1C -#define LCD_REG_29 0x1D -#define LCD_REG_30 0x1E -#define LCD_REG_31 0x1F -#define LCD_REG_32 0x20 -#define LCD_REG_33 0x21 -#define LCD_REG_34 0x22 -#define LCD_REG_36 0x24 -#define LCD_REG_37 0x25 -#define LCD_REG_40 0x28 -#define LCD_REG_41 0x29 -#define LCD_REG_43 0x2B -#define LCD_REG_45 0x2D -#define LCD_REG_48 0x30 -#define LCD_REG_49 0x31 -#define LCD_REG_50 0x32 -#define LCD_REG_51 0x33 -#define LCD_REG_52 0x34 -#define LCD_REG_53 0x35 -#define LCD_REG_54 0x36 -#define LCD_REG_55 0x37 -#define LCD_REG_56 0x38 -#define LCD_REG_57 0x39 -#define LCD_REG_58 0x3A -#define LCD_REG_59 0x3B -#define LCD_REG_60 0x3C -#define LCD_REG_61 0x3D -#define LCD_REG_62 0x3E -#define LCD_REG_63 0x3F -#define LCD_REG_64 0x40 -#define LCD_REG_65 0x41 -#define LCD_REG_66 0x42 -#define LCD_REG_67 0x43 -#define LCD_REG_68 0x44 -#define LCD_REG_69 0x45 -#define LCD_REG_70 0x46 -#define LCD_REG_71 0x47 -#define LCD_REG_72 0x48 -#define LCD_REG_73 0x49 -#define LCD_REG_74 0x4A -#define LCD_REG_75 0x4B -#define LCD_REG_76 0x4C -#define LCD_REG_77 0x4D -#define LCD_REG_78 0x4E -#define LCD_REG_79 0x4F -#define LCD_REG_80 0x50 -#define LCD_REG_81 0x51 -#define LCD_REG_82 0x52 -#define LCD_REG_83 0x53 -#define LCD_REG_96 0x60 -#define LCD_REG_97 0x61 -#define LCD_REG_106 0x6A -#define LCD_REG_118 0x76 -#define LCD_REG_128 0x80 -#define LCD_REG_129 0x81 -#define LCD_REG_130 0x82 -#define LCD_REG_131 0x83 -#define LCD_REG_132 0x84 -#define LCD_REG_133 0x85 -#define LCD_REG_134 0x86 -#define LCD_REG_135 0x87 -#define LCD_REG_136 0x88 -#define LCD_REG_137 0x89 -#define LCD_REG_139 0x8B -#define LCD_REG_140 0x8C -#define LCD_REG_141 0x8D -#define LCD_REG_143 0x8F -#define LCD_REG_144 0x90 -#define LCD_REG_145 0x91 -#define LCD_REG_146 0x92 -#define LCD_REG_147 0x93 -#define LCD_REG_148 0x94 -#define LCD_REG_149 0x95 -#define LCD_REG_150 0x96 -#define LCD_REG_151 0x97 -#define LCD_REG_152 0x98 -#define LCD_REG_153 0x99 -#define LCD_REG_154 0x9A -#define LCD_REG_157 0x9D -#define LCD_REG_192 0xC0 -#define LCD_REG_193 0xC1 -#define LCD_REG_229 0xE5 - -/** - * @brief LCD color - */ -#define LCD_COLOR_WHITE 0xFFFF -#define LCD_COLOR_BLACK 0x0000 -#define LCD_COLOR_GREY 0xF7DE -#define LCD_COLOR_BLUE 0x001F -#define LCD_COLOR_BLUE2 0x051F -#define LCD_COLOR_RED 0xF800 -#define LCD_COLOR_MAGENTA 0xF81F -#define LCD_COLOR_GREEN 0x07E0 -#define LCD_COLOR_CYAN 0x7FFF -#define LCD_COLOR_YELLOW 0xFFE0 - -/** - * @brief LCD Lines depending on the chosen fonts. - */ -#define LCD_LINE_0 LINE(0) -#define LCD_LINE_1 LINE(1) -#define LCD_LINE_2 LINE(2) -#define LCD_LINE_3 LINE(3) -#define LCD_LINE_4 LINE(4) -#define LCD_LINE_5 LINE(5) -#define LCD_LINE_6 LINE(6) -#define LCD_LINE_7 LINE(7) -#define LCD_LINE_8 LINE(8) -#define LCD_LINE_9 LINE(9) -#define LCD_LINE_10 LINE(10) -#define LCD_LINE_11 LINE(11) -#define LCD_LINE_12 LINE(12) -#define LCD_LINE_13 LINE(13) -#define LCD_LINE_14 LINE(14) -#define LCD_LINE_15 LINE(15) -#define LCD_LINE_16 LINE(16) -#define LCD_LINE_17 LINE(17) -#define LCD_LINE_18 LINE(18) -#define LCD_LINE_19 LINE(19) -#define LCD_LINE_20 LINE(20) -#define LCD_LINE_21 LINE(21) -#define LCD_LINE_22 LINE(22) -#define LCD_LINE_23 LINE(23) -#define LCD_LINE_24 LINE(24) -#define LCD_LINE_25 LINE(25) -#define LCD_LINE_26 LINE(26) -#define LCD_LINE_27 LINE(27) -#define LCD_LINE_28 LINE(28) -#define LCD_LINE_29 LINE(29) - -/** - * @brief LCD default font - */ -#define LCD_DEFAULT_FONT Font16x24 - -/** - * @brief LCD Direction - */ -#define LCD_DIR_HORIZONTAL 0x0000 -#define LCD_DIR_VERTICAL 0x0001 - -/** - * @brief LCD Size (Width and Height) - */ -#define LCD_PIXEL_WIDTH 0x0140 -#define LCD_PIXEL_HEIGHT 0x00F0 - -/** - * @} - */ - -/** @defgroup STM3210E_EVAL_LCD_Exported_Macros - * @{ - */ -#define ASSEMBLE_RGB(R, G, B) ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3)) -/** - * @} - */ - -/** @defgroup STM3210E_EVAL_LCD_Exported_Functions - * @{ - */ -/** @defgroup - * @{ - */ -void LCD_DeInit(void); -void STM3210E_LCD_Init(void); -void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor); -void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor); -void LCD_SetTextColor(__IO uint16_t Color); -void LCD_SetBackColor(__IO uint16_t Color); -void LCD_ClearLine(uint8_t Line); -void LCD_Clear(uint16_t Color); -void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos); -void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c); -void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii); -void LCD_SetFont(sFONT *fonts); -sFONT *LCD_GetFont(void); -void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr); -void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width); -void LCD_WindowModeDisable(void); -void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction); -void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width); -void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius); -void LCD_DrawMonoPict(const uint32_t *Pict); -void LCD_WriteBMP(uint32_t BmpAddress); -void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2); -void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height); -void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius); -void LCD_PolyLine(pPoint Points, uint16_t PointCount); -void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount); -void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount); -void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount); -void LCD_FillPolyLine(pPoint Points, uint16_t PointCount); -/** - * @} - */ - -/** @defgroup - * @{ - */ -void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue); -uint16_t LCD_ReadReg(uint8_t LCD_Reg); -void LCD_WriteRAM_Prepare(void); -void LCD_WriteRAM(uint16_t RGB_Code); -uint16_t LCD_ReadRAM(void); -void LCD_PowerOn(void); -void LCD_DisplayOn(void); -void LCD_DisplayOff(void); -/** - * @} - */ - -/** @defgroup - * @{ - */ -void LCD_CtrlLinesConfig(void); -void LCD_FSMCConfig(void); -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __STM3210E_EVAL_LCD_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c deleted file mode 100644 index 303505def..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c +++ /dev/null @@ -1,750 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l152_eval.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file provides: - * - set of firmware functions to manage Leds, push-button and COM ports - * - low level initialization functions for SD card (on SPI) and - * temperature sensor (LM75) available on STM32L152-EVAL - * evaluation board RevB from STMicroelectronics. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l152_eval.h" -#include "stm32l1xx_spi.h" -#include "stm32l1xx_i2c.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32L152_EVAL - * @{ - */ - -/** @defgroup STM32L152_EVAL_LOW_LEVEL - * @brief This file provides firmware functions to manage Leds, push-buttons, - * COM ports, SD card on SPI and temperature sensor (LM75) available on - * STM32L152-EVAL evaluation board from STMicroelectronics. - * @{ - */ - -/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Variables - * @{ - */ -GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT, - LED4_GPIO_PORT}; -const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN, - LED4_PIN}; -const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK, - LED4_GPIO_CLK}; - -GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT, - LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT, - DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT}; - -const uint16_t BUTTON_PIN[BUTTONn] = {KEY_BUTTON_PIN, RIGHT_BUTTON_PIN, - LEFT_BUTTON_PIN, UP_BUTTON_PIN, - DOWN_BUTTON_PIN, SEL_BUTTON_PIN}; - -const uint32_t BUTTON_CLK[BUTTONn] = {KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK, - LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK, - DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK}; - -const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {KEY_BUTTON_EXTI_LINE, - RIGHT_BUTTON_EXTI_LINE, - LEFT_BUTTON_EXTI_LINE, - UP_BUTTON_EXTI_LINE, - DOWN_BUTTON_EXTI_LINE, - SEL_BUTTON_EXTI_LINE}; - -const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {KEY_BUTTON_EXTI_PORT_SOURCE, - RIGHT_BUTTON_EXTI_PORT_SOURCE, - LEFT_BUTTON_EXTI_PORT_SOURCE, - UP_BUTTON_EXTI_PORT_SOURCE, - DOWN_BUTTON_EXTI_PORT_SOURCE, - SEL_BUTTON_EXTI_PORT_SOURCE}; - -const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {KEY_BUTTON_EXTI_PIN_SOURCE, - RIGHT_BUTTON_EXTI_PIN_SOURCE, - LEFT_BUTTON_EXTI_PIN_SOURCE, - UP_BUTTON_EXTI_PIN_SOURCE, - DOWN_BUTTON_EXTI_PIN_SOURCE, - SEL_BUTTON_EXTI_PIN_SOURCE}; - -const uint16_t BUTTON_IRQn[BUTTONn] = {KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn, - LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn, - DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn}; - -USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2}; - -GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT}; - -GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT}; - -const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK}; - -const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK}; - -const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK}; - -const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN}; - -const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN}; - -const uint16_t COM_TX_PIN_SOURCE[COMn] = {EVAL_COM1_TX_SOURCE, EVAL_COM2_TX_SOURCE}; - -const uint16_t COM_RX_PIN_SOURCE[COMn] = {EVAL_COM1_RX_SOURCE, EVAL_COM2_RX_SOURCE}; - -const uint16_t COM_TX_AF[COMn] = {EVAL_COM1_TX_AF, EVAL_COM2_TX_AF}; - -const uint16_t COM_RX_AF[COMn] = {EVAL_COM1_RX_AF, EVAL_COM2_RX_AF}; - -DMA_InitTypeDef sEEDMA_InitStructure; - -/** - * @} - */ - - -/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Functions - * @{ - */ - -/** - * @brief Configures LED GPIO. - * @param Led: Specifies the Led to be configured. - * This parameter can be one of following parameters: - * @arg LED1 - * @arg LED2 - * @arg LED3 - * @arg LED4 - * @retval None - */ -void STM_EVAL_LEDInit(Led_TypeDef Led) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable the GPIO_LED Clock */ - RCC_AHBPeriphClockCmd(GPIO_CLK[Led], ENABLE); - - /* Configure the GPIO_LED pin */ - GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led]; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz; - GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure); - GPIO_PORT[Led]->BSRRL = GPIO_PIN[Led]; -} - -/** - * @brief Turns selected LED On. - * @param Led: Specifies the Led to be set on. - * This parameter can be one of following parameters: - * @arg LED1 - * @arg LED2 - * @arg LED3 - * @arg LED4 - * @retval None - */ -void STM_EVAL_LEDOn(Led_TypeDef Led) -{ - GPIO_PORT[Led]->BSRRH = GPIO_PIN[Led]; -} - -/** - * @brief Turns selected LED Off. - * @param Led: Specifies the Led to be set off. - * This parameter can be one of following parameters: - * @arg LED1 - * @arg LED2 - * @arg LED3 - * @arg LED4 - * @retval None - */ -void STM_EVAL_LEDOff(Led_TypeDef Led) -{ - GPIO_PORT[Led]->BSRRL = GPIO_PIN[Led]; -} - -/** - * @brief Toggles the selected LED. - * @param Led: Specifies the Led to be toggled. - * This parameter can be one of following parameters: - * @arg LED1 - * @arg LED2 - * @arg LED3 - * @arg LED4 - * @retval None - */ -void STM_EVAL_LEDToggle(Led_TypeDef Led) -{ - GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led]; -} - -/** - * @brief Configures Button GPIO and EXTI Line. - * @param Button: Specifies the Button to be configured. - * This parameter can be one of following parameters: - * @arg BUTTON_KEY: Key Push Button - * @arg BUTTON_RIGHT: Joystick Right Push Button - * @arg BUTTON_LEFT: Joystick Left Push Button - * @arg BUTTON_UP: Joystick Up Push Button - * @arg BUTTON_DOWN: Joystick Down Push Button - * @arg BUTTON_SEL: Joystick Sel Push Button - * @param Button_Mode: Specifies Button mode. - * This parameter can be one of following parameters: - * @arg BUTTON_MODE_GPIO: Button will be used as simple IO - * @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt - * generation capability - * @retval None - */ -void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode) -{ - GPIO_InitTypeDef GPIO_InitStructure; - EXTI_InitTypeDef EXTI_InitStructure; - NVIC_InitTypeDef NVIC_InitStructure; - - /* There is no Wakeup and Tamper buttons on STM32L152-EVAL, the Button value should - be greater than 1. */ - if(Button > 1) - { - Button = (Button_TypeDef) (Button - 2); - - /* Enable the BUTTON Clock */ - RCC_AHBPeriphClockCmd(BUTTON_CLK[Button], ENABLE); - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - - /* Configure Button pin as input */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button]; - GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure); - - - if (Button_Mode == BUTTON_MODE_EXTI) - { - /* Connect Button EXTI Line to Button GPIO Pin */ - SYSCFG_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]); - - /* Configure Button EXTI line */ - EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button]; - EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; - - if(Button != BUTTON_KEY) - { - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; - } - else - { - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; - } - EXTI_InitStructure.EXTI_LineCmd = ENABLE; - EXTI_Init(&EXTI_InitStructure); - - /* Enable and set Button EXTI Interrupt to the lowest priority */ - NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button]; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - - NVIC_Init(&NVIC_InitStructure); - } - } -} - -/** - * @brief Returns the selected Button state. - * @param Button: Specifies the Button to be checked. - * This parameter can be one of following parameters: - * @arg BUTTON_KEY: Key Push Button - * @arg BUTTON_RIGHT: Joystick Right Push Button - * @arg BUTTON_LEFT: Joystick Left Push Button - * @arg BUTTON_UP: Joystick Up Push Button - * @arg BUTTON_DOWN: Joystick Down Push Button - * @arg BUTTON_SEL: Joystick Sel Push Button - * @retval - When Button > 1, the Button GPIO pin value is returned. - * - When Button = 0 or 1, error code (0xFF) is returned. - */ -uint32_t STM_EVAL_PBGetState(Button_TypeDef Button) -{ - /* There is no Wakeup and Tamper pins on STM32L152-EVAL, the Button value should - be greater than 1. */ - if(Button > 1) - { - Button = (Button_TypeDef) (Button - 2); - return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]); - } - else - { - return 0xFF; /* Error Code */ - } -} - -/** - * @brief Configures COM port. - * @param COM: Specifies the COM port to be configured. - * This parameter can be one of following parameters: - * @arg COM1 - * @arg COM2 - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that - * contains the configuration information for the specified USART peripheral. - * @retval None - */ -void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable GPIO clock */ - RCC_AHBPeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM], ENABLE); - - /* Enable UART clock */ - RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE); - - /* Connect PXx to USARTx_Tx */ - GPIO_PinAFConfig(COM_TX_PORT[COM], COM_TX_PIN_SOURCE[COM], COM_TX_AF[COM]); - - /* Connect PXx to USARTx_Rx */ - GPIO_PinAFConfig(COM_RX_PORT[COM], COM_RX_PIN_SOURCE[COM], COM_RX_AF[COM]); - - /* Configure USART Tx as alternate function push-pull */ - GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM]; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure); - - /* Configure USART Rx as alternate function push-pull */ - GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM]; - GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure); - - /* USART configuration */ - USART_Init(COM_USART[COM], USART_InitStruct); - - /* Enable USART */ - USART_Cmd(COM_USART[COM], ENABLE); -} - -/** - * @brief DeInitializes the SPI interface. - * @param None - * @retval None - */ -void SD_LowLevel_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - SPI_Cmd(SD_SPI, DISABLE); /*!< SD_SPI disable */ - SPI_DeInit(SD_SPI); /*!< DeInitializes the SD_SPI */ - - /*!< SD_SPI Periph clock disable */ - RCC_APB1PeriphClockCmd(SD_SPI_CLK, DISABLE); - - /*!< Configure SD_SPI pins: SCK */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI pins: MISO */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN; - GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI pins: MOSI */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN; - GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */ - GPIO_InitStructure.GPIO_Pin = SD_CS_PIN; - GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */ - GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN; - GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @brief Initializes the SD Card and put it into StandBy State (Ready for - * data transfer). - * @param None - * @retval None - */ -void SD_LowLevel_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - SPI_InitTypeDef SPI_InitStructure; - - /*!< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO - and SD_SPI_SCK_GPIO Periph clock enable */ - RCC_AHBPeriphClockCmd(SD_CS_GPIO_CLK | SD_SPI_MOSI_GPIO_CLK | SD_SPI_MISO_GPIO_CLK | - SD_SPI_SCK_GPIO_CLK | SD_DETECT_GPIO_CLK, ENABLE); - - /*!< SD_SPI Periph clock enable */ - RCC_APB1PeriphClockCmd(SD_SPI_CLK, ENABLE); - - /*!< Configure SD_SPI pins: SCK */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI pins: MISO */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN; - GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI pins: MOSI */ - GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN; - GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */ - GPIO_InitStructure.GPIO_Pin = SD_CS_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz; - GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */ - GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure); - - /* Connect PXx to SD_SPI_SCK */ - GPIO_PinAFConfig(SD_SPI_SCK_GPIO_PORT, SD_SPI_SCK_SOURCE, SD_SPI_SCK_AF); - - /* Connect PXx to SD_SPI_MISO */ - GPIO_PinAFConfig(SD_SPI_MISO_GPIO_PORT, SD_SPI_MISO_SOURCE, SD_SPI_MISO_AF); - - /* Connect PXx to SD_SPI_MOSI */ - GPIO_PinAFConfig(SD_SPI_MOSI_GPIO_PORT, SD_SPI_MOSI_SOURCE, SD_SPI_MOSI_AF); - - /*!< SD_SPI Config */ - SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; - SPI_InitStructure.SPI_Mode = SPI_Mode_Master; - SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; - SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; - SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; - SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; - SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - - SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; - SPI_InitStructure.SPI_CRCPolynomial = 7; - SPI_Init(SD_SPI, &SPI_InitStructure); - - SPI_Cmd(SD_SPI, ENABLE); /*!< SD_SPI enable */ -} - -/** - * @brief DeInitializes the LM75_I2C. - * @param None - * @retval None - */ -void LM75_LowLevel_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< Disable LM75_I2C */ - I2C_Cmd(LM75_I2C, DISABLE); - - /*!< DeInitializes the LM75_I2C */ - I2C_DeInit(LM75_I2C); - - /*!< LM75_I2C Periph clock disable */ - RCC_APB1PeriphClockCmd(LM75_I2C_CLK, DISABLE); - - /*!< Configure LM75_I2C pins: SCL */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure LM75_I2C pins: SDA */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN; - GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure LM75_I2C pin: SMBUS ALERT */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN; - GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @brief Initializes the LM75_I2C. - * @param None - * @retval None - */ -void LM75_LowLevel_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< LM75_I2C Periph clock enable */ - RCC_APB1PeriphClockCmd(LM75_I2C_CLK, ENABLE); - - /*!< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK - and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable */ - RCC_AHBPeriphClockCmd(LM75_I2C_SCL_GPIO_CLK | LM75_I2C_SDA_GPIO_CLK | - LM75_I2C_SMBUSALERT_GPIO_CLK, ENABLE); - - /*!< Configure LM75_I2C pins: SCL */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure LM75_I2C pins: SDA */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN; - GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure LM75_I2C pin: SMBUS ALERT */ - GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN; - GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure); - - - /* Connect PXx to I2C_SCL */ - GPIO_PinAFConfig(LM75_I2C_SCL_GPIO_PORT, LM75_I2C_SCL_SOURCE, LM75_I2C_SCL_AF); - - /* Connect PXx to I2C_SDA */ - GPIO_PinAFConfig(LM75_I2C_SDA_GPIO_PORT, LM75_I2C_SDA_SOURCE, LM75_I2C_SDA_AF); - - /* Connect PXx to I2C_SMBUSALER */ - GPIO_PinAFConfig(LM75_I2C_SMBUSALERT_GPIO_PORT, LM75_I2C_SMBUSALERT_SOURCE, LM75_I2C_SMBUSALERT_AF); -} - -/** - * @brief DeInitializes peripherals used by the I2C EEPROM driver. - * @param None - * @retval None - */ -void sEE_LowLevel_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - NVIC_InitTypeDef NVIC_InitStructure; - - /* sEE_I2C Peripheral Disable */ - I2C_Cmd(sEE_I2C, DISABLE); - - /* sEE_I2C DeInit */ - I2C_DeInit(sEE_I2C); - - /*!< sEE_I2C Periph clock disable */ - RCC_APB1PeriphClockCmd(sEE_I2C_CLK, DISABLE); - - /*!< GPIO configuration */ - /*!< Configure sEE_I2C pins: SCL */ - GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sEE_I2C pins: SDA */ - GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN; - GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); - - /* Configure and enable I2C DMA TX Channel interrupt */ - NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO; - NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE; - NVIC_Init(&NVIC_InitStructure); - - /* Configure and enable I2C DMA RX Channel interrupt */ - NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO; - NVIC_Init(&NVIC_InitStructure); - - /* Disable and Deinitialize the DMA channels */ - DMA_Cmd(sEE_I2C_DMA_CHANNEL_TX, DISABLE); - DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, DISABLE); - DMA_DeInit(sEE_I2C_DMA_CHANNEL_TX); - DMA_DeInit(sEE_I2C_DMA_CHANNEL_RX); -} - -/** - * @brief Initializes peripherals used by the I2C EEPROM driver. - * @param None - * @retval None - */ -void sEE_LowLevel_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - NVIC_InitTypeDef NVIC_InitStructure; - - /*!< sEE_I2C Periph clock enable */ - RCC_APB1PeriphClockCmd(sEE_I2C_CLK, ENABLE); - - /*!< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable */ - RCC_AHBPeriphClockCmd(sEE_I2C_SCL_GPIO_CLK | sEE_I2C_SDA_GPIO_CLK, ENABLE); - - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - - /* Reset sEE_I2C peripheral */ - RCC_APB1PeriphResetCmd(sEE_I2C_CLK, ENABLE); - - /* Release reset signal of sEE_I2C IP */ - RCC_APB1PeriphResetCmd(sEE_I2C_CLK, DISABLE); - - /*!< GPIO configuration */ - /*!< Configure sEE_I2C pins: SCL */ - GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure); - - /*!< Configure sEE_I2C pins: SDA */ - GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN; - GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); - - /* Connect PXx to I2C_SCL*/ - GPIO_PinAFConfig(sEE_I2C_SCL_GPIO_PORT, sEE_I2C_SCL_SOURCE, sEE_I2C_SCL_AF); - - /* Connect PXx to I2C_SDA*/ - GPIO_PinAFConfig(sEE_I2C_SDA_GPIO_PORT, sEE_I2C_SDA_SOURCE, sEE_I2C_SDA_AF); - - /* Configure and enable I2C DMA TX Channel interrupt */ - NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); - - /* Configure and enable I2C DMA RX Channel interrupt */ - NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO; - NVIC_Init(&NVIC_InitStructure); - - /*!< I2C DMA TX and RX channels configuration */ - /* Enable the DMA clock */ - RCC_AHBPeriphClockCmd(sEE_I2C_DMA_CLK, ENABLE); - - /* I2C TX DMA Channel configuration */ - DMA_DeInit(sEE_I2C_DMA_CHANNEL_TX); - sEEDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)sEE_I2C_DR_Address; - sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)0; /* This parameter will be configured durig communication */ - sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST; /* This parameter will be configured durig communication */ - sEEDMA_InitStructure.DMA_BufferSize = 0xFFFF; /* This parameter will be configured durig communication */ - sEEDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - sEEDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - sEEDMA_InitStructure.DMA_PeripheralDataSize = DMA_MemoryDataSize_Byte; - sEEDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - sEEDMA_InitStructure.DMA_Mode = DMA_Mode_Normal; - sEEDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; - sEEDMA_InitStructure.DMA_M2M = DMA_M2M_Disable; - DMA_Init(sEE_I2C_DMA_CHANNEL_TX, &sEEDMA_InitStructure); - - /* I2C RX DMA Channel configuration */ - DMA_DeInit(sEE_I2C_DMA_CHANNEL_RX); - DMA_Init(sEE_I2C_DMA_CHANNEL_RX, &sEEDMA_InitStructure); - - /* Enable the DMA Channels Interrupts */ - DMA_ITConfig(sEE_I2C_DMA_CHANNEL_TX, DMA_IT_TC, ENABLE); - DMA_ITConfig(sEE_I2C_DMA_CHANNEL_RX, DMA_IT_TC, ENABLE); -} - -/** - * @brief Initializes DMA channel used by the I2C EEPROM driver. - * @param None - * @retval None - */ -void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction) -{ - /* Initialize the DMA with the new parameters */ - if (Direction == sEE_DIRECTION_TX) - { - /* Configure the DMA Tx Channel with the buffer address and the buffer size */ - sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)pBuffer; - sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST; - sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize; - DMA_Init(sEE_I2C_DMA_CHANNEL_TX, &sEEDMA_InitStructure); - } - else - { - /* Configure the DMA Rx Channel with the buffer address and the buffer size */ - sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)pBuffer; - sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; - sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize; - DMA_Init(sEE_I2C_DMA_CHANNEL_RX, &sEEDMA_InitStructure); - } -} - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.h deleted file mode 100644 index c3ac81676..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.h +++ /dev/null @@ -1,403 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l152_eval.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains definitions for STM32L152_EVAL's Leds, push-buttons - * and COM ports hardware resources. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L152_EVAL_H -#define __STM32L152_EVAL_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32_eval.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32L152_EVAL - * @{ - */ - -/** @addtogroup STM32L152_EVAL_LOW_LEVEL - * @{ - */ - -/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Types - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Constants - * @{ - */ - -/** @addtogroup STM32L152_EVAL_LOW_LEVEL_LED - * @{ - */ -#define LEDn 4 - -#define LED1_PIN GPIO_Pin_0 -#define LED1_GPIO_PORT GPIOD -#define LED1_GPIO_CLK RCC_AHBPeriph_GPIOD - -#define LED2_PIN GPIO_Pin_1 -#define LED2_GPIO_PORT GPIOD -#define LED2_GPIO_CLK RCC_AHBPeriph_GPIOD - -#define LED3_PIN GPIO_Pin_4 -#define LED3_GPIO_PORT GPIOD -#define LED3_GPIO_CLK RCC_AHBPeriph_GPIOD - -#define LED4_PIN GPIO_Pin_5 -#define LED4_GPIO_PORT GPIOD -#define LED4_GPIO_CLK RCC_AHBPeriph_GPIOD - -/** - * @} - */ - -/** @addtogroup STM32L152_EVAL_LOW_LEVEL_BUTTON - * @{ - */ -#define BUTTONn 6 -/* On STM32L152-EVAL board, the KEY button is connected to PC.13 and it can -be use as Tamper and Wakeup pin buttons. */ - -/** - * @brief Key push-button - */ -#define KEY_BUTTON_PIN GPIO_Pin_0 -#define KEY_BUTTON_GPIO_PORT GPIOA -#define KEY_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOA -#define KEY_BUTTON_EXTI_LINE EXTI_Line0 -#define KEY_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOA -#define KEY_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource0 -#define KEY_BUTTON_EXTI_IRQn EXTI0_IRQn - -/** - * @brief Joystick Right push-button - */ -#define RIGHT_BUTTON_PIN GPIO_Pin_11 -#define RIGHT_BUTTON_GPIO_PORT GPIOE -#define RIGHT_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE -#define RIGHT_BUTTON_EXTI_LINE EXTI_Line11 -#define RIGHT_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE -#define RIGHT_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource11 -#define RIGHT_BUTTON_EXTI_IRQn EXTI15_10_IRQn - -/** - * @brief Joystick Left push-button - */ -#define LEFT_BUTTON_PIN GPIO_Pin_12 -#define LEFT_BUTTON_GPIO_PORT GPIOE -#define LEFT_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE -#define LEFT_BUTTON_EXTI_LINE EXTI_Line12 -#define LEFT_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE -#define LEFT_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource12 -#define LEFT_BUTTON_EXTI_IRQn EXTI15_10_IRQn - -/** - * @brief Joystick Up push-button - */ -#define UP_BUTTON_PIN GPIO_Pin_9 -#define UP_BUTTON_GPIO_PORT GPIOE -#define UP_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE -#define UP_BUTTON_EXTI_LINE EXTI_Line9 -#define UP_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE -#define UP_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource9 -#define UP_BUTTON_EXTI_IRQn EXTI9_5_IRQn - -/** - * @brief Joystick Down push-button - */ -#define DOWN_BUTTON_PIN GPIO_Pin_10 -#define DOWN_BUTTON_GPIO_PORT GPIOE -#define DOWN_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE -#define DOWN_BUTTON_EXTI_LINE EXTI_Line10 -#define DOWN_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE -#define DOWN_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource10 -#define DOWN_BUTTON_EXTI_IRQn EXTI15_10_IRQn - -/** - * @brief Joystick Sel push-button - */ -#define SEL_BUTTON_PIN GPIO_Pin_8 -#define SEL_BUTTON_GPIO_PORT GPIOE -#define SEL_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOE -#define SEL_BUTTON_EXTI_LINE EXTI_Line8 -#define SEL_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE -#define SEL_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource8 -#define SEL_BUTTON_EXTI_IRQn EXTI9_5_IRQn - -/** - * @} - */ - -/** @addtogroup STM32L152_EVAL_LOW_LEVEL_COM - * @{ - */ -#define COMn 2 - -/** - * @brief Definition for COM port1, connected to USART2 - */ -#define EVAL_COM1 USART2 -#define EVAL_COM1_CLK RCC_APB1Periph_USART2 - -#define EVAL_COM1_TX_PIN GPIO_Pin_5 -#define EVAL_COM1_TX_GPIO_PORT GPIOD -#define EVAL_COM1_TX_GPIO_CLK RCC_AHBPeriph_GPIOD -#define EVAL_COM1_TX_SOURCE GPIO_PinSource5 -#define EVAL_COM1_TX_AF GPIO_AF_USART2 - -#define EVAL_COM1_RX_PIN GPIO_Pin_6 -#define EVAL_COM1_RX_GPIO_PORT GPIOD -#define EVAL_COM1_RX_GPIO_CLK RCC_AHBPeriph_GPIOD -#define EVAL_COM1_RX_SOURCE GPIO_PinSource6 -#define EVAL_COM1_RX_AF GPIO_AF_USART2 - -#define EVAL_COM1_RTS_PIN GPIO_Pin_4 -#define EVAL_COM1_RTS_GPIO_PORT GPIOD -#define EVAL_COM1_RTS_GPIO_CLK RCC_AHBPeriph_GPIOD -#define EVAL_COM1_RTS_SOURCE GPIO_PinSource4 -#define EVAL_COM1_RTS_AF GPIO_AF_USART2 - -#define EVAL_COM1_CTS_PIN GPIO_Pin_3 -#define EVAL_COM1_CTS_GPIO_PORT GPIOD -#define EVAL_COM1_CTS_GPIO_CLK RCC_AHBPeriph_GPIOD -#define EVAL_COM1_CTS_SOURCE GPIO_PinSource3 -#define EVAL_COM1_CTS_AF GPIO_AF_USART2 - -#define EVAL_COM1_IRQn USART2_IRQn - -/** - * @brief Definition for COM port2, connected to USART3 - */ -#define EVAL_COM2 USART3 -#define EVAL_COM2_CLK RCC_APB1Periph_USART3 - -#define EVAL_COM2_TX_PIN GPIO_Pin_10 -#define EVAL_COM2_TX_GPIO_PORT GPIOC -#define EVAL_COM2_TX_GPIO_CLK RCC_AHBPeriph_GPIOC -#define EVAL_COM2_TX_SOURCE GPIO_PinSource10 -#define EVAL_COM2_TX_AF GPIO_AF_USART3 - -#define EVAL_COM2_RX_PIN GPIO_Pin_11 -#define EVAL_COM2_RX_GPIO_PORT GPIOC -#define EVAL_COM2_RX_GPIO_CLK RCC_AHBPeriph_GPIOC -#define EVAL_COM2_RX_SOURCE GPIO_PinSource11 -#define EVAL_COM2_RX_AF GPIO_AF_USART3 - -#define EVAL_COM2_IRQn USART3_IRQn - -/** - * @} - */ - -/** @addtogroup STM32L152_EVAL_LOW_LEVEL_SD_FLASH - * @{ - */ -/** - * @brief SD Card SPI Interface - */ -#define SD_SPI SPI2 -#define SD_SPI_CLK RCC_APB1Periph_SPI2 -#define SD_SPI_SCK_PIN GPIO_Pin_13 /* PB.13 */ -#define SD_SPI_SCK_GPIO_PORT GPIOB /* GPIOB */ -#define SD_SPI_SCK_GPIO_CLK RCC_AHBPeriph_GPIOB -#define SD_SPI_SCK_SOURCE GPIO_PinSource13 -#define SD_SPI_SCK_AF GPIO_AF_SPI2 -#define SD_SPI_MISO_PIN GPIO_Pin_14 /* PB.14 */ -#define SD_SPI_MISO_GPIO_PORT GPIOB /* GPIOB */ -#define SD_SPI_MISO_GPIO_CLK RCC_AHBPeriph_GPIOB -#define SD_SPI_MISO_SOURCE GPIO_PinSource14 -#define SD_SPI_MISO_AF GPIO_AF_SPI2 -#define SD_SPI_MOSI_PIN GPIO_Pin_15 /* PB.15 */ -#define SD_SPI_MOSI_GPIO_PORT GPIOB /* GPIOB */ -#define SD_SPI_MOSI_GPIO_CLK RCC_AHBPeriph_GPIOB -#define SD_SPI_MOSI_SOURCE GPIO_PinSource15 -#define SD_SPI_MOSI_AF GPIO_AF_SPI2 -#define SD_CS_PIN GPIO_Pin_7 /* PD.07 */ -#define SD_CS_GPIO_PORT GPIOD /* GPIOD */ -#define SD_CS_GPIO_CLK RCC_AHBPeriph_GPIOD -#define SD_DETECT_PIN GPIO_Pin_6 /* PE.06 */ -#define SD_DETECT_EXTI_LINE EXTI_Line6 -#define SD_DETECT_EXTI_PIN_SOURCE EXTI_PinSource6 - -#define SD_DETECT_GPIO_PORT GPIOE /* GPIOE */ -#define SD_DETECT_GPIO_CLK RCC_AHBPeriph_GPIOE -#define SD_DETECT_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE -#define SD_DETECT_EXTI_IRQn EXTI9_5_IRQn -/** - * @} - */ - -/** @addtogroup STM32L152_EVAL_LOW_LEVEL_TSENSOR_I2C - * @{ - */ -/** - * @brief LM75 Temperature Sensor I2C Interface pins - */ -#define LM75_I2C I2C1 -#define LM75_I2C_CLK RCC_APB1Periph_I2C1 -#define LM75_I2C_SCL_PIN GPIO_Pin_6 /* PB.06 */ -#define LM75_I2C_SCL_GPIO_PORT GPIOB /* GPIOB */ -#define LM75_I2C_SCL_GPIO_CLK RCC_AHBPeriph_GPIOB -#define LM75_I2C_SCL_SOURCE GPIO_PinSource6 -#define LM75_I2C_SCL_AF GPIO_AF_I2C1 -#define LM75_I2C_SDA_PIN GPIO_Pin_7 /* PB.07 */ -#define LM75_I2C_SDA_GPIO_PORT GPIOB /* GPIOB */ -#define LM75_I2C_SDA_GPIO_CLK RCC_AHBPeriph_GPIOB -#define LM75_I2C_SDA_SOURCE GPIO_PinSource7 -#define LM75_I2C_SDA_AF GPIO_AF_I2C1 -#define LM75_I2C_SMBUSALERT_PIN GPIO_Pin_5 /* PB.05 */ -#define LM75_I2C_SMBUSALERT_GPIO_PORT GPIOB /* GPIOB */ -#define LM75_I2C_SMBUSALERT_GPIO_CLK RCC_AHBPeriph_GPIOB -#define LM75_I2C_SMBUSALERT_SOURCE GPIO_PinSource5 -#define LM75_I2C_SMBUSALERT_AF GPIO_AF_I2C1 -#define LM75_I2C_DR ((uint32_t)0x40005410) - -#define LM75_DMA_CLK RCC_AHBPeriph_DMA1 -#define LM75_DMA_TX_CHANNEL DMA1_Channel6 -#define LM75_DMA_RX_CHANNEL DMA1_Channel7 -#define LM75_DMA_TX_TCFLAG DMA1_FLAG_TC6 -#define LM75_DMA_RX_TCFLAG DMA1_FLAG_TC7 - -/** - * @} - */ - -/** @addtogroup STM32L152_EVAL_LOW_LEVEL_I2C_EE - * @{ - */ -/** - * @brief I2C EEPROM Interface pins - */ - -#define sEE_I2C I2C1 -#define sEE_I2C_CLK RCC_APB1Periph_I2C1 -#define sEE_I2C_SCL_PIN GPIO_Pin_6 /* PB.06 */ -#define sEE_I2C_SCL_GPIO_PORT GPIOB /* GPIOB */ -#define sEE_I2C_SCL_GPIO_CLK RCC_AHBPeriph_GPIOB -#define sEE_I2C_SCL_SOURCE GPIO_PinSource6 -#define sEE_I2C_SCL_AF GPIO_AF_I2C1 -#define sEE_I2C_SDA_PIN GPIO_Pin_7 /* PB.07 */ -#define sEE_I2C_SDA_GPIO_PORT GPIOB /* GPIOB */ -#define sEE_I2C_SDA_GPIO_CLK RCC_AHBPeriph_GPIOB -#define sEE_I2C_SDA_SOURCE GPIO_PinSource7 -#define sEE_I2C_SDA_AF GPIO_AF_I2C1 -#define sEE_M24C64_32 - -#define sEE_I2C_DMA DMA1 -#define sEE_I2C_DMA_CHANNEL_TX DMA1_Channel6 -#define sEE_I2C_DMA_CHANNEL_RX DMA1_Channel7 -#define sEE_I2C_DMA_FLAG_TX_TC DMA1_IT_TC6 -#define sEE_I2C_DMA_FLAG_TX_GL DMA1_IT_GL6 -#define sEE_I2C_DMA_FLAG_RX_TC DMA1_IT_TC7 -#define sEE_I2C_DMA_FLAG_RX_GL DMA1_IT_GL7 -#define sEE_I2C_DMA_CLK RCC_AHBPeriph_DMA1 -#define sEE_I2C_DR_Address ((uint32_t)0x40005410) -#define sEE_USE_DMA - -#define sEE_I2C_DMA_TX_IRQn DMA1_Channel6_IRQn -#define sEE_I2C_DMA_RX_IRQn DMA1_Channel7_IRQn -#define sEE_I2C_DMA_TX_IRQHandler DMA1_Channel6_IRQHandler -#define sEE_I2C_DMA_RX_IRQHandler DMA1_Channel7_IRQHandler -#define sEE_I2C_DMA_PREPRIO 0 -#define sEE_I2C_DMA_SUBPRIO 0 - -#define sEE_DIRECTION_TX 0 -#define sEE_DIRECTION_RX 1 - -/* Time constant for the delay caclulation allowing to have a millisecond - incrementing counter. This value should be equal to (System Clock / 1000). - ie. if system clock = 24MHz then sEE_TIME_CONST should be 24. */ -#define sEE_TIME_CONST 24 - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Functions - * @{ - */ -void STM_EVAL_LEDInit(Led_TypeDef Led); -void STM_EVAL_LEDOn(Led_TypeDef Led); -void STM_EVAL_LEDOff(Led_TypeDef Led); -void STM_EVAL_LEDToggle(Led_TypeDef Led); -void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode); -uint32_t STM_EVAL_PBGetState(Button_TypeDef Button); -void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct); -void SD_LowLevel_DeInit(void); -void SD_LowLevel_Init(void); -void LM75_LowLevel_DeInit(void); -void LM75_LowLevel_Init(void); -void sEE_LowLevel_DeInit(void); -void sEE_LowLevel_Init(void); -void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L152_EVAL_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_glass_lcd.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_glass_lcd.c deleted file mode 100644 index da4bb04e6..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_glass_lcd.c +++ /dev/null @@ -1,855 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l152_eval_glass_lcd.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file includes the LCD Glass driver for Pacific Display - * (LCD_PD878, PD878-DP-FH-W-LV-6-RH) Module of STM32L152-EVAL board RevB. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l152_eval_glass_lcd.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32L152_EVAL - * @{ - */ - -/** @defgroup STM32L152_EVAL_GLASS_LCD - * @brief This file includes the LCD Glass driver for Pacific Display - * (LCD_PD878, PD878-DP-FH-W-LV-6-RH) Module of STM32L152-EVAL board. - * @{ - */ - -/** @defgroup STM32L152_EVAL_GLASS_LCD_Private_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32L152_EVAL_GLASS_LCD_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32L152_EVAL_GLASS_LCD_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32L152_EVAL_GLASS_LCD_Private_Variables - * @{ - */ - -/** - @verbatim -================================================================================ - GLASS LCD MAPPING -================================================================================ - A - -- ---------- - X \/ |\ |I /| - F| H | J |B - | \ | / | - --G-- --K-- - | /| \ | - E | L | N |C - | / |M \| _ - ----------- | |DP - D - - -A LCD character coding is based on the following matrix: - - -{ X , F , E , D } -{ I , J , K , N } -{ A , B , C , DP } -{ H , G , L , M } - -The character A for example is: -------------------------------- - { 0 , 1 , 1 , 0 } - { 0 , 0 , 1 , 0 } - { 1 , 1 , 1 , 0 } - { 0 , 1 , 0 , 0 } -------------------- -= 4 D 7 0 hex - -=> 'A' = 0x4D70 - - @endverbatim - */ - -/** - * @brief LETTERS AND NUMBERS MAPPING DEFINITION - */ -uint8_t digit[4]; /* Digit LCD RAM buffer */ -__I uint16_t mask[4] = {0xF000, 0x0F00, 0x00F0, 0x000F}; -__I uint8_t shift[4] = {0x0C, 0x08, 0x04, 0x00}; - -/* Letters and number map of PD_878 LCD */ -__I uint16_t LetterMap[26]= -{ -/* A B C D E F G H I */ -0x4D70, 0x6469, 0x4111, 0x6449, 0x4911, 0x4910, 0x4171, 0x0D70, 0x6009, -/* J K L M N O P Q R */ -0x0451, 0x0B12, 0x0111, 0x8750, 0x8552, 0x4551, 0x4D30, 0x4553, 0x4D32, -/* S T U V W X Y Z */ -0x4961, 0x6008, 0x0551, 0x0390, 0x05D2, 0x8282, 0x8208, 0x4281 -}; - -__I uint16_t NumberMap[10]= -{ -/* 0 1 2 3 4 5 6 7 8 9 */ -0x47D1, 0x0640, 0x4C31, 0x4C61, 0x0D60, 0x4961, 0x4971, 0x4440, 0x4D71, 0x4D61 -}; - -/** - * @} - */ - - -/** @defgroup STM32L152_EVAL_LCD_Private_Function_Prototypes - * @{ - */ -static void Convert(uint8_t* c, Point_Typedef point, Apostrophe_Typedef apostrophe); -static void delay(__IO uint32_t nCount); -static void LCD_GPIOConfig(void); - -/** - * @} - */ - -/** @defgroup STM32L152_EVAL_LCD_Private_Functions - * @{ - */ - -/** - * @brief Configures the LCD GLASS relative GPIO port IOs and LCD peripheral. - * @param None - * @retval None - */ -void LCD_GLASS_Init(void) -{ - LCD_InitTypeDef LCD_InitStructure; - - LCD_GPIOConfig(); /*!< Configure the LCD Glass GPIO pins */ - - /*!< Configure the LCD interface -------------------------------------------*/ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_LCD, ENABLE); /*!< Enable LCD APB1 Clock */ - - LCD_InitStructure.LCD_Prescaler = LCD_Prescaler_8; - LCD_InitStructure.LCD_Divider = LCD_Divider_16; - LCD_InitStructure.LCD_Duty = LCD_Duty_1_4; - LCD_InitStructure.LCD_Bias = LCD_Bias_1_3; - LCD_InitStructure.LCD_VoltageSource = LCD_VoltageSource_Internal; - LCD_Init(&LCD_InitStructure); - - /*!< Configure the Pulse On Duration */ - LCD_PulseOnDurationConfig(LCD_PulseOnDuration_2); - - /*!< Configure the LCD Contrast (3.51V) */ - LCD_ContrastConfig(LCD_Contrast_Level_7); - - /*!< Wait Until the LCD FCR register is synchronized */ - LCD_WaitForSynchro(); - - /*!< Enable LCD peripheral */ - LCD_Cmd(ENABLE); - - /*!< Wait Until the LCD is enabled */ - while(LCD_GetFlagStatus(LCD_FLAG_ENS) == RESET) - { - } - /*!< Wait Until the LCD Booster is ready */ - while(LCD_GetFlagStatus(LCD_FLAG_RDY) == RESET) - { - } -} - -/** - * @brief This function writes a char in the LCD RAM. - * @param ch: The character to dispaly. - * @param point: A point to add in front of char. - * This parameter can be one of the following values: - * @arg POINT_OFF: No point to add in front of char. - * @arg POINT_ON: Add a point in front of char. - * @param apostrophe: Flag indicating if a apostrophe has to be add in front - * of displayed character. - * This parameter can be one of the following values: - * @arg APOSTROPHE_OFF: No apostrophe to add in back of char. - * @arg APOSTROPHE_ON: Add an apostrophe in back of char. - * @param position: Position in the LCD of the caracter to write. - * This parameter can be any value in range [0:7]. - * @retval None - */ -void LCD_GLASS_DisplayChar(uint8_t* ch, Point_Typedef point, Apostrophe_Typedef apostrophe, uint8_t position) -{ - /*!< Wait Until the last LCD RAM update finish */ - while(LCD_GetFlagStatus(LCD_FLAG_UDR) != RESET) - { - } - /*!< LCD Write Char */ - LCD_GLASS_WriteChar(ch, point, apostrophe, position); - - /*!< Requesy LCD RAM update */ - LCD_UpdateDisplayRequest(); -} - -/** - * @brief This function writes a char in the LCD RAM. - * @param ptr: Pointer to string to display on the LCD Glass. - * @retval None - */ -void LCD_GLASS_DisplayString(uint8_t* ptr) -{ - uint32_t i = 0x00; - - /*!< Wait Until the last LCD RAM update finish */ - while(LCD_GetFlagStatus(LCD_FLAG_UDR) != RESET) - { - } - - /*!< Send the string character by character on lCD */ - while ((*ptr != 0) & (i < 8)) - { - /*!< Display one character on LCD */ - LCD_GLASS_WriteChar(ptr, POINT_OFF, APOSTROPHE_OFF, i); - /*!< Point on the next character */ - ptr++; - /*!< Increment the character counter */ - i++; - } - /*!< Requesy LCD RAM update */ - LCD_UpdateDisplayRequest(); -} - -/** - * @brief This function writes a char in the LCD RAM. - * @param ch: The character to dispaly. - * @param point: A point to add in front of char. - * This parameter can be one of the following values: - * @arg POINT_OFF : No point to add in front of char. - * @arg POINT_ON : Add a point in front of char. - * @param apostrophe: Flag indicating if a apostrophe has to be add in front - * of displayed character. - * This parameter can be one of the following values: - * @arg APOSTROPHE_OFF : No apostrophe to add in back of char. - * @arg APOSTROPHE_ON : Add an apostrophe in back of char. - * @param position: Position in the LCD of the caracter to write. - * This parameter can be any value in range [0:7]. - * @retval None - */ -void LCD_GLASS_WriteChar(uint8_t* ch, Point_Typedef point, Apostrophe_Typedef apostrophe, uint8_t position) -{ - uint32_t tmp = 0x00; - - Convert(ch, point, apostrophe); /*!< Convert the corresponding character */ - - switch (position) - { - case 7: - /*!< Clear the corresponding segments (SEG0, SEG1, SEG2, SEG3) */ - LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0xFFFFFFF0); - LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0xFFFFFFF0); - LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0xFFFFFFF0); - LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0xFFFFFFF0); - - /*!< Write the corresponding segments (SEG0, SEG1, SEG2, SEG3) */ - LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)(digit[0]); - LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)(digit[1]); - LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)(digit[2]); - LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)(digit[3]); - break; - - case 6: - /*!< Clear the corresponding segments (SEG4, SEG5, SEG6, SEG10) */ - LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0xFFFFFB8F); - LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0xFFFFFB8F); - LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0xFFFFFB8F); - LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0xFFFFFB8F); - - /*!< Write the corresponding segments (SEG4, SEG5, SEG6, SEG10) */ - tmp = (((digit[0] & 0x8) << 7) | ((digit[0]& 0x7) << 4)); - LCD->RAM[LCD_RAMRegister_0] |= (uint32_t) tmp; - tmp = (((digit[1] & 0x8) << 7) | ((digit[1]& 0x7) << 4)); - LCD->RAM[LCD_RAMRegister_2] |= (uint32_t) tmp; - tmp = (((digit[2] & 0x8) << 7) | ((digit[2]& 0x7) << 4)); - LCD->RAM[LCD_RAMRegister_4] |= (uint32_t) tmp; - tmp = (((digit[3] & 0x8) << 7) | ((digit[3]& 0x7) << 4)); - LCD->RAM[LCD_RAMRegister_6] |= (uint32_t) tmp; - break; - - case 5: - /*!< Clear the corresponding segments (SEG11, SEG16, SEG18, SEG19) */ - LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0xFFF2F7FF); - LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0xFFF2F7FF); - LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0xFFF2F7FF); - LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0xFFF2F7FF); - - /*!< Write the corresponding segments (SEG11, SEG16, SEG18, SEG19) */ - tmp = (((digit[0] & 0x1) << 11) | ((digit[0]& 0x2) << 15) | ((digit[0]& 0xC) << 16)); - LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)(tmp); - tmp = (((digit[1] & 0x1) << 11) | ((digit[1]& 0x2) << 15) | ((digit[1]& 0xC) << 16)); - LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)(tmp); - tmp = (((digit[2] & 0x1) << 11) | ((digit[2]& 0x2) << 15) | ((digit[2]& 0xC) << 16)); - LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)(tmp); - tmp = (((digit[3] & 0x1) << 11) | ((digit[3]& 0x2) << 15) | ((digit[3]& 0xC) << 16)); - LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)(tmp); - break; - - case 4: - /*!< Clear the corresponding segments (SEG20, SEG21, SEG22, SEG23) */ - LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0xFF0FFFFF); - LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0xFF0FFFFF); - LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0xFF0FFFFF); - LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0xFF0FFFFF); - - /*!< Write the corresponding segments (SEG20, SEG21, SEG22, SEG23) */ - LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)(digit[0] << 20); - LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)(digit[1] << 20); - LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)(digit[2] << 20); - LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)(digit[3] << 20); - break; - - case 3: - /*!< Clear the corresponding segments (SEG28, SEG29, SEG30, SEG31) */ - LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0x0FFFFFFF); - LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0x0FFFFFFF); - LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0x0FFFFFFF); - LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0x0FFFFFFF); - - /*!< Write the corresponding segments (SEG28, SEG29, SEG30, SEG31) */ - LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)(digit[0] << 28); - LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)(digit[1] << 28); - LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)(digit[2] << 28); - LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)(digit[3] << 28); - break; - - case 2: - /*!< Clear the corresponding segments (SEG32, SEG33, SEG34, SEG35) */ - LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)(0xFFFFFFF0); - LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)(0xFFFFFFF0); - LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)(0xFFFFFFF0); - LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)(0xFFFFFFF0); - - /*!< Write the corresponding segments (SEG32, SEG33, SEG34, SEG35) */ - LCD->RAM[LCD_RAMRegister_1] |= (uint32_t)(digit[0] << 0); - LCD->RAM[LCD_RAMRegister_3] |= (uint32_t)(digit[1] << 0); - LCD->RAM[LCD_RAMRegister_5] |= (uint32_t)(digit[2] << 0); - LCD->RAM[LCD_RAMRegister_7] |= (uint32_t)(digit[3] << 0); - break; - - case 1: - /*!< Clear the corresponding segments (SEG36, SEG37, SEG38, SEG39) */ - LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)(0xFFFFFF0F); - LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)(0xFFFFFF0F); - LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)(0xFFFFFF0F); - LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)(0xFFFFFF0F); - - /*!< Write the corresponding segments (SEG36, SEG37, SEG38, SEG39) */ - LCD->RAM[LCD_RAMRegister_1] |= (uint32_t)(digit[0] << 4); - LCD->RAM[LCD_RAMRegister_3] |= (uint32_t)(digit[1] << 4); - LCD->RAM[LCD_RAMRegister_5] |= (uint32_t)(digit[2] << 4); - LCD->RAM[LCD_RAMRegister_7] |= (uint32_t)(digit[3] << 4); - - break; - - case 0: - /*!< Clear the corresponding segments (SEG40, SEG41, SEG42, SEG43) */ - LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)(0xFFFFF0FF); - LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)(0xFFFFF0FF); - LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)(0xFFFFF0FF); - LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)(0xFFFFF0FF); - - /*!< Write the corresponding segments (SEG40, SEG41, SEG42, SEG43) */ - LCD->RAM[LCD_RAMRegister_1] |= (uint32_t)(digit[0] << 8); - LCD->RAM[LCD_RAMRegister_3] |= (uint32_t)(digit[1] << 8); - LCD->RAM[LCD_RAMRegister_5] |= (uint32_t)(digit[2] << 8); - LCD->RAM[LCD_RAMRegister_7] |= (uint32_t)(digit[3] << 8); - break; - } -} - -/** - * @brief Display a string in scrolling mode - * @note The LCD should be cleared before to start the write operation. - * @param ptr: Pointer to string to display on the LCD Glass. - * @param nScroll: Specifies how many time the message will be scrolled - * @param ScrollSpeed: Speciifes the speed of the scroll. - * Low value gives higher speed. - * @retval None - */ -void LCD_GLASS_ScrollString(uint8_t* ptr, uint16_t nScroll, uint16_t ScrollSpeed) -{ - uint8_t Repetition = 0; - uint8_t* ptr1; - uint8_t str[8] = ""; - ptr1 = ptr; - - LCD_GLASS_DisplayString(ptr1); - - delay(ScrollSpeed); - - for (Repetition = 0; Repetition < nScroll; Repetition++) - { - *(str + 1) = *ptr1; - *(str + 2) = *(ptr1 + 1); - *(str + 3) = *(ptr1 + 2); - *(str + 4) = *(ptr1 + 3); - *(str + 5) = *(ptr1 + 4); - *(str + 6) = *(ptr1 + 5); - *(str + 7) =*(ptr1 + 6); - *(str) = *(ptr1 + 7); - LCD_GLASS_Clear(); - LCD_GLASS_DisplayString(str); - delay(ScrollSpeed); - - *(str + 1) = *(ptr1 + 7); - *(str + 2) = *ptr1; - *(str + 3) = *(ptr1 + 1); - *(str + 4) = *(ptr1 + 2); - *(str + 5) = *(ptr1 + 3); - *(str + 6) = *(ptr1 + 4); - *(str + 7) = *(ptr1 + 5); - *(str) = *(ptr1 + 6); - LCD_GLASS_Clear(); - LCD_GLASS_DisplayString(str); - delay(ScrollSpeed); - - *(str + 1) = *(ptr1 + 6); - *(str + 2) = *(ptr1 + 7); - *(str + 3) = *ptr1; - *(str + 4) = *(ptr1 + 1); - *(str + 5) = *(ptr1 + 2); - *(str + 6) = *(ptr1 + 3); - *(str + 7) = *(ptr1 + 4); - *(str) = *(ptr1 + 5); - LCD_GLASS_Clear(); - LCD_GLASS_DisplayString(str); - delay(ScrollSpeed); - - *(str + 1) = *(ptr1 + 5); - *(str + 2) = *(ptr1 + 6); - *(str + 3) = *(ptr1 + 7); - *(str + 4) = *ptr1; - *(str + 5) = *(ptr1 + 1); - *(str + 6) = *(ptr1 + 2); - *(str + 7) = *(ptr1 + 3); - *(str) = *(ptr1 + 4); - LCD_GLASS_Clear(); - LCD_GLASS_DisplayString(str); - delay(ScrollSpeed); - - *(str + 1) = *(ptr1 + 4); - *(str + 2) = *(ptr1 + 5); - *(str + 3) = *(ptr1 + 6); - *(str + 4) = *(ptr1 + 7); - *(str + 5) = *ptr1; - *(str + 6) = *(ptr1 + 1); - *(str + 7) = *(ptr1 + 2); - *(str) = *(ptr1 + 3); - LCD_GLASS_Clear(); - LCD_GLASS_DisplayString(str); - delay(ScrollSpeed); - - *(str + 1) = *(ptr1 + 3); - *(str + 2) = *(ptr1 + 4); - *(str + 3) = *(ptr1 + 5); - *(str + 4) = *(ptr1 + 6); - *(str + 5) = *(ptr1 + 7); - *(str + 6) = *ptr1; - *(str + 7) = *(ptr1 + 1); - *(str) = *(ptr1 + 2); - LCD_GLASS_Clear(); - LCD_GLASS_DisplayString(str); - delay(ScrollSpeed); - - *(str + 1) = *(ptr1 + 2); - *(str + 2) = *(ptr1 + 3); - *(str + 3) = *(ptr1 + 4); - *(str + 4) = *(ptr1 + 5); - *(str + 5) = *(ptr1 + 6); - *(str + 6) = *(ptr1 + 7); - *(str + 7) = *ptr1; - *(str) = *(ptr1 + 1); - LCD_GLASS_Clear(); - LCD_GLASS_DisplayString(str); - delay(ScrollSpeed); - - *(str + 1) = *(ptr1 + 1); - *(str + 2) = *(ptr1 + 2); - *(str + 3) = *(ptr1 + 3); - *(str + 4) = *(ptr1 + 4); - *(str + 5) = *(ptr1 + 5); - *(str + 6) = *(ptr1 + 6); - *(str + 7) = *(ptr1 + 7); - *(str) = *(ptr1); - LCD_GLASS_Clear(); - LCD_GLASS_DisplayString(str); - delay(ScrollSpeed); - } -} - -/** - * @brief This function Clear a char in the LCD RAM. - * @param position: Position in the LCD of the caracter to write. - * This parameter can be any value in range [0:7]. - * @retval None - */ -void LCD_GLASS_ClearChar(uint8_t position) -{ - switch (position) - { - case 7: - /*!< Clear the corresponding segments (SEG0, SEG1, SEG2, SEG3) */ - LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0xFFFFFFF0); - LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0xFFFFFFF0); - LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0xFFFFFFF0); - LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0xFFFFFFF0); - break; - - case 6: - /*!< Clear the corresponding segments (SEG4, SEG5, SEG6, SEG10) */ - LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0xFFFFFB8F); - LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0xFFFFFB8F); - LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0xFFFFFB8F); - LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0xFFFFFB8F); - break; - - case 5: - /*!< Clear the corresponding segments (SEG11, SEG16, SEG18, SEG19) */ - LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0xFFF2F7FF); - LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0xFFF2F7FF); - LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0xFFF2F7FF); - LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0xFFF2F7FF); - break; - - case 4: - /*!< Clear the corresponding segments (SEG20, SEG21, SEG22, SEG23) */ - LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0xFF0FFFFF); - LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0xFF0FFFFF); - LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0xFF0FFFFF); - LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0xFF0FFFFF); - break; - - case 3: - /*!< Clear the corresponding segments (SEG28, SEG29, SEG30, SEG31) */ - LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0x0FFFFFFF); - LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0x0FFFFFFF); - LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0x0FFFFFFF); - LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0x0FFFFFFF); - break; - - case 2: - /*!< Clear the corresponding segments (SEG32, SEG33, SEG34, SEG35) */ - LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)(0xFFFFFFF0); - LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)(0xFFFFFFF0); - LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)(0xFFFFFFF0); - LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)(0xFFFFFFF0); - break; - - case 1: - /*!< Clear the corresponding segments (SEG36, SEG37, SEG38, SEG39) */ - LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)(0xFFFFFF0F); - LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)(0xFFFFFF0F); - LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)(0xFFFFFF0F); - LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)(0xFFFFFF0F); - break; - - case 0: - /*!< Clear the corresponding segments (SEG40, SEG41, SEG42, SEG43) */ - LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)(0xFFFFF0FF); - LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)(0xFFFFF0FF); - LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)(0xFFFFF0FF); - LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)(0xFFFFF0FF); - break; - } -} - -/** - * @brief This function Clear the whole LCD RAM. - * @param None - * @retval None - */ -void LCD_GLASS_Clear(void) -{ - uint32_t counter = 0; - - for (counter = 0; counter < 0x0F; counter++) - { - LCD->RAM[counter] = (uint32_t)0x00; - } -} - -/** - * @brief Converts an ascii char to an LCD digit. - * @param c: Char to display. - * @param point: A point to add in front of char. - * This parameter can be one of the following values: - * @arg POINT_OFF : No point to add in front of char. - * @arg POINT_ON : Add a point in front of char. - * @param apostrophe: Flag indicating if a apostrophe has to be add in front - * of displayed character. - * This parameter can be one of the following values: - * @arg APOSTROPHE_OFF : No apostrophe to add in back of char. - * @arg APOSTROPHE_ON : Add an apostrophe in back of char. - * @retval None - */ -static void Convert(uint8_t* c, Point_Typedef point, Apostrophe_Typedef apostrophe) -{ - uint16_t ch = 0, tmp = 0; - uint8_t i = 0; - - /*!< The character c is a letter in upper case*/ - if ((*c < 0x5B) & (*c > 0x40)) - { - ch = LetterMap[*c - 0x41]; - } - - /*!< The character c is a number*/ - if ((*c < 0x3A) & (*c > 0x2F)) - { - ch = NumberMap[*c - 0x30]; - } - - /*!< The character c is a space character */ - if (*c == 0x20) - { - ch =0x00; - } - - /*!< Set the DP seg in the character that can be displayed if the point is on */ - if (point == POINT_ON) - { - ch |= 0x0004; - } - - /*!< Set the X seg in the character that can be displayed if the apostrophe is on */ - if (apostrophe == APOSTROPHE_ON) - { - ch |= 0x1000; - } - - for (i = 0; i < 4; i++) - { - tmp = ch & mask[i]; - digit[i] =(uint8_t)(tmp >> shift[i]); - } -} - -/** - * @brief Configures the LCD Segments and Coms GPIOs. - * @param None - * @retval None - */ -static void LCD_GPIOConfig(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< Enable GPIOA, GPIOB, GPIOC, GPIOD and GPIOE AHB Clocks */ - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC - | RCC_AHBPeriph_GPIOD | RCC_AHBPeriph_GPIOE, ENABLE); - - /*!< Connect PA.08 to LCD COM0 */ - GPIO_PinAFConfig(GPIOA, GPIO_PinSource8, GPIO_AF_LCD); - - /*!< Connect PA.09 to LCD COM1 */ - GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_LCD); - - /*!< Connect PA.10 to LCD COM2 */ - GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_LCD); - - /*!< Connect PB.09 to LCD COM3 */ - GPIO_PinAFConfig(GPIOB, GPIO_PinSource9, GPIO_AF_LCD); - - /*!< Connect PA.01 to LCD SEG0 */ - GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_LCD); - - /*!< Connect PA.02 to LCD SEG1 */ - GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_LCD); - - /*!< Connect PA.03 to LCD SEG2 */ - GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_LCD); - - /*!< Connect PA.06 to LCD SEG3 */ - GPIO_PinAFConfig(GPIOA, GPIO_PinSource6, GPIO_AF_LCD); - - /*!< Connect PA.07 to LCD SEG4 */ - GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_LCD); - - /*!< Connect PB.00 to LCD SEG5 */ - GPIO_PinAFConfig(GPIOB, GPIO_PinSource0, GPIO_AF_LCD); - - /*!< Connect PB.01 to LCD SEG6 */ - GPIO_PinAFConfig(GPIOB, GPIO_PinSource1, GPIO_AF_LCD); - - /*!< Connect PB.10 to LCD SEG10 */ - GPIO_PinAFConfig(GPIOB, GPIO_PinSource10, GPIO_AF_LCD); - - /*!< Connect PB.11 to LCD SEG11 */ - GPIO_PinAFConfig(GPIOB, GPIO_PinSource11, GPIO_AF_LCD); - - /*!< Connect PB.08 to LCD SEG16 */ - GPIO_PinAFConfig(GPIOB, GPIO_PinSource8, GPIO_AF_LCD); - - /*!< Connect PC.00 to LCD SEG18 */ - GPIO_PinAFConfig(GPIOC, GPIO_PinSource0, GPIO_AF_LCD); - - /*!< Connect PC.01 to LCD SEG19 */ - GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_LCD); - - /*!< Connect PC.02 to LCD SEG20 */ - GPIO_PinAFConfig(GPIOC, GPIO_PinSource2, GPIO_AF_LCD); - - /*!< Connect PC.03 to LCD SEG21 */ - GPIO_PinAFConfig(GPIOC, GPIO_PinSource3, GPIO_AF_LCD); - - /*!< Connect PC.04 to LCD SEG22 */ - GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_LCD); - - /*!< Connect PC.05 to LCD SEG23 */ - GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_LCD); - - /*!< Connect PD.08 to LCD SEG28 */ - GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_LCD); - - /*!< Connect PD.09 to LCD SEG29 */ - GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_LCD); - - /*!< Connect PD.10 to LCD SEG30 */ - GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_LCD); - - /*!< Connect PD.11 to LCD SEG31 */ - GPIO_PinAFConfig(GPIOD, GPIO_PinSource11, GPIO_AF_LCD); - - /*!< Connect PD.12 to LCD SEG32 */ - GPIO_PinAFConfig(GPIOD, GPIO_PinSource12, GPIO_AF_LCD); - - /*!< Connect PD.13 to LCD SEG33 */ - GPIO_PinAFConfig(GPIOD, GPIO_PinSource13, GPIO_AF_LCD); - - /*!< Connect PD.14 to LCD SEG34 */ - GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_LCD); - - /*!< Connect PD.15 to LCD SEG35 */ - GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_LCD); - - /*!< Connect PE.00 to LCD SEG36 */ - GPIO_PinAFConfig(GPIOE, GPIO_PinSource0, GPIO_AF_LCD); - - /*!< Connect PE.01 to LCD SEG37 */ - GPIO_PinAFConfig(GPIOE, GPIO_PinSource1, GPIO_AF_LCD); - - /*!< Connect PE.02 to LCD SEG38 */ - GPIO_PinAFConfig(GPIOE, GPIO_PinSource2, GPIO_AF_LCD); - - /*!< Connect PE.03 to LCD SEG39 */ - GPIO_PinAFConfig(GPIOE, GPIO_PinSource3, GPIO_AF_LCD); - - /*!< Connect PC.10 to LCD SEG40 */ - GPIO_PinAFConfig(GPIOC, GPIO_PinSource10, GPIO_AF_LCD); - - /*!< Connect PC.11 to LCD SEG41 */ - GPIO_PinAFConfig(GPIOC, GPIO_PinSource11, GPIO_AF_LCD); - - /*!< Connect PC.12 to LCD SEG42 */ - GPIO_PinAFConfig(GPIOC, GPIO_PinSource12, GPIO_AF_LCD); - - /*!< Connect PD.02 to LCD SEG43 */ - GPIO_PinAFConfig(GPIOD, GPIO_PinSource2, GPIO_AF_LCD); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_6 | \ - GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 | \ - GPIO_Pin_10 | GPIO_Pin_11; - GPIO_Init(GPIOB, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | \ - GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_10 | GPIO_Pin_11 | \ - GPIO_Pin_12; - GPIO_Init(GPIOC, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | \ - GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | \ - GPIO_Pin_15; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3; - GPIO_Init(GPIOE, &GPIO_InitStructure); -} - -/** - * @brief Inserts a delay time. - * @param nCount: specifies the delay time length. - * @retval None - */ -static void delay(__IO uint32_t nCount) -{ - __IO uint32_t index = 0; - for(index = (0xFF * nCount); index != 0; index--) - { - } -} - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_glass_lcd.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_glass_lcd.h deleted file mode 100644 index 47a425e17..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_glass_lcd.h +++ /dev/null @@ -1,125 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l152_eval_glass_lcd.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief Header file for stm32l152_eval_glass_lcd.c module. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L152_EVAL_GLASS_LCD_H -#define __STM32L152_EVAL_GLASS_LCD_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32L152_EVAL - * @{ - */ - -/** @addtogroup STM32L152_EVAL_GLASS_LCD - * @{ - */ - - -/** @defgroup STM32L152_EVAL_GLASS_LCD_Exported_Types - * @{ - */ -typedef enum -{ - POINT_OFF = 0, - POINT_ON = 1 -}Point_Typedef; - -typedef enum -{ - APOSTROPHE_OFF = 0, - APOSTROPHE_ON = 1 -}Apostrophe_Typedef; -/** - * @} - */ - -/** @defgroup STM32L152_EVAL_GLASS_LCD_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @defgroup STM32L152_EVAL_GLASS_LCD_Exported_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32L152_EVAL_GLASS_LCD_Exported_Functions - * @{ - */ -void LCD_GLASS_Init(void); -void LCD_GLASS_DisplayChar(uint8_t* ch, Point_Typedef point, Apostrophe_Typedef apostrophe,uint8_t position); -void LCD_GLASS_DisplayString(uint8_t* ptr); -void LCD_GLASS_WriteChar(uint8_t* ch, Point_Typedef point, Apostrophe_Typedef apostrophe,uint8_t position); -void LCD_GLASS_ClearChar(uint8_t position); -void LCD_GLASS_Clear(void); -void LCD_GLASS_ScrollString(uint8_t* ptr, uint16_t nScroll, uint16_t ScrollSpeed); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L152_EVAL_GLASS_LCD_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_ee.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_ee.c deleted file mode 100644 index 0f85b8a37..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_ee.c +++ /dev/null @@ -1,810 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l152_eval_i2c_ee.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file provides a set of functions needed to manage an I2C M24CXX - * EEPROM memory. - * - * =================================================================== - * Notes: - * - This driver is intended for STM32L1xx families devices only. - * - There is no I2C EEPROM memory available in STM32L152-EVAL board, - * to use this driver you have to build your own hardware. - * =================================================================== - * - * It implements a high level communication layer for read and write - * from/to this memory. The needed STM32 hardware resources (I2C and - * GPIO) are defined in stm32l152_eval.h file, and the initialization is - * performed in sEE_LowLevel_Init() function declared in stm32l152_eval.c - * file. - * You can easily tailor this driver to any other development board, - * by just adapting the defines for hardware resources and - * sEE_LowLevel_Init() function. - * - * @note In this driver, basic read and write functions (sEE_ReadBuffer() - * and sEE_WritePage()) use the DMA to perform the data transfer - * to/from EEPROM memory (except when number of requested data is - * equal to 1). Thus, after calling these two functions, user - * application may perform other tasks while DMA is transferring - * data. The application should then monitor the variable holding - * the number of data in order to determine when the transfer is - * completed (variable decremented to 0). Stopping transfer tasks - * are performed into DMA interrupt handlers (which are integrated - * into this driver). - * - * +-----------------------------------------------------------------+ - * | Pin assignment | - * +---------------------------------------+-----------+-------------+ - * | STM32 I2C Pins | sEE | Pin | - * +---------------------------------------+-----------+-------------+ - * | . | E0(GND) | 1 (0V) | - * | . | E1(GND) | 2 (0V) | - * | . | E2(GND) | 3 (0V) | - * | . | E0(VSS) | 4 (0V) | - * | sEE_I2C_SDA_PIN/ SDA | SDA | 5 | - * | sEE_I2C_SCL_PIN/ SCL | SCL | 6 | - * | . | /WC(VDD)| 7 (3.3V) | - * | . | VDD | 8 (3.3V) | - * +---------------------------------------+-----------+-------------+ - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l152_eval_i2c_ee.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32L152_EVAL - * @{ - */ - -/** @addtogroup STM32L152_EVAL_I2C_EE - * @brief This file includes the I2C EEPROM driver of STM32L152-EVAL board. - * @{ - */ - -/** @defgroup STM32L152_EVAL_I2C_EE_Private_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32L152_EVAL_I2C_EE_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32L152_EVAL_I2C_EE_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32L152_EVAL_I2C_EE_Private_Variables - * @{ - */ -__IO uint16_t sEEAddress = 0; -__IO uint32_t sEETimeout = sEE_LONG_TIMEOUT; -__IO uint16_t* sEEDataReadPointer; -__IO uint8_t* sEEDataWritePointer; -__IO uint8_t sEEDataNum; -/** - * @} - */ - - -/** @defgroup STM32L152_EVAL_I2C_EE_Private_Function_Prototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32L152_EVAL_I2C_EE_Private_Functions - * @{ - */ - -/** - * @brief DeInitializes peripherals used by the I2C EEPROM driver. - * @param None - * @retval None - */ -void sEE_DeInit(void) -{ - sEE_LowLevel_DeInit(); -} - -/** - * @brief Initializes peripherals used by the I2C EEPROM driver. - * @param None - * @retval None - */ -void sEE_Init(void) -{ - I2C_InitTypeDef I2C_InitStructure; - - sEE_LowLevel_Init(); - - /*!< I2C configuration */ - /* sEE_I2C configuration */ - I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; - I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2; - I2C_InitStructure.I2C_OwnAddress1 = I2C_SLAVE_ADDRESS7; - I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; - I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; - I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED; - - /* sEE_I2C Peripheral Enable */ - I2C_Cmd(sEE_I2C, ENABLE); - /* Apply sEE_I2C configuration after enabling it */ - I2C_Init(sEE_I2C, &I2C_InitStructure); - - /* Enable the sEE_I2C peripheral DMA requests */ - I2C_DMACmd(sEE_I2C, ENABLE); - -#if defined (sEE_M24C64_32) - /*!< Select the EEPROM address according to the state of E0, E1, E2 pins */ - sEEAddress = sEE_HW_ADDRESS; -#elif defined (sEE_M24C08) - /*!< depending on the sEE Address selected in the i2c_ee.h file */ - #ifdef sEE_Block0_ADDRESS - /*!< Select the sEE Block0 to write on */ - sEEAddress = sEE_Block0_ADDRESS; - #endif - - #ifdef sEE_Block1_ADDRESS - /*!< Select the sEE Block1 to write on */ - sEEAddress = sEE_Block1_ADDRESS; - #endif - - #ifdef sEE_Block2_ADDRESS - /*!< Select the sEE Block2 to write on */ - sEEAddress = sEE_Block2_ADDRESS; - #endif - - #ifdef sEE_Block3_ADDRESS - /*!< Select the sEE Block3 to write on */ - sEEAddress = sEE_Block3_ADDRESS; - #endif -#endif /*!< sEE_M24C64_32 */ -} - -/** - * @brief Reads a block of data from the EEPROM. - * @param pBuffer : pointer to the buffer that receives the data read from - * the EEPROM. - * @param ReadAddr : EEPROM's internal address to start reading from. - * @param NumByteToRead : pointer to the variable holding number of bytes to - * be read from the EEPROM. - * - * @note The variable pointed by NumByteToRead is reset to 0 when all the - * data are read from the EEPROM. Application should monitor this - * variable in order know when the transfer is complete. - * - * @note When number of data to be read is higher than 1, this function just - * configures the communication and enable the DMA channel to transfer data. - * Meanwhile, the user application may perform other tasks. - * When number of data to be read is 1, then the DMA is not used. The byte - * is read in polling mode. - * - * @retval sEE_OK (0) if operation is correctly performed, else return value - * different from sEE_OK (0) or the timeout user callback. - */ -uint32_t sEE_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t* NumByteToRead) -{ - /* Set the pointer to the Number of data to be read. This pointer will be used - by the DMA Transfer Completer interrupt Handler in order to reset the - variable to 0. User should check on this variable in order to know if the - DMA transfer has been complete or not. */ - sEEDataReadPointer = NumByteToRead; - - /*!< While the bus is busy */ - sEETimeout = sEE_LONG_TIMEOUT; - while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BUSY)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /*!< Send START condition */ - I2C_GenerateSTART(sEE_I2C, ENABLE); - - /*!< Test on EV5 and clear it (cleared by reading SR1 then writing to DR) */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /*!< Send EEPROM address for write */ - I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Transmitter); - - /*!< Test on EV6 and clear it */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - -#ifdef sEE_M24C08 - - /*!< Send the EEPROM's internal address to read from: Only one byte address */ - I2C_SendData(sEE_I2C, ReadAddr); - -#elif defined (sEE_M24C64_32) - - /*!< Send the EEPROM's internal address to read from: MSB of the address first */ - I2C_SendData(sEE_I2C, (uint8_t)((ReadAddr & 0xFF00) >> 8)); - - /*!< Test on EV8 and clear it */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTING)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /*!< Send the EEPROM's internal address to read from: LSB of the address */ - I2C_SendData(sEE_I2C, (uint8_t)(ReadAddr & 0x00FF)); - -#endif /*!< sEE_M24C08 */ - - /*!< Test on EV8 and clear it */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BTF) == RESET) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /*!< Send STRAT condition a second time */ - I2C_GenerateSTART(sEE_I2C, ENABLE); - - /*!< Test on EV5 and clear it (cleared by reading SR1 then writing to DR) */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /*!< Send EEPROM address for read */ - I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Receiver); - - /* If number of data to be read is 1, then DMA couldn't be used */ - /* One Byte Master Reception procedure (POLLING) ---------------------------*/ - if ((uint16_t)(*NumByteToRead) < 2) - { - /* Wait on ADDR flag to be set (ADDR is still not cleared at this level */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_ADDR) == RESET) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /*!< Disable Acknowledgement */ - I2C_AcknowledgeConfig(sEE_I2C, DISABLE); - - /* Clear ADDR register by reading SR1 then SR2 register (SR1 has already been read) */ - (void)sEE_I2C->SR2; - - /*!< Send STOP Condition */ - I2C_GenerateSTOP(sEE_I2C, ENABLE); - - /* Wait for the byte to be received */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_RXNE) == RESET) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /*!< Read the byte received from the EEPROM */ - *pBuffer = I2C_ReceiveData(sEE_I2C); - - /*!< Decrement the read bytes counter */ - (uint16_t)(*NumByteToRead)--; - - /* Wait to make sure that STOP control bit has been cleared */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(sEE_I2C->CR1 & I2C_CR1_STOP) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /*!< Re-Enable Acknowledgement to be ready for another reception */ - I2C_AcknowledgeConfig(sEE_I2C, ENABLE); - } - else/* More than one Byte Master Reception procedure (DMA) -----------------*/ - { - /*!< Test on EV6 and clear it */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /* Configure the DMA Rx Channel with the buffer address and the buffer size */ - sEE_LowLevel_DMAConfig((uint32_t)pBuffer, (uint16_t)(*NumByteToRead), sEE_DIRECTION_RX); - - /* Inform the DMA that the next End Of Transfer Signal will be the last one */ - I2C_DMALastTransferCmd(sEE_I2C, ENABLE); - - /* Enable the DMA Rx Channel */ - DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, ENABLE); - } - - /* If all operations OK, return sEE_OK (0) */ - return sEE_OK; -} - -/** - * @brief Writes more than one byte to the EEPROM with a single WRITE cycle. - * - * @note The number of bytes (combined to write start address) must not - * cross the EEPROM page boundary. This function can only write into - * the boundaries of an EEPROM page. - * This function doesn't check on boundaries condition (in this driver - * the function sEE_WriteBuffer() which calls sEE_WritePage() is - * responsible of checking on Page boundaries). - * - * @param pBuffer : pointer to the buffer containing the data to be written to - * the EEPROM. - * @param WriteAddr : EEPROM's internal address to write to. - * @param NumByteToWrite : pointer to the variable holding number of bytes to - * be written into the EEPROM. - * - * @note The variable pointed by NumByteToWrite is reset to 0 when all the - * data are written to the EEPROM. Application should monitor this - * variable in order know when the transfer is complete. - * - * @note This function just configure the communication and enable the DMA - * channel to transfer data. Meanwhile, the user application may perform - * other tasks in parallel. - * - * @retval sEE_OK (0) if operation is correctly performed, else return value - * different from sEE_OK (0) or the timeout user callback. - */ -uint32_t sEE_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t* NumByteToWrite) -{ - /* Set the pointer to the Number of data to be written. This pointer will be used - by the DMA Transfer Completer interrupt Handler in order to reset the - variable to 0. User should check on this variable in order to know if the - DMA transfer has been complete or not. */ - sEEDataWritePointer = NumByteToWrite; - - /*!< While the bus is busy */ - sEETimeout = sEE_LONG_TIMEOUT; - while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BUSY)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /*!< Send START condition */ - I2C_GenerateSTART(sEE_I2C, ENABLE); - - /*!< Test on EV5 and clear it */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /*!< Send EEPROM address for write */ - sEETimeout = sEE_FLAG_TIMEOUT; - I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Transmitter); - - /*!< Test on EV6 and clear it */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - -#ifdef sEE_M24C08 - - /*!< Send the EEPROM's internal address to write to : only one byte Address */ - I2C_SendData(sEE_I2C, WriteAddr); - -#elif defined(sEE_M24C64_32) - - /*!< Send the EEPROM's internal address to write to : MSB of the address first */ - I2C_SendData(sEE_I2C, (uint8_t)((WriteAddr & 0xFF00) >> 8)); - - /*!< Test on EV8 and clear it */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTING)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /*!< Send the EEPROM's internal address to write to : LSB of the address */ - I2C_SendData(sEE_I2C, (uint8_t)(WriteAddr & 0x00FF)); - -#endif /*!< sEE_M24C08 */ - - /*!< Test on EV8 and clear it */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTING)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /* Configure the DMA Tx Channel with the buffer address and the buffer size */ - sEE_LowLevel_DMAConfig((uint32_t)pBuffer, (uint8_t)(*NumByteToWrite), sEE_DIRECTION_TX); - - /* Enable the DMA Tx Channel */ - DMA_Cmd(sEE_I2C_DMA_CHANNEL_TX, ENABLE); - - /* If all operations OK, return sEE_OK (0) */ - return sEE_OK; -} - -/** - * @brief Writes buffer of data to the I2C EEPROM. - * @param pBuffer : pointer to the buffer containing the data to be written - * to the EEPROM. - * @param WriteAddr : EEPROM's internal address to write to. - * @param NumByteToWrite : number of bytes to write to the EEPROM. - * @retval None - */ -void sEE_WriteBuffer(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite) -{ - uint8_t NumOfPage = 0, NumOfSingle = 0, count = 0; - uint16_t Addr = 0; - - Addr = WriteAddr % sEE_PAGESIZE; - count = sEE_PAGESIZE - Addr; - NumOfPage = NumByteToWrite / sEE_PAGESIZE; - NumOfSingle = NumByteToWrite % sEE_PAGESIZE; - - /*!< If WriteAddr is sEE_PAGESIZE aligned */ - if(Addr == 0) - { - /*!< If NumByteToWrite < sEE_PAGESIZE */ - if(NumOfPage == 0) - { - /* Store the number of data to be written */ - sEEDataNum = NumOfSingle; - /* Start writing data */ - sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); - /* Wait transfer through DMA to be complete */ - sEETimeout = sEE_LONG_TIMEOUT; - while (sEEDataNum > 0) - { - if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; - } - sEE_WaitEepromStandbyState(); - } - /*!< If NumByteToWrite > sEE_PAGESIZE */ - else - { - while(NumOfPage--) - { - /* Store the number of data to be written */ - sEEDataNum = sEE_PAGESIZE; - sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); - /* Wait transfer through DMA to be complete */ - sEETimeout = sEE_LONG_TIMEOUT; - while (sEEDataNum > 0) - { - if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; - } - sEE_WaitEepromStandbyState(); - WriteAddr += sEE_PAGESIZE; - pBuffer += sEE_PAGESIZE; - } - - if(NumOfSingle!=0) - { - /* Store the number of data to be written */ - sEEDataNum = NumOfSingle; - sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); - /* Wait transfer through DMA to be complete */ - sEETimeout = sEE_LONG_TIMEOUT; - while (sEEDataNum > 0) - { - if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; - } - sEE_WaitEepromStandbyState(); - } - } - } - /*!< If WriteAddr is not sEE_PAGESIZE aligned */ - else - { - /*!< If NumByteToWrite < sEE_PAGESIZE */ - if(NumOfPage== 0) - { - /*!< If the number of data to be written is more than the remaining space - in the current page: */ - if (NumByteToWrite > count) - { - /* Store the number of data to be written */ - sEEDataNum = count; - /*!< Write the data conained in same page */ - sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); - /* Wait transfer through DMA to be complete */ - sEETimeout = sEE_LONG_TIMEOUT; - while (sEEDataNum > 0) - { - if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; - } - sEE_WaitEepromStandbyState(); - - /* Store the number of data to be written */ - sEEDataNum = (NumByteToWrite - count); - /*!< Write the remaining data in the following page */ - sEE_WritePage((uint8_t*)(pBuffer + count), (WriteAddr + count), (uint8_t*)(&sEEDataNum)); - /* Wait transfer through DMA to be complete */ - sEETimeout = sEE_LONG_TIMEOUT; - while (sEEDataNum > 0) - { - if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; - } - sEE_WaitEepromStandbyState(); - } - else - { - /* Store the number of data to be written */ - sEEDataNum = NumOfSingle; - sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); - /* Wait transfer through DMA to be complete */ - sEETimeout = sEE_LONG_TIMEOUT; - while (sEEDataNum > 0) - { - if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; - } - sEE_WaitEepromStandbyState(); - } - } - /*!< If NumByteToWrite > sEE_PAGESIZE */ - else - { - NumByteToWrite -= count; - NumOfPage = NumByteToWrite / sEE_PAGESIZE; - NumOfSingle = NumByteToWrite % sEE_PAGESIZE; - - if(count != 0) - { - /* Store the number of data to be written */ - sEEDataNum = count; - sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); - /* Wait transfer through DMA to be complete */ - sEETimeout = sEE_LONG_TIMEOUT; - while (sEEDataNum > 0) - { - if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; - } - sEE_WaitEepromStandbyState(); - WriteAddr += count; - pBuffer += count; - } - - while(NumOfPage--) - { - /* Store the number of data to be written */ - sEEDataNum = sEE_PAGESIZE; - sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); - /* Wait transfer through DMA to be complete */ - sEETimeout = sEE_LONG_TIMEOUT; - while (sEEDataNum > 0) - { - if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; - } - sEE_WaitEepromStandbyState(); - WriteAddr += sEE_PAGESIZE; - pBuffer += sEE_PAGESIZE; - } - if(NumOfSingle != 0) - { - /* Store the number of data to be written */ - sEEDataNum = NumOfSingle; - sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); - /* Wait transfer through DMA to be complete */ - sEETimeout = sEE_LONG_TIMEOUT; - while (sEEDataNum > 0) - { - if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; - } - sEE_WaitEepromStandbyState(); - } - } - } -} - -/** - * @brief Wait for EEPROM Standby state. - * - * @note This function allows to wait and check that EEPROM has finished the - * last operation. It is mostly used after Write operation: after receiving - * the buffer to be written, the EEPROM may need additional time to actually - * perform the write operation. During this time, it doesn't answer to - * I2C packets addressed to it. Once the write operation is complete - * the EEPROM responds to its address. - * - * @param None - * @retval sEE_OK (0) if operation is correctly performed, else return value - * different from sEE_OK (0) or the timeout user callback. - */ -uint32_t sEE_WaitEepromStandbyState(void) -{ - __IO uint16_t tmpSR1 = 0; - __IO uint32_t sEETrials = 0; - - /*!< While the bus is busy */ - sEETimeout = sEE_LONG_TIMEOUT; - while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BUSY)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /* Keep looping till the slave acknowledge his address or maximum number - of trials is reached (this number is defined by sEE_MAX_TRIALS_NUMBER define - in stm32_eval_i2c_ee.h file) */ - while (1) - { - /*!< Send START condition */ - I2C_GenerateSTART(sEE_I2C, ENABLE); - - /*!< Test on EV5 and clear it */ - sEETimeout = sEE_FLAG_TIMEOUT; - while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT)) - { - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - - /*!< Send EEPROM address for write */ - I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Transmitter); - - /* Wait for ADDR flag to be set (Slave acknowledged his address) */ - sEETimeout = sEE_LONG_TIMEOUT; - do - { - /* Get the current value of the SR1 register */ - tmpSR1 = sEE_I2C->SR1; - - /* Update the timeout value and exit if it reach 0 */ - if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); - } - /* Keep looping till the Address is acknowledged or the AF flag is - set (address not acknowledged at time) */ - while((tmpSR1 & (I2C_SR1_ADDR | I2C_SR1_AF)) == 0); - - /* Check if the ADDR flag has been set */ - if (tmpSR1 & I2C_SR1_ADDR) - { - /* Clear ADDR Flag by reading SR1 then SR2 registers (SR1 have already - been read) */ - (void)sEE_I2C->SR2; - - /*!< STOP condition */ - I2C_GenerateSTOP(sEE_I2C, ENABLE); - - /* Exit the function */ - return sEE_OK; - } - else - { - /*!< Clear AF flag */ - I2C_ClearFlag(sEE_I2C, I2C_FLAG_AF); - } - - /* Check if the maximum allowed numbe of trials has bee reached */ - if (sEETrials++ == sEE_MAX_TRIALS_NUMBER) - { - /* If the maximum number of trials has been reached, exit the function */ - return sEE_TIMEOUT_UserCallback(); - } - } -} - -/** - * @brief This function handles the DMA Tx Channel interrupt Handler. - * @param None - * @retval None - */ -void sEE_I2C_DMA_TX_IRQHandler(void) -{ - /* Check if the DMA transfer is complete */ - if(DMA_GetFlagStatus(sEE_I2C_DMA_FLAG_TX_TC) != RESET) - { - /* Disable the DMA Tx Channel and Clear all its Flags */ - DMA_Cmd(sEE_I2C_DMA_CHANNEL_TX, DISABLE); - DMA_ClearFlag(sEE_I2C_DMA_FLAG_TX_GL); - - /*!< Wait till all data have been physically transferred on the bus */ - sEETimeout = sEE_LONG_TIMEOUT; - while(!I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BTF)) - { - if((sEETimeout--) == 0) sEE_TIMEOUT_UserCallback(); - } - - /*!< Send STOP condition */ - I2C_GenerateSTOP(sEE_I2C, ENABLE); - - /* Reset the variable holding the number of data to be written */ - *sEEDataWritePointer = 0; - } -} - -/** - * @brief This function handles the DMA Rx Channel interrupt Handler. - * @param None - * @retval None - */ -void sEE_I2C_DMA_RX_IRQHandler(void) -{ - /* Check if the DMA transfer is complete */ - if(DMA_GetFlagStatus(sEE_I2C_DMA_FLAG_RX_TC) != RESET) - { - /*!< Send STOP Condition */ - I2C_GenerateSTOP(sEE_I2C, ENABLE); - - /* Disable the DMA Rx Channel and Clear all its Flags */ - DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, DISABLE); - DMA_ClearFlag(sEE_I2C_DMA_FLAG_RX_GL); - - /* Reset the variable holding the number of data to be read */ - *sEEDataReadPointer = 0; - } -} - -#ifdef USE_DEFAULT_TIMEOUT_CALLBACK -/** - * @brief Basic management of the timeout situation. - * @param None. - * @retval None. - */ -uint32_t sEE_TIMEOUT_UserCallback(void) -{ - /* Block communication and all processes */ - while (1) - { - } -} -#endif /* USE_DEFAULT_TIMEOUT_CALLBACK */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_ee.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_ee.h deleted file mode 100644 index 78f2f579c..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_ee.h +++ /dev/null @@ -1,181 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l152_eval_i2c_ee.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains all the functions prototypes for the stm32l152_eval_i2c_ee - * firmware driver. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L152_EVAL_I2C_EE_H -#define __STM32L152_EVAL_I2C_EE_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32_eval.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32L152_EVAL - * @{ - */ - -/** @addtogroup STM32L152_EVAL_I2C_EE - * @{ - */ - -/** @defgroup STM32L152_EVAL_I2C_EE_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup STM32L152_EVAL_I2C_EE_Exported_Constants - * @{ - */ - -/* Uncomment the following line to use the default sEE_TIMEOUT_UserCallback() - function implemented in stm32_evel_i2c_ee.c file. - sEE_TIMEOUT_UserCallback() function is called whenever a timeout condition - occure during communication (waiting on an event that doesn't occur, bus - errors, busy devices ...). */ -/* #define USE_DEFAULT_TIMEOUT_CALLBACK */ - -#if !defined (sEE_M24C08) && !defined (sEE_M24C64_32) -/* Use the defines below the choose the EEPROM type */ -/* #define sEE_M24C08*/ /* Support the device: M24C08. */ -/* note: Could support: M24C01, M24C02, M24C04 and M24C16 if the blocks and - HW address are correctly defined*/ -#define sEE_M24C64_32 /* Support the devices: M24C32 and M24C64 */ -#endif - -#ifdef sEE_M24C64_32 -/* For M24C32 and M24C64 devices, E0,E1 and E2 pins are all used for device - address selection (ne need for additional address lines). According to the - Harware connection on the board (on STM3210C-EVAL board E0 = E1 = E2 = 0) */ - - #define sEE_HW_ADDRESS 0xA0 /* E0 = E1 = E2 = 0 */ - -#elif defined (sEE_M24C08) -/* The M24C08W contains 4 blocks (128byte each) with the adresses below: E2 = 0 - EEPROM Addresses defines */ - #define sEE_Block0_ADDRESS 0xA0 /* E2 = 0 */ - /*#define sEE_Block1_ADDRESS 0xA2*/ /* E2 = 0 */ - /*#define sEE_Block2_ADDRESS 0xA4*/ /* E2 = 0 */ - /*#define sEE_Block3_ADDRESS 0xA6*/ /* E2 = 0 */ - -#endif /* sEE_M24C64_32 */ - -#define I2C_SPEED 200000 -#define I2C_SLAVE_ADDRESS7 0xA0 - -#if defined (sEE_M24C08) - #define sEE_PAGESIZE 16 -#elif defined (sEE_M24C64_32) - #define sEE_PAGESIZE 32 -#endif - -/* Maximum Timeout values for flags and events waiting loops. These timeouts are - not based on accurate values, they just guarantee that the application will - not remain stuck if the I2C communication is corrupted. - You may modify these timeout values depending on CPU frequency and application - conditions (interrupts routines ...). */ -#define sEE_FLAG_TIMEOUT ((uint32_t)0x1000) -#define sEE_LONG_TIMEOUT ((uint32_t)(10 * sEE_FLAG_TIMEOUT)) - -/* Maximum number of trials for sEE_WaitEepromStandbyState() function */ -#define sEE_MAX_TRIALS_NUMBER 300 - -/* Defintions for the state of the DMA transfer */ -#define sEE_STATE_READY 0 -#define sEE_STATE_BUSY 1 -#define sEE_STATE_ERROR 2 - -#define sEE_OK 0 -#define sEE_FAIL 1 - -/** - * @} - */ - -/** @defgroup STM32L152_EVAL_I2C_EE_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32L152_EVAL_I2C_EE_Exported_Functions - * @{ - */ -void sEE_DeInit(void); -void sEE_Init(void); -uint32_t sEE_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t* NumByteToRead); -uint32_t sEE_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t* NumByteToWrite); -void sEE_WriteBuffer(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite); -uint32_t sEE_WaitEepromStandbyState(void); - -/* USER Callbacks: These are functions for which prototypes only are declared in - EEPROM driver and that should be implemented into user applicaiton. */ -/* sEE_TIMEOUT_UserCallback() function is called whenever a timeout condition - occure during communication (waiting on an event that doesn't occur, bus - errors, busy devices ...). - You can use the default timeout callback implementation by uncommenting the - define USE_DEFAULT_TIMEOUT_CALLBACK in stm32_evel_i2c_ee.h file. - Typically the user implementation of this callback should reset I2C peripheral - and re-initialize communication or in worst case reset all the application. */ -uint32_t sEE_TIMEOUT_UserCallback(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L152_EVAL_I2C_EE_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - - diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_lcd.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_lcd.c deleted file mode 100644 index 27d3a092c..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_lcd.c +++ /dev/null @@ -1,1529 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l152_eval_lcd.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320), - * AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module - * of STM32L152-EVAL board RevB. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l152_eval_lcd.h" -#include "../Common/fonts.c" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32L152_EVAL - * @{ - */ - -/** @defgroup STM32L152_EVAL_LCD - * @brief This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320), - * AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module - * of STM32L152-EVAL board. - * @{ - */ - -/** @defgroup STM32L152_EVAL_LCD_Private_Types - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32L152_EVAL_LCD_Private_Defines - * @{ - */ -#define LCD_ILI9320 0x9320 -#define LCD_SPFD5408 0x5408 -#define START_BYTE 0x70 -#define SET_INDEX 0x00 -#define READ_STATUS 0x01 -#define LCD_WRITE_REG 0x02 -#define LCD_READ_REG 0x03 -#define MAX_POLY_CORNERS 200 -#define POLY_Y(Z) ((int32_t)((Points + Z)->X)) -#define POLY_X(Z) ((int32_t)((Points + Z)->Y)) -/** - * @} - */ - -/** @defgroup STM32L152_EVAL_LCD_Private_Macros - * @{ - */ -#define ABS(X) ((X) > 0 ? (X) : -(X)) -/** - * @} - */ - -/** @defgroup STM32L152_EVAL_LCD_Private_Variables - * @{ - */ -static sFONT *LCD_Currentfonts; -/* Global variables to set the written text color */ -static __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF; -static __IO uint32_t LCDType = LCD_SPFD5408; -/** - * @} - */ - -/** @defgroup STM32L152_EVAL_LCD_Private_Function_Prototypes - * @{ - */ -#ifndef USE_Delay -static void delay(__IO uint32_t nCount); -#endif /* USE_Delay*/ - -static void PutPixel(int16_t x, int16_t y); -static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed); - -/** - * @} - */ - -/** @defgroup STM32L152_EVAL_LCD_Private_Functions - * @{ - */ - -/** - * @brief DeInitializes the LCD. - * @param None - * @retval None - */ -void STM32L152_LCD_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /*!< LCD Display Off */ - LCD_DisplayOff(); - - /*!< LCD_SPI disable */ - SPI_Cmd(LCD_SPI, DISABLE); - - /*!< LCD_SPI DeInit */ - SPI_DeInit(LCD_SPI); - - /*!< Disable SPI clock */ - RCC_APB1PeriphClockCmd(LCD_SPI_CLK, DISABLE); - - /* Configure NCS in Output Push-Pull mode */ - GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure); - - /* Configure SPI pins: SCK, MISO and MOSI */ - GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN; - GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN; - GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN; - GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @brief Setups the LCD. - * @param None - * @retval None - */ -void LCD_Setup(void) -{ -/* Configure the LCD Control pins --------------------------------------------*/ - LCD_CtrlLinesConfig(); - -/* Configure the LCD_SPI interface ----------------------------------------------*/ - LCD_SPIConfig(); - - if(LCDType == LCD_SPFD5408) - { - /* Start Initial Sequence --------------------------------------------------*/ - LCD_WriteReg(LCD_REG_227, 0x3008); /* Set internal timing */ - LCD_WriteReg(LCD_REG_231, 0x0012); /* Set internal timing */ - LCD_WriteReg(LCD_REG_239, 0x1231); /* Set internal timing */ - LCD_WriteReg(LCD_REG_1, 0x0100); /* Set SS and SM bit */ - LCD_WriteReg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ - LCD_WriteReg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ - LCD_WriteReg(LCD_REG_4, 0x0000); /* Resize register */ - LCD_WriteReg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ - LCD_WriteReg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ - LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */ - LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */ - LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */ - LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */ - /* Power On sequence -------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ - _delay_(20); /* Dis-charge capacitor power voltage (200ms) */ - LCD_WriteReg(LCD_REG_17, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_16, 0x12B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_18, 0x01BD); /* External reference voltage= Vci */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_19, 0x1400); /* VDV[4:0] for VCOM amplitude */ - LCD_WriteReg(LCD_REG_41, 0x000E); /* VCM[4:0] for VCOMH */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ - LCD_WriteReg(LCD_REG_33, 0x013F); /* GRAM Vertical Address */ - /* Adjust the Gamma Curve --------------------------------------------------*/ - LCD_WriteReg(LCD_REG_48, 0x0007); - LCD_WriteReg(LCD_REG_49, 0x0302); - LCD_WriteReg(LCD_REG_50, 0x0105); - LCD_WriteReg(LCD_REG_53, 0x0206); - LCD_WriteReg(LCD_REG_54, 0x0808); - LCD_WriteReg(LCD_REG_55, 0x0206); - LCD_WriteReg(LCD_REG_56, 0x0504); - LCD_WriteReg(LCD_REG_57, 0x0007); - LCD_WriteReg(LCD_REG_60, 0x0105); - LCD_WriteReg(LCD_REG_61, 0x0808); - /* Set GRAM area -----------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ - LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */ - LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ - LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */ - LCD_WriteReg(LCD_REG_96, 0xA700); /* Gate Scan Line */ - LCD_WriteReg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ - LCD_WriteReg(LCD_REG_106, 0x0000); /* Set scrolling line */ - /* Partial Display Control -------------------------------------------------*/ - LCD_WriteReg(LCD_REG_128, 0x0000); - LCD_WriteReg(LCD_REG_129, 0x0000); - LCD_WriteReg(LCD_REG_130, 0x0000); - LCD_WriteReg(LCD_REG_131, 0x0000); - LCD_WriteReg(LCD_REG_132, 0x0000); - LCD_WriteReg(LCD_REG_133, 0x0000); - /* Panel Control -----------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_144, 0x0010); - LCD_WriteReg(LCD_REG_146, 0x0000); - LCD_WriteReg(LCD_REG_147, 0x0003); - LCD_WriteReg(LCD_REG_149, 0x0110); - LCD_WriteReg(LCD_REG_151, 0x0000); - LCD_WriteReg(LCD_REG_152, 0x0000); - /* Set GRAM write direction and BGR = 1 - I/D=01 (Horizontal : increment, Vertical : decrement) - AM=1 (address is updated in vertical writing direction) */ - LCD_WriteReg(LCD_REG_3, 0x1018); - LCD_WriteReg(LCD_REG_7, 0x0112); /* 262K color and display ON */ - } - else if(LCDType == LCD_ILI9320) - { - _delay_(5); /* Delay 50 ms */ - /* Start Initial Sequence ------------------------------------------------*/ - LCD_WriteReg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */ - LCD_WriteReg(LCD_REG_0, 0x0001); /* Start internal OSC. */ - LCD_WriteReg(LCD_REG_1, 0x0100); /* set SS and SM bit */ - LCD_WriteReg(LCD_REG_2, 0x0700); /* set 1 line inversion */ - LCD_WriteReg(LCD_REG_3, 0x1030); /* set GRAM write direction and BGR=1. */ - LCD_WriteReg(LCD_REG_4, 0x0000); /* Resize register */ - LCD_WriteReg(LCD_REG_8, 0x0202); /* set the back porch and front porch */ - LCD_WriteReg(LCD_REG_9, 0x0000); /* set non-display area refresh cycle ISC[3:0] */ - LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */ - LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */ - LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */ - LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */ - /* Power On sequence -----------------------------------------------------*/ - LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ - _delay_(20); /* Dis-charge capacitor power voltage (200ms) */ - LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ - LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ - LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */ - /* Adjust the Gamma Curve ------------------------------------------------*/ - LCD_WriteReg(LCD_REG_48, 0x0006); - LCD_WriteReg(LCD_REG_49, 0x0101); - LCD_WriteReg(LCD_REG_50, 0x0003); - LCD_WriteReg(LCD_REG_53, 0x0106); - LCD_WriteReg(LCD_REG_54, 0x0b02); - LCD_WriteReg(LCD_REG_55, 0x0302); - LCD_WriteReg(LCD_REG_56, 0x0707); - LCD_WriteReg(LCD_REG_57, 0x0007); - LCD_WriteReg(LCD_REG_60, 0x0600); - LCD_WriteReg(LCD_REG_61, 0x020b); - - /* Set GRAM area ---------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ - LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */ - LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ - LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */ - LCD_WriteReg(LCD_REG_96, 0x2700); /* Gate Scan Line */ - LCD_WriteReg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ - LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */ - /* Partial Display Control -----------------------------------------------*/ - LCD_WriteReg(LCD_REG_128, 0x0000); - LCD_WriteReg(LCD_REG_129, 0x0000); - LCD_WriteReg(LCD_REG_130, 0x0000); - LCD_WriteReg(LCD_REG_131, 0x0000); - LCD_WriteReg(LCD_REG_132, 0x0000); - LCD_WriteReg(LCD_REG_133, 0x0000); - /* Panel Control ---------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_144, 0x0010); - LCD_WriteReg(LCD_REG_146, 0x0000); - LCD_WriteReg(LCD_REG_147, 0x0003); - LCD_WriteReg(LCD_REG_149, 0x0110); - LCD_WriteReg(LCD_REG_151, 0x0000); - LCD_WriteReg(LCD_REG_152, 0x0000); - /* Set GRAM write direction and BGR = 1 */ - /* I/D=01 (Horizontal : increment, Vertical : decrement) */ - /* AM=1 (address is updated in vertical writing direction) */ - LCD_WriteReg(LCD_REG_3, 0x1018); - LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */ - } -} - - -/** - * @brief Initializes the LCD. - * @param None - * @retval None - */ -void STM32L152_LCD_Init(void) -{ - /* Setups the LCD */ - LCD_Setup(); - - /* Try to read new LCD controller ID 0x5408 */ - if (LCD_ReadReg(LCD_REG_0) == LCD_SPFD5408) - { - LCDType = LCD_SPFD5408; - } - else - { - LCDType = LCD_ILI9320; - /* Setups the LCD */ - LCD_Setup(); - } - - LCD_SetFont(&LCD_DEFAULT_FONT); -} - -/** - * @brief Sets the LCD Text and Background colors. - * @param _TextColor: specifies the Text Color. - * @param _BackColor: specifies the Background Color. - * @retval None - */ -void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor) -{ - TextColor = _TextColor; - BackColor = _BackColor; -} - -/** - * @brief Gets the LCD Text and Background colors. - * @param _TextColor: pointer to the variable that will contain the Text - Color. - * @param _BackColor: pointer to the variable that will contain the Background - Color. - * @retval None - */ -void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor) -{ - *_TextColor = TextColor; *_BackColor = BackColor; -} - -/** - * @brief Sets the Text color. - * @param Color: specifies the Text color code RGB(5-6-5). - * @retval None - */ -void LCD_SetTextColor(__IO uint16_t Color) -{ - TextColor = Color; -} - - -/** - * @brief Sets the Background color. - * @param Color: specifies the Background color code RGB(5-6-5). - * @retval None - */ -void LCD_SetBackColor(__IO uint16_t Color) -{ - BackColor = Color; -} - -/** - * @brief Sets the Text Font. - * @param fonts: specifies the font to be used. - * @retval None - */ -void LCD_SetFont(sFONT *fonts) -{ - LCD_Currentfonts = fonts; -} - -/** - * @brief Gets the Text Font. - * @param None. - * @retval the used font. - */ -sFONT *LCD_GetFont(void) -{ - return LCD_Currentfonts; -} - -/** - * @brief Clears the selected line. - * @param Line: the Line to be cleared. - * This parameter can be one of the following values: - * @arg Linex: where x can be 0..n - * @retval None - */ -void LCD_ClearLine(uint8_t Line) -{ - uint16_t refcolumn = LCD_PIXEL_WIDTH - 1; - - /* Send the string character by character on lCD */ - while (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width) - { - /* Display one character on LCD */ - LCD_DisplayChar(Line, refcolumn, ' '); - /* Decrement the column position by 16 */ - refcolumn -= LCD_Currentfonts->Width; - } -} - - -/** - * @brief Clears the hole LCD. - * @param Color: the color of the background. - * @retval None - */ -void LCD_Clear(uint16_t Color) -{ - uint32_t index = 0; - - LCD_SetCursor(0x00, 0x013F); - - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - - for(index = 0; index < 76800; index++) - { - LCD_WriteRAM(Color); - } - - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); - -} - - -/** - * @brief Sets the cursor position. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @retval None - */ -void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos) -{ - LCD_WriteReg(LCD_REG_32, Xpos); - LCD_WriteReg(LCD_REG_33, Ypos); -} - - -/** - * @brief Draws a character on LCD. - * @param Xpos: the Line where to display the character shape. - * @param Ypos: start column address. - * @param c: pointer to the character data. - * @retval None - */ -void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c) -{ - uint32_t index = 0, i = 0; - uint8_t Xaddress = 0; - - Xaddress = Xpos; - - LCD_SetCursor(Xaddress, Ypos); - - for(index = 0; index < LCD_Currentfonts->Height; index++) - { - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - - for(i = 0; i < LCD_Currentfonts->Width; i++) - { - if((((c[index] & ((0x80 << ((LCD_Currentfonts->Width / 12 ) * 8 ) ) >> i)) == 0x00) &&(LCD_Currentfonts->Width <= 12))|| - (((c[index] & (0x1 << i)) == 0x00)&&(LCD_Currentfonts->Width > 12 ))) - - { - LCD_WriteRAM(BackColor); - } - else - { - LCD_WriteRAM(TextColor); - } - } - - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); - Xaddress++; - LCD_SetCursor(Xaddress, Ypos); - } -} - - -/** - * @brief Displays one character (16dots width, 24dots height). - * @param Line: the Line where to display the character shape . - * This parameter can be one of the following values: - * @arg Linex: where x can be 0..9 - * @param Column: start column address. - * @param Ascii: character ascii code, must be between 0x20 and 0x7E. - * @retval None - */ -void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii) -{ - Ascii -= 32; - LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]); -} - - -/** - * @brief Displays a maximum of 20 char on the LCD. - * @param Line: the Line where to display the character shape . - * This parameter can be one of the following values: - * @arg Linex: where x can be 0..9 - * @param *ptr: pointer to string to display on LCD. - * @retval None - */ -void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr) -{ - uint16_t refcolumn = LCD_PIXEL_WIDTH - 1; - - /* Send the string character by character on lCD */ - while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width)) - { - /* Display one character on LCD */ - LCD_DisplayChar(Line, refcolumn, *ptr); - /* Decrement the column position by 16 */ - refcolumn -= LCD_Currentfonts->Width; - /* Point on the next character */ - ptr++; - } -} - - -/** - * @brief Sets a display window - * @param Xpos: specifies the X buttom left position. - * @param Ypos: specifies the Y buttom left position. - * @param Height: display window height. - * @param Width: display window width. - * @retval None - */ -void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width) -{ - /* Horizontal GRAM Start Address */ - if(Xpos >= Height) - { - LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1)); - } - else - { - LCD_WriteReg(LCD_REG_80, 0); - } - /* Horizontal GRAM End Address */ - LCD_WriteReg(LCD_REG_81, Xpos); - /* Vertical GRAM Start Address */ - if(Ypos >= Width) - { - LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1)); - } - else - { - LCD_WriteReg(LCD_REG_82, 0); - } - /* Vertical GRAM End Address */ - LCD_WriteReg(LCD_REG_83, Ypos); - - LCD_SetCursor(Xpos, Ypos); -} - - -/** - * @brief Disables LCD Window mode. - * @param None - * @retval None - */ -void LCD_WindowModeDisable(void) -{ - LCD_SetDisplayWindow(239, 0x13F, 240, 320); - LCD_WriteReg(LCD_REG_3, 0x1018); -} - -/** - * @brief Displays a line. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Length: line length. - * @param Direction: line direction. - * This parameter can be one of the following values: Vertical or Horizontal. - * @retval None - */ -void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction) -{ - uint32_t i = 0; - - LCD_SetCursor(Xpos, Ypos); - - if(Direction == LCD_DIR_HORIZONTAL) - { - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - - for(i = 0; i < Length; i++) - { - LCD_WriteRAM(TextColor); - } - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); - } - else - { - for(i = 0; i < Length; i++) - { - LCD_WriteRAMWord(TextColor); - Xpos++; - LCD_SetCursor(Xpos, Ypos); - } - } -} - - -/** - * @brief Displays a rectangle. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Height: display rectangle height. - * @param Width: display rectangle width. - * @retval None - */ -void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width) -{ - LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL); - LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL); - - LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL); - LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL); -} - - -/** - * @brief Displays a circle. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Radius - * @retval None - */ -void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius) -{ - int32_t D;/* Decision Variable */ - uint32_t CurX;/* Current X Value */ - uint32_t CurY;/* Current Y Value */ - - D = 3 - (Radius << 1); - CurX = 0; - CurY = Radius; - - while (CurX <= CurY) - { - LCD_SetCursor(Xpos + CurX, Ypos + CurY); - LCD_WriteRAMWord(TextColor); - LCD_SetCursor(Xpos + CurX, Ypos - CurY); - LCD_WriteRAMWord(TextColor); - - LCD_SetCursor(Xpos - CurX, Ypos + CurY); - LCD_WriteRAMWord(TextColor); - - LCD_SetCursor(Xpos - CurX, Ypos - CurY); - LCD_WriteRAMWord(TextColor); - - LCD_SetCursor(Xpos + CurY, Ypos + CurX); - LCD_WriteRAMWord(TextColor); - - LCD_SetCursor(Xpos + CurY, Ypos - CurX); - LCD_WriteRAMWord(TextColor); - - LCD_SetCursor(Xpos - CurY, Ypos + CurX); - LCD_WriteRAMWord(TextColor); - - LCD_SetCursor(Xpos - CurY, Ypos - CurX); - LCD_WriteRAMWord(TextColor); - - if (D < 0) - { - D += (CurX << 2) + 6; - } - else - { - D += ((CurX - CurY) << 2) + 10; - CurY--; - } - CurX++; - } -} - - -/** - * @brief Displays a monocolor picture. - * @param Pict: pointer to the picture array. - * @retval None - */ -void LCD_DrawMonoPict(const uint32_t *Pict) -{ - uint32_t index = 0, i = 0; - LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1)); - - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - - for(index = 0; index < 2400; index++) - { - for(i = 0; i < 32; i++) - { - if((Pict[index] & (1 << i)) == 0x00) - { - LCD_WriteRAM(BackColor); - } - else - { - LCD_WriteRAM(TextColor); - } - } - } - - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); -} - -#ifdef USE_LCD_DrawBMP -/** - * @brief Displays a bitmap picture loaded in the SPI Flash. - * @param BmpAddress: Bmp picture address in the SPI Flash. - * @retval None - */ -void LCD_DrawBMP(uint32_t BmpAddress) -{ - uint32_t i = 0, size = 0; - /* Read bitmap size */ - sFLASH_ReadBuffer((uint8_t*)&size, BmpAddress + 2, 4); - /* get bitmap data address offset */ - sFLASH_ReadBuffer((uint8_t*)&i, BmpAddress + 10, 4); - - size = (size - i)/2; - sFLASH_StartReadSequence(BmpAddress + i); - /* Disable LCD_SPI */ - SPI_Cmd(LCD_SPI, DISABLE); - /* SPI in 16-bit mode */ - SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_16b); - /* Enable LCD_SPI */ - SPI_Cmd(LCD_SPI, ENABLE); - - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - /* Set GRAM write direction and BGR = 1 */ - /* I/D=00 (Horizontal : decrement, Vertical : decrement) */ - /* AM=1 (address is updated in vertical writing direction) */ - LCD_WriteReg(LCD_REG_3, 0x1008); - LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ - } - - /* Read bitmap data from SPI Flash and send them to LCD */ - for(i = 0; i < size; i++) - { - LCD_WriteRAM(__REV16(sFLASH_SendHalfWord(0xA5A5))); - } - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); - } - - /* Deselect the FLASH: Chip Select high */ - sFLASH_CS_HIGH(); - /* Disable LCD_SPI */ - SPI_Cmd(LCD_SPI, DISABLE); - /* SPI in 8-bit mode */ - SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_8b); - /* Enable LCD_SPI */ - SPI_Cmd(LCD_SPI, ENABLE); - - if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408)) - { - /* Set GRAM write direction and BGR = 1 */ - /* I/D = 01 (Horizontal : increment, Vertical : decrement) */ - /* AM = 1 (address is updated in vertical writing direction) */ - LCD_WriteReg(LCD_REG_3, 0x1018); - } -} -#endif /* USE_LCD_DrawBMP */ - -/** - * @brief Displays a full rectangle. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Height: rectangle height. - * @param Width: rectangle width. - * @retval None - */ -void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height) -{ - LCD_SetTextColor(TextColor); - - LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL); - LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL); - - LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL); - LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL); - - Width -= 2; - Height--; - Ypos--; - - LCD_SetTextColor(BackColor); - - while(Height--) - { - LCD_DrawLine(++Xpos, Ypos, Width, LCD_DIR_HORIZONTAL); - } - - LCD_SetTextColor(TextColor); -} - -/** - * @brief Displays a full circle. - * @param Xpos: specifies the X position. - * @param Ypos: specifies the Y position. - * @param Radius - * @retval None - */ -void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius) -{ - int32_t D; /* Decision Variable */ - uint32_t CurX;/* Current X Value */ - uint32_t CurY;/* Current Y Value */ - - D = 3 - (Radius << 1); - - CurX = 0; - CurY = Radius; - - LCD_SetTextColor(BackColor); - - while (CurX <= CurY) - { - if(CurY > 0) - { - LCD_DrawLine(Xpos - CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL); - LCD_DrawLine(Xpos + CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL); - } - - if(CurX > 0) - { - LCD_DrawLine(Xpos - CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL); - LCD_DrawLine(Xpos + CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL); - } - if (D < 0) - { - D += (CurX << 2) + 6; - } - else - { - D += ((CurX - CurY) << 2) + 10; - CurY--; - } - CurX++; - } - - LCD_SetTextColor(TextColor); - LCD_DrawCircle(Xpos, Ypos, Radius); -} - -/** - * @brief Displays an uni line (between two points). - * @param x1: specifies the point 1 x position. - * @param y1: specifies the point 1 y position. - * @param x2: specifies the point 2 x position. - * @param y2: specifies the point 2 y position. - * @retval None - */ -void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2) -{ - int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0, - yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0, - curpixel = 0; - - deltax = ABS(x2 - x1); /* The difference between the x's */ - deltay = ABS(y2 - y1); /* The difference between the y's */ - x = x1; /* Start x off at the first pixel */ - y = y1; /* Start y off at the first pixel */ - - if (x2 >= x1) /* The x-values are increasing */ - { - xinc1 = 1; - xinc2 = 1; - } - else /* The x-values are decreasing */ - { - xinc1 = -1; - xinc2 = -1; - } - - if (y2 >= y1) /* The y-values are increasing */ - { - yinc1 = 1; - yinc2 = 1; - } - else /* The y-values are decreasing */ - { - yinc1 = -1; - yinc2 = -1; - } - - if (deltax >= deltay) /* There is at least one x-value for every y-value */ - { - xinc1 = 0; /* Don't change the x when numerator >= denominator */ - yinc2 = 0; /* Don't change the y for every iteration */ - den = deltax; - num = deltax / 2; - numadd = deltay; - numpixels = deltax; /* There are more x-values than y-values */ - } - else /* There is at least one y-value for every x-value */ - { - xinc2 = 0; /* Don't change the x for every iteration */ - yinc1 = 0; /* Don't change the y when numerator >= denominator */ - den = deltay; - num = deltay / 2; - numadd = deltax; - numpixels = deltay; /* There are more y-values than x-values */ - } - - for (curpixel = 0; curpixel <= numpixels; curpixel++) - { - PutPixel(x, y); /* Draw the current pixel */ - num += numadd; /* Increase the numerator by the top of the fraction */ - if (num >= den) /* Check if numerator >= denominator */ - { - num -= den; /* Calculate the new numerator value */ - x += xinc1; /* Change the x as appropriate */ - y += yinc1; /* Change the y as appropriate */ - } - x += xinc2; /* Change the x as appropriate */ - y += yinc2; /* Change the y as appropriate */ - } -} - -/** - * @brief Displays an polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_PolyLine(pPoint Points, uint16_t PointCount) -{ - int16_t X = 0, Y = 0; - - if(PointCount < 2) - { - return; - } - - while(--PointCount) - { - X = Points->X; - Y = Points->Y; - Points++; - LCD_DrawUniLine(X, Y, Points->X, Points->Y); - } -} - -/** - * @brief Displays an relative polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @param Closed: specifies if the draw is closed or not. - * 1: closed, 0 : not closed. - * @retval None - */ -static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed) -{ - int16_t X = 0, Y = 0; - pPoint First = Points; - - if(PointCount < 2) - { - return; - } - X = Points->X; - Y = Points->Y; - while(--PointCount) - { - Points++; - LCD_DrawUniLine(X, Y, X + Points->X, Y + Points->Y); - X = X + Points->X; - Y = Y + Points->Y; - } - if(Closed) - { - LCD_DrawUniLine(First->X, First->Y, X, Y); - } -} - -/** - * @brief Displays a closed polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount) -{ - LCD_PolyLine(Points, PointCount); - LCD_DrawUniLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y); -} - -/** - * @brief Displays a relative polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount) -{ - LCD_PolyLineRelativeClosed(Points, PointCount, 0); -} - -/** - * @brief Displays a closed relative polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount) -{ - LCD_PolyLineRelativeClosed(Points, PointCount, 1); -} - - -/** - * @brief Displays a full polyline (between many points). - * @param Points: pointer to the points array. - * @param PointCount: Number of points. - * @retval None - */ -void LCD_FillPolyLine(pPoint Points, uint16_t PointCount) -{ - /* public-domain code by Darel Rex Finley, 2007 */ - uint16_t nodes = 0, nodeX[MAX_POLY_CORNERS], pixelX = 0, pixelY = 0, i = 0, - j = 0, swap = 0; - uint16_t IMAGE_LEFT = 0, IMAGE_RIGHT = 0, IMAGE_TOP = 0, IMAGE_BOTTOM = 0; - - IMAGE_LEFT = IMAGE_RIGHT = Points->X; - IMAGE_TOP= IMAGE_BOTTOM = Points->Y; - - for(i = 1; i < PointCount; i++) - { - pixelX = POLY_X(i); - if(pixelX < IMAGE_LEFT) - { - IMAGE_LEFT = pixelX; - } - if(pixelX > IMAGE_RIGHT) - { - IMAGE_RIGHT = pixelX; - } - - pixelY = POLY_Y(i); - if(pixelY < IMAGE_TOP) - { - IMAGE_TOP = pixelY; - } - if(pixelY > IMAGE_BOTTOM) - { - IMAGE_BOTTOM = pixelY; - } - } - - LCD_SetTextColor(BackColor); - - /* Loop through the rows of the image. */ - for (pixelY = IMAGE_TOP; pixelY < IMAGE_BOTTOM; pixelY++) - { - /* Build a list of nodes. */ - nodes = 0; j = PointCount-1; - - for (i = 0; i < PointCount; i++) - { - if (POLY_Y(i)<(double) pixelY && POLY_Y(j)>=(double) pixelY || POLY_Y(j)<(double) pixelY && POLY_Y(i)>=(double) pixelY) - { - nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i))); - } - j = i; - } - - /* Sort the nodes, via a simple "Bubble" sort. */ - i = 0; - while (i < nodes-1) - { - if (nodeX[i]>nodeX[i+1]) - { - swap = nodeX[i]; - nodeX[i] = nodeX[i+1]; - nodeX[i+1] = swap; - if(i) - { - i--; - } - } - else - { - i++; - } - } - - /* Fill the pixels between node pairs. */ - for (i = 0; i < nodes; i+=2) - { - if(nodeX[i] >= IMAGE_RIGHT) - { - break; - } - if(nodeX[i+1] > IMAGE_LEFT) - { - if (nodeX[i] < IMAGE_LEFT) - { - nodeX[i]=IMAGE_LEFT; - } - if(nodeX[i+1] > IMAGE_RIGHT) - { - nodeX[i+1] = IMAGE_RIGHT; - } - LCD_SetTextColor(BackColor); - LCD_DrawLine(pixelY, nodeX[i+1], nodeX[i+1] - nodeX[i], LCD_DIR_HORIZONTAL); - LCD_SetTextColor(TextColor); - PutPixel(pixelY, nodeX[i+1]); - PutPixel(pixelY, nodeX[i]); - /* for (j=nodeX[i]; j> 8); - - while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET) - { - } - - SPI_SendData(LCD_SPI, (LCD_RegValue & 0xFF)); - - while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET) - { - } - - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); -} - - -/** - * @brief Reads the selected LCD Register. - * @param LCD_Reg: address of the selected register. - * @retval LCD Register Value. - */ -uint16_t LCD_ReadReg(uint8_t LCD_Reg) -{ - uint16_t tmp = 0; - uint8_t i = 0; - - /* LCD_SPI prescaler: 4 */ - LCD_SPI->CR1 &= 0xFFC7; - LCD_SPI->CR1 |= 0x0008; - /* Write 16-bit Index (then Read Reg) */ - LCD_WriteRegIndex(LCD_Reg); - /* Read 16-bit Reg */ - /* Reset LCD control line(/CS) and Send Start-Byte */ - LCD_nCS_StartByte(START_BYTE | LCD_READ_REG); - - for(i = 0; i < 5; i++) - { - SPI_SendData(LCD_SPI, 0xFF); - while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET) - { - } - /* One byte of invalid dummy data read after the start byte */ - while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_RXNE) == RESET) - { - } - SPI_ReceiveData(LCD_SPI); - } - - SPI_SendData(LCD_SPI, 0xFF); - - /* Read upper byte */ - while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET) - { - } - - /* Read lower byte */ - while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_RXNE) == RESET) - { - } - tmp = SPI_ReceiveData(LCD_SPI); - - - SPI_SendData(LCD_SPI, 0xFF); - while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET) - { - } - - /* Read lower byte */ - while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_RXNE) == RESET) - { - } - - tmp = ((tmp & 0xFF) << 8) | SPI_ReceiveData(LCD_SPI); - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); - - /* LCD_SPI prescaler: 2 */ - LCD_SPI->CR1 &= 0xFFC7; - - return tmp; -} - - -/** - * @brief Prepare to write to the LCD RAM. - * @param None - * @retval None - */ -void LCD_WriteRAM_Prepare(void) -{ - LCD_WriteRegIndex(LCD_REG_34); /* Select GRAM Reg */ - - /* Reset LCD control line(/CS) and Send Start-Byte */ - LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG); -} - - -/** - * @brief Writes 1 word to the LCD RAM. - * @param RGB_Code: the pixel color in RGB mode (5-6-5). - * @retval None - */ -void LCD_WriteRAMWord(uint16_t RGB_Code) -{ - LCD_WriteRAM_Prepare(); - - LCD_WriteRAM(RGB_Code); - - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); -} - -/** - * @brief Writes to the LCD RAM. - * @param RGB_Code: the pixel color in RGB mode (5-6-5). - * @retval None - */ -void LCD_WriteRAM(uint16_t RGB_Code) -{ - SPI_SendData(LCD_SPI, RGB_Code >> 8); - while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET) - { - } - SPI_SendData(LCD_SPI, RGB_Code & 0xFF); - while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET) - { - } -} - - -/** - * @brief Power on the LCD. - * @param None - * @retval None - */ -void LCD_PowerOn(void) -{ - /* Power On sequence ---------------------------------------------------------*/ - LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ - _delay_(20); /* Dis-charge capacitor power voltage (200ms) */ - LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ - _delay_(5); /* Delay 50 ms */ - LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ - _delay_(5); /* delay 50 ms */ - LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ - LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ - _delay_(5); /* delay 50 ms */ - LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */ -} - - -/** - * @brief Enables the Display. - * @param None - * @retval None - */ -void LCD_DisplayOn(void) -{ - /* Display On */ - LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */ -} - - -/** - * @brief Disables the Display. - * @param None - * @retval None - */ -void LCD_DisplayOff(void) -{ - /* Display Off */ - LCD_WriteReg(LCD_REG_7, 0x0); -} - - -/** - * @brief Configures LCD control lines in Output Push-Pull mode. - * @param None - * @retval None - */ -void LCD_CtrlLinesConfig(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - RCC_AHBPeriphClockCmd(LCD_NCS_GPIO_CLK, ENABLE); - - /* Configure NCS (PF.02) in Output Push-Pull mode */ - GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure); - - LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); -} - - -/** - * @brief Sets or reset LCD control lines. - * @param GPIOx: where x can be B or D to select the GPIO peripheral. - * @param CtrlPins: the Control line. - * This parameter can be: - * @arg LCD_NCS_PIN: Chip Select pin - * @arg LCD_NWR_PIN: Read/Write Selection pin - * @arg LCD_RS_PIN: Register/RAM Selection pin - * @param BitVal: specifies the value to be written to the selected bit. - * This parameter can be: - * @arg Bit_RESET: to clear the port pin - * @arg Bit_SET: to set the port pin - * @retval None - */ -void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal) -{ - /* Set or Reset the control line */ - GPIO_WriteBit(GPIOx, CtrlPins, BitVal); -} - - -/** - * @brief Configures the LCD_SPI interface. - * @param None - * @retval None - */ -void LCD_SPIConfig(void) -{ - SPI_InitTypeDef SPI_InitStructure; - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable LCD_SPI_SCK_GPIO_CLK, LCD_SPI_MISO_GPIO_CLK and LCD_SPI_MOSI_GPIO_CLK clock */ - RCC_AHBPeriphClockCmd(LCD_SPI_SCK_GPIO_CLK | LCD_SPI_MISO_GPIO_CLK | LCD_SPI_MOSI_GPIO_CLK, ENABLE); - - /* Enable LCD_SPI and SYSCFG clock */ - RCC_APB2PeriphClockCmd(LCD_SPI_CLK | RCC_APB2Periph_SYSCFG, ENABLE); - - /* Configure LCD_SPI SCK pin */ - GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - /* Configure LCD_SPI MISO pin */ - GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN; - GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - /* Configure LCD_SPI MOSI pin */ - GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN; - GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); - - /* Connect PE.13 to SPI SCK */ - GPIO_PinAFConfig(LCD_SPI_SCK_GPIO_PORT, LCD_SPI_SCK_SOURCE, LCD_SPI_SCK_AF); - - /* Connect PE.14 to SPI MISO */ - GPIO_PinAFConfig(LCD_SPI_MISO_GPIO_PORT, LCD_SPI_MISO_SOURCE, LCD_SPI_MISO_AF); - - /* Connect PE.15 to SPI MOSI */ - GPIO_PinAFConfig(LCD_SPI_MOSI_GPIO_PORT, LCD_SPI_MOSI_SOURCE, LCD_SPI_MOSI_AF); - - SPI_DeInit(LCD_SPI); - - /* SPI Config */ - SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; - SPI_InitStructure.SPI_Mode = SPI_Mode_Master; - SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; - SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; - SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; - SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; - SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; - SPI_InitStructure.SPI_CRCPolynomial = 7; - SPI_Init(LCD_SPI, &SPI_InitStructure); - - /* SPI enable */ - SPI_Cmd(LCD_SPI, ENABLE); -} - -/** - * @brief Displays a pixel. - * @param x: pixel x. - * @param y: pixel y. - * @retval None - */ -static void PutPixel(int16_t x, int16_t y) -{ - if(x < 0 || x > 239 || y < 0 || y > 319) - { - return; - } - LCD_DrawLine(x, y, 1, LCD_DIR_HORIZONTAL); -} - -#ifndef USE_Delay -/** - * @brief Inserts a delay time. - * @param nCount: specifies the delay time length. - * @retval None - */ -static void delay(__IO uint32_t nCount) -{ - __IO uint32_t index = 0; - for(index = (34000 * nCount); index != 0; index--) - { - } -} -#endif /* USE_Delay*/ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_lcd.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_lcd.h deleted file mode 100644 index 00f7c653b..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_lcd.h +++ /dev/null @@ -1,392 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l152_eval_lcd.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief This file contains all the functions prototypes for the stm32l152_eval_lcd - * firmware driver. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L152_EVAL_LCD_H -#define __STM32L152_EVAL_LCD_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" -#include "../Common/fonts.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @addtogroup STM32L152_EVAL - * @{ - */ - -/** @addtogroup STM32L152_EVAL_LCD - * @{ - */ - - -/** @defgroup STM32L152_EVAL_LCD_Exported_Types - * @{ - */ -typedef struct -{ - int16_t X; - int16_t Y; -} Point, * pPoint; -/** - * @} - */ - -/** @defgroup STM32L152_EVAL_LCD_Exported_Constants - * @{ - */ - -/** - * @brief Uncomment the line below if you want to use LCD_DrawBMP function to - * display a bitmap picture on the LCD. This function assumes that the bitmap - * file is loaded in the SPI Flash (mounted on STM32L152-EVAL board), however - * user can tailor it according to his application hardware requirement. - */ -/*#define USE_LCD_DrawBMP*/ - -/** - * @brief Uncomment the line below if you want to use user defined Delay function - * (for precise timing), otherwise default _delay_ function defined within - * this driver is used (less precise timing). - */ -/* #define USE_Delay */ - -#ifdef USE_Delay -#include "main.h" - - #define _delay_ Delay /* !< User can provide more timing precise _delay_ function - (with 10ms time base), using SysTick for example */ -#else - #define _delay_ delay /* !< Default _delay_ function with less precise timing */ -#endif - - -/** - * @brief LCD Control pins - */ -#define LCD_NCS_PIN GPIO_Pin_2 -#define LCD_NCS_GPIO_PORT GPIOH -#define LCD_NCS_GPIO_CLK RCC_AHBPeriph_GPIOH - -/** - * @brief LCD SPI Interface pins - */ -#define LCD_SPI_SCK_PIN GPIO_Pin_13 /* PE.13 */ -#define LCD_SPI_SCK_GPIO_PORT GPIOE /* GPIOE */ -#define LCD_SPI_SCK_GPIO_CLK RCC_AHBPeriph_GPIOE -#define LCD_SPI_SCK_SOURCE GPIO_PinSource13 -#define LCD_SPI_SCK_AF GPIO_AF_SPI1 -#define LCD_SPI_MISO_PIN GPIO_Pin_14 /* PE.14 */ -#define LCD_SPI_MISO_GPIO_PORT GPIOE /* GPIOE */ -#define LCD_SPI_MISO_GPIO_CLK RCC_AHBPeriph_GPIOE -#define LCD_SPI_MISO_SOURCE GPIO_PinSource14 -#define LCD_SPI_MISO_AF GPIO_AF_SPI1 -#define LCD_SPI_MOSI_PIN GPIO_Pin_15 /* PE.15 */ -#define LCD_SPI_MOSI_GPIO_PORT GPIOE /* GPIOE */ -#define LCD_SPI_MOSI_GPIO_CLK RCC_AHBPeriph_GPIOE -#define LCD_SPI_MOSI_SOURCE GPIO_PinSource15 -#define LCD_SPI_MOSI_AF GPIO_AF_SPI1 -#define LCD_SPI SPI1 -#define LCD_SPI_CLK RCC_APB2Periph_SPI1 - - -/** - * @brief LCD Registers - */ -#define LCD_REG_0 0x00 -#define LCD_REG_1 0x01 -#define LCD_REG_2 0x02 -#define LCD_REG_3 0x03 -#define LCD_REG_4 0x04 -#define LCD_REG_5 0x05 -#define LCD_REG_6 0x06 -#define LCD_REG_7 0x07 -#define LCD_REG_8 0x08 -#define LCD_REG_9 0x09 -#define LCD_REG_10 0x0A -#define LCD_REG_12 0x0C -#define LCD_REG_13 0x0D -#define LCD_REG_14 0x0E -#define LCD_REG_15 0x0F -#define LCD_REG_16 0x10 -#define LCD_REG_17 0x11 -#define LCD_REG_18 0x12 -#define LCD_REG_19 0x13 -#define LCD_REG_20 0x14 -#define LCD_REG_21 0x15 -#define LCD_REG_22 0x16 -#define LCD_REG_23 0x17 -#define LCD_REG_24 0x18 -#define LCD_REG_25 0x19 -#define LCD_REG_26 0x1A -#define LCD_REG_27 0x1B -#define LCD_REG_28 0x1C -#define LCD_REG_29 0x1D -#define LCD_REG_30 0x1E -#define LCD_REG_31 0x1F -#define LCD_REG_32 0x20 -#define LCD_REG_33 0x21 -#define LCD_REG_34 0x22 -#define LCD_REG_36 0x24 -#define LCD_REG_37 0x25 -#define LCD_REG_40 0x28 -#define LCD_REG_41 0x29 -#define LCD_REG_43 0x2B -#define LCD_REG_45 0x2D -#define LCD_REG_48 0x30 -#define LCD_REG_49 0x31 -#define LCD_REG_50 0x32 -#define LCD_REG_51 0x33 -#define LCD_REG_52 0x34 -#define LCD_REG_53 0x35 -#define LCD_REG_54 0x36 -#define LCD_REG_55 0x37 -#define LCD_REG_56 0x38 -#define LCD_REG_57 0x39 -#define LCD_REG_59 0x3B -#define LCD_REG_60 0x3C -#define LCD_REG_61 0x3D -#define LCD_REG_62 0x3E -#define LCD_REG_63 0x3F -#define LCD_REG_64 0x40 -#define LCD_REG_65 0x41 -#define LCD_REG_66 0x42 -#define LCD_REG_67 0x43 -#define LCD_REG_68 0x44 -#define LCD_REG_69 0x45 -#define LCD_REG_70 0x46 -#define LCD_REG_71 0x47 -#define LCD_REG_72 0x48 -#define LCD_REG_73 0x49 -#define LCD_REG_74 0x4A -#define LCD_REG_75 0x4B -#define LCD_REG_76 0x4C -#define LCD_REG_77 0x4D -#define LCD_REG_78 0x4E -#define LCD_REG_79 0x4F -#define LCD_REG_80 0x50 -#define LCD_REG_81 0x51 -#define LCD_REG_82 0x52 -#define LCD_REG_83 0x53 -#define LCD_REG_96 0x60 -#define LCD_REG_97 0x61 -#define LCD_REG_106 0x6A -#define LCD_REG_118 0x76 -#define LCD_REG_128 0x80 -#define LCD_REG_129 0x81 -#define LCD_REG_130 0x82 -#define LCD_REG_131 0x83 -#define LCD_REG_132 0x84 -#define LCD_REG_133 0x85 -#define LCD_REG_134 0x86 -#define LCD_REG_135 0x87 -#define LCD_REG_136 0x88 -#define LCD_REG_137 0x89 -#define LCD_REG_139 0x8B -#define LCD_REG_140 0x8C -#define LCD_REG_141 0x8D -#define LCD_REG_143 0x8F -#define LCD_REG_144 0x90 -#define LCD_REG_145 0x91 -#define LCD_REG_146 0x92 -#define LCD_REG_147 0x93 -#define LCD_REG_148 0x94 -#define LCD_REG_149 0x95 -#define LCD_REG_150 0x96 -#define LCD_REG_151 0x97 -#define LCD_REG_152 0x98 -#define LCD_REG_153 0x99 -#define LCD_REG_154 0x9A -#define LCD_REG_157 0x9D -#define LCD_REG_192 0xC0 -#define LCD_REG_193 0xC1 -#define LCD_REG_227 0xE3 -#define LCD_REG_229 0xE5 -#define LCD_REG_231 0xE7 -#define LCD_REG_239 0xEF - - -/** - * @brief LCD color - */ -#define LCD_COLOR_WHITE 0xFFFF -#define LCD_COLOR_BLACK 0x0000 -#define LCD_COLOR_GREY 0xF7DE -#define LCD_COLOR_BLUE 0x001F -#define LCD_COLOR_BLUE2 0x051F -#define LCD_COLOR_RED 0xF800 -#define LCD_COLOR_MAGENTA 0xF81F -#define LCD_COLOR_GREEN 0x07E0 -#define LCD_COLOR_CYAN 0x7FFF -#define LCD_COLOR_YELLOW 0xFFE0 - -/** - * @brief LCD Lines depending on the chosen fonts. - */ -#define LCD_LINE_0 LINE(0) -#define LCD_LINE_1 LINE(1) -#define LCD_LINE_2 LINE(2) -#define LCD_LINE_3 LINE(3) -#define LCD_LINE_4 LINE(4) -#define LCD_LINE_5 LINE(5) -#define LCD_LINE_6 LINE(6) -#define LCD_LINE_7 LINE(7) -#define LCD_LINE_8 LINE(8) -#define LCD_LINE_9 LINE(9) -#define LCD_LINE_10 LINE(10) -#define LCD_LINE_11 LINE(11) -#define LCD_LINE_12 LINE(12) -#define LCD_LINE_13 LINE(13) -#define LCD_LINE_14 LINE(14) -#define LCD_LINE_15 LINE(15) -#define LCD_LINE_16 LINE(16) -#define LCD_LINE_17 LINE(17) -#define LCD_LINE_18 LINE(18) -#define LCD_LINE_19 LINE(19) -#define LCD_LINE_20 LINE(20) -#define LCD_LINE_21 LINE(21) -#define LCD_LINE_22 LINE(22) -#define LCD_LINE_23 LINE(23) -#define LCD_LINE_24 LINE(24) -#define LCD_LINE_25 LINE(25) -#define LCD_LINE_26 LINE(26) -#define LCD_LINE_27 LINE(27) -#define LCD_LINE_28 LINE(28) -#define LCD_LINE_29 LINE(29) - - -/** - * @brief LCD default font - */ -#define LCD_DEFAULT_FONT Font16x24 - -/** - * @brief LCD Direction - */ -#define LCD_DIR_HORIZONTAL 0x0000 -#define LCD_DIR_VERTICAL 0x0001 - -/** - * @brief LCD Size (Width and Height) - */ -#define LCD_PIXEL_WIDTH 0x0140 -#define LCD_PIXEL_HEIGHT 0x00F0 - -/** - * @} - */ - -/** @defgroup STM32L152_EVAL_LCD_Exported_Macros - * @{ - */ -#define ASSEMBLE_RGB(R, G, B) ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3)) - -/** - * @} - */ - -/** @defgroup STM32L152_EVAL_LCD_Exported_Functions - * @{ - */ -void STM32L152_LCD_DeInit(void); -void LCD_Setup(void); -void STM32L152_LCD_Init(void); -void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor); -void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor); -void LCD_SetTextColor(__IO uint16_t Color); -void LCD_SetBackColor(__IO uint16_t Color); -void LCD_ClearLine(uint8_t Line); -void LCD_Clear(uint16_t Color); -void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos); -void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c); -void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii); -void LCD_SetFont(sFONT *fonts); -sFONT *LCD_GetFont(void); -void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr); -void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width); -void LCD_WindowModeDisable(void); -void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction); -void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width); -void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius); -void LCD_DrawMonoPict(const uint32_t *Pict); -void LCD_DrawBMP(uint32_t BmpAddress); -void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2); -void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height); -void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius); -void LCD_PolyLine(pPoint Points, uint16_t PointCount); -void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount); -void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount); -void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount); -void LCD_FillPolyLine(pPoint Points, uint16_t PointCount); -void LCD_nCS_StartByte(uint8_t Start_Byte); -void LCD_WriteRegIndex(uint8_t LCD_Reg); -void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue); -void LCD_WriteRAM_Prepare(void); -void LCD_WriteRAMWord(uint16_t RGB_Code); -uint16_t LCD_ReadReg(uint8_t LCD_Reg); -void LCD_WriteRAM(uint16_t RGB_Code); -void LCD_PowerOn(void); -void LCD_DisplayOn(void); -void LCD_DisplayOff(void); - -void LCD_CtrlLinesConfig(void); -void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal); -void LCD_SPIConfig(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L152_EVAL_LCD_H */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/stm32_eval.c b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/stm32_eval.c deleted file mode 100644 index 9f7aa00be..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/stm32_eval.c +++ /dev/null @@ -1,120 +0,0 @@ -/** - ****************************************************************************** - * @file stm32_eval.c - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief STM32xx-EVAL abstraction layer. - * This file should be added to the main application to use the provided - * functions that manage Leds, push-buttons, COM ports and low level - * HW resources initialization of the different modules available on - * STM32 evaluation boards from STMicroelectronics. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32_eval.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @defgroup STM32_EVAL - * @brief This file provides firmware functions to manage Leds, push-buttons, - * COM ports and low level HW resources initialization of the different - * modules available on STM32 Evaluation Boards from STMicroelectronics. - * @{ - */ - -/** @defgroup STM32_EVAL_Abstraction_Layer - * @{ - */ - -#ifdef USE_STM32100B_EVAL - #include "stm32100b_eval/stm32100b_eval.c" -#elif defined USE_STM3210B_EVAL - #include "stm3210b_eval/stm3210b_eval.c" -#elif defined USE_STM3210E_EVAL - #include "stm3210e_eval/stm3210e_eval.c" -#elif defined USE_STM3210C_EVAL - #include "stm3210c_eval/stm3210c_eval.c" -#elif defined USE_STM32L152_EVAL - #include "stm32l152_eval/stm32l152_eval.c" -#elif defined USE_STM32100E_EVAL - #include "stm32100e_eval/stm32100e_eval.c" -#else - #error "Please select first the STM32 EVAL board to be used (in stm32_eval.h)" -#endif - -/** @defgroup STM32_EVAL_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32_EVAL_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32_EVAL_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32_EVAL_Private_Variables - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32_EVAL_Private_FunctionPrototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32_EVAL_Private_Functions - * @{ - */ -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/stm32_eval.h b/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/stm32_eval.h deleted file mode 100644 index 5c988449f..000000000 --- a/src/act/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/stm32_eval.h +++ /dev/null @@ -1,368 +0,0 @@ -/** - ****************************************************************************** - * @file stm32_eval.h - * @author MCD Application Team - * @version V4.5.0 - * @date 07-March-2011 - * @brief Header file for stm32_eval.c module. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32_EVAL_H -#define __STM32_EVAL_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32_EVAL - * @{ - */ - -/** @defgroup STM32_EVAL_Abstraction_Layer - * @{ - */ - -/** @defgroup STM32_EVAL_HARDWARE_RESOURCES - * @{ - */ - -/** -@code - The table below gives an overview of the hardware resources supported by each - STM32 EVAL board. - - LCD: TFT Color LCD (Parallel (FSMC) and Serial (SPI)) - - IOE: IO Expander on I2C - - sFLASH: serial SPI FLASH (M25Pxxx) - - sEE: serial I2C EEPROM (M24C08, M24C32, M24C64) - - TSENSOR: Temperature Sensor (LM75) - - SD: SD Card memory (SPI and SDIO (SD Card MODE)) - =================================================================================================================+ - STM32 EVAL | LED | Buttons | Com Ports | LCD | IOE | sFLASH | sEE | TSENSOR | SD (SPI) | SD(SDIO) | - =================================================================================================================+ - STM3210B-EVAL | 4 | 8 | 2 | YES (SPI) | NO | YES | NO | YES | YES | NO | - -----------------------------------------------------------------------------------------------------------------+ - STM3210E-EVAL | 4 | 8 | 2 | YES (FSMC)| NO | YES | NO | YES | NO | YES | - -----------------------------------------------------------------------------------------------------------------+ - STM3210C-EVAL | 4 | 3 | 1 | YES (SPI) | YES | NO | YES | NO | YES | NO | - -----------------------------------------------------------------------------------------------------------------+ - STM32100B-EVAL | 4 | 8 | 2 | YES (SPI) | NO | YES | NO | YES | YES | NO | - -----------------------------------------------------------------------------------------------------------------+ - STM32L152-EVAL | 4 | 8 | 2 | YES (SPI) | NO | NO | NO | YES | YES | NO | - -----------------------------------------------------------------------------------------------------------------+ - STM32100E-EVAL | 4 | 8 | 2 | YES (FSMC)| YES | YES | YES | YES | YES | NO | - =================================================================================================================+ -@endcode -*/ - -/** - * @} - */ - -/** @defgroup STM32_EVAL_Exported_Types - * @{ - */ -typedef enum -{ - LED1 = 0, - LED2 = 1, - LED3 = 2, - LED4 = 3 -} Led_TypeDef; - -typedef enum -{ - BUTTON_WAKEUP = 0, - BUTTON_TAMPER = 1, - BUTTON_KEY = 2, - BUTTON_RIGHT = 3, - BUTTON_LEFT = 4, - BUTTON_UP = 5, - BUTTON_DOWN = 6, - BUTTON_SEL = 7 -} Button_TypeDef; - -typedef enum -{ - BUTTON_MODE_GPIO = 0, - BUTTON_MODE_EXTI = 1 -} ButtonMode_TypeDef; - -typedef enum -{ - JOY_NONE = 0, - JOY_SEL = 1, - JOY_DOWN = 2, - JOY_LEFT = 3, - JOY_RIGHT = 4, - JOY_UP = 5 -} JOYState_TypeDef -; - -typedef enum -{ - COM1 = 0, - COM2 = 1 -} COM_TypeDef; -/** - * @} - */ - -/** @defgroup STM32_EVAL_Exported_Constants - * @{ - */ - -/** - * @brief Uncomment the line corresponding to the STMicroelectronics evaluation - * board used in your application. - * - * Tip: To avoid modifying this file each time you need to switch between these - * boards, you can define the board in your toolchain compiler preprocessor. - */ -#if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) && !defined (USE_STM3210E_EVAL)\ - && !defined (USE_STM3210C_EVAL) && !defined (USE_STM32L152_EVAL) && !defined (USE_STM32100E_EVAL) - //#define USE_STM32100B_EVAL - //#define USE_STM3210B_EVAL - //#define USE_STM3210E_EVAL - //#define USE_STM3210C_EVAL - //#define USE_STM32L152_EVAL - //#define USE_STM32100E_EVAL -#endif - -#ifdef USE_STM32100B_EVAL - #include "stm32f10x.h" - #include "stm32100b_eval/stm32100b_eval.h" -#elif defined USE_STM3210B_EVAL - #include "stm32f10x.h" - #include "stm3210b_eval/stm3210b_eval.h" -#elif defined USE_STM3210E_EVAL - #include "stm32f10x.h" - #include "stm3210e_eval/stm3210e_eval.h" -#elif defined USE_STM3210C_EVAL - #include "stm32f10x.h" - #include "stm3210c_eval/stm3210c_eval.h" -#elif defined USE_STM32L152_EVAL - #include "stm32l1xx.h" - #include "stm32l152_eval/stm32l152_eval.h" -#elif defined USE_STM32100E_EVAL - #include "stm32f10x.h" - #include "stm32100e_eval/stm32100e_eval.h" -#else - #error "Please select first the STM32 EVAL board to be used (in stm32_eval.h)" -#endif - - -/** - * @brief STM32 Button Defines Legacy - */ -#define Button_WAKEUP BUTTON_WAKEUP -#define Button_TAMPER BUTTON_TAMPER -#define Button_KEY BUTTON_KEY -#define Button_RIGHT BUTTON_RIGHT -#define Button_LEFT BUTTON_LEFT -#define Button_UP BUTTON_UP -#define Button_DOWN BUTTON_DOWN -#define Button_SEL BUTTON_SEL -#define Mode_GPIO BUTTON_MODE_GPIO -#define Mode_EXTI BUTTON_MODE_EXTI -#define Button_Mode_TypeDef ButtonMode_TypeDef -#define JOY_CENTER JOY_SEL -#define JOY_State_TypeDef JOYState_TypeDef - -/** - * @brief LCD Defines Legacy - */ -#define LCD_RSNWR_GPIO_CLK LCD_NWR_GPIO_CLK -#define LCD_SPI_GPIO_PORT LCD_SPI_SCK_GPIO_PORT -#define LCD_SPI_GPIO_CLK LCD_SPI_SCK_GPIO_CLK -#define R0 LCD_REG_0 -#define R1 LCD_REG_1 -#define R2 LCD_REG_2 -#define R3 LCD_REG_3 -#define R4 LCD_REG_4 -#define R5 LCD_REG_5 -#define R6 LCD_REG_6 -#define R7 LCD_REG_7 -#define R8 LCD_REG_8 -#define R9 LCD_REG_9 -#define R10 LCD_REG_10 -#define R12 LCD_REG_12 -#define R13 LCD_REG_13 -#define R14 LCD_REG_14 -#define R15 LCD_REG_15 -#define R16 LCD_REG_16 -#define R17 LCD_REG_17 -#define R18 LCD_REG_18 -#define R19 LCD_REG_19 -#define R20 LCD_REG_20 -#define R21 LCD_REG_21 -#define R22 LCD_REG_22 -#define R23 LCD_REG_23 -#define R24 LCD_REG_24 -#define R25 LCD_REG_25 -#define R26 LCD_REG_26 -#define R27 LCD_REG_27 -#define R28 LCD_REG_28 -#define R29 LCD_REG_29 -#define R30 LCD_REG_30 -#define R31 LCD_REG_31 -#define R32 LCD_REG_32 -#define R33 LCD_REG_33 -#define R34 LCD_REG_34 -#define R36 LCD_REG_36 -#define R37 LCD_REG_37 -#define R40 LCD_REG_40 -#define R41 LCD_REG_41 -#define R43 LCD_REG_43 -#define R45 LCD_REG_45 -#define R48 LCD_REG_48 -#define R49 LCD_REG_49 -#define R50 LCD_REG_50 -#define R51 LCD_REG_51 -#define R52 LCD_REG_52 -#define R53 LCD_REG_53 -#define R54 LCD_REG_54 -#define R55 LCD_REG_55 -#define R56 LCD_REG_56 -#define R57 LCD_REG_57 -#define R59 LCD_REG_59 -#define R60 LCD_REG_60 -#define R61 LCD_REG_61 -#define R62 LCD_REG_62 -#define R63 LCD_REG_63 -#define R64 LCD_REG_64 -#define R65 LCD_REG_65 -#define R66 LCD_REG_66 -#define R67 LCD_REG_67 -#define R68 LCD_REG_68 -#define R69 LCD_REG_69 -#define R70 LCD_REG_70 -#define R71 LCD_REG_71 -#define R72 LCD_REG_72 -#define R73 LCD_REG_73 -#define R74 LCD_REG_74 -#define R75 LCD_REG_75 -#define R76 LCD_REG_76 -#define R77 LCD_REG_77 -#define R78 LCD_REG_78 -#define R79 LCD_REG_79 -#define R80 LCD_REG_80 -#define R81 LCD_REG_81 -#define R82 LCD_REG_82 -#define R83 LCD_REG_83 -#define R96 LCD_REG_96 -#define R97 LCD_REG_97 -#define R106 LCD_REG_106 -#define R118 LCD_REG_118 -#define R128 LCD_REG_128 -#define R129 LCD_REG_129 -#define R130 LCD_REG_130 -#define R131 LCD_REG_131 -#define R132 LCD_REG_132 -#define R133 LCD_REG_133 -#define R134 LCD_REG_134 -#define R135 LCD_REG_135 -#define R136 LCD_REG_136 -#define R137 LCD_REG_137 -#define R139 LCD_REG_139 -#define R140 LCD_REG_140 -#define R141 LCD_REG_141 -#define R143 LCD_REG_143 -#define R144 LCD_REG_144 -#define R145 LCD_REG_145 -#define R146 LCD_REG_146 -#define R147 LCD_REG_147 -#define R148 LCD_REG_148 -#define R149 LCD_REG_149 -#define R150 LCD_REG_150 -#define R151 LCD_REG_151 -#define R152 LCD_REG_152 -#define R153 LCD_REG_153 -#define R154 LCD_REG_154 -#define R157 LCD_REG_157 -#define R192 LCD_REG_192 -#define R193 LCD_REG_193 -#define R227 LCD_REG_227 -#define R229 LCD_REG_229 -#define R231 LCD_REG_231 -#define R239 LCD_REG_239 -#define White LCD_COLOR_WHITE -#define Black LCD_COLOR_BLACK -#define Grey LCD_COLOR_GREY -#define Blue LCD_COLOR_BLUE -#define Blue2 LCD_COLOR_BLUE2 -#define Red LCD_COLOR_RED -#define Magenta LCD_COLOR_MAGENTA -#define Green LCD_COLOR_GREEN -#define Cyan LCD_COLOR_CYAN -#define Yellow LCD_COLOR_YELLOW -#define Line0 LCD_LINE_0 -#define Line1 LCD_LINE_1 -#define Line2 LCD_LINE_2 -#define Line3 LCD_LINE_3 -#define Line4 LCD_LINE_4 -#define Line5 LCD_LINE_5 -#define Line6 LCD_LINE_6 -#define Line7 LCD_LINE_7 -#define Line8 LCD_LINE_8 -#define Line9 LCD_LINE_9 -#define Horizontal LCD_DIR_HORIZONTAL -#define Vertical LCD_DIR_VERTICAL - - -/** - * @} - */ - -/** @defgroup STM32_EVAL_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32_EVAL_Exported_Functions - * @{ - */ -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32_EVAL_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) 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