Small RAM saving.
Some code ported for the ersky9x board Mavlink port commited
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bsongis
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/*
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* Authors - Gerard Valade <gerard.valade@gmail.com>
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*
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* Adapted from frsky
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#include "open9x.h"
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#include "serial.h"
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/*
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Receive serial (RS-232) characters, detecting and storing each Fr-Sky
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0x7e-framed packet as it arrives. When a complete packet has been
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received, process its data into storage variables. NOTE: This is an
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interrupt routine and should not get too lengthy. I originally had
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the buffer being checked in the perMain function (because per10ms
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isn't quite often enough for data streaming at 9600baud) but alas
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that scheme lost packets also. So each packet is parsed as it arrives,
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directly at the ISR function (through a call to frskyProcessPacket).
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If this proves a problem in the future, then I'll just have to implement
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a second buffer to receive data while one buffer is being processed (slowly).
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*/
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#ifndef SIMU
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ISR (USART0_RX_vect)
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{
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uint8_t iostat; //USART control and Status Register 0 A
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// uint8_t rh; //USART control and Status Register 0 B
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UCSR0B &= ~(1 << RXCIE0); // disable Interrupt
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sei();
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iostat = UCSR0A; //USART control and Status Register 0 A
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uint8_t byte = UDR0;
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/*
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bit 7 6 5 4 3 2 1 0
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RxC0 TxC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0
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RxC0: Receive complete
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TXC0: Transmit Complete
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UDRE0: USART Data Register Empty
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FE0: Frame Error
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DOR0: Data OverRun
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UPE0: USART Parity Error
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U2X0: Double Tx Speed
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MPCM0: MultiProcessor Comms Mode
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*/
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if (iostat & ((1 << FE0) | (1 << DOR0) | (1 << UPE0))) {
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byte = 0;
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}
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//rh = UCSR0B; //USART control and Status Register 0 B
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#ifdef MAVLINK
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(RXHandler)(byte);
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#endif
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cli();
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UCSR0B |= (1 << RXCIE0); // enable Interrupt
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}
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#endif
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inline void SERIAL_EnableRXD(void) {
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UCSR0B |= (1 << RXEN0); // enable RX
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UCSR0B |= (1 << RXCIE0); // enable Interrupt
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}
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#if 0
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void SERIAL_DisableRXD(void) {
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UCSR0B &= ~(1 << RXEN0); // disable RX
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UCSR0B &= ~(1 << RXCIE0); // disable Interrupt
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}
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#endif
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/*
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USART0 (transmit) Data Register Emtpy ISR
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Usef to transmit FrSky data packets, which are buffered in frskyTXBuffer.
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*/
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uint8_t serialTxBuffer[MAX_TX_BUFFER]; // 32 characters
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uint8_t serialTxBufferCount = 0;
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uint8_t * ptrTxISR = 0;
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serial_tx_state_t serialTxState = TX_STATE_EMPTY;
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#ifndef SIMU
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ISR(USART0_UDRE_vect)
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{
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if (serialTxBufferCount > 0) {
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UDR0 = *ptrTxISR++;
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serialTxBufferCount--;
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} else {
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UCSR0B &= ~(1 << UDRIE0); // disable UDRE0 interrupt
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serialTxState = TX_STATE_EMPTY;
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}
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}
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#endif
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void SERIAL_start_uart_send() {
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ptrTxISR = serialTxBuffer;
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serialTxBufferCount = 0;
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}
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void SERIAL_end_uart_send() {
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ptrTxISR = serialTxBuffer;
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//UCSR0B |= (1 << UDRIE0); // enable UDRE0 interrupt
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serialTxState = TX_STATE_READY;
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}
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void SERIAL_send_uart_bytes(uint8_t * buf, uint16_t len) {
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while (len--) {
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*ptrTxISR++ = *buf++;
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serialTxBufferCount++;
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}
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}
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#if 0
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void SERIAL_transmitBuffer(uint8_t len) {
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serialTxBufferCount = len;
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ptrTxISR = serialTxBuffer;
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//UCSR0B |= (1 << UDRIE0); // enable UDRE0 interrupt
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serialTxState = TX_STATE_READY;
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}
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#endif
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void SERIAL_startTX(void) {
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if (serialTxState == TX_STATE_READY) {
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serialTxState = TX_STATE_BUSY;
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UCSR0B |= (1 << UDRIE0); // enable UDRE0 interrupt
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}
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}
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static void uart_19200(void) {
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#ifndef SIMU
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#define BAUD 19200
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#include <util/setbaud.h>
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UBRR0H = UBRRH_VALUE;
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UBRR0L = UBRRL_VALUE;
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#if USE_2X
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UCSR0A |= (1 << U2X0);
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#else
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UCSR0A &= ~(1 << U2X0);
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#endif
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#endif
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}
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static void uart_38400(void) {
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#ifndef SIMU
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#undef BAUD // avoid compiler warning
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#define BAUD 38400
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#include <util/setbaud.h>
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UBRR0H = UBRRH_VALUE;
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UBRR0L = UBRRL_VALUE;
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#if USE_2X
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UCSR0A |= (1 << U2X0);
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#else
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UCSR0A &= ~(1 << U2X0);
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#endif
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#endif
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}
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static void uart_57600(void) {
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#ifndef SIMU
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#undef BAUD // avoid compiler warning
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#define BAUD 57600
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#include <util/setbaud.h>
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UBRR0H = UBRRH_VALUE;
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UBRR0L = UBRRL_VALUE;
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#if USE_2X
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UCSR0A |= (1 << U2X0);
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#else
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UCSR0A &= ~(1 << U2X0);
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#endif
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#endif
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}
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inline void SERIAL_EnableTXD(void) {
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//UCSR0B |= (1 << TXEN0); // enable TX
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UCSR0B |= (1 << TXEN0) | (1 << UDRIE0); // enable TX and TX interrupt
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}
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#if 0
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void SERIAL_DisableTXD(void) {
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UCSR0B &= ~(1 << TXEN0); // disable TX
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UCSR0B &= ~(1 << UDRIE0); // disable Interrupt
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}
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#endif
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void SERIAL_Init(void) {
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DDRE &= ~(1 << DDE0); // set RXD0 pin as input
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PORTE &= ~(1 << PORTE0); // disable pullup on RXD0 pin
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uint8_t b = 1; // TODO g_eeGeneral.baudRate;
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if (b == 0) {
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uart_19200();
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}
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else if (b == 1) {
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uart_38400();
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}
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else if (b == 2) {
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uart_57600();
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}
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#if 0
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uart_57600();
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#endif
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// UCSR0A &= ~(1 << U2X0); // disable double speed operation
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// set 8N1
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UCSR0B = 0 | (0 << RXCIE0) | (0 << TXCIE0) | (0 << UDRIE0) | (0 << RXEN0) | (0 << TXEN0) | (0 << UCSZ02);
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UCSR0C = 0 | (1 << UCSZ01) | (1 << UCSZ00);
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while (UCSR0A & (1 << RXC0))
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UDR0; // flush receive buffer
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SERIAL_EnableTXD();
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SERIAL_EnableRXD();
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}
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