From 31183cb840b78828df4f32aeca59582664142fed Mon Sep 17 00:00:00 2001
From: bsongis <bsongis@gmail.com>
Date: Tue, 8 Apr 2014 21:47:59 +0200
Subject: [PATCH] Compilation failure fixed. Plus bootloader check.

---
 radio/src/gui/menu_general.cpp              | 24 +++++++++++++--------
 radio/src/opentx.h                          |  6 ++++--
 radio/src/simpgmspace.cpp                   |  2 ++
 radio/src/targets/sky9x/audio_driver.cpp    |  2 +-
 radio/src/targets/sky9x/pulses_driver.cpp   |  4 ++--
 radio/src/targets/taranis/adc_driver.cpp    |  6 +++---
 radio/src/targets/taranis/audio_driver.cpp  |  8 +++----
 radio/src/targets/taranis/flash_driver.cpp  |  8 +++++--
 radio/src/targets/taranis/pulses_driver.cpp | 18 ++++++++--------
 9 files changed, 46 insertions(+), 32 deletions(-)

diff --git a/radio/src/gui/menu_general.cpp b/radio/src/gui/menu_general.cpp
index 2dc7c7c79..a081ae2f8 100644
--- a/radio/src/gui/menu_general.cpp
+++ b/radio/src/gui/menu_general.cpp
@@ -690,21 +690,27 @@ void flashBootloader(const char * filename)
 {
   FIL file;
   f_open(&file, filename, FA_READ);
-  uint8_t buffer[FLASH_PAGESIZE];
+  uint8_t buffer[1024];
   UINT count;
-  lcd_rect( 3, 6*FH+4, 204, 7);
+  lcd_rect(3, 6*FH+4, 204, 7);
   watchdogSetTimeout(1000/*10s*/);
   unlockFlash();
-  for (int i=0; i<BOOTLOADER_SIZE; i+=FLASH_PAGESIZE) {
-    if (f_read(&file, buffer, FLASH_PAGESIZE, &count) != FR_OK || count != FLASH_PAGESIZE) {
+  for (int i=0; i<BOOTLOADER_SIZE; i+=1024) {
+    if (f_read(&file, buffer, 1024, &count) != FR_OK || count != 1024) {
       // TODO popup error
       break;
     }
-    writeFlash((uint32_t*)(uint64_t)(FIRMWARE_ADDRESS+i), (uint32_t *)buffer);
-    lcd_hline(5, 6*FH+6, (200*i)/BOOTLOADER_SIZE, FORCE);
-    lcd_hline(5, 6*FH+7, (200*i)/BOOTLOADER_SIZE, FORCE);
-    lcd_hline(5, 6*FH+8, (200*i)/BOOTLOADER_SIZE, FORCE);
-    lcdRefresh();
+    if (i==0 && !isBootloaderStart((uint32_t *)buffer)) {
+      // TODO popup error
+      break;
+    }
+    for (int j=0; j<1024; j+=FLASH_PAGESIZE) {
+      writeFlash(CONVERT_UINT_PTR(FIRMWARE_ADDRESS+i+j), (uint32_t *)(buffer+j));
+      lcd_hline(5, 6*FH+6, (200*i)/BOOTLOADER_SIZE, FORCE);
+      lcd_hline(5, 6*FH+7, (200*i)/BOOTLOADER_SIZE, FORCE);
+      lcd_hline(5, 6*FH+8, (200*i)/BOOTLOADER_SIZE, FORCE);
+      lcdRefresh();
+    }
   }
   f_close(&file);
 }
diff --git a/radio/src/opentx.h b/radio/src/opentx.h
index 947aa1988..5c607aea9 100644
--- a/radio/src/opentx.h
+++ b/radio/src/opentx.h
@@ -240,13 +240,15 @@
   #if !defined(NOINLINE)
     #define NOINLINE
   #endif
-  #define CONVERT_PTR(x) ((uint32_t)(uint64_t)(x))
+  #define CONVERT_PTR_UINT(x) ((uint32_t)(uint64_t)(x))
+  #define CONVERT_UINT_PTR(x) ((uint32_t*)(uint64_t)(x))
   char *convertSimuPath(const char *path);
 #else
   #define FORCEINLINE inline __attribute__ ((always_inline))
   #define NOINLINE __attribute__ ((noinline))
   #define SIMU_SLEEP(x)
-  #define CONVERT_PTR(x) ((uint32_t)(x))
+  #define CONVERT_PTR_UINT(x) ((uint32_t)(x))
+  #define CONVERT_UINT_PTR(x) ((uint32_t *)(x))
   #define convertSimuPath(x) (x)
 #endif
 
diff --git a/radio/src/simpgmspace.cpp b/radio/src/simpgmspace.cpp
index c989e5d39..0d4b2eb3d 100644
--- a/radio/src/simpgmspace.cpp
+++ b/radio/src/simpgmspace.cpp
@@ -672,6 +672,8 @@ void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState New
 void RCC_LSEConfig(uint8_t RCC_LSE) { }
 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) { return RESET; }
 ErrorStatus RTC_WaitForSynchro(void) { return SUCCESS; }
+void unlockFlash() { }
 void writeFlash(uint32_t *address, uint32_t *buffer) { SIMU_SLEEP(100); }
+uint32_t isBootloaderStart(uint32_t *block) { return 1; }
 #endif
 
diff --git a/radio/src/targets/sky9x/audio_driver.cpp b/radio/src/targets/sky9x/audio_driver.cpp
index d7c5dd323..5f18edda4 100644
--- a/radio/src/targets/sky9x/audio_driver.cpp
+++ b/radio/src/targets/sky9x/audio_driver.cpp
@@ -111,7 +111,7 @@ extern "C" void DAC_IRQHandler()
 {
   AudioBuffer *nextBuffer = audioQueue.getNextFilledBuffer();
   if (nextBuffer) {
-    DACC->DACC_TNPR = CONVERT_PTR(nextBuffer->data);
+    DACC->DACC_TNPR = CONVERT_PTR_UINT(nextBuffer->data);
     DACC->DACC_TNCR = nextBuffer->size/2;
   }
   else {
diff --git a/radio/src/targets/sky9x/pulses_driver.cpp b/radio/src/targets/sky9x/pulses_driver.cpp
index a5aef743e..86f93bb90 100644
--- a/radio/src/targets/sky9x/pulses_driver.cpp
+++ b/radio/src/targets/sky9x/pulses_driver.cpp
@@ -167,7 +167,7 @@ extern "C" void PWM_IRQHandler(void)
         else {
           // Kick off serial output here
           sscptr = SSC;
-          sscptr->SSC_TPR = CONVERT_PTR(pxxStream[0]);
+          sscptr->SSC_TPR = CONVERT_PTR_UINT(pxxStream[0]);
           sscptr->SSC_TCR = (uint8_t *)pxxStreamPtr[0] - (uint8_t *)pxxStream[0];
           sscptr->SSC_PTCR = SSC_PTCR_TXTEN; // Start transfers
         }
@@ -191,7 +191,7 @@ extern "C" void PWM_IRQHandler(void)
         else {
           // Kick off serial output here
           sscptr = SSC;
-          sscptr->SSC_TPR = CONVERT_PTR(dsm2Stream);
+          sscptr->SSC_TPR = CONVERT_PTR_UINT(dsm2Stream);
           sscptr->SSC_TCR = (uint8_t *)dsm2StreamPtr - (uint8_t *)dsm2Stream;
           sscptr->SSC_PTCR = SSC_PTCR_TXTEN; // Start transfers
         }
diff --git a/radio/src/targets/taranis/adc_driver.cpp b/radio/src/targets/taranis/adc_driver.cpp
index cabb2565b..28ee55976 100644
--- a/radio/src/targets/taranis/adc_driver.cpp
+++ b/radio/src/targets/taranis/adc_driver.cpp
@@ -99,8 +99,8 @@ void adcInit()
   ADC->CCR = 0 ; //ADC_CCR_ADCPRE_0 ;             // Clock div 2
 
   DMA2_Stream0->CR = DMA_SxCR_PL | DMA_SxCR_MSIZE_0 | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC ;
-  DMA2_Stream0->PAR = CONVERT_PTR(&ADC1->DR);
-  DMA2_Stream0->M0AR = CONVERT_PTR(Analog_values);
+  DMA2_Stream0->PAR = CONVERT_PTR_UINT(&ADC1->DR);
+  DMA2_Stream0->M0AR = CONVERT_PTR_UINT(Analog_values);
   DMA2_Stream0->FCR = DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
 }
 
@@ -111,7 +111,7 @@ void adcRead()
   DMA2_Stream0->CR &= ~DMA_SxCR_EN ;              // Disable DMA
   ADC1->SR &= ~(uint32_t) ( ADC_SR_EOC | ADC_SR_STRT | ADC_SR_OVR ) ;
   DMA2->LIFCR = DMA_LIFCR_CTCIF0 | DMA_LIFCR_CHTIF0 |DMA_LIFCR_CTEIF0 | DMA_LIFCR_CDMEIF0 | DMA_LIFCR_CFEIF0 ; // Write ones to clear bits
-  DMA2_Stream0->M0AR = CONVERT_PTR(Analog_values);
+  DMA2_Stream0->M0AR = CONVERT_PTR_UINT(Analog_values);
   DMA2_Stream0->NDTR = NUMBER_ANALOG ;
   DMA2_Stream0->CR |= DMA_SxCR_EN ;               // Enable DMA
   ADC1->CR2 |= (uint32_t)ADC_CR2_SWSTART ;
diff --git a/radio/src/targets/taranis/audio_driver.cpp b/radio/src/targets/taranis/audio_driver.cpp
index 15d6fdd37..9c350b16a 100644
--- a/radio/src/targets/taranis/audio_driver.cpp
+++ b/radio/src/targets/taranis/audio_driver.cpp
@@ -78,8 +78,8 @@ void dacInit()
   DMA1->HIFCR = DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5 | DMA_HIFCR_CTEIF5 | DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5 ; // Write ones to clear bits
   DMA1_Stream5->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 |
                      DMA_SxCR_MSIZE_0 | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_CIRC ;
-  DMA1_Stream5->PAR = CONVERT_PTR(&DAC->DHR12R1);
-  // DMA1_Stream5->M0AR = CONVERT_PTR(Sine_values);
+  DMA1_Stream5->PAR = CONVERT_PTR_UINT(&DAC->DHR12R1);
+  // DMA1_Stream5->M0AR = CONVERT_PTR_UINT(Sine_values);
   DMA1_Stream5->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
   // DMA1_Stream5->NDTR = 100 ;
 
@@ -99,7 +99,7 @@ bool dacQueue(AudioBuffer *buffer)
     dacIdle = 0;
     DMA1_Stream5->CR &= ~DMA_SxCR_EN ;                              // Disable DMA channel
     DMA1->HIFCR = DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5 | DMA_HIFCR_CTEIF5 | DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5 ; // Write ones to clear bits
-    DMA1_Stream5->M0AR = CONVERT_PTR(buffer->data);
+    DMA1_Stream5->M0AR = CONVERT_PTR_UINT(buffer->data);
     DMA1_Stream5->NDTR = buffer->size;
     DMA1_Stream5->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE ;               // Enable DMA channel and interrupt
     DAC->SR = DAC_SR_DMAUDR1 ;                      // Write 1 to clear flag
@@ -156,7 +156,7 @@ extern "C" void DMA1_Stream5_IRQHandler()
 
   AudioBuffer *nextBuffer = audioQueue.getNextFilledBuffer();
   if (nextBuffer) {
-    DMA1_Stream5->M0AR = CONVERT_PTR(nextBuffer->data);
+    DMA1_Stream5->M0AR = CONVERT_PTR_UINT(nextBuffer->data);
     DMA1_Stream5->NDTR = nextBuffer->size;
     DMA1->HIFCR = DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5 | DMA_HIFCR_CTEIF5 | DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5 ; // Write ones to clear bits
     DMA1_Stream5->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE ;       // Enable DMA channel
diff --git a/radio/src/targets/taranis/flash_driver.cpp b/radio/src/targets/taranis/flash_driver.cpp
index d081a2422..7e5be65ba 100644
--- a/radio/src/targets/taranis/flash_driver.cpp
+++ b/radio/src/targets/taranis/flash_driver.cpp
@@ -114,6 +114,10 @@ uint32_t isFirmwareStart(uint32_t *block)
 
 uint32_t isBootloaderStart(uint32_t *block)
 {
-  // TODO search for "BOOT" inside the block
-  return 1;
+  for (int i=0; i<256; i++) {
+    if (block[i] == 0x544F4F42/*BOOT*/) {
+      return 1;
+    }
+  }
+  return 0;
 }
diff --git a/radio/src/targets/taranis/pulses_driver.cpp b/radio/src/targets/taranis/pulses_driver.cpp
index 03dba6085..d91da6834 100644
--- a/radio/src/targets/taranis/pulses_driver.cpp
+++ b/radio/src/targets/taranis/pulses_driver.cpp
@@ -259,8 +259,8 @@ static void init_pa10_pxx()
   DMA2->HIFCR = DMA_HIFCR_CTCIF6 | DMA_HIFCR_CHTIF6 | DMA_HIFCR_CTEIF6 | DMA_HIFCR_CDMEIF6 | DMA_HIFCR_CFEIF6 ; // Write ones to clear bits
   DMA2_Stream6->CR = DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0
                                                          | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ;
-  DMA2_Stream6->PAR = CONVERT_PTR(&TIM1->DMAR);
-  DMA2_Stream6->M0AR = CONVERT_PTR(&pxxStream[INTERNAL_MODULE][1]);
+  DMA2_Stream6->PAR = CONVERT_PTR_UINT(&TIM1->DMAR);
+  DMA2_Stream6->M0AR = CONVERT_PTR_UINT(&pxxStream[INTERNAL_MODULE][1]);
 //      DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
 //      DMA2_Stream2->NDTR = 100 ;
   DMA2_Stream6->CR |= DMA_SxCR_EN ;               // Enable DMA
@@ -344,7 +344,7 @@ extern "C" void TIM1_CC_IRQHandler()
   if (s_current_protocol[INTERNAL_MODULE] == PROTO_PXX) {
     DMA2_Stream6->CR &= ~DMA_SxCR_EN ;              // Disable DMA
     DMA2->HIFCR = DMA_HIFCR_CTCIF6 | DMA_HIFCR_CHTIF6 | DMA_HIFCR_CTEIF6 | DMA_HIFCR_CDMEIF6 | DMA_HIFCR_CFEIF6 ; // Write ones to clear bits
-    DMA2_Stream6->M0AR = CONVERT_PTR(&pxxStream[INTERNAL_MODULE][1]);
+    DMA2_Stream6->M0AR = CONVERT_PTR_UINT(&pxxStream[INTERNAL_MODULE][1]);
     DMA2_Stream6->CR |= DMA_SxCR_EN ;               // Enable DMA
     TIM1->CCR3 = pxxStream[INTERNAL_MODULE][0];
     TIM1->DIER |= TIM_DIER_CC2IE ;  // Enable this interrupt
@@ -422,8 +422,8 @@ static void init_pa7_pxx()
   DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
   DMA2_Stream2->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0
                                                          | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ;
-  DMA2_Stream2->PAR = CONVERT_PTR(&TIM8->DMAR);
-  DMA2_Stream2->M0AR = CONVERT_PTR(&pxxStream[EXTERNAL_MODULE][1]);
+  DMA2_Stream2->PAR = CONVERT_PTR_UINT(&TIM8->DMAR);
+  DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&pxxStream[EXTERNAL_MODULE][1]);
 //      DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
 //      DMA2_Stream2->NDTR = 100 ;
   DMA2_Stream2->CR |= DMA_SxCR_EN ;               // Enable DMA
@@ -496,8 +496,8 @@ static void init_pa7_dsm2()
   DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
   DMA2_Stream2->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0
                                                          | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ;
-  DMA2_Stream2->PAR = CONVERT_PTR(&TIM8->DMAR);
-  DMA2_Stream2->M0AR = CONVERT_PTR(&dsm2Stream[1]);
+  DMA2_Stream2->PAR = CONVERT_PTR_UINT(&TIM8->DMAR);
+  DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&dsm2Stream[1]);
 //      DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
 //      DMA2_Stream2->NDTR = 100 ;
   DMA2_Stream2->CR |= DMA_SxCR_EN ;               // Enable DMA
@@ -586,7 +586,7 @@ extern "C" void TIM8_CC_IRQHandler()
   if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PXX) {
     DMA2_Stream2->CR &= ~DMA_SxCR_EN ;              // Disable DMA
     DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
-    DMA2_Stream2->M0AR = CONVERT_PTR(&pxxStream[EXTERNAL_MODULE][1]);
+    DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&pxxStream[EXTERNAL_MODULE][1]);
     DMA2_Stream2->CR |= DMA_SxCR_EN ;               // Enable DMA
     TIM8->CCR1 = pxxStream[EXTERNAL_MODULE][0];
     TIM8->DIER |= TIM_DIER_CC2IE ;  // Enable this interrupt
@@ -595,7 +595,7 @@ extern "C" void TIM8_CC_IRQHandler()
   else if (s_current_protocol[EXTERNAL_MODULE] >= PROTO_DSM2_LP45 && s_current_protocol[EXTERNAL_MODULE] <= PROTO_DSM2_DSMX) {
     DMA2_Stream2->CR &= ~DMA_SxCR_EN ;              // Disable DMA
     DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
-    DMA2_Stream2->M0AR = CONVERT_PTR(&dsm2Stream[1]);
+    DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&dsm2Stream[1]);
     DMA2_Stream2->CR |= DMA_SxCR_EN ;               // Enable DMA
     TIM8->CCR1 = dsm2Stream[0];
     TIM8->DIER |= TIM_DIER_CC2IE ;  // Enable this interrupt