[Taranis X9E] Fixes (frequencies on M4, pots calibration, soft power
delay after startup)
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@@ -163,6 +163,7 @@ void adcRead()
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DMA2->LIFCR = DMA_LIFCR_CTCIF0 | DMA_LIFCR_CHTIF0 |DMA_LIFCR_CTEIF0 | DMA_LIFCR_CDMEIF0 | DMA_LIFCR_CFEIF0 ; // Write ones to clear bits
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DMA2_Stream0->CR |= DMA_SxCR_EN ; // Enable DMA
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ADC1->CR2 |= (uint32_t)ADC_CR2_SWSTART ;
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#if defined(REV9E)
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DMA2_Stream1->CR &= ~DMA_SxCR_EN ; // Disable DMA
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ADC3->SR &= ~(uint32_t) ( ADC_SR_EOC | ADC_SR_STRT | ADC_SR_OVR ) ;
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@@ -170,12 +171,23 @@ void adcRead()
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DMA2_Stream1->CR |= DMA_SxCR_EN ; // Enable DMA
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ADC3->CR2 |= (uint32_t)ADC_CR2_SWSTART ;
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#endif // #if defined(REV9E)
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#if defined(REV9E)
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for (unsigned int i=0; i<10000; i++) {
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if ((DMA2->LISR & DMA_LISR_TCIF0) && (DMA2->LISR & DMA_LISR_TCIF1)) {
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break;
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}
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}
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DMA2_Stream0->CR &= ~DMA_SxCR_EN ; // Disable DMA
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DMA2_Stream1->CR &= ~DMA_SxCR_EN ; // Disable DMA
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#else
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for (unsigned int i=0; i<10000; i++) {
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if (DMA2->LISR & DMA_LISR_TCIF0) {
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break;
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}
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}
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DMA2_Stream0->CR &= ~DMA_SxCR_EN ; // Disable DMA
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#endif
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#if !defined(REV3)
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// adc direction correct
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