From 4ffb1a34dc424f6c6bea5cd948b7769ec96b1391 Mon Sep 17 00:00:00 2001
From: 3djc <lesitewebdejc@hotmail.com>
Date: Thu, 9 Apr 2020 10:19:49 +0200
Subject: [PATCH] Fix T12 DMA conflict (#7505)

---
 .../arm/stm32/intmodule_serial_driver.cpp     | 32 ++++++++++++++++++-
 radio/src/targets/taranis/hal.h               |  5 ---
 2 files changed, 31 insertions(+), 6 deletions(-)

diff --git a/radio/src/targets/common/arm/stm32/intmodule_serial_driver.cpp b/radio/src/targets/common/arm/stm32/intmodule_serial_driver.cpp
index e2f01f586..56b71d97c 100755
--- a/radio/src/targets/common/arm/stm32/intmodule_serial_driver.cpp
+++ b/radio/src/targets/common/arm/stm32/intmodule_serial_driver.cpp
@@ -21,12 +21,18 @@
 #include "opentx.h"
 
 ModuleFifo intmoduleFifo;
+#if !defined(INTMODULE_DMA_STREAM)
+uint8_t * intmoduleTxBufferData;
+uint8_t intmoduleTxBufferRemaining;
+#endif
 
 void intmoduleStop()
 {
   GPIO_ResetBits(INTMODULE_PWR_GPIO, INTMODULE_PWR_GPIO_PIN);
 
+#if defined(INTMODULE_DMA_STREAM)
   INTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA
+#endif
 
   GPIO_InitTypeDef GPIO_InitStructure;
   GPIO_InitStructure.GPIO_Pin = INTMODULE_TX_GPIO_PIN | INTMODULE_RX_GPIO_PIN;
@@ -57,7 +63,11 @@ void intmoduleSerialStart(uint32_t baudrate, uint8_t rxEnable, uint16_t parity,
   INTERNAL_MODULE_ON();
 
   NVIC_InitTypeDef NVIC_InitStructure;
+#if defined(INTMODULE_DMA_STREAM)
   NVIC_InitStructure.NVIC_IRQChannel = INTMODULE_DMA_STREAM_IRQ;
+#else
+  NVIC_InitStructure.NVIC_IRQChannel = INTMODULE_USART_IRQn;
+#endif
   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; /* Not used as 4 bits are used for the pre-emption priority. */;
   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
@@ -118,8 +128,22 @@ void intmoduleTimerStart(uint32_t periodMs)
 #define USART_FLAG_ERRORS (USART_FLAG_ORE | USART_FLAG_NE | USART_FLAG_FE | USART_FLAG_PE)
 extern "C" void INTMODULE_USART_IRQHandler(void)
 {
-  uint32_t status = INTMODULE_USART->SR;
+#if !defined(INTMODULE_DMA_STREAM)
+  // Send
+  if (USART_GetITStatus(INTMODULE_USART, USART_IT_TXE) != RESET) {
+    if (intmoduleTxBufferRemaining) {
+      USART_SendData(INTMODULE_USART, intmoduleTxBufferData[0]);
+      intmoduleTxBufferData++;
+      intmoduleTxBufferRemaining--;
+    }
+    else {
+      USART_ITConfig(INTMODULE_USART, USART_IT_TXE, DISABLE);
+    }
+  }
+#endif
 
+  // Receive
+  uint32_t status = INTMODULE_USART->SR;
   while (status & (USART_FLAG_RXNE | USART_FLAG_ERRORS)) {
     uint8_t data = INTMODULE_USART->DR;
     if (status & USART_FLAG_ERRORS) {
@@ -143,6 +167,7 @@ void intmoduleSendBuffer(const uint8_t * data, uint8_t size)
   if (size == 0)
     return;
 
+#if defined(INTMODULE_DMA_STREAM)
   DMA_InitTypeDef DMA_InitStructure;
   DMA_DeInit(INTMODULE_DMA_STREAM);
   DMA_InitStructure.DMA_Channel = INTMODULE_DMA_CHANNEL;
@@ -163,6 +188,11 @@ void intmoduleSendBuffer(const uint8_t * data, uint8_t size)
   DMA_Init(INTMODULE_DMA_STREAM, &DMA_InitStructure);
   DMA_Cmd(INTMODULE_DMA_STREAM, ENABLE);
   USART_DMACmd(INTMODULE_USART, USART_DMAReq_Tx, ENABLE);
+#else
+  intmoduleTxBufferData = (uint8_t *)data;
+  intmoduleTxBufferRemaining = size;
+  USART_ITConfig(INTMODULE_USART, USART_IT_TXE, ENABLE);
+#endif
 }
 
 void intmoduleSendNextFrame()
diff --git a/radio/src/targets/taranis/hal.h b/radio/src/targets/taranis/hal.h
index b8d1c7177..b55226edf 100644
--- a/radio/src/targets/taranis/hal.h
+++ b/radio/src/targets/taranis/hal.h
@@ -1078,11 +1078,6 @@
   #define INTMODULE_GPIO_AF               GPIO_AF_USART3
   #define INTMODULE_USART_IRQn            USART3_IRQn
   #define INTMODULE_USART_IRQHandler      USART3_IRQHandler
-  #define INTMODULE_DMA_STREAM            DMA1_Stream3
-  #define INTMODULE_DMA_STREAM_IRQ        DMA1_Stream3_IRQn
-  #define INTMODULE_DMA_STREAM_IRQHandler DMA1_Stream3_IRQHandler
-  #define INTMODULE_DMA_FLAG_TC           DMA_IT_TCIF3
-  #define INTMODULE_DMA_CHANNEL           DMA_Channel_4
   #define INTMODULE_RCC_APB1Periph        RCC_APB1Periph_TIM2
   #define INTMODULE_RCC_APB2Periph        RCC_APB1Periph_USART3
   #define INTMODULE_TIMER                 TIM2