From 5a2d6cb250da23b02baced981cd7138aa0cc0f4b Mon Sep 17 00:00:00 2001 From: bsongis Date: Mon, 10 Dec 2012 21:00:02 +0000 Subject: [PATCH] [X9D] Makefile option added: CPUARM [Sky9x] GVARS Bug in EEPROM [Sky9x] Mu-law codec added --- src/FatFs/ffconf.h | 6 +- src/Makefile | 8 +- src/beeper.h | 11 +- src/board_sky9x.cpp | 133 +- src/board_x9d.cpp | 1153 +++++++ src/board_x9d.h | 112 + src/eeprom_avr.cpp | 6 +- src/frsky.cpp | 20 +- src/general_menus.cpp | 30 +- src/keys.cpp | 4 +- src/lcd.cpp | 4 +- src/main_views.cpp | 2 +- src/model_menus.cpp | 74 +- src/myeeprom.h | 32 +- src/open9x.cpp | 131 +- src/open9x.h | 48 +- src/sdcard.h | 6 +- src/simpgmspace.cpp | 20 +- src/simpgmspace.h | 4 +- src/simu.cpp | 12 +- src/sky9x/audio.cpp | 33 +- src/sky9x/audio.h | 2 +- src/statistics_views.cpp | 8 +- src/translations.cpp | 14 +- src/translations.h | 18 +- src/translations/en.h | 4 +- src/x9d/Audio.c | 105 + src/x9d/Audio.h | 28 + src/x9d/Macro_define.h | 27 + src/x9d/adc.c | 107 + src/x9d/adc.h | 16 + src/x9d/buttons.c | 135 + src/x9d/buttons.h | 5 + src/x9d/hal.h | 255 ++ src/x9d/i2c_ee.c | 426 +++ src/x9d/i2c_ee.h | 56 + src/x9d/lcd_driver.cpp | 197 ++ src/x9d/main.c | 62 + src/x9d/pwr_ctrl.c | 50 + src/x9d/pwr_ctrl.h | 7 + src/x9d/rtc.c | 282 ++ src/x9d/rtc.h | 30 + src/x9d/spi.c | 128 + src/x9d/spi.h | 36 + src/x9d/stm32f2xx.h | 6964 ++++++++++++++++++++++++++++++++++++++ src/x9d/stm32f2xx_it.c | 257 ++ src/x9d/stm32f2xx_it.h | 60 + src/x9d/timer_init.c | 256 ++ src/x9d/timer_init.h | 34 + 49 files changed, 11057 insertions(+), 361 deletions(-) create mode 100644 src/board_x9d.cpp create mode 100644 src/board_x9d.h create mode 100644 src/x9d/Audio.c create mode 100644 src/x9d/Audio.h create mode 100644 src/x9d/Macro_define.h create mode 100644 src/x9d/adc.c create mode 100644 src/x9d/adc.h create mode 100644 src/x9d/buttons.c create mode 100644 src/x9d/buttons.h create mode 100644 src/x9d/hal.h create mode 100644 src/x9d/i2c_ee.c create mode 100644 src/x9d/i2c_ee.h create mode 100644 src/x9d/lcd_driver.cpp create mode 100644 src/x9d/main.c create mode 100644 src/x9d/pwr_ctrl.c create mode 100644 src/x9d/pwr_ctrl.h create mode 100644 src/x9d/rtc.c create mode 100644 src/x9d/rtc.h create mode 100644 src/x9d/spi.c create mode 100644 src/x9d/spi.h create mode 100644 src/x9d/stm32f2xx.h create mode 100644 src/x9d/stm32f2xx_it.c create mode 100644 src/x9d/stm32f2xx_it.h create mode 100644 src/x9d/timer_init.c create mode 100644 src/x9d/timer_init.h diff --git a/src/FatFs/ffconf.h b/src/FatFs/ffconf.h index 5bbce477c..ce30ee020 100644 --- a/src/FatFs/ffconf.h +++ b/src/FatFs/ffconf.h @@ -9,7 +9,7 @@ #ifndef _FFCONF #define _FFCONF 6502 /* Revision ID */ -#if defined(PCBSKY9X) && !defined(SIMU) +#if defined(CPUARM) && !defined(SIMU) #ifdef __cplusplus extern "C" { #endif @@ -98,7 +98,7 @@ extern "C" { / 1 - ASCII only (Valid for non LFN cfg.) */ -#if defined(PCBSKY9X) +#if defined(CPUARM) #define _USE_LFN 2 /* 0 to 3 */ #define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */ #else @@ -184,7 +184,7 @@ extern "C" { /* A header file that defines sync object types on the O/S, such as / windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */ -#if defined(PCBSKY9X) +#if defined(CPUARM) #define _FS_REENTRANT 1 /* 0:Disable or 1:Enable */ #else #define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */ diff --git a/src/Makefile b/src/Makefile index 4011b11d8..00992229c 100644 --- a/src/Makefile +++ b/src/Makefile @@ -449,10 +449,10 @@ RUN_FROM_FLASH = 1 ifeq ($(PCB), X9D) # X9D, so ... OPT = 2 - CPPDEFS += -DPCBX9D -DPCBSKY9X -DREVB -DCPUARM -DEEPROM_VARIANT=0 -DAUDIO -DHAPTIC -DPXX -DDSM2 -DDSM2_PPM -DROTARY_ENCODERS=1 -DLCD212 + CPPDEFS += -DPCBX9D -DCPUARM -DEEPROM_VARIANT=0 -DAUDIO -DHAPTIC -DPXX -DDSM2 -DDSM2_PPM -DROTARY_ENCODERS=1 -DLCD212 EXTRAINCDIRS += sky9x CoOS/kernel CoOS/portable - BOARDSRC = board_sky9x.cpp - EXTRABOARDSRC += sky9x/lcd_driver.cpp + BOARDSRC = board_x9d.cpp + EXTRABOARDSRC += x9d/lcd_driver.cpp SRC += sky9x/core_cm3.c sky9x/board_lowlevel.c sky9x/crt.c sky9x/vectors_sam3s.c SRC += CoOS/kernel/core.c CoOS/kernel/hook.c CoOS/kernel/task.c CoOS/kernel/event.c CoOS/kernel/time.c CoOS/kernel/timer.c CoOS/kernel/flag.c CoOS/kernel/mutex.c CoOS/kernel/serviceReq.c CoOS/portable/GCC/port.c CoOS/portable/arch.c SRC += sky9x/usb/device/core/USBD_UDP.c sky9x/usb/device/core/USBDDriver.c @@ -462,7 +462,7 @@ ifeq ($(PCB), X9D) EEPROMSRC = eeprom_arm.cpp eeprom_conversions.cpp PULSESSRC = pulses_arm.cpp CPPSRC += sky9x/audio.cpp haptic.cpp - CPPSRC += sky9x/sound_driver.cpp sky9x/haptic_driver.cpp sky9x/sdcard_driver.cpp + CPPSRC += sky9x/sound_driver.cpp sky9x/sdcard_driver.cpp CPPSRC += bmp.cpp monitors_views.cpp ifeq ($(SDCARD), YES) diff --git a/src/beeper.h b/src/beeper.h index 367e6048b..a49b19312 100644 --- a/src/beeper.h +++ b/src/beeper.h @@ -44,13 +44,14 @@ extern bool warbleC; extern uint8_t hapticTick; #endif -#if defined(PCBSKY9X) -#include "sky9x/sound.h" -inline void _beep(uint8_t b) { +#if defined(CPUARM) +inline void _beep(uint8_t b) +{ buzzer_sound(b); } #else -inline void _beep(uint8_t b) { +inline void _beep(uint8_t b) +{ g_beepCnt = b; } #endif @@ -86,7 +87,7 @@ extern void beep(uint8_t val); #define IS_AUDIO_BUSY() (g_beepCnt || beepAgain || beepOn) #define AUDIO_RESET() -#if !defined(PCBSKY9X) +#if !defined(CPUARM) inline void AUDIO_HEARTBEAT() { if(g_beepCnt) { diff --git a/src/board_sky9x.cpp b/src/board_sky9x.cpp index c58b6a3a0..db9e66014 100644 --- a/src/board_sky9x.cpp +++ b/src/board_sky9x.cpp @@ -751,7 +751,7 @@ void board_init() startSound() ; - alawInit(); + codecsInit(); eeprom_init(); @@ -760,7 +760,6 @@ void board_init() init_SDcard(); } - #endif // keys: @@ -779,21 +778,8 @@ uint32_t read_keys() x = lcdLock ? lcdInputs : PIOC->PIO_PDSR; // 6 LEFT, 5 RIGHT, 4 DOWN, 3 UP () x <<= 1; -#if defined(PCBX9D) - y = 0; - if (x & 0x00000020) - y |= 0x02 << KEY_PLUS; - if (x & 0x00000004) - y |= 0x02 << KEY_MENU; - if (x & 0x00000010) - y |= 0x02 << KEY_MINUS; - if (x & 0x00000040) - y |= 0x02 << KEY_PAGE; - if (x & 0x02000000) - y |= 0x02 << KEY_EXIT; - if (PIOB->PIO_PDSR & 0x000000020) - y |= 0x02 << KEY_ENTER; -#elif defined(REVA) + +#if defined(REVA) y = (x & 0x00000060); if (x & 0x00000008) y |= 0x10; @@ -898,118 +884,6 @@ uint8_t keyDown() return ~read_keys() & 0x7E ; } -#if defined(PCBX9D) -extern uint32_t keyState(EnumKeys enuk) -{ - register uint32_t c ; - - CPU_UINT xxx = 0; - - if (enuk < (int) DIM(keys)) return keys[enuk].state() ? 1 : 0; - - c = PIOC->PIO_PDSR ; - - // printf("c=%x\n", c); fflush(stdout); - - switch ((uint8_t) enuk) { - case SW_SA0: - xxx = !(c & 0x80000000); - break; - - case SW_SA2: - xxx = c & 0x80000000; - break; - - case SW_SB0: - xxx = !(c & 0x08000000) && !(c & 0x04000000); - break; - - case SW_SB1: - xxx = (c & 0x08000000) && !(c & 0x04000000); - break; - - case SW_SB2: - xxx = !(c & 0x08000000) && (c & 0x04000000); - break; - - case SW_SC0: - xxx = !(c & 0x00800000) && !(c & 0x00400000); - break; - - case SW_SC1: - xxx = (c & 0x00800000) && !(c & 0x00400000); - break; - - case SW_SC2: - xxx = !(c & 0x00800000) && (c & 0x00400000); - break; - - case SW_SD0: - xxx = !(c & 0x00200000) && !(c & 0x00100000); - break; - - case SW_SD1: - xxx = (c & 0x00200000) && !(c & 0x00100000); - break; - - case SW_SD2: - xxx = !(c & 0x00200000) && (c & 0x00100000); - break; - - case SW_SE0: - xxx = !(c & 0x00080000) && !(c & 0x00040000); - break; - - case SW_SE1: - xxx = (c & 0x00080000) && !(c & 0x00040000); - break; - - case SW_SE2: - xxx = !(c & 0x00080000) && (c & 0x00040000); - break; - - case SW_SF0: - xxx = !(c & 0x00020000) && !(c & 0x00010000); - break; - - case SW_SF1: - xxx = (c & 0x00020000) && !(c & 0x00010000); - break; - - case SW_SF2: - xxx = !(c & 0x00020000) && (c & 0x00010000); - break; - - case SW_SG0: - xxx = !(c & 0x00008000) && !(c & 0x00004000); - break; - - case SW_SG1: - xxx = (c & 0x00008000) && !(c & 0x00004000); - break; - - case SW_SG2: - xxx = !(c & 0x00008000) && (c & 0x00004000); - break; - - case SW_SH0: - xxx = !(c & 0x00002000); - break; - - case SW_SH2: - xxx = c & 0x00002000; - break; - - default: - break; - } - - if (xxx) { - return 1; - } - return 0; -} -#else extern uint32_t keyState(EnumKeys enuk) { register uint32_t a ; @@ -1080,7 +954,6 @@ extern uint32_t keyState(EnumKeys enuk) } return 0; } -#endif uint16_t Analog_values[NUMBER_ANALOG] ; uint8_t temperature = 0; // Raw temp reading diff --git a/src/board_x9d.cpp b/src/board_x9d.cpp new file mode 100644 index 000000000..3ec7c3edc --- /dev/null +++ b/src/board_x9d.cpp @@ -0,0 +1,1153 @@ +/* + * Authors (alphabetical order) + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "open9x.h" +#include "sky9x/board.h" + +uint32_t Master_frequency ; +volatile uint32_t Tenms ; + +/** Console baudrate 9600. */ +#define CONSOLE_BAUDRATE 9600 +/** Usart Hw interface used by the console (UART0). */ +#define CONSOLE_USART UART0 +/** Usart Hw ID used by the console (UART0). */ +#define CONSOLE_ID ID_UART0 +/** Pins description corresponding to Rxd,Txd, (UART pins) */ +#define CONSOLE_PINS {PINS_UART} + +/** Second serial baudrate 9600. */ +#define SECOND_BAUDRATE 9600 +/** Usart Hw interface used by the console (UART0). */ +#define SECOND_USART USART0 +/** Usart Hw ID used by the console (UART0). */ +#define SECOND_ID ID_USART0 +/** Pins description corresponding to Rxd,Txd, (UART pins) */ +#define SECOND_PINS {PINS_USART0} + +#define CPU_INT int32_t +#define CPU_UINT uint32_t + +#if !defined(REVA) +inline void init_soft_power() +{ + // Configure RF_power (PC17) + configure_pins( PIO_PC17, PIN_ENABLE | PIN_INPUT | PIN_PORTC | PIN_NO_PULLUP | PIN_PULLDOWN ) ; + configure_pins( PIO_PA8, PIN_ENABLE | PIN_INPUT | PIN_PORTA | PIN_PULLUP ) ; // Enable bit A8 (Soft Power) +} +#endif + +uint32_t check_soft_power() +{ +#ifdef SIMU + return e_power_on; +#else + if ( PIOC->PIO_PDSR & PIO_PC17 ) // Power on + { + return e_power_on ; + } + + if (usbPlugged()) + { + return e_power_usb ; // Detected USB + } + + if ( PIOA->PIO_PDSR & PIO_PA8 ) // Trainer plugged in + { + return e_power_trainer ; + } + + return e_power_off; +#endif +} + +// turn off soft power +void soft_power_off() +{ + configure_pins( PIO_PA8, PIN_ENABLE | PIN_OUTPUT | PIN_LOW | PIN_PORTA | PIN_NO_PULLUP ) ; +} + +extern "C" void sam_boot( void ) ; + +// Prototype +// Free pins (PA16 is stock buzzer) +// PA23, PA24, PA25, PB7, PB13 +// PC20, PC21(labelled 17), PC22, PC24 +// REVB +// PA25, use for stock buzzer +// PB14, PB6 +// PC21, PC19, PC15 (PPM2 output) +inline void config_free_pins() +{ +#if defined(REVA) + register Pio * pioptr = PIOA ; + pioptr->PIO_PER = 0x03800000L ; // Enable bits A25,24,23 + pioptr->PIO_ODR = 0x03800000L ; // Set as input + pioptr->PIO_PUER = 0x03800000L ; // Enable pullups + + pioptr = PIOB ; + pioptr->PIO_PER = 0x00002080L ; // Enable bits B13, 7 + pioptr->PIO_ODR = 0x00002080L ; // Set as input + pioptr->PIO_PUER = 0x00002080L ; // Enable pullups + + pioptr = PIOC ; + pioptr->PIO_PER = 0x01700000L ; // Enable bits C24,22,21,20 + pioptr->PIO_ODR = 0x01700000L ; // Set as input + pioptr->PIO_PUER = 0x01700000L ; // Enable pullups +#else + configure_pins( PIO_PB14, PIN_ENABLE | PIN_INPUT | PIN_PORTB | PIN_PULLUP ) ; +#endif +} + +// Assumes PMC has already enabled clocks to ports +inline void setup_switches() +{ +#if defined(REVA) + register Pio *pioptr = PIOA ; + pioptr->PIO_PER = 0xF8008184 ; // Enable bits + pioptr->PIO_ODR = 0xF8008184 ; // Set bits input + pioptr->PIO_PUER = 0xF8008184 ; // Set bits with pullups + + pioptr = PIOB ; + pioptr->PIO_PER = 0x00000010 ; // Enable bits + pioptr->PIO_ODR = 0x00000010 ; // Set bits input + pioptr->PIO_PUER = 0x00000010 ; // Set bits with pullups + + pioptr = PIOC ; + pioptr->PIO_PER = 0x10014900 ; // Enable bits + pioptr->PIO_ODR = 0x10014900 ; // Set bits input + pioptr->PIO_PUER = 0x10014900 ; // Set bits with pullups +#else + configure_pins( 0x01808087, PIN_ENABLE | PIN_INPUT | PIN_PORTA | PIN_PULLUP ) ; + configure_pins( 0x00000030, PIN_ENABLE | PIN_INPUT | PIN_PORTB | PIN_PULLUP ) ; + configure_pins( 0x91114900, PIN_ENABLE | PIN_INPUT | PIN_PORTC | PIN_PULLUP ) ; +#endif +} + +#ifdef SIMU +#define end_ppm_capture() +#define sam_boot() +#else + +inline void UART3_Configure( uint32_t baudrate, uint32_t masterClock) +{ +// const Pin pPins[] = CONSOLE_PINS; + register Uart *pUart = BT_USART; + + /* Configure PIO */ + configure_pins( (PIO_PB2 | PIO_PB3), PIN_PERIPHERAL | PIN_INPUT | PIN_PER_A | PIN_PORTB | PIN_NO_PULLUP ) ; + + /* Configure PMC */ + PMC->PMC_PCER0 = 1 << BT_ID; + + /* Reset and disable receiver & transmitter */ + pUart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX + | UART_CR_RXDIS | UART_CR_TXDIS; + + /* Configure mode */ + pUart->UART_MR = 0x800 ; // NORMAL, No Parity + + /* Configure baudrate */ + /* Asynchronous, no oversampling */ + pUart->UART_BRGR = ( (masterClock / baudrate) + 8 ) / 16; + + /* Disable PDC channel */ + pUart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS; + + /* Enable receiver and transmitter */ + pUart->UART_CR = UART_CR_RXEN | UART_CR_TXEN; + +#if 0 + pUart->UART_IER = UART_IER_RXRDY ; + NVIC_EnableIRQ(UART1_IRQn) ; +#endif +} + +void UART3_Stop() +{ + BT_USART->UART_IDR = UART_IDR_RXRDY ; + NVIC_DisableIRQ(UART1_IRQn) ; +} + +// USART0 configuration +// Work in Progress, UNTESTED +// Uses PA5 and PA6 (RXD and TXD) +inline void UART2_Configure( uint32_t baudrate, uint32_t masterClock) +{ +//// const Pin pPins[] = CONSOLE_PINS; + register Usart *pUsart = SECOND_USART; + + /* Configure PIO */ + configure_pins( (PIO_PA5 | PIO_PA6), PIN_PERIPHERAL | PIN_INPUT | PIN_PER_A | PIN_PORTA | PIN_NO_PULLUP ) ; + +// /* Configure PMC */ + PMC->PMC_PCER0 = 1 << SECOND_ID; + +// /* Reset and disable receiver & transmitter */ + pUsart->US_CR = US_CR_RSTRX | US_CR_RSTTX + | US_CR_RXDIS | US_CR_TXDIS; + +// /* Configure mode */ + pUsart->US_MR = 0x000008C0 ; // NORMAL, No Parity, 8 bit + +// /* Configure baudrate */ +// /* Asynchronous, no oversampling */ + pUsart->US_BRGR = (masterClock / baudrate) / 16; + +// /* Disable PDC channel */ + pUsart->US_PTCR = US_PTCR_RXTDIS | US_PTCR_TXTDIS; + +// /* Enable receiver and transmitter */ + pUsart->US_CR = US_CR_RXEN | US_CR_TXEN; +} + +// Starts TIMER0 at full speed (MCK/2) for delay timing +// @ 36MHz this is 18MHz +// This was 6 MHz, we may need to slow it to TIMER_CLOCK2 (MCK/8=4.5 MHz) +inline void start_timer0() +{ + register Tc *ptc ; + + // Enable peripheral clock TC0 = bit 23 thru TC5 = bit 28 + PMC->PMC_PCER0 |= 0x00800000L ; // Enable peripheral clock to TC0 + + ptc = TC0 ; // Tc block 0 (TC0-2) + ptc->TC_BCR = 0 ; // No sync + ptc->TC_BMR = 2 ; + ptc->TC_CHANNEL[0].TC_CMR = 0x00008001 ; // Waveform mode MCK/8 for 36MHz osc. + ptc->TC_CHANNEL[0].TC_RC = 0xFFF0 ; + ptc->TC_CHANNEL[0].TC_RA = 0 ; + ptc->TC_CHANNEL[0].TC_CMR = 0x00008040 ; // 0000 0000 0000 0000 1000 0000 0100 0000, stop at regC + ptc->TC_CHANNEL[0].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) +} + +// TIMER2 at 200Hz, provides 5mS for sound and 10mS tick on interrupt +// Starts TIMER2 at 200Hz, commentd out drive of TIOA2 (A26, EXT2) +inline void start_timer2() +{ + register Tc *ptc ; + register uint32_t timer ; + + // Enable peripheral clock TC0 = bit 23 thru TC5 = bit 28 + PMC->PMC_PCER0 |= 0x02000000L ; // Enable peripheral clock to TC2 + + timer = Master_frequency / 12800 / 2; // MCK/128 and 200 Hz + + ptc = TC0 ; // Tc block 0 (TC0-2) + ptc->TC_BCR = 0 ; // No sync + ptc->TC_BMR = 0 ; + ptc->TC_CHANNEL[2].TC_CMR = 0x00008000 ; // Waveform mode + ptc->TC_CHANNEL[2].TC_RC = timer ; // 10 Hz + ptc->TC_CHANNEL[2].TC_RA = timer >> 1 ; + ptc->TC_CHANNEL[2].TC_CMR = 0x0009C003 ; // 0000 0000 0000 1001 1100 0000 0000 0011 + ptc->TC_CHANNEL[2].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) + + NVIC_EnableIRQ(TC2_IRQn) ; + TC0->TC_CHANNEL[2].TC_IER = TC_IER0_CPCS ; +} + +// Start TIMER3 for input capture +inline void start_timer3() +{ + register Tc *ptc ; + + // Enable peripheral clock TC0 = bit 23 thru TC5 = bit 28 + PMC->PMC_PCER0 |= 0x04000000L ; // Enable peripheral clock to TC3 + + ptc = TC1 ; // Tc block 1 (TC3-5) + ptc->TC_BCR = 0 ; // No sync + ptc->TC_BMR = 2 ; + ptc->TC_CHANNEL[0].TC_CMR = 0x00000000 ; // Capture mode + ptc->TC_CHANNEL[0].TC_CMR = 0x00090005 ; // 0000 0000 0000 1001 0000 0000 0000 0101, XC0, A rise, b fall + ptc->TC_CHANNEL[0].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) + + configure_pins( PIO_PC23, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_B | PIN_PORTC | PIN_PULLUP ) ; + + NVIC_SetPriority( TC3_IRQn, 14 ) ; // Low priority interrupt + NVIC_EnableIRQ(TC3_IRQn) ; + ptc->TC_CHANNEL[0].TC_IER = TC_IER0_LDRAS ; +} + +// Start Timer4 to provide 0.5uS clock for input capture +void start_timer4() +{ + register Tc *ptc ; + register uint32_t timer ; + + timer = Master_frequency / (2*2000000) ; // MCK/2 and 2MHz + + // Enable peripheral clock TC0 = bit 23 thru TC5 = bit 28 + PMC->PMC_PCER0 |= 0x08000000L ; // Enable peripheral clock to TC4 + + ptc = TC1 ; // Tc block 1 (TC3-5) + ptc->TC_BCR = 0 ; // No sync + ptc->TC_BMR = 0 ; + ptc->TC_CHANNEL[1].TC_CMR = 0x00008000 ; // Waveform mode + ptc->TC_CHANNEL[1].TC_RC = timer ; + ptc->TC_CHANNEL[1].TC_RA = timer >> 1 ; + ptc->TC_CHANNEL[1].TC_CMR = 0x0009C000 ; // 0000 0000 0000 1001 1100 0000 0100 0000 + // MCK/2, set @ RA, Clear @ RC waveform + ptc->TC_CHANNEL[1].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) +} + +// Timer3 used for PPM_IN pulse width capture. Counter running at 16MHz / 8 = 2MHz +// equating to one count every half millisecond. (2 counts = 1ms). Control channel +// count delta values thus can range from about 1600 to 4400 counts (800us to 2200us), +// corresponding to a PPM signal in the range 0.8ms to 2.2ms (1.5ms at center). +// (The timer is free-running and is thus not reset to zero at each capture interval.) +// Timer 4 generates the 2MHz clock to clock Timer 3 + +extern "C" void TC3_IRQHandler() //capture ppm in at 2MHz +{ + uint16_t capture ; + static uint16_t lastCapt ; + + capture = TC1->TC_CHANNEL[0].TC_RA ; + (void) TC1->TC_CHANNEL[0].TC_SR ; // Acknowledgethe interrupt + + uint16_t val = (capture - lastCapt) / 2; + + // G: We process g_ppmIns immediately here, to make servo movement as smooth as possible + // while under trainee control + if (val>4000 && val < 16000) // G: Prioritize reset pulse. (Needed when less than 8 incoming pulses) + ppmInState = 1; // triggered + else + { + if (ppmInState && ppmInState<=8) + { + if (val>800 && val<2200) // if valid pulse-width range + { + g_ppmIns[ppmInState++ - 1] = + (int16_t)(val - 1500)*(g_eeGeneral.PPM_Multiplier+10)/10; //+-500 != 512, but close enough. + } + else + ppmInState = 0; // not triggered + } + } + + lastCapt = capture; +} + +void start_ppm_capture() +{ + start_timer4() ; + start_timer3() ; +} + +void end_ppm_capture() +{ + TC1->TC_CHANNEL[0].TC_IDR = TC_IDR0_LDRAS ; + NVIC_DisableIRQ(TC3_IRQn) ; +} + +extern "C" void TC2_IRQHandler() +{ + register uint32_t dummy; + static uint32_t pre_scale ; // Used to get 10 Hz counter + + /* Clear status bit to acknowledge interrupt */ + dummy = TC0->TC_CHANNEL[2].TC_SR; + (void) dummy ; // Discard value - prevents compiler warning + + HAPTIC_HEARTBEAT(); + AUDIO_HEARTBEAT(); + + if ( ++pre_scale >= 2 ) { + Tenms |= 1 ; // 10 mS has passed + if ( Buzzer_count ) { + if ( --Buzzer_count == 0 ) + buzzer_off() ; + } + pre_scale = 0 ; + per10ms(); + } +} + +// Settings for mode register ADC_MR +// USEQ off - silicon problem, doesn't work +// TRANSFER = 1 +// TRACKTIM = 4 (5 clock periods) +// ANACH = 0 +// SETTLING = 1 (not used if ANACH = 0) +// STARTUP = 1 (8 clock periods) +// PRESCAL = 3.6 MHz clock (between 1 and 20MHz) +// FREERUN = 0 +// FWUP = 0 +// SLEEP = 0 +// LOWRES = 0 +// TRGSEL = 0 +// TRGEN = 0 (software trigger only) +inline void init_adc() +{ + register Adc *padc ; + register uint32_t timer ; + + timer = ( Master_frequency / (3600000*2) ) << 8 ; + // Enable peripheral clock ADC = bit 29 + PMC->PMC_PCER0 |= 0x20000000L ; // Enable peripheral clock to ADC + padc = ADC ; + padc->ADC_MR = 0x14110000 | timer ; // 0001 0100 0001 0001 xxxx xxxx 0000 0000 + padc->ADC_ACR = ADC_ACR_TSON ; // Turn on temp sensor +#if defined(REVA) + padc->ADC_CHER = 0x0000E23E ; // channels 1,2,3,4,5,9,13,14,15 +#else + padc->ADC_CHER = 0x0000E33E ; // channels 1,2,3,4,5,8,9,13,14,15 +#endif + padc->ADC_CGR = 0 ; // Gain = 1, all channels + padc->ADC_COR = 0 ; // Single ended, 0 offset, all channels +} + +// PWM used for PPM generation, and LED Backlight +// Output pin PB5 not used, PA17 used as PWMH3 peripheral C +// PWM peripheral ID = 31 (0x80000000) +// Ensure PB5 is three state/input, used on REVB for MENU KEY + +// Configure PWM3 as PPM drive, +// PWM0 is LED backlight PWM on PWMH0 +// This is PC18 peripheral B, Also enable PC22 peripheral B, this is PPM-JACK (PWML3) +// +// REVB board: +// PWML2, output as peripheral C on PA16, is for HAPTIC +// For testing, just drive it out with PWM +// PWML1 for PPM2 output as peripheral B on PC15 +// For testing, just drive it out with PWM +void init_pwm() +{ + register Pwm *pwmptr ; + register uint32_t timer ; + + PMC->PMC_PCER0 |= ( 1 << ID_PWM ) ; // Enable peripheral clock to PWM + + MATRIX->CCFG_SYSIO |= 0x00000020L ; // Disable TDO let PB5 work! + + /* Configure PIO */ +#if defined(REVA) + register Pio *pioptr = PIOB ; + pioptr->PIO_PER = 0x00000020L ; // Enable bit B5 + pioptr->PIO_ODR = 0x00000020L ; // set as input +#else + configure_pins( PIO_PA16, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_C | PIN_PORTA | PIN_NO_PULLUP ) ; +#endif + + configure_pins( PIO_PC18, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_B | PIN_PORTC | PIN_NO_PULLUP ) ; + +#if !defined(REVA) + configure_pins( PIO_PC15, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_B | PIN_PORTC | PIN_NO_PULLUP ) ; + configure_pins( PIO_PC22, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_B | PIN_PORTC | PIN_NO_PULLUP ) ; +#endif + + // Configure clock - depends on MCK frequency + timer = Master_frequency / 2000000 ; + timer |= ( Master_frequency / ( 32* 10000 ) ) << 16 ; + timer &= 0x00FF00FF ; + + pwmptr = PWM ; + pwmptr->PWM_CLK = 0x05000000 | timer ; // MCK for DIVA, DIVA = 18 gives 0.5uS clock period @35MHz // MCK/32 / timer = 10000Hz for CLKB + + // PWM0 for LED backlight + pwmptr->PWM_CH_NUM[0].PWM_CMR = 0x0000000C ; // CLKB + pwmptr->PWM_CH_NUM[0].PWM_CPDR = 100 ; // Period + pwmptr->PWM_CH_NUM[0].PWM_CPDRUPD = 100 ; // Period + pwmptr->PWM_CH_NUM[0].PWM_CDTY = 40 ; // Duty + pwmptr->PWM_CH_NUM[0].PWM_CDTYUPD = 40 ; // Duty + pwmptr->PWM_ENA = PWM_ENA_CHID0 ; // Enable channel 0 + +#if !defined(REVA) + // PWM1 for PPM2 output 100Hz test + pwmptr->PWM_CH_NUM[1].PWM_CMR = 0x0000000C ; // CLKB + pwmptr->PWM_CH_NUM[1].PWM_CPDR = 100 ; // Period + pwmptr->PWM_CH_NUM[1].PWM_CPDRUPD = 100 ; // Period + pwmptr->PWM_CH_NUM[1].PWM_CDTY = 40 ; // Duty + pwmptr->PWM_CH_NUM[1].PWM_CDTYUPD = 40 ; // Duty + pwmptr->PWM_ENA = PWM_ENA_CHID1 ; // Enable channel 1 +#endif + +#if !defined(REVA) + // PWM2 for HAPTIC drive 100Hz test + pwmptr->PWM_CH_NUM[2].PWM_CMR = 0x0000000C ; // CLKB + pwmptr->PWM_CH_NUM[2].PWM_CPDR = 100 ; // Period + pwmptr->PWM_CH_NUM[2].PWM_CPDRUPD = 100 ; // Period + pwmptr->PWM_CH_NUM[2].PWM_CDTY = 40 ; // Duty + pwmptr->PWM_CH_NUM[2].PWM_CDTYUPD = 40 ; // Duty + pwmptr->PWM_OOV &= ~0x00040000 ; // Force low + pwmptr->PWM_OSS = 0x00040000 ; // Force low + // pwmptr->PWM_ENA = PWM_ENA_CHID2 ; // Enable channel 2 // TODO on REVA? +#endif +} + +// LCD i/o pins +// LCD_RES PC27 +// LCD_CS1 PC26 +// LCD_E PC12 +// LCD_RnW PC13 +// LCD_A0 PC15 +// LCD_D0 PC0 +// LCD_D1 PC7 +// LCD_D2 PC6 +// LCD_D3 PC5 +// LCD_D4 PC4 +// LCD_D5 PC3 +// LCD_D6 PC2 +// LCD_D7 PC1 + +#define LCD_DATA 0x000000FFL +#if defined(REVA) +#define LCD_A0 0x00008000L +#else +#define LCD_A0 0x00000080L +#endif +#define LCD_RnW 0x00002000L +#define LCD_E 0x00001000L +#define LCD_CS1 0x04000000L +#define LCD_RES 0x08000000L + +void configure_pins( uint32_t pins, uint16_t config ) +{ + register Pio *pioptr ; + + pioptr = PIOA + ( ( config & PIN_PORT_MASK ) >> 6) ; + if ( config & PIN_PULLUP ) + { + pioptr->PIO_PPDDR = pins ; + pioptr->PIO_PUER = pins ; + } + else + { + pioptr->PIO_PUDR = pins ; + } + + if ( config & PIN_PULLDOWN ) + { + pioptr->PIO_PUDR = pins ; + pioptr->PIO_PPDER = pins ; + } + else + { + pioptr->PIO_PPDDR = pins ; + } + + if ( config & PIN_HIGH ) + { + pioptr->PIO_SODR = pins ; + } + else + { + pioptr->PIO_CODR = pins ; + } + + if ( config & PIN_INPUT ) + { + pioptr->PIO_ODR = pins ; + } + else + { + pioptr->PIO_OER = pins ; + } + + if ( config & PIN_PERI_MASK_L ) + { + pioptr->PIO_ABCDSR[0] |= pins ; + } + else + { + pioptr->PIO_ABCDSR[0] &= ~pins ; + } + if ( config & PIN_PERI_MASK_H ) + { + pioptr->PIO_ABCDSR[1] |= pins ; + } + else + { + pioptr->PIO_ABCDSR[1] &= ~pins ; + } + + if ( config & PIN_ENABLE ) + { + pioptr->PIO_PER = pins ; + } + else + { + pioptr->PIO_PDR = pins ; + } +} + +void board_init() +{ + // register uint32_t goto_usb ; + register Pio *pioptr ; + // Debug variable + // uint32_t both_on ; + + MATRIX->CCFG_SYSIO |= 0x000000F0L ; // Disable syspins, enable B4,5,6,7 + + PMC->PMC_PCER0 = (1<PIO_PER = PIO_PA21 ; // Enable bit A21 (EXT3) + pioptr->PIO_OER = PIO_PA21 ; // Set bit A21 as output + pioptr->PIO_SODR = PIO_PA21 ; // Set bit A21 ON +#else + init_soft_power() ; +#endif + + // pioptr->PIO_PUER = 0x80000000 ; // Enable pullup on bit A31 (EXIT) + // pioptr->PIO_PER = 0x80000000 ; // Enable bit A31 + + pioptr = PIOC ; + pioptr->PIO_PER = PIO_PC25 ; // Enable bit C25 (USB-detect) + // pioptr->PIO_OER = 0x80000000L ; // Set bit C31 as output + // pioptr->PIO_SODR = 0x80000000L ; // Set bit C31 + +#if defined(REVA) + // Configure RF_power (PC17) and PPM-jack-in (PC19), neither need pullups + pioptr->PIO_PER = 0x000A0000L ; // Enable bit C19, C17 + pioptr->PIO_ODR = 0x000A0000L ; // Set bits C19 and C17 as input +#endif + + config_free_pins() ; + + // Next section configures the key inputs on the LCD data +#if defined(REVA) + pioptr->PIO_PER = 0x0000003DL ; // Enable bits 2,3,4,5, 0 + pioptr->PIO_OER = PIO_PC0 ; // Set bit 0 output + pioptr->PIO_ODR = 0x0000003CL ; // Set bits 2, 3, 4, 5 input + pioptr->PIO_PUER = 0x0000003CL ; // Set bits 2, 3, 4, 5 with pullups +#else + pioptr->PIO_PER = 0x0000003BL ; // Enable bits 1,3,4,5, 0 + pioptr->PIO_OER = PIO_PC0 ; // Set bit 0 output + pioptr->PIO_ODR = 0x0000003AL ; // Set bits 1, 3, 4, 5 input + pioptr->PIO_PUER = 0x0000003AL ; // Set bits 1, 3, 4, 5 with pullups +#endif + + pioptr = PIOB ; +#if defined(REVA) + pioptr->PIO_PUER = PIO_PB6 ; // Enable pullup on bit B6 (MENU) + pioptr->PIO_PER = PIO_PB6 ; // Enable bit B6 +#else + pioptr->PIO_PUER = PIO_PB5 ; // Enable pullup on bit B5 (MENU) + pioptr->PIO_PER = PIO_PB5 ; // Enable bit B5 +#endif + + setup_switches() ; + + // Enable PCK2 on PB3, This is for testing of Timer 2 working + // It will be used as serial data to the Bluetooth module + pioptr->PIO_ABCDSR[0] |= PIO_PB3 ; // Peripheral B + pioptr->PIO_ABCDSR[1] &= ~PIO_PB3 ; // Peripheral B + pioptr->PIO_PDR = PIO_PB3 ; // Assign to peripheral + PMC->PMC_SCER |= 0x0400 ; // PCK2 enabled + PMC->PMC_PCK[2] = 2 ; // PCK2 is PLLA + + DEBUG_UART_Configure( 9600, Master_frequency ) ; + UART2_Configure( 9600, Master_frequency ) ; // Testing + UART3_Configure( 9600, Master_frequency ) ; // TODO not needed, done after ... + + start_timer2() ; + start_timer0() ; + init_adc() ; + init_pwm() ; + + __enable_irq() ; + + startSound() ; + + codecsInit(); + + eeprom_init(); + + init_SDcard(); + +} +#endif + +// keys: +// KEY_EXIT PA31 (PC24) +// KEY_MENU PB6 (PB5) +// KEY_DOWN LCD5 PC3 (PC5) +// KEY_UP LCD6 PC2 (PC1) +// KEY_RIGHT LCD4 PC4 (PC4) +// KEY_LEFT LCD3 PC5 (PC3) +// Reqd. bit 6 LEFT, 5 RIGHT, 4 UP, 3 DOWN 2 EXIT 1 MENU +// LCD pins 5 DOWN, 4 RIGHT, 3 LEFT, 1 UP +uint32_t read_keys() +{ + register uint32_t x; + register uint32_t y; + + x = PIOC->PIO_PDSR; // 6 LEFT, 5 RIGHT, 4 DOWN, 3 UP () + x <<= 1; + + y = 0; + if (x & 0x00000020) + y |= 0x02 << KEY_PLUS; + if (x & 0x00000004) + y |= 0x02 << KEY_MENU; + if (x & 0x00000010) + y |= 0x02 << KEY_MINUS; + if (x & 0x00000040) + y |= 0x02 << KEY_PAGE; + if (x & 0x02000000) + y |= 0x02 << KEY_EXIT; + if (PIOB->PIO_PDSR & 0x000000020) + y |= 0x02 << KEY_ENTER; + + return y ; +} + +uint32_t read_trims() +{ + uint32_t trims; + uint32_t trima; + + trims = 0; + + trima = PIOA->PIO_PDSR; + +// TRIM_LH_DOWN PA7 (PA23) +#if defined(REVA) + if ( ( trima & 0x0080 ) == 0 ) +#else + if ((trima & 0x00800000) == 0) +#endif + { + trims |= 1; + } + +// TRIM_LV_DOWN PA27 (PA24) +#if defined(REVA) + if ( ( trima & 0x08000000 ) == 0 ) +#else + if ((trima & 0x01000000) == 0) +#endif + { + trims |= 4; + } + +// TRIM_RV_UP PA30 (PA1) +#if defined(REVA) + if ( ( trima & 0x40000000 ) == 0 ) +#else + if ((trima & 0x00000002) == 0) +#endif + { + trims |= 0x20; + } + +// TRIM_RH_DOWN PA29 (PA0) +#if defined(REVA) + if ( ( trima & 0x20000000 ) == 0 ) +#else + if ((trima & 0x00000001) == 0) +#endif + { + trims |= 0x40; + } + +// TRIM_LH_UP PB4 + if ((PIOB->PIO_PDSR & 0x10) == 0) { + trims |= 2; + } + + trima = PIOC->PIO_PDSR; +// TRIM_LV_UP PC28 + if ((trima & 0x10000000) == 0) { + trims |= 8; + } + +// TRIM_RV_DOWN PC10 + if ((trima & 0x00000400) == 0) { + trims |= 0x10; + } + +// TRIM_RH_UP PC9 + if ((trima & 0x00000200) == 0) { + trims |= 0x80; + } + + return trims; +} + +uint8_t keyDown() +{ + return ~read_keys() & 0x7E ; +} + +extern uint32_t keyState(EnumKeys enuk) +{ + register uint32_t c ; + + CPU_UINT xxx = 0; + + if (enuk < (int) DIM(keys)) return keys[enuk].state() ? 1 : 0; + + c = PIOC->PIO_PDSR ; + + // printf("c=%x\n", c); fflush(stdout); + + switch ((uint8_t) enuk) { + case SW_SA0: + xxx = !(c & 0x80000000); + break; + + case SW_SA2: + xxx = c & 0x80000000; + break; + + case SW_SB0: + xxx = !(c & 0x08000000) && !(c & 0x04000000); + break; + + case SW_SB1: + xxx = (c & 0x08000000) && !(c & 0x04000000); + break; + + case SW_SB2: + xxx = !(c & 0x08000000) && (c & 0x04000000); + break; + + case SW_SC0: + xxx = !(c & 0x00800000) && !(c & 0x00400000); + break; + + case SW_SC1: + xxx = (c & 0x00800000) && !(c & 0x00400000); + break; + + case SW_SC2: + xxx = !(c & 0x00800000) && (c & 0x00400000); + break; + + case SW_SD0: + xxx = !(c & 0x00200000) && !(c & 0x00100000); + break; + + case SW_SD1: + xxx = (c & 0x00200000) && !(c & 0x00100000); + break; + + case SW_SD2: + xxx = !(c & 0x00200000) && (c & 0x00100000); + break; + + case SW_SE0: + xxx = !(c & 0x00080000) && !(c & 0x00040000); + break; + + case SW_SE1: + xxx = (c & 0x00080000) && !(c & 0x00040000); + break; + + case SW_SE2: + xxx = !(c & 0x00080000) && (c & 0x00040000); + break; + + case SW_SF0: + xxx = !(c & 0x00020000) && !(c & 0x00010000); + break; + + case SW_SF1: + xxx = (c & 0x00020000) && !(c & 0x00010000); + break; + + case SW_SF2: + xxx = !(c & 0x00020000) && (c & 0x00010000); + break; + + case SW_SG0: + xxx = !(c & 0x00008000) && !(c & 0x00004000); + break; + + case SW_SG1: + xxx = (c & 0x00008000) && !(c & 0x00004000); + break; + + case SW_SG2: + xxx = !(c & 0x00008000) && (c & 0x00004000); + break; + + case SW_SH0: + xxx = !(c & 0x00002000); + break; + + case SW_SH2: + xxx = c & 0x00002000; + break; + + default: + break; + } + + if (xxx) { + return 1; + } + return 0; +} + +uint16_t Analog_values[NUMBER_ANALOG] ; +uint8_t temperature = 0; // Raw temp reading +uint8_t maxTemperature = 0 ; // Raw temp reading + +// Read 8 (9 for REVB) ADC channels +// Documented bug, must do them 1 by 1 +void read_9_adc() +{ + register Adc *padc; + register uint32_t y; + register uint32_t x; + + padc = ADC; + y = padc->ADC_ISR; // Clear EOC flags + for (y = NUMBER_ANALOG+1; --y > 0;) { + padc->ADC_CR = 2; // Start conversion + x = 0; + while ((padc->ADC_ISR & 0x01000000) == 0) { + // wait for DRDY flag + if (++x > 1000000) { + break; // Software timeout + } + } + x = padc->ADC_LCDR; // Clear DRSY flag + } + // Next bit may be done using the PDC + Analog_values[0] = ADC->ADC_CDR1; + Analog_values[1] = ADC->ADC_CDR2; + Analog_values[2] = ADC->ADC_CDR3; + Analog_values[3] = ADC->ADC_CDR4; + Analog_values[4] = ADC->ADC_CDR5; + Analog_values[5] = ADC->ADC_CDR9; + Analog_values[6] = ADC->ADC_CDR13; + Analog_values[7] = ADC->ADC_CDR14; + +#if defined(REVA) + Analog_values[8] = ADC->ADC_CDR8 ; +#endif + + temperature = (((int32_t)temperature * 7) + ((((int32_t)ADC->ADC_CDR15 - 838) * 621) >> 11)) >> 3; // Filter it + if (get_tmr10ms() >= 100 && temperature > maxTemperature) { + maxTemperature = temperature; + } +} + +void readKeysAndTrims() +{ + register uint32_t i; + +#if defined(ROTARY_ENCODERS) + keys[BTN_REa].input(!(PIOB->PIO_PDSR & 0x40), BTN_REa); +#endif + + uint8_t enuk = KEY_MENU; + uint8_t in = ~read_keys(); + for (i = 1; i < 7; i++) { + keys[enuk].input(in & (1 << i), (EnumKeys) enuk); + ++enuk; + } + + in = read_trims(); + + for (i = 1; i < 256; i <<= 1) { + keys[enuk].input(in & i, (EnumKeys) enuk); + ++enuk; + } +} + +#define RX_UART_BUFFER_SIZE 32 + +struct t_rxUartBuffer +{ + uint8_t fifo[RX_UART_BUFFER_SIZE] ; + uint8_t *outPtr ; +} ; + +struct t_rxUartBuffer TelemetryInBuffer[2] ; +uint32_t TelemetryActiveBuffer ; + +void startPdcUsartReceive() +{ + register Usart *pUsart = SECOND_USART; + + TelemetryInBuffer[0].outPtr = TelemetryInBuffer[0].fifo ; + TelemetryInBuffer[1].outPtr = TelemetryInBuffer[1].fifo ; +#ifndef SIMU + // TODO because of the 64bits cast ... + pUsart->US_RPR = (uint32_t)TelemetryInBuffer[0].fifo ; + pUsart->US_RNPR = (uint32_t)TelemetryInBuffer[1].fifo ; +#endif + pUsart->US_RCR = RX_UART_BUFFER_SIZE ; + pUsart->US_RNCR = RX_UART_BUFFER_SIZE ; + pUsart->US_PTCR = US_PTCR_RXTEN ; + TelemetryActiveBuffer = 0 ; +} + +void endPdcUsartReceive() +{ + register Usart *pUsart = SECOND_USART; + + pUsart->US_PTCR = US_PTCR_RXTDIS ; +} + +void rxPdcUsart( void (*pChProcess)(uint8_t x) ) +{ +#if !defined(SIMU) + register Usart *pUsart = SECOND_USART; + uint8_t *ptr ; + uint8_t *endPtr ; +// uint32_t bufIndex ; +// uint32_t i ; + uint32_t j ; + + //Find out where the DMA has got to + __disable_irq() ; + pUsart->US_PTCR = US_PTCR_RXTDIS ; // Freeze DMA + ptr = (uint8_t *)pUsart->US_RPR ; + j = pUsart->US_RNCR ; + pUsart->US_PTCR = US_PTCR_RXTEN ; // DMA active again + __enable_irq() ; + + endPtr = ptr - 1 ; + ptr = TelemetryInBuffer[TelemetryActiveBuffer].outPtr ; + if ( j == 0 ) // First buf is full + { + endPtr = &TelemetryInBuffer[TelemetryActiveBuffer].fifo[RX_UART_BUFFER_SIZE-1] ; // last byte + } + while ( ptr <= endPtr ) + { + (*pChProcess)(*ptr++) ; + } + TelemetryInBuffer[TelemetryActiveBuffer].outPtr = ptr ; + if ( j == 0 ) // First buf is full + { + TelemetryInBuffer[TelemetryActiveBuffer].outPtr = TelemetryInBuffer[TelemetryActiveBuffer].fifo ; + pUsart->US_RNPR = (uint32_t)TelemetryInBuffer[TelemetryActiveBuffer].fifo ; + pUsart->US_RNCR = RX_UART_BUFFER_SIZE ; + TelemetryActiveBuffer ^= 1 ; // Other buffer is active + rxPdcUsart( pChProcess ) ; // Get any chars from second buffer + } +#endif +} + +uint32_t txPdcUsart( uint8_t *buffer, uint32_t size ) +{ + register Usart *pUsart = SECOND_USART; + + if ( pUsart->US_TNCR == 0 ) + { +#ifndef SIMU + pUsart->US_TNPR = (uint32_t)buffer ; +#endif + pUsart->US_TNCR = size ; + pUsart->US_PTCR = US_PTCR_TXTEN ; + return 1 ; + } + return 0 ; +} + +uint32_t txPdcPending() +{ + register Usart *pUsart = SECOND_USART; + uint32_t x ; + + __disable_irq() ; + pUsart->US_PTCR = US_PTCR_TXTDIS ; // Freeze DMA + x = pUsart->US_TNCR ; // Total + x += pUsart->US_TCR ; // Still to send + pUsart->US_PTCR = US_PTCR_TXTEN ; // DMA active again + __enable_irq() ; + + return x ; +} + +void end_bt_tx_interrupt() +{ + Uart *pUart = BT_USART ; + pUart->UART_IDR = UART_IDR_TXBUFE ; + NVIC_DisableIRQ(UART1_IRQn) ; +} + +void usbBootloader() +{ + // This might be replaced by a software reset + // Any interrupts that have been enabled must be disabled here + // BEFORE calling sam_boot() + endPdcUsartReceive() ; // Terminate any serial reception + end_bt_tx_interrupt() ; + end_ppm_capture() ; + end_spi() ; + end_sound() ; + + TC0->TC_CHANNEL[2].TC_IDR = TC_IDR0_CPCS ; + TC0->TC_CHANNEL[0].TC_CCR = TC_CCR0_CLKDIS ; + TC0->TC_CHANNEL[1].TC_CCR = TC_CCR0_CLKDIS ; + TC0->TC_CHANNEL[2].TC_CCR = TC_CCR0_CLKDIS ; + TC1->TC_CHANNEL[0].TC_CCR = TC_CCR0_CLKDIS ; + TC1->TC_CHANNEL[1].TC_CCR = TC_CCR0_CLKDIS ; + TC1->TC_CHANNEL[2].TC_CCR = TC_CCR0_CLKDIS ; + PWM->PWM_DIS = PWM_DIS_CHID0 | PWM_DIS_CHID1 | PWM_DIS_CHID2 | PWM_DIS_CHID3 ; // Disable all + NVIC_DisableIRQ(TC2_IRQn) ; + + disable_main_ppm() ; + // PWM->PWM_IDR1 = PWM_IDR1_CHID3 ; + // NVIC_DisableIRQ(PWM_IRQn) ; + disable_ssc() ; + + DEBUG_UART_Stop(); + UART3_Stop(); + + sam_boot() ; +} + +#if !defined(REVA) +uint16_t getCurrent() +{ + static uint16_t Current ; + static uint32_t Current_sum ; + static uint8_t Current_count ; + + Current_sum += anaIn(NUMBER_ANALOG-1); + if (++Current_count >= 50) { + Current = Current_sum / 5 ; + Current_sum = 0 ; + Current_count = 0 ; + } + + uint32_t current_scale = 488 + g_eeGeneral.currentCalib ; + return (current_scale * Current) / 8192; +} +#endif + +uint8_t getTemperature() +{ + return temperature + g_eeGeneral.temperatureCalib; +} + diff --git a/src/board_x9d.h b/src/board_x9d.h new file mode 100644 index 000000000..9e7196249 --- /dev/null +++ b/src/board_x9d.h @@ -0,0 +1,112 @@ +/* + * Authors (alphabetical order) + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef board_sky9x_h +#define board_sky9x_h + +#include +#include "sky9x/board.h" +#include "sky9x/sound_driver.h" +#include "sky9x/haptic_driver.h" +#include "sky9x/debug.h" + +#if defined(BLUETOOTH) +#include "sky9x/bluetooth.h" +#endif + +extern "C" { +extern void init_SDcard(); +extern void sdInit(); +} + +#define sdPoll10ms() + +void usbMassStorage(); + +#define PIN_ENABLE 0x001 +#define PIN_PERIPHERAL 0x000 +#define PIN_INPUT 0x002 +#define PIN_OUTPUT 0x000 +#define PIN_PULLUP 0x004 +#define PIN_NO_PULLUP 0x000 +#define PIN_PULLDOWN 0x008 +#define PIN_NO_PULLDOWN 0x000 +#define PIN_PERI_MASK_L 0x010 +#define PIN_PERI_MASK_H 0x020 +#define PIN_PER_A 0x000 +#define PIN_PER_B 0x010 +#define PIN_PER_C 0x020 +#define PIN_PER_D 0x030 +#define PIN_PORT_MASK 0x0C0 +#define PIN_PORTA 0x000 +#define PIN_PORTB 0x040 +#define PIN_PORTC 0x080 +#define PIN_LOW 0x000 +#define PIN_HIGH 0x100 + +void configure_pins( uint32_t pins, uint16_t config ); +uint16_t getCurrent(); + +extern uint8_t temperature ; // Raw temp reading +extern uint8_t maxTemperature ; // Raw temp reading +uint8_t getTemperature(); + +#define strcpy_P strcpy +#define strcat_P strcat + +extern uint32_t read_keys(); +#define KEYS_PRESSED() (~read_keys()) +#define DBLKEYS_PRESSED_RGT_LFT(i) ((in & (0x20 + 0x40)) == (0x20 + 0x40)) +#define DBLKEYS_PRESSED_UP_DWN(i) ((in & (0x10 + 0x08)) == (0x10 + 0x08)) +#define DBLKEYS_PRESSED_RGT_UP(i) ((in & (0x20 + 0x10)) == (0x20 + 0x10)) +#define DBLKEYS_PRESSED_LFT_DWN(i) ((in & (0x40 + 0x08)) == (0x40 + 0x08)) + +#if !defined(REVA) +extern uint16_t Current_analogue; +extern uint16_t Current_max; +extern uint32_t Current_accumulator; +extern uint32_t Current_used; +extern uint16_t sessionTimer; +#endif + +#if defined(REVC) +#define BOOTLOADER_REQUEST() (usbPlugged()) +#else +#define BOOTLOADER_REQUEST() (check_soft_power() == e_power_usb) +#endif + +#define SLAVE_MODE() (check_soft_power() == e_power_trainer) +#define JACK_PPM_OUT() PIOC->PIO_PDR = PIO_PC22 +#define JACK_PPM_IN() PIOC->PIO_PER = PIO_PC22 + +#endif diff --git a/src/eeprom_avr.cpp b/src/eeprom_avr.cpp index aebb067b7..f4f5d0f63 100644 --- a/src/eeprom_avr.cpp +++ b/src/eeprom_avr.cpp @@ -77,7 +77,7 @@ ISR(EE_READY_vect) eeprom_write_byte(); } else { -#if defined (PCBGRUVIN9X) +#if defined(PCBGRUVIN9X) EECR &= ~(1<= 3600 && (~att & DBLSIZE)) { qr = div(qr.quot, 60); @@ -715,7 +715,7 @@ void putsSwitches(xcoord_t x, uint8_t y, int8_t idx, LcdFlags att) if (idx > MAX_SWITCH) { idx -= ((att & SWONOFF) ? MAX_SWITCH+1 : MAX_SWITCH); char suffix = 'm'; -#if defined(PCBSKY9X) +#if defined(CPUARM) if (idx > MAX_SWITCH+1) { suffix = 's'; idx -= MAX_SWITCH+1; diff --git a/src/main_views.cpp b/src/main_views.cpp index c356aa2dc..6c1cae4ae 100644 --- a/src/main_views.cpp +++ b/src/main_views.cpp @@ -213,7 +213,7 @@ void displayTimers() #endif -#if defined(PCBSKY9X) +#if defined(CPUARM) void displayVoltage() { if (g_vbat100mV > g_eeGeneral.vBatWarn && g_eeGeneral.temperatureWarn && getTemperature() >= g_eeGeneral.temperatureWarn) { diff --git a/src/model_menus.cpp b/src/model_menus.cpp index fa949524e..f5ecc4411 100644 --- a/src/model_menus.cpp +++ b/src/model_menus.cpp @@ -120,7 +120,7 @@ bool listSdFiles(const char *path, const char *extension, const uint8_t maxlen, static uint16_t s_last_menu_offset = 0; -#if defined(PCBSKY9X) +#if defined(CPUARM) if (selection) { memset(reusableBuffer.models.menu_bss, 0, sizeof(reusableBuffer.models.menu_bss)); strcpy(reusableBuffer.models.menu_bss[0], path); @@ -216,7 +216,7 @@ void menuModelSelect(uint8_t event) { TITLE(STR_MENUMODELSEL); -#if defined(PCBSKY9X) +#if defined(CPUARM) #define REFRESH(x) #elif defined(PCBGRUVIN9X) && defined(SDCARD) static bool refresh = true; @@ -254,7 +254,7 @@ void menuModelSelect(uint8_t event) #endif if (s_editMode > 0) s_editMode = 0; -#if !defined(PCBSKY9X) +#if !defined(CPUARM) if (event #if defined(ROTARY_ENCODERS) || oldSub != m_posVert @@ -430,7 +430,7 @@ void menuModelSelect(uint8_t event) } -#if !defined(PCBSKY9X) +#if !defined(CPUARM) lcd_puts(9*FW-(LEN_FREE-4)*FW, 0, STR_FREE); if (refresh) reusableBuffer.models.eepromfree = EeFsGetFree(); lcd_outdezAtt(17*FW, 0, reusableBuffer.models.eepromfree, 0); @@ -469,7 +469,7 @@ void menuModelSelect(uint8_t event) k %= MAX_MODELS; if (eeModelExists(k)) { -#if defined(PCBSKY9X) +#if defined(CPUARM) putsModelName(4*FW, y, ModelNames[k], k, 0); #else uint16_t & size = reusableBuffer.models.listsizes[i]; @@ -488,7 +488,7 @@ void menuModelSelect(uint8_t event) } if (s_warning) { -#if defined(PCBSKY9X) +#if defined(CPUARM) s_warning_info = ModelNames[sub]; #else char * name = reusableBuffer.models.mainname; @@ -621,7 +621,7 @@ enum menuModelSetupItems { ITEM_MODEL_PROTOCOL_PARAMS }; -#if defined(PCBSKY9X) || defined(PCBGRUVIN9X) +#if defined(CPUARM) || defined(PCBGRUVIN9X) #define FIELD_TIMER_MAX 3 #else #define FIELD_TIMER_MAX 2 @@ -665,7 +665,7 @@ void menuModelSetup(uint8_t event) switch(k) { case ITEM_MODEL_NAME: editName(MODEL_SETUP_2ND_COLUMN, y, g_model.name, sizeof(g_model.name), event, attr, m_posHorz); -#if defined(PCBSKY9X) +#if defined(CPUARM) memcpy(ModelNames[g_eeGeneral.currModel], g_model.name, sizeof(g_model.name)); #endif break; @@ -698,7 +698,7 @@ void menuModelSetup(uint8_t event) putsTime(MODEL_SETUP_2ND_COLUMN+5*FW-2, y, timer->start, (attr && m_posHorz==1 ? blink:0), (attr && m_posHorz==2 ? blink:0) ); -#if defined(PCBSKY9X) || defined(PCBGRUVIN9X) +#if defined(CPUARM) || defined(PCBGRUVIN9X) lcd_putcAtt(MODEL_SETUP_2ND_COLUMN+10*FW-1, y, g_model.timers[k-ITEM_MODEL_TIMER1].remanent ? 'R' : '-', (attr && m_posHorz==3) ? blink : 0); #endif if (attr && (editMode>0 || p1valdiff)) { @@ -716,7 +716,7 @@ void menuModelSetup(uint8_t event) timer->start -= qr.rem ; if ((int16_t)timer->start < 0) timer->start=0; break; -#if defined(PCBSKY9X) || defined(PCBGRUVIN9X) +#if defined(CPUARM) || defined(PCBGRUVIN9X) case 3: CHECK_INCDEC_MODELVAR(event, g_model.timers[k-ITEM_MODEL_TIMER1].remanent, 0, 1); break; @@ -953,7 +953,7 @@ uint8_t editDelay(const uint8_t y, const uint8_t event, const uint8_t attr, cons #if defined(FLIGHT_PHASES) -#if defined(PCBSKY9X) +#if defined(CPUARM) #define PhasesType uint16_t #else #define PhasesType uint8_t @@ -965,12 +965,12 @@ PhasesType editPhases(uint8_t x, uint8_t y, uint8_t event, PhasesType value, uin uint8_t posHorz = m_posHorz; -#if defined(PCBSKY9X) && !defined(LCD212) +#if defined(CPUARM) && !defined(LCD212) bool expoMenu = (x==EXPO_ONE_2ND_COLUMN-2*FW); #endif for (uint8_t p=0; p EXPO_ONE_2ND_COLUMN+2*FW))) continue; #endif @@ -1189,7 +1189,7 @@ void menuModelPhasesAll(uint8_t event) uint8_t att; for (uint8_t i=0; i7*FH) continue; #else @@ -1246,7 +1246,7 @@ void menuModelPhasesAll(uint8_t event) #endif } -#if defined(PCBSKY9X) +#if defined(CPUARM) if (s_pgOfs != MAX_PHASES-6) return; #endif @@ -1700,7 +1700,7 @@ bool swapExpoMix(uint8_t expo, uint8_t &idx, uint8_t up) } enum ExposFields { - IF_PCBSKY9X(EXPO_FIELD_NAME) + IF_CPUARM(EXPO_FIELD_NAME) EXPO_FIELD_WIDTH, EXPO_FIELD_EXPO, IF_CURVES(EXPO_FIELD_CURVE) @@ -1715,7 +1715,7 @@ void menuModelExpoOne(uint8_t event) ExpoData *ed = expoaddress(s_currIdx); putsChnRaw(7*FW+FW/2,0,ed->chn+1,0); - SUBMENU(STR_MENUDREXPO, EXPO_FIELD_MAX, {IF_PCBSKY9X(ZCHAR|(sizeof(ed->name)-1)) 0, 0, IF_CURVES(1) IF_FLIGHT_PHASES(MAX_PHASES-1) 0 /*, ...*/}); + SUBMENU(STR_MENUDREXPO, EXPO_FIELD_MAX, {IF_CPUARM(ZCHAR|(sizeof(ed->name)-1)) 0, 0, IF_CURVES(1) IF_FLIGHT_PHASES(MAX_PHASES-1) 0 /*, ...*/}); int8_t sub = m_posVert; @@ -1725,7 +1725,7 @@ void menuModelExpoOne(uint8_t event) uint8_t attr = (sub==i ? (s_editMode>0 ? BLINK|INVERS : INVERS) : 0); switch(i) { -#if defined(PCBSKY9X) +#if defined(CPUARM) case EXPO_FIELD_NAME: editName(EXPO_ONE_2ND_COLUMN+3*FW-sizeof(ed->name)*FW, y, ed->name, sizeof(ed->name), event, attr, m_posHorz); break; @@ -1794,7 +1794,7 @@ void menuModelExpoOne(uint8_t event) } enum MixFields { - IF_PCBSKY9X(MIX_FIELD_NAME) + IF_CPUARM(MIX_FIELD_NAME) MIX_FIELD_SOURCE, MIX_FIELD_WEIGHT, MIX_FIELD_OFFSET, @@ -1827,11 +1827,11 @@ void menuModelMixOne(uint8_t event) #if defined(ROTARY_ENCODERS) if ((m_posVert == MIX_FIELD_TRIM && md2->srcRaw > NUM_STICKS) || (m_posVert == MIX_FIELD_CURVE && md2->curveMode == MODE_CURVE)) - SUBMENU_NOTITLE(MIX_FIELD_COUNT, {IF_PCBSKY9X(ZCHAR|(sizeof(md2->name)-1)) 0, 0, 0, 0, IF_CURVES(0) 0, IF_FLIGHT_PHASES(MAX_PHASES-1) 0 /*, ...*/}) + SUBMENU_NOTITLE(MIX_FIELD_COUNT, {IF_CPUARM(ZCHAR|(sizeof(md2->name)-1)) 0, 0, 0, 0, IF_CURVES(0) 0, IF_FLIGHT_PHASES(MAX_PHASES-1) 0 /*, ...*/}) else - SUBMENU_NOTITLE(MIX_FIELD_COUNT, {IF_PCBSKY9X(ZCHAR|(sizeof(md2->name)-1)) 0, 0, 0, 1, IF_CURVES(1) 0, IF_FLIGHT_PHASES(MAX_PHASES-1) 0 /*, ...*/}); + SUBMENU_NOTITLE(MIX_FIELD_COUNT, {IF_CPUARM(ZCHAR|(sizeof(md2->name)-1)) 0, 0, 0, 1, IF_CURVES(1) 0, IF_FLIGHT_PHASES(MAX_PHASES-1) 0 /*, ...*/}); #else - SUBMENU_NOTITLE(MIX_FIELD_COUNT, {IF_PCBSKY9X(ZCHAR|(sizeof(md2->name)-1)) 0, 0, 0, 1, IF_CURVES(1) 0, IF_FLIGHT_PHASES(MAX_PHASES-1) 0 /*, ...*/}); + SUBMENU_NOTITLE(MIX_FIELD_COUNT, {IF_CPUARM(ZCHAR|(sizeof(md2->name)-1)) 0, 0, 0, 1, IF_CURVES(1) 0, IF_FLIGHT_PHASES(MAX_PHASES-1) 0 /*, ...*/}); #endif int8_t sub = m_posVert; @@ -1842,7 +1842,7 @@ void menuModelMixOne(uint8_t event) int8_t i = k + s_pgOfs; uint8_t attr = (sub==i ? (editMode>0 ? BLINK|INVERS : INVERS) : 0); switch(i) { -#if defined(PCBSKY9X) +#if defined(CPUARM) case MIX_FIELD_NAME: editName(MIXES_2ND_COLUMN, y, md2->name, sizeof(md2->name), event, attr, m_posHorz); break; @@ -2138,7 +2138,7 @@ void menuModelExpoMix(uint8_t expo, uint8_t event) else displayGVar(EXPO_LINE_EXPO_POS, y, ed->curveParam); -#if defined(PCBSKY9X) +#if defined(CPUARM) if (ed->name[0]) { putsSwitches(11*FW, y, ed->swtch, 0); lcd_putsnAtt(DISPLAY_W-sizeof(ed->name)*FW-MENUS_SCROLLBAR_WIDTH, y, ed->name, sizeof(ed->name), ZCHAR | (isExpoActive(i) ? BOLD : 0)); @@ -2160,7 +2160,7 @@ void menuModelExpoMix(uint8_t expo, uint8_t event) md->weight = gvarMenuItem(11*FW+3, y, md->weight, -125, 125, attr, event); -#if defined(PCBSKY9X) +#if defined(CPUARM) if (md->name[0]) { lcd_putsnAtt(DISPLAY_W-sizeof(md->name)*FW-MENUS_SCROLLBAR_WIDTH, y, md->name, sizeof(md->name), ZCHAR | (isMixActive(i) ? BOLD : 0)); } @@ -2302,7 +2302,7 @@ enum LimitsItems { void menuModelLimits(uint8_t event) { -#if defined(PCBSKY9X) +#if defined(CPUARM) MENU(STR_MENULIMITS, menuTabModel, e_Limits, 1+NUM_CHNOUT+1, {0, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, 0}); #else MENU(STR_MENULIMITS, menuTabModel, e_Limits, 1+NUM_CHNOUT+1, {0, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, ITEM_LIMITS_MAXROW, 0}); @@ -2515,7 +2515,7 @@ void menuModelCurvesAll(uint8_t event) } #endif -#if defined(PCBSKY9X) +#if defined(CPUARM) enum CustomSwitchFields { CSW_FIELD_FUNCTION, CSW_FIELD_V1, @@ -2788,7 +2788,7 @@ void menuModelCustomSwitches(uint8_t event) void menuModelCustomFunctions(uint8_t event) { -#if defined(PCBSKY9X) && defined(SDCARD) +#if defined(CPUARM) && defined(SDCARD) uint8_t _event = event; if (s_menu_count) { event = 0; @@ -2817,7 +2817,7 @@ void menuModelCustomFunctions(uint8_t event) } putsSwitches(3, y, sd->swtch, SWONOFF | attr | ((abs(sd->swtch) <= (MAX_SWITCH+1) && getSwitch(sd->swtch, 0) && (sd->func > FUNC_INSTANT_TRIM || sd->active)) ? BOLD : 0)); if (active || AUTOSWITCH_MENU_LONG()) { -#if defined(PCBSKY9X) +#if defined(CPUARM) CHECK_INCDEC_MODELSWITCH(event, sd->swtch, SWITCH_OFF-MAX_SWITCH, SWITCH_ON+MAX_SWITCH+1+2*MAX_PSWITCH); #else CHECK_INCDEC_MODELSWITCH(event, sd->swtch, SWITCH_OFF-MAX_SWITCH, SWITCH_ON+MAX_SWITCH+1); @@ -2883,7 +2883,7 @@ void menuModelCustomFunctions(uint8_t event) lcd_outdezAtt(MODEL_CUSTOM_FUNC_3RD_COLUMN, y, val_displayed, attr|LEFT); } #endif -#if defined(PCBSKY9X) && defined(SDCARD) +#if defined(CPUARM) && defined(SDCARD) else if (sd->func == FUNC_PLAY_TRACK || sd->func == FUNC_BACKGND_MUSIC) { if (ZLEN(sd->param)) lcd_putsnAtt(MODEL_CUSTOM_FUNC_3RD_COLUMN, y, sd->param, sizeof(sd->param), attr); @@ -2904,7 +2904,7 @@ void menuModelCustomFunctions(uint8_t event) putsChnRaw(MODEL_CUSTOM_FUNC_3RD_COLUMN, y, val_displayed+1, attr); } #endif -#if defined(PCBSKY9X) +#if defined(CPUARM) else if (sd->func == FUNC_VOLUME) { val_max = NUM_XCHNRAW-1; putsChnRaw(MODEL_CUSTOM_FUNC_3RD_COLUMN, y, val_displayed+1, attr); @@ -2979,7 +2979,7 @@ void menuModelCustomFunctions(uint8_t event) } } -#if defined(PCBSKY9X) && defined(SDCARD) +#if defined(CPUARM) && defined(SDCARD) if (s_menu_count) { const char * result = displayMenu(_event); if (result) { @@ -3033,7 +3033,7 @@ enum menuModelTelemetryItems { ITEM_TELEMETRY_SCREEN_LINE6, ITEM_TELEMETRY_SCREEN_LINE7, ITEM_TELEMETRY_SCREEN_LINE8, -#if defined(PCBSKY9X) +#if defined(CPUARM) ITEM_TELEMETRY_SCREEN_LABEL3, ITEM_TELEMETRY_SCREEN_LINE9, ITEM_TELEMETRY_SCREEN_LINE10, @@ -3058,7 +3058,7 @@ enum menuModelTelemetryItems { void menuModelTelemetry(uint8_t event) { - MENU(STR_MENUTELEMETRY, menuTabModel, e_Telemetry, ITEM_TELEMETRY_MAX+1, {0, (uint8_t)-1, 1, 0, 2, 2, (uint8_t)-1, 1, 0, 2, 2, (uint8_t)-1, 1, 1, USRDATA_LINES 0, 0, IF_VARIO((uint8_t)-1) IF_VARIO(0) IF_VARIO(1) 0, 2, 2, 2, 2, 0, 2, 2, 2, IF_PCBSKY9X(2) IF_PCBSKY9X(0) IF_PCBSKY9X(2) IF_PCBSKY9X(2) IF_PCBSKY9X(2) 2 }); + MENU(STR_MENUTELEMETRY, menuTabModel, e_Telemetry, ITEM_TELEMETRY_MAX+1, {0, (uint8_t)-1, 1, 0, 2, 2, (uint8_t)-1, 1, 0, 2, 2, (uint8_t)-1, 1, 1, USRDATA_LINES 0, 0, IF_VARIO((uint8_t)-1) IF_VARIO(0) IF_VARIO(1) 0, 2, 2, 2, 2, 0, 2, 2, 2, IF_CPUARM(2) IF_CPUARM(0) IF_CPUARM(2) IF_CPUARM(2) IF_CPUARM(2) 2 }); uint8_t sub = m_posVert - 1; @@ -3246,7 +3246,7 @@ void menuModelTelemetry(uint8_t event) case ITEM_TELEMETRY_SCREEN_LABEL1: case ITEM_TELEMETRY_SCREEN_LABEL2: -#if defined(PCBSKY9X) +#if defined(CPUARM) case ITEM_TELEMETRY_SCREEN_LABEL3: { uint8_t screenIndex = (k < ITEM_TELEMETRY_SCREEN_LABEL2 ? 0 : (k < ITEM_TELEMETRY_SCREEN_LABEL3 ? 1 : 2)); @@ -3276,7 +3276,7 @@ void menuModelTelemetry(uint8_t event) case ITEM_TELEMETRY_SCREEN_LINE7: case ITEM_TELEMETRY_SCREEN_LINE8: -#if defined(PCBSKY9X) +#if defined(CPUARM) case ITEM_TELEMETRY_SCREEN_LINE9: case ITEM_TELEMETRY_SCREEN_LINE10: case ITEM_TELEMETRY_SCREEN_LINE11: @@ -3289,7 +3289,7 @@ void menuModelTelemetry(uint8_t event) screenIndex = 0; lineIndex = k-ITEM_TELEMETRY_SCREEN_LINE1; } -#if defined(PCBSKY9X) +#if defined(CPUARM) else if (k >= ITEM_TELEMETRY_SCREEN_LABEL3) { screenIndex = 2; lineIndex = k-ITEM_TELEMETRY_SCREEN_LINE9; diff --git a/src/myeeprom.h b/src/myeeprom.h index 902154cd7..9cef1229b 100644 --- a/src/myeeprom.h +++ b/src/myeeprom.h @@ -48,7 +48,9 @@ #define WARN_MEM (!(g_eeGeneral.warnOpts & WARN_MEM_BIT)) #define BEEP_VAL ( (g_eeGeneral.warnOpts & WARN_BVAL_BIT) >>3 ) -#if defined(PCBSKY9X) +#if defined(PCBX9D) +#define EEPROM_VER 213 +#elif defined(PCBSKY9X) #define EEPROM_VER 213 #elif defined(PCBGRUVIN9X) #define EEPROM_VER 212 @@ -99,7 +101,7 @@ enum BeeperMode { e_mode_all }; -#if defined(PCBSKY9X) +#if defined(CPUARM) #define EXTRA_GENERAL_FIELDS \ uint8_t speakerVolume; \ uint8_t backlightBright; \ @@ -195,7 +197,7 @@ PACK(typedef struct t_EEGeneral { #define LEN_FP_NAME 6 #endif -#if defined(PCBSKY9X) +#if defined(CPUARM) PACK(typedef struct t_ExpoData { uint8_t mode; // 0=end, 1=pos, 2=neg, 3=both uint8_t chn; @@ -243,7 +245,7 @@ PACK(typedef struct t_LimitData { #define MODE_EXPO 0 #define MODE_CURVE 1 -#if defined(PCBSKY9X) +#if defined(CPUARM) #define MAX_DELAY 60 /* 30 seconds */ #define MAX_SLOW 60 /* 30 seconds */ PACK(typedef struct t_MixData { @@ -290,7 +292,7 @@ PACK(typedef struct t_MixData { }) MixData; #endif -#if defined(PCBSKY9X) +#if defined(CPUARM) #define MAX_CSW_DURATION 120 /*60s*/ #define MAX_CSW_DELAY 120 /*60s*/ PACK(typedef struct t_CustomSwData { // Custom Switches data @@ -326,11 +328,11 @@ enum Functions { #if !defined(PCBSTD) FUNC_LOGS, #endif -#if defined(PCBSKY9X) +#if defined(CPUARM) FUNC_VOLUME, #endif FUNC_BACKLIGHT, -#if defined(PCBSKY9X) +#if defined(CPUARM) FUNC_BACKGND_MUSIC, FUNC_BACKGND_MUSIC_PAUSE, #endif @@ -344,7 +346,7 @@ enum Functions { FUNC_MAX }; -#if defined(PCBSKY9X) +#if defined(CPUARM) PACK(typedef struct t_FuncSwData { // Function Switches data int8_t swtch; //input uint8_t func; @@ -479,7 +481,7 @@ enum FrskySource { FRSKY_SOURCE_CELLS, }; -#if defined(PCBSKY9X) +#if defined(CPUARM) #define MAX_FRSKY_SCREENS 3 PACK(typedef struct t_FrSkyData { FrSkyChannelData channels[2]; @@ -602,7 +604,7 @@ typedef char gvar_name_t[6]; #define GVAR_VALUE(x, p) g_model.phaseData[p].gvars[x] #else #define MAX_GVARS 0 -#define MODEL_GVARS_DATA +#define MODEL_GVARS_DATA gvar_name_t gvarsNames[5] #define PHASE_GVARS_DATA gvar_t gvars[5] #endif @@ -616,7 +618,7 @@ PACK(typedef struct t_PhaseData { PHASE_GVARS_DATA; }) PhaseData; -#if defined(PCBSKY9X) +#if defined(CPUARM) #define MAX_MODELS 60 #define NUM_CHNOUT 32 // number of real output channels CH1-CH32 #define MAX_PHASES 9 @@ -644,7 +646,7 @@ PACK(typedef struct t_PhaseData { #define MAX_TIMERS 2 -#if defined(PCBSKY9X) +#if defined(CPUARM) #define MAX_CURVES 16 #define NUM_POINTS 512 #define CURVTYPE int16_t @@ -669,7 +671,7 @@ enum MixSources { MIXSRC_P2, MIXSRC_P3, #endif -#if defined(PCBSKY9X) && !defined(PCBX9D) +#if defined(PCBSKY9X) MIXSRC_REa, #elif defined(PCBGRUVIN9X) MIXSRC_REa, @@ -743,7 +745,7 @@ enum MixSources { #define TMRMODE_THR_REL 3 #define TMRMODE_THR_TRG 4 -#if defined(PCBGRUVIN9X) || defined(PCBSKY9X) +#if defined(PCBGRUVIN9X) || defined(CPUARM) PACK(typedef struct t_TimerData { int8_t mode; // timer trigger source -> off, abs, stk, stk%, sw/!sw, !m_sw/!m_sw uint16_t start; @@ -791,7 +793,7 @@ enum Dsm2Variants { #define TELEMETRY_DATA #endif -#if defined(PCBGRUVIN9X) || defined(PCBSKY9X) +#if defined(PCBGRUVIN9X) || defined(CPUARM) #define BeepANACenter uint16_t #else #define BeepANACenter uint8_t diff --git a/src/open9x.cpp b/src/open9x.cpp index 33afc6d44..57ba0696c 100644 --- a/src/open9x.cpp +++ b/src/open9x.cpp @@ -33,7 +33,7 @@ #include "open9x.h" -#if defined(PCBSKY9X) +#if defined(CPUARM) #define MIXER_STACK_SIZE 500 #define MENUS_STACK_SIZE 1000 #define AUDIO_STACK_SIZE 500 @@ -100,7 +100,7 @@ void loadModelBitmap() } #endif -#if !defined(PCBSKY9X) +#if !defined(CPUARM) uint8_t g_tmr1Latency_max; uint8_t g_tmr1Latency_min; #endif @@ -111,7 +111,7 @@ uint8_t unexpectedShutdown = 0; uint16_t maxMixerDuration; uint16_t lastMixerDuration; -#if defined(AUDIO) && !defined(PCBSKY9X) +#if defined(AUDIO) && !defined(CPUARM) audioQueue audio; #endif @@ -183,7 +183,7 @@ uint8_t zlen(const char *str, uint8_t size) volatile tmr10ms_t g_tmr10ms; -#if defined(PCBSKY9X) +#if defined(CPUARM) volatile uint8_t rtc_count=0; #endif @@ -200,7 +200,7 @@ void per10ms() AUDIO_INACTIVITY(); } -#if defined (PCBSKY9X) +#if defined(CPUARM) Tenms |= 1 ; // 10 mS has passed #endif @@ -208,7 +208,7 @@ void per10ms() /* Update global Date/Time every 100 per10ms cycles */ if (++g_ms100 == 100) { g_rtcTime++; // inc global unix timestamp one second -#if defined (PCBSKY9X) +#if defined(CPUARM) if (g_rtcTime < 60 || rtc_count<5) { rtc_init(); rtc_count++; @@ -223,11 +223,11 @@ void per10ms() readKeysAndTrims(); -#if defined(MAVLINK) && !defined(PCBSKY9X) +#if defined(MAVLINK) && !defined(CPUARM) check_mavlink(); #endif -#if defined (FRSKY) && !defined(PCBSKY9X) && !(defined(PCBSTD) && (defined(AUDIO) || defined(VOICE))) +#if defined(FRSKY) && !defined(CPUARM) && !(defined(PCBSTD) && (defined(AUDIO) || defined(VOICE))) check_frsky(); #endif @@ -509,7 +509,7 @@ void applyExpos(int16_t *anas) } } -#if !defined(PCBSKY9X) +#if !defined(CPUARM) int16_t calc100toRESX(int8_t x) { // return (int16_t)x*10 + x/4 - x/64; @@ -531,7 +531,6 @@ int16_t calcRESXto1000(int16_t x) // *1000/1024 = x - x/32 + x/128 return (x - x/32 + x/128); } - #endif int16_t applyLimits(uint8_t channel, int32_t value) @@ -648,7 +647,7 @@ int16_t getValue(uint8_t i) else return 0; } -#if defined(PCBSKY9X) +#if defined(CPUARM) #define GETSWITCH_RECURSIVE_TYPE uint32_t volatile bool s_default_switch_value; #else @@ -659,7 +658,7 @@ volatile GETSWITCH_RECURSIVE_TYPE s_last_switch_used; volatile GETSWITCH_RECURSIVE_TYPE s_last_switch_value; /* recursive function. stack as of today (16/03/2012) grows by 8bytes at each call, which is ok! */ -#if defined(PCBSKY9X) +#if defined(CPUARM) uint32_t delays[NUM_CSW]; uint32_t durations[NUM_CSW]; #endif @@ -671,7 +670,7 @@ bool __getSwitch(int8_t swtch) bool result; if (swtch == 0) -#if defined(PCBSKY9X) +#if defined(CPUARM) return s_default_switch_value; #else return s_last_switch_used & ((GETSWITCH_RECURSIVE_TYPE)1<<15); @@ -714,7 +713,7 @@ bool __getSwitch(int8_t swtch) } } -#if !defined(PCBSKY9X) +#if !defined(CPUARM) if (result) s_last_switch_value |= ((GETSWITCH_RECURSIVE_TYPE)1<delay) { if (result) { if (delays[cs_idx] > get_tmr10ms()) @@ -842,7 +841,7 @@ bool __getSwitch(int8_t swtch) bool getSwitch(int8_t swtch, bool nc) { -#if defined(PCBSKY9X) +#if defined(CPUARM) s_last_switch_used = 0; s_last_switch_value = 0; s_default_switch_value = nc; @@ -1051,7 +1050,7 @@ void setGVarValue(uint8_t idx, int8_t value, int8_t phase) #endif -#if defined(FRSKY) || defined(PCBSKY9X) +#if defined(FRSKY) || defined(CPUARM) void putsTelemetryValue(uint8_t x, uint8_t y, int16_t val, uint8_t unit, uint8_t att) { #ifdef IMPERIAL_UNITS @@ -1133,7 +1132,7 @@ void doSplash() lcd_img(0, 0, splash_lbm, 0, 0); refreshDisplay(); -#if !defined(PCBSKY9X) +#if !defined(CPUARM) AUDIO_TADA(); #endif @@ -1154,7 +1153,7 @@ void doSplash() { #if defined(SIMU) SIMU_SLEEP(1); -#elif defined(PCBSKY9X) +#elif defined(CPUARM) CoTickDelay(1); #endif @@ -1189,7 +1188,7 @@ void doSplash() void checkAll() { -#if !defined(PCBSKY9X) +#if !defined(CPUARM) checkLowEEPROM(); #endif @@ -1197,7 +1196,7 @@ void checkAll() checkSwitches(); } -#if !defined(PCBSKY9X) +#if !defined(CPUARM) void checkLowEEPROM() { if (g_eeGeneral.disableMemoryWarning) return; @@ -1342,7 +1341,7 @@ void message(const pm_char *title, const pm_char *t, const char *last MESSAGE_SO int8_t trimGvar[NUM_STICKS] = { -1, -1, -1, -1 }; #endif -#if defined(PCBSKY9X) +#if defined(CPUARM) void checkTrims() { uint8_t event = getEvent(true); @@ -1387,7 +1386,7 @@ uint8_t checkTrim(uint8_t event) int8_t v = (s==0) ? min(32, abs(before)/4+1) : 1 << (s-1); // 1=>1 2=>2 3=>4 4=>8 if (thro) v = 4; // if throttle trim and trim trottle then step=4 int16_t after = (k&1) ? before + v : before - v; // positive = k&1 -#if defined(PCBSKY9X) +#if defined(CPUARM) uint8_t beepTrim = 0; #else bool beepTrim = false; @@ -1448,16 +1447,16 @@ uint8_t checkTrim(uint8_t event) else { AUDIO_TRIM(event, after); } -#if !defined(PCBSKY9X) +#if !defined(CPUARM) return 0; #endif } -#if !defined(PCBSKY9X) +#if !defined(CPUARM) return event; #endif } -#if defined(PCBSKY9X) && !defined(REVA) +#if defined(CPUARM) && !defined(REVA) uint16_t Current_analogue; uint16_t Current_max; uint32_t Current_accumulator; @@ -1496,7 +1495,7 @@ uint16_t anaIn(uint8_t chan) // ana-in: 3 1 2 0 4 5 6 7 //static pm_char crossAna[] PROGMEM ={4,2,3,1,5,6,7,0}; // wenn schon Tabelle, dann muss sich auch lohnen // Google Translate (German): // if table already, then it must also be worthwhile -#if defined(PCBSKY9X) +#if defined(CPUARM) static const uint8_t crossAna[]={1,5,7,0,4,6,2,3,8}; #if !defined(REVA) if ( chan == 8 ) { @@ -1511,7 +1510,7 @@ uint16_t anaIn(uint8_t chan) return *p; } -#if defined(PCBSKY9X) +#if defined(CPUARM) void getADC() { register uint32_t x; @@ -1547,7 +1546,7 @@ void getADC() } #endif -#if !defined(PCBSKY9X) +#if !defined(CPUARM) void getADC_bandgap() { #if defined (PCBGRUVIN9X) @@ -1903,7 +1902,7 @@ PLAY_FUNCTION(playValue, uint8_t idx) } #endif -#if defined(PCBSKY9X) +#if defined(CPUARM) static uint8_t currentSpeakerVolume = 255; uint8_t requiredSpeakerVolume; uint8_t fnSwitchDuration[NUM_FSW] = { 0 }; @@ -1936,7 +1935,7 @@ void evalFunctions() MASK_FUNC_TYPE function_mask = (sd->func >= FUNC_TRAINER ? ((MASK_FUNC_TYPE)1 << (sd->func-FUNC_TRAINER)) : 0); MASK_FSW_TYPE switch_mask = ((MASK_FSW_TYPE)1 << i); uint8_t momentary = 0; -#if defined(PCBSKY9X) +#if defined(CPUARM) uint8_t shrt=0, lng=0; if (swtch > MAX_SWITCH+1+MAX_SWITCH+1+MAX_PSWITCH) { lng = 1; @@ -1956,7 +1955,7 @@ void evalFunctions() momentary = 1; swtch += MAX_SWITCH+1; } -#if defined(PCBSKY9X) +#if defined(CPUARM) bool sw; if ((sw=getSwitch(swtch, 0)) || (shrt&&fnSwitchDuration[i]>0&&fnSwitchDuration[i]=(uint8_t)FSW_PRESSLONG_DURATION)) { if (shrt || lng) { @@ -2018,7 +2017,7 @@ void evalFunctions() } } -#if defined(PCBSKY9X) && defined(SDCARD) +#if defined(CPUARM) && defined(SDCARD) if ((shrt || lng) && (activeFunctions & function_mask)) { if (sd->func == FUNC_BACKGND_MUSIC) { STOP_PLAY(i+1); @@ -2038,7 +2037,7 @@ void evalFunctions() } #endif -#if defined(PCBSKY9X) && defined(SDCARD) +#if defined(CPUARM) && defined(SDCARD) else if (sd->func == FUNC_PLAY_TRACK || sd->func == FUNC_BACKGND_MUSIC) { if (IS_PLAYING(i+1)) { switch_mask = 0; @@ -2124,10 +2123,10 @@ void evalFunctions() activeFunctionSwitches |= switch_mask; } else { -#if defined(PCBSKY9X) +#if defined(CPUARM) fnSwitchDuration[i] = 0; #endif -#if defined(PCBSKY9X) && defined(SDCARD) +#if defined(CPUARM) && defined(SDCARD) if (!COMPLEX_SWITCH && sd->func == FUNC_BACKGND_MUSIC) { STOP_PLAY(i+1); } @@ -2462,7 +2461,7 @@ ACTIVE_MIXES_TYPE activeMixes; #endif int32_t sum_chans512[NUM_CHNOUT] = {0}; -#if defined(PCBSKY9X) +#if defined(CPUARM) FORCEINLINE bool doMixerCalculations() #else FORCEINLINE void doMixerCalculations() @@ -2484,7 +2483,7 @@ FORCEINLINE void doMixerCalculations() getADC(); -#if defined(PCBSKY9X) && !defined(REVA) && !defined(SIMU) +#if defined(CPUARM) && !defined(REVA) && !defined(SIMU) Current_analogue = ( Current_analogue * 31 + s_anaFilt[8] ) >> 5 ; if (Current_analogue > Current_max) Current_max = Current_analogue ; @@ -2567,11 +2566,11 @@ FORCEINLINE void doMixerCalculations() #endif // Bandgap has had plenty of time to settle... -#if !defined(PCBSKY9X) +#if !defined(CPUARM) getADC_bandgap(); #endif -#if defined(PCBSKY9X) +#if defined(CPUARM) if (!tick10ms) return false; //make sure the rest happen only every 10ms. #else if (!tick10ms) return; //make sure the rest happen only every 10ms. @@ -2769,7 +2768,7 @@ FORCEINLINE void doMixerCalculations() } } -#if defined(PCBSKY9X) +#if defined(CPUARM) requiredSpeakerVolume = g_eeGeneral.speakerVolume; #endif @@ -2779,7 +2778,7 @@ FORCEINLINE void doMixerCalculations() if (s_rangecheck_mode) AUDIO_PLAY(AU_FRSKY_CHEEP); #endif -#if defined(PCBSKY9X) +#if defined(CPUARM) if (currentSpeakerVolume != requiredSpeakerVolume) { setVolume(requiredSpeakerVolume); currentSpeakerVolume = requiredSpeakerVolume; @@ -2793,7 +2792,7 @@ void perMain() { #if defined(SIMU) doMixerCalculations(); -#elif !defined(PCBSKY9X) +#elif !defined(CPUARM) uint16_t t0 = getTmr16KHz(); int16_t delta = (nextMixerEndTime - lastMixerDuration) - t0; if (delta > 0 && delta < MAX_MIXER_DELTA) return; @@ -2808,7 +2807,7 @@ void perMain() #endif // TODO same code here + integrate the timer which could be common -#if defined(PCBSKY9X) +#if defined(CPUARM) if (!Tenms) return; Tenms = 0 ; @@ -2822,7 +2821,7 @@ void perMain() } #endif -#if defined(PCBSKY9X) +#if defined(CPUARM) if (Eeprom32_process_state != E32_IDLE) ee32_process(); else if (TIME_TO_WRITE) @@ -2841,11 +2840,11 @@ void perMain() writeLogs(); #endif -#if defined(PCBSKY9X) && defined(SIMU) +#if defined(CPUARM) && defined(SIMU) checkTrims(); #endif -#if defined(PCBSKY9X) +#if defined(CPUARM) uint8_t evt = getEvent(false); #else uint8_t evt = getEvent(); @@ -2856,7 +2855,7 @@ void perMain() checkBacklight(); -#if defined(PCBSKY9X) && defined(FRSKY) +#if defined(CPUARM) && defined(FRSKY) check_frsky(); #endif @@ -2914,7 +2913,7 @@ void perMain() if (g_vbat100mV <= g_eeGeneral.vBatWarn && g_vbat100mV>50) { AUDIO_TX_BATTERY_LOW(); } -#if defined(PCBSKY9X) +#if defined(CPUARM) else if (g_eeGeneral.temperatureWarn && getTemperature() >= g_eeGeneral.temperatureWarn) { AUDIO_TX_TEMP_HIGH(); } @@ -2929,7 +2928,7 @@ void perMain() int16_t g_ppmIns[8]; uint8_t ppmInState = 0; //0=unsync 1..8= wait for value i-1 -#if !defined(SIMU) && !defined(PCBSKY9X) +#if !defined(SIMU) && !defined(CPUARM) volatile uint8_t g_tmr16KHz; //continuous timer 16ms (16MHz/1024/256) -- 8-bit counter overflow ISR(TIMER_16KHZ_VECT, ISR_NOBLOCK) @@ -3096,7 +3095,7 @@ ISR(TIMER3_CAPT_vect) // G: High frequency noise can cause stack overflo with IS // TODO serial_arm and serial_avr -#if defined (FRSKY) && !defined(PCBSKY9X) +#if defined(FRSKY) && !defined(CPUARM) FORCEINLINE void FRSKY_USART0_vect() { if (frskyTxBufferCount > 0) { @@ -3108,7 +3107,7 @@ FORCEINLINE void FRSKY_USART0_vect() } #endif -#if defined (DSM2_SERIAL) && !defined(PCBSKY9X) +#if defined(DSM2_SERIAL) && !defined(CPUARM) FORCEINLINE void DSM2_USART0_vect() { UDR0 = *((uint16_t*)pulses2MHzRPtr); // transmit next byte @@ -3121,7 +3120,7 @@ FORCEINLINE void DSM2_USART0_vect() } #endif -#if !defined(SIMU) && !defined(PCBSKY9X) +#if !defined(SIMU) && !defined(CPUARM) #if defined (FRSKY) || defined(DSM2_SERIAL) ISR(USART0_UDRE_vect) { @@ -3198,7 +3197,7 @@ void moveTrimsToOffsets() // copy state of 3 primary to subtrim AUDIO_WARNING2(); } -#if defined(PCBSKY9X) || defined(PCBGRUVIN9X) +#if defined(CPUARM) || defined(PCBGRUVIN9X) void saveTimers() { for (uint8_t i=0; iPWM_CH_NUM[0].PWM_CDTYUPD = g_eeGeneral.backlightBright; #elif defined(VOICE) SET_VOLUME(g_eeGeneral.speakerVolume+7); #endif -#if defined(PCBSKY9X) && defined(BLUETOOTH) +#if defined(BLUETOOTH) btInit(); #endif @@ -3331,7 +3330,7 @@ inline void open9xInit(OPEN9X_INIT_ARGS) else { doSplash(); -#if defined(PCBSKY9X) && defined(SDCARD) +#if defined(CPUARM) && defined(SDCARD) for (int i=0; i<500 && !Card_initialized; i++) { CoTickDelay(1); // 2ms } @@ -3341,7 +3340,7 @@ inline void open9xInit(OPEN9X_INIT_ARGS) checkAlarm(); } -#if defined(PCBSKY9X) || defined(PCBGRUVIN9X) +#if defined(CPUARM) || defined(PCBGRUVIN9X) if (!g_eeGeneral.unexpectedShutdown) { g_eeGeneral.unexpectedShutdown = 1; eeDirty(EE_GENERAL); @@ -3351,7 +3350,7 @@ inline void open9xInit(OPEN9X_INIT_ARGS) lcdSetContrast(); backlightOn(); -#if defined(PCBSKY9X) +#if defined(CPUARM) start_ppm_capture(); // TODO inside startPulses? s_pulses_paused = false; @@ -3363,7 +3362,7 @@ inline void open9xInit(OPEN9X_INIT_ARGS) wdt_enable(WDTO_500MS); } -#if defined(PCBSKY9X) +#if defined(CPUARM) void mixerTask(void * pdata) { s_pulses_paused = true; @@ -3504,11 +3503,11 @@ int main(void) init_rotary_sw(); #endif -#if !defined(PCBSKY9X) +#if !defined(CPUARM) open9xInit(mcusr); #endif -#if defined(PCBSKY9X) +#if defined(CPUARM) if (BOOTLOADER_REQUEST()) { soft_power_off(); // Only turn power off if necessary @@ -3569,14 +3568,12 @@ int main(void) perMain(); -#if !defined(PCBSKY9X) - if(heartbeat == HEART_TIMER_PULSES+HEART_TIMER10ms) { + if (heartbeat == HEART_TIMER_PULSES+HEART_TIMER10ms) { wdt_reset(); heartbeat = 0; } -#endif } -#endif // PCBSKY9X +#endif #if defined(PCBGRUVIN9X) // Time to switch off diff --git a/src/open9x.h b/src/open9x.h index 62ff59f21..9f80d2cc6 100644 --- a/src/open9x.h +++ b/src/open9x.h @@ -54,6 +54,12 @@ #define IF_PCBX9D(x) #endif +#if defined(CPUARM) +#define IF_CPUARM(x) x, +#else +#define IF_CPUARM(x) +#endif + #if defined(RTCLOCK) #define IF_RTCLOCK(x) x, #else @@ -147,7 +153,9 @@ #define VARIO_VARIANT 0x0080 #define HAPTIC_VARIANT 0x0100 */ -#if defined(PCBSKY9X) +#if defined(PCBX9D) +#include "board_x9d.h" +#elif defined(PCBSKY9X) #include "board_sky9x.h" #elif defined(PCBGRUVIN9X) #include "board_gruvin9x.h" @@ -157,7 +165,7 @@ #if defined(SIMU) #include "simpgmspace.h" -#elif defined(PCBSKY9X) +#elif defined(CPUARM) typedef const unsigned char pm_uchar; typedef const char pm_char; typedef const uint16_t pm_uint16_t; @@ -198,7 +206,7 @@ extern void board_init(); #define PPM_CENTER 1500 -#if defined(PCBSKY9X) +#if defined(CPUARM) #include "eeprom_arm.h" #include "pulses_arm.h" #else @@ -240,7 +248,7 @@ extern uint8_t s_bind_allowed; #if !defined(SIMU) #define assert(x) -#if !defined(PCBSKY9X) || !defined(DEBUG) +#if !defined(CPUARM) || !defined(DEBUG) #define printf printf_not_allowed #endif #endif @@ -701,7 +709,7 @@ extern char idx2char(int8_t idx); void clearKeyEvents(); void pauseEvents(uint8_t enuk); void killEvents(uint8_t enuk); -#if defined(PCBSKY9X) +#if defined(CPUARM) uint8_t getEvent(bool trim); #else uint8_t getEvent(); @@ -717,7 +725,7 @@ enum PowerState { e_power_off }; -#if defined(PCBSKY9X) +#if defined(CPUARM) uint32_t keyState(EnumKeys enuk); uint32_t check_soft_power(); #else @@ -863,13 +871,13 @@ extern uint8_t s_traceWr; extern int8_t s_traceCnt; #endif -#if defined(PCBSKY9X) +#if defined(CPUARM) static inline uint16_t getTmr2MHz() { return TC1->TC_CHANNEL[0].TC_CV; } #else uint16_t getTmr16KHz(); #endif -#if defined(PCBSKY9X) +#if defined(CPUARM) uint16_t stack_free(uint8_t tid); #else uint16_t stack_free(); @@ -908,7 +916,7 @@ extern uint8_t s_eeDirtyMsk; extern void backlightOn(); -#if defined (PCBSKY9X) +#if defined (CPUARM) #define __BACKLIGHT_ON (PWM->PWM_CH_NUM[0].PWM_CDTY = g_eeGeneral.backlightBright) #define __BACKLIGHT_OFF (PWM->PWM_CH_NUM[0].PWM_CDTY = 100) #if defined(REVA) @@ -975,7 +983,7 @@ template FORCEINLINE t limit(t mi, t x, t ma) { return min(max(mi,x),ma uint16_t isqrt32(uint32_t n); #endif -#if defined(PCBSKY9X) +#if defined(CPUARM) #if !defined(SIMU) extern "C" { #include @@ -997,7 +1005,7 @@ inline void resumeMixerCalculations() #define resumeMixerCalculations() #endif -#if defined(PCBSKY9X) || defined(PCBGRUVIN9X) +#if defined(CPUARM) || defined(PCBGRUVIN9X) void saveTimers(); #else #define saveTimers() @@ -1013,7 +1021,7 @@ void eeLoadModel(uint8_t id); void generalDefault(); void modelDefault(uint8_t id); -#if defined(PCBSKY9X) +#if defined(CPUARM) inline int32_t calc100toRESX(register int8_t x) { return x * 1024 / 100; @@ -1040,7 +1048,7 @@ extern int16_t calc1000toRESX(int16_t x); extern int16_t calcRESXto1000(int16_t x); #endif -#if defined(PCBSKY9X) +#if defined(CPUARM) // This doesn't need protection on this processor #define tmr10ms_t uint32_t extern volatile tmr10ms_t g_tmr10ms; @@ -1114,7 +1122,7 @@ extern void incSubtrim(uint8_t idx, int16_t inc); extern void instantTrim(); extern void moveTrimsToOffsets(); -#if defined(PCBSKY9X) +#if defined(CPUARM) #define ACTIVE_EXPOS_TYPE uint32_t #define ACTIVE_MIXES_TYPE uint64_t #else @@ -1139,7 +1147,7 @@ inline bool isMixActive(uint8_t mix) #define isMixActive(x) false #endif -#if defined(PCBSKY9X) +#if defined(CPUARM) #define MASK_FSW_TYPE uint32_t // current max = 32 function switches #define MASK_FUNC_TYPE uint32_t // current max = 32 functions #else @@ -1199,7 +1207,7 @@ extern uint16_t jeti_keys; enum AUDIO_SOUNDS { AU_INACTIVITY, AU_TX_BATTERY_LOW, -#if defined(PCBSKY9X) +#if defined(CPUARM) AU_TX_MAH_HIGH, AU_TX_TEMP_HIGH, #endif @@ -1218,7 +1226,7 @@ enum AUDIO_SOUNDS { AU_WARNING2, AU_WARNING3, AU_TRIM_MIDDLE, -#if defined(PCBSKY9X) +#if defined(CPUARM) AU_TRIM_END, #endif AU_TADA, @@ -1251,7 +1259,7 @@ enum AUDIO_SOUNDS { }; #if defined(AUDIO) -#if defined(PCBSKY9X) +#if defined(CPUARM) #include "sky9x/audio.h" #else #include "stock/audio.h" @@ -1288,7 +1296,7 @@ union ReusableBuffer { /* 128 bytes on stock */ -#if !defined(PCBSKY9X) +#if !defined(CPUARM) uint8_t eefs_buffer[BLOCKS]; // 128bytes used by EeFsck #endif @@ -1327,7 +1335,7 @@ extern union ReusableBuffer reusableBuffer; void checkFlashOnBeep(); -#if defined(FRSKY) || defined(PCBSKY9X) +#if defined(FRSKY) || defined(CPUARM) void putsTelemetryValue(uint8_t x, uint8_t y, int16_t val, uint8_t unit, uint8_t att); #endif diff --git a/src/sdcard.h b/src/sdcard.h index 952e63f78..c35de59b2 100644 --- a/src/sdcard.h +++ b/src/sdcard.h @@ -78,7 +78,7 @@ inline const pm_char *SDCARD_ERROR(FRESULT result) extern void sdMountPoll(); #endif -#if defined(PCBSKY9X) && !(defined(SIMU)) +#if defined(CPUARM) && !(defined(SIMU)) extern "C" { extern uint32_t sd_card_ready(); extern uint32_t sd_card_mounted(); @@ -88,7 +88,9 @@ extern uint32_t sd_card_mounted(); #define sd_card_mounted() (true) #endif -#if defined(PCBSKY9X) +#if defined(PCBX9D) +#define O9X_FOURCC 0x3378396F // o9x for X9D +#elif defined(PCBSKY9X) #define O9X_FOURCC 0x3278396F // o9x for sky9x #elif defined(PCBGRUVIN9X) #define O9X_FOURCC 0x3178396F // o9x for gruvin9x diff --git a/src/simpgmspace.cpp b/src/simpgmspace.cpp index 70fca507e..1780be4b9 100644 --- a/src/simpgmspace.cpp +++ b/src/simpgmspace.cpp @@ -43,7 +43,7 @@ uint16_t dummyport16; const char *eepromFile = NULL; FILE *fp = NULL; -#if defined(PCBSKY9X) +#if defined(CPUARM) Pio Pioa, Piob, Pioc; Pwm pwm; Twi Twio; @@ -63,7 +63,7 @@ extern const char* eeprom_buffer_data; uint8_t eeprom[EESIZE]; sem_t *eeprom_write_sem; -#if defined(PCBSKY9X) +#if defined(CPUARM) #define SWITCH_CASE(swtch, pin, bit) \ case -DSW(swtch): \ pin &= ~(1< #endif -#if defined(PCBSKY9X) +#if defined(CPUARM) FATFS g_FATFS_Obj; #endif @@ -568,7 +568,7 @@ FRESULT f_getcwd (TCHAR *path, UINT sz_path) return FR_OK; } -#if defined(PCBSKY9X) +#if defined(CPUARM) int32_t Card_state = SD_ST_MOUNTED; uint32_t Card_CSD[4]; // TODO elsewhere #endif diff --git a/src/simpgmspace.h b/src/simpgmspace.h index 9ad340647..89a542e5c 100644 --- a/src/simpgmspace.h +++ b/src/simpgmspace.h @@ -96,7 +96,7 @@ typedef const int16_t pm_int16_t; typedef const int8_t pm_int8_t; extern sem_t *eeprom_write_sem; -#if defined(PCBSKY9X) +#if defined(CPUARM) extern Pio Pioa, Piob, Pioc; extern Twi Twio; extern Dacc dacc; @@ -266,7 +266,7 @@ extern void rxPdcUsart( void (*pChProcess)(uint8_t x) ); #define ISR(x) void x() -#if defined(PCBSKY9X) +#if defined(CPUARM) extern volatile uint32_t Tenms; extern uint32_t Master_frequency; #define NVIC_EnableIRQ(x) diff --git a/src/simu.cpp b/src/simu.cpp index e729a902e..5bbc51c6e 100644 --- a/src/simu.cpp +++ b/src/simu.cpp @@ -273,7 +273,7 @@ long Open9xSim::onTimeout(FXObject*,FXSelector,void*) #endif }; -#if defined(PCBSKY9X) +#if defined(CPUARM) PIOC->PIO_PDSR |= ERSKY9X_DOWN_MASK | ERSKY9X_UP_MASK | ERSKY9X_RIGHT_MASK | ERSKY9X_LEFT_MASK ; ERSKY9X_EXIT_PIO->PIO_PDSR |= ERSKY9X_EXIT_MASK; PIOB->PIO_PDSR |= ERSKY9X_RETURN_MASK; @@ -290,7 +290,7 @@ long Open9xSim::onTimeout(FXObject*,FXSelector,void*) for(unsigned i=0; igetKeyState(keys1[i])) { -#if defined(PCBSKY9X) +#if defined(CPUARM) ((Pio*)keys1[i+3])->PIO_PDSR &= ~(keys1[i+4]); #elif defined(PCBGRUVIN9X) pin |= (1<PIO_PDSR |= (0x00800000 | 0x01000000 | 0x00000002 | 0x00000001); PIOB->PIO_PDSR |= (0x00000050); PIOC->PIO_PDSR |= (0x10000000 | 0x00000400 | 0x00000200); @@ -327,7 +327,7 @@ long Open9xSim::onTimeout(FXObject*,FXSelector,void*) for(unsigned i=0; igetKeyState(keys2[i])) { -#if defined(PCBSKY9X) +#if defined(CPUARM) switch(i) { case 6: PIOA->PIO_PDSR &= ~0x00800000; @@ -425,7 +425,7 @@ void Open9xSim::refreshDiplay() { if (lcd_refresh) { lcd_refresh = false; -#if defined(PCBSKY9X) +#if defined(CPUARM) if (PWM->PWM_CH_NUM[0].PWM_CDTY != 100) #elif defined(PCBGRUVIN9X) if (portc & 1<> SEG_SHIFT; + + return (u_val & SIGN_BIT) ? (BIAS - t) : (t - BIAS); +} + +void codecsInit() +{ + for (uint32_t i=0; i<256; i++) { alawTable[i] = (0x8000 + alaw2linear(i)) >> 4; + ulawTable[i] = (0x8000 + ulaw2linear(i)) >> 4; + } } AudioQueue audioQueue; @@ -155,6 +176,7 @@ extern uint16_t Sine_values[]; #define CODEC_ID_PCM_S16LE 1 #define CODEC_ID_PCM_ALAW 6 +#define CODEC_ID_PCM_MULAW 7 #ifndef SIMU void audioTask(void* pdata) @@ -243,6 +265,13 @@ void AudioQueue::sdWakeup(AudioContext & context) for (i = read; i < WAV_BUFFER_SIZE; i++) wavSamplesBuffer[i] = 0x8000; } + else if (context.pcmCodec == CODEC_ID_PCM_MULAW) { + int32_t i; + for (i = read - 1; i >= 0; i--) + wavSamplesBuffer[i] = ulawTable[((uint8_t *) wavSamplesBuffer)[i]]; + for (i = read; i < WAV_BUFFER_SIZE; i++) + wavSamplesBuffer[i] = 0x8000; + } read /= 2; register Dacc *dacptr = DACC; diff --git a/src/sky9x/audio.h b/src/sky9x/audio.h index dac2cb361..64cb4c5c1 100644 --- a/src/sky9x/audio.h +++ b/src/sky9x/audio.h @@ -132,7 +132,7 @@ class AudioQueue { extern AudioQueue audioQueue; -void alawInit(); +void codecsInit(); void audioEvent(uint8_t e, uint8_t f=BEEP_DEFAULT_FREQ); #define AUDIO_TADA() audioEvent(AU_TADA) diff --git a/src/statistics_views.cpp b/src/statistics_views.cpp index 986336c05..c0863564e 100644 --- a/src/statistics_views.cpp +++ b/src/statistics_views.cpp @@ -80,7 +80,7 @@ void menuStatisticsView(uint8_t event) #endif } -#if defined(PCBSKY9X) +#if defined(CPUARM) #define MENU_DEBUG_COL_OFS (13*FW) #else #define MENU_DEBUG_COL_OFS (14*FW) @@ -92,7 +92,7 @@ void menuStatisticsDebug(uint8_t event) switch(event) { -#if defined(PCBSKY9X) +#if defined(CPUARM) case EVT_KEY_LONG(KEY_MENU): g_eeGeneral.mAhUsed = 0; g_eeGeneral.globalTimer = 0; @@ -104,7 +104,7 @@ void menuStatisticsDebug(uint8_t event) break; #endif case EVT_KEY_FIRST(KEY_MENU): -#if !defined(PCBSKY9X) +#if !defined(CPUARM) g_tmr1Latency_min = 0xff; g_tmr1Latency_max = 0; #endif @@ -120,7 +120,7 @@ void menuStatisticsDebug(uint8_t event) return; } -#if defined(PCBSKY9X) +#if defined(CPUARM) #if !defined(REVA) lcd_putsLeft(1*FH, STR_CPU_CURRENT); putsTelemetryValue(MENU_DEBUG_COL_OFS, 1*FH, getCurrent(), UNIT_MILLIAMPS, 0); diff --git a/src/translations.cpp b/src/translations.cpp index 08388cd6c..f6084f9a8 100644 --- a/src/translations.cpp +++ b/src/translations.cpp @@ -64,7 +64,7 @@ const pm_char STR_OPEN9X[] PROGMEM = ISTR(VFSWRESET) ISTR(FUNCSOUNDS) ISTR(VTELEMCHNS) -#if defined(FRSKY) || defined(PCBSKY9X) +#if defined(FRSKY) || defined(CPUARM) ISTR(VTELEMUNIT) ISTR(VALARM) ISTR(VALARMFN) @@ -87,10 +87,10 @@ const pm_char STR_OPEN9X[] PROGMEM = #if defined(DSM2) ISTR(DSM2MODE) #endif -#if defined(PCBGRUVIN9X) || defined (PCBSKY9X) +#if defined(PCBGRUVIN9X) || defined (CPUARM) ISTR(DATETIME) #endif -#if defined(PCBSKY9X) +#if defined(CPUARM) ISTR(VLCD) #endif ; @@ -235,7 +235,7 @@ const pm_char STR_EEPROMOVERFLOW[] PROGMEM = TR_EEPROMOVERFLOW; const pm_char STR_TRIMS2OFFSETS[] PROGMEM = TR_TRIMS2OFFSETS; const pm_char STR_MENURADIOSETUP[] PROGMEM = TR_MENURADIOSETUP; -#if defined(PCBGRUVIN9X) || defined(PCBSKY9X) +#if defined(PCBGRUVIN9X) || defined(CPUARM) const pm_char STR_MENUDATEANDTIME[] PROGMEM = TR_MENUDATEANDTIME; #endif @@ -294,18 +294,18 @@ const pm_char STR_LATITUDE[] PROGMEM = TR_LATITUDE; const pm_char STR_LONGITUDE[] PROGMEM = TR_LONGITUDE; #endif -#if defined(PCBSKY9X) || defined(PCBGRUVIN9X) +#if defined(CPUARM) || defined(PCBGRUVIN9X) const pm_char STR_SHUTDOWN[] PROGMEM = TR_SHUTDOWN; #endif const pm_char STR_BATT_CALIB[] PROGMEM = TR_BATT_CALIB; -#if defined(PCBSKY9X) || defined(FRSKY) +#if defined(CPUARM) || defined(FRSKY) const pm_char STR_VOLTAGE[] PROGMEM = TR_VOLTAGE; const pm_char STR_CURRENT[] PROGMEM = TR_CURRENT; #endif -#if defined(PCBSKY9X) +#if defined(CPUARM) const pm_char STR_CURRENT_CALIB[] PROGMEM = TR_CURRENT_CALIB; #endif diff --git a/src/translations.h b/src/translations.h index 141e051d8..c7218776d 100644 --- a/src/translations.h +++ b/src/translations.h @@ -97,7 +97,7 @@ extern const pm_char STR_OPEN9X[]; #define OFS_VFSWRESET (OFS_VFSWFUNC + sizeof(TR_VFSWFUNC)) #define OFS_FUNCSOUNDS (OFS_VFSWRESET + sizeof(TR_VFSWRESET)) #define OFS_VTELEMCHNS (OFS_FUNCSOUNDS + sizeof(TR_FUNCSOUNDS)) -#if defined(FRSKY) || defined(PCBSKY9X) +#if defined(FRSKY) || defined(CPUARM) #define OFS_VTELEMUNIT (OFS_VTELEMCHNS + sizeof(TR_VTELEMCHNS)) #define OFS_VALARM (OFS_VTELEMUNIT + sizeof(TR_VTELEMUNIT)) #define OFS_VALARMFN (OFS_VALARM + sizeof(TR_VALARM)) @@ -132,10 +132,10 @@ extern const pm_char STR_OPEN9X[]; #else #define OFS_ENDDSM2 (OFS_VTMRMODES + sizeof(TR_VTMRMODES)) #endif -#if defined(PCBGRUVIN9X) || defined (PCBSKY9X) +#if defined(PCBGRUVIN9X) || defined(CPUARM) #define OFS_DATETIME (OFS_ENDDSM2) #endif -#if defined(PCBSKY9X) +#if defined(CPUARM) #define OFS_VLCD (OFS_DATETIME + sizeof(TR_DATETIME)) #endif @@ -165,7 +165,7 @@ extern const pm_char STR_OPEN9X[]; #define STR_FUNCSOUNDS (STR_OPEN9X + OFS_FUNCSOUNDS) #define STR_VTELEMCHNS (STR_OPEN9X + OFS_VTELEMCHNS) -#if defined(FRSKY) || defined(PCBSKY9X) +#if defined(FRSKY) || defined(CPUARM) #define STR_VTELEMUNIT (STR_OPEN9X + OFS_VTELEMUNIT) #define STR_VALARM (STR_OPEN9X + OFS_VALARM) #define STR_VALARMFN (STR_OPEN9X + OFS_VALARMFN) @@ -199,11 +199,11 @@ extern const pm_char STR_OPEN9X[]; #define STR_VRENCODERS (STR_OPEN9X + OFS_VRENCODERS) #endif -#if defined(PCBGRUVIN9X) || defined(PCBSKY9X) +#if defined(PCBGRUVIN9X) || defined(CPUARM) #define STR_DATETIME (STR_OPEN9X + OFS_DATETIME) #endif -#if defined(PCBSKY9X) +#if defined(CPUARM) #define STR_VLCD (STR_OPEN9X + OFS_VLCD) #endif @@ -382,18 +382,18 @@ extern const pm_char STR_LATITUDE[]; extern const pm_char STR_LONGITUDE[]; #endif -#if defined(PCBSKY9X) || defined(PCBGRUVIN9X) +#if defined(CPUARM) || defined(PCBGRUVIN9X) extern const pm_char STR_SHUTDOWN[]; #endif extern const pm_char STR_BATT_CALIB[]; -#if defined(PCBSKY9X) || defined(FRSKY) +#if defined(CPUARM) || defined(FRSKY) extern const pm_char STR_VOLTAGE[]; extern const pm_char STR_CURRENT[]; #endif -#if defined(PCBSKY9X) +#if defined(CPUARM) extern const pm_char STR_CURRENT_CALIB[]; #define LEN_CALIB_FIELDS (PSIZE(TR_BATT_CALIB) > PSIZE(TR_CURRENT_CALIB) ? PSIZE(TR_BATT_CALIB) : PSIZE(TR_CURRENT_CALIB)) #else diff --git a/src/translations/en.h b/src/translations/en.h index cdf4d8a5c..1e7c9f794 100644 --- a/src/translations/en.h +++ b/src/translations/en.h @@ -105,7 +105,7 @@ #define TR_PLAY_TRACK "[PlayTrack]" #define TR_PLAY_VALUE "[PlayValue]" #endif -#if defined(PCBSKY9X) +#if defined(CPUARM) #if defined(SDCARD) #define TR_SDCLOGS "SD Logs\0 " #else @@ -350,7 +350,7 @@ #define STR_US (STR_TMR1LATMAXUS+12) #define TR_TMR1LATMINUS "Tmr1Lat min\006us" #define TR_TMR1JITTERUS "Tmr1 Jitter\006us" -#if defined(PCBSKY9X) +#if defined(CPUARM) #define TR_TMIXMAXMS "Tmix max\012ms" #else #define TR_TMIXMAXMS "Tmix max\014ms" diff --git a/src/x9d/Audio.c b/src/x9d/Audio.c new file mode 100644 index 000000000..69b641a64 --- /dev/null +++ b/src/x9d/Audio.c @@ -0,0 +1,105 @@ +/** + ****************************************************************************** + * @file Project/Audio/Audio.c + * @author X9D Application Team + * @version V 0.2 + * @date 12-JULY-2012 + * @brief This file provides drivers foe Audio module.I2S AND GPIO Included. + ****************************************************************************** +*/ + +#include "stm32f2xx.h" +#include "Audio.h" +#include "hal.h" + + +static +void Audio_GPIO_Init() +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* EnableI2C GPIO clocks */ + RCC_AHB1PeriphClockCmd(CODEC_I2S_GPIO_CLOCK, ENABLE);//GPIOA C + + /* CODEC_I2S pins configuration: WS, SCK and SD pins -----------------------------*/ + GPIO_InitStructure.GPIO_Pin = CODEC_I2S_SCK_PIN | CODEC_I2S_SD_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(CODEC_I2S_GPIO, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = CODEC_I2S_WS_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(CODEC_I2S_WS_GPIO, &GPIO_InitStructure); + + /* Connect pins to I2S peripheral */ + GPIO_PinAFConfig(CODEC_I2S_WS_GPIO, CODEC_I2S_WS_PINSRC, CODEC_I2S_GPIO_AF); + GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_SCK_PINSRC, CODEC_I2S_GPIO_AF); + GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_SD_PINSRC, CODEC_I2S_GPIO_AF); + +#ifdef CODEC_MCLK_ENABLED + /* CODEC_I2S pins configuration: MCK pin */ + GPIO_InitStructure.GPIO_Pin = CODEC_I2S_MCK_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(CODEC_I2S_MCK_GPIO, &GPIO_InitStructure); + /* Connect pins to I2S peripheral */ + GPIO_PinAFConfig(CODEC_I2S_MCK_GPIO, CODEC_I2S_MCK_PINSRC, CODEC_I2S_GPIO_AF); +#endif /* CODEC_MCLK_ENABLED */ + +/*CODEC_I2S_MUTE & CODEC_I2S_FLT GPIO CONFIG*/ + GPIO_InitStructure.GPIO_Pin = CODEC_I2S_MUTE;// | CODEC_I2S_FLT; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(CODEC_I2S_GPIO, &GPIO_InitStructure); + GPIO_SetBits(CODEC_I2S_GPIO,CODEC_I2S_MUTE); + // GPIO_SetBits(CODEC_I2S_CTL_GPIO,CODEC_I2S_FLT); +} + +void I2S2_Init() +{ + I2S_InitTypeDef I2S_InitStructure; + + Audio_GPIO_Init(); + + /*CONFIG the I2S_RCC ,MUST before enabling the I2S APB clock*/ + //PLLI2SN 302,PLLI2SR 2,I2SDIV 53,I2SODD 1,FS 44.1KHZ,16bit,Error 0.0011% + RCC_PLLI2SConfig(302,2); + RCC_PLLI2SCmd(ENABLE); + RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S); + + /* Enable the CODEC_I2S peripheral clock */ + RCC_APB1PeriphClockCmd(CODEC_I2S_CLK, ENABLE); + /* CODEC_I2S peripheral configuration */ + SPI_I2S_DeInit(CODEC_I2S); + I2S_InitStructure.I2S_AudioFreq = AudioFreq; + I2S_InitStructure.I2S_Standard = I2S_Standard_Phillips; + I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b; + I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;//clk 0 when idle state + I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx; +#ifdef CODEC_MCLK_ENABLED + I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Enable; +#elif defined(CODEC_MCLK_DISABLED) + I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable; +#else + #error "No selection for the MCLK output has been defined !" +#endif /* CODEC_MCLK_ENABLED */ + + /* Initialize the I2S peripheral with the structure above */ + I2S_Init(CODEC_I2S, &I2S_InitStructure); + I2S_Cmd(CODEC_I2S,ENABLE); + //interrupt +#ifdef CODEC_USE_INT + SPI_I2S_ITConfig(CODEC_I2S,SPI_I2S_IT_TXE,ENABLE); +#elif defined(CODEC_USE_DMA) +#error "DMA is not initialized" +#endif +} diff --git a/src/x9d/Audio.h b/src/x9d/Audio.h new file mode 100644 index 000000000..fae74fb0b --- /dev/null +++ b/src/x9d/Audio.h @@ -0,0 +1,28 @@ +/** + ****************************************************************************** + * @file Project/Audio/Audio.h + * @author X9D Application Team + * @version V 0.2 + * @date 12-JULY-2011 + * @brief Header for Audio.c. + ****************************************************************************** +*/ +#ifndef _AUDIO_H_ +#define _AUDIO_H_ + +#include "stdint.h" +#include "Macro_define.h" + +extern const uint16_t AUDIO_SAMPLE[]; +// +void I2S2_Init(); + + +typedef struct{ + uint32_t size; //number of chars per font + uint16_t *base; //font addr +}A_SAMPLE; + +extern A_SAMPLE demo_sample; + +#endif \ No newline at end of file diff --git a/src/x9d/Macro_define.h b/src/x9d/Macro_define.h new file mode 100644 index 000000000..a954e8177 --- /dev/null +++ b/src/x9d/Macro_define.h @@ -0,0 +1,27 @@ +/** + ****************************************************************************** + * @file Project/Macro_define.h + * @author X9D Application Team + * @Hardware version V0.2 + * @date 11-July-2012 + * @brief This file provides Macro defines for testing or working. + * * + ****************************************************************************** +*/ +#ifndef _Macro_Define_H_ +#define _Macro_Define_H_ +#include "stm32f2xx.h" + +#define assert(x) do{ if(!(x)) while(1);}while(0); + +#define udelay(x) do{ uint32_t temp; temp=((x+0)<<3); while(--temp);}while(0) +#define delayUsec(x) udelay(x) + +#define LCD_TEST +#define AUDIO_TEST +//#define I2C_TEST +//#define ADC_TEST + + + +#endif \ No newline at end of file diff --git a/src/x9d/adc.c b/src/x9d/adc.c new file mode 100644 index 000000000..13ad3f21b --- /dev/null +++ b/src/x9d/adc.c @@ -0,0 +1,107 @@ +/** + ****************************************************************************** + * @file Project/adc/adc.c + * @author X9D Application Team + * @Hardware version V0.2 + * @date 11-July-2012 + * @brief This file provides adc Init and drivers. + * * + ****************************************************************************** +*/ +#include "stm32f2xx.h" +#include "adc.h" +#include "hal.h" +#include "msg_que.h" +#include "stdio.h" +#include "stdlib.h" +#include "item.h" + + + +#define ADC1_DR_ADDRESS ((uint32_t)0x4001204C) +//#define ADC2_DR_ADDRESS ((uint32_t)0x4001214C) +//#define ADC3_DR_ADDRESS ((uint32_t)0x4001224C) + +__IO uint16_t ADC1ConvertedValue[10] = {0}; + + +void adc_clk_init() +{ + /* Enable peripheral clocks *************************************************/ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOADC, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); +} + + + +void adc_gpio_init() +{ + GPIO_InitTypeDef GPIO_InitStructure; +//AIN state + /* Configure ADC1 Channel5 pin as analog input ******************************/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ; + GPIO_Init(GPIOC, &GPIO_InitStructure); + +} +void adc_init() //one adc +{ + ADC_InitTypeDef ADC_InitStructure; + ADC_CommonInitTypeDef ADC_CommonInitStructure; + DMA_InitTypeDef DMA_InitStructure; + + adc_clk_init();//enable + adc_gpio_init();//AIN + + /* ADC1 regular channel configuration ************************************/ + ADC_InitStructure.ADC_Resolution = ADC_Resolution_10b; + ADC_InitStructure.ADC_ScanConvMode = DISABLE; + ADC_InitStructure.ADC_ContinuousConvMode = ENABLE; // + ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; // + ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; // + ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStructure.ADC_NbrOfConversion = 1;// + ADC_Init(ADC1, &ADC_InitStructure); + + /* ADC Common configuration ********************** ***************************/ + ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent;//one ADC + ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_6Cycles;//6* 1/30M + ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;// + ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div2; //60M/2 + ADC_CommonInit(&ADC_CommonInitStructure); + + /* ADC1 regular channel configuration */ + ADC_RegularChannelConfig(ADC1, ADC_Channel_15, 1, ADC_SampleTime_3Cycles);// + + + /* DMA2 Stream0 channel0 configuration **************************************/ + DMA_InitStructure.DMA_Channel = DMA_Channel_0; + DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)ADC1_DR_ADDRESS; + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)ADC1ConvertedValue; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + DMA_InitStructure.DMA_BufferSize = 1; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord; + DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; + DMA_InitStructure.DMA_Priority = DMA_Priority_High; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + DMA_Init(DMA2_Stream0, &DMA_InitStructure); + DMA_Cmd(DMA2_Stream0, ENABLE); + + /* Enable DMA request after last transfer (Single-ADC mode) */ + ADC_DMARequestAfterLastTransferCmd(ADC1, ENABLE); + + /* Enable ADC1 DMA */ + ADC_DMACmd(ADC1, ENABLE); + + /* Enable ADC1 */ + ADC_Cmd(ADC1, ENABLE); + +} diff --git a/src/x9d/adc.h b/src/x9d/adc.h new file mode 100644 index 000000000..f8e0885c2 --- /dev/null +++ b/src/x9d/adc.h @@ -0,0 +1,16 @@ +/** + ****************************************************************************** + * @file Project/adc/adc.h + * @author X9D Application Team + * @Hardware version V0.2 + * @date 11-July-2012 + * @brief This file provides adc Init and drivers. + * * + ****************************************************************************** +*/ +#ifndef _ADC_INIT_H_ +#define _ADC_INIT_H_ + + +void adc_init(); +#endif \ No newline at end of file diff --git a/src/x9d/buttons.c b/src/x9d/buttons.c new file mode 100644 index 000000000..975d1a3bb --- /dev/null +++ b/src/x9d/buttons.c @@ -0,0 +1,135 @@ +#include "stm32f2xx.h" +#include "hal.h" +#include "buttons.h" + + +void Buttons_Init() //上拉输入状态 +{ + GPIO_InitTypeDef GPIO_InitStructure; + /* GPIOC GPIOD clock enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOBUTTON, ENABLE); + + /* GPIO Configuration*/ + GPIO_InitStructure.GPIO_Pin = PIN_BUTTON_UP | PIN_BUTTON_ENTER | PIN_BUTTON_DOWN | PIN_TRIM3_UP | PIN_TRIM3_DN + | PIN_TRIM4_UP |PIN_TRIM4_DN | PIN_SW_A_L | PIN_SW_D_L | PIN_SW_F_H | PIN_SW_G_H + | PIN_SW_G_L | PIN_SW_H_L; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; + GPIO_Init(GPIOE, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = PIN_HOME | PIN_ESC | PIN_PAGE; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;//复位状态，IN时应该忽略 + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; + GPIO_Init(GPIOD, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = PIN_TRIM1_UP | PIN_TRIM1_DN | PIN_TRIM2_UP | PIN_TRIM2_DN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = PIN_SW_B_H | PIN_SW_B_L | PIN_SW_C_H | PIN_SW_C_L | PIN_SW_D_H | PIN_SW_E_H | PIN_SW_F_L; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = PIN_SW_E_L; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +} + +//short pin_status=0; +//short pin_status1=0; + +void detect_buttons() +{ + /*short t_pin;short t_pin1; + static short key_down_interval; + key_down_interval++;//计数循环多少次有键按下 + + t_pin = (~(GPIOC->IDR)) &(PIN_BUTTON_UP | PIN_BUTTON_ENTER | PIN_BUTTON_DOWN); + t_pin1=(~(GPIOB->IDR)) &(PIN_POWER | PIN_BIND); + + if( (t_pin1 & PIN_BIND) && (!(pin_status1 & PIN_BIND))&&(!(t_pin1 & PIN_POWER)) ) + { + } + if( (t_pin1 & PIN_POWER) && (!(pin_status1 & PIN_POWER))) + { + + } + if( (pin_status1 & PIN_BIND) && (pin_status1 & PIN_POWER )) + { + static char t_pin_bind; + t_pin_bind++;//这个变量 + if( (t_pin_bind ==39) || (t_pin_bind==69)){ + t_pin_bind =40; + //SetIDProc(0,0,0,t_pin_bind); + } + } + + if( (t_pin & PIN_BUTTON_UP) && (!(pin_status & PIN_BUTTON_UP )) ) + { + + } + if( (t_pin & PIN_BUTTON_ENTER) && (!(pin_status & PIN_BUTTON_ENTER )) ) + { + + } + if( (t_pin & PIN_BUTTON_DOWN) && (!(pin_status & PIN_BUTTON_DOWN )) ) + { + } + ////////////////////////////////////////////////////////////////////////////////////// + if( (pin_status & PIN_BUTTON_UP)) + { + static char t_pin_up; + t_pin_up++;//这个变量 + if( (t_pin_up ==9) || (t_pin_up==22)){ + t_pin_up =10; + + }else if((!(t_pin & PIN_BUTTON_UP))) + { + } + } + + if( (pin_status & PIN_BUTTON_ENTER)) + { + static char t_pin_enter; + t_pin_enter++; + if( (t_pin_enter ==9) || (t_pin_enter ==22)){ + t_pin_enter =10; + + }else if((!(t_pin & PIN_BUTTON_ENTER))){ + if(t_pin_enter<9) + + t_pin_enter =0; + } + } + + if( (pin_status & PIN_BUTTON_DOWN)) + { + static char t_pin_down; + t_pin_down++; + if( (t_pin_down ==9) || (t_pin_down==22) ){ + t_pin_down =10; + + }else if((!(t_pin & PIN_BUTTON_DOWN))){ + if(t_pin_down<9) + + t_pin_down =0; + } + } + + pin_status = t_pin; + pin_status1=t_pin1;*/ +} \ No newline at end of file diff --git a/src/x9d/buttons.h b/src/x9d/buttons.h new file mode 100644 index 000000000..c91a2b5a2 --- /dev/null +++ b/src/x9d/buttons.h @@ -0,0 +1,5 @@ +#ifndef _BUTTONS_H_ +#define _BUTTONS_H_ + + +#endif \ No newline at end of file diff --git a/src/x9d/hal.h b/src/x9d/hal.h new file mode 100644 index 000000000..cf1868b4d --- /dev/null +++ b/src/x9d/hal.h @@ -0,0 +1,255 @@ +#ifndef _HAL_ +#define _HAL_ + +/******************************** +GPIOS----所有涉及GPIO的定义 +*******************************************/ + +#define RCC_AHB1Periph_GPIOBUTTON (RCC_AHB1Periph_GPIOA|RCC_AHB1Periph_GPIOB|RCC_AHB1Periph_GPIOC|RCC_AHB1Periph_GPIOD|RCC_AHB1Periph_GPIOE) +//Button +#define PIN_BUTTON_UP GPIO_Pin_0 //SW3 PE.10 +#define PIN_BUTTON_ENTER GPIO_Pin_1 //SW2 PE.11 +#define PIN_BUTTON_DOWN GPIO_Pin_2 //SW1 PE.12 +#define PIN_HOME GPIO_Pin_11 //SW4 PD.07 +#define PIN_ESC GPIO_Pin_12 //SW5 PD.03 +#define PIN_PAGE GPIO_Pin_10 //SW6 PD.02 + +//Trim +#define PIN_TRIM1_UP GPIO_Pin_3 //PC.03 +#define PIN_TRIM1_DN GPIO_Pin_2 //PC.02 +#define PIN_TRIM2_UP GPIO_Pin_1 //PC.01 +#define PIN_TRIM2_DN GPIO_Pin_13 //PC.13 +#define PIN_TRIM3_UP GPIO_Pin_4 //PE.04 +#define PIN_TRIM3_DN GPIO_Pin_3 //PE.03 +#define PIN_TRIM4_UP GPIO_Pin_6 //PE.06 +#define PIN_TRIM4_DN GPIO_Pin_5 //PE.05 + +//Switch +#define PIN_SW_A_L GPIO_Pin_14 //PE.14 +#define PIN_SW_B_H GPIO_Pin_3 //PB.03 +#define PIN_SW_B_L GPIO_Pin_4 //PB.04 +#define PIN_SW_C_H GPIO_Pin_5 //PB.05 +#define PIN_SW_C_L GPIO_Pin_6 //PB.06 +#define PIN_SW_D_H GPIO_Pin_7 //PB.07 +#define PIN_SW_D_L GPIO_Pin_2 //PE.02 +#define PIN_SW_E_H GPIO_Pin_0 //PB.00 +#define PIN_SW_E_L GPIO_Pin_5 //PA.05 +#define PIN_SW_F_H GPIO_Pin_7 //PE.07 +#define PIN_SW_F_L GPIO_Pin_1 //PB.01 +#define PIN_SW_G_H GPIO_Pin_9 //PE.09 +#define PIN_SW_G_L GPIO_Pin_8 //PE.08 +#define PIN_SW_H_L GPIO_Pin_13 //PE.13 + +//ADC---8个 +#define PIN_STK_J1 GPIO_Pin_0 //PA.00 +#define PIN_STK_J2 GPIO_Pin_1 //PA.01 +#define PIN_STK_J3 GPIO_Pin_2 //PA.02 +#define PIN_STK_J4 GPIO_Pin_3 //PA.03 +#define PIN_SLD_J1 GPIO_Pin_4 //PC.04 +#define PIN_SLD_J2 GPIO_Pin_5 //PC.05 +#define PIN_FLP_J1 GPIO_Pin_6 //PA.06 +#define PIN_FLP_J2 GPIO_Pin_7 //PA.07 +#define PIN_MVOLT GPIO_Pin_0 //PC.00 +#define RCC_AHB1Periph_GPIOADC RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC + +//DAC---1个 +#define PIN_AUDIO_DAC GPIO_Pin_4 //PA.04 + +//Power_OFF Delay and LED +#define PIN_PWR_LED GPIO_Pin_6 //PC.06 +#define PIN_PWR_STATUS GPIO_Pin_1 //PD.01 +#define PIN_MCU_PWR GPIO_Pin_0 //PD.00 +#define RCC_AHB1Periph_GPIOPWR RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD +#define GPIOPWRLED GPIOC +#define GPIOPWR GPIOD + +//Smart-Port +#define PIN_SPORT_ON GPIO_Pin_4 //PD.04 +#define PIN_SPORT_TX GPIO_Pin_5 //PD.05 +#define PIN_SPORT_RX GPIO_Pin_6 //PD.06 + +//Trainer Port +#define PIN_TR_PPM_IN GPIO_Pin_8 //PC.08 +#define PIN_TR_PPM_OUT GPIO_Pin_9 //PC.09 + +//Cppm +#define RCC_AHB1Periph_GPIOCPPM RCC_AHB1Periph_GPIOA +#define PIN_CPPM_OUT GPIO_Pin_8 //PA.08 +#define GPIOCPPM GPIOA +#define GPIO_PinSource_CPPM GPIO_PinSource8 +//Heart Beat +#define PIN_HEART_BEAT GPIO_Pin_7 //PC.07 + +//Update UART----RS232 ---UART3 +#define PIN_UPDATE_UART_TX GPIO_Pin_10 //PB.10 +#define PIN_UPDATE_UART_RX GPIO_Pin_11 //PB.11 + +//USB_OTG +#define PIN_FS_VBUS GPIO_Pin_9 //PA.09 +#define PIN_FS_ID GPIO_Pin_10 //PA.10 +#define PIN_FS_DM GPIO_Pin_11 //PA.11 +#define PIN_FS_DP GPIO_Pin_12 //PA.12 + +//BackLight PB8 +#define RCC_AHB1Periph_GPIOBL RCC_AHB1Periph_GPIOB +#define GPIO_Pin_BL GPIO_Pin_8 //PB.08 +#define GPIOBL GPIOB +#define GPIO_PinSource_BL GPIO_PinSource8 + +//LCD GPIOD 10-14 模拟spi +#define RCC_AHB1Periph_LCD RCC_AHB1Periph_GPIOD +#define GPIO_LCD GPIOD +#define PIN_LCD_MOSI GPIO_Pin_10 //PD.10 +#define PIN_LCD_CLK GPIO_Pin_11 //PD.11 +#define PIN_LCD_NCS GPIO_Pin_14 //PD.14 +#define PIN_LCD_A0 GPIO_Pin_13 //PD.13 +#define PIN_LCD_RST //GPIO_Pin_12 //pd12 test //RESET occurs when powered up,but should delay before initialize + +//Audio----I2S3 +//#define CODEC_I2S_ADDRESS 0x4000380C +#define CODEC_I2S SPI3 +#define CODEC_I2S_CLK RCC_APB1Periph_SPI3 +#define CODEC_I2S_GPIO_AF GPIO_AF_SPI3 +#define CODEC_I2S_IRQ SPI3_IRQn +#define CODEC_I2S_GPIO_CLOCK (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC )//| RCC_AHB1Periph_GPIOE) +#define CODEC_I2S_WS_PIN GPIO_Pin_15 //PA.15 +#define CODEC_I2S_SCK_PIN GPIO_Pin_10 //PC.10 +#define CODEC_I2S_SD_PIN GPIO_Pin_12 //PC.12 +#define CODEC_I2S_MCK_PIN GPIO_Pin_6 //DISABLED +#define CODEC_I2S_WS_PINSRC GPIO_PinSource15 +#define CODEC_I2S_SCK_PINSRC GPIO_PinSource10 +#define CODEC_I2S_SD_PINSRC GPIO_PinSource12 +#define CODEC_I2S_MCK_PINSRC GPIO_PinSource6 +#define CODEC_I2S_GPIO GPIOC +#define CODEC_I2S_MCK_GPIO GPIOC +#define CODEC_I2S_WS_GPIO GPIOA +#define CODEC_I2S_MUTE GPIO_Pin_11 //PC.11 +//#define CODEC_I2S_FLT GPIO_Pin_ //IIR/FIR +//#define CODEC_I2S_MODE GPIO_Pin_ //Connect to GND=I2S_STANDARD + +//Eeprom与cat5137 +#define I2C_EE_GPIO GPIOE +#define I2C_EE_WP_GPIO GPIOB +#define I2C_EE_GPIO_CLK RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOE +#define I2C_EE_SCL GPIO_Pin_1 //PE1 +#define I2C_EE_SDA GPIO_Pin_0 //PE0 +#define I2C_EE_WP GPIO_Pin_9 //PB9 + +//SD卡---spi2 +#define SPI_SD SPI2 +#define GPIO_AF_SD GPIO_AF_SPI2 +#define RCC_AHB1Periph_GPIO_CS RCC_AHB1Periph_GPIOB +#define GPIO_SPI_SD GPIOB +#define GPIO_Pin_SPI_SD_CS GPIO_Pin_12 //PB.12 +#define GPIO_Pin_SPI_SD_SCK GPIO_Pin_13 //PB.13 +#define GPIO_Pin_SPI_SD_MISO GPIO_Pin_14 //PB.14 +#define GPIO_Pin_SPI_SD_MOSI GPIO_Pin_15 //PB.15 +#define GPIO_PinSource_CS GPIO_PinSource12 +#define GPIO_PinSource_SCK GPIO_PinSource13 +#define GPIO_PinSource_MISO GPIO_PinSource14 +#define GPIO_PinSource_MOSI GPIO_PinSource15 +#define RCC_APBPeriphClockCmd_SPI_SD RCC_APB1PeriphClockCmd +#define RCC_APBPeriph_SPI_SD RCC_APB1Periph_SPI2 +#define RCC_AHBxPeriph_GPIO_WP RCC_AHB1Periph_GPIOD +#define RCC_AHBxPeriph_GPIO_CP RCC_AHB1Periph_GPIOD +#define GPIO_Mode_WP GPIO_Mode_OUT//lock? +#define GPIO_Mode_CP GPIO_Mode_IN // +#define GPIO_Pin_WP GPIO_Pin_8 //PD.08 +#define GPIO_Pin_CP GPIO_Pin_9 //PD.09 +#define GPIO_CTL_SD GPIOD +/***************************************************************************** +************************************************************************** +*******************************************************************************/ + +//其他接口涉及的可修改的宏定义 +/****************************** +lcd用 +**************************************/ +#define HIGHT (64) +#define WIDTH (212) + +/***************************************** +Audio----I2S3-----SPI3 +***************************************************************/ +//#define CODEC_MCLK_ENABLED +#define CODEC_MCLK_DISABLED +#define CODEC_USE_INT +//#define CODEC_USE_DMA +#define AudioFreq I2S_AudioFreq_44k +/************************************************* +模拟I2C---EEPROM and CAT5137共用 +********************************************************/ +#define EE_M24C08 /* Support the device: M24C08. */ +//#define EE_M24C64_32 /* Support the devices: M24C32 and M24C64 */ +#define I2C_Speed 200000 + +#if defined (EE_M24C08) + #define I2C_FLASH_PAGESIZE (16) +#elif defined (EE_M24C64_32) + #define I2C_FLASH_PAGESIZE (32) +#endif + +#ifdef EE_M24C64_32 + #define EEPROM_HW_ADDRESS 0xA0 /* E0 = E1 = E2 = 0 */ +#elif defined (EE_M24C08) +//#define EEPROM_Block0_ADDRESS 0xA0 /* 000*/ +#define EEPROM_Block1_ADDRESS 0xA2 /* E3 E2 E1= 001 */ +//#define EEPROM_Block2_ADDRESS 0xA4 /* 010 */ +//#define EEPROM_Block3_ADDRESS 0xA6 /* 011 */ +#endif + +#define USE_CAT5137 /*Support the Volume Control*/ + +#ifdef USE_CAT5137 +#define I2C_CAT5137_ADDRESS 0x5C//0101110 +#endif + + +/***************************************** +SD card----SPI2 +***************************************************************/ +// demo uses a command line option to define this (see Makefile): +// #define STM32_SD_USE_DMA +#ifdef STM32_SD_USE_DMA +// #warning "Information only: using DMA" +#pragma message "*** Using DMA ***" +#endif +/* set to 1 to provide a disk_ioctrl function even if not needed by the FatFs */ +#define STM32_SD_DISK_IOCTRL_FORCE (0) + +#define CARD_SUPPLY_SWITCHABLE (0) //0，power on not depend any IO +#define SOCKET_WP_CONNECTED (0) +#define SOCKET_CP_CONNECTED (0) + +#define SPI_BaudRatePrescaler_SPI_SD SPI_BaudRatePrescaler_4 // - for SPI1 and full-speed APB2: 60MHz/4 =15MHZ < 20MHZ + +//selectable +//DMA相关未作修改 +#define DMA_Channel_SPI_SD_RX DMA1_Channel2 +#define DMA_Channel_SPI_SD_TX DMA1_Channel3 +#define DMA_FLAG_SPI_SD_TC_RX DMA1_FLAG_TC2 +#define DMA_FLAG_SPI_SD_TC_TX DMA1_FLAG_TC3 + +/****************************************** + +***************************************************************/ + + + + + + + + + + + + + + + + + + + +#endif \ No newline at end of file diff --git a/src/x9d/i2c_ee.c b/src/x9d/i2c_ee.c new file mode 100644 index 000000000..6fb1111a8 --- /dev/null +++ b/src/x9d/i2c_ee.c @@ -0,0 +1,426 @@ +/** + ****************************************************************************** + * @file Project/ee_drivers/i2c_ee.c + * @author X9D Application Team + * @version V 0.2 + * @date 12-JULY-2012 + * @brief This file provides a set of functions needed to manage the + * communication between I2C peripheral and I2C M24CXX EEPROM. + CAT5137 added,share the I2C. + ****************************************************************************** +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "i2c_ee.h" +#include "hal.h" +#include "Macro_define.h" + + + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +uint16_t EEPROM_ADDRESS; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Configure the used I/O ports pin + * @param None + * @retval None + */ +static +void I2C_GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + GPIOB->BSRRH =I2C_EE_WP; //PB9 + GPIO_InitStructure.GPIO_Pin = I2C_EE_WP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(I2C_EE_WP_GPIO, &GPIO_InitStructure); + + /* Configure I2C_EE pins: SCL and SDA */ + GPIO_InitStructure.GPIO_Pin = I2C_EE_SCL | I2C_EE_SDA;//PE0,PE1 + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(I2C_EE_GPIO, &GPIO_InitStructure); +} + +/** + * @brief I2C Configuration + * @param None + * @retval None + */ +//when use harware I2C +void I2C_Configuration(void) +{ +} + + +short I2C_START() +{ + SDA_H; I2C_delay(); + SCL_H; I2C_delay(); + //if(!SDA_read)return 0; //SDA线为低电平则总线忙,退出 + SDA_L; I2C_delay(); + //if(SDA_read) return 0; //SDA线为高电平则总线出错,退出 + SCL_L; I2C_delay(); + return 1; +} + +void I2C_STOP() +{ + SCL_L; I2C_delay(); + SDA_L; I2C_delay(); + SCL_H; I2C_delay(); + SDA_H; I2C_delay(); +} + +void I2C_ACK() +{ + SCL_L; I2C_delay(); + SDA_L; I2C_delay(); + SCL_H; I2C_delay(); + SCL_L; I2C_delay(); +} +void I2C_NO_ACK() +{ + SCL_L; I2C_delay(); + SDA_H; I2C_delay(); + SCL_H; I2C_delay(); + SCL_L; I2C_delay(); +} +short I2C_WAIT_ACK() //返回为:=1有ACK,=0无ACK +{ + short i=50; + SCL_L; I2C_delay(); + SDA_H; I2C_delay(); + SCL_H; I2C_delay(); + while(i){ + if(SDA_read) + { + I2C_delay(); + i--; + }else{ + i=2; + break; + } + } + SCL_L; I2C_delay(); + + return i; +} + +void I2C_SEND_DATA(char SendByte) +{ + short i=8; + while(i--) + { + SCL_L; I2C_delay(); + if(SendByte&0x80) + SDA_H; + else + SDA_L; + SendByte<<=1; I2C_delay(); + SCL_H; I2C_delay(); + } + SCL_L; I2C_delay(); +} +char I2C_READ() //数据从高位到低位// +{ + short i=8; + char ReceiveByte=0; + + SDA_H; + while(i--) + { + ReceiveByte<<=1; + SCL_L; I2C_delay(); + SCL_H; I2C_delay(); + if(SDA_read) + { + ReceiveByte|=0x01; + } + } + SCL_L; + return ReceiveByte; +} + + + + +void I2C_EE_Init() +{ + /* GPIO Periph clock enable */ + RCC_AHB1PeriphClockCmd(I2C_EE_GPIO_CLK, ENABLE); + + /* GPIO configuration */ + I2C_GPIO_Configuration(); + +#if defined (EE_M24C64_32) + /* Select the EEPROM address according to the state of E0, E1, E2 pins */ + EEPROM_ADDRESS = EEPROM_HW_ADDRESS; +#elif defined (EE_M24C08) + /* depending on the EEPROM Address selected in the i2c_ee.h file */ + #ifdef EEPROM_Block0_ADDRESS + /* Select the EEPROM Block0 to write on */ + EEPROM_ADDRESS = EEPROM_Block0_ADDRESS; + #endif + + #ifdef EEPROM_Block1_ADDRESS + /* Select the EEPROM Block1 to write on */ + EEPROM_ADDRESS = EEPROM_Block1_ADDRESS; + #endif + + #ifdef EEPROM_Block2_ADDRESS + /* Select the EEPROM Block2 to write on */ + EEPROM_ADDRESS = EEPROM_Block2_ADDRESS; + #endif + + #ifdef EEPROM_Block3_ADDRESS + /* Select the EEPROM Block3 to write on */ + EEPROM_ADDRESS = EEPROM_Block3_ADDRESS; + #endif +#endif /* EE_M24C64_32 */ + +} + + +/** + * @brief Writes one byte to the I2C EEPROM. + * @param pBuffer : pointer to the buffer containing the data to be + * written to the EEPROM. + * @param WriteAddr : EEPROM's internal address to write to. + * @retval None + */ +void I2C_EE_ByteWrite(uint8_t* pBuffer, uint16_t WriteAddr) +{ + I2C_START(); + I2C_SEND_DATA(EEPROM_ADDRESS | EE_CMD_WRITE); + I2C_WAIT_ACK(); +#ifdef EE_M24C08 + I2C_SEND_DATA(WriteAddr); + I2C_WAIT_ACK(); +#elif defined(EE_M24C64_32) + I2C_SEND_DATA((uint8_t)((WriteAddr&0xFF00)>>8) ); + I2C_WAIT_ACK(); + I2C_SEND_DATA((uint8_t)(WriteAddr&0xFF)); + I2C_WAIT_ACK(); +#endif + I2C_SEND_DATA(*pBuffer); + I2C_WAIT_ACK(); + I2C_STOP(); +} + +/** + * @brief Reads a block of data from the EEPROM. + * @param pBuffer : pointer to the buffer that receives the data read + * from the EEPROM. + * @param ReadAddr : EEPROM's internal address to read from. + * @param NumByteToRead : number of bytes to read from the EEPROM. + * @retval None + */ +void I2C_EE_BufferRead(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t NumByteToRead) +{ + I2C_START(); + I2C_SEND_DATA(EEPROM_ADDRESS |EE_CMD_WRITE); + I2C_WAIT_ACK(); + +#ifdef EE_M24C08 + I2C_SEND_DATA(ReadAddr); + I2C_WAIT_ACK(); +#elif defined(EE_M24C64_32) + I2C_SEND_DATA((uint8_t)((ReadAddr & 0xFF00) >> 8)); + I2C_WAIT_ACK(); + I2C_SEND_DATA((uint8_t)(ReadAddr & 0x00FF)); + I2C_WAIT_ACK(); +#endif + I2C_STOP(); + + I2C_START(); + I2C_SEND_DATA(EEPROM_ADDRESS | EE_CMD_READ); + I2C_WAIT_ACK(); + while(NumByteToRead) + { + if(NumByteToRead ==1){ + *pBuffer =I2C_READ(); + I2C_NO_ACK(); + I2C_STOP(); + }else{ + *pBuffer =I2C_READ(); + I2C_ACK(); + pBuffer++; + } + NumByteToRead--; + } +} + +/** + * @brief Writes buffer of data to the I2C EEPROM. + * @param pBuffer : pointer to the buffer containing the data to be + * written to the EEPROM. + * @param WriteAddr : EEPROM's internal address to write to. + * @param NumByteToWrite : number of bytes to write to the EEPROM. + * @retval None + */ +//整页的整页写 其他多字节写 +void I2C_EE_BufferWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite) +{ + uint8_t NumOfPage = 0, NumOfSingle = 0, count = 0; + uint16_t Addr = 0; + + Addr = WriteAddr % I2C_FLASH_PAGESIZE; + count = I2C_FLASH_PAGESIZE - Addr; + NumOfPage = NumByteToWrite / I2C_FLASH_PAGESIZE; + NumOfSingle = NumByteToWrite % I2C_FLASH_PAGESIZE; + + /* If WriteAddr is I2C_FLASH_PAGESIZE aligned */ + if(Addr == 0) + { + /* If NumByteToWrite < I2C_FLASH_PAGESIZE */ + if(NumOfPage == 0) + { + I2C_EE_PageWrite(pBuffer, WriteAddr, NumOfSingle); + I2C_EE_WaitEepromStandbyState(); + } + /* If NumByteToWrite > I2C_FLASH_PAGESIZE */ + else + { + while(NumOfPage--) + { + I2C_EE_PageWrite(pBuffer, WriteAddr, I2C_FLASH_PAGESIZE); + I2C_EE_WaitEepromStandbyState(); + WriteAddr += I2C_FLASH_PAGESIZE; + pBuffer += I2C_FLASH_PAGESIZE; + } + + if(NumOfSingle!=0) + { + I2C_EE_PageWrite(pBuffer, WriteAddr, NumOfSingle); + I2C_EE_WaitEepromStandbyState(); + } + } + } + /* If WriteAddr is not I2C_FLASH_PAGESIZE aligned */ + else + { + /* If NumByteToWrite < I2C_FLASH_PAGESIZE */ + if(NumOfPage== 0) + { + /* If the number of data to be written is more than the remaining space + in the current page: */ + if (NumByteToWrite > count) + { + /* Write the data conained in same page */ + I2C_EE_PageWrite(pBuffer, WriteAddr, count); + I2C_EE_WaitEepromStandbyState(); + + /* Write the remaining data in the following page */ + I2C_EE_PageWrite((uint8_t*)(pBuffer + count), (WriteAddr + count), (NumByteToWrite - count)); + I2C_EE_WaitEepromStandbyState(); + } + else + { + I2C_EE_PageWrite(pBuffer, WriteAddr, NumOfSingle); + I2C_EE_WaitEepromStandbyState(); + } + } + /* If NumByteToWrite > I2C_FLASH_PAGESIZE */ + else + { + NumByteToWrite -= count; + NumOfPage = NumByteToWrite / I2C_FLASH_PAGESIZE; + NumOfSingle = NumByteToWrite % I2C_FLASH_PAGESIZE; + + if(count != 0) + { + I2C_EE_PageWrite(pBuffer, WriteAddr, count); + I2C_EE_WaitEepromStandbyState(); + WriteAddr += count; + pBuffer += count; + } + + while(NumOfPage--) + { + I2C_EE_PageWrite(pBuffer, WriteAddr, I2C_FLASH_PAGESIZE); + I2C_EE_WaitEepromStandbyState(); + WriteAddr += I2C_FLASH_PAGESIZE; + pBuffer += I2C_FLASH_PAGESIZE; + } + if(NumOfSingle != 0) + { + I2C_EE_PageWrite(pBuffer, WriteAddr, NumOfSingle); + I2C_EE_WaitEepromStandbyState(); + } + } + } + //I2C_EE_WaitEepromStandbyState(); +} + +/** + * @brief Writes more than one byte to the EEPROM with a single WRITE cycle. + * @note The number of byte can't exceed the EEPROM page size. + * @param pBuffer : pointer to the buffer containing the data to be + * written to the EEPROM. + * @param WriteAddr : EEPROM's internal address to write to. + * @param NumByteToWrite : number of bytes to write to the EEPROM. + * @retval None + */ +void I2C_EE_PageWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t NumByteToWrite) +{ + I2C_START(); + I2C_SEND_DATA(EEPROM_ADDRESS|EE_CMD_WRITE); + I2C_WAIT_ACK(); + +#ifdef EE_M24C08 + I2C_SEND_DATA(WriteAddr); + I2C_WAIT_ACK(); +#elif defined(EE_M24C64_32) + I2C_SEND_DATA((uint8_t)((WriteAddr & 0xFF00) >> 8)); + I2C_WAIT_ACK(); + I2C_SEND_DATA((uint8_t)(WriteAddr & 0x00FF)); + I2C_WAIT_ACK(); +#endif /* EE_M24C08 */ + + /* While there is data to be written */ + while(NumByteToWrite--) + { + I2C_SEND_DATA(*pBuffer); + I2C_WAIT_ACK(); + pBuffer++; + } + I2C_STOP(); +} + +/** + * @brief Wait for EEPROM Standby state + * @param None + * @retval None + */ +void I2C_EE_WaitEepromStandbyState(void) +{ + /*__IO*/ volatile uint16_t SR1_Tmp = 0; + + do + { + I2C_START(); + I2C_SEND_DATA(EEPROM_ADDRESS|EE_CMD_WRITE); + + }while(0== I2C_WAIT_ACK()); + I2C_STOP(); + +} + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/i2c_ee.h b/src/x9d/i2c_ee.h new file mode 100644 index 000000000..833ef931e --- /dev/null +++ b/src/x9d/i2c_ee.h @@ -0,0 +1,56 @@ +/** + ****************************************************************************** + * @file Project/ee_drivers/i2c_ee.h + * @author X9D Application Team + * @version V 0.2 + * @date 12-JLY-2012 + * @brief Header for i2c_ee.c module + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __I2C_EE_H +#define __I2C_EE_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm32f2xx_conf.h" +#include "stdint.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + + +#define EE_CMD_WRITE (0) +#define EE_CMD_READ (1) +#define I2C_delay() do{delayUsec(5);}while(0) + +#define SCL_H do{GPIOB->BSRRL = I2C_EE_SCL;}while(0) +#define SCL_L do{GPIOB->BSRRH = I2C_EE_SCL;}while(0) +#define SDA_H do{GPIOB->BSRRL = I2C_EE_SDA;}while(0) +#define SDA_L do{GPIOB->BSRRH = I2C_EE_SDA;}while(0) +#define SCL_read (GPIOB->IDR & I2C_EE_SCL) +#define SDA_read (GPIOB->IDR & I2C_EE_SDA) + +/* Exported functions ------------------------------------------------------- */ +void I2C_EE_Init(void); +void I2C_EE_ByteWrite(uint8_t* pBuffer, uint16_t WriteAddr); +void I2C_EE_PageWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t NumByteToWrite); +void I2C_EE_BufferWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite); +void I2C_EE_BufferRead(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t NumByteToRead); +void I2C_EE_WaitEepromStandbyState(void); + +#endif /* __I2C_EE_H */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ + diff --git a/src/x9d/lcd_driver.cpp b/src/x9d/lcd_driver.cpp new file mode 100644 index 000000000..dfed4a421 --- /dev/null +++ b/src/x9d/lcd_driver.cpp @@ -0,0 +1,197 @@ +/** + ****************************************************************************** + * @file Project/lcd/lcd.c + * @author X9D Application Team + * @Hardware version V0.2 + * @date 11-July-2012 + * @brief This file provides LCD Init and botom drivers. + * * + ****************************************************************************** +*/ +#include +#include "lcd.h" +#include "spi.h" +#include "hal.h" +#include "Macro_define.h" + +#define WriteData(x) AspiData(x) +#define WriteCommand(x) AspiCmd(x) + +void Set_Address(u8 x, u8 y) +{ + WriteCommand(x&0x0F); //Set Column Address LSB CA[3:0] + WriteCommand((x>>4)|0x10); //Set Column Address MSB CA[7:4] + + WriteCommand((y&0x0F)|0x60); //Set Row Address LSB RA [3:0] + WriteCommand(((y>>4)&0x0F)|0x70); //Set Row Address MSB RA [7:4] +} + +/**6 ponits in one line share the same address,3 bytes in the buffer. +3 bytes wrote in one time */ +void refreshDisplay() +{ + u8 _x1,_x0,temp_x0,temp_x00; + + _x1 =( DISPLAY_W>>1) + 1; + + temp_x0 = 0; + temp_x00 = temp_x0/3; + + for(uint32_t y0=0; y0<=y1; y0++) + { + Set_Address(0, y0);//change the address every column + AspiCmd(0xAF); + for(uint_32_t x=0; x_x0<=_x1; _x0++) + { + WriteData(lcd_buffer[_x0][y0]); + //WriteData(lcd_buffer[_x0][y0]); + //WriteData(lcd_buffer[_x0][y0]); + } + } +} + +/**Init the Backlight GPIO */ +static void LCD_BL_Config() +{ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOBL, ENABLE); + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin =GPIO_Pin_BL; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOBL, &GPIO_InitStructure); +} + +/** Init the anolog spi gpio +*/ +static void LCD_Hardware_Init() +{ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_LCD, ENABLE); + + GPIO_InitTypeDef GPIO_InitStructure; + + /*!< Configure lcd CLK\ MOSI\ A0pin in output pushpull mode *************/ + GPIO_InitStructure.GPIO_Pin =PIN_LCD_MOSI | PIN_LCD_CLK | PIN_LCD_A0; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIO_LCD, &GPIO_InitStructure); + + /*!< Configure lcd NCS pin in output pushpull mode ,PULLUP *************/ + GPIO_InitStructure.GPIO_Pin = PIN_LCD_NCS; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + + GPIO_Init(GPIO_LCD, &GPIO_InitStructure); +} + +#if 0 +void Delay(uint32_t ms); +/* Initialize the LCD */ +#endif + +static void LCD_Init() +{ + /*Hardware Reset need delay*/ + /*LCD_RST_LOW(); + Delay(50); + LCD_RST_HIGH();*/ + + AspiCmd(0x25); //Temperature compensation curve definition: 0x25 = -0.05%/oC + AspiCmd(0x2b); //Panel loading set ,Internal VLCD. + AspiCmd(0xEA); //set bias=1/10 :Command table NO.27 + AspiCmd(0x81); //Set Vop + AspiCmd(50); //0--255 + AspiCmd(0xA6); //inverse display off + AspiCmd(0xD1); //SET RGB:Command table NO.21 .SET RGB or BGR. D1=RGB + AspiCmd(0xD5); //set color mode 4K and 12bits :Command table NO.22 + AspiCmd(0xA0); //line rates,25.2 Klps + AspiCmd(0xC8); //SET N-LINE INVERSION + AspiCmd(0x00); //Disable NIV + AspiCmd(0xF1); //Set CEN + AspiCmd(0x3F); // 1/64DUTY + AspiCmd(0x84); //Disable Partial Display + AspiCmd(0xC4); //MY=1,MX=0 + AspiCmd(0x89); //WA=1,column (CA) increment (+1) first until CA reaches CA boundary, then RA will increment by (+1). + + AspiCmd(0xF8); //Set Window Program Enable ,inside modle + AspiCmd(0xF4); //starting column address of RAM program window. + AspiCmd(0x00); + AspiCmd(0xF5); //starting row address of RAM program window. + AspiCmd(0x60); + AspiCmd(0xF6); //ending column address of RAM program window. + AspiCmd(0x47); + AspiCmd(0xF7); //ending row address of RAM program window. + AspiCmd(0x9F); + + AspiCmd(0xAF); //dc2=1,IC into exit SLEEP MODE, dc3=1 gray=ON 开灰阶 ,dc4=1 Green Enhanc mode disabled 绿色增强模式关 + +} + +void lcd_init() +{ + LCD_BL_Config(); + LCD_Hardware_Init(); + LCD_Init(); +} + +#if 0 +/*************************************************************** +***********FOR Test +**********************************************************************/ +void Delay(uint32_t ms) +{ + u8 i; + while(ms != 0) + { + for(i=0;i<250;i++) {} + for(i=0;i<75;i++) {} + ms--; + } +} + + +void TEST_LCD() +{ + //static u32 cnt; + //CC中断 + GPIO_SetBits(GPIOB,GPIO_Pin_8);//BACKLIGHT + + //Delay(3000); + //paintScreen(); + clearScreen(); + drawPoint(0,0,1); + paintRect(0,0,0,0); + reversePoint(0,0); + paintRect(0,0,0,0); + Delay(3000); + drawPoint(1,0,1); + paintRect(0,0,1,0); + Delay(3000); + reversePoint(1,0); + paintRect(0,0,1,0); + Delay(3000); + drawPoint(0,1,1); + paintRect(0,1,0,1); + Delay(3000); + reversePoint(0,1); + paintRect(0,1,0,1); + + drawPoint(211,0,1); + paintRect(0,0,211,0); + Delay(3000); + reversePoint(211,0); + paintRect(0,0,211,0); + + drawPoint(211,63,1); + paintRect(211,63,211,63); + Delay(3000); + reversePoint(211,63); + paintRect(211,63,211,63); + +} +#endif diff --git a/src/x9d/main.c b/src/x9d/main.c new file mode 100644 index 000000000..0bc3c08e6 --- /dev/null +++ b/src/x9d/main.c @@ -0,0 +1,62 @@ +/** + ****************************************************************************** + * @file Project/main.c + * @author X9D Application Team + * @Hardware version V0.2 + * @date 11-July-2012 + * @brief This file provides the main fuction. + * * + ****************************************************************************** +*/ +#include "stm32f2xx.h" +#include "intrinsics.h" +#include "stdint.h" +#include "stdio.h" +#include "SYS_NVIC.h" +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +#include "lcd.h" +#include "gui_tsk.h" +#include "item.h" +#include "Audio.h" +#include "sys_man.h" +#include "Macro_define.h" + +#ifdef I2C_TEST +#include "i2c_ee.h" + +#endif + +#ifdef ADC_TEST +#include "adc.h" +#endif + + + + +int main() +{ + + Delay(10000); //delay 200+ ms +#ifdef DEBUG + debug(); +#endif + __disable_interrupt(); + +/*HCLK=120M,SYSCLK=120M,PCLK1=30M,PCLK2=60M,SO APB1=60M(div=4),APB2=120M(div=2)*/ + + RCC_ClocksTypeDef RCC_Clocks; + RCC_GetClocksFreq(&RCC_Clocks);//add to watch to see the values + +//clock init ok ,other peripherals init code; + + __enable_interrupt(); + + while(1) + { + } + //return 0; +} + diff --git a/src/x9d/pwr_ctrl.c b/src/x9d/pwr_ctrl.c new file mode 100644 index 000000000..1b8348637 --- /dev/null +++ b/src/x9d/pwr_ctrl.c @@ -0,0 +1,50 @@ +#include "hal.h" +#include "stm32f2xx.h" +#include "pwr_ctrl.h" + +void pwr_ctrl_down() +{ + GPIO_SetBits(GPIOPWR,PIN_MCU_PWR); + //ee_save_data(); + GPIO_ResetBits(GPIOPWR,PIN_MCU_PWR); +} + +void pwr_ctrl_on() +{ + +} + +void check_pwr() //定时抑或中断，再测试 +{ + if( GPIO_ReadInputDataBit(GPIOPWR,PIN_PWR_STATUS) == Bit_RESET) + { + pwr_ctrl_down(); + } +} + + +void pwr_io_init() +{ + GPIO_InitTypeDef GPIO_InitStructure; + /* GPIOC GPIOD clock enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOPWR, ENABLE); + + /* GPIO Configuration*/ + GPIO_InitStructure.GPIO_Pin = PIN_MCU_PWR | PIN_PWR_ON; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; + GPIO_Init(GPIOPWR, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = PIN_PWR_STATUS; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_Init(GPIOPWR, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = PIN_PWR_LED; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; + GPIO_Init(GPIOPWRLED, &GPIO_InitStructure); +} diff --git a/src/x9d/pwr_ctrl.h b/src/x9d/pwr_ctrl.h new file mode 100644 index 000000000..6f2663dde --- /dev/null +++ b/src/x9d/pwr_ctrl.h @@ -0,0 +1,7 @@ +#ifndef _PWR_CTRL_H_ +#define _PWR_CTRL_H_ + + + + +#endif \ No newline at end of file diff --git a/src/x9d/rtc.c b/src/x9d/rtc.c new file mode 100644 index 000000000..be8279184 --- /dev/null +++ b/src/x9d/rtc.c @@ -0,0 +1,282 @@ +/*-------------------------------------------------------------------------- */ +/* RTC controls for STM32 */ +/* Copyright (c) 2009, Martin Thomas 4/2009, 3BSD-license */ +/* partly based on code from STMircoelectronics, Peter Dannegger, "LaLaDumm" */ +/*-------------------------------------------------------------------------- */ + +#include +#include "stm32f10x.h" +#include "rtc.h" + +#define FIRSTYEAR 2000 // start year +#define FIRSTDAY 6 // 0 = Sunday + +static const uint8_t DaysInMonth[] = { 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; + +/******************************************************************************* +* Function Name : isDST +* Description : checks if given time is in Daylight Saving time-span. +* Input : time-struct, must be fully populated including weekday +* Output : none +* Return : false: no DST ("winter"), true: in DST ("summer") +* DST according to German standard +* Based on code from Peter Dannegger found in the microcontroller.net forum. +*******************************************************************************/ +static bool isDST( const RTC_t *t ) +{ + uint8_t wday, month; // locals for faster access + + month = t->month; + + if( month < 3 || month > 10 ) { // month 1, 2, 11, 12 + return false; // -> Winter + } + + wday = t->wday; + + if( t->mday - wday >= 25 && (wday || t->hour >= 2) ) { // after last Sunday 2:00 + if( month == 10 ) { // October -> Winter + return false; + } + } else { // before last Sunday 2:00 + if( month == 3 ) { // March -> Winter + return false; + } + } + + return true; +} + +/******************************************************************************* +* Function Name : adjustDST +* Description : adjusts time to DST if needed +* Input : non DST time-struct, must be fully populated including weekday +* Output : time-stuct gets modified +* Return : false: no DST ("winter"), true: in DST ("summer") +* DST according to German standard +* Based on code from Peter Dannegger found in the mikrocontroller.net forum. +*******************************************************************************/ +static bool adjustDST( RTC_t *t ) +{ + uint8_t hour, day, wday, month; // locals for faster access + + hour = t->hour; + day = t->mday; + wday = t->wday; + month = t->month; + + if ( isDST(t) ) { + t->dst = 1; + hour++; // add one hour + if( hour == 24 ){ // next day + hour = 0; + wday++; // next weekday + if( wday == 7 ) { + wday = 0; + } + if( day == DaysInMonth[month-1] ) { // next month + day = 0; + month++; + } + day++; + } + t->month = month; + t->hour = hour; + t->mday = day; + t->wday = wday; + return true; + } else { + t->dst = 0; + return false; + } +} + +/******************************************************************************* +* Function Name : counter_to_struct +* Description : populates time-struct based on counter-value +* Input : - counter-value (unit seconds, 0 -> 1.1.2000 00:00:00), +* - Pointer to time-struct +* Output : time-struct gets populated, DST not taken into account here +* Return : none +* Based on code from Peter Dannegger found in the mikrocontroller.net forum. +*******************************************************************************/ +static void counter_to_struct( uint32_t sec, RTC_t *t ) +{ + uint16_t day; + uint8_t year; + uint16_t dayofyear; + uint8_t leap400; + uint8_t month; + + t->sec = sec % 60; + sec /= 60; + t->min = sec % 60; + sec /= 60; + t->hour = sec % 24; + day = (uint16_t)(sec / 24); + + t->wday = (day + FIRSTDAY) % 7; // weekday + + year = FIRSTYEAR % 100; // 0..99 + leap400 = 4 - ((FIRSTYEAR - 1) / 100 & 3); // 4, 3, 2, 1 + + for(;;) { + dayofyear = 365; + if( (year & 3) == 0 ) { + dayofyear = 366; // leap year + if( year == 0 || year == 100 || year == 200 ) { // 100 year exception + if( --leap400 ) { // 400 year exception + dayofyear = 365; + } + } + } + if( day < dayofyear ) { + break; + } + day -= dayofyear; + year++; // 00..136 / 99..235 + } + t->year = year + FIRSTYEAR / 100 * 100; // + century + + if( dayofyear & 1 && day > 58 ) { // no leap year and after 28.2. + day++; // skip 29.2. + } + + for( month = 1; day >= DaysInMonth[month-1]; month++ ) { + day -= DaysInMonth[month-1]; + } + + t->month = month; // 1..12 + t->mday = day + 1; // 1..31 +} + +/******************************************************************************* +* Function Name : struct_to_counter +* Description : calculates second-counter from populated time-struct +* Input : Pointer to time-struct +* Output : none +* Return : counter-value (unit seconds, 0 -> 1.1.2000 00:00:00), +* Based on code from "LalaDumm" found in the mikrocontroller.net forum. +*******************************************************************************/ +static uint32_t struct_to_counter( const RTC_t *t ) +{ + uint16_t i; + uint32_t result = 0; + uint16_t idx, year; + + year = t->year; + + /* Calculate days of years before */ + result = (uint32_t)year * 365; + if (t->year >= 1) { + result += (year + 3) / 4; + result -= (year - 1) / 100; + result += (year - 1) / 400; + } + + /* Start with 2000 a.d. */ + result -= 730485UL; + + /* Make month an array index */ + idx = t->month - 1; + + /* Loop thru each month, adding the days */ + for (i = 0; i < idx; i++) { + result += DaysInMonth[i]; + } + + /* Leap year? adjust February */ + if (year%400 == 0 || (year%4 == 0 && year%100 !=0)) { + ; + } else { + if (t->month > 1) { + result--; + } + } + + /* Add remaining days */ + result += t->mday; + + /* Convert to seconds, add all the other stuff */ + result = (result-1) * 86400L + (uint32_t)t->hour * 3600 + + (uint32_t)t->min * 60 + t->sec; + + return result; +} + +/******************************************************************************* +* Function Name : rtc_gettime +* Description : populates structure from HW-RTC, takes DST into account +* Input : None +* Output : time-struct gets modified +* Return : always true/not used +*******************************************************************************/ +bool rtc_gettime (RTC_t *rtc) +{ + uint32_t t; + + while ( ( t = RTC_GetCounter() ) != RTC_GetCounter() ) { ; } + counter_to_struct( t, rtc ); // get non DST time + adjustDST( rtc ); + + return true; +} + +/******************************************************************************* +* Function Name : my_RTC_SetCounter +* Description : sets the hardware-counter +* Input : new counter-value +* Output : None +* Return : None +*******************************************************************************/ +static void my_RTC_SetCounter(uint32_t cnt) +{ + /* Wait until last write operation on RTC registers has finished */ + RTC_WaitForLastTask(); + /* Change the current time */ + RTC_SetCounter(cnt); + /* Wait until last write operation on RTC registers has finished */ + RTC_WaitForLastTask(); +} + +/******************************************************************************* +* Function Name : rtc_settime +* Description : sets HW-RTC with values from time-struct, takes DST into +* account, HW-RTC always running in non-DST time +* Input : None +* Output : None +* Return : not used +*******************************************************************************/ +bool rtc_settime (const RTC_t *rtc) +{ + uint32_t cnt; + RTC_t ts; + + cnt = struct_to_counter( rtc ); // non-DST counter-value + counter_to_struct( cnt, &ts ); // normalize struct (for weekday) + if ( isDST( &ts ) ) { + cnt -= 60*60; // Subtract one hour + } + PWR_BackupAccessCmd(ENABLE); + my_RTC_SetCounter( cnt ); + PWR_BackupAccessCmd(DISABLE); + + return true; +} + +/******************************************************************************* +* Function Name : rtc_init +* Description : initializes HW RTC, +* sets default time-stamp if RTC has not been initialized before +* Input : None +* Output : None +* Return : not used +* see STM RTC example in the StdPeriph-Library package +*******************************************************************************/ +int rtc_init(void) //not use back_vcc +{ + +} + + + diff --git a/src/x9d/rtc.h b/src/x9d/rtc.h new file mode 100644 index 000000000..a8f064ae8 --- /dev/null +++ b/src/x9d/rtc.h @@ -0,0 +1,30 @@ +#ifndef RTC_H_ +#define RTC_H_ + +#include +//#include "interger.h" +//#include +#include "stm32f2xx.h" +#ifndef false +#define false FALSE +#endif +#ifndef true +#define true TRUE +#endif + +typedef struct { + uint16_t year; /* 1..4095 */ + uint8_t month; /* 1..12 */ + uint8_t mday; /* 1..31 */ + uint8_t wday; /* 0..6, Sunday = 0*/ + uint8_t hour; /* 0..23 */ + uint8_t min; /* 0..59 */ + uint8_t sec; /* 0..59 */ + uint8_t dst; /* 0 Winter, !=0 Summer */ +} RTC_t; + +int rtc_init(void); +bool rtc_gettime (RTC_t*); /* Get time */ +bool rtc_settime (const RTC_t*); /* Set time */ + +#endif diff --git a/src/x9d/spi.c b/src/x9d/spi.c new file mode 100644 index 000000000..0f76b6195 --- /dev/null +++ b/src/x9d/spi.c @@ -0,0 +1,128 @@ +/** + ****************************************************************************** + * @file Project/spi/spi.c + * @author X9D Application Team + * @Hardware version V0.2 + * @date 11-July-2012 + * @brief This file provides spi Init(Analog spi),read and write. + driver for LCD. + * * + ****************************************************************************** +*/ +#include "spi.h" +#include "hal.h" +/** +**********send command to lcd************** +*/ +//hardware spi +/*u16 spiCmd(u8 addr) +{ + u8 readValue; + + SPI_RS_LOW(); + SPI_NCS_LOW(); + + SPI_WRITE_BYTE(addr); + SPI_WAIT_DONE(); + + readValue=SPI_READ_BYTE(); + SPI_NCS_HIGH(); + return readValue; +}*/ + +//Anolog spi +void AspiCmd(u8 Command_Byte) +{ + int i=8; + LCD_A0_LOW(); + + LCD_CLK_HIGH(); + LCD_NCS_LOW(); + + while (i--) + { + LCD_CLK_LOW(); + if(Command_Byte&0x80) + { + LCD_MOSI_HIGH(); + } + else LCD_MOSI_LOW(); + + Command_Byte=Command_Byte<<1; + LCD_CLK_HIGH(); + } + LCD_NCS_HIGH(); + LCD_A0_HIGH(); +} + +/** + +********send data to lcd************** + +*/ + +//hardware spi +/* +u16 spiData(u8 addr) +{ + u16 readValue; + OLED_RS_HIGH(); + SPI_NCS_LOW(); + + SPI_WRITE_BYTE(addr); + SPI_WAIT_DONE(); + + readValue=SPI_READ_BYTE(); + SPI_NCS_HIGH(); + return readValue; +} +*/ + +//Anolog spi +void AspiData(u8 Para_data) +{ + int i=8; + LCD_CLK_HIGH(); + LCD_A0_HIGH(); + LCD_NCS_LOW(); + while (i--) + { + if(Para_data&0x80) + { + LCD_MOSI_HIGH(); + }else LCD_MOSI_LOW(); + Para_data<<=1; + LCD_CLK_LOW(); + __no_operation(); + LCD_CLK_HIGH(); + __no_operation(); + } + LCD_NCS_HIGH(); + LCD_A0_HIGH(); +} + +/*** +**********read one byte in a register******* +*/ + +/* +u16 spiRegAccess(u8 addrByte, u8 writeValue) +{ + u8 readValue; + + SPI_NCS_LOW(); + + SPI_WRITE_BYTE(addrByte); + SPI_WAIT_DONE(); + + SPI_WRITE_BYTE(writeValue); + SPI_WAIT_DONE(); + + readValue=SPI_READ_BYTE(); + SPI_NCS_HIGH(); + return readValue; +} + +*/ + + diff --git a/src/x9d/spi.h b/src/x9d/spi.h new file mode 100644 index 000000000..7ddce36e5 --- /dev/null +++ b/src/x9d/spi.h @@ -0,0 +1,36 @@ +/** + ****************************************************************************** + * @file Project/spi/spi.h + * @author X9D Application Team + * @Hardware version V0.2 + * @date 11-July-2012 + * @brief spi.c' Header file. + * * + ****************************************************************************** +*/ +#ifndef _SPI_H_ +#define _SPI_H_ + +#include "stm32f2xx.h" + +#define LCD_NCS_HIGH() do{GPIO_SetBits(GPIO_LCD, PIN_LCD_NCS);}while(0) +#define LCD_NCS_LOW() do{GPIO_ResetBits(GPIO_LCD, PIN_LCD_NCS);}while(0) + +#define LCD_A0_HIGH() do{GPIO_SetBits(GPIO_LCD, PIN_LCD_A0);}while(0) +#define LCD_A0_LOW() do{GPIO_ResetBits(GPIO_LCD, PIN_LCD_A0);}while(0) + +#define LCD_RST_HIGH() do{GPIO_SetBits(GPIO_LCD, PIN_LCD_RST);}while(0) +#define LCD_RST_LOW() do{GPIO_ResetBits(GPIO_LCD, PIN_LCD_RST);}while(0) + +#define LCD_CLK_HIGH() do{GPIO_SetBits(GPIO_LCD, PIN_LCD_CLK);}while(0) +#define LCD_CLK_LOW() do{GPIO_ResetBits(GPIO_LCD, PIN_LCD_CLK);}while(0) + +#define LCD_MOSI_HIGH() do{GPIO_SetBits(GPIO_LCD, PIN_LCD_MOSI);}while(0) +#define LCD_MOSI_LOW() do{GPIO_ResetBits(GPIO_LCD, PIN_LCD_MOSI);}while(0) + +void AspiCmd(u8 Command_Byte); +void AspiData(u8 Para_data); +//u16 spiRegAccess(u8 addrByte, u8 writeValue); + +#endif + diff --git a/src/x9d/stm32f2xx.h b/src/x9d/stm32f2xx.h new file mode 100644 index 000000000..e0470a703 --- /dev/null +++ b/src/x9d/stm32f2xx.h @@ -0,0 +1,6964 @@ +/** + ****************************************************************************** + * @file stm32f2xx.h + * @author MCD Application Team + * @version V1.1.3 + * @date 05-March-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F2xx devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripheral抯 drivers in application code(i.e. + * code will be based on direct access to peripheral抯 registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral抯 registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx + * @{ + */ + +#ifndef __STM32F2xx_H +#define __STM32F2xx_H +//#include "stm32f2xx_conf.h" +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F2XX) + #define STM32F2XX +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (STM32F2XX) + #error "Please select first the target STM32F2XX device used in your application (in stm32f2xx.h file)" +#endif + +#if !defined (USE_STDPERIPH_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif /* USE_STDPERIPH_DRIVER */ + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)12000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ +#endif /* HSE_STARTUP_TIMEOUT */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief STM32F2XX Standard Peripherals Library version number V1.1.3 + */ +#define __STM32F2XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F2XX_STDPERIPH_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __STM32F2XX_STDPERIPH_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ +#define __STM32F2XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F2XX_STDPERIPH_VERSION ((__STM32F2XX_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F2XX_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F2XX_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F2XX_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */ +#define __MPU_PRESENT 1 /*!< STM32F2XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F2XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @brief STM32F2XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80 /*!< Hash and Rng global interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +#include "system_stm32f2xx.h" +#include + +/** @addtogroup Exported_types + * @{ + */ +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + __IO uint32_t RESERVED8; + __IO uint32_t PTPTSSR; /* added for STM32F2xx */ + uint32_t RESERVED9[565]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + __IO uint32_t DMARSWTR; /* added for STM32F2xx */ + uint32_t RESERVED10[8]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */ +} FLASH_TypeDef; + +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FSMC_Bank1E_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FSMC_Bank2_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FSMC_Bank3_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ + __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ + __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ + __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ + __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ +} FSMC_Bank4_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ + __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + uint32_t RESERVED3; /*!< Reserved, 0x38 */ + uint32_t RESERVED4; /*!< Reserved, 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + uint32_t RESERVED5; /*!< Reserved, 0x44 */ + uint32_t RESERVED6; /*!< Reserved, 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + uint16_t RESERVED11; /*!< Reserved, 0x46 */ + __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + uint16_t RESERVED12; /*!< Reserved, 0x4A */ + __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint16_t RESERVED13; /*!< Reserved, 0x4E */ + __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ + uint16_t RESERVED14; /*!< Reserved, 0x52 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief Crypto Processor + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ + __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ + __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ + __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ + __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ + __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ + __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ + __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ + __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ + __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ + __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ + __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ + __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ + __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ + __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ + __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ + __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ + __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ +} CRYP_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[51]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1C0 */ +} HASH_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ + +#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300) +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) + +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) +#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) +#define BKPSRAM_BASE (AHB1PERIPH_BASE + 0x4000) +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +/*!< AHB2 peripherals */ +#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) +#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) +#define HASH_BASE (AHB2PERIPH_BASE + 0x60400) +#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) + +/*!< FSMC Bankx registers base address */ +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) +#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE ((uint32_t )0xE0042000) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define CRYP ((CRYP_TypeDef *) CRYP_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) +#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) +#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint8_t)0x01) /*!*/ + +#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!
© COPYRIGHT 2012 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "Macro_define.h" + +/** @addtogroup Template_Project + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +//void SVC_Handler(void) +//{ +//} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +//void PendSV_Handler(void) +//{ +//} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +//void SysTick_Handler(void) +//{ + +//} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +#ifdef AUDIO_TEST +#include "Audio.h" +void SPI3_IRQHandler(void) +{ + + +} +#endif +//all the available peripheral interrupt handler's name are followed +/* + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto + DCD HASH_RNG_IRQHandler ; Hash and Rng +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/stm32f2xx_it.h b/src/x9d/stm32f2xx_it.h new file mode 100644 index 000000000..ab94b737a --- /dev/null +++ b/src/x9d/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file Project/STM32F2xx_StdPeriph_Template/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/timer_init.c b/src/x9d/timer_init.c new file mode 100644 index 000000000..65c164c9a --- /dev/null +++ b/src/x9d/timer_init.c @@ -0,0 +1,256 @@ +#include "stm32f2xx.h" +#include "timer_init.h" +#include "hal.h" +#include "msg_que.h" +//Hardware Init Of Timer + +//TIM10_CH1 LCD backlight +//PWM OUTPUT MODE 500HZ,400HZ闪动。修改TIM10-> CCR1（1-4000）改变占空比，正比。 +void TIM10_CH1_BL_Init() +{ + uint16_t PrescalerValue = 0; + + TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; + TIM_OCInitTypeDef TIM_OCInitStructure; + + GPIO_InitTypeDef GPIO_InitStructure; + /* TIM10 clock enable ,GPIOBL clock enable */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM10, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOBL, ENABLE); + + /* GPIOC Configuration: TIM10_CH1 (PB.08)*/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_BL; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; + GPIO_Init(GPIOBL, &GPIO_InitStructure); + /* Connect TIM10 pins to AF3 */ + GPIO_PinAFConfig(GPIOBL, GPIO_PinSource_BL, GPIO_AF_TIM10); + + /* + APB2 = 120M,分频系数6，TIM10计数频率2M。TIM10频率为2M/4000=500HZ. + so the TIM10 Channel 1 generates a PWM signal with a frequency equal to + 500Hz and a duty cycle = (TIM10_CCR1/ TIM10_ARR + 1)* 100 = 50% + */ + + /* Compute the prescaler value */ + PrescalerValue = (uint16_t) ((SystemCoreClock ) / 2000000) - 1; + /* Time base configuration */ + TIM_TimeBaseStructure.TIM_Period = 3999; //ARR=19999 + TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + + TIM_TimeBaseInit(TIM10, &TIM_TimeBaseStructure); + + /* PWM1 Mode configuration: Channel1 */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse =2000; //TIM10-> CCR1 + TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; + + TIM_OC1Init(TIM10, &TIM_OCInitStructure); + TIM_OC1PreloadConfig(TIM10, TIM_OCPreload_Enable); + + /* TIM10 enable counter */ + TIM_Cmd(TIM10, ENABLE); +} + +void TIM10_CH1_BL_Adjust(char mode) +{ + switch(mode) + { + case BKL_DEC: + TIM10->CCR1 += 250; + if(TIM10->CCR1>4000) + TIM10->CCR1 = 4000; + break; + case BKL_INC: + if(TIM10->CCR1 < 250) + TIM10->CCR1 = 0; + else + TIM10->CCR1 -= 250; + break; + case BKL_OFF: TIM_Cmd(TIM10, DISABLE);break; + case BKL_ON: TIM_Cmd(TIM10, ENABLE);break; + + default:break; + } +} + +//TIM1_CH1:CPPM_OUTPUT +void TIM1_CH1_CPPM_Init() +{ +} + + +static struct TimerStruct timer_struct[MAX_TIMER]; +char led_lights; + +/******************************************* + 初始化应用层定时器 +*******************************************/ +static void initTimerStruct(void) +{ + char i; + for(i=0;ivalid){ + p->expires--; + if(p->expires==0) + { + p->valid=0; + //raiseEvent(p->event); + postMessage(p->pMsg->hWnd, p->pMsg->iMsg, p->pMsg->wParam, p->pMsg->lParam); + } + } + p++; + } + } +} + + + +/**************************************** +* 设置定时器 +****************************************/ +void setTimer(char timerID,char expires,PMSG pMsg) +{ + struct TimerStruct *p=&timer_struct[timerID]; + p->expires=expires; + p->pMsg =pMsg; + p->valid=1; +} +/**************************************** +* 取消定时器 +****************************************/ +void cancelTimer(char timerID) +{ + timer_struct[timerID].valid=0; +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/************************************************************************** +***************************************************************************** +******************************************************************************/ + +static struct TimerStruct timer_struct[MAX_TIMER]; + +/******************************************* + 初始化应用层定时器 +*******************************************/ +static void initTimerStruct(void) +{ + char i; + for(i=0;ivalid){ + p->expires--; + if(p->expires==0) + { + p->valid=0; + //raiseEvent(p->event); + postMessage(p->pMsg->hWnd, p->pMsg->iMsg, p->pMsg->wParam, p->pMsg->lParam); + } + } + p++; + } + } +} + + + +/**************************************** +* 设置定时器 +****************************************/ +void setTimer(char timerID,char expires,PMSG pMsg) +{ + struct TimerStruct *p=&timer_struct[timerID]; + p->expires=expires; + p->pMsg =pMsg; + p->valid=1; +} +/**************************************** +* 取消定时器 +****************************************/ +void cancelTimer(char timerID) +{ + timer_struct[timerID].valid=0; +} + +/**************************************************************************** +****************************************************************************/ \ No newline at end of file diff --git a/src/x9d/timer_init.h b/src/x9d/timer_init.h new file mode 100644 index 000000000..105f2ec59 --- /dev/null +++ b/src/x9d/timer_init.h @@ -0,0 +1,34 @@ +#ifndef _TIMER_INIT_H_ +#define _TIMER_INIT_H_ + +#include "frgui.h" + +#define MAX_TIMER (5) //最大的timerID + +#define TIMER_1 (0) +#define TIMER_2 (1) +#define TIMER_3 (2) +#define TIMER_4 (3) +#define TIMER_5 (4) + +struct TimerStruct +{ + char valid; + char expires; + PMSG pMsg; +}; + +void initTimer(void); +void setTimer(char timerID,char expires,PMSG pMsg); +void cancelTimer(char timerID); +void timer_interrupt(void); +void timer_tick(void); +void TIM10_CH1_BL_Init(); + +#define BKL_DEC (0) +#define BKL_INC (1) +#define BKL_OFF (2) +#define BKL_ON (3) + + +#endif